diff options
| -rw-r--r-- | arch/riscv/dts/Makefile | 1 | ||||
| -rw-r--r-- | arch/riscv/dts/xilinx-binman.dts | 12 | ||||
| -rw-r--r-- | arch/riscv/dts/xilinx-mbv32.dts | 2 | ||||
| -rw-r--r-- | arch/riscv/dts/xilinx-mbv64.dts | 2 | ||||
| -rw-r--r-- | configs/xilinx_mbv32_defconfig | 1 | ||||
| -rw-r--r-- | configs/xilinx_mbv32_smode_defconfig | 1 | ||||
| -rw-r--r-- | configs/xilinx_mbv64_defconfig | 1 | ||||
| -rw-r--r-- | configs/xilinx_mbv64_smode_defconfig | 1 |
8 files changed, 17 insertions, 4 deletions
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 2b10c2d6c01..68dfe9ce56d 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb +dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/riscv/dts/xilinx-binman.dts b/arch/riscv/dts/xilinx-binman.dts new file mode 100644 index 00000000000..715080ed763 --- /dev/null +++ b/arch/riscv/dts/xilinx-binman.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * binman file for AMD MicroBlaze V + * + * (C) Copyright 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <[email protected]> + */ + +/dts-v1/; + +#include "binman.dtsi" diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index b426510f343..f7a3e076fd5 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -9,8 +9,6 @@ /dts-v1/; -#include "binman.dtsi" - / { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts index 3762def29f9..e6235ed2f52 100644 --- a/arch/riscv/dts/xilinx-mbv64.dts +++ b/arch/riscv/dts/xilinx-mbv64.dts @@ -9,8 +9,6 @@ /dts-v1/; -#include "binman.dtsi" - / { #address-cells = <2>; #size-cells = <2>; diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index a6268dd1dde..e3341179a68 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -41,5 +41,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index 2073bc71092..c95b4497395 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -45,5 +45,6 @@ CONFIG_XILINX_UARTLITE=y # CONFIG_RISCV_TIMER is not set CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig index 3bedec95b77..a3cc1a5669e 100644 --- a/configs/xilinx_mbv64_defconfig +++ b/configs/xilinx_mbv64_defconfig @@ -42,5 +42,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig index e45e4e638bb..3d49670c60c 100644 --- a/configs/xilinx_mbv64_smode_defconfig +++ b/configs/xilinx_mbv64_smode_defconfig @@ -46,5 +46,6 @@ CONFIG_XILINX_UARTLITE=y # CONFIG_RISCV_TIMER is not set CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y |