diff options
| -rw-r--r-- | configs/j784s4_evm_a72_defconfig | 2 | ||||
| -rw-r--r-- | drivers/pci_endpoint/pcie_cdns_ti_ep.c | 33 |
2 files changed, 33 insertions, 2 deletions
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 67aa18a16da..fc7acbae694 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -125,6 +125,8 @@ CONFIG_MUX_MMIO=y CONFIG_PHY_TI_DP83867=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCIE_CDNS_TI_EP=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_PHY_CADENCE_TORRENT=y diff --git a/drivers/pci_endpoint/pcie_cdns_ti_ep.c b/drivers/pci_endpoint/pcie_cdns_ti_ep.c index 661b6ba5b55..021bd73a383 100644 --- a/drivers/pci_endpoint/pcie_cdns_ti_ep.c +++ b/drivers/pci_endpoint/pcie_cdns_ti_ep.c @@ -20,6 +20,7 @@ #include <regmap.h> #include <syscon.h> #include <pci_ep.h> +#include <linux/delay.h> #include "pcie-cadence.h" @@ -90,15 +91,26 @@ static int pcie_cdns_reset(struct udevice *dev, struct power_domain *pci_pwrdmn) dev_err(dev, "failed to power on: %d\n", ret); return ret; } - + mdelay(1); return 0; } static int pcie_cdns_config_serdes(struct udevice *dev) { + int ret; + + if (CONFIG_IS_ENABLED(MUX_MMIO)) { + struct udevice *mux; + + ret = uclass_get_device_by_seq(UCLASS_MUX, 0, &mux); + if (ret) { + dev_err(dev, "unable to get mux\n"); + return ret; + } + } + if (CONFIG_IS_ENABLED(PHY_CADENCE_TORRENT)) { struct phy serdes; - int ret = 7; ret = generic_phy_get_by_name(dev, "pcie-phy", &serdes); if (ret != 0 && ret != -EBUSY) { @@ -263,9 +275,11 @@ static int pcie_cdns_ti_ep_probe(struct udevice *dev) struct pcie_cdns_ti_ep *pcie = dev_get_priv(dev); struct pcie_cdns_ti_ep_data *data; struct power_domain pci_pwrdmn; + struct cdns_pcie pcie_dev; struct clk *clk; int ret; + pcie_dev.reg_base = pcie->reg_base; pcie->dev = dev; data = (struct pcie_cdns_ti_ep_data *)dev_get_driver_data(dev); if (!data) @@ -316,6 +330,13 @@ static int pcie_cdns_ti_ep_probe(struct udevice *dev) return ret; } + /* + * Disable all the functions except function 0 (anyway BIT(0) is + * hardwired to 1). This is required to avoid RC from enumerating + * those functions which are not even configured. + */ + cdns_pcie_writel(&pcie_dev, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0)); + return 0; } @@ -377,11 +398,19 @@ static const struct pcie_cdns_ti_ep_data am64_pcie_ep_data = { .max_lanes = 1, }; +static const struct pcie_cdns_ti_ep_data j784s4_pcie_ep_data = { + .max_lanes = 4, +}; + static const struct udevice_id pcie_cdns_ti_ep_ids[] = { { .compatible = "ti,am64-pcie-ep", .data = (ulong)&am64_pcie_ep_data, }, + { + .compatible = "ti,j784s4-pcie-ep", + .data = (ulong)&j784s4_pcie_ep_data, + }, {}, }; |