diff options
| -rw-r--r-- | arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/dts/r8a78000-u-boot.dtsi | 8 | ||||
| -rw-r--r-- | board/renesas/common/gen5-cm33.c | 70 | ||||
| -rw-r--r-- | drivers/remoteproc/renesas_rsip.c | 45 | ||||
| -rw-r--r-- | include/dt-bindings/reset/r8a78000-reset-scmi.h | 2 |
5 files changed, 56 insertions, 70 deletions
diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi index 872cbfdbad6..5a76d9740a0 100644 --- a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi @@ -90,6 +90,7 @@ scp@c1340000 { compatible = "renesas,r8a78000-rproc"; reg = <0 0xc1340000 0 0x80000>; + resets = <&mdlc_scp SCP_RESET_DOMAIN_ID_SCP>; }; ram@e9800000 { /* DBSC5 */ diff --git a/arch/arm/dts/r8a78000-u-boot.dtsi b/arch/arm/dts/r8a78000-u-boot.dtsi index df21a9e03a2..67da58f6474 100644 --- a/arch/arm/dts/r8a78000-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-u-boot.dtsi @@ -170,6 +170,14 @@ bootph-all; }; + mdlc_scp: system-controller@c1330000 { + compatible = "renesas,r8a78000-mdlc"; + reg = <0 0xc1330000 0 0x1000>; + #power-domain-cells = <1>; + #reset-cells = <1>; + bootph-all; + }; + i2c0: i2c@c11d0000 { compatible = "renesas,i2c-r8a78000", "renesas,rcar-gen5-i2c"; diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c index b2f6087a943..f532daa16d5 100644 --- a/board/renesas/common/gen5-cm33.c +++ b/board/renesas/common/gen5-cm33.c @@ -535,12 +535,6 @@ static void clk_control_set_pll(void) #define MDLC_HSCN_BASE 0xc9c90000 /* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ #define MDLC_RT_BASE 0xb9440000 -#define MDLC_SCP_BASE 0xc1330000 - -#define MDLC_SCP_MSRES02 (MDLC_SCP_BASE + 0x908) -#define MDLC_SCP_MSRESS02 (MDLC_SCP_BASE + 0x968) -#define MDLC_SCP_MSRES02_SCP_MASK GENMASK(1, 0) -#define MDLC_SCP_PKCPROT1 (MDLC_SCP_BASE + 0xcf4) #define MDLC_PERW_MSRES05 (MDLC_PERW_BASE + 0x914) #define MDLC_PERW_MSRESS05 (MDLC_PERW_BASE + 0x974) @@ -669,32 +663,6 @@ static void mdlc_rmw_msres(const u32 prot, const u32 res, const u32 mask, const } /** - * mdlc_set_reset() - Set IP into reset - * @prot: Protect register - * @res: Reset register - * @stat: Reset register - * @mask: Mask in the register to clear - */ -static void mdlc_set_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) -{ - u32 status; - - mdlc_wait_for_reset(res, stat); - - status = field_get(mask, readl(stat)); - if (status == MDLC_MSRESS_STOP) { - mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_STANDBY); - mdlc_wait_for_reset(res, stat); - status = field_get(mask, readl(stat)); - } - - if (status == MDLC_MSRESS_STANDBY || status == MDLC_MSRESS_RUN) { - mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); - mdlc_wait_for_reset(res, stat); - } -} - -/** * mdlc_release_reset() - Release IP from reset * @prot: Protect register * @res: Reset register @@ -1260,41 +1228,6 @@ static void load_perm_tables(void) writel(0xffffffff, 0xe9a081fc); } -#define SCP_STCM_BASE 0xc1000000 -#define SCP_BASE 0xc1340000 -#define SCP_CFGVECTABLE (SCP_BASE + 0x0) -#define SCP_CFGNSSTCALIB (SCP_BASE + 0x10) -#define SCP_CPUWAIT (SCP_BASE + 0x30) -#define SCP_CFGNSSTCALIB_13_3MHZ 0x010040f0 -#define SCP_CPUWAIT_WAIT BIT(0) - -/** - * scp_initialize() - Initialize SCP - * - * Put SCP into reset, configure SCP entry point address and systick timer, - * release SCP from reset, and zero out SCP STCM regions. - */ -static void scp_initialize(void) -{ - u32 addr; - - mdlc_set_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, - MDLC_SCP_MSRES02_SCP_MASK); - - writel(SCP_STCM_BASE, SCP_CFGVECTABLE); - writel(SCP_CFGNSSTCALIB_13_3MHZ, SCP_CFGNSSTCALIB); - setbits_le32(SCP_CPUWAIT, SCP_CPUWAIT_WAIT); - - mdlc_release_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, - MDLC_SCP_MSRES02_SCP_MASK); - - /* Fill zero to SCP STCM regions 0 ... 27 */ - for (addr = SCP_STCM_BASE; addr < 0xc1061b00; addr += 8) - writeq(0, addr); - - asm volatile("dsb sy"); -} - #define GIC720AE_GICR_PWRR(cpu) \ (GICR_BASE + 0x24 + ((cpu) * 0x40000)) @@ -1362,9 +1295,6 @@ int mach_cpu_init(void) load_perm_tables(); gic720ae_init(); - /* Release SCP from reset */ - scp_initialize(); - return 0; } diff --git a/drivers/remoteproc/renesas_rsip.c b/drivers/remoteproc/renesas_rsip.c index cabcc2822bd..cbf999e88f2 100644 --- a/drivers/remoteproc/renesas_rsip.c +++ b/drivers/remoteproc/renesas_rsip.c @@ -13,6 +13,7 @@ #include <linux/sizes.h> #include <malloc.h> #include <remoteproc.h> +#include <reset.h> /* R-Car X5H contains 1 SCP core, 6 lockstep Cortex-R52 and 32 Cortex-A720AE cores. */ #define RCAR5_SCP_CORES 1 @@ -20,6 +21,9 @@ #define RCAR5_CA720_CORES 32 #define SCP_BASE 0xc1340000 +#define SCP_CFGVECTABLE (SCP_BASE + 0x0) +#define SCP_CFGNSSTCALIB (SCP_BASE + 0x10) +#define SCP_CFGNSSTCALIB_13_3MHZ 0x010040f0 #define SCP_CPUWAIT (SCP_BASE + 0x30) #define SCP_CPUWAIT_WAIT BIT(0) #define SCP_STCM 0xc1000000 @@ -248,6 +252,32 @@ static int renesas_rsip_rproc_is_running(struct udevice *dev) */ static int renesas_rsip_rproc_init(struct udevice *dev) { + struct renesas_rsip_rproc_privdata *priv = dev_get_priv(dev); + struct reset_ctl *rst = dev_get_priv(dev->parent); + u32 addr; + + if (priv->core_id != 0) /* No init for non-SCP cores */ + return 0; + + /* + * Put SCP into reset, configure SCP entry point address and systick + * timer, release SCP from reset, and zero out SCP STCM regions. + */ + + reset_assert(rst); + + writel(SCP_STCM, SCP_CFGVECTABLE); + writel(SCP_CFGNSSTCALIB_13_3MHZ, SCP_CFGNSSTCALIB); + setbits_le32(SCP_CPUWAIT, SCP_CPUWAIT_WAIT); + + reset_deassert(rst); + + /* Fill zero to SCP STCM regions 0 ... 27 */ + for (addr = SCP_STCM; addr < 0xc1061b00; addr += 8) + writeq(0, addr); + + asm volatile("dsb sy"); + return 0; } @@ -300,6 +330,19 @@ U_BOOT_DRIVER(renesas_rsip_core) = { }; /** + * renesas_rsip_rproc_probe() - Common rproc driver probe + * @dev: corresponding remote processor parent device + * + * Return: 0 if all went ok, else corresponding -ve error + */ +static int renesas_rsip_rproc_probe(struct udevice *parent) +{ + struct reset_ctl *rst = dev_get_priv(parent); + + return reset_get_by_index(parent, 0, rst); +} + +/** * renesas_rsip_rproc_bind() - Bind rproc driver to each core control * @dev: corresponding remote processor parent device * @@ -358,4 +401,6 @@ U_BOOT_DRIVER(renesas_rsip_rproc) = { .of_match = renesas_rsip_rproc_ids, .id = UCLASS_NOP, .bind = renesas_rsip_rproc_bind, + .probe = renesas_rsip_rproc_probe, + .priv_auto = sizeof(struct reset_ctl), }; diff --git a/include/dt-bindings/reset/r8a78000-reset-scmi.h b/include/dt-bindings/reset/r8a78000-reset-scmi.h index 3d84bfb073a..bf8c1b710f0 100644 --- a/include/dt-bindings/reset/r8a78000-reset-scmi.h +++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h @@ -24,4 +24,6 @@ #define SCP_RESET_DOMAIN_ID_MPPHY31 0x67 #define SCP_RESET_DOMAIN_ID_MPPHY02 0x68 +#define SCP_RESET_DOMAIN_ID_SCP 0x20 + #endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */ |