diff options
| -rw-r--r-- | arch/arm/dts/zynqmp-clk-ccf.dtsi | 15 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp.dtsi | 1 |
2 files changed, 14 insertions, 2 deletions
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 482f432ba7f..877962df2b3 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -3,7 +3,7 @@ * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -49,6 +49,14 @@ clock-frequency = <27000000>; clock-output-names = "aux_ref_clk"; }; + + rtc_clk: rtc-clk { + bootph-all; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; + }; }; &zynqmp_firmware { @@ -302,3 +310,8 @@ <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; + +&rtc { + clocks = <&rtc_clk>; + clock-names = "rtc"; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 13cfca66657..c225eb219f4 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1006,7 +1006,6 @@ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "alarm", "sec"; - calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { |