diff options
Diffstat (limited to 'Documentation/devicetree/bindings/misc')
5 files changed, 0 insertions, 98 deletions
diff --git a/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt b/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt deleted file mode 100644 index 64a9b5b154b..00000000000 --- a/Documentation/devicetree/bindings/misc/fsl,mpc83xx-serdes.txt +++ /dev/null @@ -1,24 +0,0 @@ -MPC83xx SerDes controller devices - -MPC83xx SoCs contain a built-in SerDes controller that determines which -protocols (SATA, PCI Express, SGMII, ...) are used on the system's serdes lines -and how the lines are configured. - -Required properties: -- compatible: must be "fsl,mpc83xx-serdes" -- reg: must point to the serdes controller's register map -- proto: selects for which protocol the serdes lines are configured. One of - "sata", "pex", "pex-x2", "sgmii" -- serdes-clk: determines the frequency the serdes lines are configured for. One - of 100, 125, 150. -- vdd: determines whether 1.0V core VDD is used or not - -Example: - -SERDES: serdes@e3000 { - reg = <0xe3000 0x200>; - compatible = "fsl,mpc83xx-serdes"; - proto = "pex"; - serdes-clk = <100>; - vdd; -}; diff --git a/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt b/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt deleted file mode 100644 index db2ff8ca128..00000000000 --- a/Documentation/devicetree/bindings/misc/gdsys,io-endpoint.txt +++ /dev/null @@ -1,20 +0,0 @@ -gdsys IO endpoint of IHS FPGA devices - -The IO endpoint of IHS FPGA devices is a packet-based transmission interface -that allows interconnected gdsys devices to send and receive data over the -FPGA's main ethernet connection. - -Required properties: -- compatible: must be "gdsys,io-endpoint" -- reg: describes the address and length of the endpoint's register map (within - the FPGA's register space) - -Example: - -fpga0_ep0 { - compatible = "gdsys,io-endpoint"; - reg = <0x020 0x10 - 0x320 0x10 - 0x340 0x10 - 0x360 0x10>; -}; diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt b/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt deleted file mode 100644 index acd466fdc6d..00000000000 --- a/Documentation/devicetree/bindings/misc/gdsys,iocon_fpga.txt +++ /dev/null @@ -1,19 +0,0 @@ -gdsys IHS FPGA for CON devices - -The gdsys IHS FPGA is the main FPGA on gdsys CON devices. This driver provides -support for enabling and starting the FPGA, as well as verifying working bus -communication. - -Required properties: -- compatible: must be "gdsys,iocon_fpga" -- reset-gpios: List of GPIOs controlling the FPGA's reset -- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is - done - -Example: - -FPGA0 { - compatible = "gdsys,iocon_fpga"; - reset-gpios = <&PPCPCA 26 0>; - done-gpios = <&GPIO_VB0 19 0>; -}; diff --git a/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt b/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt deleted file mode 100644 index 819db22bf7d..00000000000 --- a/Documentation/devicetree/bindings/misc/gdsys,iocpu_fpga.txt +++ /dev/null @@ -1,19 +0,0 @@ -gdsys IHS FPGA for CPU devices - -The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides -support for enabling and starting the FPGA, as well as verifying working bus -communication. - -Required properties: -- compatible: must be "gdsys,iocpu_fpga" -- reset-gpios: List of GPIOs controlling the FPGA's reset -- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is - done - -Example: - -FPGA0 { - compatible = "gdsys,iocpu_fpga"; - reset-gpios = <&PPCPCA 26 0>; - done-gpios = <&GPIO_VB0 19 0>; -}; diff --git a/Documentation/devicetree/bindings/misc/gdsys,soc.txt b/Documentation/devicetree/bindings/misc/gdsys,soc.txt deleted file mode 100644 index 278e935b166..00000000000 --- a/Documentation/devicetree/bindings/misc/gdsys,soc.txt +++ /dev/null @@ -1,16 +0,0 @@ -gdsys soc bus driver - -This driver provides a simple interface for the busses associated with gdsys -IHS FPGAs. The bus itself contains devices whose register maps are contained -within the FPGA's register space. - -Required properties: -- fpga: A phandle to the controlling IHS FPGA - -Example: - -FPGA0BUS: fpga0bus { - compatible = "gdsys,soc"; - ranges = <0x0 0xe0600000 0x00004000>; - fpga = <&FPGA0>; -}; |
