diff options
Diffstat (limited to 'arch')
187 files changed, 19544 insertions, 15869 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f624675eadf..514bf2000b4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1082,6 +1082,7 @@ config ARCH_APPLE imply CMD_GPT imply BOOTSTD_FULL imply OF_HAS_PRIOR_STAGE + imply OF_UPSTREAM config ARCH_OWL bool "Actions Semi OWL SoCs" diff --git a/arch/arm/config.mk b/arch/arm/config.mk index a7eff84a267..bce9a31e966 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -112,6 +112,14 @@ endif # needed for relocation LDFLAGS_u-boot += -pie +ifeq ($(CONFIG_ARM64),y) +# U-Boot uses fixed 4K granules, so we force the linker to match. +# Otherwise, we're subject to toolchain preferences, (e.g Fedora's +# aarch64-linux-none toolchain selects 64K granules) and we end up wasting +# a lot of space in ELFs with MMU_PGPROT enabled. +LDFLAGS_u-boot += -z common-page-size=0x1000 -z max-page-size=0x1000 +endif + # # FIXME: binutils versions < 2.22 have a bug in the assembler where # branches to weak symbols can be incorrectly optimized in thumb mode diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 39479df7b21..7c0e3f6d055 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -810,8 +810,10 @@ __weak void mmu_setup(void) el = current_el(); set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL), MEMORY_ATTRIBUTES); +} - /* enable the mmu */ +void mmu_enable(void) +{ set_sctlr(get_sctlr() | CR_M); } @@ -881,6 +883,7 @@ void dcache_enable(void) if (!mmu_status()) { __asm_invalidate_tlb_all(); mmu_setup(); + mmu_enable(); } /* Set up page tables only once (it is done also by mmu_setup()) */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cfbaa475701..a047494b1fd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1143,7 +1143,7 @@ int arch_early_init_r(void) #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif -#ifdef CONFIG_SYS_FSL_HAS_RGMII +#if defined(CONFIG_SYS_FSL_HAS_RGMII) && defined(CONFIG_FSL_MC_ENET) /* some dpmacs in armv8a based freescale layerscape SOCs can be * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via * EC*_PMUX(rgmii) bits in RCW. @@ -1158,6 +1158,10 @@ int arch_early_init_r(void) * function of SOC, the dpmac will be enabled as RGMII even if it was * also enabled before as SGMII. If ECx_PMUX is not configured for * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init(). + * + * fsl_rgmii_init() itself is only built under CONFIG_FSL_MC_ENET + * (drivers/net/ldpaa_eth/); gate the call the same way so builds + * without MC-ENET still link. */ fsl_rgmii_init(); #endif @@ -1549,7 +1553,8 @@ void lmb_arch_add_memory(void) gd->arch.resv_ram < ram_start + ram_size) ram_size = gd->arch.resv_ram - ram_start; #endif - lmb_add(ram_start, ram_size); + if (ram_size > 0) + lmb_add(ram_start, ram_size); } } #endif diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 87de09979b1..f834d770dd6 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -129,3 +129,18 @@ void __noreturn psci_system_off(void) while (1) ; } + +int psci_features(u32 psci_func_id) +{ + struct pt_regs regs; + + regs.regs[0] = ARM_PSCI_1_0_FN_PSCI_FEATURES; + regs.regs[1] = psci_func_id; + + if (use_smc_for_psci) + smc_call(®s); + else + hvc_call(®s); + + return regs.regs[0]; +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4085d4c2de1..2b65cd9105c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -32,13 +32,6 @@ dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb -dtb-$(CONFIG_ARCH_APPLE) += \ - t8103-j274.dtb \ - t8103-j293.dtb \ - t8103-j313.dtb \ - t8103-j456.dtb \ - t8103-j457.dtb - dtb-$(CONFIG_ARCH_DAVINCI) += \ da850-lcdk.dtb \ da850-lego-ev3.dtb @@ -52,12 +45,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_RK3128) += \ - rk3128-evb.dtb - -dtb-$(CONFIG_ROCKCHIP_RK322X) += \ - rk3229-evb.dtb - dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ @@ -906,12 +893,11 @@ dtb-$(CONFIG_RZA1) += \ r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb -dtb-$(CONFIG_RCAR_GEN5) += \ - r8a78000-ironhide.dtb +dtb-$(CONFIG_RCAR_GEN3) += \ + r8a779md-geist.dtb -ifdef CONFIG_RCAR_GEN5 -DTC_FLAGS += -R 4 -p 0x1000 -endif +dtb-$(CONFIG_RCAR_GEN5) += \ + r8a78000-ironhide-cm33.dtb dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb @@ -1079,8 +1065,7 @@ dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\ k3-j721s2-r5-common-proc-board.dtb -dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-aquila-dev.dtb \ - k3-am69-r5-aquila-dev.dtb \ +dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-aquila-dev.dtb \ k3-am69-r5-sk.dtb \ k3-j784s4-r5-evm.dtb @@ -1105,6 +1090,9 @@ dtb-$(CONFIG_SOC_K3_AM62D2) += k3-am62d2-r5-evm.dtb dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \ k3-am62p5-verdin-r5.dtb +mt8371-genio-520-evk-ufs-dtbs := mt8371-genio-520-evk.dtb mt8371-genio-common-ufs.dtbo +mt8391-genio-720-evk-ufs-dtbs := mt8391-genio-720-evk.dtb mt8371-genio-common-ufs.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ @@ -1125,7 +1113,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7988-sd-rfb.dtb \ mt8183-pumpkin.dtb \ mt8371-genio-520-evk.dtb \ + mt8371-genio-520-evk-ufs.dtb \ mt8391-genio-720-evk.dtb \ + mt8391-genio-720-evk-ufs.dtb \ mt8512-bm1-emmc.dtb \ mt8516-pumpkin.dtb \ mt8518-ap1-emmc.dtb diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi index 910d2a5c778..194ab344350 100644 --- a/arch/arm/dts/fsl-ls1012a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi @@ -17,7 +17,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -25,7 +25,7 @@ spi-max-frequency = <1000000>; /* input clock */ }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -33,7 +33,7 @@ reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 796d72fc9ed..b0f3fd79094 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -48,7 +48,7 @@ clocks = <&sysclk>; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -178,7 +178,7 @@ clocks = <&clockgen 4 0>; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 3b063d0257d..ac5b2d9dde9 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -26,29 +26,29 @@ bus-num = <0>; status = "okay"; - dflash0: sst25wf040b { + dflash0: sst25wf040b@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash1: en25s64 { + dflash1: en25s64@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash2: n25q128a { + dflash2: n25q128a@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -60,29 +60,29 @@ bus-num = <0>; status = "okay"; - dflash3: sst25wf040b { + dflash3: sst25wf040b@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash4: en25s64 { + dflash4: en25s64@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash5: n25q128a { + dflash5: n25q128a@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -94,10 +94,10 @@ bus-num = <0>; status = "okay"; - dflash8: en25s64 { + dflash8: en25s64@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 5e02cd91d75..fa1bda51108 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -21,7 +21,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -31,7 +31,7 @@ reg = <0>; }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -41,7 +41,7 @@ reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts index f5b3bb68b3d..80787907df6 100644 --- a/arch/arm/dts/fsl-ls1043a-rdb.dts +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -28,7 +28,7 @@ bus-num = <0>; status = "okay"; - dspiflash: n25q12a { + dspiflash: n25q12a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 21643a1d951..7337d3cecb6 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -54,7 +54,7 @@ clocks = <&sysclk>; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -67,7 +67,7 @@ status = "disabled"; }; - dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -306,7 +306,7 @@ clock-names = "ipg"; status = "disabled"; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index d66824975c5..706405ba805 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -21,7 +21,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -31,7 +31,7 @@ reg = <0>; }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -41,7 +41,7 @@ reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 44ee4c5808d..ceb5d6b3356 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -54,7 +54,7 @@ clocks = <&sysclk>; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -67,7 +67,7 @@ status = "disabled"; }; - dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -311,7 +311,7 @@ status = "disabled"; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/fsl-ls1088a-qds-21-x-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-qds-21-x-u-boot.dtsi new file mode 100644 index 00000000000..1d58f1c593b --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-21-x-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * + */ + +#include <config.h> + +#include "fsl-ls1088a-qds-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1088a-qds-29-x-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-qds-29-x-u-boot.dtsi new file mode 100644 index 00000000000..1d58f1c593b --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-29-x-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * + */ + +#include <config.h> + +#include "fsl-ls1088a-qds-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi index 4d21d4fbd5e..83635a2e40d 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi @@ -144,7 +144,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -152,7 +152,7 @@ spi-max-frequency = <1000000>; /* input clock */ }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -160,7 +160,7 @@ reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi index 4e6700d586e..0d64795bf44 100644 --- a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi @@ -18,11 +18,3 @@ ethernet9 = &dpmac1; }; }; - -&i2c0 { - uc: board-controller@7e { - compatible = "traverse,ten64-controller"; - reg = <0x7e>; - }; -}; - diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts b/arch/arm/dts/fsl-ls1088a-ten64.dts deleted file mode 100644 index 0d11440d88d..00000000000 --- a/arch/arm/dts/fsl-ls1088a-ten64.dts +++ /dev/null @@ -1,388 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Traverse Technologies Ten64 - * (LS1088A) board - * Based on fsl-ls1088a-rdb.dts - * Copyright 2017-2020 NXP - * Copyright 2019-2023 Traverse Technologies - * - * Author: Mathew McBride <[email protected]> - */ - -/dts-v1/; - -#include "fsl-ls1088a.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Traverse Ten64"; - compatible = "traverse,ten64", "fsl,ls1088a"; - - aliases { - serial0 = &duart0; - serial1 = &duart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - buttons { - compatible = "gpio-keys"; - - /* Fired by system controller when - * external power off (e.g ATX Power Button) - * asserted - */ - button-powerdn { - label = "External Power Down"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - }; - - /* Rear Panel 'ADMIN' button (GPIO_H) */ - button-admin { - label = "ADMIN button"; - gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - linux,code = <KEY_WPS_BUTTON>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "ten64:green:sfp1:down"; - gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "ten64:green:sfp2:up"; - gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - label = "ten64:admin"; - gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; - }; - }; - - sfp_xg0: dpmac2-sfp { - compatible = "sff,sfp"; - i2c-bus = <&sfplower_i2c>; - tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>; - los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <2000>; - }; - - sfp_xg1: dpmac1-sfp { - compatible = "sff,sfp"; - i2c-bus = <&sfpupper_i2c>; - tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>; - los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <2000>; - }; -}; - -/* XG1 - Upper SFP */ -&dpmac1 { - sfp = <&sfp_xg1>; - pcs-handle = <&pcs1>; - phy-connection-type = "10gbase-r"; - managed = "in-band-status"; -}; - -/* XG0 - Lower SFP */ -&dpmac2 { - sfp = <&sfp_xg0>; - pcs-handle = <&pcs2>; - phy-connection-type = "10gbase-r"; - managed = "in-band-status"; -}; - -/* DPMAC3..6 is GE4 to GE8 */ -&dpmac3 { - phy-handle = <&mdio1_phy5>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs3_0>; -}; - -&dpmac4 { - phy-handle = <&mdio1_phy6>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs3_1>; -}; - -&dpmac5 { - phy-handle = <&mdio1_phy7>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs3_2>; -}; - -&dpmac6 { - phy-handle = <&mdio1_phy8>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs3_3>; -}; - -/* DPMAC7..10 is GE0 to GE3 */ -&dpmac7 { - phy-handle = <&mdio1_phy1>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs7_0>; -}; - -&dpmac8 { - phy-handle = <&mdio1_phy2>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs7_1>; -}; - -&dpmac9 { - phy-handle = <&mdio1_phy3>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs7_2>; -}; - -&dpmac10 { - phy-handle = <&mdio1_phy4>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs7_3>; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&emdio1 { - status = "okay"; - - mdio1_phy5: ethernet-phy@c { - reg = <0xc>; - }; - - mdio1_phy6: ethernet-phy@d { - reg = <0xd>; - }; - - mdio1_phy7: ethernet-phy@e { - reg = <0xe>; - }; - - mdio1_phy8: ethernet-phy@f { - reg = <0xf>; - }; - - mdio1_phy1: ethernet-phy@1c { - reg = <0x1c>; - }; - - mdio1_phy2: ethernet-phy@1d { - reg = <0x1d>; - }; - - mdio1_phy3: ethernet-phy@1e { - reg = <0x1e>; - }; - - mdio1_phy4: ethernet-phy@1f { - reg = <0x1f>; - }; -}; - -&esdhc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - sfpgpio: gpio@76 { - compatible = "ti,tca9539"; - reg = <0x76>; - #gpio-cells = <2>; - gpio-controller; - - admin_led_lower { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-low; - }; - }; - - at97sc: tpm@29 { - compatible = "atmel,at97sc3204t"; - reg = <0x29>; - }; -}; - -&i2c2 { - status = "okay"; - - rx8035: rtc@32 { - compatible = "epson,rx8035"; - reg = <0x32>; - }; -}; - -&i2c3 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9540"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - sfpupper_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - sfplower_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&pcs_mdio1 { - status = "okay"; -}; - -&pcs_mdio2 { - status = "okay"; -}; - -&pcs_mdio3 { - status = "okay"; -}; - -&pcs_mdio7 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - en25s64: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0 0x100000>; - }; - - partition@100000 { - label = "bl3"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "mcfirmware"; - reg = <0x300000 0x200000>; - }; - - partition@500000 { - label = "ubootenv"; - reg = <0x500000 0x80000>; - }; - - partition@580000 { - label = "dpl"; - reg = <0x580000 0x40000>; - }; - - partition@5C0000 { - label = "dpc"; - reg = <0x5C0000 0x40000>; - }; - - partition@600000 { - label = "devicetree"; - reg = <0x600000 0x40000>; - }; - }; - }; - - nand: flash@1 { - compatible = "spi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* reserved for future boot direct from NAND flash - * (this would use the same layout as the 8MiB NOR flash) - */ - partition@0 { - label = "nand-boot-reserved"; - reg = <0 0x800000>; - }; - - /* recovery / install environment */ - partition@800000 { - label = "recovery"; - reg = <0x800000 0x2000000>; - }; - - /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */ - partition@2800000 { - label = "ubia"; - reg = <0x2800000 0x6C00000>; - }; - - /* ubib (second OpenWrt) */ - partition@9400000 { - label = "ubib"; - reg = <0x9400000 0x6C00000>; - }; - }; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi index efcfdd96aef..8ae45f6a638 100644 --- a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -55,9 +55,14 @@ &usb0 { compatible = "fsl,layerscape-dwc3", "snps,dwc3"; + status = "okay"; }; &usb1 { compatible = "fsl,layerscape-dwc3", "snps,dwc3"; + status = "okay"; }; +&esdhc { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index e5fb137ac02..9a62f148d8e 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -978,51 +978,61 @@ dpmac1: ethernet@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <1>; + status = "disabled"; }; dpmac2: ethernet@2 { compatible = "fsl,qoriq-mc-dpmac"; reg = <2>; + status = "disabled"; }; dpmac3: ethernet@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <3>; + status = "disabled"; }; dpmac4: ethernet@4 { compatible = "fsl,qoriq-mc-dpmac"; reg = <4>; + status = "disabled"; }; dpmac5: ethernet@5 { compatible = "fsl,qoriq-mc-dpmac"; reg = <5>; + status = "disabled"; }; dpmac6: ethernet@6 { compatible = "fsl,qoriq-mc-dpmac"; reg = <6>; + status = "disabled"; }; dpmac7: ethernet@7 { compatible = "fsl,qoriq-mc-dpmac"; reg = <7>; + status = "disabled"; }; dpmac8: ethernet@8 { compatible = "fsl,qoriq-mc-dpmac"; reg = <8>; + status = "disabled"; }; dpmac9: ethernet@9 { compatible = "fsl,qoriq-mc-dpmac"; reg = <9>; + status = "disabled"; }; dpmac10: ethernet@a { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xa>; + status = "disabled"; }; }; }; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dtsi b/arch/arm/dts/fsl-ls2080a-qds.dtsi index cb7851f2cc0..f442baa8bfe 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dtsi +++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi @@ -31,7 +31,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -40,7 +40,7 @@ spi-cpha; reg = <0>; }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -49,7 +49,7 @@ spi-cpha; reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts b/arch/arm/dts/fsl-ls2080a-rdb.dts index 0a87caeba96..5a9b5c06e23 100644 --- a/arch/arm/dts/fsl-ls2080a-rdb.dts +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts @@ -22,7 +22,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q512a { + dflash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index d754eb4d5cc..c1173a95f24 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -118,7 +118,7 @@ interrupts = <0 35 0x4>; /* Level high type */ }; - dspi: dspi@2100000 { + dspi: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -127,7 +127,7 @@ spi-num-chipselects = <6>; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls2080a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/fsl-ls2081a-rdb.dts b/arch/arm/dts/fsl-ls2081a-rdb.dts index b0b7ef08a02..61f0ed9b821 100644 --- a/arch/arm/dts/fsl-ls2081a-rdb.dts +++ b/arch/arm/dts/fsl-ls2081a-rdb.dts @@ -25,7 +25,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q512a { + dflash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index a609290000f..1884946cc7a 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -113,7 +113,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q512a { + dflash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index e96605b1b4f..6fa36de0622 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -31,28 +31,28 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -64,28 +64,28 @@ bus-num = <0>; status = "okay"; - dflash3: n25q128a { + dflash3: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash4: sst25wf040b { + dflash4: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash5: en25s64 { + dflash5: en25s64@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -97,28 +97,28 @@ bus-num = <0>; status = "okay"; - dflash6: n25q128a { + dflash6: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash7: sst25wf040b { + dflash7: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash8: en25s64 { + dflash8: en25s64@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 680c69c7b73..4b4b1c100b8 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -134,7 +134,7 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; - fspi: flexspi@20c0000 { + fspi: spi@20c0000 { compatible = "nxp,lx2160a-fspi"; #address-cells = <1>; #size-cells = <0>; @@ -221,7 +221,7 @@ status = "disabled"; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -230,7 +230,7 @@ spi-num-chipselects = <6>; }; - dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -239,7 +239,7 @@ spi-num-chipselects = <6>; }; - dspi2: dspi@2120000 { + dspi2: spi@2120000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts index 0ca30df8620..4eaf982529d 100644 --- a/arch/arm/dts/fsl-lx2162a-qds.dts +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -41,28 +41,28 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -74,28 +74,28 @@ bus-num = <0>; status = "okay"; - dflash3: n25q128a { + dflash3: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash4: sst25wf040b { + dflash4: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash5: en25s64 { + dflash5: en25s64@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -107,28 +107,28 @@ bus-num = <0>; status = "okay"; - dflash6: n25q128a { + dflash6: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash7: sst25wf040b { + dflash7: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash8: en25s64 { + dflash8: en25s64@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; diff --git a/arch/arm/dts/imx7d-mba7-u-boot.dtsi b/arch/arm/dts/imx7d-mba7-u-boot.dtsi new file mode 100644 index 00000000000..3ccc95a7ac6 --- /dev/null +++ b/arch/arm/dts/imx7d-mba7-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for TQ-Systems TQMa7D board on MBa7x carrier board. + * + * Copyright (C) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany + * Author: Steffen Doster + */ + +#include "imx7s-mba7-u-boot.dtsi" diff --git a/arch/arm/dts/imx7s-mba7-u-boot.dtsi b/arch/arm/dts/imx7s-mba7-u-boot.dtsi new file mode 100644 index 00000000000..bb560f4d85b --- /dev/null +++ b/arch/arm/dts/imx7s-mba7-u-boot.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for TQ-Systems TQMa7S board on MBa7x carrier board. + * + * Copyright (C) 2025-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany + * Author: Steffen Doster + */ + +#include "imx7s-tqma7-u-boot.dtsi" + +/ { + config { + u-boot,mmc-env-offset = <0x100000>; + u-boot,mmc-env-offset-redundant = <0x110000>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&gpio4 { + /* Deassert BOOT_EN after boot to separate BOOT_CFG circuits from LCD signals */ + boot-en-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + }; +}; + +&wdog1 { + u-boot,noautostart; + timeout-sec = <60>; +}; + +&iomuxc { + bootph-pre-ram; +}; + +&pinctrl_uart6 { + bootph-pre-ram; +}; + +&uart6 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx7s-tqma7-u-boot.dtsi b/arch/arm/dts/imx7s-tqma7-u-boot.dtsi new file mode 100644 index 00000000000..2d1d614cd57 --- /dev/null +++ b/arch/arm/dts/imx7s-tqma7-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for TQ-Systems TQMa7S module. + * + * Copyright (C) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany + * Author: Steffen Doster + */ + +#include "imx7s-u-boot.dtsi" + +&soc { + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; +}; + +&aips3 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index d891e8062fe..ab135fc8a47 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -50,14 +50,6 @@ section { pad-byte = <0x00>; -#ifdef CONFIG_FSPI_CONF_HEADER - fspi_conf_block { - filename = CONFIG_FSPI_CONF_FILE; - type = "blob-ext"; - size = <0x1000>; - }; -#endif - #ifdef CONFIG_IMX_HAB nxp-imx8mcst@0 { filename = "u-boot-spl-mkimage.signed.bin"; @@ -68,7 +60,12 @@ binman_imx_spl: nxp-imx8mimage { filename = "u-boot-spl-mkimage.bin"; +#ifdef CONFIG_FSPI_CONF_HEADER + nxp,boot-from = "fspi"; + nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE; +#else nxp,boot-from = "sd"; +#endif nxp,rom-version = <1>; nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; args; /* Needed by mkimage etype superclass */ diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 29eecd6d70d..8993605af3c 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -104,14 +104,6 @@ section { pad-byte = <0x00>; -#ifdef CONFIG_FSPI_CONF_HEADER - fspi_conf_block { - filename = CONFIG_FSPI_CONF_FILE; - type = "blob-ext"; - offset = <0x400>; - }; -#endif - #ifdef CONFIG_IMX_HAB nxp-imx8mcst@0 { filename = "u-boot-spl-mkimage.signed.bin"; @@ -122,7 +114,12 @@ binman_imx_spl: nxp-imx8mimage { filename = "u-boot-spl-mkimage.bin"; +#ifdef CONFIG_FSPI_CONF_HEADER + nxp,boot-from = "fspi"; + nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE; +#else nxp,boot-from = "sd"; +#endif nxp,rom-version = <2>; nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; args; /* Needed by mkimage etype superclass */ diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index d987f68b6ba..ca80dc994b1 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -2,19 +2,105 @@ #include "imx8mq-u-boot.dtsi" +&aips1 { + bootph-all; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&pinctrl_i2c1 { + bootph-all; +}; + +&i2c1 { + bootph-all; +}; + +&soc { + bootph-all; + bootph-pre-ram; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} { + bootph-all; +}; + &pinctrl_uart1 { bootph-pre-ram; }; +&uart1 { + bootph-pre-ram; +}; + &usdhc1 { + bootph-pre-ram; mmc-hs400-1_8v; + /delete-property/ vqmmc-supply; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; }; &usdhc2 { + bootph-pre-ram; sd-uhs-sdr104; sd-uhs-ddr50; }; -&uart1 { +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2 { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +#ifdef CONFIG_FSL_CAAM +&crypto { + bootph-pre-ram; +}; + +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { bootph-pre-ram; }; +#endif diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi index d361f3f5592..7ab7706d7a7 100644 --- a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi @@ -2,26 +2,90 @@ #include "imx8mq-u-boot.dtsi" +&aips1 { + bootph-all; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&pinctrl_i2c1 { + bootph-all; +}; + +&i2c1 { + bootph-all; +}; + +&soc { + bootph-all; + bootph-pre-ram; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} { + bootph-all; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&uart1 { + bootph-pre-ram; +}; + &usdhc1 { + bootph-pre-ram; mmc-hs400-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; }; &usdhc2 { + bootph-pre-ram; sd-uhs-sdr104; sd-uhs-ddr50; }; +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2 { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + &uart1 { + bootph-pre-ram; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; }; &uart2 { + bootph-pre-ram; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; }; &uart3 { + bootph-pre-ram; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; }; diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi index 98da015a444..4d326040c0a 100644 --- a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi @@ -10,7 +10,7 @@ bootph-pre-ram; }; -&binman_imx_spl { +&binman { section { signed-hdmi-imx8m { filename = "signed_dp_imx8m.bin"; diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi index 05f809c035d..11b81f0bbb9 100644 --- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi @@ -2,7 +2,12 @@ #include "imx8mq-u-boot.dtsi" +&gpio2 { + bootph-pre-ram; +}; + ®_usdhc2_vmmc { + bootph-pre-ram; u-boot,off-on-delay-us = <20000>; }; @@ -13,3 +18,39 @@ &pinctrl_uart1 { bootph-pre-ram; }; + +&usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 0687fcdbd68..ed2c704f2e5 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -41,6 +41,33 @@ filename = "flash.bin"; section { pad-byte = <0x00>; + /* + * signed_hdmi_imx8m.bin contains a 1KB zero-filled padding at + * its beginning. This padding has no functional purpose, but + * the firmware is provided and signed by NXP, so the head + * must be preserved and should not be removed. + * + * When the signed HDMI firmware is placed at the beginning of + * flash.bin, the IVT header of u-boot-spl must still reside at + * a 4KB-aligned address. Since flash.bin starts with the HDMI + * firmware (including its 1KB padding), there is already a 1KB + * empty region at the head of flash.bin. + * + * The required 4KB alignment is therefore calculated relative + * to the location after this 1KB padding. To achieve this, we + * explicitly set align and align-size to 0x1000, and add an + * additional 0x400 (1KB) fill to account for the padding. + */ + signed-hdmi-imx8m { + filename = "signed_hdmi_imx8m.bin"; + type = "blob-ext"; + align = <0x1000>; + align-size = <0x1000>; + }; + + fill { + size = <0x400>; + }; #ifdef CONFIG_IMX_HAB nxp-imx8mcst@0 { @@ -51,145 +78,142 @@ #endif binman_imx_spl: nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <1>; - nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; - args; /* Needed by mkimage etype superclass */ - - section { - align = <4>; - align-size = <4>; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <1>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; + section { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem.bin"; + align-end = <4>; + type = "blob-ext"; + }; - signed-hdmi-imx8m { - filename = "signed_hdmi_imx8m.bin"; - type = "blob-ext"; - }; + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem.bin"; + align-end = <4>; + type = "blob-ext"; }; }; + }; #ifdef CONFIG_IMX_HAB }; +#endif + }; - nxp-imx8mcst@1 { - filename = "u-boot-fit.signed.bin"; - nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>; - offset = <0x58000>; - args; /* Needed by mkimage etype superclass */ +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>; + offset = <0x58400>; + args; /* Needed by mkimage etype superclass */ #endif - binman_imx_fit: fit { - description = "Configuration to load ATF before U-Boot"; - filename = "u-boot.itb"; + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; + filename = "u-boot.itb"; #ifndef CONFIG_IMX_HAB - fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; #endif - #address-cells = <1>; + #address-cells = <1>; - offset = <0x57c00>; + offset = <0x58000>; - images { - uboot { - arch = "arm64"; - compression = "none"; - description = "U-Boot (64-bit)"; - load = <CONFIG_TEXT_BASE>; - type = "standalone"; + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = <CONFIG_TEXT_BASE>; + type = "standalone"; - uboot-blob { - filename = "u-boot-nodtb.bin"; - type = "blob-ext"; - }; + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; }; + }; #ifndef CONFIG_ARMV8_PSCI - atf { - arch = "arm64"; - compression = "none"; - description = "ARM Trusted Firmware"; - entry = <0x910000>; - load = <0x910000>; - type = "firmware"; + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x910000>; + load = <0x910000>; + type = "firmware"; - atf-blob { - filename = "bl31.bin"; - type = "blob-ext"; - }; + atf-blob { + filename = "bl31.bin"; + type = "blob-ext"; }; + }; #endif - tee: tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>; - entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>; + tee: tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>; + entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>; - tee-os { - filename = "tee.bin"; - optional; - }; + tee-os { + filename = "tee.bin"; + optional; }; + }; - fdt { - compression = "none"; - description = "NAME"; - type = "flat_dt"; + fdt { + compression = "none"; + description = "NAME"; + type = "flat_dt"; - uboot-fdt-blob { - filename = "u-boot.dtb"; - type = "blob-ext"; - }; + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; }; }; + }; - configurations { - default = "conf"; + configurations { + default = "conf"; - conf { - description = "NAME"; - fdt = "fdt"; - firmware = "uboot"; + conf { + description = "NAME"; + fdt = "fdt"; + firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI - loadables = "atf", "tee"; + loadables = "atf", "tee"; #endif - }; }; }; -#ifdef CONFIG_IMX_HAB }; -#endif +#ifdef CONFIG_IMX_HAB }; +#endif }; diff --git a/arch/arm/dts/imx943-u-boot.dtsi b/arch/arm/dts/imx943-u-boot.dtsi index 3457442a3b0..8a7a6f11158 100644 --- a/arch/arm/dts/imx943-u-boot.dtsi +++ b/arch/arm/dts/imx943-u-boot.dtsi @@ -339,12 +339,6 @@ }; }; - netc_timer0: ethernet@0,1 { - compatible = "pci1131,ee02"; - reg = <0x100 0 0 0 0>; - status = "disabled"; - }; - netc_switch: ethernet-switch@0,2 { compatible = "pci1131,eef2", "nxp,imx943-netc-switch"; reg = <0x200 0 0 0 0>; @@ -408,12 +402,6 @@ status = "disabled"; }; - netc_timer1: ethernet@0,1 { - compatible = "pci1131,ee02"; - reg = <0x10100 0 0 0 0>; - status = "disabled"; - }; - enetc1: ethernet@8,0 { compatible = "pci1131,e101"; reg = <0x14000 0 0 0 0>; @@ -426,12 +414,6 @@ status = "disabled"; }; - netc_timer2: ethernet@10,1 { - compatible = "pci1131,ee02"; - reg = <0x18100 0 0 0 0>; - status = "disabled"; - }; - netc_emdio: mdio@18,0 { compatible = "pci1131,ee00"; reg = <0x1c000 0 0 0 0>; diff --git a/arch/arm/dts/imx95-verdin-dev.dtsi b/arch/arm/dts/imx95-verdin-dev.dtsi new file mode 100644 index 00000000000..803480eef47 --- /dev/null +++ b/arch/arm/dts/imx95-verdin-dev.dtsi @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + clocks = <&scmi_clk IMX95_CLK_SAI3>; + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3_mclk>; + #sound-dai-cells = <0>; + }; + + carrier_gpio_expander: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&lpuart7 { + rs485-rts-active-low; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +&netc_emdio { + ethphy2: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin I2S_1 */ +&sai3 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; diff --git a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi new file mode 100644 index 00000000000..83802156d52 --- /dev/null +++ b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) Toradex */ + +#include "imx95-u-boot.dtsi" + +/ { + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-imem} { + filename = "lpddr4x_imem_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-dmem} { + filename = "lpddr4x_dmem_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-imem-qb} { + filename = "lpddr4x_imem_qb_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-dmem-qb} { + filename = "lpddr4x_dmem_qb_v202409.bin"; +}; + +&gpio1 { + reg = <0 0x47400000 0 0x1000>, <0 0x47400000 0 0x40>; + bootph-pre-ram; + + ctrl-sleep-moci-hog { + bootph-pre-ram; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <14 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + }; +}; + +&som_gpio_expander { + bootph-pre-ram; +}; + +&lpi2c2 { + bootph-pre-ram; +}; + +&lpuart1 { + clocks = <&scmi_clk IMX95_CLK_LPUART1>, <&scmi_clk IMX95_CLK_LPUART1>; + clock-names = "ipg", "per"; + bootph-pre-ram; +}; + +&pinctrl_ctrl_sleep_moci { + bootph-pre-ram; +}; + +&pinctrl_io_exp_int { + bootph-pre-ram; +}; + +&pinctrl_lpi2c2 { + bootph-pre-ram; +}; + +&pinctrl_lpi2c2_gpio { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&som_gpio_expander { + bootph-pre-ram; +}; + +&usb2 { + /delete-property/power-domains; +}; + +&usb3 { + status = "disabled"; +}; + +&usb3_dwc3 { + status = "disabled"; +}; + +&usb_recov_ctrl { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&wdog3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx95-verdin-wifi-dev.dts b/arch/arm/dts/imx95-verdin-wifi-dev.dts new file mode 100644 index 00000000000..345d3724702 --- /dev/null +++ b/arch/arm/dts/imx95-verdin-wifi-dev.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Verdin Development Board"; + compatible = "toradex,verdin-imx95-wifi-dev", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm/dts/imx95-verdin-wifi.dtsi b/arch/arm/dts/imx95-verdin-wifi.dtsi new file mode 100644 index 00000000000..256c9ed0460 --- /dev/null +++ b/arch/arm/dts/imx95-verdin-wifi.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + /* PMIC_EN_WIFI */ + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PDn_MAYA-W260"; + startup-delay-us = <2000>; + }; +}; + +/* On-module Bluetooth */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + uart-has-rtscts; + + status = "okay"; + + som_bt: bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_wifi_en>; + + status = "okay"; +}; diff --git a/arch/arm/dts/imx95-verdin.dtsi b/arch/arm/dts/imx95-verdin.dtsi new file mode 100644 index 00000000000..29cd4b91a16 --- /dev/null +++ b/arch/arm/dts/imx95-verdin.dtsi @@ -0,0 +1,1172 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx95.dtsi" +#include "imx95-u-boot.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + i2c0 = &lpi2c2; + i2c1 = &lpi2c4; + i2c2 = &lpi2c3; + i2c3 = &i3c2; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart7; + serial1 = &lpuart8; + serial2 = &lpuart1; + serial3 = &lpuart2; + serial4 = &lpuart6; + usb0 = &usb2; + usb1 = &usb3; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + /* Verdin USB_1_ID (SODIMM 161) */ + id-gpios = <&som_gpio_expander 5 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb1_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_id>; + }; + }; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + verdin_key_wakeup: key-wakeup { + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Verdin USB_1_EN (SODIMM 155) */ + gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Verdin USB_2_EN (SODIMM 185) */ + gpios = <&som_gpio_expander 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_EN"; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vsel>; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + states = <1800000 0x1>, + <3300000 0x0>; + regulator-name = "PMIC_SD2_VSEL"; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + cm7: remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu7 0 1 + &mu7 1 1 + &mu7 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; +}; + +&gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153", + "SODIMM_20", + "SODIMM_22", + "SODIMM_252", /* 10 */ + "", + "SODIMM_189", + "IO_EXP_INT", + "SODIMM_256", + ""; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = + "SODIMM_206", /* 0 */ + "SODIMM_198", + "SODIMM_200", + "SODIMM_196", + "", + "SODIMM_15", + "SODIMM_16", + "", + "SODIMM_131", + "SODIMM_129", + "SODIMM_135", /* 10 */ + "SODIMM_133", + "SODIMM_139", + "SODIMM_137", + "SODIMM_143", + "SODIMM_141", + "SODIMM_30", + "SODIMM_38", + "SODIMM_208", + "SODIMM_19", + "SODIMM_36", /* 20 */ + "SODIMM_34", + "SODIMM_93", + "SODIMM_95", + "SODIMM_210", + "SODIMM_24", + "SODIMM_32", + "SODIMM_26", + "SODIMM_53", + "SODIMM_55", + "SODIMM_12", /* 30 */ + "SODIMM_14"; +}; + +&gpio3 { + gpio-line-names = + "SODIMM_84", /* 0 */ + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72", + "SODIMM_76", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "PMIC_SD2_VSEL", + "", /* 20 */ + "", + "", + "", + "", + "", + "SODIMM_91", + "SODIMM_218", + "", + "", + "", /* 30 */ + ""; +}; + +&gpio4 { + gpio-line-names = + "SODIMM_59", /* 0 */ + "SODIMM_57", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "SODIMM_193", + "SODIMM_191", + "SODIMM_215", + "SODIMM_217", + "SODIMM_219", + "SODIMM_221", + "SODIMM_211", /* 20 */ + "SODIMM_213", + "SODIMM_199", + "SODIMM_197", + "SODIMM_201", + "SODIMM_203", + "SODIMM_205", + "SODIMM_207", + "SODIMM_216", + "SODIMM_202"; +}; + +&gpio5 { + gpio-line-names = + "SODIMM_56", /* 0 */ + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "SODIMM_46", + "SODIMM_44", + "SODIMM_42", + "SODIMM_48", + "SODIMM_66", + "SODIMM_52", + "SODIMM_54", /* 10 */ + "SODIMM_64", + "SODIMM_212", + "", + "", + "", + "", + ""; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <400000>; +}; + +/* CTRL_I2C (On-module I2C) */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>, <&pinctrl_io_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>, <&pinctrl_io_exp_int>; + clock-frequency = <400000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; + + status = "okay"; + + som_gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "SODIMM_220", /* 0 */ + "SODIMM_222", + "SODIMM_17", + "SODIMM_21", + "SODIMM_244", + "SODIMM_161", + "SODIMM_157", + "SODIMM_155", + "SODIMM_185", + "SODIMM_187", + "USB_RECOV_CTRL#", /* 10 */ + "ENET1_INT#", + "TPM_INT#", + "TPM_CS#", + "", + ""; + + /* + * Switch USB to default position: + * - SoC USB2 -> Verdin USB_1 + * - SoC USB1 -> Verdin USB_2 + * Reset configuration: + * - SoC USB1 -> Verdin USB_1 (USB recovery) + * - SoC USB2 not connected + */ + usb_recov_ctrl: usb-recov-ctrl-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "USB_RECOV_CTRL#"; + output-high; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_spi1_cs>; + cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, + <&som_gpio_expander 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi6's per-clock (twice the max speed) is 24 MHz + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Verdin UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Verdin UART_1 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>, <&pinctrl_uart8_cts>, <&pinctrl_uart8_rts>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_bus0 { + msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; //NETC Timer + iommu-map = <0x0 &smmu 0x20 0x1>, + <0x10 &smmu 0x21 0x1>, + <0x20 &smmu 0x22 0x1>, + <0x40 &smmu 0x23 0x1>, + <0x50 &smmu 0x25 0x1>, + <0x60 &smmu 0x26 0x1>, + <0x80 &smmu 0x24 0x1>, + <0xc0 &smmu 0x27 0x1>; +}; + +/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_LOW>; +}; + +/* Verdin I2S_1 */ +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = <KEY_POWER>; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Verdin PWM_1 */ +&tpm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm4>; +}; + +/* Verdin PWM_2 */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; +}; + +/* Verdin USB_1 */ +&usb2 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; + vbus-supply = <®_usb1_vbus>; + + port { + usb1_id: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "host"; +}; + +&usb3_phy { + vbus-supply = <®_usb2_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* On-module Bluetooth on WB SKUs, module-specific UART otherwise */ + pinctrl_bt_uart: btuartgrp { + fsl,pins = <IMX95_PAD_GPIO_IO04__LPUART6_TX 0x31e>, /* WiFi_UART_SoC_TXD */ + <IMX95_PAD_GPIO_IO33__LPUART6_RX 0x31e>, /* WiFi_UART_SoC_RXD */ + <IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x31e>, /* WiFi_UART_SoC_CTS */ + <IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e>; /* WiFi_UART_SoC_RTS */ + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_csi1_mclk: csi1mclkgrp { + fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SODIMM 91 */ + }; + + /* Verdin CTRL_SLEEP_MOCI# */ + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x51e>; /* SODIMM 256 */ + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* SODIMM 252 */ + }; + + /* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ + pinctrl_emdio: emdiogrp { + fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* ENET2_MDC, SODIMM 193 */ + <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* ENET2_MDIO, SODIMM 191 */ + }; + + /* Verdin ETH_1 (On-module PHY) */ + pinctrl_enetc0: enetc0grp { + fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ + <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ + <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ + <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ + <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ + <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ + <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ + <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ + <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ + <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ + <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ + <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ + }; + + /* Verdin ETH_2_RGMII */ + pinctrl_enetc1: enetc1grp { + fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */ + <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */ + <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */ + <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */ + <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */ + <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */ + <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */ + <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */ + <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */ + <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */ + <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */ + <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */ + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: eth2rgmiiintgrp { + fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* SODIMM 189 */ + }; + + /* Verdin CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SODIMM 20 */ + <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SODIMM 22 */ + }; + + /* Verdin CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SODIMM 24 */ + <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SODIMM 26 */ + }; + + /* Verdin QSPI_1 */ + pinctrl_flexspi1: flexspi1grp { + fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>, /* SODIMM 54 */ + <IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x3fe>, /* SODIMM 64 */ + <IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x3fe>, /* SODIMM 52 */ + <IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x3fe>, /* SODIMM 56 */ + <IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x3fe>, /* SODIMM 58 */ + <IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x3fe>, /* SODIMM 60 */ + <IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x3fe>, /* SODIMM 62 */ + <IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x3fe>; /* SODIMM 66 */ + }; + + /* Verdin GPIO_1 */ + pinctrl_gpio1: gpio1grp { + fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x51e>; /* SODIMM 206 */ + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio2: gpio2grp { + fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x51e>; /* SODIMM 208 */ + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio3: gpio3grp { + fsl,pins = <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x51e>; /* SODIMM 210 */ + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = <IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x51e>; /* SODIMM 212 */ + }; + + /* Verdin GPIO_5_CSI */ + pinctrl_gpio5: gpio5grp { + fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x51e>; /* SODIMM 216 */ + }; + + /* Verdin GPIO_6_CSI */ + pinctrl_gpio6: gpio6grp { + fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e>; /* SODIMM 218 */ + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_bclk_gpio: i2s2bclkgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x51e>; /* SODIMM 42 */ + }; + + /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_d_in_gpio: i2s2dingpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x31e>; /* SODIMM 48 */ + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_d_out_gpio: i2s2doutgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x51e>; /* SODIMM 46 */ + }; + + /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_sync_gpio: i2s2syncgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x51e>; /* SODIMM 44 */ + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* SODIMM 59 */ + <IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* SODIMM 57 */ + }; + + pinctrl_io_exp_int: ioexpintgrp { + fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* IO_EXP_INT */ + }; + + /* CTRL_I2C (On-module I2C) */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* CTRL_I2C_SCL */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* CTRL_I2C_SDA */ + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* CTRL_I2C_SCL */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* CTRL_I2C_SDA */ + }; + + /* Verdin I2C_2_DSI */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SODIMM 53 */ + <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SODIMM 55 */ + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SODIMM 53 */ + <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SODIMM 55 */ + }; + + /* Verdin I2C_1 */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* SODIMM 14 */ + <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* SODIMM 12 */ + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* SODIMM 14 */ + <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* SODIMM 12 */ + }; + + /* Verdin I2C_4_CSI */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SODIMM 93 */ + <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SODIMM 95 */ + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SODIMM 93 */ + <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SODIMM 95 */ + }; + + /* Verdin SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SODIMM 198 */ + <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SODIMM 200 */ + <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SODIMM 196 */ + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: qspi1clkgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x11e>; /* SODIMM 52 */ + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: qspi1cs2gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x11e>; /* SODIMM 64 */ + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: qspi1csgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x11e>; /* SODIMM 54 */ + }; + + /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_dqs_gpio: qspi1dqsgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x11e>; /* SODIMM 66 */ + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: qspi1io0gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x119e>; /* SODIMM 56 */ + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: qspi1io1gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x119e>; /* SODIMM 58 */ + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: qspi1io2gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x11e>; /* SODIMM 60 */ + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: qspi1io3gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x11e>; /* SODIMM 62 */ + }; + + /* Verdin I2S_1 */ + pinctrl_sai3: sai3grp { + fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SODIMM 30 */ + <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SODIMM 36 */ + <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SODIMM 34 */ + <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SODIMM 32 */ + }; + + /* Verdin I2S_1_MCLK */ + pinctrl_sai3_mclk: sai3mclkgrp { + fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SODIMM 38 */ + }; + + /* Verdin I2S_2 */ + pinctrl_sai5: sai5grp { + fsl,pins = <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SODIMM 46 */ + <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>, /* SODIMM 44 */ + <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SODIMM 42 */ + <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>; /* SODIMM 48 */ + }; + + /* Verdin SPI_1_CS */ + pinctrl_spi1_cs: spi1csgrp { + fsl,pins = <IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x3fe>; /* SODIMM 202 */ + }; + + /* Verdin PWM_1 */ + pinctrl_tpm4: tpm4grp { + fsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0 0x11e>; /* SODIMM 15 */ + }; + + /* Verdin PWM_2 */ + pinctrl_tpm5: tpm5grp { + fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SODIMM 16 */ + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_tpm6_gpio: tpm6gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x51e>; /* SODIMM 19 */ + }; + + /* Verdin PWM_3_DSI */ + pinctrl_tpm6: tpm6grp { + fsl,pins = <IMX95_PAD_GPIO_IO19__TPM6_CH2 0x11e>; /* SODIMM 19 */ + }; + + /* Verdin UART_3, used as the Linux Console */ + pinctrl_uart1: uart1grp { + fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>, /* SODIMM 147 */ + <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>; /* SODIMM 149 */ + }; + + /* Verdin UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SODIMM 151 */ + <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SODIMM 153 */ + }; + + /* Verdin UART_1 */ + pinctrl_uart7: uart7grp { + fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX 0x31e>, /* SODIMM 131 */ + <IMX95_PAD_GPIO_IO09__LPUART7_RX 0x31e>, /* SODIMM 129 */ + <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* SODIMM 135 */ + <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* SODIMM 133 */ + }; + + /* Verdin UART_2 CTS */ + pinctrl_uart8_cts: uart8ctsgrp { + fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x31e>; /* SODIMM 143 */ + }; + + /* Verdin UART_2 RTS */ + pinctrl_uart8_rts: uart8rtsgrp { + fsl,pins = <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x31e>; /* SODIMM 141 */ + }; + + /* Verdin UART_2 RX/TX */ + pinctrl_uart8: uart8grp { + fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>, /* SODIMM 139 */ + <IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e>; /* SODIMM 137 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */ + }; + + /* Verdin SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SODIMM 78 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SODIMM 74 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SODIMM 80 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SODIMM 82 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SODIMM 70 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SODIMM 78 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SODIMM 74 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SODIMM 80 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SODIMM 82 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SODIMM 70 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SODIMM 78 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SODIMM 74 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SODIMM 80 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SODIMM 82 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SODIMM 70 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SODIMM 72 */ + }; + + /* Verdin SD_1_CD# */ + pinctrl_usdhc2_cd: usdhc2-cdgrp { + fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SODIMM 84 */ + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { + fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SODIMM 76 */ + }; + + pinctrl_usdhc2_vsel: usdhc2-vselgrp { + fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */ + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */ + <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */ + <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */ + <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */ + <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */ + <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */ + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */ + <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */ + <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */ + <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */ + <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */ + <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */ + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x51e>; /* PMIC_EN_WIFI */ + }; +}; diff --git a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi index 9e4af4d9f72..36640f31d61 100644 --- a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi +++ b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi @@ -12,6 +12,9 @@ reg = <0x0 0x80000000 0x0 0x20000000>; }; + chosen { + stdout-path = "serial0:115200n8"; + }; }; &sdhc { diff --git a/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi new file mode 100644 index 00000000000..ea773a2ca4f --- /dev/null +++ b/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi @@ -0,0 +1,4410 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:50:37 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_0 27500000 +#define DDRSS_PLL_FREQUENCY_1 1066500000 +#define DDRSS_PLL_FREQUENCY_2 1066500000 + +#define MULTI_DDR_CFG_INTRLV_GRAN 0 +#define MULTI_DDR_CFG_INTRLV_SIZE 11 +#define MULTI_DDR_CFG_ECC_ENABLE 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 0 +#define MULTI_DDR_CFG_EMIFS_ACTIVE 3 + +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000003 +#define DDR_REG1_SIZE_LSB 0x80000000 + + +#define DDRSS0_CTL_00_DATA 0x00000B00 +#define DDRSS0_CTL_01_DATA 0x00000000 +#define DDRSS0_CTL_02_DATA 0x00000000 +#define DDRSS0_CTL_03_DATA 0x00000000 +#define DDRSS0_CTL_04_DATA 0x00000000 +#define DDRSS0_CTL_05_DATA 0x00000000 +#define DDRSS0_CTL_06_DATA 0x00000000 +#define DDRSS0_CTL_07_DATA 0x00002AF8 +#define DDRSS0_CTL_08_DATA 0x0001ADAF +#define DDRSS0_CTL_09_DATA 0x00000005 +#define DDRSS0_CTL_10_DATA 0x0000006E +#define DDRSS0_CTL_11_DATA 0x000681C8 +#define DDRSS0_CTL_12_DATA 0x004111C9 +#define DDRSS0_CTL_13_DATA 0x00000005 +#define DDRSS0_CTL_14_DATA 0x000010A9 +#define DDRSS0_CTL_15_DATA 0x000681C8 +#define DDRSS0_CTL_16_DATA 0x004111C9 +#define DDRSS0_CTL_17_DATA 0x00000005 +#define DDRSS0_CTL_18_DATA 0x000010A9 +#define DDRSS0_CTL_19_DATA 0x01010000 +#define DDRSS0_CTL_20_DATA 0x01011001 +#define DDRSS0_CTL_21_DATA 0x02010000 +#define DDRSS0_CTL_22_DATA 0x00020100 +#define DDRSS0_CTL_23_DATA 0x0000000B +#define DDRSS0_CTL_24_DATA 0x0000001C +#define DDRSS0_CTL_25_DATA 0x00000000 +#define DDRSS0_CTL_26_DATA 0x00000000 +#define DDRSS0_CTL_27_DATA 0x03020200 +#define DDRSS0_CTL_28_DATA 0x00005656 +#define DDRSS0_CTL_29_DATA 0x00100000 +#define DDRSS0_CTL_30_DATA 0x00000000 +#define DDRSS0_CTL_31_DATA 0x00000000 +#define DDRSS0_CTL_32_DATA 0x00000000 +#define DDRSS0_CTL_33_DATA 0x00000000 +#define DDRSS0_CTL_34_DATA 0x040C0000 +#define DDRSS0_CTL_35_DATA 0x12501250 +#define DDRSS0_CTL_36_DATA 0x00050804 +#define DDRSS0_CTL_37_DATA 0x09040008 +#define DDRSS0_CTL_38_DATA 0x15000204 +#define DDRSS0_CTL_39_DATA 0x1760008B +#define DDRSS0_CTL_40_DATA 0x1500422B +#define DDRSS0_CTL_41_DATA 0x1760008B +#define DDRSS0_CTL_42_DATA 0x2000422B +#define DDRSS0_CTL_43_DATA 0x000A0A09 +#define DDRSS0_CTL_44_DATA 0x040003C5 +#define DDRSS0_CTL_45_DATA 0x1E161104 +#define DDRSS0_CTL_46_DATA 0x1000922C +#define DDRSS0_CTL_47_DATA 0x1E161110 +#define DDRSS0_CTL_48_DATA 0x1000922C +#define DDRSS0_CTL_49_DATA 0x02030410 +#define DDRSS0_CTL_50_DATA 0x2C060500 +#define DDRSS0_CTL_51_DATA 0x08292C29 +#define DDRSS0_CTL_52_DATA 0x14000E0A +#define DDRSS0_CTL_53_DATA 0x04010A0A +#define DDRSS0_CTL_54_DATA 0x01010004 +#define DDRSS0_CTL_55_DATA 0x0454540A +#define DDRSS0_CTL_56_DATA 0x04313104 +#define DDRSS0_CTL_57_DATA 0x00003131 +#define DDRSS0_CTL_58_DATA 0x00010100 +#define DDRSS0_CTL_59_DATA 0x03010000 +#define DDRSS0_CTL_60_DATA 0x00001508 +#define DDRSS0_CTL_61_DATA 0x00000068 +#define DDRSS0_CTL_62_DATA 0x0000032B +#define DDRSS0_CTL_63_DATA 0x00001035 +#define DDRSS0_CTL_64_DATA 0x0000032B +#define DDRSS0_CTL_65_DATA 0x00001035 +#define DDRSS0_CTL_66_DATA 0x00000005 +#define DDRSS0_CTL_67_DATA 0x00050000 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 +#define DDRSS0_CTL_71_DATA 0x00120103 +#define DDRSS0_CTL_72_DATA 0x00100005 +#define DDRSS0_CTL_73_DATA 0x2F080010 +#define DDRSS0_CTL_74_DATA 0x0505012F +#define DDRSS0_CTL_75_DATA 0x0401030A +#define DDRSS0_CTL_76_DATA 0x041E100B +#define DDRSS0_CTL_77_DATA 0x100B0401 +#define DDRSS0_CTL_78_DATA 0x0001041E +#define DDRSS0_CTL_79_DATA 0x00160016 +#define DDRSS0_CTL_80_DATA 0x033B033B +#define DDRSS0_CTL_81_DATA 0x033B033B +#define DDRSS0_CTL_82_DATA 0x03050505 +#define DDRSS0_CTL_83_DATA 0x03010303 +#define DDRSS0_CTL_84_DATA 0x200B100B +#define DDRSS0_CTL_85_DATA 0x04041004 +#define DDRSS0_CTL_86_DATA 0x200B100B +#define DDRSS0_CTL_87_DATA 0x04041004 +#define DDRSS0_CTL_88_DATA 0x03010000 +#define DDRSS0_CTL_89_DATA 0x00010000 +#define DDRSS0_CTL_90_DATA 0x00000000 +#define DDRSS0_CTL_91_DATA 0x00000000 +#define DDRSS0_CTL_92_DATA 0x01000000 +#define DDRSS0_CTL_93_DATA 0x80104002 +#define DDRSS0_CTL_94_DATA 0x00000000 +#define DDRSS0_CTL_95_DATA 0x00040005 +#define DDRSS0_CTL_96_DATA 0x00000000 +#define DDRSS0_CTL_97_DATA 0x00050000 +#define DDRSS0_CTL_98_DATA 0x00000004 +#define DDRSS0_CTL_99_DATA 0x00000000 +#define DDRSS0_CTL_100_DATA 0x00040005 +#define DDRSS0_CTL_101_DATA 0x00000000 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 +#define DDRSS0_CTL_107_DATA 0x00000000 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 +#define DDRSS0_CTL_114_DATA 0x00000000 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 +#define DDRSS0_CTL_121_DATA 0x00000000 +#define DDRSS0_CTL_122_DATA 0x00007173 +#define DDRSS0_CTL_123_DATA 0x00000000 +#define DDRSS0_CTL_124_DATA 0x00000000 +#define DDRSS0_CTL_125_DATA 0x00000000 +#define DDRSS0_CTL_126_DATA 0x00000000 +#define DDRSS0_CTL_127_DATA 0x00000000 +#define DDRSS0_CTL_128_DATA 0x00000000 +#define DDRSS0_CTL_129_DATA 0x00000000 +#define DDRSS0_CTL_130_DATA 0x00000000 +#define DDRSS0_CTL_131_DATA 0x0B030500 +#define DDRSS0_CTL_132_DATA 0x00040B04 +#define DDRSS0_CTL_133_DATA 0x0A090000 +#define DDRSS0_CTL_134_DATA 0x0A090701 +#define DDRSS0_CTL_135_DATA 0x0900000E +#define DDRSS0_CTL_136_DATA 0x0907010A +#define DDRSS0_CTL_137_DATA 0x00000E0A +#define DDRSS0_CTL_138_DATA 0x07010A09 +#define DDRSS0_CTL_139_DATA 0x000E0A09 +#define DDRSS0_CTL_140_DATA 0x07000401 +#define DDRSS0_CTL_141_DATA 0x00000000 +#define DDRSS0_CTL_142_DATA 0x00000000 +#define DDRSS0_CTL_143_DATA 0x00000000 +#define DDRSS0_CTL_144_DATA 0x00000000 +#define DDRSS0_CTL_145_DATA 0x00000000 +#define DDRSS0_CTL_146_DATA 0x00000000 +#define DDRSS0_CTL_147_DATA 0x00000000 +#define DDRSS0_CTL_148_DATA 0x08080000 +#define DDRSS0_CTL_149_DATA 0x01000000 +#define DDRSS0_CTL_150_DATA 0x800000C0 +#define DDRSS0_CTL_151_DATA 0x800000C0 +#define DDRSS0_CTL_152_DATA 0x800000C0 +#define DDRSS0_CTL_153_DATA 0x00000000 +#define DDRSS0_CTL_154_DATA 0x00001500 +#define DDRSS0_CTL_155_DATA 0x00000000 +#define DDRSS0_CTL_156_DATA 0x00000001 +#define DDRSS0_CTL_157_DATA 0x00000002 +#define DDRSS0_CTL_158_DATA 0x0000100E +#define DDRSS0_CTL_159_DATA 0x00000000 +#define DDRSS0_CTL_160_DATA 0x00000000 +#define DDRSS0_CTL_161_DATA 0x00000000 +#define DDRSS0_CTL_162_DATA 0x00000000 +#define DDRSS0_CTL_163_DATA 0x00000000 +#define DDRSS0_CTL_164_DATA 0x000B0000 +#define DDRSS0_CTL_165_DATA 0x000E0006 +#define DDRSS0_CTL_166_DATA 0x000E0404 +#define DDRSS0_CTL_167_DATA 0x00D601AB +#define DDRSS0_CTL_168_DATA 0x10100216 +#define DDRSS0_CTL_169_DATA 0x01AB0216 +#define DDRSS0_CTL_170_DATA 0x021600D6 +#define DDRSS0_CTL_171_DATA 0x02161010 +#define DDRSS0_CTL_172_DATA 0x00000000 +#define DDRSS0_CTL_173_DATA 0x00000000 +#define DDRSS0_CTL_174_DATA 0x00000000 +#define DDRSS0_CTL_175_DATA 0x3FF40084 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 +#define DDRSS0_CTL_178_DATA 0x36000000 +#define DDRSS0_CTL_179_DATA 0x27270036 +#define DDRSS0_CTL_180_DATA 0x0F0F0000 +#define DDRSS0_CTL_181_DATA 0x16000000 +#define DDRSS0_CTL_182_DATA 0x00841616 +#define DDRSS0_CTL_183_DATA 0x3FF43FF4 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 +#define DDRSS0_CTL_185_DATA 0x00000000 +#define DDRSS0_CTL_186_DATA 0x00363600 +#define DDRSS0_CTL_187_DATA 0x00002727 +#define DDRSS0_CTL_188_DATA 0x00000F0F +#define DDRSS0_CTL_189_DATA 0x16161600 +#define DDRSS0_CTL_190_DATA 0x00000020 +#define DDRSS0_CTL_191_DATA 0x01000000 +#define DDRSS0_CTL_192_DATA 0x00000001 +#define DDRSS0_CTL_193_DATA 0x00000000 +#define DDRSS0_CTL_194_DATA 0x01000000 +#define DDRSS0_CTL_195_DATA 0x00000001 +#define DDRSS0_CTL_196_DATA 0x00000000 +#define DDRSS0_CTL_197_DATA 0x00000000 +#define DDRSS0_CTL_198_DATA 0x00000000 +#define DDRSS0_CTL_199_DATA 0x00000000 +#define DDRSS0_CTL_200_DATA 0x00000000 +#define DDRSS0_CTL_201_DATA 0x00000000 +#define DDRSS0_CTL_202_DATA 0x00000000 +#define DDRSS0_CTL_203_DATA 0x00000000 +#define DDRSS0_CTL_204_DATA 0x00000000 +#define DDRSS0_CTL_205_DATA 0x00000000 +#define DDRSS0_CTL_206_DATA 0x02000000 +#define DDRSS0_CTL_207_DATA 0x01080101 +#define DDRSS0_CTL_208_DATA 0x00000000 +#define DDRSS0_CTL_209_DATA 0x00000000 +#define DDRSS0_CTL_210_DATA 0x00000000 +#define DDRSS0_CTL_211_DATA 0x00000000 +#define DDRSS0_CTL_212_DATA 0x00000000 +#define DDRSS0_CTL_213_DATA 0x00000000 +#define DDRSS0_CTL_214_DATA 0x00000000 +#define DDRSS0_CTL_215_DATA 0x00000000 +#define DDRSS0_CTL_216_DATA 0x00000000 +#define DDRSS0_CTL_217_DATA 0x00000000 +#define DDRSS0_CTL_218_DATA 0x00000000 +#define DDRSS0_CTL_219_DATA 0x00000000 +#define DDRSS0_CTL_220_DATA 0x00000000 +#define DDRSS0_CTL_221_DATA 0x00000000 +#define DDRSS0_CTL_222_DATA 0x00001000 +#define DDRSS0_CTL_223_DATA 0x006403E8 +#define DDRSS0_CTL_224_DATA 0x00000000 +#define DDRSS0_CTL_225_DATA 0x00000000 +#define DDRSS0_CTL_226_DATA 0x00000000 +#define DDRSS0_CTL_227_DATA 0x15110000 +#define DDRSS0_CTL_228_DATA 0x00040C18 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 +#define DDRSS0_CTL_231_DATA 0x00000000 +#define DDRSS0_CTL_232_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 +#define DDRSS0_CTL_235_DATA 0x00000000 +#define DDRSS0_CTL_236_DATA 0x00000000 +#define DDRSS0_CTL_237_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 +#define DDRSS0_CTL_240_DATA 0x00000000 +#define DDRSS0_CTL_241_DATA 0x00000000 +#define DDRSS0_CTL_242_DATA 0x00030000 +#define DDRSS0_CTL_243_DATA 0x00000000 +#define DDRSS0_CTL_244_DATA 0x00000000 +#define DDRSS0_CTL_245_DATA 0x00000000 +#define DDRSS0_CTL_246_DATA 0x00000000 +#define DDRSS0_CTL_247_DATA 0x00000000 +#define DDRSS0_CTL_248_DATA 0x00000000 +#define DDRSS0_CTL_249_DATA 0x00000000 +#define DDRSS0_CTL_250_DATA 0x00000000 +#define DDRSS0_CTL_251_DATA 0x00000000 +#define DDRSS0_CTL_252_DATA 0x00000000 +#define DDRSS0_CTL_253_DATA 0x00000000 +#define DDRSS0_CTL_254_DATA 0x00000000 +#define DDRSS0_CTL_255_DATA 0x00000000 +#define DDRSS0_CTL_256_DATA 0x00000000 +#define DDRSS0_CTL_257_DATA 0x01000200 +#define DDRSS0_CTL_258_DATA 0x00370040 +#define DDRSS0_CTL_259_DATA 0x00020008 +#define DDRSS0_CTL_260_DATA 0x00400100 +#define DDRSS0_CTL_261_DATA 0x00400855 +#define DDRSS0_CTL_262_DATA 0x01000200 +#define DDRSS0_CTL_263_DATA 0x08550040 +#define DDRSS0_CTL_264_DATA 0x00000040 +#define DDRSS0_CTL_265_DATA 0x006B0003 +#define DDRSS0_CTL_266_DATA 0x0100006B +#define DDRSS0_CTL_267_DATA 0x03030303 +#define DDRSS0_CTL_268_DATA 0x00000000 +#define DDRSS0_CTL_269_DATA 0x00000202 +#define DDRSS0_CTL_270_DATA 0x00001FFF +#define DDRSS0_CTL_271_DATA 0x3FFF2000 +#define DDRSS0_CTL_272_DATA 0x03FF0000 +#define DDRSS0_CTL_273_DATA 0x000103FF +#define DDRSS0_CTL_274_DATA 0x0FFF0B00 +#define DDRSS0_CTL_275_DATA 0x01010001 +#define DDRSS0_CTL_276_DATA 0x01010101 +#define DDRSS0_CTL_277_DATA 0x01180101 +#define DDRSS0_CTL_278_DATA 0x00030000 +#define DDRSS0_CTL_279_DATA 0x00000000 +#define DDRSS0_CTL_280_DATA 0x00000000 +#define DDRSS0_CTL_281_DATA 0x00000000 +#define DDRSS0_CTL_282_DATA 0x00000000 +#define DDRSS0_CTL_283_DATA 0x00000000 +#define DDRSS0_CTL_284_DATA 0x00000000 +#define DDRSS0_CTL_285_DATA 0x00000000 +#define DDRSS0_CTL_286_DATA 0x00040101 +#define DDRSS0_CTL_287_DATA 0x04010100 +#define DDRSS0_CTL_288_DATA 0x00000000 +#define DDRSS0_CTL_289_DATA 0x00000000 +#define DDRSS0_CTL_290_DATA 0x03030300 +#define DDRSS0_CTL_291_DATA 0x00010101 +#define DDRSS0_CTL_292_DATA 0x00000000 +#define DDRSS0_CTL_293_DATA 0x00000000 +#define DDRSS0_CTL_294_DATA 0x00000000 +#define DDRSS0_CTL_295_DATA 0x00000000 +#define DDRSS0_CTL_296_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF +#define DDRSS0_CTL_299_DATA 0x00000000 +#define DDRSS0_CTL_300_DATA 0x00000000 +#define DDRSS0_CTL_301_DATA 0x00000000 +#define DDRSS0_CTL_302_DATA 0x00000000 +#define DDRSS0_CTL_303_DATA 0x00000000 +#define DDRSS0_CTL_304_DATA 0x00000000 +#define DDRSS0_CTL_305_DATA 0x00000000 +#define DDRSS0_CTL_306_DATA 0x00000000 +#define DDRSS0_CTL_307_DATA 0x00000000 +#define DDRSS0_CTL_308_DATA 0x00000000 +#define DDRSS0_CTL_309_DATA 0x00000000 +#define DDRSS0_CTL_310_DATA 0x00000000 +#define DDRSS0_CTL_311_DATA 0x00000000 +#define DDRSS0_CTL_312_DATA 0x00000000 +#define DDRSS0_CTL_313_DATA 0x01000000 +#define DDRSS0_CTL_314_DATA 0x00020201 +#define DDRSS0_CTL_315_DATA 0x01000101 +#define DDRSS0_CTL_316_DATA 0x01010001 +#define DDRSS0_CTL_317_DATA 0x00010101 +#define DDRSS0_CTL_318_DATA 0x050A0A03 +#define DDRSS0_CTL_319_DATA 0x10082323 +#define DDRSS0_CTL_320_DATA 0x00090310 +#define DDRSS0_CTL_321_DATA 0x0B0C030F +#define DDRSS0_CTL_322_DATA 0x0B0C0306 +#define DDRSS0_CTL_323_DATA 0x0C090006 +#define DDRSS0_CTL_324_DATA 0x0100000C +#define DDRSS0_CTL_325_DATA 0x08040801 +#define DDRSS0_CTL_326_DATA 0x00000004 +#define DDRSS0_CTL_327_DATA 0x00000000 +#define DDRSS0_CTL_328_DATA 0x00010000 +#define DDRSS0_CTL_329_DATA 0x00280D00 +#define DDRSS0_CTL_330_DATA 0x00000001 +#define DDRSS0_CTL_331_DATA 0x00030001 +#define DDRSS0_CTL_332_DATA 0x00000000 +#define DDRSS0_CTL_333_DATA 0x00000000 +#define DDRSS0_CTL_334_DATA 0x00000000 +#define DDRSS0_CTL_335_DATA 0x00000000 +#define DDRSS0_CTL_336_DATA 0x00000000 +#define DDRSS0_CTL_337_DATA 0x00000000 +#define DDRSS0_CTL_338_DATA 0x00000000 +#define DDRSS0_CTL_339_DATA 0x00000000 +#define DDRSS0_CTL_340_DATA 0x01000000 +#define DDRSS0_CTL_341_DATA 0x00000001 +#define DDRSS0_CTL_342_DATA 0x00010100 +#define DDRSS0_CTL_343_DATA 0x03030000 +#define DDRSS0_CTL_344_DATA 0x00000000 +#define DDRSS0_CTL_345_DATA 0x00000000 +#define DDRSS0_CTL_346_DATA 0x00000000 +#define DDRSS0_CTL_347_DATA 0x00000000 +#define DDRSS0_CTL_348_DATA 0x00000000 +#define DDRSS0_CTL_349_DATA 0x00000000 +#define DDRSS0_CTL_350_DATA 0x00000000 +#define DDRSS0_CTL_351_DATA 0x00000000 +#define DDRSS0_CTL_352_DATA 0x00000000 +#define DDRSS0_CTL_353_DATA 0x00000000 +#define DDRSS0_CTL_354_DATA 0x00000000 +#define DDRSS0_CTL_355_DATA 0x00000000 +#define DDRSS0_CTL_356_DATA 0x00000000 +#define DDRSS0_CTL_357_DATA 0x00000000 +#define DDRSS0_CTL_358_DATA 0x00000000 +#define DDRSS0_CTL_359_DATA 0x00000000 +#define DDRSS0_CTL_360_DATA 0x000556AA +#define DDRSS0_CTL_361_DATA 0x000AAAAA +#define DDRSS0_CTL_362_DATA 0x000AA955 +#define DDRSS0_CTL_363_DATA 0x00055555 +#define DDRSS0_CTL_364_DATA 0x000B3133 +#define DDRSS0_CTL_365_DATA 0x0004CD33 +#define DDRSS0_CTL_366_DATA 0x0004CECC +#define DDRSS0_CTL_367_DATA 0x000B32CC +#define DDRSS0_CTL_368_DATA 0x00010300 +#define DDRSS0_CTL_369_DATA 0x03000100 +#define DDRSS0_CTL_370_DATA 0x00000000 +#define DDRSS0_CTL_371_DATA 0x00000000 +#define DDRSS0_CTL_372_DATA 0x00000000 +#define DDRSS0_CTL_373_DATA 0x00000000 +#define DDRSS0_CTL_374_DATA 0x00000000 +#define DDRSS0_CTL_375_DATA 0x00000000 +#define DDRSS0_CTL_376_DATA 0x00000000 +#define DDRSS0_CTL_377_DATA 0x00010000 +#define DDRSS0_CTL_378_DATA 0x00000404 +#define DDRSS0_CTL_379_DATA 0x00000000 +#define DDRSS0_CTL_380_DATA 0x00000000 +#define DDRSS0_CTL_381_DATA 0x00000000 +#define DDRSS0_CTL_382_DATA 0x00000000 +#define DDRSS0_CTL_383_DATA 0x00000000 +#define DDRSS0_CTL_384_DATA 0x00000000 +#define DDRSS0_CTL_385_DATA 0x00000000 +#define DDRSS0_CTL_386_DATA 0x00000000 +#define DDRSS0_CTL_387_DATA 0x3A3A1B00 +#define DDRSS0_CTL_388_DATA 0x000A0000 +#define DDRSS0_CTL_389_DATA 0x000000C6 +#define DDRSS0_CTL_390_DATA 0x00000200 +#define DDRSS0_CTL_391_DATA 0x00000200 +#define DDRSS0_CTL_392_DATA 0x00000200 +#define DDRSS0_CTL_393_DATA 0x00000200 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC +#define DDRSS0_CTL_396_DATA 0x00000204 +#define DDRSS0_CTL_397_DATA 0x0000206A +#define DDRSS0_CTL_398_DATA 0x00000200 +#define DDRSS0_CTL_399_DATA 0x00000200 +#define DDRSS0_CTL_400_DATA 0x00000200 +#define DDRSS0_CTL_401_DATA 0x00000200 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A +#define DDRSS0_CTL_406_DATA 0x00000200 +#define DDRSS0_CTL_407_DATA 0x00000200 +#define DDRSS0_CTL_408_DATA 0x00000200 +#define DDRSS0_CTL_409_DATA 0x00000200 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 +#define DDRSS0_CTL_413_DATA 0x03030202 +#define DDRSS0_CTL_414_DATA 0x00000022 +#define DDRSS0_CTL_415_DATA 0x00000000 +#define DDRSS0_CTL_416_DATA 0x00000000 +#define DDRSS0_CTL_417_DATA 0x00001403 +#define DDRSS0_CTL_418_DATA 0x000007D0 +#define DDRSS0_CTL_419_DATA 0x00000000 +#define DDRSS0_CTL_420_DATA 0x00000000 +#define DDRSS0_CTL_421_DATA 0x00030000 +#define DDRSS0_CTL_422_DATA 0x0007001F +#define DDRSS0_CTL_423_DATA 0x001B0033 +#define DDRSS0_CTL_424_DATA 0x001B0033 +#define DDRSS0_CTL_425_DATA 0x00000000 +#define DDRSS0_CTL_426_DATA 0x00000000 +#define DDRSS0_CTL_427_DATA 0x02000000 +#define DDRSS0_CTL_428_DATA 0x01000404 +#define DDRSS0_CTL_429_DATA 0x0B220B22 +#define DDRSS0_CTL_430_DATA 0x00000105 +#define DDRSS0_CTL_431_DATA 0x00010101 +#define DDRSS0_CTL_432_DATA 0x00010101 +#define DDRSS0_CTL_433_DATA 0x00010001 +#define DDRSS0_CTL_434_DATA 0x00000101 +#define DDRSS0_CTL_435_DATA 0x02000201 +#define DDRSS0_CTL_436_DATA 0x02010000 +#define DDRSS0_CTL_437_DATA 0x00000200 +#define DDRSS0_CTL_438_DATA 0x28060000 +#define DDRSS0_CTL_439_DATA 0x00000128 +#define DDRSS0_CTL_440_DATA 0xFFFFFFFF +#define DDRSS0_CTL_441_DATA 0xFFFFFFFF +#define DDRSS0_CTL_442_DATA 0x00000000 +#define DDRSS0_CTL_443_DATA 0x00000000 +#define DDRSS0_CTL_444_DATA 0x00000000 +#define DDRSS0_CTL_445_DATA 0x00000000 +#define DDRSS0_CTL_446_DATA 0x00000000 +#define DDRSS0_CTL_447_DATA 0x00000000 +#define DDRSS0_CTL_448_DATA 0x00000000 +#define DDRSS0_CTL_449_DATA 0x00000000 +#define DDRSS0_CTL_450_DATA 0x00000000 +#define DDRSS0_CTL_451_DATA 0x00000000 +#define DDRSS0_CTL_452_DATA 0x00000000 +#define DDRSS0_CTL_453_DATA 0x00000000 +#define DDRSS0_CTL_454_DATA 0x00000000 +#define DDRSS0_CTL_455_DATA 0x00000000 +#define DDRSS0_CTL_456_DATA 0x00000000 +#define DDRSS0_CTL_457_DATA 0x00000000 +#define DDRSS0_CTL_458_DATA 0x00000000 + +#define DDRSS0_PI_00_DATA 0x00000B00 +#define DDRSS0_PI_01_DATA 0x00000000 +#define DDRSS0_PI_02_DATA 0x00000000 +#define DDRSS0_PI_03_DATA 0x00000000 +#define DDRSS0_PI_04_DATA 0x00000000 +#define DDRSS0_PI_05_DATA 0x00000101 +#define DDRSS0_PI_06_DATA 0x00640000 +#define DDRSS0_PI_07_DATA 0x00000001 +#define DDRSS0_PI_08_DATA 0x00000000 +#define DDRSS0_PI_09_DATA 0x00000000 +#define DDRSS0_PI_10_DATA 0x00000000 +#define DDRSS0_PI_11_DATA 0x00000000 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 +#define DDRSS0_PI_14_DATA 0x0800000F +#define DDRSS0_PI_15_DATA 0x00000103 +#define DDRSS0_PI_16_DATA 0x00000005 +#define DDRSS0_PI_17_DATA 0x00000000 +#define DDRSS0_PI_18_DATA 0x00000000 +#define DDRSS0_PI_19_DATA 0x00000000 +#define DDRSS0_PI_20_DATA 0x00000000 +#define DDRSS0_PI_21_DATA 0x00000000 +#define DDRSS0_PI_22_DATA 0x00000000 +#define DDRSS0_PI_23_DATA 0x00000000 +#define DDRSS0_PI_24_DATA 0x00000000 +#define DDRSS0_PI_25_DATA 0x00000000 +#define DDRSS0_PI_26_DATA 0x00010100 +#define DDRSS0_PI_27_DATA 0x00280A00 +#define DDRSS0_PI_28_DATA 0x00000000 +#define DDRSS0_PI_29_DATA 0x0F000000 +#define DDRSS0_PI_30_DATA 0x00003200 +#define DDRSS0_PI_31_DATA 0x00000000 +#define DDRSS0_PI_32_DATA 0x00000000 +#define DDRSS0_PI_33_DATA 0x01010102 +#define DDRSS0_PI_34_DATA 0x00000000 +#define DDRSS0_PI_35_DATA 0x000000AA +#define DDRSS0_PI_36_DATA 0x00000055 +#define DDRSS0_PI_37_DATA 0x000000B5 +#define DDRSS0_PI_38_DATA 0x0000004A +#define DDRSS0_PI_39_DATA 0x00000056 +#define DDRSS0_PI_40_DATA 0x000000A9 +#define DDRSS0_PI_41_DATA 0x000000A9 +#define DDRSS0_PI_42_DATA 0x000000B5 +#define DDRSS0_PI_43_DATA 0x00000000 +#define DDRSS0_PI_44_DATA 0x00000000 +#define DDRSS0_PI_45_DATA 0x000F0F00 +#define DDRSS0_PI_46_DATA 0x0000001B +#define DDRSS0_PI_47_DATA 0x000007D0 +#define DDRSS0_PI_48_DATA 0x00000300 +#define DDRSS0_PI_49_DATA 0x00000000 +#define DDRSS0_PI_50_DATA 0x00000000 +#define DDRSS0_PI_51_DATA 0x01000000 +#define DDRSS0_PI_52_DATA 0x00010101 +#define DDRSS0_PI_53_DATA 0x00000000 +#define DDRSS0_PI_54_DATA 0x00030000 +#define DDRSS0_PI_55_DATA 0x0F000000 +#define DDRSS0_PI_56_DATA 0x00000017 +#define DDRSS0_PI_57_DATA 0x00000000 +#define DDRSS0_PI_58_DATA 0x00000000 +#define DDRSS0_PI_59_DATA 0x00000000 +#define DDRSS0_PI_60_DATA 0x0A0A140A +#define DDRSS0_PI_61_DATA 0x10020201 +#define DDRSS0_PI_62_DATA 0x00020805 +#define DDRSS0_PI_63_DATA 0x01000404 +#define DDRSS0_PI_64_DATA 0x00000000 +#define DDRSS0_PI_65_DATA 0x00000000 +#define DDRSS0_PI_66_DATA 0x01000100 +#define DDRSS0_PI_67_DATA 0x0102020F +#define DDRSS0_PI_68_DATA 0x00340000 +#define DDRSS0_PI_69_DATA 0x00000000 +#define DDRSS0_PI_70_DATA 0x00000000 +#define DDRSS0_PI_71_DATA 0x0000FFFF +#define DDRSS0_PI_72_DATA 0x01000000 +#define DDRSS0_PI_73_DATA 0x00080000 +#define DDRSS0_PI_74_DATA 0x02000200 +#define DDRSS0_PI_75_DATA 0x01000100 +#define DDRSS0_PI_76_DATA 0x01000000 +#define DDRSS0_PI_77_DATA 0x02000200 +#define DDRSS0_PI_78_DATA 0x00000200 +#define DDRSS0_PI_79_DATA 0x00000000 +#define DDRSS0_PI_80_DATA 0x00000000 +#define DDRSS0_PI_81_DATA 0x00000000 +#define DDRSS0_PI_82_DATA 0x00000000 +#define DDRSS0_PI_83_DATA 0x00000000 +#define DDRSS0_PI_84_DATA 0x00000000 +#define DDRSS0_PI_85_DATA 0x00000000 +#define DDRSS0_PI_86_DATA 0x00000000 +#define DDRSS0_PI_87_DATA 0x00000000 +#define DDRSS0_PI_88_DATA 0x00000000 +#define DDRSS0_PI_89_DATA 0x00000000 +#define DDRSS0_PI_90_DATA 0x00000000 +#define DDRSS0_PI_91_DATA 0x00000400 +#define DDRSS0_PI_92_DATA 0x02010000 +#define DDRSS0_PI_93_DATA 0x00080003 +#define DDRSS0_PI_94_DATA 0x00080000 +#define DDRSS0_PI_95_DATA 0x00000001 +#define DDRSS0_PI_96_DATA 0x00000000 +#define DDRSS0_PI_97_DATA 0x0000AA00 +#define DDRSS0_PI_98_DATA 0x00000000 +#define DDRSS0_PI_99_DATA 0x00000000 +#define DDRSS0_PI_100_DATA 0x00010000 +#define DDRSS0_PI_101_DATA 0x00000000 +#define DDRSS0_PI_102_DATA 0x00000000 +#define DDRSS0_PI_103_DATA 0x00000000 +#define DDRSS0_PI_104_DATA 0x00000000 +#define DDRSS0_PI_105_DATA 0x00000000 +#define DDRSS0_PI_106_DATA 0x00000000 +#define DDRSS0_PI_107_DATA 0x00000000 +#define DDRSS0_PI_108_DATA 0x00000000 +#define DDRSS0_PI_109_DATA 0x00000000 +#define DDRSS0_PI_110_DATA 0x00000000 +#define DDRSS0_PI_111_DATA 0x00000000 +#define DDRSS0_PI_112_DATA 0x00000000 +#define DDRSS0_PI_113_DATA 0x00000000 +#define DDRSS0_PI_114_DATA 0x00000000 +#define DDRSS0_PI_115_DATA 0x00000000 +#define DDRSS0_PI_116_DATA 0x00000000 +#define DDRSS0_PI_117_DATA 0x00000000 +#define DDRSS0_PI_118_DATA 0x00000000 +#define DDRSS0_PI_119_DATA 0x00000000 +#define DDRSS0_PI_120_DATA 0x00000000 +#define DDRSS0_PI_121_DATA 0x00000000 +#define DDRSS0_PI_122_DATA 0x00000000 +#define DDRSS0_PI_123_DATA 0x00000000 +#define DDRSS0_PI_124_DATA 0x00000000 +#define DDRSS0_PI_125_DATA 0x00000008 +#define DDRSS0_PI_126_DATA 0x00000000 +#define DDRSS0_PI_127_DATA 0x00000000 +#define DDRSS0_PI_128_DATA 0x00000000 +#define DDRSS0_PI_129_DATA 0x00000000 +#define DDRSS0_PI_130_DATA 0x00000000 +#define DDRSS0_PI_131_DATA 0x00000000 +#define DDRSS0_PI_132_DATA 0x00000000 +#define DDRSS0_PI_133_DATA 0x00000000 +#define DDRSS0_PI_134_DATA 0x00000002 +#define DDRSS0_PI_135_DATA 0x00000000 +#define DDRSS0_PI_136_DATA 0x00000000 +#define DDRSS0_PI_137_DATA 0x0000000A +#define DDRSS0_PI_138_DATA 0x00000019 +#define DDRSS0_PI_139_DATA 0x00000100 +#define DDRSS0_PI_140_DATA 0x00000000 +#define DDRSS0_PI_141_DATA 0x00000000 +#define DDRSS0_PI_142_DATA 0x00000000 +#define DDRSS0_PI_143_DATA 0x00000000 +#define DDRSS0_PI_144_DATA 0x01000000 +#define DDRSS0_PI_145_DATA 0x00010003 +#define DDRSS0_PI_146_DATA 0x02000101 +#define DDRSS0_PI_147_DATA 0x01030001 +#define DDRSS0_PI_148_DATA 0x00010400 +#define DDRSS0_PI_149_DATA 0x06000105 +#define DDRSS0_PI_150_DATA 0x01070001 +#define DDRSS0_PI_151_DATA 0x00000000 +#define DDRSS0_PI_152_DATA 0x00000000 +#define DDRSS0_PI_153_DATA 0x00000000 +#define DDRSS0_PI_154_DATA 0x00010001 +#define DDRSS0_PI_155_DATA 0x00000000 +#define DDRSS0_PI_156_DATA 0x00000000 +#define DDRSS0_PI_157_DATA 0x00000000 +#define DDRSS0_PI_158_DATA 0x00000000 +#define DDRSS0_PI_159_DATA 0x00000401 +#define DDRSS0_PI_160_DATA 0x00000000 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 +#define DDRSS0_PI_164_DATA 0x00000034 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 +#define DDRSS0_PI_167_DATA 0x02000200 +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 +#define DDRSS0_PI_171_DATA 0x0000032B +#define DDRSS0_PI_172_DATA 0x00001035 +#define DDRSS0_PI_173_DATA 0x0000032B +#define DDRSS0_PI_174_DATA 0x04001035 +#define DDRSS0_PI_175_DATA 0x01010404 +#define DDRSS0_PI_176_DATA 0x00001500 +#define DDRSS0_PI_177_DATA 0x00150015 +#define DDRSS0_PI_178_DATA 0x01000100 +#define DDRSS0_PI_179_DATA 0x00000100 +#define DDRSS0_PI_180_DATA 0x00000000 +#define DDRSS0_PI_181_DATA 0x01010101 +#define DDRSS0_PI_182_DATA 0x00000000 +#define DDRSS0_PI_183_DATA 0x00000000 +#define DDRSS0_PI_184_DATA 0x00000000 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 +#define DDRSS0_PI_187_DATA 0x00040402 +#define DDRSS0_PI_188_DATA 0x000D0035 +#define DDRSS0_PI_189_DATA 0x00218049 +#define DDRSS0_PI_190_DATA 0x00218049 +#define DDRSS0_PI_191_DATA 0x01000101 +#define DDRSS0_PI_192_DATA 0x0004000E +#define DDRSS0_PI_193_DATA 0x00040216 +#define DDRSS0_PI_194_DATA 0x01000216 +#define DDRSS0_PI_195_DATA 0x000F000F +#define DDRSS0_PI_196_DATA 0x02170100 +#define DDRSS0_PI_197_DATA 0x01000217 +#define DDRSS0_PI_198_DATA 0x02170217 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B +#define DDRSS0_PI_201_DATA 0x0A070601 +#define DDRSS0_PI_202_DATA 0x1F130A0D +#define DDRSS0_PI_203_DATA 0x1F130A14 +#define DDRSS0_PI_204_DATA 0x0000C014 +#define DDRSS0_PI_205_DATA 0x00C01000 +#define DDRSS0_PI_206_DATA 0x00C01000 +#define DDRSS0_PI_207_DATA 0x00021000 +#define DDRSS0_PI_208_DATA 0x0024000E +#define DDRSS0_PI_209_DATA 0x00240216 +#define DDRSS0_PI_210_DATA 0x00110216 +#define DDRSS0_PI_211_DATA 0x32000056 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 +#define DDRSS0_PI_214_DATA 0x03013212 +#define DDRSS0_PI_215_DATA 0x00003600 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 +#define DDRSS0_PI_220_DATA 0x0A032001 +#define DDRSS0_PI_221_DATA 0x2C31110A +#define DDRSS0_PI_222_DATA 0x00002918 +#define DDRSS0_PI_223_DATA 0x6000838E +#define DDRSS0_PI_224_DATA 0x1E202008 +#define DDRSS0_PI_225_DATA 0x2C311116 +#define DDRSS0_PI_226_DATA 0x00002918 +#define DDRSS0_PI_227_DATA 0x6000838E +#define DDRSS0_PI_228_DATA 0x1E202008 +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 +#define DDRSS0_PI_235_DATA 0x033B0016 +#define DDRSS0_PI_236_DATA 0x0303033B +#define DDRSS0_PI_237_DATA 0x002AF803 +#define DDRSS0_PI_238_DATA 0x0001ADAF +#define DDRSS0_PI_239_DATA 0x00000005 +#define DDRSS0_PI_240_DATA 0x0000006E +#define DDRSS0_PI_241_DATA 0x00000016 +#define DDRSS0_PI_242_DATA 0x000681C8 +#define DDRSS0_PI_243_DATA 0x0001ADAF +#define DDRSS0_PI_244_DATA 0x00000005 +#define DDRSS0_PI_245_DATA 0x000010A9 +#define DDRSS0_PI_246_DATA 0x0000033B +#define DDRSS0_PI_247_DATA 0x000681C8 +#define DDRSS0_PI_248_DATA 0x0001ADAF +#define DDRSS0_PI_249_DATA 0x00000005 +#define DDRSS0_PI_250_DATA 0x000010A9 +#define DDRSS0_PI_251_DATA 0x0100033B +#define DDRSS0_PI_252_DATA 0x00370040 +#define DDRSS0_PI_253_DATA 0x00010008 +#define DDRSS0_PI_254_DATA 0x08550040 +#define DDRSS0_PI_255_DATA 0x00010040 +#define DDRSS0_PI_256_DATA 0x08550040 +#define DDRSS0_PI_257_DATA 0x00000340 +#define DDRSS0_PI_258_DATA 0x006B006B +#define DDRSS0_PI_259_DATA 0x08040404 +#define DDRSS0_PI_260_DATA 0x00000055 +#define DDRSS0_PI_261_DATA 0x55083C5A +#define DDRSS0_PI_262_DATA 0x5A000000 +#define DDRSS0_PI_263_DATA 0x0055083C +#define DDRSS0_PI_264_DATA 0x3C5A0000 +#define DDRSS0_PI_265_DATA 0x00005508 +#define DDRSS0_PI_266_DATA 0x0C3C5A00 +#define DDRSS0_PI_267_DATA 0x080F0E0D +#define DDRSS0_PI_268_DATA 0x000B0A09 +#define DDRSS0_PI_269_DATA 0x00030201 +#define DDRSS0_PI_270_DATA 0x01000000 +#define DDRSS0_PI_271_DATA 0x04020201 +#define DDRSS0_PI_272_DATA 0x00080804 +#define DDRSS0_PI_273_DATA 0x00000000 +#define DDRSS0_PI_274_DATA 0x00000000 +#define DDRSS0_PI_275_DATA 0x00F30084 +#define DDRSS0_PI_276_DATA 0x00160000 +#define DDRSS0_PI_277_DATA 0x36F33FF4 +#define DDRSS0_PI_278_DATA 0x00160F27 +#define DDRSS0_PI_279_DATA 0x36F33FF4 +#define DDRSS0_PI_280_DATA 0x00160F27 +#define DDRSS0_PI_281_DATA 0x00F30084 +#define DDRSS0_PI_282_DATA 0x00160000 +#define DDRSS0_PI_283_DATA 0x36F33FF4 +#define DDRSS0_PI_284_DATA 0x00160F27 +#define DDRSS0_PI_285_DATA 0x36F33FF4 +#define DDRSS0_PI_286_DATA 0x00160F27 +#define DDRSS0_PI_287_DATA 0x00F30084 +#define DDRSS0_PI_288_DATA 0x00160000 +#define DDRSS0_PI_289_DATA 0x36F33FF4 +#define DDRSS0_PI_290_DATA 0x00160F27 +#define DDRSS0_PI_291_DATA 0x36F33FF4 +#define DDRSS0_PI_292_DATA 0x00160F27 +#define DDRSS0_PI_293_DATA 0x00F30084 +#define DDRSS0_PI_294_DATA 0x00160000 +#define DDRSS0_PI_295_DATA 0x36F33FF4 +#define DDRSS0_PI_296_DATA 0x00160F27 +#define DDRSS0_PI_297_DATA 0x36F33FF4 +#define DDRSS0_PI_298_DATA 0x00160F27 +#define DDRSS0_PI_299_DATA 0x00000000 + +#define DDRSS0_PHY_00_DATA 0x000004F0 +#define DDRSS0_PHY_01_DATA 0x00000000 +#define DDRSS0_PHY_02_DATA 0x00030200 +#define DDRSS0_PHY_03_DATA 0x00000000 +#define DDRSS0_PHY_04_DATA 0x00000000 +#define DDRSS0_PHY_05_DATA 0x01030000 +#define DDRSS0_PHY_06_DATA 0x00010000 +#define DDRSS0_PHY_07_DATA 0x01030004 +#define DDRSS0_PHY_08_DATA 0x01000000 +#define DDRSS0_PHY_09_DATA 0x00000000 +#define DDRSS0_PHY_10_DATA 0x00000000 +#define DDRSS0_PHY_11_DATA 0x01000001 +#define DDRSS0_PHY_12_DATA 0x00000200 +#define DDRSS0_PHY_13_DATA 0x000800C0 +#define DDRSS0_PHY_14_DATA 0x060100CC +#define DDRSS0_PHY_15_DATA 0x00030066 +#define DDRSS0_PHY_16_DATA 0x00000000 +#define DDRSS0_PHY_17_DATA 0x00000301 +#define DDRSS0_PHY_18_DATA 0x0000AAAA +#define DDRSS0_PHY_19_DATA 0x00005555 +#define DDRSS0_PHY_20_DATA 0x0000B5B5 +#define DDRSS0_PHY_21_DATA 0x00004A4A +#define DDRSS0_PHY_22_DATA 0x00005656 +#define DDRSS0_PHY_23_DATA 0x0000A9A9 +#define DDRSS0_PHY_24_DATA 0x0000A9A9 +#define DDRSS0_PHY_25_DATA 0x0000B5B5 +#define DDRSS0_PHY_26_DATA 0x00000000 +#define DDRSS0_PHY_27_DATA 0x00000000 +#define DDRSS0_PHY_28_DATA 0x2A000000 +#define DDRSS0_PHY_29_DATA 0x00000808 +#define DDRSS0_PHY_30_DATA 0x0F000000 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002002 +#define DDRSS0_PHY_34_DATA 0x00000000 +#define DDRSS0_PHY_35_DATA 0x00000000 +#define DDRSS0_PHY_36_DATA 0x55555555 +#define DDRSS0_PHY_37_DATA 0xAAAAAAAA +#define DDRSS0_PHY_38_DATA 0x55555555 +#define DDRSS0_PHY_39_DATA 0xAAAAAAAA +#define DDRSS0_PHY_40_DATA 0x00005555 +#define DDRSS0_PHY_41_DATA 0x01000100 +#define DDRSS0_PHY_42_DATA 0x00800180 +#define DDRSS0_PHY_43_DATA 0x00000001 +#define DDRSS0_PHY_44_DATA 0x00000000 +#define DDRSS0_PHY_45_DATA 0x00000000 +#define DDRSS0_PHY_46_DATA 0x00000000 +#define DDRSS0_PHY_47_DATA 0x00000000 +#define DDRSS0_PHY_48_DATA 0x00000000 +#define DDRSS0_PHY_49_DATA 0x00000000 +#define DDRSS0_PHY_50_DATA 0x00000000 +#define DDRSS0_PHY_51_DATA 0x00000000 +#define DDRSS0_PHY_52_DATA 0x00000000 +#define DDRSS0_PHY_53_DATA 0x00000000 +#define DDRSS0_PHY_54_DATA 0x00000000 +#define DDRSS0_PHY_55_DATA 0x00000000 +#define DDRSS0_PHY_56_DATA 0x00000000 +#define DDRSS0_PHY_57_DATA 0x00000000 +#define DDRSS0_PHY_58_DATA 0x00000000 +#define DDRSS0_PHY_59_DATA 0x00000000 +#define DDRSS0_PHY_60_DATA 0x00000000 +#define DDRSS0_PHY_61_DATA 0x00000000 +#define DDRSS0_PHY_62_DATA 0x00000000 +#define DDRSS0_PHY_63_DATA 0x00000000 +#define DDRSS0_PHY_64_DATA 0x00000000 +#define DDRSS0_PHY_65_DATA 0x00000000 +#define DDRSS0_PHY_66_DATA 0x00000104 +#define DDRSS0_PHY_67_DATA 0x00000120 +#define DDRSS0_PHY_68_DATA 0x00000000 +#define DDRSS0_PHY_69_DATA 0x00000000 +#define DDRSS0_PHY_70_DATA 0x00000000 +#define DDRSS0_PHY_71_DATA 0x00000000 +#define DDRSS0_PHY_72_DATA 0x00000000 +#define DDRSS0_PHY_73_DATA 0x00000000 +#define DDRSS0_PHY_74_DATA 0x00000000 +#define DDRSS0_PHY_75_DATA 0x00000001 +#define DDRSS0_PHY_76_DATA 0x07FF0000 +#define DDRSS0_PHY_77_DATA 0x0080081F +#define DDRSS0_PHY_78_DATA 0x00081020 +#define DDRSS0_PHY_79_DATA 0x04010000 +#define DDRSS0_PHY_80_DATA 0x00000000 +#define DDRSS0_PHY_81_DATA 0x00000000 +#define DDRSS0_PHY_82_DATA 0x00000000 +#define DDRSS0_PHY_83_DATA 0x00000100 +#define DDRSS0_PHY_84_DATA 0x01CC0C01 +#define DDRSS0_PHY_85_DATA 0x1003CC0C +#define DDRSS0_PHY_86_DATA 0x20000140 +#define DDRSS0_PHY_87_DATA 0x07FF0200 +#define DDRSS0_PHY_88_DATA 0x0000DD01 +#define DDRSS0_PHY_89_DATA 0x10100303 +#define DDRSS0_PHY_90_DATA 0x10101010 +#define DDRSS0_PHY_91_DATA 0x10101010 +#define DDRSS0_PHY_92_DATA 0x00021010 +#define DDRSS0_PHY_93_DATA 0x00100010 +#define DDRSS0_PHY_94_DATA 0x00100010 +#define DDRSS0_PHY_95_DATA 0x00100010 +#define DDRSS0_PHY_96_DATA 0x00100010 +#define DDRSS0_PHY_97_DATA 0x00050010 +#define DDRSS0_PHY_98_DATA 0x51517041 +#define DDRSS0_PHY_99_DATA 0x31C06001 +#define DDRSS0_PHY_100_DATA 0x07AB01AB +#define DDRSS0_PHY_101_DATA 0x00C0C001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 +#define DDRSS0_PHY_103_DATA 0x10001000 +#define DDRSS0_PHY_104_DATA 0x0C083E42 +#define DDRSS0_PHY_105_DATA 0x0F0C3701 +#define DDRSS0_PHY_106_DATA 0x01000140 +#define DDRSS0_PHY_107_DATA 0x0C000420 +#define DDRSS0_PHY_108_DATA 0x00000198 +#define DDRSS0_PHY_109_DATA 0x0A0000D0 +#define DDRSS0_PHY_110_DATA 0x00030200 +#define DDRSS0_PHY_111_DATA 0x02800000 +#define DDRSS0_PHY_112_DATA 0x80800000 +#define DDRSS0_PHY_113_DATA 0x000E2010 +#define DDRSS0_PHY_114_DATA 0x76543210 +#define DDRSS0_PHY_115_DATA 0x00000008 +#define DDRSS0_PHY_116_DATA 0x02800280 +#define DDRSS0_PHY_117_DATA 0x02800280 +#define DDRSS0_PHY_118_DATA 0x02800280 +#define DDRSS0_PHY_119_DATA 0x02800280 +#define DDRSS0_PHY_120_DATA 0x00000280 +#define DDRSS0_PHY_121_DATA 0x0000A000 +#define DDRSS0_PHY_122_DATA 0x00A000A0 +#define DDRSS0_PHY_123_DATA 0x00A000A0 +#define DDRSS0_PHY_124_DATA 0x00A000A0 +#define DDRSS0_PHY_125_DATA 0x00A000A0 +#define DDRSS0_PHY_126_DATA 0x00A000A0 +#define DDRSS0_PHY_127_DATA 0x00A000A0 +#define DDRSS0_PHY_128_DATA 0x00A000A0 +#define DDRSS0_PHY_129_DATA 0x00A000A0 +#define DDRSS0_PHY_130_DATA 0x01C200A0 +#define DDRSS0_PHY_131_DATA 0x01A00005 +#define DDRSS0_PHY_132_DATA 0x00000000 +#define DDRSS0_PHY_133_DATA 0x00000000 +#define DDRSS0_PHY_134_DATA 0x00080200 +#define DDRSS0_PHY_135_DATA 0x00000000 +#define DDRSS0_PHY_136_DATA 0x20202020 +#define DDRSS0_PHY_137_DATA 0x20202020 +#define DDRSS0_PHY_138_DATA 0xF0F02020 +#define DDRSS0_PHY_139_DATA 0x00000000 +#define DDRSS0_PHY_140_DATA 0x00000000 +#define DDRSS0_PHY_141_DATA 0x00000000 +#define DDRSS0_PHY_142_DATA 0x00000000 +#define DDRSS0_PHY_143_DATA 0x00000000 +#define DDRSS0_PHY_144_DATA 0x00000000 +#define DDRSS0_PHY_145_DATA 0x00000000 +#define DDRSS0_PHY_146_DATA 0x00000000 +#define DDRSS0_PHY_147_DATA 0x00000000 +#define DDRSS0_PHY_148_DATA 0x00000000 +#define DDRSS0_PHY_149_DATA 0x00000000 +#define DDRSS0_PHY_150_DATA 0x00000000 +#define DDRSS0_PHY_151_DATA 0x00000000 +#define DDRSS0_PHY_152_DATA 0x00000000 +#define DDRSS0_PHY_153_DATA 0x00000000 +#define DDRSS0_PHY_154_DATA 0x00000000 +#define DDRSS0_PHY_155_DATA 0x00000000 +#define DDRSS0_PHY_156_DATA 0x00000000 +#define DDRSS0_PHY_157_DATA 0x00000000 +#define DDRSS0_PHY_158_DATA 0x00000000 +#define DDRSS0_PHY_159_DATA 0x00000000 +#define DDRSS0_PHY_160_DATA 0x00000000 +#define DDRSS0_PHY_161_DATA 0x00000000 +#define DDRSS0_PHY_162_DATA 0x00000000 +#define DDRSS0_PHY_163_DATA 0x00000000 +#define DDRSS0_PHY_164_DATA 0x00000000 +#define DDRSS0_PHY_165_DATA 0x00000000 +#define DDRSS0_PHY_166_DATA 0x00000000 +#define DDRSS0_PHY_167_DATA 0x00000000 +#define DDRSS0_PHY_168_DATA 0x00000000 +#define DDRSS0_PHY_169_DATA 0x00000000 +#define DDRSS0_PHY_170_DATA 0x00000000 +#define DDRSS0_PHY_171_DATA 0x00000000 +#define DDRSS0_PHY_172_DATA 0x00000000 +#define DDRSS0_PHY_173_DATA 0x00000000 +#define DDRSS0_PHY_174_DATA 0x00000000 +#define DDRSS0_PHY_175_DATA 0x00000000 +#define DDRSS0_PHY_176_DATA 0x00000000 +#define DDRSS0_PHY_177_DATA 0x00000000 +#define DDRSS0_PHY_178_DATA 0x00000000 +#define DDRSS0_PHY_179_DATA 0x00000000 +#define DDRSS0_PHY_180_DATA 0x00000000 +#define DDRSS0_PHY_181_DATA 0x00000000 +#define DDRSS0_PHY_182_DATA 0x00000000 +#define DDRSS0_PHY_183_DATA 0x00000000 +#define DDRSS0_PHY_184_DATA 0x00000000 +#define DDRSS0_PHY_185_DATA 0x00000000 +#define DDRSS0_PHY_186_DATA 0x00000000 +#define DDRSS0_PHY_187_DATA 0x00000000 +#define DDRSS0_PHY_188_DATA 0x00000000 +#define DDRSS0_PHY_189_DATA 0x00000000 +#define DDRSS0_PHY_190_DATA 0x00000000 +#define DDRSS0_PHY_191_DATA 0x00000000 +#define DDRSS0_PHY_192_DATA 0x00000000 +#define DDRSS0_PHY_193_DATA 0x00000000 +#define DDRSS0_PHY_194_DATA 0x00000000 +#define DDRSS0_PHY_195_DATA 0x00000000 +#define DDRSS0_PHY_196_DATA 0x00000000 +#define DDRSS0_PHY_197_DATA 0x00000000 +#define DDRSS0_PHY_198_DATA 0x00000000 +#define DDRSS0_PHY_199_DATA 0x00000000 +#define DDRSS0_PHY_200_DATA 0x00000000 +#define DDRSS0_PHY_201_DATA 0x00000000 +#define DDRSS0_PHY_202_DATA 0x00000000 +#define DDRSS0_PHY_203_DATA 0x00000000 +#define DDRSS0_PHY_204_DATA 0x00000000 +#define DDRSS0_PHY_205_DATA 0x00000000 +#define DDRSS0_PHY_206_DATA 0x00000000 +#define DDRSS0_PHY_207_DATA 0x00000000 +#define DDRSS0_PHY_208_DATA 0x00000000 +#define DDRSS0_PHY_209_DATA 0x00000000 +#define DDRSS0_PHY_210_DATA 0x00000000 +#define DDRSS0_PHY_211_DATA 0x00000000 +#define DDRSS0_PHY_212_DATA 0x00000000 +#define DDRSS0_PHY_213_DATA 0x00000000 +#define DDRSS0_PHY_214_DATA 0x00000000 +#define DDRSS0_PHY_215_DATA 0x00000000 +#define DDRSS0_PHY_216_DATA 0x00000000 +#define DDRSS0_PHY_217_DATA 0x00000000 +#define DDRSS0_PHY_218_DATA 0x00000000 +#define DDRSS0_PHY_219_DATA 0x00000000 +#define DDRSS0_PHY_220_DATA 0x00000000 +#define DDRSS0_PHY_221_DATA 0x00000000 +#define DDRSS0_PHY_222_DATA 0x00000000 +#define DDRSS0_PHY_223_DATA 0x00000000 +#define DDRSS0_PHY_224_DATA 0x00000000 +#define DDRSS0_PHY_225_DATA 0x00000000 +#define DDRSS0_PHY_226_DATA 0x00000000 +#define DDRSS0_PHY_227_DATA 0x00000000 +#define DDRSS0_PHY_228_DATA 0x00000000 +#define DDRSS0_PHY_229_DATA 0x00000000 +#define DDRSS0_PHY_230_DATA 0x00000000 +#define DDRSS0_PHY_231_DATA 0x00000000 +#define DDRSS0_PHY_232_DATA 0x00000000 +#define DDRSS0_PHY_233_DATA 0x00000000 +#define DDRSS0_PHY_234_DATA 0x00000000 +#define DDRSS0_PHY_235_DATA 0x00000000 +#define DDRSS0_PHY_236_DATA 0x00000000 +#define DDRSS0_PHY_237_DATA 0x00000000 +#define DDRSS0_PHY_238_DATA 0x00000000 +#define DDRSS0_PHY_239_DATA 0x00000000 +#define DDRSS0_PHY_240_DATA 0x00000000 +#define DDRSS0_PHY_241_DATA 0x00000000 +#define DDRSS0_PHY_242_DATA 0x00000000 +#define DDRSS0_PHY_243_DATA 0x00000000 +#define DDRSS0_PHY_244_DATA 0x00000000 +#define DDRSS0_PHY_245_DATA 0x00000000 +#define DDRSS0_PHY_246_DATA 0x00000000 +#define DDRSS0_PHY_247_DATA 0x00000000 +#define DDRSS0_PHY_248_DATA 0x00000000 +#define DDRSS0_PHY_249_DATA 0x00000000 +#define DDRSS0_PHY_250_DATA 0x00000000 +#define DDRSS0_PHY_251_DATA 0x00000000 +#define DDRSS0_PHY_252_DATA 0x00000000 +#define DDRSS0_PHY_253_DATA 0x00000000 +#define DDRSS0_PHY_254_DATA 0x00000000 +#define DDRSS0_PHY_255_DATA 0x00000000 +#define DDRSS0_PHY_256_DATA 0x000004F0 +#define DDRSS0_PHY_257_DATA 0x00000000 +#define DDRSS0_PHY_258_DATA 0x00030200 +#define DDRSS0_PHY_259_DATA 0x00000000 +#define DDRSS0_PHY_260_DATA 0x00000000 +#define DDRSS0_PHY_261_DATA 0x01030000 +#define DDRSS0_PHY_262_DATA 0x00010000 +#define DDRSS0_PHY_263_DATA 0x01030004 +#define DDRSS0_PHY_264_DATA 0x01000000 +#define DDRSS0_PHY_265_DATA 0x00000000 +#define DDRSS0_PHY_266_DATA 0x00000000 +#define DDRSS0_PHY_267_DATA 0x01000001 +#define DDRSS0_PHY_268_DATA 0x00000200 +#define DDRSS0_PHY_269_DATA 0x000800C0 +#define DDRSS0_PHY_270_DATA 0x060100CC +#define DDRSS0_PHY_271_DATA 0x00030066 +#define DDRSS0_PHY_272_DATA 0x00000000 +#define DDRSS0_PHY_273_DATA 0x00000301 +#define DDRSS0_PHY_274_DATA 0x0000AAAA +#define DDRSS0_PHY_275_DATA 0x00005555 +#define DDRSS0_PHY_276_DATA 0x0000B5B5 +#define DDRSS0_PHY_277_DATA 0x00004A4A +#define DDRSS0_PHY_278_DATA 0x00005656 +#define DDRSS0_PHY_279_DATA 0x0000A9A9 +#define DDRSS0_PHY_280_DATA 0x0000A9A9 +#define DDRSS0_PHY_281_DATA 0x0000B5B5 +#define DDRSS0_PHY_282_DATA 0x00000000 +#define DDRSS0_PHY_283_DATA 0x00000000 +#define DDRSS0_PHY_284_DATA 0x2A000000 +#define DDRSS0_PHY_285_DATA 0x00000808 +#define DDRSS0_PHY_286_DATA 0x0F000000 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002002 +#define DDRSS0_PHY_290_DATA 0x00000000 +#define DDRSS0_PHY_291_DATA 0x00000000 +#define DDRSS0_PHY_292_DATA 0x55555555 +#define DDRSS0_PHY_293_DATA 0xAAAAAAAA +#define DDRSS0_PHY_294_DATA 0x55555555 +#define DDRSS0_PHY_295_DATA 0xAAAAAAAA +#define DDRSS0_PHY_296_DATA 0x00005555 +#define DDRSS0_PHY_297_DATA 0x01000100 +#define DDRSS0_PHY_298_DATA 0x00800180 +#define DDRSS0_PHY_299_DATA 0x00000000 +#define DDRSS0_PHY_300_DATA 0x00000000 +#define DDRSS0_PHY_301_DATA 0x00000000 +#define DDRSS0_PHY_302_DATA 0x00000000 +#define DDRSS0_PHY_303_DATA 0x00000000 +#define DDRSS0_PHY_304_DATA 0x00000000 +#define DDRSS0_PHY_305_DATA 0x00000000 +#define DDRSS0_PHY_306_DATA 0x00000000 +#define DDRSS0_PHY_307_DATA 0x00000000 +#define DDRSS0_PHY_308_DATA 0x00000000 +#define DDRSS0_PHY_309_DATA 0x00000000 +#define DDRSS0_PHY_310_DATA 0x00000000 +#define DDRSS0_PHY_311_DATA 0x00000000 +#define DDRSS0_PHY_312_DATA 0x00000000 +#define DDRSS0_PHY_313_DATA 0x00000000 +#define DDRSS0_PHY_314_DATA 0x00000000 +#define DDRSS0_PHY_315_DATA 0x00000000 +#define DDRSS0_PHY_316_DATA 0x00000000 +#define DDRSS0_PHY_317_DATA 0x00000000 +#define DDRSS0_PHY_318_DATA 0x00000000 +#define DDRSS0_PHY_319_DATA 0x00000000 +#define DDRSS0_PHY_320_DATA 0x00000000 +#define DDRSS0_PHY_321_DATA 0x00000000 +#define DDRSS0_PHY_322_DATA 0x00000104 +#define DDRSS0_PHY_323_DATA 0x00000120 +#define DDRSS0_PHY_324_DATA 0x00000000 +#define DDRSS0_PHY_325_DATA 0x00000000 +#define DDRSS0_PHY_326_DATA 0x00000000 +#define DDRSS0_PHY_327_DATA 0x00000000 +#define DDRSS0_PHY_328_DATA 0x00000000 +#define DDRSS0_PHY_329_DATA 0x00000000 +#define DDRSS0_PHY_330_DATA 0x00000000 +#define DDRSS0_PHY_331_DATA 0x00000001 +#define DDRSS0_PHY_332_DATA 0x07FF0000 +#define DDRSS0_PHY_333_DATA 0x0080081F +#define DDRSS0_PHY_334_DATA 0x00081020 +#define DDRSS0_PHY_335_DATA 0x04010000 +#define DDRSS0_PHY_336_DATA 0x00000000 +#define DDRSS0_PHY_337_DATA 0x00000000 +#define DDRSS0_PHY_338_DATA 0x00000000 +#define DDRSS0_PHY_339_DATA 0x00000100 +#define DDRSS0_PHY_340_DATA 0x01CC0C01 +#define DDRSS0_PHY_341_DATA 0x1003CC0C +#define DDRSS0_PHY_342_DATA 0x20000140 +#define DDRSS0_PHY_343_DATA 0x07FF0200 +#define DDRSS0_PHY_344_DATA 0x0000DD01 +#define DDRSS0_PHY_345_DATA 0x10100303 +#define DDRSS0_PHY_346_DATA 0x10101010 +#define DDRSS0_PHY_347_DATA 0x10101010 +#define DDRSS0_PHY_348_DATA 0x00021010 +#define DDRSS0_PHY_349_DATA 0x00100010 +#define DDRSS0_PHY_350_DATA 0x00100010 +#define DDRSS0_PHY_351_DATA 0x00100010 +#define DDRSS0_PHY_352_DATA 0x00100010 +#define DDRSS0_PHY_353_DATA 0x00050010 +#define DDRSS0_PHY_354_DATA 0x51517041 +#define DDRSS0_PHY_355_DATA 0x31C06001 +#define DDRSS0_PHY_356_DATA 0x07AB01AB +#define DDRSS0_PHY_357_DATA 0x00C0C001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 +#define DDRSS0_PHY_359_DATA 0x10001000 +#define DDRSS0_PHY_360_DATA 0x0C083E42 +#define DDRSS0_PHY_361_DATA 0x0F0C3701 +#define DDRSS0_PHY_362_DATA 0x01000140 +#define DDRSS0_PHY_363_DATA 0x0C000420 +#define DDRSS0_PHY_364_DATA 0x00000198 +#define DDRSS0_PHY_365_DATA 0x0A0000D0 +#define DDRSS0_PHY_366_DATA 0x00030200 +#define DDRSS0_PHY_367_DATA 0x02800000 +#define DDRSS0_PHY_368_DATA 0x80800000 +#define DDRSS0_PHY_369_DATA 0x000E2010 +#define DDRSS0_PHY_370_DATA 0x76543210 +#define DDRSS0_PHY_371_DATA 0x00000008 +#define DDRSS0_PHY_372_DATA 0x02800280 +#define DDRSS0_PHY_373_DATA 0x02800280 +#define DDRSS0_PHY_374_DATA 0x02800280 +#define DDRSS0_PHY_375_DATA 0x02800280 +#define DDRSS0_PHY_376_DATA 0x00000280 +#define DDRSS0_PHY_377_DATA 0x0000A000 +#define DDRSS0_PHY_378_DATA 0x00A000A0 +#define DDRSS0_PHY_379_DATA 0x00A000A0 +#define DDRSS0_PHY_380_DATA 0x00A000A0 +#define DDRSS0_PHY_381_DATA 0x00A000A0 +#define DDRSS0_PHY_382_DATA 0x00A000A0 +#define DDRSS0_PHY_383_DATA 0x00A000A0 +#define DDRSS0_PHY_384_DATA 0x00A000A0 +#define DDRSS0_PHY_385_DATA 0x00A000A0 +#define DDRSS0_PHY_386_DATA 0x01C200A0 +#define DDRSS0_PHY_387_DATA 0x01A00005 +#define DDRSS0_PHY_388_DATA 0x00000000 +#define DDRSS0_PHY_389_DATA 0x00000000 +#define DDRSS0_PHY_390_DATA 0x00080200 +#define DDRSS0_PHY_391_DATA 0x00000000 +#define DDRSS0_PHY_392_DATA 0x20202020 +#define DDRSS0_PHY_393_DATA 0x20202020 +#define DDRSS0_PHY_394_DATA 0xF0F02020 +#define DDRSS0_PHY_395_DATA 0x00000000 +#define DDRSS0_PHY_396_DATA 0x00000000 +#define DDRSS0_PHY_397_DATA 0x00000000 +#define DDRSS0_PHY_398_DATA 0x00000000 +#define DDRSS0_PHY_399_DATA 0x00000000 +#define DDRSS0_PHY_400_DATA 0x00000000 +#define DDRSS0_PHY_401_DATA 0x00000000 +#define DDRSS0_PHY_402_DATA 0x00000000 +#define DDRSS0_PHY_403_DATA 0x00000000 +#define DDRSS0_PHY_404_DATA 0x00000000 +#define DDRSS0_PHY_405_DATA 0x00000000 +#define DDRSS0_PHY_406_DATA 0x00000000 +#define DDRSS0_PHY_407_DATA 0x00000000 +#define DDRSS0_PHY_408_DATA 0x00000000 +#define DDRSS0_PHY_409_DATA 0x00000000 +#define DDRSS0_PHY_410_DATA 0x00000000 +#define DDRSS0_PHY_411_DATA 0x00000000 +#define DDRSS0_PHY_412_DATA 0x00000000 +#define DDRSS0_PHY_413_DATA 0x00000000 +#define DDRSS0_PHY_414_DATA 0x00000000 +#define DDRSS0_PHY_415_DATA 0x00000000 +#define DDRSS0_PHY_416_DATA 0x00000000 +#define DDRSS0_PHY_417_DATA 0x00000000 +#define DDRSS0_PHY_418_DATA 0x00000000 +#define DDRSS0_PHY_419_DATA 0x00000000 +#define DDRSS0_PHY_420_DATA 0x00000000 +#define DDRSS0_PHY_421_DATA 0x00000000 +#define DDRSS0_PHY_422_DATA 0x00000000 +#define DDRSS0_PHY_423_DATA 0x00000000 +#define DDRSS0_PHY_424_DATA 0x00000000 +#define DDRSS0_PHY_425_DATA 0x00000000 +#define DDRSS0_PHY_426_DATA 0x00000000 +#define DDRSS0_PHY_427_DATA 0x00000000 +#define DDRSS0_PHY_428_DATA 0x00000000 +#define DDRSS0_PHY_429_DATA 0x00000000 +#define DDRSS0_PHY_430_DATA 0x00000000 +#define DDRSS0_PHY_431_DATA 0x00000000 +#define DDRSS0_PHY_432_DATA 0x00000000 +#define DDRSS0_PHY_433_DATA 0x00000000 +#define DDRSS0_PHY_434_DATA 0x00000000 +#define DDRSS0_PHY_435_DATA 0x00000000 +#define DDRSS0_PHY_436_DATA 0x00000000 +#define DDRSS0_PHY_437_DATA 0x00000000 +#define DDRSS0_PHY_438_DATA 0x00000000 +#define DDRSS0_PHY_439_DATA 0x00000000 +#define DDRSS0_PHY_440_DATA 0x00000000 +#define DDRSS0_PHY_441_DATA 0x00000000 +#define DDRSS0_PHY_442_DATA 0x00000000 +#define DDRSS0_PHY_443_DATA 0x00000000 +#define DDRSS0_PHY_444_DATA 0x00000000 +#define DDRSS0_PHY_445_DATA 0x00000000 +#define DDRSS0_PHY_446_DATA 0x00000000 +#define DDRSS0_PHY_447_DATA 0x00000000 +#define DDRSS0_PHY_448_DATA 0x00000000 +#define DDRSS0_PHY_449_DATA 0x00000000 +#define DDRSS0_PHY_450_DATA 0x00000000 +#define DDRSS0_PHY_451_DATA 0x00000000 +#define DDRSS0_PHY_452_DATA 0x00000000 +#define DDRSS0_PHY_453_DATA 0x00000000 +#define DDRSS0_PHY_454_DATA 0x00000000 +#define DDRSS0_PHY_455_DATA 0x00000000 +#define DDRSS0_PHY_456_DATA 0x00000000 +#define DDRSS0_PHY_457_DATA 0x00000000 +#define DDRSS0_PHY_458_DATA 0x00000000 +#define DDRSS0_PHY_459_DATA 0x00000000 +#define DDRSS0_PHY_460_DATA 0x00000000 +#define DDRSS0_PHY_461_DATA 0x00000000 +#define DDRSS0_PHY_462_DATA 0x00000000 +#define DDRSS0_PHY_463_DATA 0x00000000 +#define DDRSS0_PHY_464_DATA 0x00000000 +#define DDRSS0_PHY_465_DATA 0x00000000 +#define DDRSS0_PHY_466_DATA 0x00000000 +#define DDRSS0_PHY_467_DATA 0x00000000 +#define DDRSS0_PHY_468_DATA 0x00000000 +#define DDRSS0_PHY_469_DATA 0x00000000 +#define DDRSS0_PHY_470_DATA 0x00000000 +#define DDRSS0_PHY_471_DATA 0x00000000 +#define DDRSS0_PHY_472_DATA 0x00000000 +#define DDRSS0_PHY_473_DATA 0x00000000 +#define DDRSS0_PHY_474_DATA 0x00000000 +#define DDRSS0_PHY_475_DATA 0x00000000 +#define DDRSS0_PHY_476_DATA 0x00000000 +#define DDRSS0_PHY_477_DATA 0x00000000 +#define DDRSS0_PHY_478_DATA 0x00000000 +#define DDRSS0_PHY_479_DATA 0x00000000 +#define DDRSS0_PHY_480_DATA 0x00000000 +#define DDRSS0_PHY_481_DATA 0x00000000 +#define DDRSS0_PHY_482_DATA 0x00000000 +#define DDRSS0_PHY_483_DATA 0x00000000 +#define DDRSS0_PHY_484_DATA 0x00000000 +#define DDRSS0_PHY_485_DATA 0x00000000 +#define DDRSS0_PHY_486_DATA 0x00000000 +#define DDRSS0_PHY_487_DATA 0x00000000 +#define DDRSS0_PHY_488_DATA 0x00000000 +#define DDRSS0_PHY_489_DATA 0x00000000 +#define DDRSS0_PHY_490_DATA 0x00000000 +#define DDRSS0_PHY_491_DATA 0x00000000 +#define DDRSS0_PHY_492_DATA 0x00000000 +#define DDRSS0_PHY_493_DATA 0x00000000 +#define DDRSS0_PHY_494_DATA 0x00000000 +#define DDRSS0_PHY_495_DATA 0x00000000 +#define DDRSS0_PHY_496_DATA 0x00000000 +#define DDRSS0_PHY_497_DATA 0x00000000 +#define DDRSS0_PHY_498_DATA 0x00000000 +#define DDRSS0_PHY_499_DATA 0x00000000 +#define DDRSS0_PHY_500_DATA 0x00000000 +#define DDRSS0_PHY_501_DATA 0x00000000 +#define DDRSS0_PHY_502_DATA 0x00000000 +#define DDRSS0_PHY_503_DATA 0x00000000 +#define DDRSS0_PHY_504_DATA 0x00000000 +#define DDRSS0_PHY_505_DATA 0x00000000 +#define DDRSS0_PHY_506_DATA 0x00000000 +#define DDRSS0_PHY_507_DATA 0x00000000 +#define DDRSS0_PHY_508_DATA 0x00000000 +#define DDRSS0_PHY_509_DATA 0x00000000 +#define DDRSS0_PHY_510_DATA 0x00000000 +#define DDRSS0_PHY_511_DATA 0x00000000 +#define DDRSS0_PHY_512_DATA 0x000004F0 +#define DDRSS0_PHY_513_DATA 0x00000000 +#define DDRSS0_PHY_514_DATA 0x00030200 +#define DDRSS0_PHY_515_DATA 0x00000000 +#define DDRSS0_PHY_516_DATA 0x00000000 +#define DDRSS0_PHY_517_DATA 0x01030000 +#define DDRSS0_PHY_518_DATA 0x00010000 +#define DDRSS0_PHY_519_DATA 0x01030004 +#define DDRSS0_PHY_520_DATA 0x01000000 +#define DDRSS0_PHY_521_DATA 0x00000000 +#define DDRSS0_PHY_522_DATA 0x00000000 +#define DDRSS0_PHY_523_DATA 0x01000001 +#define DDRSS0_PHY_524_DATA 0x00000200 +#define DDRSS0_PHY_525_DATA 0x000800C0 +#define DDRSS0_PHY_526_DATA 0x060100CC +#define DDRSS0_PHY_527_DATA 0x00030066 +#define DDRSS0_PHY_528_DATA 0x00000000 +#define DDRSS0_PHY_529_DATA 0x00000301 +#define DDRSS0_PHY_530_DATA 0x0000AAAA +#define DDRSS0_PHY_531_DATA 0x00005555 +#define DDRSS0_PHY_532_DATA 0x0000B5B5 +#define DDRSS0_PHY_533_DATA 0x00004A4A +#define DDRSS0_PHY_534_DATA 0x00005656 +#define DDRSS0_PHY_535_DATA 0x0000A9A9 +#define DDRSS0_PHY_536_DATA 0x0000A9A9 +#define DDRSS0_PHY_537_DATA 0x0000B5B5 +#define DDRSS0_PHY_538_DATA 0x00000000 +#define DDRSS0_PHY_539_DATA 0x00000000 +#define DDRSS0_PHY_540_DATA 0x2A000000 +#define DDRSS0_PHY_541_DATA 0x00000808 +#define DDRSS0_PHY_542_DATA 0x0F000000 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002002 +#define DDRSS0_PHY_546_DATA 0x00000000 +#define DDRSS0_PHY_547_DATA 0x00000000 +#define DDRSS0_PHY_548_DATA 0x55555555 +#define DDRSS0_PHY_549_DATA 0xAAAAAAAA +#define DDRSS0_PHY_550_DATA 0x55555555 +#define DDRSS0_PHY_551_DATA 0xAAAAAAAA +#define DDRSS0_PHY_552_DATA 0x00005555 +#define DDRSS0_PHY_553_DATA 0x01000100 +#define DDRSS0_PHY_554_DATA 0x00800180 +#define DDRSS0_PHY_555_DATA 0x00000001 +#define DDRSS0_PHY_556_DATA 0x00000000 +#define DDRSS0_PHY_557_DATA 0x00000000 +#define DDRSS0_PHY_558_DATA 0x00000000 +#define DDRSS0_PHY_559_DATA 0x00000000 +#define DDRSS0_PHY_560_DATA 0x00000000 +#define DDRSS0_PHY_561_DATA 0x00000000 +#define DDRSS0_PHY_562_DATA 0x00000000 +#define DDRSS0_PHY_563_DATA 0x00000000 +#define DDRSS0_PHY_564_DATA 0x00000000 +#define DDRSS0_PHY_565_DATA 0x00000000 +#define DDRSS0_PHY_566_DATA 0x00000000 +#define DDRSS0_PHY_567_DATA 0x00000000 +#define DDRSS0_PHY_568_DATA 0x00000000 +#define DDRSS0_PHY_569_DATA 0x00000000 +#define DDRSS0_PHY_570_DATA 0x00000000 +#define DDRSS0_PHY_571_DATA 0x00000000 +#define DDRSS0_PHY_572_DATA 0x00000000 +#define DDRSS0_PHY_573_DATA 0x00000000 +#define DDRSS0_PHY_574_DATA 0x00000000 +#define DDRSS0_PHY_575_DATA 0x00000000 +#define DDRSS0_PHY_576_DATA 0x00000000 +#define DDRSS0_PHY_577_DATA 0x00000000 +#define DDRSS0_PHY_578_DATA 0x00000104 +#define DDRSS0_PHY_579_DATA 0x00000120 +#define DDRSS0_PHY_580_DATA 0x00000000 +#define DDRSS0_PHY_581_DATA 0x00000000 +#define DDRSS0_PHY_582_DATA 0x00000000 +#define DDRSS0_PHY_583_DATA 0x00000000 +#define DDRSS0_PHY_584_DATA 0x00000000 +#define DDRSS0_PHY_585_DATA 0x00000000 +#define DDRSS0_PHY_586_DATA 0x00000000 +#define DDRSS0_PHY_587_DATA 0x00000001 +#define DDRSS0_PHY_588_DATA 0x07FF0000 +#define DDRSS0_PHY_589_DATA 0x0080081F +#define DDRSS0_PHY_590_DATA 0x00081020 +#define DDRSS0_PHY_591_DATA 0x04010000 +#define DDRSS0_PHY_592_DATA 0x00000000 +#define DDRSS0_PHY_593_DATA 0x00000000 +#define DDRSS0_PHY_594_DATA 0x00000000 +#define DDRSS0_PHY_595_DATA 0x00000100 +#define DDRSS0_PHY_596_DATA 0x01CC0C01 +#define DDRSS0_PHY_597_DATA 0x1003CC0C +#define DDRSS0_PHY_598_DATA 0x20000140 +#define DDRSS0_PHY_599_DATA 0x07FF0200 +#define DDRSS0_PHY_600_DATA 0x0000DD01 +#define DDRSS0_PHY_601_DATA 0x10100303 +#define DDRSS0_PHY_602_DATA 0x10101010 +#define DDRSS0_PHY_603_DATA 0x10101010 +#define DDRSS0_PHY_604_DATA 0x00021010 +#define DDRSS0_PHY_605_DATA 0x00100010 +#define DDRSS0_PHY_606_DATA 0x00100010 +#define DDRSS0_PHY_607_DATA 0x00100010 +#define DDRSS0_PHY_608_DATA 0x00100010 +#define DDRSS0_PHY_609_DATA 0x00050010 +#define DDRSS0_PHY_610_DATA 0x51517041 +#define DDRSS0_PHY_611_DATA 0x31C06001 +#define DDRSS0_PHY_612_DATA 0x07AB01AB +#define DDRSS0_PHY_613_DATA 0x00C0C001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 +#define DDRSS0_PHY_615_DATA 0x10001000 +#define DDRSS0_PHY_616_DATA 0x0C083E42 +#define DDRSS0_PHY_617_DATA 0x0F0C3701 +#define DDRSS0_PHY_618_DATA 0x01000140 +#define DDRSS0_PHY_619_DATA 0x0C000420 +#define DDRSS0_PHY_620_DATA 0x00000198 +#define DDRSS0_PHY_621_DATA 0x0A0000D0 +#define DDRSS0_PHY_622_DATA 0x00030200 +#define DDRSS0_PHY_623_DATA 0x02800000 +#define DDRSS0_PHY_624_DATA 0x80800000 +#define DDRSS0_PHY_625_DATA 0x000E2010 +#define DDRSS0_PHY_626_DATA 0x76543210 +#define DDRSS0_PHY_627_DATA 0x00000008 +#define DDRSS0_PHY_628_DATA 0x02800280 +#define DDRSS0_PHY_629_DATA 0x02800280 +#define DDRSS0_PHY_630_DATA 0x02800280 +#define DDRSS0_PHY_631_DATA 0x02800280 +#define DDRSS0_PHY_632_DATA 0x00000280 +#define DDRSS0_PHY_633_DATA 0x0000A000 +#define DDRSS0_PHY_634_DATA 0x00A000A0 +#define DDRSS0_PHY_635_DATA 0x00A000A0 +#define DDRSS0_PHY_636_DATA 0x00A000A0 +#define DDRSS0_PHY_637_DATA 0x00A000A0 +#define DDRSS0_PHY_638_DATA 0x00A000A0 +#define DDRSS0_PHY_639_DATA 0x00A000A0 +#define DDRSS0_PHY_640_DATA 0x00A000A0 +#define DDRSS0_PHY_641_DATA 0x00A000A0 +#define DDRSS0_PHY_642_DATA 0x01C200A0 +#define DDRSS0_PHY_643_DATA 0x01A00005 +#define DDRSS0_PHY_644_DATA 0x00000000 +#define DDRSS0_PHY_645_DATA 0x00000000 +#define DDRSS0_PHY_646_DATA 0x00080200 +#define DDRSS0_PHY_647_DATA 0x00000000 +#define DDRSS0_PHY_648_DATA 0x20202020 +#define DDRSS0_PHY_649_DATA 0x20202020 +#define DDRSS0_PHY_650_DATA 0xF0F02020 +#define DDRSS0_PHY_651_DATA 0x00000000 +#define DDRSS0_PHY_652_DATA 0x00000000 +#define DDRSS0_PHY_653_DATA 0x00000000 +#define DDRSS0_PHY_654_DATA 0x00000000 +#define DDRSS0_PHY_655_DATA 0x00000000 +#define DDRSS0_PHY_656_DATA 0x00000000 +#define DDRSS0_PHY_657_DATA 0x00000000 +#define DDRSS0_PHY_658_DATA 0x00000000 +#define DDRSS0_PHY_659_DATA 0x00000000 +#define DDRSS0_PHY_660_DATA 0x00000000 +#define DDRSS0_PHY_661_DATA 0x00000000 +#define DDRSS0_PHY_662_DATA 0x00000000 +#define DDRSS0_PHY_663_DATA 0x00000000 +#define DDRSS0_PHY_664_DATA 0x00000000 +#define DDRSS0_PHY_665_DATA 0x00000000 +#define DDRSS0_PHY_666_DATA 0x00000000 +#define DDRSS0_PHY_667_DATA 0x00000000 +#define DDRSS0_PHY_668_DATA 0x00000000 +#define DDRSS0_PHY_669_DATA 0x00000000 +#define DDRSS0_PHY_670_DATA 0x00000000 +#define DDRSS0_PHY_671_DATA 0x00000000 +#define DDRSS0_PHY_672_DATA 0x00000000 +#define DDRSS0_PHY_673_DATA 0x00000000 +#define DDRSS0_PHY_674_DATA 0x00000000 +#define DDRSS0_PHY_675_DATA 0x00000000 +#define DDRSS0_PHY_676_DATA 0x00000000 +#define DDRSS0_PHY_677_DATA 0x00000000 +#define DDRSS0_PHY_678_DATA 0x00000000 +#define DDRSS0_PHY_679_DATA 0x00000000 +#define DDRSS0_PHY_680_DATA 0x00000000 +#define DDRSS0_PHY_681_DATA 0x00000000 +#define DDRSS0_PHY_682_DATA 0x00000000 +#define DDRSS0_PHY_683_DATA 0x00000000 +#define DDRSS0_PHY_684_DATA 0x00000000 +#define DDRSS0_PHY_685_DATA 0x00000000 +#define DDRSS0_PHY_686_DATA 0x00000000 +#define DDRSS0_PHY_687_DATA 0x00000000 +#define DDRSS0_PHY_688_DATA 0x00000000 +#define DDRSS0_PHY_689_DATA 0x00000000 +#define DDRSS0_PHY_690_DATA 0x00000000 +#define DDRSS0_PHY_691_DATA 0x00000000 +#define DDRSS0_PHY_692_DATA 0x00000000 +#define DDRSS0_PHY_693_DATA 0x00000000 +#define DDRSS0_PHY_694_DATA 0x00000000 +#define DDRSS0_PHY_695_DATA 0x00000000 +#define DDRSS0_PHY_696_DATA 0x00000000 +#define DDRSS0_PHY_697_DATA 0x00000000 +#define DDRSS0_PHY_698_DATA 0x00000000 +#define DDRSS0_PHY_699_DATA 0x00000000 +#define DDRSS0_PHY_700_DATA 0x00000000 +#define DDRSS0_PHY_701_DATA 0x00000000 +#define DDRSS0_PHY_702_DATA 0x00000000 +#define DDRSS0_PHY_703_DATA 0x00000000 +#define DDRSS0_PHY_704_DATA 0x00000000 +#define DDRSS0_PHY_705_DATA 0x00000000 +#define DDRSS0_PHY_706_DATA 0x00000000 +#define DDRSS0_PHY_707_DATA 0x00000000 +#define DDRSS0_PHY_708_DATA 0x00000000 +#define DDRSS0_PHY_709_DATA 0x00000000 +#define DDRSS0_PHY_710_DATA 0x00000000 +#define DDRSS0_PHY_711_DATA 0x00000000 +#define DDRSS0_PHY_712_DATA 0x00000000 +#define DDRSS0_PHY_713_DATA 0x00000000 +#define DDRSS0_PHY_714_DATA 0x00000000 +#define DDRSS0_PHY_715_DATA 0x00000000 +#define DDRSS0_PHY_716_DATA 0x00000000 +#define DDRSS0_PHY_717_DATA 0x00000000 +#define DDRSS0_PHY_718_DATA 0x00000000 +#define DDRSS0_PHY_719_DATA 0x00000000 +#define DDRSS0_PHY_720_DATA 0x00000000 +#define DDRSS0_PHY_721_DATA 0x00000000 +#define DDRSS0_PHY_722_DATA 0x00000000 +#define DDRSS0_PHY_723_DATA 0x00000000 +#define DDRSS0_PHY_724_DATA 0x00000000 +#define DDRSS0_PHY_725_DATA 0x00000000 +#define DDRSS0_PHY_726_DATA 0x00000000 +#define DDRSS0_PHY_727_DATA 0x00000000 +#define DDRSS0_PHY_728_DATA 0x00000000 +#define DDRSS0_PHY_729_DATA 0x00000000 +#define DDRSS0_PHY_730_DATA 0x00000000 +#define DDRSS0_PHY_731_DATA 0x00000000 +#define DDRSS0_PHY_732_DATA 0x00000000 +#define DDRSS0_PHY_733_DATA 0x00000000 +#define DDRSS0_PHY_734_DATA 0x00000000 +#define DDRSS0_PHY_735_DATA 0x00000000 +#define DDRSS0_PHY_736_DATA 0x00000000 +#define DDRSS0_PHY_737_DATA 0x00000000 +#define DDRSS0_PHY_738_DATA 0x00000000 +#define DDRSS0_PHY_739_DATA 0x00000000 +#define DDRSS0_PHY_740_DATA 0x00000000 +#define DDRSS0_PHY_741_DATA 0x00000000 +#define DDRSS0_PHY_742_DATA 0x00000000 +#define DDRSS0_PHY_743_DATA 0x00000000 +#define DDRSS0_PHY_744_DATA 0x00000000 +#define DDRSS0_PHY_745_DATA 0x00000000 +#define DDRSS0_PHY_746_DATA 0x00000000 +#define DDRSS0_PHY_747_DATA 0x00000000 +#define DDRSS0_PHY_748_DATA 0x00000000 +#define DDRSS0_PHY_749_DATA 0x00000000 +#define DDRSS0_PHY_750_DATA 0x00000000 +#define DDRSS0_PHY_751_DATA 0x00000000 +#define DDRSS0_PHY_752_DATA 0x00000000 +#define DDRSS0_PHY_753_DATA 0x00000000 +#define DDRSS0_PHY_754_DATA 0x00000000 +#define DDRSS0_PHY_755_DATA 0x00000000 +#define DDRSS0_PHY_756_DATA 0x00000000 +#define DDRSS0_PHY_757_DATA 0x00000000 +#define DDRSS0_PHY_758_DATA 0x00000000 +#define DDRSS0_PHY_759_DATA 0x00000000 +#define DDRSS0_PHY_760_DATA 0x00000000 +#define DDRSS0_PHY_761_DATA 0x00000000 +#define DDRSS0_PHY_762_DATA 0x00000000 +#define DDRSS0_PHY_763_DATA 0x00000000 +#define DDRSS0_PHY_764_DATA 0x00000000 +#define DDRSS0_PHY_765_DATA 0x00000000 +#define DDRSS0_PHY_766_DATA 0x00000000 +#define DDRSS0_PHY_767_DATA 0x00000000 +#define DDRSS0_PHY_768_DATA 0x000004F0 +#define DDRSS0_PHY_769_DATA 0x00000000 +#define DDRSS0_PHY_770_DATA 0x00030200 +#define DDRSS0_PHY_771_DATA 0x00000000 +#define DDRSS0_PHY_772_DATA 0x00000000 +#define DDRSS0_PHY_773_DATA 0x01030000 +#define DDRSS0_PHY_774_DATA 0x00010000 +#define DDRSS0_PHY_775_DATA 0x01030004 +#define DDRSS0_PHY_776_DATA 0x01000000 +#define DDRSS0_PHY_777_DATA 0x00000000 +#define DDRSS0_PHY_778_DATA 0x00000000 +#define DDRSS0_PHY_779_DATA 0x01000001 +#define DDRSS0_PHY_780_DATA 0x00000200 +#define DDRSS0_PHY_781_DATA 0x000800C0 +#define DDRSS0_PHY_782_DATA 0x060100CC +#define DDRSS0_PHY_783_DATA 0x00030066 +#define DDRSS0_PHY_784_DATA 0x00000000 +#define DDRSS0_PHY_785_DATA 0x00000301 +#define DDRSS0_PHY_786_DATA 0x0000AAAA +#define DDRSS0_PHY_787_DATA 0x00005555 +#define DDRSS0_PHY_788_DATA 0x0000B5B5 +#define DDRSS0_PHY_789_DATA 0x00004A4A +#define DDRSS0_PHY_790_DATA 0x00005656 +#define DDRSS0_PHY_791_DATA 0x0000A9A9 +#define DDRSS0_PHY_792_DATA 0x0000A9A9 +#define DDRSS0_PHY_793_DATA 0x0000B5B5 +#define DDRSS0_PHY_794_DATA 0x00000000 +#define DDRSS0_PHY_795_DATA 0x00000000 +#define DDRSS0_PHY_796_DATA 0x2A000000 +#define DDRSS0_PHY_797_DATA 0x00000808 +#define DDRSS0_PHY_798_DATA 0x0F000000 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002002 +#define DDRSS0_PHY_802_DATA 0x00000000 +#define DDRSS0_PHY_803_DATA 0x00000000 +#define DDRSS0_PHY_804_DATA 0x55555555 +#define DDRSS0_PHY_805_DATA 0xAAAAAAAA +#define DDRSS0_PHY_806_DATA 0x55555555 +#define DDRSS0_PHY_807_DATA 0xAAAAAAAA +#define DDRSS0_PHY_808_DATA 0x00005555 +#define DDRSS0_PHY_809_DATA 0x01000100 +#define DDRSS0_PHY_810_DATA 0x00800180 +#define DDRSS0_PHY_811_DATA 0x00000000 +#define DDRSS0_PHY_812_DATA 0x00000000 +#define DDRSS0_PHY_813_DATA 0x00000000 +#define DDRSS0_PHY_814_DATA 0x00000000 +#define DDRSS0_PHY_815_DATA 0x00000000 +#define DDRSS0_PHY_816_DATA 0x00000000 +#define DDRSS0_PHY_817_DATA 0x00000000 +#define DDRSS0_PHY_818_DATA 0x00000000 +#define DDRSS0_PHY_819_DATA 0x00000000 +#define DDRSS0_PHY_820_DATA 0x00000000 +#define DDRSS0_PHY_821_DATA 0x00000000 +#define DDRSS0_PHY_822_DATA 0x00000000 +#define DDRSS0_PHY_823_DATA 0x00000000 +#define DDRSS0_PHY_824_DATA 0x00000000 +#define DDRSS0_PHY_825_DATA 0x00000000 +#define DDRSS0_PHY_826_DATA 0x00000000 +#define DDRSS0_PHY_827_DATA 0x00000000 +#define DDRSS0_PHY_828_DATA 0x00000000 +#define DDRSS0_PHY_829_DATA 0x00000000 +#define DDRSS0_PHY_830_DATA 0x00000000 +#define DDRSS0_PHY_831_DATA 0x00000000 +#define DDRSS0_PHY_832_DATA 0x00000000 +#define DDRSS0_PHY_833_DATA 0x00000000 +#define DDRSS0_PHY_834_DATA 0x00000104 +#define DDRSS0_PHY_835_DATA 0x00000120 +#define DDRSS0_PHY_836_DATA 0x00000000 +#define DDRSS0_PHY_837_DATA 0x00000000 +#define DDRSS0_PHY_838_DATA 0x00000000 +#define DDRSS0_PHY_839_DATA 0x00000000 +#define DDRSS0_PHY_840_DATA 0x00000000 +#define DDRSS0_PHY_841_DATA 0x00000000 +#define DDRSS0_PHY_842_DATA 0x00000000 +#define DDRSS0_PHY_843_DATA 0x00000001 +#define DDRSS0_PHY_844_DATA 0x07FF0000 +#define DDRSS0_PHY_845_DATA 0x0080081F +#define DDRSS0_PHY_846_DATA 0x00081020 +#define DDRSS0_PHY_847_DATA 0x04010000 +#define DDRSS0_PHY_848_DATA 0x00000000 +#define DDRSS0_PHY_849_DATA 0x00000000 +#define DDRSS0_PHY_850_DATA 0x00000000 +#define DDRSS0_PHY_851_DATA 0x00000100 +#define DDRSS0_PHY_852_DATA 0x01CC0C01 +#define DDRSS0_PHY_853_DATA 0x1003CC0C +#define DDRSS0_PHY_854_DATA 0x20000140 +#define DDRSS0_PHY_855_DATA 0x07FF0200 +#define DDRSS0_PHY_856_DATA 0x0000DD01 +#define DDRSS0_PHY_857_DATA 0x10100303 +#define DDRSS0_PHY_858_DATA 0x10101010 +#define DDRSS0_PHY_859_DATA 0x10101010 +#define DDRSS0_PHY_860_DATA 0x00021010 +#define DDRSS0_PHY_861_DATA 0x00100010 +#define DDRSS0_PHY_862_DATA 0x00100010 +#define DDRSS0_PHY_863_DATA 0x00100010 +#define DDRSS0_PHY_864_DATA 0x00100010 +#define DDRSS0_PHY_865_DATA 0x00050010 +#define DDRSS0_PHY_866_DATA 0x51517041 +#define DDRSS0_PHY_867_DATA 0x31C06001 +#define DDRSS0_PHY_868_DATA 0x07AB01AB +#define DDRSS0_PHY_869_DATA 0x00C0C001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 +#define DDRSS0_PHY_871_DATA 0x10001000 +#define DDRSS0_PHY_872_DATA 0x0C083E42 +#define DDRSS0_PHY_873_DATA 0x0F0C3701 +#define DDRSS0_PHY_874_DATA 0x01000140 +#define DDRSS0_PHY_875_DATA 0x0C000420 +#define DDRSS0_PHY_876_DATA 0x00000198 +#define DDRSS0_PHY_877_DATA 0x0A0000D0 +#define DDRSS0_PHY_878_DATA 0x00030200 +#define DDRSS0_PHY_879_DATA 0x02800000 +#define DDRSS0_PHY_880_DATA 0x80800000 +#define DDRSS0_PHY_881_DATA 0x000E2010 +#define DDRSS0_PHY_882_DATA 0x76543210 +#define DDRSS0_PHY_883_DATA 0x00000008 +#define DDRSS0_PHY_884_DATA 0x02800280 +#define DDRSS0_PHY_885_DATA 0x02800280 +#define DDRSS0_PHY_886_DATA 0x02800280 +#define DDRSS0_PHY_887_DATA 0x02800280 +#define DDRSS0_PHY_888_DATA 0x00000280 +#define DDRSS0_PHY_889_DATA 0x0000A000 +#define DDRSS0_PHY_890_DATA 0x00A000A0 +#define DDRSS0_PHY_891_DATA 0x00A000A0 +#define DDRSS0_PHY_892_DATA 0x00A000A0 +#define DDRSS0_PHY_893_DATA 0x00A000A0 +#define DDRSS0_PHY_894_DATA 0x00A000A0 +#define DDRSS0_PHY_895_DATA 0x00A000A0 +#define DDRSS0_PHY_896_DATA 0x00A000A0 +#define DDRSS0_PHY_897_DATA 0x00A000A0 +#define DDRSS0_PHY_898_DATA 0x01C200A0 +#define DDRSS0_PHY_899_DATA 0x01A00005 +#define DDRSS0_PHY_900_DATA 0x00000000 +#define DDRSS0_PHY_901_DATA 0x00000000 +#define DDRSS0_PHY_902_DATA 0x00080200 +#define DDRSS0_PHY_903_DATA 0x00000000 +#define DDRSS0_PHY_904_DATA 0x20202020 +#define DDRSS0_PHY_905_DATA 0x20202020 +#define DDRSS0_PHY_906_DATA 0xF0F02020 +#define DDRSS0_PHY_907_DATA 0x00000000 +#define DDRSS0_PHY_908_DATA 0x00000000 +#define DDRSS0_PHY_909_DATA 0x00000000 +#define DDRSS0_PHY_910_DATA 0x00000000 +#define DDRSS0_PHY_911_DATA 0x00000000 +#define DDRSS0_PHY_912_DATA 0x00000000 +#define DDRSS0_PHY_913_DATA 0x00000000 +#define DDRSS0_PHY_914_DATA 0x00000000 +#define DDRSS0_PHY_915_DATA 0x00000000 +#define DDRSS0_PHY_916_DATA 0x00000000 +#define DDRSS0_PHY_917_DATA 0x00000000 +#define DDRSS0_PHY_918_DATA 0x00000000 +#define DDRSS0_PHY_919_DATA 0x00000000 +#define DDRSS0_PHY_920_DATA 0x00000000 +#define DDRSS0_PHY_921_DATA 0x00000000 +#define DDRSS0_PHY_922_DATA 0x00000000 +#define DDRSS0_PHY_923_DATA 0x00000000 +#define DDRSS0_PHY_924_DATA 0x00000000 +#define DDRSS0_PHY_925_DATA 0x00000000 +#define DDRSS0_PHY_926_DATA 0x00000000 +#define DDRSS0_PHY_927_DATA 0x00000000 +#define DDRSS0_PHY_928_DATA 0x00000000 +#define DDRSS0_PHY_929_DATA 0x00000000 +#define DDRSS0_PHY_930_DATA 0x00000000 +#define DDRSS0_PHY_931_DATA 0x00000000 +#define DDRSS0_PHY_932_DATA 0x00000000 +#define DDRSS0_PHY_933_DATA 0x00000000 +#define DDRSS0_PHY_934_DATA 0x00000000 +#define DDRSS0_PHY_935_DATA 0x00000000 +#define DDRSS0_PHY_936_DATA 0x00000000 +#define DDRSS0_PHY_937_DATA 0x00000000 +#define DDRSS0_PHY_938_DATA 0x00000000 +#define DDRSS0_PHY_939_DATA 0x00000000 +#define DDRSS0_PHY_940_DATA 0x00000000 +#define DDRSS0_PHY_941_DATA 0x00000000 +#define DDRSS0_PHY_942_DATA 0x00000000 +#define DDRSS0_PHY_943_DATA 0x00000000 +#define DDRSS0_PHY_944_DATA 0x00000000 +#define DDRSS0_PHY_945_DATA 0x00000000 +#define DDRSS0_PHY_946_DATA 0x00000000 +#define DDRSS0_PHY_947_DATA 0x00000000 +#define DDRSS0_PHY_948_DATA 0x00000000 +#define DDRSS0_PHY_949_DATA 0x00000000 +#define DDRSS0_PHY_950_DATA 0x00000000 +#define DDRSS0_PHY_951_DATA 0x00000000 +#define DDRSS0_PHY_952_DATA 0x00000000 +#define DDRSS0_PHY_953_DATA 0x00000000 +#define DDRSS0_PHY_954_DATA 0x00000000 +#define DDRSS0_PHY_955_DATA 0x00000000 +#define DDRSS0_PHY_956_DATA 0x00000000 +#define DDRSS0_PHY_957_DATA 0x00000000 +#define DDRSS0_PHY_958_DATA 0x00000000 +#define DDRSS0_PHY_959_DATA 0x00000000 +#define DDRSS0_PHY_960_DATA 0x00000000 +#define DDRSS0_PHY_961_DATA 0x00000000 +#define DDRSS0_PHY_962_DATA 0x00000000 +#define DDRSS0_PHY_963_DATA 0x00000000 +#define DDRSS0_PHY_964_DATA 0x00000000 +#define DDRSS0_PHY_965_DATA 0x00000000 +#define DDRSS0_PHY_966_DATA 0x00000000 +#define DDRSS0_PHY_967_DATA 0x00000000 +#define DDRSS0_PHY_968_DATA 0x00000000 +#define DDRSS0_PHY_969_DATA 0x00000000 +#define DDRSS0_PHY_970_DATA 0x00000000 +#define DDRSS0_PHY_971_DATA 0x00000000 +#define DDRSS0_PHY_972_DATA 0x00000000 +#define DDRSS0_PHY_973_DATA 0x00000000 +#define DDRSS0_PHY_974_DATA 0x00000000 +#define DDRSS0_PHY_975_DATA 0x00000000 +#define DDRSS0_PHY_976_DATA 0x00000000 +#define DDRSS0_PHY_977_DATA 0x00000000 +#define DDRSS0_PHY_978_DATA 0x00000000 +#define DDRSS0_PHY_979_DATA 0x00000000 +#define DDRSS0_PHY_980_DATA 0x00000000 +#define DDRSS0_PHY_981_DATA 0x00000000 +#define DDRSS0_PHY_982_DATA 0x00000000 +#define DDRSS0_PHY_983_DATA 0x00000000 +#define DDRSS0_PHY_984_DATA 0x00000000 +#define DDRSS0_PHY_985_DATA 0x00000000 +#define DDRSS0_PHY_986_DATA 0x00000000 +#define DDRSS0_PHY_987_DATA 0x00000000 +#define DDRSS0_PHY_988_DATA 0x00000000 +#define DDRSS0_PHY_989_DATA 0x00000000 +#define DDRSS0_PHY_990_DATA 0x00000000 +#define DDRSS0_PHY_991_DATA 0x00000000 +#define DDRSS0_PHY_992_DATA 0x00000000 +#define DDRSS0_PHY_993_DATA 0x00000000 +#define DDRSS0_PHY_994_DATA 0x00000000 +#define DDRSS0_PHY_995_DATA 0x00000000 +#define DDRSS0_PHY_996_DATA 0x00000000 +#define DDRSS0_PHY_997_DATA 0x00000000 +#define DDRSS0_PHY_998_DATA 0x00000000 +#define DDRSS0_PHY_999_DATA 0x00000000 +#define DDRSS0_PHY_1000_DATA 0x00000000 +#define DDRSS0_PHY_1001_DATA 0x00000000 +#define DDRSS0_PHY_1002_DATA 0x00000000 +#define DDRSS0_PHY_1003_DATA 0x00000000 +#define DDRSS0_PHY_1004_DATA 0x00000000 +#define DDRSS0_PHY_1005_DATA 0x00000000 +#define DDRSS0_PHY_1006_DATA 0x00000000 +#define DDRSS0_PHY_1007_DATA 0x00000000 +#define DDRSS0_PHY_1008_DATA 0x00000000 +#define DDRSS0_PHY_1009_DATA 0x00000000 +#define DDRSS0_PHY_1010_DATA 0x00000000 +#define DDRSS0_PHY_1011_DATA 0x00000000 +#define DDRSS0_PHY_1012_DATA 0x00000000 +#define DDRSS0_PHY_1013_DATA 0x00000000 +#define DDRSS0_PHY_1014_DATA 0x00000000 +#define DDRSS0_PHY_1015_DATA 0x00000000 +#define DDRSS0_PHY_1016_DATA 0x00000000 +#define DDRSS0_PHY_1017_DATA 0x00000000 +#define DDRSS0_PHY_1018_DATA 0x00000000 +#define DDRSS0_PHY_1019_DATA 0x00000000 +#define DDRSS0_PHY_1020_DATA 0x00000000 +#define DDRSS0_PHY_1021_DATA 0x00000000 +#define DDRSS0_PHY_1022_DATA 0x00000000 +#define DDRSS0_PHY_1023_DATA 0x00000000 +#define DDRSS0_PHY_1024_DATA 0x00000000 +#define DDRSS0_PHY_1025_DATA 0x00000000 +#define DDRSS0_PHY_1026_DATA 0x00000000 +#define DDRSS0_PHY_1027_DATA 0x00000000 +#define DDRSS0_PHY_1028_DATA 0x00000000 +#define DDRSS0_PHY_1029_DATA 0x00000100 +#define DDRSS0_PHY_1030_DATA 0x00000200 +#define DDRSS0_PHY_1031_DATA 0x00000000 +#define DDRSS0_PHY_1032_DATA 0x00000000 +#define DDRSS0_PHY_1033_DATA 0x00000000 +#define DDRSS0_PHY_1034_DATA 0x00000000 +#define DDRSS0_PHY_1035_DATA 0x00400000 +#define DDRSS0_PHY_1036_DATA 0x00000080 +#define DDRSS0_PHY_1037_DATA 0x00DCBA98 +#define DDRSS0_PHY_1038_DATA 0x03000000 +#define DDRSS0_PHY_1039_DATA 0x00200000 +#define DDRSS0_PHY_1040_DATA 0x00000000 +#define DDRSS0_PHY_1041_DATA 0x00000000 +#define DDRSS0_PHY_1042_DATA 0x00000000 +#define DDRSS0_PHY_1043_DATA 0x00000000 +#define DDRSS0_PHY_1044_DATA 0x00000000 +#define DDRSS0_PHY_1045_DATA 0x0000002A +#define DDRSS0_PHY_1046_DATA 0x00000015 +#define DDRSS0_PHY_1047_DATA 0x00000015 +#define DDRSS0_PHY_1048_DATA 0x0000002A +#define DDRSS0_PHY_1049_DATA 0x00000033 +#define DDRSS0_PHY_1050_DATA 0x0000000C +#define DDRSS0_PHY_1051_DATA 0x0000000C +#define DDRSS0_PHY_1052_DATA 0x00000033 +#define DDRSS0_PHY_1053_DATA 0x00543210 +#define DDRSS0_PHY_1054_DATA 0x003F0000 +#define DDRSS0_PHY_1055_DATA 0x000F3F3F +#define DDRSS0_PHY_1056_DATA 0x20202003 +#define DDRSS0_PHY_1057_DATA 0x00202020 +#define DDRSS0_PHY_1058_DATA 0x20008008 +#define DDRSS0_PHY_1059_DATA 0x00000810 +#define DDRSS0_PHY_1060_DATA 0x00000F00 +#define DDRSS0_PHY_1061_DATA 0x00000000 +#define DDRSS0_PHY_1062_DATA 0x00000000 +#define DDRSS0_PHY_1063_DATA 0x00000000 +#define DDRSS0_PHY_1064_DATA 0x000305CC +#define DDRSS0_PHY_1065_DATA 0x00030000 +#define DDRSS0_PHY_1066_DATA 0x00000300 +#define DDRSS0_PHY_1067_DATA 0x00000300 +#define DDRSS0_PHY_1068_DATA 0x00000300 +#define DDRSS0_PHY_1069_DATA 0x00000300 +#define DDRSS0_PHY_1070_DATA 0x00000300 +#define DDRSS0_PHY_1071_DATA 0x42080010 +#define DDRSS0_PHY_1072_DATA 0x0000803E +#define DDRSS0_PHY_1073_DATA 0x00000001 +#define DDRSS0_PHY_1074_DATA 0x01000102 +#define DDRSS0_PHY_1075_DATA 0x00008000 +#define DDRSS0_PHY_1076_DATA 0x00000000 +#define DDRSS0_PHY_1077_DATA 0x00000000 +#define DDRSS0_PHY_1078_DATA 0x00000000 +#define DDRSS0_PHY_1079_DATA 0x00000000 +#define DDRSS0_PHY_1080_DATA 0x00000000 +#define DDRSS0_PHY_1081_DATA 0x00000000 +#define DDRSS0_PHY_1082_DATA 0x00000000 +#define DDRSS0_PHY_1083_DATA 0x00000000 +#define DDRSS0_PHY_1084_DATA 0x00000000 +#define DDRSS0_PHY_1085_DATA 0x00000000 +#define DDRSS0_PHY_1086_DATA 0x00000000 +#define DDRSS0_PHY_1087_DATA 0x00000000 +#define DDRSS0_PHY_1088_DATA 0x00000000 +#define DDRSS0_PHY_1089_DATA 0x00000000 +#define DDRSS0_PHY_1090_DATA 0x00000000 +#define DDRSS0_PHY_1091_DATA 0x00000000 +#define DDRSS0_PHY_1092_DATA 0x00000000 +#define DDRSS0_PHY_1093_DATA 0x00000000 +#define DDRSS0_PHY_1094_DATA 0x00000000 +#define DDRSS0_PHY_1095_DATA 0x00000000 +#define DDRSS0_PHY_1096_DATA 0x00000000 +#define DDRSS0_PHY_1097_DATA 0x00000000 +#define DDRSS0_PHY_1098_DATA 0x00000000 +#define DDRSS0_PHY_1099_DATA 0x00000000 +#define DDRSS0_PHY_1100_DATA 0x00000000 +#define DDRSS0_PHY_1101_DATA 0x00000000 +#define DDRSS0_PHY_1102_DATA 0x00000000 +#define DDRSS0_PHY_1103_DATA 0x00000000 +#define DDRSS0_PHY_1104_DATA 0x00000000 +#define DDRSS0_PHY_1105_DATA 0x00000000 +#define DDRSS0_PHY_1106_DATA 0x00000000 +#define DDRSS0_PHY_1107_DATA 0x00000000 +#define DDRSS0_PHY_1108_DATA 0x00000000 +#define DDRSS0_PHY_1109_DATA 0x00000000 +#define DDRSS0_PHY_1110_DATA 0x00000000 +#define DDRSS0_PHY_1111_DATA 0x00000000 +#define DDRSS0_PHY_1112_DATA 0x00000000 +#define DDRSS0_PHY_1113_DATA 0x00000000 +#define DDRSS0_PHY_1114_DATA 0x00000000 +#define DDRSS0_PHY_1115_DATA 0x00000000 +#define DDRSS0_PHY_1116_DATA 0x00000000 +#define DDRSS0_PHY_1117_DATA 0x00000000 +#define DDRSS0_PHY_1118_DATA 0x00000000 +#define DDRSS0_PHY_1119_DATA 0x00000000 +#define DDRSS0_PHY_1120_DATA 0x00000000 +#define DDRSS0_PHY_1121_DATA 0x00000000 +#define DDRSS0_PHY_1122_DATA 0x00000000 +#define DDRSS0_PHY_1123_DATA 0x00000000 +#define DDRSS0_PHY_1124_DATA 0x00000000 +#define DDRSS0_PHY_1125_DATA 0x00000000 +#define DDRSS0_PHY_1126_DATA 0x00000000 +#define DDRSS0_PHY_1127_DATA 0x00000000 +#define DDRSS0_PHY_1128_DATA 0x00000000 +#define DDRSS0_PHY_1129_DATA 0x00000000 +#define DDRSS0_PHY_1130_DATA 0x00000000 +#define DDRSS0_PHY_1131_DATA 0x00000000 +#define DDRSS0_PHY_1132_DATA 0x00000000 +#define DDRSS0_PHY_1133_DATA 0x00000000 +#define DDRSS0_PHY_1134_DATA 0x00000000 +#define DDRSS0_PHY_1135_DATA 0x00000000 +#define DDRSS0_PHY_1136_DATA 0x00000000 +#define DDRSS0_PHY_1137_DATA 0x00000000 +#define DDRSS0_PHY_1138_DATA 0x00000000 +#define DDRSS0_PHY_1139_DATA 0x00000000 +#define DDRSS0_PHY_1140_DATA 0x00000000 +#define DDRSS0_PHY_1141_DATA 0x00000000 +#define DDRSS0_PHY_1142_DATA 0x00000000 +#define DDRSS0_PHY_1143_DATA 0x00000000 +#define DDRSS0_PHY_1144_DATA 0x00000000 +#define DDRSS0_PHY_1145_DATA 0x00000000 +#define DDRSS0_PHY_1146_DATA 0x00000000 +#define DDRSS0_PHY_1147_DATA 0x00000000 +#define DDRSS0_PHY_1148_DATA 0x00000000 +#define DDRSS0_PHY_1149_DATA 0x00000000 +#define DDRSS0_PHY_1150_DATA 0x00000000 +#define DDRSS0_PHY_1151_DATA 0x00000000 +#define DDRSS0_PHY_1152_DATA 0x00000000 +#define DDRSS0_PHY_1153_DATA 0x00000000 +#define DDRSS0_PHY_1154_DATA 0x00000000 +#define DDRSS0_PHY_1155_DATA 0x00000000 +#define DDRSS0_PHY_1156_DATA 0x00000000 +#define DDRSS0_PHY_1157_DATA 0x00000000 +#define DDRSS0_PHY_1158_DATA 0x00000000 +#define DDRSS0_PHY_1159_DATA 0x00000000 +#define DDRSS0_PHY_1160_DATA 0x00000000 +#define DDRSS0_PHY_1161_DATA 0x00000000 +#define DDRSS0_PHY_1162_DATA 0x00000000 +#define DDRSS0_PHY_1163_DATA 0x00000000 +#define DDRSS0_PHY_1164_DATA 0x00000000 +#define DDRSS0_PHY_1165_DATA 0x00000000 +#define DDRSS0_PHY_1166_DATA 0x00000000 +#define DDRSS0_PHY_1167_DATA 0x00000000 +#define DDRSS0_PHY_1168_DATA 0x00000000 +#define DDRSS0_PHY_1169_DATA 0x00000000 +#define DDRSS0_PHY_1170_DATA 0x00000000 +#define DDRSS0_PHY_1171_DATA 0x00000000 +#define DDRSS0_PHY_1172_DATA 0x00000000 +#define DDRSS0_PHY_1173_DATA 0x00000000 +#define DDRSS0_PHY_1174_DATA 0x00000000 +#define DDRSS0_PHY_1175_DATA 0x00000000 +#define DDRSS0_PHY_1176_DATA 0x00000000 +#define DDRSS0_PHY_1177_DATA 0x00000000 +#define DDRSS0_PHY_1178_DATA 0x00000000 +#define DDRSS0_PHY_1179_DATA 0x00000000 +#define DDRSS0_PHY_1180_DATA 0x00000000 +#define DDRSS0_PHY_1181_DATA 0x00000000 +#define DDRSS0_PHY_1182_DATA 0x00000000 +#define DDRSS0_PHY_1183_DATA 0x00000000 +#define DDRSS0_PHY_1184_DATA 0x00000000 +#define DDRSS0_PHY_1185_DATA 0x00000000 +#define DDRSS0_PHY_1186_DATA 0x00000000 +#define DDRSS0_PHY_1187_DATA 0x00000000 +#define DDRSS0_PHY_1188_DATA 0x00000000 +#define DDRSS0_PHY_1189_DATA 0x00000000 +#define DDRSS0_PHY_1190_DATA 0x00000000 +#define DDRSS0_PHY_1191_DATA 0x00000000 +#define DDRSS0_PHY_1192_DATA 0x00000000 +#define DDRSS0_PHY_1193_DATA 0x00000000 +#define DDRSS0_PHY_1194_DATA 0x00000000 +#define DDRSS0_PHY_1195_DATA 0x00000000 +#define DDRSS0_PHY_1196_DATA 0x00000000 +#define DDRSS0_PHY_1197_DATA 0x00000000 +#define DDRSS0_PHY_1198_DATA 0x00000000 +#define DDRSS0_PHY_1199_DATA 0x00000000 +#define DDRSS0_PHY_1200_DATA 0x00000000 +#define DDRSS0_PHY_1201_DATA 0x00000000 +#define DDRSS0_PHY_1202_DATA 0x00000000 +#define DDRSS0_PHY_1203_DATA 0x00000000 +#define DDRSS0_PHY_1204_DATA 0x00000000 +#define DDRSS0_PHY_1205_DATA 0x00000000 +#define DDRSS0_PHY_1206_DATA 0x00000000 +#define DDRSS0_PHY_1207_DATA 0x00000000 +#define DDRSS0_PHY_1208_DATA 0x00000000 +#define DDRSS0_PHY_1209_DATA 0x00000000 +#define DDRSS0_PHY_1210_DATA 0x00000000 +#define DDRSS0_PHY_1211_DATA 0x00000000 +#define DDRSS0_PHY_1212_DATA 0x00000000 +#define DDRSS0_PHY_1213_DATA 0x00000000 +#define DDRSS0_PHY_1214_DATA 0x00000000 +#define DDRSS0_PHY_1215_DATA 0x00000000 +#define DDRSS0_PHY_1216_DATA 0x00000000 +#define DDRSS0_PHY_1217_DATA 0x00000000 +#define DDRSS0_PHY_1218_DATA 0x00000000 +#define DDRSS0_PHY_1219_DATA 0x00000000 +#define DDRSS0_PHY_1220_DATA 0x00000000 +#define DDRSS0_PHY_1221_DATA 0x00000000 +#define DDRSS0_PHY_1222_DATA 0x00000000 +#define DDRSS0_PHY_1223_DATA 0x00000000 +#define DDRSS0_PHY_1224_DATA 0x00000000 +#define DDRSS0_PHY_1225_DATA 0x00000000 +#define DDRSS0_PHY_1226_DATA 0x00000000 +#define DDRSS0_PHY_1227_DATA 0x00000000 +#define DDRSS0_PHY_1228_DATA 0x00000000 +#define DDRSS0_PHY_1229_DATA 0x00000000 +#define DDRSS0_PHY_1230_DATA 0x00000000 +#define DDRSS0_PHY_1231_DATA 0x00000000 +#define DDRSS0_PHY_1232_DATA 0x00000000 +#define DDRSS0_PHY_1233_DATA 0x00000000 +#define DDRSS0_PHY_1234_DATA 0x00000000 +#define DDRSS0_PHY_1235_DATA 0x00000000 +#define DDRSS0_PHY_1236_DATA 0x00000000 +#define DDRSS0_PHY_1237_DATA 0x00000000 +#define DDRSS0_PHY_1238_DATA 0x00000000 +#define DDRSS0_PHY_1239_DATA 0x00000000 +#define DDRSS0_PHY_1240_DATA 0x00000000 +#define DDRSS0_PHY_1241_DATA 0x00000000 +#define DDRSS0_PHY_1242_DATA 0x00000000 +#define DDRSS0_PHY_1243_DATA 0x00000000 +#define DDRSS0_PHY_1244_DATA 0x00000000 +#define DDRSS0_PHY_1245_DATA 0x00000000 +#define DDRSS0_PHY_1246_DATA 0x00000000 +#define DDRSS0_PHY_1247_DATA 0x00000000 +#define DDRSS0_PHY_1248_DATA 0x00000000 +#define DDRSS0_PHY_1249_DATA 0x00000000 +#define DDRSS0_PHY_1250_DATA 0x00000000 +#define DDRSS0_PHY_1251_DATA 0x00000000 +#define DDRSS0_PHY_1252_DATA 0x00000000 +#define DDRSS0_PHY_1253_DATA 0x00000000 +#define DDRSS0_PHY_1254_DATA 0x00000000 +#define DDRSS0_PHY_1255_DATA 0x00000000 +#define DDRSS0_PHY_1256_DATA 0x00000000 +#define DDRSS0_PHY_1257_DATA 0x00000000 +#define DDRSS0_PHY_1258_DATA 0x00000000 +#define DDRSS0_PHY_1259_DATA 0x00000000 +#define DDRSS0_PHY_1260_DATA 0x00000000 +#define DDRSS0_PHY_1261_DATA 0x00000000 +#define DDRSS0_PHY_1262_DATA 0x00000000 +#define DDRSS0_PHY_1263_DATA 0x00000000 +#define DDRSS0_PHY_1264_DATA 0x00000000 +#define DDRSS0_PHY_1265_DATA 0x00000000 +#define DDRSS0_PHY_1266_DATA 0x00000000 +#define DDRSS0_PHY_1267_DATA 0x00000000 +#define DDRSS0_PHY_1268_DATA 0x00000000 +#define DDRSS0_PHY_1269_DATA 0x00000000 +#define DDRSS0_PHY_1270_DATA 0x00000000 +#define DDRSS0_PHY_1271_DATA 0x00000000 +#define DDRSS0_PHY_1272_DATA 0x00000000 +#define DDRSS0_PHY_1273_DATA 0x00000000 +#define DDRSS0_PHY_1274_DATA 0x00000000 +#define DDRSS0_PHY_1275_DATA 0x00000000 +#define DDRSS0_PHY_1276_DATA 0x00000000 +#define DDRSS0_PHY_1277_DATA 0x00000000 +#define DDRSS0_PHY_1278_DATA 0x00000000 +#define DDRSS0_PHY_1279_DATA 0x00000000 +#define DDRSS0_PHY_1280_DATA 0x00000000 +#define DDRSS0_PHY_1281_DATA 0x00010100 +#define DDRSS0_PHY_1282_DATA 0x00000000 +#define DDRSS0_PHY_1283_DATA 0x00000000 +#define DDRSS0_PHY_1284_DATA 0x00050000 +#define DDRSS0_PHY_1285_DATA 0x04000000 +#define DDRSS0_PHY_1286_DATA 0x00000055 +#define DDRSS0_PHY_1287_DATA 0x00000000 +#define DDRSS0_PHY_1288_DATA 0x00000000 +#define DDRSS0_PHY_1289_DATA 0x00000000 +#define DDRSS0_PHY_1290_DATA 0x00000000 +#define DDRSS0_PHY_1291_DATA 0x00002001 +#define DDRSS0_PHY_1292_DATA 0x0000400F +#define DDRSS0_PHY_1293_DATA 0x50020028 +#define DDRSS0_PHY_1294_DATA 0x01010000 +#define DDRSS0_PHY_1295_DATA 0x80080001 +#define DDRSS0_PHY_1296_DATA 0x10200000 +#define DDRSS0_PHY_1297_DATA 0x00000008 +#define DDRSS0_PHY_1298_DATA 0x00000000 +#define DDRSS0_PHY_1299_DATA 0x01090E00 +#define DDRSS0_PHY_1300_DATA 0x00040101 +#define DDRSS0_PHY_1301_DATA 0x0000010F +#define DDRSS0_PHY_1302_DATA 0x00000000 +#define DDRSS0_PHY_1303_DATA 0x00000064 +#define DDRSS0_PHY_1304_DATA 0x00000000 +#define DDRSS0_PHY_1305_DATA 0x01010000 +#define DDRSS0_PHY_1306_DATA 0x01080402 +#define DDRSS0_PHY_1307_DATA 0x01200F02 +#define DDRSS0_PHY_1308_DATA 0x00194280 +#define DDRSS0_PHY_1309_DATA 0x00000004 +#define DDRSS0_PHY_1310_DATA 0x00042000 +#define DDRSS0_PHY_1311_DATA 0x00000000 +#define DDRSS0_PHY_1312_DATA 0x00000000 +#define DDRSS0_PHY_1313_DATA 0x00000000 +#define DDRSS0_PHY_1314_DATA 0x00000000 +#define DDRSS0_PHY_1315_DATA 0x00000000 +#define DDRSS0_PHY_1316_DATA 0x00000000 +#define DDRSS0_PHY_1317_DATA 0x01000000 +#define DDRSS0_PHY_1318_DATA 0x00000705 +#define DDRSS0_PHY_1319_DATA 0x00000054 +#define DDRSS0_PHY_1320_DATA 0x00030820 +#define DDRSS0_PHY_1321_DATA 0x00010820 +#define DDRSS0_PHY_1322_DATA 0x00010820 +#define DDRSS0_PHY_1323_DATA 0x00010820 +#define DDRSS0_PHY_1324_DATA 0x00010820 +#define DDRSS0_PHY_1325_DATA 0x00010820 +#define DDRSS0_PHY_1326_DATA 0x00010820 +#define DDRSS0_PHY_1327_DATA 0x00010820 +#define DDRSS0_PHY_1328_DATA 0x00010820 +#define DDRSS0_PHY_1329_DATA 0x00000000 +#define DDRSS0_PHY_1330_DATA 0x00000074 +#define DDRSS0_PHY_1331_DATA 0x00000400 +#define DDRSS0_PHY_1332_DATA 0x00000108 +#define DDRSS0_PHY_1333_DATA 0x00000000 +#define DDRSS0_PHY_1334_DATA 0x00000000 +#define DDRSS0_PHY_1335_DATA 0x00000000 +#define DDRSS0_PHY_1336_DATA 0x00000000 +#define DDRSS0_PHY_1337_DATA 0x00000000 +#define DDRSS0_PHY_1338_DATA 0x03000000 +#define DDRSS0_PHY_1339_DATA 0x00000000 +#define DDRSS0_PHY_1340_DATA 0x00000000 +#define DDRSS0_PHY_1341_DATA 0x00000000 +#define DDRSS0_PHY_1342_DATA 0x04102006 +#define DDRSS0_PHY_1343_DATA 0x00041020 +#define DDRSS0_PHY_1344_DATA 0x01C98C98 +#define DDRSS0_PHY_1345_DATA 0x3F400000 +#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS0_PHY_1347_DATA 0x0000001F +#define DDRSS0_PHY_1348_DATA 0x00000000 +#define DDRSS0_PHY_1349_DATA 0x00000000 +#define DDRSS0_PHY_1350_DATA 0x00000000 +#define DDRSS0_PHY_1351_DATA 0x00010000 +#define DDRSS0_PHY_1352_DATA 0x00000000 +#define DDRSS0_PHY_1353_DATA 0x00000000 +#define DDRSS0_PHY_1354_DATA 0x00000000 +#define DDRSS0_PHY_1355_DATA 0x00000000 +#define DDRSS0_PHY_1356_DATA 0x76543210 +#define DDRSS0_PHY_1357_DATA 0x00010198 +#define DDRSS0_PHY_1358_DATA 0x00000000 +#define DDRSS0_PHY_1359_DATA 0x00000000 +#define DDRSS0_PHY_1360_DATA 0x00000000 +#define DDRSS0_PHY_1361_DATA 0x00040700 +#define DDRSS0_PHY_1362_DATA 0x00000000 +#define DDRSS0_PHY_1363_DATA 0x00000000 +#define DDRSS0_PHY_1364_DATA 0x00000000 +#define DDRSS0_PHY_1365_DATA 0x00000000 +#define DDRSS0_PHY_1366_DATA 0x00000000 +#define DDRSS0_PHY_1367_DATA 0x00000002 +#define DDRSS0_PHY_1368_DATA 0x00000000 +#define DDRSS0_PHY_1369_DATA 0x00000000 +#define DDRSS0_PHY_1370_DATA 0x00000000 +#define DDRSS0_PHY_1371_DATA 0x00000000 +#define DDRSS0_PHY_1372_DATA 0x00000000 +#define DDRSS0_PHY_1373_DATA 0x00000000 +#define DDRSS0_PHY_1374_DATA 0x00080000 +#define DDRSS0_PHY_1375_DATA 0x000007FF +#define DDRSS0_PHY_1376_DATA 0x00000000 +#define DDRSS0_PHY_1377_DATA 0x00000000 +#define DDRSS0_PHY_1378_DATA 0x00000000 +#define DDRSS0_PHY_1379_DATA 0x00000000 +#define DDRSS0_PHY_1380_DATA 0x00000000 +#define DDRSS0_PHY_1381_DATA 0x00000000 +#define DDRSS0_PHY_1382_DATA 0x000FFFFF +#define DDRSS0_PHY_1383_DATA 0x000FFFFF +#define DDRSS0_PHY_1384_DATA 0x0000FFFF +#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS0_PHY_1386_DATA 0x030FFFFF +#define DDRSS0_PHY_1387_DATA 0x01FFFFFF +#define DDRSS0_PHY_1388_DATA 0x0000FFFF +#define DDRSS0_PHY_1389_DATA 0x00000000 +#define DDRSS0_PHY_1390_DATA 0x00000000 +#define DDRSS0_PHY_1391_DATA 0x00000000 +#define DDRSS0_PHY_1392_DATA 0x00000000 +#define DDRSS0_PHY_1393_DATA 0x0001F7C0 +#define DDRSS0_PHY_1394_DATA 0x00000003 +#define DDRSS0_PHY_1395_DATA 0x00000000 +#define DDRSS0_PHY_1396_DATA 0x00001142 +#define DDRSS0_PHY_1397_DATA 0x040207AB +#define DDRSS0_PHY_1398_DATA 0x01000080 +#define DDRSS0_PHY_1399_DATA 0x03900390 +#define DDRSS0_PHY_1400_DATA 0x03900390 +#define DDRSS0_PHY_1401_DATA 0x00000390 +#define DDRSS0_PHY_1402_DATA 0x00000390 +#define DDRSS0_PHY_1403_DATA 0x00000390 +#define DDRSS0_PHY_1404_DATA 0x00000390 +#define DDRSS0_PHY_1405_DATA 0x00000005 +#define DDRSS0_PHY_1406_DATA 0x01813FCC +#define DDRSS0_PHY_1407_DATA 0x000000CC +#define DDRSS0_PHY_1408_DATA 0x0C000DFF +#define DDRSS0_PHY_1409_DATA 0x30000DFF +#define DDRSS0_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1411_DATA 0x000100F0 +#define DDRSS0_PHY_1412_DATA 0x780DFFCC +#define DDRSS0_PHY_1413_DATA 0x00007E31 +#define DDRSS0_PHY_1414_DATA 0x000CBF11 +#define DDRSS0_PHY_1415_DATA 0x01990010 +#define DDRSS0_PHY_1416_DATA 0x000CBF11 +#define DDRSS0_PHY_1417_DATA 0x01990010 +#define DDRSS0_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1419_DATA 0x00EF00F0 +#define DDRSS0_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1421_DATA 0x01FF00F0 +#define DDRSS0_PHY_1422_DATA 0x20040006 + +#define DDRSS1_CTL_00_DATA 0x00000B00 +#define DDRSS1_CTL_01_DATA 0x00000000 +#define DDRSS1_CTL_02_DATA 0x00000000 +#define DDRSS1_CTL_03_DATA 0x00000000 +#define DDRSS1_CTL_04_DATA 0x00000000 +#define DDRSS1_CTL_05_DATA 0x00000000 +#define DDRSS1_CTL_06_DATA 0x00000000 +#define DDRSS1_CTL_07_DATA 0x00002AF8 +#define DDRSS1_CTL_08_DATA 0x0001ADAF +#define DDRSS1_CTL_09_DATA 0x00000005 +#define DDRSS1_CTL_10_DATA 0x0000006E +#define DDRSS1_CTL_11_DATA 0x000681C8 +#define DDRSS1_CTL_12_DATA 0x004111C9 +#define DDRSS1_CTL_13_DATA 0x00000005 +#define DDRSS1_CTL_14_DATA 0x000010A9 +#define DDRSS1_CTL_15_DATA 0x000681C8 +#define DDRSS1_CTL_16_DATA 0x004111C9 +#define DDRSS1_CTL_17_DATA 0x00000005 +#define DDRSS1_CTL_18_DATA 0x000010A9 +#define DDRSS1_CTL_19_DATA 0x01010000 +#define DDRSS1_CTL_20_DATA 0x01011001 +#define DDRSS1_CTL_21_DATA 0x02010000 +#define DDRSS1_CTL_22_DATA 0x00020100 +#define DDRSS1_CTL_23_DATA 0x0000000B +#define DDRSS1_CTL_24_DATA 0x0000001C +#define DDRSS1_CTL_25_DATA 0x00000000 +#define DDRSS1_CTL_26_DATA 0x00000000 +#define DDRSS1_CTL_27_DATA 0x03020200 +#define DDRSS1_CTL_28_DATA 0x00005656 +#define DDRSS1_CTL_29_DATA 0x00100000 +#define DDRSS1_CTL_30_DATA 0x00000000 +#define DDRSS1_CTL_31_DATA 0x00000000 +#define DDRSS1_CTL_32_DATA 0x00000000 +#define DDRSS1_CTL_33_DATA 0x00000000 +#define DDRSS1_CTL_34_DATA 0x040C0000 +#define DDRSS1_CTL_35_DATA 0x12501250 +#define DDRSS1_CTL_36_DATA 0x00050804 +#define DDRSS1_CTL_37_DATA 0x09040008 +#define DDRSS1_CTL_38_DATA 0x15000204 +#define DDRSS1_CTL_39_DATA 0x1760008B +#define DDRSS1_CTL_40_DATA 0x1500422B +#define DDRSS1_CTL_41_DATA 0x1760008B +#define DDRSS1_CTL_42_DATA 0x2000422B +#define DDRSS1_CTL_43_DATA 0x000A0A09 +#define DDRSS1_CTL_44_DATA 0x040003C5 +#define DDRSS1_CTL_45_DATA 0x1E161104 +#define DDRSS1_CTL_46_DATA 0x1000922C +#define DDRSS1_CTL_47_DATA 0x1E161110 +#define DDRSS1_CTL_48_DATA 0x1000922C +#define DDRSS1_CTL_49_DATA 0x02030410 +#define DDRSS1_CTL_50_DATA 0x2C060500 +#define DDRSS1_CTL_51_DATA 0x08292C29 +#define DDRSS1_CTL_52_DATA 0x14000E0A +#define DDRSS1_CTL_53_DATA 0x04010A0A +#define DDRSS1_CTL_54_DATA 0x01010004 +#define DDRSS1_CTL_55_DATA 0x0454540A +#define DDRSS1_CTL_56_DATA 0x04313104 +#define DDRSS1_CTL_57_DATA 0x00003131 +#define DDRSS1_CTL_58_DATA 0x00010100 +#define DDRSS1_CTL_59_DATA 0x03010000 +#define DDRSS1_CTL_60_DATA 0x00001508 +#define DDRSS1_CTL_61_DATA 0x00000068 +#define DDRSS1_CTL_62_DATA 0x0000032B +#define DDRSS1_CTL_63_DATA 0x00001035 +#define DDRSS1_CTL_64_DATA 0x0000032B +#define DDRSS1_CTL_65_DATA 0x00001035 +#define DDRSS1_CTL_66_DATA 0x00000005 +#define DDRSS1_CTL_67_DATA 0x00050000 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 +#define DDRSS1_CTL_71_DATA 0x00120103 +#define DDRSS1_CTL_72_DATA 0x00100005 +#define DDRSS1_CTL_73_DATA 0x2F080010 +#define DDRSS1_CTL_74_DATA 0x0505012F +#define DDRSS1_CTL_75_DATA 0x0401030A +#define DDRSS1_CTL_76_DATA 0x041E100B +#define DDRSS1_CTL_77_DATA 0x100B0401 +#define DDRSS1_CTL_78_DATA 0x0001041E +#define DDRSS1_CTL_79_DATA 0x00160016 +#define DDRSS1_CTL_80_DATA 0x033B033B +#define DDRSS1_CTL_81_DATA 0x033B033B +#define DDRSS1_CTL_82_DATA 0x03050505 +#define DDRSS1_CTL_83_DATA 0x03010303 +#define DDRSS1_CTL_84_DATA 0x200B100B +#define DDRSS1_CTL_85_DATA 0x04041004 +#define DDRSS1_CTL_86_DATA 0x200B100B +#define DDRSS1_CTL_87_DATA 0x04041004 +#define DDRSS1_CTL_88_DATA 0x03010000 +#define DDRSS1_CTL_89_DATA 0x00010000 +#define DDRSS1_CTL_90_DATA 0x00000000 +#define DDRSS1_CTL_91_DATA 0x00000000 +#define DDRSS1_CTL_92_DATA 0x01000000 +#define DDRSS1_CTL_93_DATA 0x80104002 +#define DDRSS1_CTL_94_DATA 0x00000000 +#define DDRSS1_CTL_95_DATA 0x00040005 +#define DDRSS1_CTL_96_DATA 0x00000000 +#define DDRSS1_CTL_97_DATA 0x00050000 +#define DDRSS1_CTL_98_DATA 0x00000004 +#define DDRSS1_CTL_99_DATA 0x00000000 +#define DDRSS1_CTL_100_DATA 0x00040005 +#define DDRSS1_CTL_101_DATA 0x00000000 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 +#define DDRSS1_CTL_107_DATA 0x00000000 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 +#define DDRSS1_CTL_114_DATA 0x00000000 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 +#define DDRSS1_CTL_121_DATA 0x00000000 +#define DDRSS1_CTL_122_DATA 0x00007173 +#define DDRSS1_CTL_123_DATA 0x00000000 +#define DDRSS1_CTL_124_DATA 0x00000000 +#define DDRSS1_CTL_125_DATA 0x00000000 +#define DDRSS1_CTL_126_DATA 0x00000000 +#define DDRSS1_CTL_127_DATA 0x00000000 +#define DDRSS1_CTL_128_DATA 0x00000000 +#define DDRSS1_CTL_129_DATA 0x00000000 +#define DDRSS1_CTL_130_DATA 0x00000000 +#define DDRSS1_CTL_131_DATA 0x0B030500 +#define DDRSS1_CTL_132_DATA 0x00040B04 +#define DDRSS1_CTL_133_DATA 0x0A090000 +#define DDRSS1_CTL_134_DATA 0x0A090701 +#define DDRSS1_CTL_135_DATA 0x0900000E +#define DDRSS1_CTL_136_DATA 0x0907010A +#define DDRSS1_CTL_137_DATA 0x00000E0A +#define DDRSS1_CTL_138_DATA 0x07010A09 +#define DDRSS1_CTL_139_DATA 0x000E0A09 +#define DDRSS1_CTL_140_DATA 0x07000401 +#define DDRSS1_CTL_141_DATA 0x00000000 +#define DDRSS1_CTL_142_DATA 0x00000000 +#define DDRSS1_CTL_143_DATA 0x00000000 +#define DDRSS1_CTL_144_DATA 0x00000000 +#define DDRSS1_CTL_145_DATA 0x00000000 +#define DDRSS1_CTL_146_DATA 0x00000000 +#define DDRSS1_CTL_147_DATA 0x00000000 +#define DDRSS1_CTL_148_DATA 0x08080000 +#define DDRSS1_CTL_149_DATA 0x01000000 +#define DDRSS1_CTL_150_DATA 0x800000C0 +#define DDRSS1_CTL_151_DATA 0x800000C0 +#define DDRSS1_CTL_152_DATA 0x800000C0 +#define DDRSS1_CTL_153_DATA 0x00000000 +#define DDRSS1_CTL_154_DATA 0x00001500 +#define DDRSS1_CTL_155_DATA 0x00000000 +#define DDRSS1_CTL_156_DATA 0x00000001 +#define DDRSS1_CTL_157_DATA 0x00000002 +#define DDRSS1_CTL_158_DATA 0x0000100E +#define DDRSS1_CTL_159_DATA 0x00000000 +#define DDRSS1_CTL_160_DATA 0x00000000 +#define DDRSS1_CTL_161_DATA 0x00000000 +#define DDRSS1_CTL_162_DATA 0x00000000 +#define DDRSS1_CTL_163_DATA 0x00000000 +#define DDRSS1_CTL_164_DATA 0x000B0000 +#define DDRSS1_CTL_165_DATA 0x000E0006 +#define DDRSS1_CTL_166_DATA 0x000E0404 +#define DDRSS1_CTL_167_DATA 0x00D601AB +#define DDRSS1_CTL_168_DATA 0x10100216 +#define DDRSS1_CTL_169_DATA 0x01AB0216 +#define DDRSS1_CTL_170_DATA 0x021600D6 +#define DDRSS1_CTL_171_DATA 0x02161010 +#define DDRSS1_CTL_172_DATA 0x00000000 +#define DDRSS1_CTL_173_DATA 0x00000000 +#define DDRSS1_CTL_174_DATA 0x00000000 +#define DDRSS1_CTL_175_DATA 0x3FF40084 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x36000000 +#define DDRSS1_CTL_179_DATA 0x27270036 +#define DDRSS1_CTL_180_DATA 0x0F0F0000 +#define DDRSS1_CTL_181_DATA 0x16000000 +#define DDRSS1_CTL_182_DATA 0x00841616 +#define DDRSS1_CTL_183_DATA 0x3FF43FF4 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 +#define DDRSS1_CTL_185_DATA 0x00000000 +#define DDRSS1_CTL_186_DATA 0x00363600 +#define DDRSS1_CTL_187_DATA 0x00002727 +#define DDRSS1_CTL_188_DATA 0x00000F0F +#define DDRSS1_CTL_189_DATA 0x16161600 +#define DDRSS1_CTL_190_DATA 0x00000020 +#define DDRSS1_CTL_191_DATA 0x01000000 +#define DDRSS1_CTL_192_DATA 0x00000001 +#define DDRSS1_CTL_193_DATA 0x00000000 +#define DDRSS1_CTL_194_DATA 0x01000000 +#define DDRSS1_CTL_195_DATA 0x00000001 +#define DDRSS1_CTL_196_DATA 0x00000000 +#define DDRSS1_CTL_197_DATA 0x00000000 +#define DDRSS1_CTL_198_DATA 0x00000000 +#define DDRSS1_CTL_199_DATA 0x00000000 +#define DDRSS1_CTL_200_DATA 0x00000000 +#define DDRSS1_CTL_201_DATA 0x00000000 +#define DDRSS1_CTL_202_DATA 0x00000000 +#define DDRSS1_CTL_203_DATA 0x00000000 +#define DDRSS1_CTL_204_DATA 0x00000000 +#define DDRSS1_CTL_205_DATA 0x00000000 +#define DDRSS1_CTL_206_DATA 0x02000000 +#define DDRSS1_CTL_207_DATA 0x01080101 +#define DDRSS1_CTL_208_DATA 0x00000000 +#define DDRSS1_CTL_209_DATA 0x00000000 +#define DDRSS1_CTL_210_DATA 0x00000000 +#define DDRSS1_CTL_211_DATA 0x00000000 +#define DDRSS1_CTL_212_DATA 0x00000000 +#define DDRSS1_CTL_213_DATA 0x00000000 +#define DDRSS1_CTL_214_DATA 0x00000000 +#define DDRSS1_CTL_215_DATA 0x00000000 +#define DDRSS1_CTL_216_DATA 0x00000000 +#define DDRSS1_CTL_217_DATA 0x00000000 +#define DDRSS1_CTL_218_DATA 0x00000000 +#define DDRSS1_CTL_219_DATA 0x00000000 +#define DDRSS1_CTL_220_DATA 0x00000000 +#define DDRSS1_CTL_221_DATA 0x00000000 +#define DDRSS1_CTL_222_DATA 0x00001000 +#define DDRSS1_CTL_223_DATA 0x006403E8 +#define DDRSS1_CTL_224_DATA 0x00000000 +#define DDRSS1_CTL_225_DATA 0x00000000 +#define DDRSS1_CTL_226_DATA 0x00000000 +#define DDRSS1_CTL_227_DATA 0x15110000 +#define DDRSS1_CTL_228_DATA 0x00040C18 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 +#define DDRSS1_CTL_231_DATA 0x00000000 +#define DDRSS1_CTL_232_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 +#define DDRSS1_CTL_235_DATA 0x00000000 +#define DDRSS1_CTL_236_DATA 0x00000000 +#define DDRSS1_CTL_237_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 +#define DDRSS1_CTL_240_DATA 0x00000000 +#define DDRSS1_CTL_241_DATA 0x00000000 +#define DDRSS1_CTL_242_DATA 0x00030000 +#define DDRSS1_CTL_243_DATA 0x00000000 +#define DDRSS1_CTL_244_DATA 0x00000000 +#define DDRSS1_CTL_245_DATA 0x00000000 +#define DDRSS1_CTL_246_DATA 0x00000000 +#define DDRSS1_CTL_247_DATA 0x00000000 +#define DDRSS1_CTL_248_DATA 0x00000000 +#define DDRSS1_CTL_249_DATA 0x00000000 +#define DDRSS1_CTL_250_DATA 0x00000000 +#define DDRSS1_CTL_251_DATA 0x00000000 +#define DDRSS1_CTL_252_DATA 0x00000000 +#define DDRSS1_CTL_253_DATA 0x00000000 +#define DDRSS1_CTL_254_DATA 0x00000000 +#define DDRSS1_CTL_255_DATA 0x00000000 +#define DDRSS1_CTL_256_DATA 0x00000000 +#define DDRSS1_CTL_257_DATA 0x01000200 +#define DDRSS1_CTL_258_DATA 0x00370040 +#define DDRSS1_CTL_259_DATA 0x00020008 +#define DDRSS1_CTL_260_DATA 0x00400100 +#define DDRSS1_CTL_261_DATA 0x00400855 +#define DDRSS1_CTL_262_DATA 0x01000200 +#define DDRSS1_CTL_263_DATA 0x08550040 +#define DDRSS1_CTL_264_DATA 0x00000040 +#define DDRSS1_CTL_265_DATA 0x006B0003 +#define DDRSS1_CTL_266_DATA 0x0100006B +#define DDRSS1_CTL_267_DATA 0x03030303 +#define DDRSS1_CTL_268_DATA 0x00000000 +#define DDRSS1_CTL_269_DATA 0x00000202 +#define DDRSS1_CTL_270_DATA 0x00001FFF +#define DDRSS1_CTL_271_DATA 0x3FFF2000 +#define DDRSS1_CTL_272_DATA 0x03FF0000 +#define DDRSS1_CTL_273_DATA 0x000103FF +#define DDRSS1_CTL_274_DATA 0x0FFF0B00 +#define DDRSS1_CTL_275_DATA 0x01010001 +#define DDRSS1_CTL_276_DATA 0x01010101 +#define DDRSS1_CTL_277_DATA 0x01180101 +#define DDRSS1_CTL_278_DATA 0x00030000 +#define DDRSS1_CTL_279_DATA 0x00000000 +#define DDRSS1_CTL_280_DATA 0x00000000 +#define DDRSS1_CTL_281_DATA 0x00000000 +#define DDRSS1_CTL_282_DATA 0x00000000 +#define DDRSS1_CTL_283_DATA 0x00000000 +#define DDRSS1_CTL_284_DATA 0x00000000 +#define DDRSS1_CTL_285_DATA 0x00000000 +#define DDRSS1_CTL_286_DATA 0x00040101 +#define DDRSS1_CTL_287_DATA 0x04010100 +#define DDRSS1_CTL_288_DATA 0x00000000 +#define DDRSS1_CTL_289_DATA 0x00000000 +#define DDRSS1_CTL_290_DATA 0x03030300 +#define DDRSS1_CTL_291_DATA 0x00010101 +#define DDRSS1_CTL_292_DATA 0x00000000 +#define DDRSS1_CTL_293_DATA 0x00000000 +#define DDRSS1_CTL_294_DATA 0x00000000 +#define DDRSS1_CTL_295_DATA 0x00000000 +#define DDRSS1_CTL_296_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF +#define DDRSS1_CTL_299_DATA 0x00000000 +#define DDRSS1_CTL_300_DATA 0x00000000 +#define DDRSS1_CTL_301_DATA 0x00000000 +#define DDRSS1_CTL_302_DATA 0x00000000 +#define DDRSS1_CTL_303_DATA 0x00000000 +#define DDRSS1_CTL_304_DATA 0x00000000 +#define DDRSS1_CTL_305_DATA 0x00000000 +#define DDRSS1_CTL_306_DATA 0x00000000 +#define DDRSS1_CTL_307_DATA 0x00000000 +#define DDRSS1_CTL_308_DATA 0x00000000 +#define DDRSS1_CTL_309_DATA 0x00000000 +#define DDRSS1_CTL_310_DATA 0x00000000 +#define DDRSS1_CTL_311_DATA 0x00000000 +#define DDRSS1_CTL_312_DATA 0x00000000 +#define DDRSS1_CTL_313_DATA 0x01000000 +#define DDRSS1_CTL_314_DATA 0x00020201 +#define DDRSS1_CTL_315_DATA 0x01000101 +#define DDRSS1_CTL_316_DATA 0x01010001 +#define DDRSS1_CTL_317_DATA 0x00010101 +#define DDRSS1_CTL_318_DATA 0x050A0A03 +#define DDRSS1_CTL_319_DATA 0x10082323 +#define DDRSS1_CTL_320_DATA 0x00090310 +#define DDRSS1_CTL_321_DATA 0x0B0C030F +#define DDRSS1_CTL_322_DATA 0x0B0C0306 +#define DDRSS1_CTL_323_DATA 0x0C090006 +#define DDRSS1_CTL_324_DATA 0x0100000C +#define DDRSS1_CTL_325_DATA 0x08040801 +#define DDRSS1_CTL_326_DATA 0x00000004 +#define DDRSS1_CTL_327_DATA 0x00000000 +#define DDRSS1_CTL_328_DATA 0x00010000 +#define DDRSS1_CTL_329_DATA 0x00280D00 +#define DDRSS1_CTL_330_DATA 0x00000001 +#define DDRSS1_CTL_331_DATA 0x00030001 +#define DDRSS1_CTL_332_DATA 0x00000000 +#define DDRSS1_CTL_333_DATA 0x00000000 +#define DDRSS1_CTL_334_DATA 0x00000000 +#define DDRSS1_CTL_335_DATA 0x00000000 +#define DDRSS1_CTL_336_DATA 0x00000000 +#define DDRSS1_CTL_337_DATA 0x00000000 +#define DDRSS1_CTL_338_DATA 0x00000000 +#define DDRSS1_CTL_339_DATA 0x00000000 +#define DDRSS1_CTL_340_DATA 0x01000000 +#define DDRSS1_CTL_341_DATA 0x00000001 +#define DDRSS1_CTL_342_DATA 0x00010100 +#define DDRSS1_CTL_343_DATA 0x03030000 +#define DDRSS1_CTL_344_DATA 0x00000000 +#define DDRSS1_CTL_345_DATA 0x00000000 +#define DDRSS1_CTL_346_DATA 0x00000000 +#define DDRSS1_CTL_347_DATA 0x00000000 +#define DDRSS1_CTL_348_DATA 0x00000000 +#define DDRSS1_CTL_349_DATA 0x00000000 +#define DDRSS1_CTL_350_DATA 0x00000000 +#define DDRSS1_CTL_351_DATA 0x00000000 +#define DDRSS1_CTL_352_DATA 0x00000000 +#define DDRSS1_CTL_353_DATA 0x00000000 +#define DDRSS1_CTL_354_DATA 0x00000000 +#define DDRSS1_CTL_355_DATA 0x00000000 +#define DDRSS1_CTL_356_DATA 0x00000000 +#define DDRSS1_CTL_357_DATA 0x00000000 +#define DDRSS1_CTL_358_DATA 0x00000000 +#define DDRSS1_CTL_359_DATA 0x00000000 +#define DDRSS1_CTL_360_DATA 0x000556AA +#define DDRSS1_CTL_361_DATA 0x000AAAAA +#define DDRSS1_CTL_362_DATA 0x000AA955 +#define DDRSS1_CTL_363_DATA 0x00055555 +#define DDRSS1_CTL_364_DATA 0x000B3133 +#define DDRSS1_CTL_365_DATA 0x0004CD33 +#define DDRSS1_CTL_366_DATA 0x0004CECC +#define DDRSS1_CTL_367_DATA 0x000B32CC +#define DDRSS1_CTL_368_DATA 0x00010300 +#define DDRSS1_CTL_369_DATA 0x03000100 +#define DDRSS1_CTL_370_DATA 0x00000000 +#define DDRSS1_CTL_371_DATA 0x00000000 +#define DDRSS1_CTL_372_DATA 0x00000000 +#define DDRSS1_CTL_373_DATA 0x00000000 +#define DDRSS1_CTL_374_DATA 0x00000000 +#define DDRSS1_CTL_375_DATA 0x00000000 +#define DDRSS1_CTL_376_DATA 0x00000000 +#define DDRSS1_CTL_377_DATA 0x00010000 +#define DDRSS1_CTL_378_DATA 0x00000404 +#define DDRSS1_CTL_379_DATA 0x00000000 +#define DDRSS1_CTL_380_DATA 0x00000000 +#define DDRSS1_CTL_381_DATA 0x00000000 +#define DDRSS1_CTL_382_DATA 0x00000000 +#define DDRSS1_CTL_383_DATA 0x00000000 +#define DDRSS1_CTL_384_DATA 0x00000000 +#define DDRSS1_CTL_385_DATA 0x00000000 +#define DDRSS1_CTL_386_DATA 0x00000000 +#define DDRSS1_CTL_387_DATA 0x3A3A1B00 +#define DDRSS1_CTL_388_DATA 0x000A0000 +#define DDRSS1_CTL_389_DATA 0x000000C6 +#define DDRSS1_CTL_390_DATA 0x00000200 +#define DDRSS1_CTL_391_DATA 0x00000200 +#define DDRSS1_CTL_392_DATA 0x00000200 +#define DDRSS1_CTL_393_DATA 0x00000200 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC +#define DDRSS1_CTL_396_DATA 0x00000204 +#define DDRSS1_CTL_397_DATA 0x0000206A +#define DDRSS1_CTL_398_DATA 0x00000200 +#define DDRSS1_CTL_399_DATA 0x00000200 +#define DDRSS1_CTL_400_DATA 0x00000200 +#define DDRSS1_CTL_401_DATA 0x00000200 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A +#define DDRSS1_CTL_406_DATA 0x00000200 +#define DDRSS1_CTL_407_DATA 0x00000200 +#define DDRSS1_CTL_408_DATA 0x00000200 +#define DDRSS1_CTL_409_DATA 0x00000200 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 +#define DDRSS1_CTL_413_DATA 0x03030202 +#define DDRSS1_CTL_414_DATA 0x00000022 +#define DDRSS1_CTL_415_DATA 0x00000000 +#define DDRSS1_CTL_416_DATA 0x00000000 +#define DDRSS1_CTL_417_DATA 0x00001403 +#define DDRSS1_CTL_418_DATA 0x000007D0 +#define DDRSS1_CTL_419_DATA 0x00000000 +#define DDRSS1_CTL_420_DATA 0x00000000 +#define DDRSS1_CTL_421_DATA 0x00030000 +#define DDRSS1_CTL_422_DATA 0x0007001F +#define DDRSS1_CTL_423_DATA 0x001B0033 +#define DDRSS1_CTL_424_DATA 0x001B0033 +#define DDRSS1_CTL_425_DATA 0x00000000 +#define DDRSS1_CTL_426_DATA 0x00000000 +#define DDRSS1_CTL_427_DATA 0x02000000 +#define DDRSS1_CTL_428_DATA 0x01000404 +#define DDRSS1_CTL_429_DATA 0x0B220B22 +#define DDRSS1_CTL_430_DATA 0x00000105 +#define DDRSS1_CTL_431_DATA 0x00010101 +#define DDRSS1_CTL_432_DATA 0x00010101 +#define DDRSS1_CTL_433_DATA 0x00010001 +#define DDRSS1_CTL_434_DATA 0x00000101 +#define DDRSS1_CTL_435_DATA 0x02000201 +#define DDRSS1_CTL_436_DATA 0x02010000 +#define DDRSS1_CTL_437_DATA 0x00000200 +#define DDRSS1_CTL_438_DATA 0x28060000 +#define DDRSS1_CTL_439_DATA 0x00000128 +#define DDRSS1_CTL_440_DATA 0xFFFFFFFF +#define DDRSS1_CTL_441_DATA 0xFFFFFFFF +#define DDRSS1_CTL_442_DATA 0x00000000 +#define DDRSS1_CTL_443_DATA 0x00000000 +#define DDRSS1_CTL_444_DATA 0x00000000 +#define DDRSS1_CTL_445_DATA 0x00000000 +#define DDRSS1_CTL_446_DATA 0x00000000 +#define DDRSS1_CTL_447_DATA 0x00000000 +#define DDRSS1_CTL_448_DATA 0x00000000 +#define DDRSS1_CTL_449_DATA 0x00000000 +#define DDRSS1_CTL_450_DATA 0x00000000 +#define DDRSS1_CTL_451_DATA 0x00000000 +#define DDRSS1_CTL_452_DATA 0x00000000 +#define DDRSS1_CTL_453_DATA 0x00000000 +#define DDRSS1_CTL_454_DATA 0x00000000 +#define DDRSS1_CTL_455_DATA 0x00000000 +#define DDRSS1_CTL_456_DATA 0x00000000 +#define DDRSS1_CTL_457_DATA 0x00000000 +#define DDRSS1_CTL_458_DATA 0x00000000 + +#define DDRSS1_PI_00_DATA 0x00000B00 +#define DDRSS1_PI_01_DATA 0x00000000 +#define DDRSS1_PI_02_DATA 0x00000000 +#define DDRSS1_PI_03_DATA 0x00000000 +#define DDRSS1_PI_04_DATA 0x00000000 +#define DDRSS1_PI_05_DATA 0x00000101 +#define DDRSS1_PI_06_DATA 0x00640000 +#define DDRSS1_PI_07_DATA 0x00000001 +#define DDRSS1_PI_08_DATA 0x00000000 +#define DDRSS1_PI_09_DATA 0x00000000 +#define DDRSS1_PI_10_DATA 0x00000000 +#define DDRSS1_PI_11_DATA 0x00000000 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 +#define DDRSS1_PI_14_DATA 0x0800000F +#define DDRSS1_PI_15_DATA 0x00000103 +#define DDRSS1_PI_16_DATA 0x00000005 +#define DDRSS1_PI_17_DATA 0x00000000 +#define DDRSS1_PI_18_DATA 0x00000000 +#define DDRSS1_PI_19_DATA 0x00000000 +#define DDRSS1_PI_20_DATA 0x00000000 +#define DDRSS1_PI_21_DATA 0x00000000 +#define DDRSS1_PI_22_DATA 0x00000000 +#define DDRSS1_PI_23_DATA 0x00000000 +#define DDRSS1_PI_24_DATA 0x00000000 +#define DDRSS1_PI_25_DATA 0x00000000 +#define DDRSS1_PI_26_DATA 0x00010100 +#define DDRSS1_PI_27_DATA 0x00280A00 +#define DDRSS1_PI_28_DATA 0x00000000 +#define DDRSS1_PI_29_DATA 0x0F000000 +#define DDRSS1_PI_30_DATA 0x00003200 +#define DDRSS1_PI_31_DATA 0x00000000 +#define DDRSS1_PI_32_DATA 0x00000000 +#define DDRSS1_PI_33_DATA 0x01010102 +#define DDRSS1_PI_34_DATA 0x00000000 +#define DDRSS1_PI_35_DATA 0x000000AA +#define DDRSS1_PI_36_DATA 0x00000055 +#define DDRSS1_PI_37_DATA 0x000000B5 +#define DDRSS1_PI_38_DATA 0x0000004A +#define DDRSS1_PI_39_DATA 0x00000056 +#define DDRSS1_PI_40_DATA 0x000000A9 +#define DDRSS1_PI_41_DATA 0x000000A9 +#define DDRSS1_PI_42_DATA 0x000000B5 +#define DDRSS1_PI_43_DATA 0x00000000 +#define DDRSS1_PI_44_DATA 0x00000000 +#define DDRSS1_PI_45_DATA 0x000F0F00 +#define DDRSS1_PI_46_DATA 0x0000001B +#define DDRSS1_PI_47_DATA 0x000007D0 +#define DDRSS1_PI_48_DATA 0x00000300 +#define DDRSS1_PI_49_DATA 0x00000000 +#define DDRSS1_PI_50_DATA 0x00000000 +#define DDRSS1_PI_51_DATA 0x01000000 +#define DDRSS1_PI_52_DATA 0x00010101 +#define DDRSS1_PI_53_DATA 0x00000000 +#define DDRSS1_PI_54_DATA 0x00030000 +#define DDRSS1_PI_55_DATA 0x0F000000 +#define DDRSS1_PI_56_DATA 0x00000017 +#define DDRSS1_PI_57_DATA 0x00000000 +#define DDRSS1_PI_58_DATA 0x00000000 +#define DDRSS1_PI_59_DATA 0x00000000 +#define DDRSS1_PI_60_DATA 0x0A0A140A +#define DDRSS1_PI_61_DATA 0x10020201 +#define DDRSS1_PI_62_DATA 0x00020805 +#define DDRSS1_PI_63_DATA 0x01000404 +#define DDRSS1_PI_64_DATA 0x00000000 +#define DDRSS1_PI_65_DATA 0x00000000 +#define DDRSS1_PI_66_DATA 0x00000100 +#define DDRSS1_PI_67_DATA 0x0002020F +#define DDRSS1_PI_68_DATA 0x00340000 +#define DDRSS1_PI_69_DATA 0x00000000 +#define DDRSS1_PI_70_DATA 0x00000000 +#define DDRSS1_PI_71_DATA 0x0000FFFF +#define DDRSS1_PI_72_DATA 0x01000000 +#define DDRSS1_PI_73_DATA 0x00080000 +#define DDRSS1_PI_74_DATA 0x02000200 +#define DDRSS1_PI_75_DATA 0x01000100 +#define DDRSS1_PI_76_DATA 0x01000000 +#define DDRSS1_PI_77_DATA 0x02000200 +#define DDRSS1_PI_78_DATA 0x00000200 +#define DDRSS1_PI_79_DATA 0x00000000 +#define DDRSS1_PI_80_DATA 0x00000000 +#define DDRSS1_PI_81_DATA 0x00000000 +#define DDRSS1_PI_82_DATA 0x00000000 +#define DDRSS1_PI_83_DATA 0x00000000 +#define DDRSS1_PI_84_DATA 0x00000000 +#define DDRSS1_PI_85_DATA 0x00000000 +#define DDRSS1_PI_86_DATA 0x00000000 +#define DDRSS1_PI_87_DATA 0x00000000 +#define DDRSS1_PI_88_DATA 0x00000000 +#define DDRSS1_PI_89_DATA 0x00000000 +#define DDRSS1_PI_90_DATA 0x00000000 +#define DDRSS1_PI_91_DATA 0x00000400 +#define DDRSS1_PI_92_DATA 0x02010000 +#define DDRSS1_PI_93_DATA 0x00080003 +#define DDRSS1_PI_94_DATA 0x00080000 +#define DDRSS1_PI_95_DATA 0x00000001 +#define DDRSS1_PI_96_DATA 0x00000000 +#define DDRSS1_PI_97_DATA 0x0000AA00 +#define DDRSS1_PI_98_DATA 0x00000000 +#define DDRSS1_PI_99_DATA 0x00000000 +#define DDRSS1_PI_100_DATA 0x00010000 +#define DDRSS1_PI_101_DATA 0x00000000 +#define DDRSS1_PI_102_DATA 0x00000000 +#define DDRSS1_PI_103_DATA 0x00000000 +#define DDRSS1_PI_104_DATA 0x00000000 +#define DDRSS1_PI_105_DATA 0x00000000 +#define DDRSS1_PI_106_DATA 0x00000000 +#define DDRSS1_PI_107_DATA 0x00000000 +#define DDRSS1_PI_108_DATA 0x00000000 +#define DDRSS1_PI_109_DATA 0x00000000 +#define DDRSS1_PI_110_DATA 0x00000000 +#define DDRSS1_PI_111_DATA 0x00000000 +#define DDRSS1_PI_112_DATA 0x00000000 +#define DDRSS1_PI_113_DATA 0x00000000 +#define DDRSS1_PI_114_DATA 0x00000000 +#define DDRSS1_PI_115_DATA 0x00000000 +#define DDRSS1_PI_116_DATA 0x00000000 +#define DDRSS1_PI_117_DATA 0x00000000 +#define DDRSS1_PI_118_DATA 0x00000000 +#define DDRSS1_PI_119_DATA 0x00000000 +#define DDRSS1_PI_120_DATA 0x00000000 +#define DDRSS1_PI_121_DATA 0x00000000 +#define DDRSS1_PI_122_DATA 0x00000000 +#define DDRSS1_PI_123_DATA 0x00000000 +#define DDRSS1_PI_124_DATA 0x00000000 +#define DDRSS1_PI_125_DATA 0x00000008 +#define DDRSS1_PI_126_DATA 0x00000000 +#define DDRSS1_PI_127_DATA 0x00000000 +#define DDRSS1_PI_128_DATA 0x00000000 +#define DDRSS1_PI_129_DATA 0x00000000 +#define DDRSS1_PI_130_DATA 0x00000000 +#define DDRSS1_PI_131_DATA 0x00000000 +#define DDRSS1_PI_132_DATA 0x00000000 +#define DDRSS1_PI_133_DATA 0x00000000 +#define DDRSS1_PI_134_DATA 0x00000002 +#define DDRSS1_PI_135_DATA 0x00000000 +#define DDRSS1_PI_136_DATA 0x00000000 +#define DDRSS1_PI_137_DATA 0x0000000A +#define DDRSS1_PI_138_DATA 0x00000019 +#define DDRSS1_PI_139_DATA 0x00000100 +#define DDRSS1_PI_140_DATA 0x00000000 +#define DDRSS1_PI_141_DATA 0x00000000 +#define DDRSS1_PI_142_DATA 0x00000000 +#define DDRSS1_PI_143_DATA 0x00000000 +#define DDRSS1_PI_144_DATA 0x01000000 +#define DDRSS1_PI_145_DATA 0x00010003 +#define DDRSS1_PI_146_DATA 0x02000101 +#define DDRSS1_PI_147_DATA 0x01030001 +#define DDRSS1_PI_148_DATA 0x00010400 +#define DDRSS1_PI_149_DATA 0x06000105 +#define DDRSS1_PI_150_DATA 0x01070001 +#define DDRSS1_PI_151_DATA 0x00000000 +#define DDRSS1_PI_152_DATA 0x00000000 +#define DDRSS1_PI_153_DATA 0x00000000 +#define DDRSS1_PI_154_DATA 0x00010001 +#define DDRSS1_PI_155_DATA 0x00000000 +#define DDRSS1_PI_156_DATA 0x00000000 +#define DDRSS1_PI_157_DATA 0x00000000 +#define DDRSS1_PI_158_DATA 0x00000000 +#define DDRSS1_PI_159_DATA 0x00000401 +#define DDRSS1_PI_160_DATA 0x00000000 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 +#define DDRSS1_PI_164_DATA 0x00000034 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 +#define DDRSS1_PI_167_DATA 0x02000200 +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 +#define DDRSS1_PI_171_DATA 0x0000032B +#define DDRSS1_PI_172_DATA 0x00001035 +#define DDRSS1_PI_173_DATA 0x0000032B +#define DDRSS1_PI_174_DATA 0x04001035 +#define DDRSS1_PI_175_DATA 0x01010404 +#define DDRSS1_PI_176_DATA 0x00001500 +#define DDRSS1_PI_177_DATA 0x00150015 +#define DDRSS1_PI_178_DATA 0x01000100 +#define DDRSS1_PI_179_DATA 0x00000100 +#define DDRSS1_PI_180_DATA 0x00000000 +#define DDRSS1_PI_181_DATA 0x01010101 +#define DDRSS1_PI_182_DATA 0x00000000 +#define DDRSS1_PI_183_DATA 0x00000000 +#define DDRSS1_PI_184_DATA 0x00000000 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 +#define DDRSS1_PI_187_DATA 0x00040402 +#define DDRSS1_PI_188_DATA 0x000D0035 +#define DDRSS1_PI_189_DATA 0x00218049 +#define DDRSS1_PI_190_DATA 0x00218049 +#define DDRSS1_PI_191_DATA 0x01000101 +#define DDRSS1_PI_192_DATA 0x0004000E +#define DDRSS1_PI_193_DATA 0x00040216 +#define DDRSS1_PI_194_DATA 0x01000216 +#define DDRSS1_PI_195_DATA 0x000F000F +#define DDRSS1_PI_196_DATA 0x02170100 +#define DDRSS1_PI_197_DATA 0x01000217 +#define DDRSS1_PI_198_DATA 0x02170217 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B +#define DDRSS1_PI_201_DATA 0x0A070601 +#define DDRSS1_PI_202_DATA 0x1F130A0D +#define DDRSS1_PI_203_DATA 0x1F130A14 +#define DDRSS1_PI_204_DATA 0x0000C014 +#define DDRSS1_PI_205_DATA 0x00C01000 +#define DDRSS1_PI_206_DATA 0x00C01000 +#define DDRSS1_PI_207_DATA 0x00021000 +#define DDRSS1_PI_208_DATA 0x0024000E +#define DDRSS1_PI_209_DATA 0x00240216 +#define DDRSS1_PI_210_DATA 0x00110216 +#define DDRSS1_PI_211_DATA 0x32000056 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 +#define DDRSS1_PI_214_DATA 0x03013212 +#define DDRSS1_PI_215_DATA 0x00003600 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 +#define DDRSS1_PI_220_DATA 0x0A032001 +#define DDRSS1_PI_221_DATA 0x2C31110A +#define DDRSS1_PI_222_DATA 0x00002918 +#define DDRSS1_PI_223_DATA 0x6000838E +#define DDRSS1_PI_224_DATA 0x1E202008 +#define DDRSS1_PI_225_DATA 0x2C311116 +#define DDRSS1_PI_226_DATA 0x00002918 +#define DDRSS1_PI_227_DATA 0x6000838E +#define DDRSS1_PI_228_DATA 0x1E202008 +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 +#define DDRSS1_PI_235_DATA 0x033B0016 +#define DDRSS1_PI_236_DATA 0x0303033B +#define DDRSS1_PI_237_DATA 0x002AF803 +#define DDRSS1_PI_238_DATA 0x0001ADAF +#define DDRSS1_PI_239_DATA 0x00000005 +#define DDRSS1_PI_240_DATA 0x0000006E +#define DDRSS1_PI_241_DATA 0x00000016 +#define DDRSS1_PI_242_DATA 0x000681C8 +#define DDRSS1_PI_243_DATA 0x0001ADAF +#define DDRSS1_PI_244_DATA 0x00000005 +#define DDRSS1_PI_245_DATA 0x000010A9 +#define DDRSS1_PI_246_DATA 0x0000033B +#define DDRSS1_PI_247_DATA 0x000681C8 +#define DDRSS1_PI_248_DATA 0x0001ADAF +#define DDRSS1_PI_249_DATA 0x00000005 +#define DDRSS1_PI_250_DATA 0x000010A9 +#define DDRSS1_PI_251_DATA 0x0100033B +#define DDRSS1_PI_252_DATA 0x00370040 +#define DDRSS1_PI_253_DATA 0x00010008 +#define DDRSS1_PI_254_DATA 0x08550040 +#define DDRSS1_PI_255_DATA 0x00010040 +#define DDRSS1_PI_256_DATA 0x08550040 +#define DDRSS1_PI_257_DATA 0x00000340 +#define DDRSS1_PI_258_DATA 0x006B006B +#define DDRSS1_PI_259_DATA 0x08040404 +#define DDRSS1_PI_260_DATA 0x00000055 +#define DDRSS1_PI_261_DATA 0x55083C5A +#define DDRSS1_PI_262_DATA 0x5A000000 +#define DDRSS1_PI_263_DATA 0x0055083C +#define DDRSS1_PI_264_DATA 0x3C5A0000 +#define DDRSS1_PI_265_DATA 0x00005508 +#define DDRSS1_PI_266_DATA 0x0C3C5A00 +#define DDRSS1_PI_267_DATA 0x080F0E0D +#define DDRSS1_PI_268_DATA 0x000B0A09 +#define DDRSS1_PI_269_DATA 0x00030201 +#define DDRSS1_PI_270_DATA 0x01000000 +#define DDRSS1_PI_271_DATA 0x04020201 +#define DDRSS1_PI_272_DATA 0x00080804 +#define DDRSS1_PI_273_DATA 0x00000000 +#define DDRSS1_PI_274_DATA 0x00000000 +#define DDRSS1_PI_275_DATA 0x00F30084 +#define DDRSS1_PI_276_DATA 0x00160000 +#define DDRSS1_PI_277_DATA 0x36F33FF4 +#define DDRSS1_PI_278_DATA 0x00160F27 +#define DDRSS1_PI_279_DATA 0x36F33FF4 +#define DDRSS1_PI_280_DATA 0x00160F27 +#define DDRSS1_PI_281_DATA 0x00F30084 +#define DDRSS1_PI_282_DATA 0x00160000 +#define DDRSS1_PI_283_DATA 0x36F33FF4 +#define DDRSS1_PI_284_DATA 0x00160F27 +#define DDRSS1_PI_285_DATA 0x36F33FF4 +#define DDRSS1_PI_286_DATA 0x00160F27 +#define DDRSS1_PI_287_DATA 0x00F30084 +#define DDRSS1_PI_288_DATA 0x00160000 +#define DDRSS1_PI_289_DATA 0x36F33FF4 +#define DDRSS1_PI_290_DATA 0x00160F27 +#define DDRSS1_PI_291_DATA 0x36F33FF4 +#define DDRSS1_PI_292_DATA 0x00160F27 +#define DDRSS1_PI_293_DATA 0x00F30084 +#define DDRSS1_PI_294_DATA 0x00160000 +#define DDRSS1_PI_295_DATA 0x36F33FF4 +#define DDRSS1_PI_296_DATA 0x00160F27 +#define DDRSS1_PI_297_DATA 0x36F33FF4 +#define DDRSS1_PI_298_DATA 0x00160F27 +#define DDRSS1_PI_299_DATA 0x00000000 + +#define DDRSS1_PHY_00_DATA 0x000004F0 +#define DDRSS1_PHY_01_DATA 0x00000000 +#define DDRSS1_PHY_02_DATA 0x00030200 +#define DDRSS1_PHY_03_DATA 0x00000000 +#define DDRSS1_PHY_04_DATA 0x00000000 +#define DDRSS1_PHY_05_DATA 0x01030000 +#define DDRSS1_PHY_06_DATA 0x00010000 +#define DDRSS1_PHY_07_DATA 0x01030004 +#define DDRSS1_PHY_08_DATA 0x01000000 +#define DDRSS1_PHY_09_DATA 0x00000000 +#define DDRSS1_PHY_10_DATA 0x00000000 +#define DDRSS1_PHY_11_DATA 0x01000001 +#define DDRSS1_PHY_12_DATA 0x00000200 +#define DDRSS1_PHY_13_DATA 0x000800C0 +#define DDRSS1_PHY_14_DATA 0x060100CC +#define DDRSS1_PHY_15_DATA 0x00030066 +#define DDRSS1_PHY_16_DATA 0x00000000 +#define DDRSS1_PHY_17_DATA 0x00000301 +#define DDRSS1_PHY_18_DATA 0x0000AAAA +#define DDRSS1_PHY_19_DATA 0x00005555 +#define DDRSS1_PHY_20_DATA 0x0000B5B5 +#define DDRSS1_PHY_21_DATA 0x00004A4A +#define DDRSS1_PHY_22_DATA 0x00005656 +#define DDRSS1_PHY_23_DATA 0x0000A9A9 +#define DDRSS1_PHY_24_DATA 0x0000A9A9 +#define DDRSS1_PHY_25_DATA 0x0000B5B5 +#define DDRSS1_PHY_26_DATA 0x00000000 +#define DDRSS1_PHY_27_DATA 0x00000000 +#define DDRSS1_PHY_28_DATA 0x2A000000 +#define DDRSS1_PHY_29_DATA 0x00000808 +#define DDRSS1_PHY_30_DATA 0x0F000000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 +#define DDRSS1_PHY_33_DATA 0x0C002006 +#define DDRSS1_PHY_34_DATA 0x00000000 +#define DDRSS1_PHY_35_DATA 0x00000000 +#define DDRSS1_PHY_36_DATA 0x55555555 +#define DDRSS1_PHY_37_DATA 0xAAAAAAAA +#define DDRSS1_PHY_38_DATA 0x55555555 +#define DDRSS1_PHY_39_DATA 0xAAAAAAAA +#define DDRSS1_PHY_40_DATA 0x00005555 +#define DDRSS1_PHY_41_DATA 0x01000100 +#define DDRSS1_PHY_42_DATA 0x00800180 +#define DDRSS1_PHY_43_DATA 0x00000001 +#define DDRSS1_PHY_44_DATA 0x00000000 +#define DDRSS1_PHY_45_DATA 0x00000000 +#define DDRSS1_PHY_46_DATA 0x00000000 +#define DDRSS1_PHY_47_DATA 0x00000000 +#define DDRSS1_PHY_48_DATA 0x00000000 +#define DDRSS1_PHY_49_DATA 0x00000000 +#define DDRSS1_PHY_50_DATA 0x00000000 +#define DDRSS1_PHY_51_DATA 0x00000000 +#define DDRSS1_PHY_52_DATA 0x00000000 +#define DDRSS1_PHY_53_DATA 0x00000000 +#define DDRSS1_PHY_54_DATA 0x00000000 +#define DDRSS1_PHY_55_DATA 0x00000000 +#define DDRSS1_PHY_56_DATA 0x00000000 +#define DDRSS1_PHY_57_DATA 0x00000000 +#define DDRSS1_PHY_58_DATA 0x00000000 +#define DDRSS1_PHY_59_DATA 0x00000000 +#define DDRSS1_PHY_60_DATA 0x00000000 +#define DDRSS1_PHY_61_DATA 0x00000000 +#define DDRSS1_PHY_62_DATA 0x00000000 +#define DDRSS1_PHY_63_DATA 0x00000000 +#define DDRSS1_PHY_64_DATA 0x00000000 +#define DDRSS1_PHY_65_DATA 0x00000000 +#define DDRSS1_PHY_66_DATA 0x00000104 +#define DDRSS1_PHY_67_DATA 0x00000120 +#define DDRSS1_PHY_68_DATA 0x00000000 +#define DDRSS1_PHY_69_DATA 0x00000000 +#define DDRSS1_PHY_70_DATA 0x00000000 +#define DDRSS1_PHY_71_DATA 0x00000000 +#define DDRSS1_PHY_72_DATA 0x00000000 +#define DDRSS1_PHY_73_DATA 0x00000000 +#define DDRSS1_PHY_74_DATA 0x00000000 +#define DDRSS1_PHY_75_DATA 0x00000001 +#define DDRSS1_PHY_76_DATA 0x07FF0000 +#define DDRSS1_PHY_77_DATA 0x0080081F +#define DDRSS1_PHY_78_DATA 0x00081020 +#define DDRSS1_PHY_79_DATA 0x04010000 +#define DDRSS1_PHY_80_DATA 0x00000000 +#define DDRSS1_PHY_81_DATA 0x00000000 +#define DDRSS1_PHY_82_DATA 0x00000000 +#define DDRSS1_PHY_83_DATA 0x00000100 +#define DDRSS1_PHY_84_DATA 0x01CC0C01 +#define DDRSS1_PHY_85_DATA 0x1003CC0C +#define DDRSS1_PHY_86_DATA 0x20000140 +#define DDRSS1_PHY_87_DATA 0x07FF0200 +#define DDRSS1_PHY_88_DATA 0x0000DD01 +#define DDRSS1_PHY_89_DATA 0x10100303 +#define DDRSS1_PHY_90_DATA 0x10101010 +#define DDRSS1_PHY_91_DATA 0x10101010 +#define DDRSS1_PHY_92_DATA 0x00021010 +#define DDRSS1_PHY_93_DATA 0x00100010 +#define DDRSS1_PHY_94_DATA 0x00100010 +#define DDRSS1_PHY_95_DATA 0x00100010 +#define DDRSS1_PHY_96_DATA 0x00100010 +#define DDRSS1_PHY_97_DATA 0x00050010 +#define DDRSS1_PHY_98_DATA 0x51517041 +#define DDRSS1_PHY_99_DATA 0x31C06001 +#define DDRSS1_PHY_100_DATA 0x07AB01AB +#define DDRSS1_PHY_101_DATA 0x00C0C001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 +#define DDRSS1_PHY_103_DATA 0x10001000 +#define DDRSS1_PHY_104_DATA 0x0C083E42 +#define DDRSS1_PHY_105_DATA 0x0F0C3701 +#define DDRSS1_PHY_106_DATA 0x01000140 +#define DDRSS1_PHY_107_DATA 0x0C000420 +#define DDRSS1_PHY_108_DATA 0x00000198 +#define DDRSS1_PHY_109_DATA 0x0A0000D0 +#define DDRSS1_PHY_110_DATA 0x00030200 +#define DDRSS1_PHY_111_DATA 0x02800000 +#define DDRSS1_PHY_112_DATA 0x80800000 +#define DDRSS1_PHY_113_DATA 0x000E2010 +#define DDRSS1_PHY_114_DATA 0x76543210 +#define DDRSS1_PHY_115_DATA 0x00000008 +#define DDRSS1_PHY_116_DATA 0x02800280 +#define DDRSS1_PHY_117_DATA 0x02800280 +#define DDRSS1_PHY_118_DATA 0x02800280 +#define DDRSS1_PHY_119_DATA 0x02800280 +#define DDRSS1_PHY_120_DATA 0x00000280 +#define DDRSS1_PHY_121_DATA 0x0000A000 +#define DDRSS1_PHY_122_DATA 0x00A000A0 +#define DDRSS1_PHY_123_DATA 0x00A000A0 +#define DDRSS1_PHY_124_DATA 0x00A000A0 +#define DDRSS1_PHY_125_DATA 0x00A000A0 +#define DDRSS1_PHY_126_DATA 0x00A000A0 +#define DDRSS1_PHY_127_DATA 0x00A000A0 +#define DDRSS1_PHY_128_DATA 0x00A000A0 +#define DDRSS1_PHY_129_DATA 0x00A000A0 +#define DDRSS1_PHY_130_DATA 0x01C200A0 +#define DDRSS1_PHY_131_DATA 0x01A00005 +#define DDRSS1_PHY_132_DATA 0x00000000 +#define DDRSS1_PHY_133_DATA 0x00000000 +#define DDRSS1_PHY_134_DATA 0x00080200 +#define DDRSS1_PHY_135_DATA 0x00000000 +#define DDRSS1_PHY_136_DATA 0x20202020 +#define DDRSS1_PHY_137_DATA 0x20202020 +#define DDRSS1_PHY_138_DATA 0xF0F02020 +#define DDRSS1_PHY_139_DATA 0x00000000 +#define DDRSS1_PHY_140_DATA 0x00000000 +#define DDRSS1_PHY_141_DATA 0x00000000 +#define DDRSS1_PHY_142_DATA 0x00000000 +#define DDRSS1_PHY_143_DATA 0x00000000 +#define DDRSS1_PHY_144_DATA 0x00000000 +#define DDRSS1_PHY_145_DATA 0x00000000 +#define DDRSS1_PHY_146_DATA 0x00000000 +#define DDRSS1_PHY_147_DATA 0x00000000 +#define DDRSS1_PHY_148_DATA 0x00000000 +#define DDRSS1_PHY_149_DATA 0x00000000 +#define DDRSS1_PHY_150_DATA 0x00000000 +#define DDRSS1_PHY_151_DATA 0x00000000 +#define DDRSS1_PHY_152_DATA 0x00000000 +#define DDRSS1_PHY_153_DATA 0x00000000 +#define DDRSS1_PHY_154_DATA 0x00000000 +#define DDRSS1_PHY_155_DATA 0x00000000 +#define DDRSS1_PHY_156_DATA 0x00000000 +#define DDRSS1_PHY_157_DATA 0x00000000 +#define DDRSS1_PHY_158_DATA 0x00000000 +#define DDRSS1_PHY_159_DATA 0x00000000 +#define DDRSS1_PHY_160_DATA 0x00000000 +#define DDRSS1_PHY_161_DATA 0x00000000 +#define DDRSS1_PHY_162_DATA 0x00000000 +#define DDRSS1_PHY_163_DATA 0x00000000 +#define DDRSS1_PHY_164_DATA 0x00000000 +#define DDRSS1_PHY_165_DATA 0x00000000 +#define DDRSS1_PHY_166_DATA 0x00000000 +#define DDRSS1_PHY_167_DATA 0x00000000 +#define DDRSS1_PHY_168_DATA 0x00000000 +#define DDRSS1_PHY_169_DATA 0x00000000 +#define DDRSS1_PHY_170_DATA 0x00000000 +#define DDRSS1_PHY_171_DATA 0x00000000 +#define DDRSS1_PHY_172_DATA 0x00000000 +#define DDRSS1_PHY_173_DATA 0x00000000 +#define DDRSS1_PHY_174_DATA 0x00000000 +#define DDRSS1_PHY_175_DATA 0x00000000 +#define DDRSS1_PHY_176_DATA 0x00000000 +#define DDRSS1_PHY_177_DATA 0x00000000 +#define DDRSS1_PHY_178_DATA 0x00000000 +#define DDRSS1_PHY_179_DATA 0x00000000 +#define DDRSS1_PHY_180_DATA 0x00000000 +#define DDRSS1_PHY_181_DATA 0x00000000 +#define DDRSS1_PHY_182_DATA 0x00000000 +#define DDRSS1_PHY_183_DATA 0x00000000 +#define DDRSS1_PHY_184_DATA 0x00000000 +#define DDRSS1_PHY_185_DATA 0x00000000 +#define DDRSS1_PHY_186_DATA 0x00000000 +#define DDRSS1_PHY_187_DATA 0x00000000 +#define DDRSS1_PHY_188_DATA 0x00000000 +#define DDRSS1_PHY_189_DATA 0x00000000 +#define DDRSS1_PHY_190_DATA 0x00000000 +#define DDRSS1_PHY_191_DATA 0x00000000 +#define DDRSS1_PHY_192_DATA 0x00000000 +#define DDRSS1_PHY_193_DATA 0x00000000 +#define DDRSS1_PHY_194_DATA 0x00000000 +#define DDRSS1_PHY_195_DATA 0x00000000 +#define DDRSS1_PHY_196_DATA 0x00000000 +#define DDRSS1_PHY_197_DATA 0x00000000 +#define DDRSS1_PHY_198_DATA 0x00000000 +#define DDRSS1_PHY_199_DATA 0x00000000 +#define DDRSS1_PHY_200_DATA 0x00000000 +#define DDRSS1_PHY_201_DATA 0x00000000 +#define DDRSS1_PHY_202_DATA 0x00000000 +#define DDRSS1_PHY_203_DATA 0x00000000 +#define DDRSS1_PHY_204_DATA 0x00000000 +#define DDRSS1_PHY_205_DATA 0x00000000 +#define DDRSS1_PHY_206_DATA 0x00000000 +#define DDRSS1_PHY_207_DATA 0x00000000 +#define DDRSS1_PHY_208_DATA 0x00000000 +#define DDRSS1_PHY_209_DATA 0x00000000 +#define DDRSS1_PHY_210_DATA 0x00000000 +#define DDRSS1_PHY_211_DATA 0x00000000 +#define DDRSS1_PHY_212_DATA 0x00000000 +#define DDRSS1_PHY_213_DATA 0x00000000 +#define DDRSS1_PHY_214_DATA 0x00000000 +#define DDRSS1_PHY_215_DATA 0x00000000 +#define DDRSS1_PHY_216_DATA 0x00000000 +#define DDRSS1_PHY_217_DATA 0x00000000 +#define DDRSS1_PHY_218_DATA 0x00000000 +#define DDRSS1_PHY_219_DATA 0x00000000 +#define DDRSS1_PHY_220_DATA 0x00000000 +#define DDRSS1_PHY_221_DATA 0x00000000 +#define DDRSS1_PHY_222_DATA 0x00000000 +#define DDRSS1_PHY_223_DATA 0x00000000 +#define DDRSS1_PHY_224_DATA 0x00000000 +#define DDRSS1_PHY_225_DATA 0x00000000 +#define DDRSS1_PHY_226_DATA 0x00000000 +#define DDRSS1_PHY_227_DATA 0x00000000 +#define DDRSS1_PHY_228_DATA 0x00000000 +#define DDRSS1_PHY_229_DATA 0x00000000 +#define DDRSS1_PHY_230_DATA 0x00000000 +#define DDRSS1_PHY_231_DATA 0x00000000 +#define DDRSS1_PHY_232_DATA 0x00000000 +#define DDRSS1_PHY_233_DATA 0x00000000 +#define DDRSS1_PHY_234_DATA 0x00000000 +#define DDRSS1_PHY_235_DATA 0x00000000 +#define DDRSS1_PHY_236_DATA 0x00000000 +#define DDRSS1_PHY_237_DATA 0x00000000 +#define DDRSS1_PHY_238_DATA 0x00000000 +#define DDRSS1_PHY_239_DATA 0x00000000 +#define DDRSS1_PHY_240_DATA 0x00000000 +#define DDRSS1_PHY_241_DATA 0x00000000 +#define DDRSS1_PHY_242_DATA 0x00000000 +#define DDRSS1_PHY_243_DATA 0x00000000 +#define DDRSS1_PHY_244_DATA 0x00000000 +#define DDRSS1_PHY_245_DATA 0x00000000 +#define DDRSS1_PHY_246_DATA 0x00000000 +#define DDRSS1_PHY_247_DATA 0x00000000 +#define DDRSS1_PHY_248_DATA 0x00000000 +#define DDRSS1_PHY_249_DATA 0x00000000 +#define DDRSS1_PHY_250_DATA 0x00000000 +#define DDRSS1_PHY_251_DATA 0x00000000 +#define DDRSS1_PHY_252_DATA 0x00000000 +#define DDRSS1_PHY_253_DATA 0x00000000 +#define DDRSS1_PHY_254_DATA 0x00000000 +#define DDRSS1_PHY_255_DATA 0x00000000 +#define DDRSS1_PHY_256_DATA 0x000004F0 +#define DDRSS1_PHY_257_DATA 0x00000000 +#define DDRSS1_PHY_258_DATA 0x00030200 +#define DDRSS1_PHY_259_DATA 0x00000000 +#define DDRSS1_PHY_260_DATA 0x00000000 +#define DDRSS1_PHY_261_DATA 0x01030000 +#define DDRSS1_PHY_262_DATA 0x00010000 +#define DDRSS1_PHY_263_DATA 0x01030004 +#define DDRSS1_PHY_264_DATA 0x01000000 +#define DDRSS1_PHY_265_DATA 0x00000000 +#define DDRSS1_PHY_266_DATA 0x00000000 +#define DDRSS1_PHY_267_DATA 0x01000001 +#define DDRSS1_PHY_268_DATA 0x00000200 +#define DDRSS1_PHY_269_DATA 0x000800C0 +#define DDRSS1_PHY_270_DATA 0x060100CC +#define DDRSS1_PHY_271_DATA 0x00030066 +#define DDRSS1_PHY_272_DATA 0x00000000 +#define DDRSS1_PHY_273_DATA 0x00000301 +#define DDRSS1_PHY_274_DATA 0x0000AAAA +#define DDRSS1_PHY_275_DATA 0x00005555 +#define DDRSS1_PHY_276_DATA 0x0000B5B5 +#define DDRSS1_PHY_277_DATA 0x00004A4A +#define DDRSS1_PHY_278_DATA 0x00005656 +#define DDRSS1_PHY_279_DATA 0x0000A9A9 +#define DDRSS1_PHY_280_DATA 0x0000A9A9 +#define DDRSS1_PHY_281_DATA 0x0000B5B5 +#define DDRSS1_PHY_282_DATA 0x00000000 +#define DDRSS1_PHY_283_DATA 0x00000000 +#define DDRSS1_PHY_284_DATA 0x2A000000 +#define DDRSS1_PHY_285_DATA 0x00000808 +#define DDRSS1_PHY_286_DATA 0x0F000000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 +#define DDRSS1_PHY_289_DATA 0x0C002006 +#define DDRSS1_PHY_290_DATA 0x00000000 +#define DDRSS1_PHY_291_DATA 0x00000000 +#define DDRSS1_PHY_292_DATA 0x55555555 +#define DDRSS1_PHY_293_DATA 0xAAAAAAAA +#define DDRSS1_PHY_294_DATA 0x55555555 +#define DDRSS1_PHY_295_DATA 0xAAAAAAAA +#define DDRSS1_PHY_296_DATA 0x00005555 +#define DDRSS1_PHY_297_DATA 0x01000100 +#define DDRSS1_PHY_298_DATA 0x00800180 +#define DDRSS1_PHY_299_DATA 0x00000000 +#define DDRSS1_PHY_300_DATA 0x00000000 +#define DDRSS1_PHY_301_DATA 0x00000000 +#define DDRSS1_PHY_302_DATA 0x00000000 +#define DDRSS1_PHY_303_DATA 0x00000000 +#define DDRSS1_PHY_304_DATA 0x00000000 +#define DDRSS1_PHY_305_DATA 0x00000000 +#define DDRSS1_PHY_306_DATA 0x00000000 +#define DDRSS1_PHY_307_DATA 0x00000000 +#define DDRSS1_PHY_308_DATA 0x00000000 +#define DDRSS1_PHY_309_DATA 0x00000000 +#define DDRSS1_PHY_310_DATA 0x00000000 +#define DDRSS1_PHY_311_DATA 0x00000000 +#define DDRSS1_PHY_312_DATA 0x00000000 +#define DDRSS1_PHY_313_DATA 0x00000000 +#define DDRSS1_PHY_314_DATA 0x00000000 +#define DDRSS1_PHY_315_DATA 0x00000000 +#define DDRSS1_PHY_316_DATA 0x00000000 +#define DDRSS1_PHY_317_DATA 0x00000000 +#define DDRSS1_PHY_318_DATA 0x00000000 +#define DDRSS1_PHY_319_DATA 0x00000000 +#define DDRSS1_PHY_320_DATA 0x00000000 +#define DDRSS1_PHY_321_DATA 0x00000000 +#define DDRSS1_PHY_322_DATA 0x00000104 +#define DDRSS1_PHY_323_DATA 0x00000120 +#define DDRSS1_PHY_324_DATA 0x00000000 +#define DDRSS1_PHY_325_DATA 0x00000000 +#define DDRSS1_PHY_326_DATA 0x00000000 +#define DDRSS1_PHY_327_DATA 0x00000000 +#define DDRSS1_PHY_328_DATA 0x00000000 +#define DDRSS1_PHY_329_DATA 0x00000000 +#define DDRSS1_PHY_330_DATA 0x00000000 +#define DDRSS1_PHY_331_DATA 0x00000001 +#define DDRSS1_PHY_332_DATA 0x07FF0000 +#define DDRSS1_PHY_333_DATA 0x0080081F +#define DDRSS1_PHY_334_DATA 0x00081020 +#define DDRSS1_PHY_335_DATA 0x04010000 +#define DDRSS1_PHY_336_DATA 0x00000000 +#define DDRSS1_PHY_337_DATA 0x00000000 +#define DDRSS1_PHY_338_DATA 0x00000000 +#define DDRSS1_PHY_339_DATA 0x00000100 +#define DDRSS1_PHY_340_DATA 0x01CC0C01 +#define DDRSS1_PHY_341_DATA 0x1003CC0C +#define DDRSS1_PHY_342_DATA 0x20000140 +#define DDRSS1_PHY_343_DATA 0x07FF0200 +#define DDRSS1_PHY_344_DATA 0x0000DD01 +#define DDRSS1_PHY_345_DATA 0x10100303 +#define DDRSS1_PHY_346_DATA 0x10101010 +#define DDRSS1_PHY_347_DATA 0x10101010 +#define DDRSS1_PHY_348_DATA 0x00021010 +#define DDRSS1_PHY_349_DATA 0x00100010 +#define DDRSS1_PHY_350_DATA 0x00100010 +#define DDRSS1_PHY_351_DATA 0x00100010 +#define DDRSS1_PHY_352_DATA 0x00100010 +#define DDRSS1_PHY_353_DATA 0x00050010 +#define DDRSS1_PHY_354_DATA 0x51517041 +#define DDRSS1_PHY_355_DATA 0x31C06001 +#define DDRSS1_PHY_356_DATA 0x07AB01AB +#define DDRSS1_PHY_357_DATA 0x00C0C001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 +#define DDRSS1_PHY_359_DATA 0x10001000 +#define DDRSS1_PHY_360_DATA 0x0C083E42 +#define DDRSS1_PHY_361_DATA 0x0F0C3701 +#define DDRSS1_PHY_362_DATA 0x01000140 +#define DDRSS1_PHY_363_DATA 0x0C000420 +#define DDRSS1_PHY_364_DATA 0x00000198 +#define DDRSS1_PHY_365_DATA 0x0A0000D0 +#define DDRSS1_PHY_366_DATA 0x00030200 +#define DDRSS1_PHY_367_DATA 0x02800000 +#define DDRSS1_PHY_368_DATA 0x80800000 +#define DDRSS1_PHY_369_DATA 0x000E2010 +#define DDRSS1_PHY_370_DATA 0x76543210 +#define DDRSS1_PHY_371_DATA 0x00000008 +#define DDRSS1_PHY_372_DATA 0x02800280 +#define DDRSS1_PHY_373_DATA 0x02800280 +#define DDRSS1_PHY_374_DATA 0x02800280 +#define DDRSS1_PHY_375_DATA 0x02800280 +#define DDRSS1_PHY_376_DATA 0x00000280 +#define DDRSS1_PHY_377_DATA 0x0000A000 +#define DDRSS1_PHY_378_DATA 0x00A000A0 +#define DDRSS1_PHY_379_DATA 0x00A000A0 +#define DDRSS1_PHY_380_DATA 0x00A000A0 +#define DDRSS1_PHY_381_DATA 0x00A000A0 +#define DDRSS1_PHY_382_DATA 0x00A000A0 +#define DDRSS1_PHY_383_DATA 0x00A000A0 +#define DDRSS1_PHY_384_DATA 0x00A000A0 +#define DDRSS1_PHY_385_DATA 0x00A000A0 +#define DDRSS1_PHY_386_DATA 0x01C200A0 +#define DDRSS1_PHY_387_DATA 0x01A00005 +#define DDRSS1_PHY_388_DATA 0x00000000 +#define DDRSS1_PHY_389_DATA 0x00000000 +#define DDRSS1_PHY_390_DATA 0x00080200 +#define DDRSS1_PHY_391_DATA 0x00000000 +#define DDRSS1_PHY_392_DATA 0x20202020 +#define DDRSS1_PHY_393_DATA 0x20202020 +#define DDRSS1_PHY_394_DATA 0xF0F02020 +#define DDRSS1_PHY_395_DATA 0x00000000 +#define DDRSS1_PHY_396_DATA 0x00000000 +#define DDRSS1_PHY_397_DATA 0x00000000 +#define DDRSS1_PHY_398_DATA 0x00000000 +#define DDRSS1_PHY_399_DATA 0x00000000 +#define DDRSS1_PHY_400_DATA 0x00000000 +#define DDRSS1_PHY_401_DATA 0x00000000 +#define DDRSS1_PHY_402_DATA 0x00000000 +#define DDRSS1_PHY_403_DATA 0x00000000 +#define DDRSS1_PHY_404_DATA 0x00000000 +#define DDRSS1_PHY_405_DATA 0x00000000 +#define DDRSS1_PHY_406_DATA 0x00000000 +#define DDRSS1_PHY_407_DATA 0x00000000 +#define DDRSS1_PHY_408_DATA 0x00000000 +#define DDRSS1_PHY_409_DATA 0x00000000 +#define DDRSS1_PHY_410_DATA 0x00000000 +#define DDRSS1_PHY_411_DATA 0x00000000 +#define DDRSS1_PHY_412_DATA 0x00000000 +#define DDRSS1_PHY_413_DATA 0x00000000 +#define DDRSS1_PHY_414_DATA 0x00000000 +#define DDRSS1_PHY_415_DATA 0x00000000 +#define DDRSS1_PHY_416_DATA 0x00000000 +#define DDRSS1_PHY_417_DATA 0x00000000 +#define DDRSS1_PHY_418_DATA 0x00000000 +#define DDRSS1_PHY_419_DATA 0x00000000 +#define DDRSS1_PHY_420_DATA 0x00000000 +#define DDRSS1_PHY_421_DATA 0x00000000 +#define DDRSS1_PHY_422_DATA 0x00000000 +#define DDRSS1_PHY_423_DATA 0x00000000 +#define DDRSS1_PHY_424_DATA 0x00000000 +#define DDRSS1_PHY_425_DATA 0x00000000 +#define DDRSS1_PHY_426_DATA 0x00000000 +#define DDRSS1_PHY_427_DATA 0x00000000 +#define DDRSS1_PHY_428_DATA 0x00000000 +#define DDRSS1_PHY_429_DATA 0x00000000 +#define DDRSS1_PHY_430_DATA 0x00000000 +#define DDRSS1_PHY_431_DATA 0x00000000 +#define DDRSS1_PHY_432_DATA 0x00000000 +#define DDRSS1_PHY_433_DATA 0x00000000 +#define DDRSS1_PHY_434_DATA 0x00000000 +#define DDRSS1_PHY_435_DATA 0x00000000 +#define DDRSS1_PHY_436_DATA 0x00000000 +#define DDRSS1_PHY_437_DATA 0x00000000 +#define DDRSS1_PHY_438_DATA 0x00000000 +#define DDRSS1_PHY_439_DATA 0x00000000 +#define DDRSS1_PHY_440_DATA 0x00000000 +#define DDRSS1_PHY_441_DATA 0x00000000 +#define DDRSS1_PHY_442_DATA 0x00000000 +#define DDRSS1_PHY_443_DATA 0x00000000 +#define DDRSS1_PHY_444_DATA 0x00000000 +#define DDRSS1_PHY_445_DATA 0x00000000 +#define DDRSS1_PHY_446_DATA 0x00000000 +#define DDRSS1_PHY_447_DATA 0x00000000 +#define DDRSS1_PHY_448_DATA 0x00000000 +#define DDRSS1_PHY_449_DATA 0x00000000 +#define DDRSS1_PHY_450_DATA 0x00000000 +#define DDRSS1_PHY_451_DATA 0x00000000 +#define DDRSS1_PHY_452_DATA 0x00000000 +#define DDRSS1_PHY_453_DATA 0x00000000 +#define DDRSS1_PHY_454_DATA 0x00000000 +#define DDRSS1_PHY_455_DATA 0x00000000 +#define DDRSS1_PHY_456_DATA 0x00000000 +#define DDRSS1_PHY_457_DATA 0x00000000 +#define DDRSS1_PHY_458_DATA 0x00000000 +#define DDRSS1_PHY_459_DATA 0x00000000 +#define DDRSS1_PHY_460_DATA 0x00000000 +#define DDRSS1_PHY_461_DATA 0x00000000 +#define DDRSS1_PHY_462_DATA 0x00000000 +#define DDRSS1_PHY_463_DATA 0x00000000 +#define DDRSS1_PHY_464_DATA 0x00000000 +#define DDRSS1_PHY_465_DATA 0x00000000 +#define DDRSS1_PHY_466_DATA 0x00000000 +#define DDRSS1_PHY_467_DATA 0x00000000 +#define DDRSS1_PHY_468_DATA 0x00000000 +#define DDRSS1_PHY_469_DATA 0x00000000 +#define DDRSS1_PHY_470_DATA 0x00000000 +#define DDRSS1_PHY_471_DATA 0x00000000 +#define DDRSS1_PHY_472_DATA 0x00000000 +#define DDRSS1_PHY_473_DATA 0x00000000 +#define DDRSS1_PHY_474_DATA 0x00000000 +#define DDRSS1_PHY_475_DATA 0x00000000 +#define DDRSS1_PHY_476_DATA 0x00000000 +#define DDRSS1_PHY_477_DATA 0x00000000 +#define DDRSS1_PHY_478_DATA 0x00000000 +#define DDRSS1_PHY_479_DATA 0x00000000 +#define DDRSS1_PHY_480_DATA 0x00000000 +#define DDRSS1_PHY_481_DATA 0x00000000 +#define DDRSS1_PHY_482_DATA 0x00000000 +#define DDRSS1_PHY_483_DATA 0x00000000 +#define DDRSS1_PHY_484_DATA 0x00000000 +#define DDRSS1_PHY_485_DATA 0x00000000 +#define DDRSS1_PHY_486_DATA 0x00000000 +#define DDRSS1_PHY_487_DATA 0x00000000 +#define DDRSS1_PHY_488_DATA 0x00000000 +#define DDRSS1_PHY_489_DATA 0x00000000 +#define DDRSS1_PHY_490_DATA 0x00000000 +#define DDRSS1_PHY_491_DATA 0x00000000 +#define DDRSS1_PHY_492_DATA 0x00000000 +#define DDRSS1_PHY_493_DATA 0x00000000 +#define DDRSS1_PHY_494_DATA 0x00000000 +#define DDRSS1_PHY_495_DATA 0x00000000 +#define DDRSS1_PHY_496_DATA 0x00000000 +#define DDRSS1_PHY_497_DATA 0x00000000 +#define DDRSS1_PHY_498_DATA 0x00000000 +#define DDRSS1_PHY_499_DATA 0x00000000 +#define DDRSS1_PHY_500_DATA 0x00000000 +#define DDRSS1_PHY_501_DATA 0x00000000 +#define DDRSS1_PHY_502_DATA 0x00000000 +#define DDRSS1_PHY_503_DATA 0x00000000 +#define DDRSS1_PHY_504_DATA 0x00000000 +#define DDRSS1_PHY_505_DATA 0x00000000 +#define DDRSS1_PHY_506_DATA 0x00000000 +#define DDRSS1_PHY_507_DATA 0x00000000 +#define DDRSS1_PHY_508_DATA 0x00000000 +#define DDRSS1_PHY_509_DATA 0x00000000 +#define DDRSS1_PHY_510_DATA 0x00000000 +#define DDRSS1_PHY_511_DATA 0x00000000 +#define DDRSS1_PHY_512_DATA 0x000004F0 +#define DDRSS1_PHY_513_DATA 0x00000000 +#define DDRSS1_PHY_514_DATA 0x00030200 +#define DDRSS1_PHY_515_DATA 0x00000000 +#define DDRSS1_PHY_516_DATA 0x00000000 +#define DDRSS1_PHY_517_DATA 0x01030000 +#define DDRSS1_PHY_518_DATA 0x00010000 +#define DDRSS1_PHY_519_DATA 0x01030004 +#define DDRSS1_PHY_520_DATA 0x01000000 +#define DDRSS1_PHY_521_DATA 0x00000000 +#define DDRSS1_PHY_522_DATA 0x00000000 +#define DDRSS1_PHY_523_DATA 0x01000001 +#define DDRSS1_PHY_524_DATA 0x00000200 +#define DDRSS1_PHY_525_DATA 0x000800C0 +#define DDRSS1_PHY_526_DATA 0x060100CC +#define DDRSS1_PHY_527_DATA 0x00030066 +#define DDRSS1_PHY_528_DATA 0x00000000 +#define DDRSS1_PHY_529_DATA 0x00000301 +#define DDRSS1_PHY_530_DATA 0x0000AAAA +#define DDRSS1_PHY_531_DATA 0x00005555 +#define DDRSS1_PHY_532_DATA 0x0000B5B5 +#define DDRSS1_PHY_533_DATA 0x00004A4A +#define DDRSS1_PHY_534_DATA 0x00005656 +#define DDRSS1_PHY_535_DATA 0x0000A9A9 +#define DDRSS1_PHY_536_DATA 0x0000A9A9 +#define DDRSS1_PHY_537_DATA 0x0000B5B5 +#define DDRSS1_PHY_538_DATA 0x00000000 +#define DDRSS1_PHY_539_DATA 0x00000000 +#define DDRSS1_PHY_540_DATA 0x2A000000 +#define DDRSS1_PHY_541_DATA 0x00000808 +#define DDRSS1_PHY_542_DATA 0x0F000000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 +#define DDRSS1_PHY_545_DATA 0x0C002006 +#define DDRSS1_PHY_546_DATA 0x00000000 +#define DDRSS1_PHY_547_DATA 0x00000000 +#define DDRSS1_PHY_548_DATA 0x55555555 +#define DDRSS1_PHY_549_DATA 0xAAAAAAAA +#define DDRSS1_PHY_550_DATA 0x55555555 +#define DDRSS1_PHY_551_DATA 0xAAAAAAAA +#define DDRSS1_PHY_552_DATA 0x00005555 +#define DDRSS1_PHY_553_DATA 0x01000100 +#define DDRSS1_PHY_554_DATA 0x00800180 +#define DDRSS1_PHY_555_DATA 0x00000001 +#define DDRSS1_PHY_556_DATA 0x00000000 +#define DDRSS1_PHY_557_DATA 0x00000000 +#define DDRSS1_PHY_558_DATA 0x00000000 +#define DDRSS1_PHY_559_DATA 0x00000000 +#define DDRSS1_PHY_560_DATA 0x00000000 +#define DDRSS1_PHY_561_DATA 0x00000000 +#define DDRSS1_PHY_562_DATA 0x00000000 +#define DDRSS1_PHY_563_DATA 0x00000000 +#define DDRSS1_PHY_564_DATA 0x00000000 +#define DDRSS1_PHY_565_DATA 0x00000000 +#define DDRSS1_PHY_566_DATA 0x00000000 +#define DDRSS1_PHY_567_DATA 0x00000000 +#define DDRSS1_PHY_568_DATA 0x00000000 +#define DDRSS1_PHY_569_DATA 0x00000000 +#define DDRSS1_PHY_570_DATA 0x00000000 +#define DDRSS1_PHY_571_DATA 0x00000000 +#define DDRSS1_PHY_572_DATA 0x00000000 +#define DDRSS1_PHY_573_DATA 0x00000000 +#define DDRSS1_PHY_574_DATA 0x00000000 +#define DDRSS1_PHY_575_DATA 0x00000000 +#define DDRSS1_PHY_576_DATA 0x00000000 +#define DDRSS1_PHY_577_DATA 0x00000000 +#define DDRSS1_PHY_578_DATA 0x00000104 +#define DDRSS1_PHY_579_DATA 0x00000120 +#define DDRSS1_PHY_580_DATA 0x00000000 +#define DDRSS1_PHY_581_DATA 0x00000000 +#define DDRSS1_PHY_582_DATA 0x00000000 +#define DDRSS1_PHY_583_DATA 0x00000000 +#define DDRSS1_PHY_584_DATA 0x00000000 +#define DDRSS1_PHY_585_DATA 0x00000000 +#define DDRSS1_PHY_586_DATA 0x00000000 +#define DDRSS1_PHY_587_DATA 0x00000001 +#define DDRSS1_PHY_588_DATA 0x07FF0000 +#define DDRSS1_PHY_589_DATA 0x0080081F +#define DDRSS1_PHY_590_DATA 0x00081020 +#define DDRSS1_PHY_591_DATA 0x04010000 +#define DDRSS1_PHY_592_DATA 0x00000000 +#define DDRSS1_PHY_593_DATA 0x00000000 +#define DDRSS1_PHY_594_DATA 0x00000000 +#define DDRSS1_PHY_595_DATA 0x00000100 +#define DDRSS1_PHY_596_DATA 0x01CC0C01 +#define DDRSS1_PHY_597_DATA 0x1003CC0C +#define DDRSS1_PHY_598_DATA 0x20000140 +#define DDRSS1_PHY_599_DATA 0x07FF0200 +#define DDRSS1_PHY_600_DATA 0x0000DD01 +#define DDRSS1_PHY_601_DATA 0x10100303 +#define DDRSS1_PHY_602_DATA 0x10101010 +#define DDRSS1_PHY_603_DATA 0x10101010 +#define DDRSS1_PHY_604_DATA 0x00021010 +#define DDRSS1_PHY_605_DATA 0x00100010 +#define DDRSS1_PHY_606_DATA 0x00100010 +#define DDRSS1_PHY_607_DATA 0x00100010 +#define DDRSS1_PHY_608_DATA 0x00100010 +#define DDRSS1_PHY_609_DATA 0x00050010 +#define DDRSS1_PHY_610_DATA 0x51517041 +#define DDRSS1_PHY_611_DATA 0x31C06001 +#define DDRSS1_PHY_612_DATA 0x07AB01AB +#define DDRSS1_PHY_613_DATA 0x00C0C001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 +#define DDRSS1_PHY_615_DATA 0x10001000 +#define DDRSS1_PHY_616_DATA 0x0C083E42 +#define DDRSS1_PHY_617_DATA 0x0F0C3701 +#define DDRSS1_PHY_618_DATA 0x01000140 +#define DDRSS1_PHY_619_DATA 0x0C000420 +#define DDRSS1_PHY_620_DATA 0x00000198 +#define DDRSS1_PHY_621_DATA 0x0A0000D0 +#define DDRSS1_PHY_622_DATA 0x00030200 +#define DDRSS1_PHY_623_DATA 0x02800000 +#define DDRSS1_PHY_624_DATA 0x80800000 +#define DDRSS1_PHY_625_DATA 0x000E2010 +#define DDRSS1_PHY_626_DATA 0x76543210 +#define DDRSS1_PHY_627_DATA 0x00000008 +#define DDRSS1_PHY_628_DATA 0x02800280 +#define DDRSS1_PHY_629_DATA 0x02800280 +#define DDRSS1_PHY_630_DATA 0x02800280 +#define DDRSS1_PHY_631_DATA 0x02800280 +#define DDRSS1_PHY_632_DATA 0x00000280 +#define DDRSS1_PHY_633_DATA 0x0000A000 +#define DDRSS1_PHY_634_DATA 0x00A000A0 +#define DDRSS1_PHY_635_DATA 0x00A000A0 +#define DDRSS1_PHY_636_DATA 0x00A000A0 +#define DDRSS1_PHY_637_DATA 0x00A000A0 +#define DDRSS1_PHY_638_DATA 0x00A000A0 +#define DDRSS1_PHY_639_DATA 0x00A000A0 +#define DDRSS1_PHY_640_DATA 0x00A000A0 +#define DDRSS1_PHY_641_DATA 0x00A000A0 +#define DDRSS1_PHY_642_DATA 0x01C200A0 +#define DDRSS1_PHY_643_DATA 0x01A00005 +#define DDRSS1_PHY_644_DATA 0x00000000 +#define DDRSS1_PHY_645_DATA 0x00000000 +#define DDRSS1_PHY_646_DATA 0x00080200 +#define DDRSS1_PHY_647_DATA 0x00000000 +#define DDRSS1_PHY_648_DATA 0x20202020 +#define DDRSS1_PHY_649_DATA 0x20202020 +#define DDRSS1_PHY_650_DATA 0xF0F02020 +#define DDRSS1_PHY_651_DATA 0x00000000 +#define DDRSS1_PHY_652_DATA 0x00000000 +#define DDRSS1_PHY_653_DATA 0x00000000 +#define DDRSS1_PHY_654_DATA 0x00000000 +#define DDRSS1_PHY_655_DATA 0x00000000 +#define DDRSS1_PHY_656_DATA 0x00000000 +#define DDRSS1_PHY_657_DATA 0x00000000 +#define DDRSS1_PHY_658_DATA 0x00000000 +#define DDRSS1_PHY_659_DATA 0x00000000 +#define DDRSS1_PHY_660_DATA 0x00000000 +#define DDRSS1_PHY_661_DATA 0x00000000 +#define DDRSS1_PHY_662_DATA 0x00000000 +#define DDRSS1_PHY_663_DATA 0x00000000 +#define DDRSS1_PHY_664_DATA 0x00000000 +#define DDRSS1_PHY_665_DATA 0x00000000 +#define DDRSS1_PHY_666_DATA 0x00000000 +#define DDRSS1_PHY_667_DATA 0x00000000 +#define DDRSS1_PHY_668_DATA 0x00000000 +#define DDRSS1_PHY_669_DATA 0x00000000 +#define DDRSS1_PHY_670_DATA 0x00000000 +#define DDRSS1_PHY_671_DATA 0x00000000 +#define DDRSS1_PHY_672_DATA 0x00000000 +#define DDRSS1_PHY_673_DATA 0x00000000 +#define DDRSS1_PHY_674_DATA 0x00000000 +#define DDRSS1_PHY_675_DATA 0x00000000 +#define DDRSS1_PHY_676_DATA 0x00000000 +#define DDRSS1_PHY_677_DATA 0x00000000 +#define DDRSS1_PHY_678_DATA 0x00000000 +#define DDRSS1_PHY_679_DATA 0x00000000 +#define DDRSS1_PHY_680_DATA 0x00000000 +#define DDRSS1_PHY_681_DATA 0x00000000 +#define DDRSS1_PHY_682_DATA 0x00000000 +#define DDRSS1_PHY_683_DATA 0x00000000 +#define DDRSS1_PHY_684_DATA 0x00000000 +#define DDRSS1_PHY_685_DATA 0x00000000 +#define DDRSS1_PHY_686_DATA 0x00000000 +#define DDRSS1_PHY_687_DATA 0x00000000 +#define DDRSS1_PHY_688_DATA 0x00000000 +#define DDRSS1_PHY_689_DATA 0x00000000 +#define DDRSS1_PHY_690_DATA 0x00000000 +#define DDRSS1_PHY_691_DATA 0x00000000 +#define DDRSS1_PHY_692_DATA 0x00000000 +#define DDRSS1_PHY_693_DATA 0x00000000 +#define DDRSS1_PHY_694_DATA 0x00000000 +#define DDRSS1_PHY_695_DATA 0x00000000 +#define DDRSS1_PHY_696_DATA 0x00000000 +#define DDRSS1_PHY_697_DATA 0x00000000 +#define DDRSS1_PHY_698_DATA 0x00000000 +#define DDRSS1_PHY_699_DATA 0x00000000 +#define DDRSS1_PHY_700_DATA 0x00000000 +#define DDRSS1_PHY_701_DATA 0x00000000 +#define DDRSS1_PHY_702_DATA 0x00000000 +#define DDRSS1_PHY_703_DATA 0x00000000 +#define DDRSS1_PHY_704_DATA 0x00000000 +#define DDRSS1_PHY_705_DATA 0x00000000 +#define DDRSS1_PHY_706_DATA 0x00000000 +#define DDRSS1_PHY_707_DATA 0x00000000 +#define DDRSS1_PHY_708_DATA 0x00000000 +#define DDRSS1_PHY_709_DATA 0x00000000 +#define DDRSS1_PHY_710_DATA 0x00000000 +#define DDRSS1_PHY_711_DATA 0x00000000 +#define DDRSS1_PHY_712_DATA 0x00000000 +#define DDRSS1_PHY_713_DATA 0x00000000 +#define DDRSS1_PHY_714_DATA 0x00000000 +#define DDRSS1_PHY_715_DATA 0x00000000 +#define DDRSS1_PHY_716_DATA 0x00000000 +#define DDRSS1_PHY_717_DATA 0x00000000 +#define DDRSS1_PHY_718_DATA 0x00000000 +#define DDRSS1_PHY_719_DATA 0x00000000 +#define DDRSS1_PHY_720_DATA 0x00000000 +#define DDRSS1_PHY_721_DATA 0x00000000 +#define DDRSS1_PHY_722_DATA 0x00000000 +#define DDRSS1_PHY_723_DATA 0x00000000 +#define DDRSS1_PHY_724_DATA 0x00000000 +#define DDRSS1_PHY_725_DATA 0x00000000 +#define DDRSS1_PHY_726_DATA 0x00000000 +#define DDRSS1_PHY_727_DATA 0x00000000 +#define DDRSS1_PHY_728_DATA 0x00000000 +#define DDRSS1_PHY_729_DATA 0x00000000 +#define DDRSS1_PHY_730_DATA 0x00000000 +#define DDRSS1_PHY_731_DATA 0x00000000 +#define DDRSS1_PHY_732_DATA 0x00000000 +#define DDRSS1_PHY_733_DATA 0x00000000 +#define DDRSS1_PHY_734_DATA 0x00000000 +#define DDRSS1_PHY_735_DATA 0x00000000 +#define DDRSS1_PHY_736_DATA 0x00000000 +#define DDRSS1_PHY_737_DATA 0x00000000 +#define DDRSS1_PHY_738_DATA 0x00000000 +#define DDRSS1_PHY_739_DATA 0x00000000 +#define DDRSS1_PHY_740_DATA 0x00000000 +#define DDRSS1_PHY_741_DATA 0x00000000 +#define DDRSS1_PHY_742_DATA 0x00000000 +#define DDRSS1_PHY_743_DATA 0x00000000 +#define DDRSS1_PHY_744_DATA 0x00000000 +#define DDRSS1_PHY_745_DATA 0x00000000 +#define DDRSS1_PHY_746_DATA 0x00000000 +#define DDRSS1_PHY_747_DATA 0x00000000 +#define DDRSS1_PHY_748_DATA 0x00000000 +#define DDRSS1_PHY_749_DATA 0x00000000 +#define DDRSS1_PHY_750_DATA 0x00000000 +#define DDRSS1_PHY_751_DATA 0x00000000 +#define DDRSS1_PHY_752_DATA 0x00000000 +#define DDRSS1_PHY_753_DATA 0x00000000 +#define DDRSS1_PHY_754_DATA 0x00000000 +#define DDRSS1_PHY_755_DATA 0x00000000 +#define DDRSS1_PHY_756_DATA 0x00000000 +#define DDRSS1_PHY_757_DATA 0x00000000 +#define DDRSS1_PHY_758_DATA 0x00000000 +#define DDRSS1_PHY_759_DATA 0x00000000 +#define DDRSS1_PHY_760_DATA 0x00000000 +#define DDRSS1_PHY_761_DATA 0x00000000 +#define DDRSS1_PHY_762_DATA 0x00000000 +#define DDRSS1_PHY_763_DATA 0x00000000 +#define DDRSS1_PHY_764_DATA 0x00000000 +#define DDRSS1_PHY_765_DATA 0x00000000 +#define DDRSS1_PHY_766_DATA 0x00000000 +#define DDRSS1_PHY_767_DATA 0x00000000 +#define DDRSS1_PHY_768_DATA 0x000004F0 +#define DDRSS1_PHY_769_DATA 0x00000000 +#define DDRSS1_PHY_770_DATA 0x00030200 +#define DDRSS1_PHY_771_DATA 0x00000000 +#define DDRSS1_PHY_772_DATA 0x00000000 +#define DDRSS1_PHY_773_DATA 0x01030000 +#define DDRSS1_PHY_774_DATA 0x00010000 +#define DDRSS1_PHY_775_DATA 0x01030004 +#define DDRSS1_PHY_776_DATA 0x01000000 +#define DDRSS1_PHY_777_DATA 0x00000000 +#define DDRSS1_PHY_778_DATA 0x00000000 +#define DDRSS1_PHY_779_DATA 0x01000001 +#define DDRSS1_PHY_780_DATA 0x00000200 +#define DDRSS1_PHY_781_DATA 0x000800C0 +#define DDRSS1_PHY_782_DATA 0x060100CC +#define DDRSS1_PHY_783_DATA 0x00030066 +#define DDRSS1_PHY_784_DATA 0x00000000 +#define DDRSS1_PHY_785_DATA 0x00000301 +#define DDRSS1_PHY_786_DATA 0x0000AAAA +#define DDRSS1_PHY_787_DATA 0x00005555 +#define DDRSS1_PHY_788_DATA 0x0000B5B5 +#define DDRSS1_PHY_789_DATA 0x00004A4A +#define DDRSS1_PHY_790_DATA 0x00005656 +#define DDRSS1_PHY_791_DATA 0x0000A9A9 +#define DDRSS1_PHY_792_DATA 0x0000A9A9 +#define DDRSS1_PHY_793_DATA 0x0000B5B5 +#define DDRSS1_PHY_794_DATA 0x00000000 +#define DDRSS1_PHY_795_DATA 0x00000000 +#define DDRSS1_PHY_796_DATA 0x2A000000 +#define DDRSS1_PHY_797_DATA 0x00000808 +#define DDRSS1_PHY_798_DATA 0x0F000000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 +#define DDRSS1_PHY_801_DATA 0x0C002006 +#define DDRSS1_PHY_802_DATA 0x00000000 +#define DDRSS1_PHY_803_DATA 0x00000000 +#define DDRSS1_PHY_804_DATA 0x55555555 +#define DDRSS1_PHY_805_DATA 0xAAAAAAAA +#define DDRSS1_PHY_806_DATA 0x55555555 +#define DDRSS1_PHY_807_DATA 0xAAAAAAAA +#define DDRSS1_PHY_808_DATA 0x00005555 +#define DDRSS1_PHY_809_DATA 0x01000100 +#define DDRSS1_PHY_810_DATA 0x00800180 +#define DDRSS1_PHY_811_DATA 0x00000000 +#define DDRSS1_PHY_812_DATA 0x00000000 +#define DDRSS1_PHY_813_DATA 0x00000000 +#define DDRSS1_PHY_814_DATA 0x00000000 +#define DDRSS1_PHY_815_DATA 0x00000000 +#define DDRSS1_PHY_816_DATA 0x00000000 +#define DDRSS1_PHY_817_DATA 0x00000000 +#define DDRSS1_PHY_818_DATA 0x00000000 +#define DDRSS1_PHY_819_DATA 0x00000000 +#define DDRSS1_PHY_820_DATA 0x00000000 +#define DDRSS1_PHY_821_DATA 0x00000000 +#define DDRSS1_PHY_822_DATA 0x00000000 +#define DDRSS1_PHY_823_DATA 0x00000000 +#define DDRSS1_PHY_824_DATA 0x00000000 +#define DDRSS1_PHY_825_DATA 0x00000000 +#define DDRSS1_PHY_826_DATA 0x00000000 +#define DDRSS1_PHY_827_DATA 0x00000000 +#define DDRSS1_PHY_828_DATA 0x00000000 +#define DDRSS1_PHY_829_DATA 0x00000000 +#define DDRSS1_PHY_830_DATA 0x00000000 +#define DDRSS1_PHY_831_DATA 0x00000000 +#define DDRSS1_PHY_832_DATA 0x00000000 +#define DDRSS1_PHY_833_DATA 0x00000000 +#define DDRSS1_PHY_834_DATA 0x00000104 +#define DDRSS1_PHY_835_DATA 0x00000120 +#define DDRSS1_PHY_836_DATA 0x00000000 +#define DDRSS1_PHY_837_DATA 0x00000000 +#define DDRSS1_PHY_838_DATA 0x00000000 +#define DDRSS1_PHY_839_DATA 0x00000000 +#define DDRSS1_PHY_840_DATA 0x00000000 +#define DDRSS1_PHY_841_DATA 0x00000000 +#define DDRSS1_PHY_842_DATA 0x00000000 +#define DDRSS1_PHY_843_DATA 0x00000001 +#define DDRSS1_PHY_844_DATA 0x07FF0000 +#define DDRSS1_PHY_845_DATA 0x0080081F +#define DDRSS1_PHY_846_DATA 0x00081020 +#define DDRSS1_PHY_847_DATA 0x04010000 +#define DDRSS1_PHY_848_DATA 0x00000000 +#define DDRSS1_PHY_849_DATA 0x00000000 +#define DDRSS1_PHY_850_DATA 0x00000000 +#define DDRSS1_PHY_851_DATA 0x00000100 +#define DDRSS1_PHY_852_DATA 0x01CC0C01 +#define DDRSS1_PHY_853_DATA 0x1003CC0C +#define DDRSS1_PHY_854_DATA 0x20000140 +#define DDRSS1_PHY_855_DATA 0x07FF0200 +#define DDRSS1_PHY_856_DATA 0x0000DD01 +#define DDRSS1_PHY_857_DATA 0x10100303 +#define DDRSS1_PHY_858_DATA 0x10101010 +#define DDRSS1_PHY_859_DATA 0x10101010 +#define DDRSS1_PHY_860_DATA 0x00021010 +#define DDRSS1_PHY_861_DATA 0x00100010 +#define DDRSS1_PHY_862_DATA 0x00100010 +#define DDRSS1_PHY_863_DATA 0x00100010 +#define DDRSS1_PHY_864_DATA 0x00100010 +#define DDRSS1_PHY_865_DATA 0x00050010 +#define DDRSS1_PHY_866_DATA 0x51517041 +#define DDRSS1_PHY_867_DATA 0x31C06001 +#define DDRSS1_PHY_868_DATA 0x07AB01AB +#define DDRSS1_PHY_869_DATA 0x00C0C001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 +#define DDRSS1_PHY_871_DATA 0x10001000 +#define DDRSS1_PHY_872_DATA 0x0C083E42 +#define DDRSS1_PHY_873_DATA 0x0F0C3701 +#define DDRSS1_PHY_874_DATA 0x01000140 +#define DDRSS1_PHY_875_DATA 0x0C000420 +#define DDRSS1_PHY_876_DATA 0x00000198 +#define DDRSS1_PHY_877_DATA 0x0A0000D0 +#define DDRSS1_PHY_878_DATA 0x00030200 +#define DDRSS1_PHY_879_DATA 0x02800000 +#define DDRSS1_PHY_880_DATA 0x80800000 +#define DDRSS1_PHY_881_DATA 0x000E2010 +#define DDRSS1_PHY_882_DATA 0x76543210 +#define DDRSS1_PHY_883_DATA 0x00000008 +#define DDRSS1_PHY_884_DATA 0x02800280 +#define DDRSS1_PHY_885_DATA 0x02800280 +#define DDRSS1_PHY_886_DATA 0x02800280 +#define DDRSS1_PHY_887_DATA 0x02800280 +#define DDRSS1_PHY_888_DATA 0x00000280 +#define DDRSS1_PHY_889_DATA 0x0000A000 +#define DDRSS1_PHY_890_DATA 0x00A000A0 +#define DDRSS1_PHY_891_DATA 0x00A000A0 +#define DDRSS1_PHY_892_DATA 0x00A000A0 +#define DDRSS1_PHY_893_DATA 0x00A000A0 +#define DDRSS1_PHY_894_DATA 0x00A000A0 +#define DDRSS1_PHY_895_DATA 0x00A000A0 +#define DDRSS1_PHY_896_DATA 0x00A000A0 +#define DDRSS1_PHY_897_DATA 0x00A000A0 +#define DDRSS1_PHY_898_DATA 0x01C200A0 +#define DDRSS1_PHY_899_DATA 0x01A00005 +#define DDRSS1_PHY_900_DATA 0x00000000 +#define DDRSS1_PHY_901_DATA 0x00000000 +#define DDRSS1_PHY_902_DATA 0x00080200 +#define DDRSS1_PHY_903_DATA 0x00000000 +#define DDRSS1_PHY_904_DATA 0x20202020 +#define DDRSS1_PHY_905_DATA 0x20202020 +#define DDRSS1_PHY_906_DATA 0xF0F02020 +#define DDRSS1_PHY_907_DATA 0x00000000 +#define DDRSS1_PHY_908_DATA 0x00000000 +#define DDRSS1_PHY_909_DATA 0x00000000 +#define DDRSS1_PHY_910_DATA 0x00000000 +#define DDRSS1_PHY_911_DATA 0x00000000 +#define DDRSS1_PHY_912_DATA 0x00000000 +#define DDRSS1_PHY_913_DATA 0x00000000 +#define DDRSS1_PHY_914_DATA 0x00000000 +#define DDRSS1_PHY_915_DATA 0x00000000 +#define DDRSS1_PHY_916_DATA 0x00000000 +#define DDRSS1_PHY_917_DATA 0x00000000 +#define DDRSS1_PHY_918_DATA 0x00000000 +#define DDRSS1_PHY_919_DATA 0x00000000 +#define DDRSS1_PHY_920_DATA 0x00000000 +#define DDRSS1_PHY_921_DATA 0x00000000 +#define DDRSS1_PHY_922_DATA 0x00000000 +#define DDRSS1_PHY_923_DATA 0x00000000 +#define DDRSS1_PHY_924_DATA 0x00000000 +#define DDRSS1_PHY_925_DATA 0x00000000 +#define DDRSS1_PHY_926_DATA 0x00000000 +#define DDRSS1_PHY_927_DATA 0x00000000 +#define DDRSS1_PHY_928_DATA 0x00000000 +#define DDRSS1_PHY_929_DATA 0x00000000 +#define DDRSS1_PHY_930_DATA 0x00000000 +#define DDRSS1_PHY_931_DATA 0x00000000 +#define DDRSS1_PHY_932_DATA 0x00000000 +#define DDRSS1_PHY_933_DATA 0x00000000 +#define DDRSS1_PHY_934_DATA 0x00000000 +#define DDRSS1_PHY_935_DATA 0x00000000 +#define DDRSS1_PHY_936_DATA 0x00000000 +#define DDRSS1_PHY_937_DATA 0x00000000 +#define DDRSS1_PHY_938_DATA 0x00000000 +#define DDRSS1_PHY_939_DATA 0x00000000 +#define DDRSS1_PHY_940_DATA 0x00000000 +#define DDRSS1_PHY_941_DATA 0x00000000 +#define DDRSS1_PHY_942_DATA 0x00000000 +#define DDRSS1_PHY_943_DATA 0x00000000 +#define DDRSS1_PHY_944_DATA 0x00000000 +#define DDRSS1_PHY_945_DATA 0x00000000 +#define DDRSS1_PHY_946_DATA 0x00000000 +#define DDRSS1_PHY_947_DATA 0x00000000 +#define DDRSS1_PHY_948_DATA 0x00000000 +#define DDRSS1_PHY_949_DATA 0x00000000 +#define DDRSS1_PHY_950_DATA 0x00000000 +#define DDRSS1_PHY_951_DATA 0x00000000 +#define DDRSS1_PHY_952_DATA 0x00000000 +#define DDRSS1_PHY_953_DATA 0x00000000 +#define DDRSS1_PHY_954_DATA 0x00000000 +#define DDRSS1_PHY_955_DATA 0x00000000 +#define DDRSS1_PHY_956_DATA 0x00000000 +#define DDRSS1_PHY_957_DATA 0x00000000 +#define DDRSS1_PHY_958_DATA 0x00000000 +#define DDRSS1_PHY_959_DATA 0x00000000 +#define DDRSS1_PHY_960_DATA 0x00000000 +#define DDRSS1_PHY_961_DATA 0x00000000 +#define DDRSS1_PHY_962_DATA 0x00000000 +#define DDRSS1_PHY_963_DATA 0x00000000 +#define DDRSS1_PHY_964_DATA 0x00000000 +#define DDRSS1_PHY_965_DATA 0x00000000 +#define DDRSS1_PHY_966_DATA 0x00000000 +#define DDRSS1_PHY_967_DATA 0x00000000 +#define DDRSS1_PHY_968_DATA 0x00000000 +#define DDRSS1_PHY_969_DATA 0x00000000 +#define DDRSS1_PHY_970_DATA 0x00000000 +#define DDRSS1_PHY_971_DATA 0x00000000 +#define DDRSS1_PHY_972_DATA 0x00000000 +#define DDRSS1_PHY_973_DATA 0x00000000 +#define DDRSS1_PHY_974_DATA 0x00000000 +#define DDRSS1_PHY_975_DATA 0x00000000 +#define DDRSS1_PHY_976_DATA 0x00000000 +#define DDRSS1_PHY_977_DATA 0x00000000 +#define DDRSS1_PHY_978_DATA 0x00000000 +#define DDRSS1_PHY_979_DATA 0x00000000 +#define DDRSS1_PHY_980_DATA 0x00000000 +#define DDRSS1_PHY_981_DATA 0x00000000 +#define DDRSS1_PHY_982_DATA 0x00000000 +#define DDRSS1_PHY_983_DATA 0x00000000 +#define DDRSS1_PHY_984_DATA 0x00000000 +#define DDRSS1_PHY_985_DATA 0x00000000 +#define DDRSS1_PHY_986_DATA 0x00000000 +#define DDRSS1_PHY_987_DATA 0x00000000 +#define DDRSS1_PHY_988_DATA 0x00000000 +#define DDRSS1_PHY_989_DATA 0x00000000 +#define DDRSS1_PHY_990_DATA 0x00000000 +#define DDRSS1_PHY_991_DATA 0x00000000 +#define DDRSS1_PHY_992_DATA 0x00000000 +#define DDRSS1_PHY_993_DATA 0x00000000 +#define DDRSS1_PHY_994_DATA 0x00000000 +#define DDRSS1_PHY_995_DATA 0x00000000 +#define DDRSS1_PHY_996_DATA 0x00000000 +#define DDRSS1_PHY_997_DATA 0x00000000 +#define DDRSS1_PHY_998_DATA 0x00000000 +#define DDRSS1_PHY_999_DATA 0x00000000 +#define DDRSS1_PHY_1000_DATA 0x00000000 +#define DDRSS1_PHY_1001_DATA 0x00000000 +#define DDRSS1_PHY_1002_DATA 0x00000000 +#define DDRSS1_PHY_1003_DATA 0x00000000 +#define DDRSS1_PHY_1004_DATA 0x00000000 +#define DDRSS1_PHY_1005_DATA 0x00000000 +#define DDRSS1_PHY_1006_DATA 0x00000000 +#define DDRSS1_PHY_1007_DATA 0x00000000 +#define DDRSS1_PHY_1008_DATA 0x00000000 +#define DDRSS1_PHY_1009_DATA 0x00000000 +#define DDRSS1_PHY_1010_DATA 0x00000000 +#define DDRSS1_PHY_1011_DATA 0x00000000 +#define DDRSS1_PHY_1012_DATA 0x00000000 +#define DDRSS1_PHY_1013_DATA 0x00000000 +#define DDRSS1_PHY_1014_DATA 0x00000000 +#define DDRSS1_PHY_1015_DATA 0x00000000 +#define DDRSS1_PHY_1016_DATA 0x00000000 +#define DDRSS1_PHY_1017_DATA 0x00000000 +#define DDRSS1_PHY_1018_DATA 0x00000000 +#define DDRSS1_PHY_1019_DATA 0x00000000 +#define DDRSS1_PHY_1020_DATA 0x00000000 +#define DDRSS1_PHY_1021_DATA 0x00000000 +#define DDRSS1_PHY_1022_DATA 0x00000000 +#define DDRSS1_PHY_1023_DATA 0x00000000 +#define DDRSS1_PHY_1024_DATA 0x00000000 +#define DDRSS1_PHY_1025_DATA 0x00000000 +#define DDRSS1_PHY_1026_DATA 0x00000000 +#define DDRSS1_PHY_1027_DATA 0x00000000 +#define DDRSS1_PHY_1028_DATA 0x00000000 +#define DDRSS1_PHY_1029_DATA 0x00000100 +#define DDRSS1_PHY_1030_DATA 0x00000200 +#define DDRSS1_PHY_1031_DATA 0x00000000 +#define DDRSS1_PHY_1032_DATA 0x00000000 +#define DDRSS1_PHY_1033_DATA 0x00000000 +#define DDRSS1_PHY_1034_DATA 0x00000000 +#define DDRSS1_PHY_1035_DATA 0x00400000 +#define DDRSS1_PHY_1036_DATA 0x00000080 +#define DDRSS1_PHY_1037_DATA 0x00DCBA98 +#define DDRSS1_PHY_1038_DATA 0x03000000 +#define DDRSS1_PHY_1039_DATA 0x00200000 +#define DDRSS1_PHY_1040_DATA 0x00000000 +#define DDRSS1_PHY_1041_DATA 0x00000000 +#define DDRSS1_PHY_1042_DATA 0x00000000 +#define DDRSS1_PHY_1043_DATA 0x00000000 +#define DDRSS1_PHY_1044_DATA 0x00000000 +#define DDRSS1_PHY_1045_DATA 0x0000002A +#define DDRSS1_PHY_1046_DATA 0x00000015 +#define DDRSS1_PHY_1047_DATA 0x00000015 +#define DDRSS1_PHY_1048_DATA 0x0000002A +#define DDRSS1_PHY_1049_DATA 0x00000033 +#define DDRSS1_PHY_1050_DATA 0x0000000C +#define DDRSS1_PHY_1051_DATA 0x0000000C +#define DDRSS1_PHY_1052_DATA 0x00000033 +#define DDRSS1_PHY_1053_DATA 0x00543210 +#define DDRSS1_PHY_1054_DATA 0x003F0000 +#define DDRSS1_PHY_1055_DATA 0x000F3F3F +#define DDRSS1_PHY_1056_DATA 0x20202003 +#define DDRSS1_PHY_1057_DATA 0x00202020 +#define DDRSS1_PHY_1058_DATA 0x20008008 +#define DDRSS1_PHY_1059_DATA 0x00000810 +#define DDRSS1_PHY_1060_DATA 0x00000F00 +#define DDRSS1_PHY_1061_DATA 0x00000000 +#define DDRSS1_PHY_1062_DATA 0x00000000 +#define DDRSS1_PHY_1063_DATA 0x00000000 +#define DDRSS1_PHY_1064_DATA 0x000305CC +#define DDRSS1_PHY_1065_DATA 0x00030000 +#define DDRSS1_PHY_1066_DATA 0x00000300 +#define DDRSS1_PHY_1067_DATA 0x00000300 +#define DDRSS1_PHY_1068_DATA 0x00000300 +#define DDRSS1_PHY_1069_DATA 0x00000300 +#define DDRSS1_PHY_1070_DATA 0x00000300 +#define DDRSS1_PHY_1071_DATA 0x42080010 +#define DDRSS1_PHY_1072_DATA 0x0000803E +#define DDRSS1_PHY_1073_DATA 0x00000001 +#define DDRSS1_PHY_1074_DATA 0x01000102 +#define DDRSS1_PHY_1075_DATA 0x00008000 +#define DDRSS1_PHY_1076_DATA 0x00000000 +#define DDRSS1_PHY_1077_DATA 0x00000000 +#define DDRSS1_PHY_1078_DATA 0x00000000 +#define DDRSS1_PHY_1079_DATA 0x00000000 +#define DDRSS1_PHY_1080_DATA 0x00000000 +#define DDRSS1_PHY_1081_DATA 0x00000000 +#define DDRSS1_PHY_1082_DATA 0x00000000 +#define DDRSS1_PHY_1083_DATA 0x00000000 +#define DDRSS1_PHY_1084_DATA 0x00000000 +#define DDRSS1_PHY_1085_DATA 0x00000000 +#define DDRSS1_PHY_1086_DATA 0x00000000 +#define DDRSS1_PHY_1087_DATA 0x00000000 +#define DDRSS1_PHY_1088_DATA 0x00000000 +#define DDRSS1_PHY_1089_DATA 0x00000000 +#define DDRSS1_PHY_1090_DATA 0x00000000 +#define DDRSS1_PHY_1091_DATA 0x00000000 +#define DDRSS1_PHY_1092_DATA 0x00000000 +#define DDRSS1_PHY_1093_DATA 0x00000000 +#define DDRSS1_PHY_1094_DATA 0x00000000 +#define DDRSS1_PHY_1095_DATA 0x00000000 +#define DDRSS1_PHY_1096_DATA 0x00000000 +#define DDRSS1_PHY_1097_DATA 0x00000000 +#define DDRSS1_PHY_1098_DATA 0x00000000 +#define DDRSS1_PHY_1099_DATA 0x00000000 +#define DDRSS1_PHY_1100_DATA 0x00000000 +#define DDRSS1_PHY_1101_DATA 0x00000000 +#define DDRSS1_PHY_1102_DATA 0x00000000 +#define DDRSS1_PHY_1103_DATA 0x00000000 +#define DDRSS1_PHY_1104_DATA 0x00000000 +#define DDRSS1_PHY_1105_DATA 0x00000000 +#define DDRSS1_PHY_1106_DATA 0x00000000 +#define DDRSS1_PHY_1107_DATA 0x00000000 +#define DDRSS1_PHY_1108_DATA 0x00000000 +#define DDRSS1_PHY_1109_DATA 0x00000000 +#define DDRSS1_PHY_1110_DATA 0x00000000 +#define DDRSS1_PHY_1111_DATA 0x00000000 +#define DDRSS1_PHY_1112_DATA 0x00000000 +#define DDRSS1_PHY_1113_DATA 0x00000000 +#define DDRSS1_PHY_1114_DATA 0x00000000 +#define DDRSS1_PHY_1115_DATA 0x00000000 +#define DDRSS1_PHY_1116_DATA 0x00000000 +#define DDRSS1_PHY_1117_DATA 0x00000000 +#define DDRSS1_PHY_1118_DATA 0x00000000 +#define DDRSS1_PHY_1119_DATA 0x00000000 +#define DDRSS1_PHY_1120_DATA 0x00000000 +#define DDRSS1_PHY_1121_DATA 0x00000000 +#define DDRSS1_PHY_1122_DATA 0x00000000 +#define DDRSS1_PHY_1123_DATA 0x00000000 +#define DDRSS1_PHY_1124_DATA 0x00000000 +#define DDRSS1_PHY_1125_DATA 0x00000000 +#define DDRSS1_PHY_1126_DATA 0x00000000 +#define DDRSS1_PHY_1127_DATA 0x00000000 +#define DDRSS1_PHY_1128_DATA 0x00000000 +#define DDRSS1_PHY_1129_DATA 0x00000000 +#define DDRSS1_PHY_1130_DATA 0x00000000 +#define DDRSS1_PHY_1131_DATA 0x00000000 +#define DDRSS1_PHY_1132_DATA 0x00000000 +#define DDRSS1_PHY_1133_DATA 0x00000000 +#define DDRSS1_PHY_1134_DATA 0x00000000 +#define DDRSS1_PHY_1135_DATA 0x00000000 +#define DDRSS1_PHY_1136_DATA 0x00000000 +#define DDRSS1_PHY_1137_DATA 0x00000000 +#define DDRSS1_PHY_1138_DATA 0x00000000 +#define DDRSS1_PHY_1139_DATA 0x00000000 +#define DDRSS1_PHY_1140_DATA 0x00000000 +#define DDRSS1_PHY_1141_DATA 0x00000000 +#define DDRSS1_PHY_1142_DATA 0x00000000 +#define DDRSS1_PHY_1143_DATA 0x00000000 +#define DDRSS1_PHY_1144_DATA 0x00000000 +#define DDRSS1_PHY_1145_DATA 0x00000000 +#define DDRSS1_PHY_1146_DATA 0x00000000 +#define DDRSS1_PHY_1147_DATA 0x00000000 +#define DDRSS1_PHY_1148_DATA 0x00000000 +#define DDRSS1_PHY_1149_DATA 0x00000000 +#define DDRSS1_PHY_1150_DATA 0x00000000 +#define DDRSS1_PHY_1151_DATA 0x00000000 +#define DDRSS1_PHY_1152_DATA 0x00000000 +#define DDRSS1_PHY_1153_DATA 0x00000000 +#define DDRSS1_PHY_1154_DATA 0x00000000 +#define DDRSS1_PHY_1155_DATA 0x00000000 +#define DDRSS1_PHY_1156_DATA 0x00000000 +#define DDRSS1_PHY_1157_DATA 0x00000000 +#define DDRSS1_PHY_1158_DATA 0x00000000 +#define DDRSS1_PHY_1159_DATA 0x00000000 +#define DDRSS1_PHY_1160_DATA 0x00000000 +#define DDRSS1_PHY_1161_DATA 0x00000000 +#define DDRSS1_PHY_1162_DATA 0x00000000 +#define DDRSS1_PHY_1163_DATA 0x00000000 +#define DDRSS1_PHY_1164_DATA 0x00000000 +#define DDRSS1_PHY_1165_DATA 0x00000000 +#define DDRSS1_PHY_1166_DATA 0x00000000 +#define DDRSS1_PHY_1167_DATA 0x00000000 +#define DDRSS1_PHY_1168_DATA 0x00000000 +#define DDRSS1_PHY_1169_DATA 0x00000000 +#define DDRSS1_PHY_1170_DATA 0x00000000 +#define DDRSS1_PHY_1171_DATA 0x00000000 +#define DDRSS1_PHY_1172_DATA 0x00000000 +#define DDRSS1_PHY_1173_DATA 0x00000000 +#define DDRSS1_PHY_1174_DATA 0x00000000 +#define DDRSS1_PHY_1175_DATA 0x00000000 +#define DDRSS1_PHY_1176_DATA 0x00000000 +#define DDRSS1_PHY_1177_DATA 0x00000000 +#define DDRSS1_PHY_1178_DATA 0x00000000 +#define DDRSS1_PHY_1179_DATA 0x00000000 +#define DDRSS1_PHY_1180_DATA 0x00000000 +#define DDRSS1_PHY_1181_DATA 0x00000000 +#define DDRSS1_PHY_1182_DATA 0x00000000 +#define DDRSS1_PHY_1183_DATA 0x00000000 +#define DDRSS1_PHY_1184_DATA 0x00000000 +#define DDRSS1_PHY_1185_DATA 0x00000000 +#define DDRSS1_PHY_1186_DATA 0x00000000 +#define DDRSS1_PHY_1187_DATA 0x00000000 +#define DDRSS1_PHY_1188_DATA 0x00000000 +#define DDRSS1_PHY_1189_DATA 0x00000000 +#define DDRSS1_PHY_1190_DATA 0x00000000 +#define DDRSS1_PHY_1191_DATA 0x00000000 +#define DDRSS1_PHY_1192_DATA 0x00000000 +#define DDRSS1_PHY_1193_DATA 0x00000000 +#define DDRSS1_PHY_1194_DATA 0x00000000 +#define DDRSS1_PHY_1195_DATA 0x00000000 +#define DDRSS1_PHY_1196_DATA 0x00000000 +#define DDRSS1_PHY_1197_DATA 0x00000000 +#define DDRSS1_PHY_1198_DATA 0x00000000 +#define DDRSS1_PHY_1199_DATA 0x00000000 +#define DDRSS1_PHY_1200_DATA 0x00000000 +#define DDRSS1_PHY_1201_DATA 0x00000000 +#define DDRSS1_PHY_1202_DATA 0x00000000 +#define DDRSS1_PHY_1203_DATA 0x00000000 +#define DDRSS1_PHY_1204_DATA 0x00000000 +#define DDRSS1_PHY_1205_DATA 0x00000000 +#define DDRSS1_PHY_1206_DATA 0x00000000 +#define DDRSS1_PHY_1207_DATA 0x00000000 +#define DDRSS1_PHY_1208_DATA 0x00000000 +#define DDRSS1_PHY_1209_DATA 0x00000000 +#define DDRSS1_PHY_1210_DATA 0x00000000 +#define DDRSS1_PHY_1211_DATA 0x00000000 +#define DDRSS1_PHY_1212_DATA 0x00000000 +#define DDRSS1_PHY_1213_DATA 0x00000000 +#define DDRSS1_PHY_1214_DATA 0x00000000 +#define DDRSS1_PHY_1215_DATA 0x00000000 +#define DDRSS1_PHY_1216_DATA 0x00000000 +#define DDRSS1_PHY_1217_DATA 0x00000000 +#define DDRSS1_PHY_1218_DATA 0x00000000 +#define DDRSS1_PHY_1219_DATA 0x00000000 +#define DDRSS1_PHY_1220_DATA 0x00000000 +#define DDRSS1_PHY_1221_DATA 0x00000000 +#define DDRSS1_PHY_1222_DATA 0x00000000 +#define DDRSS1_PHY_1223_DATA 0x00000000 +#define DDRSS1_PHY_1224_DATA 0x00000000 +#define DDRSS1_PHY_1225_DATA 0x00000000 +#define DDRSS1_PHY_1226_DATA 0x00000000 +#define DDRSS1_PHY_1227_DATA 0x00000000 +#define DDRSS1_PHY_1228_DATA 0x00000000 +#define DDRSS1_PHY_1229_DATA 0x00000000 +#define DDRSS1_PHY_1230_DATA 0x00000000 +#define DDRSS1_PHY_1231_DATA 0x00000000 +#define DDRSS1_PHY_1232_DATA 0x00000000 +#define DDRSS1_PHY_1233_DATA 0x00000000 +#define DDRSS1_PHY_1234_DATA 0x00000000 +#define DDRSS1_PHY_1235_DATA 0x00000000 +#define DDRSS1_PHY_1236_DATA 0x00000000 +#define DDRSS1_PHY_1237_DATA 0x00000000 +#define DDRSS1_PHY_1238_DATA 0x00000000 +#define DDRSS1_PHY_1239_DATA 0x00000000 +#define DDRSS1_PHY_1240_DATA 0x00000000 +#define DDRSS1_PHY_1241_DATA 0x00000000 +#define DDRSS1_PHY_1242_DATA 0x00000000 +#define DDRSS1_PHY_1243_DATA 0x00000000 +#define DDRSS1_PHY_1244_DATA 0x00000000 +#define DDRSS1_PHY_1245_DATA 0x00000000 +#define DDRSS1_PHY_1246_DATA 0x00000000 +#define DDRSS1_PHY_1247_DATA 0x00000000 +#define DDRSS1_PHY_1248_DATA 0x00000000 +#define DDRSS1_PHY_1249_DATA 0x00000000 +#define DDRSS1_PHY_1250_DATA 0x00000000 +#define DDRSS1_PHY_1251_DATA 0x00000000 +#define DDRSS1_PHY_1252_DATA 0x00000000 +#define DDRSS1_PHY_1253_DATA 0x00000000 +#define DDRSS1_PHY_1254_DATA 0x00000000 +#define DDRSS1_PHY_1255_DATA 0x00000000 +#define DDRSS1_PHY_1256_DATA 0x00000000 +#define DDRSS1_PHY_1257_DATA 0x00000000 +#define DDRSS1_PHY_1258_DATA 0x00000000 +#define DDRSS1_PHY_1259_DATA 0x00000000 +#define DDRSS1_PHY_1260_DATA 0x00000000 +#define DDRSS1_PHY_1261_DATA 0x00000000 +#define DDRSS1_PHY_1262_DATA 0x00000000 +#define DDRSS1_PHY_1263_DATA 0x00000000 +#define DDRSS1_PHY_1264_DATA 0x00000000 +#define DDRSS1_PHY_1265_DATA 0x00000000 +#define DDRSS1_PHY_1266_DATA 0x00000000 +#define DDRSS1_PHY_1267_DATA 0x00000000 +#define DDRSS1_PHY_1268_DATA 0x00000000 +#define DDRSS1_PHY_1269_DATA 0x00000000 +#define DDRSS1_PHY_1270_DATA 0x00000000 +#define DDRSS1_PHY_1271_DATA 0x00000000 +#define DDRSS1_PHY_1272_DATA 0x00000000 +#define DDRSS1_PHY_1273_DATA 0x00000000 +#define DDRSS1_PHY_1274_DATA 0x00000000 +#define DDRSS1_PHY_1275_DATA 0x00000000 +#define DDRSS1_PHY_1276_DATA 0x00000000 +#define DDRSS1_PHY_1277_DATA 0x00000000 +#define DDRSS1_PHY_1278_DATA 0x00000000 +#define DDRSS1_PHY_1279_DATA 0x00000000 +#define DDRSS1_PHY_1280_DATA 0x00000000 +#define DDRSS1_PHY_1281_DATA 0x00010100 +#define DDRSS1_PHY_1282_DATA 0x00000000 +#define DDRSS1_PHY_1283_DATA 0x00000000 +#define DDRSS1_PHY_1284_DATA 0x00050000 +#define DDRSS1_PHY_1285_DATA 0x04000000 +#define DDRSS1_PHY_1286_DATA 0x00000055 +#define DDRSS1_PHY_1287_DATA 0x00000000 +#define DDRSS1_PHY_1288_DATA 0x00000000 +#define DDRSS1_PHY_1289_DATA 0x00000000 +#define DDRSS1_PHY_1290_DATA 0x00000000 +#define DDRSS1_PHY_1291_DATA 0x00002001 +#define DDRSS1_PHY_1292_DATA 0x0000400F +#define DDRSS1_PHY_1293_DATA 0x50020028 +#define DDRSS1_PHY_1294_DATA 0x01010000 +#define DDRSS1_PHY_1295_DATA 0x80080001 +#define DDRSS1_PHY_1296_DATA 0x10200000 +#define DDRSS1_PHY_1297_DATA 0x00000008 +#define DDRSS1_PHY_1298_DATA 0x00000000 +#define DDRSS1_PHY_1299_DATA 0x01090E00 +#define DDRSS1_PHY_1300_DATA 0x00040101 +#define DDRSS1_PHY_1301_DATA 0x0000010F +#define DDRSS1_PHY_1302_DATA 0x00000000 +#define DDRSS1_PHY_1303_DATA 0x00000064 +#define DDRSS1_PHY_1304_DATA 0x00000000 +#define DDRSS1_PHY_1305_DATA 0x01010000 +#define DDRSS1_PHY_1306_DATA 0x01080402 +#define DDRSS1_PHY_1307_DATA 0x01200F02 +#define DDRSS1_PHY_1308_DATA 0x00194280 +#define DDRSS1_PHY_1309_DATA 0x00000004 +#define DDRSS1_PHY_1310_DATA 0x00042000 +#define DDRSS1_PHY_1311_DATA 0x00000000 +#define DDRSS1_PHY_1312_DATA 0x00000000 +#define DDRSS1_PHY_1313_DATA 0x00000000 +#define DDRSS1_PHY_1314_DATA 0x00000000 +#define DDRSS1_PHY_1315_DATA 0x00000000 +#define DDRSS1_PHY_1316_DATA 0x00000000 +#define DDRSS1_PHY_1317_DATA 0x01000000 +#define DDRSS1_PHY_1318_DATA 0x00000705 +#define DDRSS1_PHY_1319_DATA 0x00000054 +#define DDRSS1_PHY_1320_DATA 0x00030820 +#define DDRSS1_PHY_1321_DATA 0x00010820 +#define DDRSS1_PHY_1322_DATA 0x00010820 +#define DDRSS1_PHY_1323_DATA 0x00010820 +#define DDRSS1_PHY_1324_DATA 0x00010820 +#define DDRSS1_PHY_1325_DATA 0x00010820 +#define DDRSS1_PHY_1326_DATA 0x00010820 +#define DDRSS1_PHY_1327_DATA 0x00010820 +#define DDRSS1_PHY_1328_DATA 0x00010820 +#define DDRSS1_PHY_1329_DATA 0x00000000 +#define DDRSS1_PHY_1330_DATA 0x00000074 +#define DDRSS1_PHY_1331_DATA 0x00000400 +#define DDRSS1_PHY_1332_DATA 0x00000108 +#define DDRSS1_PHY_1333_DATA 0x00000000 +#define DDRSS1_PHY_1334_DATA 0x00000000 +#define DDRSS1_PHY_1335_DATA 0x00000000 +#define DDRSS1_PHY_1336_DATA 0x00000000 +#define DDRSS1_PHY_1337_DATA 0x00000000 +#define DDRSS1_PHY_1338_DATA 0x03000000 +#define DDRSS1_PHY_1339_DATA 0x00000000 +#define DDRSS1_PHY_1340_DATA 0x00000000 +#define DDRSS1_PHY_1341_DATA 0x00000000 +#define DDRSS1_PHY_1342_DATA 0x04102006 +#define DDRSS1_PHY_1343_DATA 0x00041020 +#define DDRSS1_PHY_1344_DATA 0x01C98C98 +#define DDRSS1_PHY_1345_DATA 0x3F400000 +#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS1_PHY_1347_DATA 0x0000001F +#define DDRSS1_PHY_1348_DATA 0x00000000 +#define DDRSS1_PHY_1349_DATA 0x00000000 +#define DDRSS1_PHY_1350_DATA 0x00000000 +#define DDRSS1_PHY_1351_DATA 0x00010000 +#define DDRSS1_PHY_1352_DATA 0x00000000 +#define DDRSS1_PHY_1353_DATA 0x00000000 +#define DDRSS1_PHY_1354_DATA 0x00000000 +#define DDRSS1_PHY_1355_DATA 0x00000000 +#define DDRSS1_PHY_1356_DATA 0x76543210 +#define DDRSS1_PHY_1357_DATA 0x00010198 +#define DDRSS1_PHY_1358_DATA 0x00000000 +#define DDRSS1_PHY_1359_DATA 0x00000000 +#define DDRSS1_PHY_1360_DATA 0x00000000 +#define DDRSS1_PHY_1361_DATA 0x00040700 +#define DDRSS1_PHY_1362_DATA 0x00000000 +#define DDRSS1_PHY_1363_DATA 0x00000000 +#define DDRSS1_PHY_1364_DATA 0x00000000 +#define DDRSS1_PHY_1365_DATA 0x00000000 +#define DDRSS1_PHY_1366_DATA 0x00000000 +#define DDRSS1_PHY_1367_DATA 0x00000002 +#define DDRSS1_PHY_1368_DATA 0x00000000 +#define DDRSS1_PHY_1369_DATA 0x00000000 +#define DDRSS1_PHY_1370_DATA 0x00000000 +#define DDRSS1_PHY_1371_DATA 0x00000000 +#define DDRSS1_PHY_1372_DATA 0x00000000 +#define DDRSS1_PHY_1373_DATA 0x00000000 +#define DDRSS1_PHY_1374_DATA 0x00080000 +#define DDRSS1_PHY_1375_DATA 0x000007FF +#define DDRSS1_PHY_1376_DATA 0x00000000 +#define DDRSS1_PHY_1377_DATA 0x00000000 +#define DDRSS1_PHY_1378_DATA 0x00000000 +#define DDRSS1_PHY_1379_DATA 0x00000000 +#define DDRSS1_PHY_1380_DATA 0x00000000 +#define DDRSS1_PHY_1381_DATA 0x00000000 +#define DDRSS1_PHY_1382_DATA 0x000FFFFF +#define DDRSS1_PHY_1383_DATA 0x000FFFFF +#define DDRSS1_PHY_1384_DATA 0x0000FFFF +#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS1_PHY_1386_DATA 0x030FFFFF +#define DDRSS1_PHY_1387_DATA 0x01FFFFFF +#define DDRSS1_PHY_1388_DATA 0x0000FFFF +#define DDRSS1_PHY_1389_DATA 0x00000000 +#define DDRSS1_PHY_1390_DATA 0x00000000 +#define DDRSS1_PHY_1391_DATA 0x00000000 +#define DDRSS1_PHY_1392_DATA 0x00000000 +#define DDRSS1_PHY_1393_DATA 0x0001F7C0 +#define DDRSS1_PHY_1394_DATA 0x00000003 +#define DDRSS1_PHY_1395_DATA 0x00000000 +#define DDRSS1_PHY_1396_DATA 0x00001142 +#define DDRSS1_PHY_1397_DATA 0x040207AB +#define DDRSS1_PHY_1398_DATA 0x01000080 +#define DDRSS1_PHY_1399_DATA 0x03900390 +#define DDRSS1_PHY_1400_DATA 0x03900390 +#define DDRSS1_PHY_1401_DATA 0x00000390 +#define DDRSS1_PHY_1402_DATA 0x00000390 +#define DDRSS1_PHY_1403_DATA 0x00000390 +#define DDRSS1_PHY_1404_DATA 0x00000390 +#define DDRSS1_PHY_1405_DATA 0x00000005 +#define DDRSS1_PHY_1406_DATA 0x01813FCC +#define DDRSS1_PHY_1407_DATA 0x000000CC +#define DDRSS1_PHY_1408_DATA 0x0C000DFF +#define DDRSS1_PHY_1409_DATA 0x30000DFF +#define DDRSS1_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1411_DATA 0x000100F0 +#define DDRSS1_PHY_1412_DATA 0x780DFFCC +#define DDRSS1_PHY_1413_DATA 0x00007E31 +#define DDRSS1_PHY_1414_DATA 0x000CBF11 +#define DDRSS1_PHY_1415_DATA 0x01990010 +#define DDRSS1_PHY_1416_DATA 0x000CBF11 +#define DDRSS1_PHY_1417_DATA 0x01990010 +#define DDRSS1_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1419_DATA 0x00EF00F0 +#define DDRSS1_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1421_DATA 0x01FF00F0 +#define DDRSS1_PHY_1422_DATA 0x20040006 + + diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts index b61d22b3b4b..c43e7a1c46e 100644 --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-am68-sk-base-board.dts" -#include "k3-j721s2-ddr-evm-lp4-4266.dtsi" +#include "k3-am68-ddr-sk-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" #include "k3-am68-sk-base-board-u-boot.dtsi" #include "k3-j721s2-r5.dtsi" diff --git a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi index 5b8b8539da3..c3a66ac8dae 100644 --- a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2025 Toradex - https://www.toradex.com/ */ -#define SPL_BOARD_DTB "spl/dts/k3-am69-aquila-dev.dtb" +#define SPL_BOARD_DTB "spl/dts/ti/k3-am69-aquila-dev.dtb" #define BOARD_DESCRIPTION "k3-am69-aquila" #define UBOOT_BOARD_DESCRIPTION "U-Boot for AM69 Aquila board" @@ -12,6 +12,11 @@ #if defined(CONFIG_CPU_V7R) &binman { + tiboot3_am69_gp { + insert-template = <&tiboot3_j784s4_gp>; + filename = "tiboot3-am69-gp-aquila.bin"; + }; + tiboot3-am69-hs { insert-template = <&tiboot3_j784s4_hs>; filename = "tiboot3-am69-hs-aquila.bin"; @@ -28,6 +33,10 @@ filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin"; }; +&ti_fs_gp { + filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin"; +}; + &sysfw_inner_cert { filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin"; }; @@ -78,6 +87,72 @@ u-boot-unsigned { insert-template = <&u_boot_unsigned>; }; + + firmware-aquila-am69-gp.bin { + filename = "firmware-aquila-am69-gp.bin"; + + blob-ext@1 { + filename = "tiboot3-am69-gp-aquila.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin_unsigned"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img_unsigned"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-aquila-am69-hs.bin { + filename = "firmware-aquila-am69-hs.bin"; + + blob-ext@1 { + filename = "tiboot3-am69-hs-aquila.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-aquila-am69-hs-fs.bin { + filename = "firmware-aquila-am69-hs-fs.bin"; + + blob-ext@1 { + filename = "tiboot3-am69-hs-fs-aquila.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; }; #endif diff --git a/arch/arm/dts/k3-am69-aquila-dev.dts b/arch/arm/dts/k3-am69-aquila-dev.dts deleted file mode 100644 index c7ce804eac7..00000000000 --- a/arch/arm/dts/k3-am69-aquila-dev.dts +++ /dev/null @@ -1,576 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2025 Toradex - * - * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 - * https://www.toradex.com/products/carrier-board/aquila-development-board-kit - */ - -/dts-v1/; - -#include <dt-bindings/pwm/pwm.h> -#include "k3-am69-aquila.dtsi" - -/ { - model = "Toradex Aquila AM69 on Aquila Development Board"; - compatible = "toradex,aquila-am69-dev", - "toradex,aquila-am69", - "ti,j784s4"; - - aliases { - eeprom1 = &carrier_eeprom; - }; - - reg_1v8_sw: regulator-1v8-sw { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "Carrier_1V8"; - }; - - reg_3v3_dp: regulator-3v3-dp { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_21_dp>; - /* Aquila GPIO_21_DP (AQUILA B57) */ - gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "DP_3V3"; - startup-delay-us = <10000>; - }; - - dp0-connector { - compatible = "dp-connector"; - dp-pwr-supply = <®_3v3_dp>; - label = "Display Port"; - type = "full-size"; - - port { - dp0_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,name = "aquila-wm8904"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Microphone Jack", "MICBIAS", - "IN1L", "Microphone Jack", - "IN1R", "Digital Mic"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Microphone", "Digital Mic", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; - - codec_dai: simple-audio-card,codec { - sound-dai = <&wm8904_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&mcasp4>; - }; - }; -}; - -/* Aquila CTRL_PWR_BTN_MICO# */ -&aquila_key_power { - status = "okay"; -}; - -/* Aquila CTRL_WAKE1_MICO# */ -&aquila_key_wake { - status = "okay"; -}; - -/* On-module ETH_1 MDIO */ -&davinci_mdio { - status = "okay"; -}; - -&dp0_ports { - port@4 { - reg = <4>; - dp0_out: endpoint { - remote-endpoint = <&dp0_connector_in>; - }; - }; -}; - -&dss { - status = "okay"; -}; - -&main0_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main0_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main0_alert1>; - }; - }; -}; - -&main1_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main1_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main1_alert1>; - }; - }; -}; - -&main2_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main2_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main2_alert1>; - }; - }; -}; - -&main3_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main3_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main3_alert1>; - }; - }; -}; - -&main4_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main4_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main4_alert1>; - }; - }; -}; - -/* Aquila ETH_2 */ -&main_cpsw0 { - status = "okay"; -}; - -/* Aquila ETH_2 SGMII PHY */ -&main_cpsw0_port8 { - phy-handle = <&cpsw0_port8_phy4>; - status = "okay"; -}; - -/* Aquila ETH_2_XGMII_MDIO */ -&main_cpsw0_mdio { - status = "okay"; - - cpsw0_port8_phy4: ethernet-phy@4 { - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth2_int>; - interrupt-parent = <&main_gpio0>; - interrupts = <44 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -/* Aquila PWM_1 */ -&main_ehrpwm0 { - status = "okay"; -}; - -/* Aquila PWM_4_DP */ -&main_ehrpwm2 { - status = "okay"; -}; - -/* Aquila PWM_2 */ -&main_ehrpwm1 { - status = "okay"; -}; - -/* Aquila PWM_3_DSI */ -&main_ehrpwm5 { - status = "okay"; -}; - -&main_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_01>, /* Aquila GPIO_01 */ - <&pinctrl_gpio_02>, /* Aquila GPIO_02 */ - <&pinctrl_gpio_03>; /* Aquila GPIO_03 */ -}; - -/* Aquila I2C_3_DSI1 */ -&main_i2c0 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - /* I2C on DSI Connector Pin #4 and #6 */ - i2c_dsi_0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* I2C on DSI Connector Pin #52 and #54 */ - i2c_dsi_1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -/* Aquila I2C_4_CSI1 */ -&main_i2c1 { - status = "okay"; -}; - -/* Aquila I2C_5_CSI2 */ -&main_i2c2 { - status = "okay"; -}; - -/* Aquila I2C_6 */ -&main_i2c5 { - status = "okay"; -}; - -/* Aquila CAN_1 */ -&main_mcan10 { - status = "okay"; -}; - -/* Aquila CAN_3 */ -&main_mcan13 { - status = "okay"; -}; - -/* Aquila SD_1 */ -&main_sdhci1 { - status = "okay"; -}; - -/* Aquila SPI_2 */ -&main_spi0 { - status = "okay"; -}; - -/* Aquila SPI_1 */ -&main_spi2 { - status = "okay"; -}; - -/* Aquila UART_1 */ -&main_uart4 { - status = "okay"; -}; - -/* Aquila UART_3, used as the Linux console */ -&main_uart8 { - status = "okay"; -}; - -/* Aquila I2S_1 */ -&mcasp4 { - status = "okay"; -}; - -&mcu_cpsw { - status = "okay"; -}; - -/* On-module ETH_1 RGMII */ -&mcu_cpsw_port1 { - status = "okay"; -}; - -/* Aquila I2C_1 */ -&mcu_i2c0 { - clock-frequency = <100000>; - status = "okay"; - - fan_controller: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #pwm-cells = <2>; - - fan: fan { - cooling-levels = <102 179 255>; - #cooling-cells = <2>; - pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; - }; - }; - - wm8904_1a: audio-codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_extrefclk1>; - #sound-dai-cells = <0>; - clocks = <&audio_refclk1>; - clock-names = "mclk"; - AVDD-supply = <®_1v8_sw>; - CPVDD-supply = <®_1v8_sw>; - DBVDD-supply = <®_1v8_sw>; - DCVDD-supply = <®_1v8_sw>; - MICVDD-supply = <®_1v8_sw>; - - wlf,drc-cfg-names = "default", "peaklimiter"; - /* - * Config registers per name, respectively: - * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 - * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 - */ - wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, - /bits/ 16 <0x04af 0x324b 0x0010 0x0408>; - - /* GPIO1 = DMIC_CLK, don't touch others */ - wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; - - wlf,in1r-as-dmicdat2; - }; - - /* Current measurement into module VCC */ - hwmon@41 { - compatible = "ti,ina226"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - - temperature-sensor@4f { - compatible = "ti,tmp1075"; - reg = <0x4f>; - }; - - /* USB-C OTG (TCPC USB PD PHY) */ - tcpc@52 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x52>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_int>; - interrupt-parent = <&main_gpio0>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; - - connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C OTG"; - power-role = "dual"; - try-power-role = "sink"; - self-powered; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - op-sink-microwatt = <1000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_1_con_hs: endpoint { - remote-endpoint = <&usb0_hs>; - }; - }; - - port@1 { - reg = <1>; - - usb_1_con_ss: endpoint { - remote-endpoint = <&usb0_ss_mux>; - }; - }; - }; - }; - }; - - carrier_eeprom: eeprom@57 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x57>; - pagesize = <16>; - }; -}; - -/* Aquila I2C_2 */ -&mcu_i2c1 { - status = "okay"; -}; - -/* Aquila CAN_2 */ -&mcu_mcan0 { - status = "okay"; -}; - -/* Aquila CAN_4 */ -&mcu_mcan1 { - status = "okay"; -}; - -/* Aquila UART_4 */ -&mcu_uart0 { - status = "okay"; -}; - -&mhdp { - status = "okay"; -}; - -/* Aquila QSPI_1 */ -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_ospi0_4bit>, <&pinctrl_mcu_ospi0_cs0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - cdns,read-delay = <0>; - cdns,tchsh-ns = <3>; - cdns,tsd2d-ns = <10>; - cdns,tshsl-ns = <30>; - cdns,tslch-ns = <8>; - }; -}; - -/* Aquila PCIE_1 */ -&pcie0_rc { - status = "okay"; -}; - -/* Aquila PCIE_2 */ -&pcie1_rc { - status = "okay"; -}; - -&serdes2 { - status = "okay"; -}; - -&serdes4 { - status = "okay"; -}; - -&serdes_wiz2 { - status = "okay"; -}; - -&serdes_wiz4 { - status = "okay"; -}; - -/* Aquila ADC_[1-4] */ -&tscadc0 { - status = "okay"; -}; - -&usbss0 { - status = "okay"; -}; - -&usb0ss_mux { - status = "okay"; - - port { - usb0_ss_mux: endpoint { - remote-endpoint = <&usb_1_con_ss>; - }; - }; -}; - -&usb0 { - status = "okay"; - - port { - usb0_hs: endpoint { - remote-endpoint = <&usb_1_con_hs>; - }; - }; -}; - -&wkup0_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&wkup0_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&wkup0_alert1>; - }; - }; -}; - -&wkup1_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&wkup1_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&wkup1_alert1>; - }; - }; -}; - -&wkup_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_04>, /* Aquila GPIO_04 */ - <&pinctrl_gpio_05>, /* Aquila GPIO_05 */ - <&pinctrl_gpio_06>, /* Aquila GPIO_06 */ - <&pinctrl_gpio_07>, /* Aquila GPIO_07 */ - <&pinctrl_gpio_08>; /* Aquila GPIO_08 */ -}; - -/* Aquila UART_2, through RS485 transceiver */ -&wkup_uart0 { - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - status = "okay"; -}; diff --git a/arch/arm/dts/k3-am69-aquila.dtsi b/arch/arm/dts/k3-am69-aquila.dtsi deleted file mode 100644 index 5e1f92fc85f..00000000000 --- a/arch/arm/dts/k3-am69-aquila.dtsi +++ /dev/null @@ -1,1837 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2025 Toradex - * - * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-cadence.h> -#include <dt-bindings/usb/pd.h> -#include "k3-j784s4.dtsi" - -/ { - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - can0 = &main_mcan10; - can1 = &mcu_mcan0; - can2 = &main_mcan13; - can3 = &mcu_mcan1; - eeprom0 = &som_eeprom; - ethernet0 = &mcu_cpsw_port1; - ethernet1 = &main_cpsw0_port8; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &mcu_i2c1; - i2c3 = &main_i2c0; - i2c4 = &main_i2c1; - i2c5 = &main_i2c2; - i2c6 = &main_i2c5; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - rtc0 = &rtc_i2c; - serial0 = &main_uart4; - serial1 = &wkup_uart0; - serial2 = &main_uart8; - serial3 = &mcu_uart0; - usb0 = &usb0; - }; - - aquila_key_power: gpio-key-power { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwr_btn_int>; - status = "disabled"; - - key-power { - /* Aquila CTRL_PWR_BTN_MICO# (AQUILA B93) */ - gpios = <&wkup_gpio0 36 GPIO_ACTIVE_LOW>; - label = "Power Button"; - linux,code = <KEY_POWER>; - }; - }; - - aquila_key_wake: gpio-key-wakeup { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; - status = "disabled"; - - key-wakeup { - /* Aquila CTRL_WAKE1_MICO# (AQUILA D6) */ - gpios = <&wkup_gpio0 49 GPIO_ACTIVE_LOW>; - label = "Wake Up"; - linux,code = <KEY_WAKEUP>; - wakeup-source; - }; - }; - - /* Aquila CTRL_RESET_MICO# (AQUILA B92) */ - gpio-restart { - compatible = "gpio-restart"; - /* COLD_RESET_REQ */ - gpios = <&som_gpio_expander 1 GPIO_ACTIVE_HIGH>; - priority = <192>; - }; - - /* PWR_DOWN_REQ */ - gpio-poweroff { - compatible = "gpio-poweroff"; - /* PWR_DOWN_REQ */ - gpios = <&som_gpio_expander 2 GPIO_ACTIVE_HIGH>; - timeout-ms = <3000>; - }; - - memory@80000000 { - device_type = "memory"; - /* 32G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x07 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - }; - - /* Module Power Supply (VCC) */ - reg_vin: regulator-vin { - compatible = "regulator-fixed"; - regulator-name = "+V_IN"; - }; - - /* Enabled by EN_3V3_VIO (PMIC_GPIO_9) */ - reg_1v1_usb_bridge: regulator-1v1-vio { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "+V1.1_VIO"; - vin-supply = <®_vin>; - }; - - reg_3v3_wifi: regulator-3v3-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_en_3v3_wifi>; - gpio = <&wkup_gpio0 57 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_WIFI"; - startup-delay-us = <20000>; - vin-supply = <®_vin>; - }; - - reg_1v8_stby: regulator-1v8-stby { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_STBY"; - vin-supply = <®_vin>; - }; - - /* Aquila SD_1_PWR_EN */ - reg_sdhc1_vmmc: regulator-sdhci1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1_pwr_en>; - /* Aquila SD_1_PWR_EN (AQUILA A6) */ - gpio = <&main_gpio0 52 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <100000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+3V3_SD"; - startup-delay-us = <20000>; - }; - - reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { - compatible = "regulator-gpio"; - /* SDIO_PWR_SEL_3.3V */ - gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+VDD_SD_DV"; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - /* On-module USB_1_SS mux */ - usb0ss_mux: gpio-sbu-mux { - compatible = "ti,tmuxhs4212", "gpio-sbu-mux"; - orientation-switch; - /* USB_MUX_SEL */ - select-gpios = <&som_gpio_expander 0 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; -}; - -&main_pmx0 { - /* Aquila DP_1_HPD */ - pinctrl_main_dp0_hpd: main-dp0-hpd-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ /* AQUILA B59 */ - >; - }; - - /* Aquila PWM_1 */ - pinctrl_main_ehrpwm0_b: main-ehrpwm0b-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x064, PIN_OUTPUT, 9) /* (AF38) MCAN0_TX.EHRPWM0_B */ /* AQUILA C25 */ - >; - }; - - /* Aquila PWM_2 */ - pinctrl_main_ehrpwm1_a: main-ehrpwm1a-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x060, PIN_OUTPUT, 9) /* (AE36) MCASP2_AXR1.EHRPWM1_A */ /* AQUILA C26 */ - >; - }; - - /* Aquila PWM_3_DSI */ - pinctrl_main_ehrpwm5_a: main-ehrpwm5a-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x084, PIN_OUTPUT, 9) /* (AG38) MCASP0_AXR5.EHRPWM5_A */ /* AQUILA B46 */ - >; - }; - - /* Aquila PWM_4_DP */ - pinctrl_main_ehrpwm2_a: main-ehrpwm2a-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x040, PIN_INPUT, 9) /* (AF37) MCASP0_AXR0.EHRPWM2_A */ /* AQUILA B58 */ - >; - }; - - /* PMIC_INT# */ - pinctrl_pmic_int: main-gpio0-0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTn.GPIO0_0 */ - >; - }; - - /* Aquila GPIO_09_CSI_1 */ - pinctrl_gpio_09_csi_1: main-gpio0-1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ /* AQUILA B17 */ - >; - }; - - /* Aquila GPIO_10_CSI_1 */ - pinctrl_gpio_10_csi_1: main-gpio0-2-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ /* AQUILA B18 */ - >; - }; - - /* Aquila USB_1_OC# */ - pinctrl_usb1_oc: main-gpio0-10-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x028, PIN_INPUT, 7) /* (AE33) MCAN16_RX.GPIO0_10 */ /* AQUILA B75 */ - >; - }; - - /* Aquila USB_1_EN */ - pinctrl_usb1_en_gpio: main-gpio0-11-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x02c, PIN_INPUT, 7) /* (AL32) GPIO0_11 */ /* AQUILA B77 */ - >; - }; - - /* Aquila GPIO_17_DSI_1 */ - pinctrl_gpio_17_dsi_1: main-gpio0-12-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x030, PIN_INPUT, 7) /* (AK37) GPIO0_12 */ /* AQUILA B42 */ - >; - }; - - /* Aquila GPIO_19_DSI_1 */ - pinctrl_gpio_19_dsi_1: main-gpio0-13-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ /* AQUILA B44 */ - >; - }; - - /* Aquila GPIO_02 */ - pinctrl_gpio_02: main-gpio0-17-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x044, PIN_INPUT, 7) /* (AG37) MCASP0_AXR1.GPIO0_17 */ /* AQUILA D24 */ - >; - }; - - /* Aquila GPIO_20_DSI_1 */ - pinctrl_gpio_20_dsi_1: main-gpio0-18-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x048, PIN_INPUT, 7) /* (AK33) MCASP0_AXR2.GPIO0_18 */ /* AQUILA B45 */ - >; - }; - - /* Aquila GPIO_21_DP */ - pinctrl_gpio_21_dp: main-gpio0-21-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x054, PIN_INPUT, 7) /* (AD37) MCASP2_ACLKX.GPIO0_21 */ /* AQUILA B57 */ - >; - }; - - /* Aquila USB_1_INT# */ - pinctrl_usb1_int: main-gpio0-28-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x070, PIN_INPUT, 7) /* (AH38) MCAN1_RX.GPIO0_28 */ /* AQUILA B74 */ - >; - }; - - /* Aquila GPIO_03 */ - pinctrl_gpio_03: main-gpio0-29-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x074, PIN_INPUT, 7) /* (AC33) MCAN2_TX.GPIO0_29 */ /* AQUILA D25 */ - >; - }; - - /* Aquila GPIO_18_DSI_1 */ - pinctrl_gpio_18_dsi_1: main-gpio0-31-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x07c, PIN_INPUT, 7) /* (AJ38) MCASP0_AXR3.GPIO0_31 */ /* AQUILA B43 */ - >; - }; - - /* Aquila PCIE_1_RESET# */ - pinctrl_pcie0_reset: main-gpio0-32-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x080, PIN_INPUT, 7) /* (AK34) MCASP0_AXR4.GPIO0_32 */ /* AQUILA C38 */ - >; - }; - - /* Aquila PWM_3_DSI as GPIO */ - pinctrl_pwm3_dsi_gpio: main-gpio0-33-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x084, PIN_INPUT, 7) /* (AG38) MCASP0_AXR5.GPIO0_33 */ /* AQUILA B46 */ - >; - }; - - /* Aquila GPIO_01 */ - pinctrl_gpio_01: main-gpio0-34-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x088, PIN_INPUT, 7) /* (AF36) MCASP0_AXR6.GPIO0_34 */ /* AQUILA D23 */ - >; - }; - - /* Aquila PCIE_2_RESET# */ - pinctrl_pcie1_reset: main-gpio0-41-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ /* AQUILA C35 */ - >; - }; - - /* Aquila ETH_2_xGMII_INT# */ - pinctrl_eth2_int: main-gpio0-44-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 7) /* (AL33) MCASP1_AXR3.GPIO0_44 */ /* AQUILA B81 */ - >; - }; - - /* Aquila GPIO_11_CSI_1 */ - pinctrl_gpio_11_csi_1: main-gpio0-47-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ /* AQUILA A11 */ - >; - }; - - /* Aquila GPIO_12_CSI_1 */ - pinctrl_gpio_12_csi_1: main-gpio0-48-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ /* AQUILA B19 */ - >; - }; - - /* Aquila SD_1_PWR_EN */ - pinctrl_sd1_pwr_en: main-gpio0-52-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0d0, PIN_INPUT, 7) /* (AP38) SPI0_CS1.GPIO0_52 */ /* AQUILA A6 */ - >; - }; - - /* Aquila SD_1_CD# as GPIO */ - pinctrl_sd1_cd_gpio: main-gpio0-58-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0e8, PIN_INPUT_PULLUP, 7) /* (AR38) TIMER_IO0.GPIO0_58 */ /* AQUILA A1 */ - >; - }; - - /* Aquila I2C_3_DSI1 */ - pinctrl_main_i2c0: main-i2c0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ /* AQUILA B41 */ - J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ /* AQUILA B40 */ - >; - }; - - /* Aquila I2C_4_CSI1 */ - pinctrl_main_i2c1: main-i2c1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x020, PIN_INPUT_PULLUP, 12) /* (AJ35) MCAN15_RX.I2C1_SCL */ /* AQUILA A13 */ - J784S4_IOPAD(0x024, PIN_INPUT_PULLUP, 12) /* (AH34) MCAN16_TX.I2C1_SDA */ /* AQUILA A12 */ - >; - }; - - /* Aquila I2C_5_CSI2 */ - pinctrl_main_i2c2: main-i2c2-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x04c, PIN_INPUT_PULLUP, 13) /* (AC32) MCASP1_AXR1.I2C2_SCL */ /* AQUILA C6 */ - J784S4_IOPAD(0x050, PIN_INPUT_PULLUP, 13) /* (AC37) MCASP1_AXR2.I2C2_SDA */ /* AQUILA C5 */ - >; - }; - - /* Aquila I2C_6 */ - pinctrl_main_i2c5: main-i2c5-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x01c, PIN_INPUT_PULLUP, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ /* AQUILA C19 */ - J784S4_IOPAD(0x018, PIN_INPUT_PULLUP, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ /* AQUILA C18 */ - >; - }; - - /* Aquila I2S_1_MCLK */ - pinctrl_audio_extrefclk1: audio-extrefclk1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ /* AQUILA B24 */ - >; - }; - - /* Aquila CAN_1 */ - pinctrl_main_mcan10: main-mcan10-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0b8, PIN_INPUT, 0) /* (AC34) MCASP1_ACLKX.MCAN10_RX */ /* AQUILA B49 */ - J784S4_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (AL34) MCASP1_AXR4.MCAN10_TX */ /* AQUILA B48 */ - >; - }; - - /* Aquila CAN_3 */ - pinctrl_main_mcan13: main-mcan13-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x010, PIN_INPUT, 0) /* (AH33) MCAN13_RX */ /* AQUILA B54 */ - J784S4_IOPAD(0x00c, PIN_OUTPUT, 0) /* (AF33) MCAN13_TX */ /* AQUILA B53 */ - >; - }; - - /* Aquila I2S_1 */ - pinctrl_main_mcasp4: main-mcasp4-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0c8, PIN_INPUT, 1) /* (AJ32) EXT_REFCLK1.MCASP4_ACLKX */ /* AQUILA B20 */ - J784S4_IOPAD(0x06c, PIN_INPUT, 1) /* (AJ37) MCAN1_TX.MCASP4_AFSX */ /* AQUILA B21 */ - J784S4_IOPAD(0x068, PIN_OUTPUT, 1) /* (AE38) MCAN0_RX.MCASP4_AXR1 */ /* AQUILA B22 */ - J784S4_IOPAD(0x0c4, PIN_INPUT, 1) /* (AD36) ECAP0_IN_APWM_OUT.MCASP4_AXR2 */ /* AQUILA B23 */ - >; - }; - - /* Aquila ETH_2_XGMII_MDIO */ - pinctrl_main_mdio1: main-mdio1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x058, PIN_OUTPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ /* AQUILA B90 */ - J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ /* AQUILA B89 */ - >; - }; - - /* Aquila SD_1 */ - pinctrl_main_mmc1: main-mmc1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ /* AQUILA A5 */ - J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ /* AQUILA A7 */ - J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ - J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ /* AQUILA A3 */ - J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ /* AQUILA A2 */ - J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ /* AQUILA A10 */ - J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ /* AQUILA A8 */ - >; - }; - - /* Aquila SPI_2 */ - pinctrl_main_spi0: main-spi0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AN38) SPI0_CLK */ /* AQUILA D14 */ - J784S4_IOPAD(0x0d8, PIN_INPUT, 0) /* (AM35) SPI0_D0 */ /* AQUILA D15 */ - J784S4_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (AM36) SPI0_D1 */ /* AQUILA D17 */ - >; - }; - - /* Aquila SPI_2 CS */ - pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */ - >; - }; - - /* Aquila SPI_1 */ - pinctrl_main_spi2: main-spi2-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0a0, PIN_OUTPUT, 10) /* (AD34) MCASP0_AXR12.SPI2_CLK */ /* AQUILA D12 */ - J784S4_IOPAD(0x0a8, PIN_INPUT, 10) /* (AF34) MCASP0_AXR14.SPI2_D0 */ /* AQUILA D10 */ - J784S4_IOPAD(0x0ac, PIN_OUTPUT, 10) /* (AE34) MCASP0_AXR15.SPI2_D1 */ /* AQUILA D11 */ - >; - }; - - /* Aquila SPI_1 CS */ - pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */ - >; - }; - - /* Aquila UART_1 */ - pinctrl_main_uart4: main-uart4-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x094, PIN_INPUT, 11) /* (AG35) MCASP0_AXR9.UART4_CTSn */ /* AQUILA B36 */ - J784S4_IOPAD(0x098, PIN_OUTPUT, 11) /* (AH36) MCASP0_AXR10.UART4_RTSn */ /* AQUILA B38 */ - J784S4_IOPAD(0x08c, PIN_INPUT, 11) /* (AE35) MCASP0_AXR7.UART4_RXD */ /* AQUILA B35 */ - J784S4_IOPAD(0x090, PIN_OUTPUT, 11) /* (AC35) MCASP0_AXR8.UART4_TXD */ /* AQUILA B37 */ - >; - }; - - /* Aquila UART_3, used as the Linux console */ - pinctrl_main_uart8: main-uart8-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x038, PIN_INPUT, 11) /* (AK35) MCASP0_ACLKX.UART8_RXD */ /* AQUILA D19 */ - J784S4_IOPAD(0x03c, PIN_OUTPUT, 11) /* (AK38) MCASP0_AFSX.UART8_TXD */ /* AQUILA D20 */ - >; - }; -}; - -&wkup_pmx0 { - /* Aquila QSPI_1 (4-bit) */ - pinctrl_mcu_ospi0_4bit: mcu-ospi0-4bit-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ /* AQUILA B65 */ - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ /* AQUILA B68 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ /* AQUILA B67 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ /* AQUILA B61 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ /* AQUILA B60 */ - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ /* AQUILA B63 */ - >; - }; - - /* Aquila QSPI_1 (8-bit) */ - pinctrl_mcu_ospi0_8bit: mcu-ospi0-8bit-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ /* AQUILA B65 */ - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ /* AQUILA B68 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ /* AQUILA B67 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ /* AQUILA B61 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ /* AQUILA B60 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ /* AQUILA B70 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ /* AQUILA B71 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ /* AQUILA B72 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ /* AQUILA B73 */ - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ /* AQUILA B63 */ - >; - }; - - /* Aquila QSPI_1_CS1# */ - pinctrl_mcu_ospi0_cs0: mcu-ospi0-cs0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ /* AQUILA B66 */ - >; - }; - - /* Aquila QSPI_1_CS2# */ - pinctrl_mcu_ospi0_cs1: mcu-ospi0-cs1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (A33) MCU_OSPI0_CSn1 */ /* AQUILA B62 */ - >; - }; - - /* Aquila QSPI_1_SCK as GPIO */ - pinctrl_wkup_gpio_16: wkup-gpio0-16-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (E32) MCU_OSPI0_CLK.WKUP_GPIO0_16 */ /* AQUILA B65 */ - >; - }; - - /* Aquila GPIO_04 */ - pinctrl_gpio_04: wkup-gpio0-17-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (D32) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */ /* AQUILA C20 */ - >; - }; - - /* Aquila QSPI_1_DQS as GPIO */ - pinctrl_wkup_gpio_18: wkup-gpio0-18-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (C34) MCU_OSPI0_DQS.WKUP_GPIO0_18 */ /* AQUILA B63 */ - >; - }; - - /* Aquila QSPI_1_IO0 as GPIO */ - pinctrl_wkup_gpio_19: wkup-gpio0-19-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (B33) MCU_OSPI0_D0.WKUP_GPIO0_19 */ /* AQUILA B68 */ - >; - }; - - /* Aquila QSPI_1_IO1 as GPIO */ - pinctrl_wkup_gpio_20: wkup-gpio0-20-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (B32) MCU_OSPI0_D1.WKUP_GPIO0_20 */ /* AQUILA B67 */ - >; - }; - - /* Aquila QSPI_1_IO2 as GPIO */ - pinctrl_wkup_gpio_21: wkup-gpio0-21-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (C33) MCU_OSPI0_D2.WKUP_GPIO0_21 */ /* AQUILA B61 */ - >; - }; - - /* Aquila QSPI_1_IO3 as GPIO */ - pinctrl_wkup_gpio_22: wkup-gpio0-22-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 7) /* (C35) MCU_OSPI0_D3.WKUP_GPIO0_22 */ /* AQUILA B60 */ - >; - }; - - /* Aquila QSPI_1_IO4 as GPIO */ - pinctrl_wkup_gpio_23: wkup-gpio0-23-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (D33) MCU_OSPI0_D4.WKUP_GPIO0_23 */ /* AQUILA B70 */ - >; - }; - - /* Aquila QSPI_1_IO5 as GPIO */ - pinctrl_wkup_gpio_24: wkup-gpio0-24-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (D34) MCU_OSPI0_D5.WKUP_GPIO0_24 */ /* AQUILA B71 */ - >; - }; - - /* Aquila QSPI_1_IO6 as GPIO */ - pinctrl_wkup_gpio_25: wkup-gpio0-25-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (E34) MCU_OSPI0_D6.WKUP_GPIO0_25 */ /* AQUILA B72 */ - >; - }; - - /* Aquila QSPI_1_IO7 as GPIO */ - pinctrl_wkup_gpio_26: wkup-gpio0-26-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (E33) MCU_OSPI0_D7.WKUP_GPIO0_26 */ /* AQUILA B73 */ - >; - }; - - /* Aquila QSPI_1_CS#1 as GPIO */ - pinctrl_wkup_gpio_27: wkup-gpio0-27-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 7) /* (A32) MCU_OSPI0_CSn0.WKUP_GPIO0_27 */ /* AQUILA B66 */ - >; - }; - - /* Aquila QSPI_1_CS#2 as GPIO */ - pinctrl_wkup_gpio_28: wkup-gpio0-28-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 7) /* (A33) MCU_OSPI0_CSn1.WKUP_GPIO0_28 */ /* AQUILA B62 */ - >; - }; -}; - -&wkup_pmx1 { - /* Aquila UART_4 (RXD) */ - pinctrl_mcu_uart0_rx: mcu-uart0-rx-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 4) /* (D31) MCU_OSPI1_D1.MCU_UART0_RXD */ /* AQUILA D21 */ - >; - }; - - /* Aquila GPIO_05 */ - pinctrl_gpio_05: wkup-gpio0-29-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (B34) MCU_OSPI0_CSn2.WKUP_GPIO0_29 */ /* AQUILA C21 */ - >; - }; - - /* Aquila GPIO_06 */ - pinctrl_gpio_06: wkup-gpio0-30-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (C32) MCU_OSPI0_CSn3.WKUP_GPIO0_30 */ /* AQUILA C22 */ - >; - }; - - /* Aquila GPIO_07 */ - pinctrl_gpio_07: wkup-gpio0-31-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (F32) MCU_OSPI1_CLK.WKUP_GPIO0_31 */ /* AQUILA C23 */ - >; - }; - - /* Aquila GPIO_13_CSI_2 */ - pinctrl_gpio_13_csi_2: wkup-gpio0-32-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (C31) MCU_OSPI1_LBCLKO.WKUP_GPIO0_32 */ /* AQUILA C1 */ - >; - }; - - /* Aquila GPIO_14_CSI_2 */ - pinctrl_gpio_14_csi_2: wkup-gpio0-33-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (F31) MCU_OSPI1_DQS.WKUP_GPIO0_33 */ /* AQUILA C2 */ - >; - }; - - /* RTC_IRQ# */ - pinctrl_rtc_irq: wkup-gpio0-34-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (E35) MCU_OSPI1_D0.WKUP_GPIO0_34 */ - >; - }; - - /* Aquila CTRL_PWR_BTN_MICO# (PWR_BTN_INT#) */ - pinctrl_pwr_btn_int: wkup-gpio0-36-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT_PULLUP, 7) /* (G31) MCU_OSPI1_D2.WKUP_GPIO0_36 */ /* AQUILA B92 */ - >; - }; - - /* Aquila GPIO_15_CSI_2 */ - pinctrl_gpio_15_csi_2: wkup-gpio0-37-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (F33) MCU_OSPI1_D3.WKUP_GPIO0_37 */ /* AQUILA C3 */ - >; - }; - - /* Aquila GPIO_08 */ - pinctrl_gpio_08: wkup-gpio0-38-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (G32) MCU_OSPI1_CSn0.WKUP_GPIO0_38 */ /* AQUILA C24 */ - >; - }; - - /* Aquila GPIO_16_CSI_2 */ - pinctrl_gpio_16_csi_2: wkup-gpio0-39-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ /* AQUILA C4 */ - >; - }; -}; - -&wkup_pmx2 { - /* Aquila ADC_[1-4] */ - pinctrl_mcu_adc0: mcu-adc0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (P36) MCU_ADC0_AIN0 */ /* AQUILA D1 */ - J784S4_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V36) MCU_ADC0_AIN1 */ /* AQUILA D2 */ - J784S4_WKUP_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (T34) MCU_ADC0_AIN2 */ /* AQUILA D3 */ - J784S4_WKUP_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (T36) MCU_ADC0_AIN3 */ /* AQUILA D4 */ - >; - }; - - /* Aquila CTRL_MCLK_MOCI */ - pinctrl_mcu_clkout0: mcu-clkout0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x084, PIN_OUTPUT, 6) /* (M38) WKUP_GPIO0_11.MCU_CLKOUT0 */ /* AQUILA A14 */ - >; - }; - - /* Aquila I2C_1 */ - pinctrl_mcu_i2c0: mcu-i2c0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (M35) MCU_I2C0_SCL */ /* AQUILA D8 */ - J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (G34) MCU_I2C0_SDA */ /* AQUILA D7 */ - >; - }; - - /* Aquila I2C_2 */ - pinctrl_mcu_i2c1: mcu-i2c1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ /* AQUILA C17 */ - J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ /* AQUILA C16 */ - >; - }; - - /* Aquila CAN_2 */ - pinctrl_mcu_mcan0: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ /* AQUILA B51 */ - J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ /* AQUILA B50 */ - >; - }; - - /* Aquila CAN_4 */ - pinctrl_mcu_mcan1: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ /* AQUILA B56 */ - J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ /* AQUILA B55 */ - >; - }; - - /* On-module ETH_1 MDIO */ - pinctrl_mcu_mdio: mcu-mdio-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ - J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ - >; - }; - - /* On-module ETH_1 RGMII */ - pinctrl_mcu_rgmii1: mcu-rgmii1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ - J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ - J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ - J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ - J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ - J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ - J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ - >; - }; - - /* On-module SPI (TPM_SPI) */ - pinctrl_mcu_spi0: mcu-spi0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (G38) MCU_SPI0_CLK */ - J784S4_WKUP_IOPAD(0x044, PIN_OUTPUT, 0) /* (F37) MCU_SPI0_CS0 */ - J784S4_WKUP_IOPAD(0x03c, PIN_INPUT, 0) /* (H36) MCU_SPI0_D0 */ - J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (J38) MCU_SPI0_D1 */ - >; - }; - - /* Aquila UART_4 (TX) */ - pinctrl_mcu_uart0_tx: mcu-uart0-tx-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 2) /* (L33) WKUP_GPIO0_10.MCU_UART0_TXD */ /* AQUILA D22 */ - >; - }; - - /* On-module Wi-Fi Power Enable */ - pinctrl_en_3v3_wifi: wkup-gpio0-57-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ - >; - }; - - /* On-module TPM IRQ# */ - pinctrl_tpm_irq: wkup-gpio0-81-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 7) /* (V34) MCU_ADC1_AIN2.WKUP_GPIO0_81 */ - >; - }; - - /* On-module I2C - WKUP_I2C0 */ - pinctrl_wkup_i2c0: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ - J784S4_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ - >; - }; - - /* Aquila UART_2 */ - pinctrl_wkup_uart0: wkup-uart0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ /* AQUILA B32 */ - J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ /* AQUILA B34 */ - J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ /* AQUILA B31 */ - J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ /* AQUILA B33 */ - >; - }; -}; - -&wkup_pmx3 { - /* Aquila CTRL_WAKE1_MICO# */ - pinctrl_ctrl_wake1_mico: wkup-gpio0-49-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_INPUT_PULLUP, 7) /* (M33) WKUP_GPIO0_49 */ /* AQUILA D6 */ - >; - }; -}; - -/* Aquila I2S_1_MCLK */ -&audio_refclk1 { - assigned-clock-rates = <24576000>; -}; - -/* On-module ETH_1 MDIO */ -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_mdio>; - status = "disabled"; - - mcu_phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&wkup_gpio0>; - interrupts = <79 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&dss { - assigned-clocks = <&k3_clks 218 2>, - <&k3_clks 218 5>; - assigned-clock-parents = <&k3_clks 218 3>, - <&k3_clks 218 7>; - status = "disabled"; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; -}; - -&dp0_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; -}; - -&main0_crit { - temperature = <105000>; -}; - -&main0_thermal { - trips { - main0_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main0_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&main1_crit { - temperature = <105000>; -}; - -&main1_thermal { - trips { - main1_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main1_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&main2_crit { - temperature = <105000>; -}; - -&main2_thermal { - trips { - main2_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main2_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&main3_crit { - temperature = <105000>; -}; - -&main3_thermal { - trips { - main3_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main3_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&main4_crit { - temperature = <105000>; -}; - -&main4_thermal { - trips { - main4_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main4_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -/* Aquila ETH_2 SGMII PHY */ -&main_cpsw0_port8 { - phy-mode = "sgmii"; - phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_sgmii_link>; - phy-names = "mac", "serdes"; - status = "disabled"; -}; - -/* Aquila ETH_2_XGMII_MDIO */ -&main_cpsw0_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mdio1>; -}; - -/* Aquila PWM_1 */ -&main_ehrpwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_ehrpwm0_b>; - status = "disabled"; -}; - -/* Aquila PWM_2 */ -&main_ehrpwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_ehrpwm1_a>; - status = "disabled"; -}; - -/* Aquila PWM_4_DP */ -&main_ehrpwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_ehrpwm2_a>; - status = "disabled"; -}; - -/* Aquila PWM_3_DSI */ -&main_ehrpwm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_ehrpwm5_a>; - status = "disabled"; -}; - -&main_gpio0 { - gpio-line-names = - "", /* 0 */ - "AQUILA_B17", - "AQUILA_B18", - "AQUILA_B53", - "AQUILA_B54", - "AQUILA_B59", - "AQUILA_C18", - "AQUILA_C19", - "AQUILA_A13", - "AQUILA_A12", - "AQUILA_B75", /* 10 */ - "AQUILA_B77", - "AQUILA_B42", - "AQUILA_B44", - "AQUILA_D19", - "AQUILA_D20", - "AQUILA_B58", - "AQUILA_D24", - "AQUILA_B45", - "AQUILA_C06", - "AQUILA_C05", /* 20 */ - "AQUILA_B57", - "AQUILA_B90", - "AQUILA_B89", - "AQUILA_C26", - "AQUILA_C25", - "AQUILA_B22", - "AQUILA_B21", - "AQUILA_B74", - "AQUILA_D25", - "AQUILA_B24", /* 30 */ - "AQUILA_B43", - "AQUILA_C38", - "AQUILA_B46", - "AQUILA_D23", - "AQUILA_B35", - "AQUILA_B37", - "AQUILA_B36", - "AQUILA_B38", - "AQUILA_D09", - "AQUILA_D12", /* 40 */ - "AQUILA_C35", - "AQUILA_D10", - "AQUILA_D11", - "AQUILA_B81", - "AQUILA_B48", - "AQUILA_B49", - "AQUILA_A11", - "AQUILA_B19", - "AQUILA_B23", - "AQUILA_B20", /* 50 */ - "AQUILA_D16", - "AQUILA_A06", - "AQUILA_D14", - "AQUILA_D15", - "AQUILA_D17", - "AQUILA_B41", - "AQUILA_B40", - "AQUILA_A01", - "", - "AQUILA_A08", /* 60 */ - "AQUILA_A10", - "AQUILA_A02", - "AQUILA_A03", - "AQUILA_A05", - "AQUILA_A07"; - - status = "okay"; -}; - -/* Aquila I2C_3_DSI1 */ -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c0>; - clock-frequency = <100000>; - status = "disabled"; -}; - -/* Aquila I2C_4_CSI1 */ -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c1>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila I2C_5_CSI2 */ -&main_i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c2>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila I2C_6 */ -&main_i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c5>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila CAN_1 */ -&main_mcan10 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mcan10>; - status = "disabled"; -}; - -/* Aquila CAN_3 */ -&main_mcan13 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mcan13>; - status = "disabled"; -}; - -/* On-module eMMC */ -&main_sdhci0 { - disable-wp; - non-removable; - ti,driver-strength-ohm = <50>; - status = "okay"; -}; - -/* Aquila SD_1 */ -&main_sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mmc1>, <&pinctrl_sd1_cd_gpio>; - cd-gpios = <&main_gpio0 58 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <®_sdhc1_vmmc>; - vqmmc-supply = <®_sdhc1_vqmmc>; - ti,driver-strength-ohm = <50>; - ti,fails-without-test-cd; - status = "disabled"; -}; - -/* Aquila SPI_2 */ -&main_spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>; - status = "disabled"; -}; - -/* Aquila SPI_1 */ -&main_spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>; - status = "disabled"; -}; - -/* Aquila UART_1 */ -&main_uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_uart4>; - status = "disabled"; -}; - -/* Aquila UART_3, used as the Linux console */ -&main_uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_uart8>; - status = "disabled"; -}; - -/* Aquila I2S_1 */ -&mcasp4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mcasp4>; - op-mode = <0>; /* MCASP_I2S_MODE */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 1 2 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tdm-slots = <2>; - #sound-dai-cells = <0>; - status = "disabled"; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_rgmii1>; - status = "disabled"; -}; - -/* On-module ETH_1 RGMII */ -&mcu_cpsw_port1 { - phy-handle = <&mcu_phy0>; - phy-mode = "rgmii-id"; - status = "disabled"; -}; - -/* Aquila I2C_1 */ -&mcu_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_i2c0>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila I2C_2 */ -&mcu_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_i2c1>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila CAN_2 */ -&mcu_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_mcan0>; - status = "disabled"; -}; - -/* Aquila CAN_4 */ -&mcu_mcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_mcan1>; - status = "disabled"; -}; - -/* On-module SPI (TPM_SPI) */ -&mcu_spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_spi0>; - status = "okay"; - - tpm@0 { - compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpm_irq>; - interrupt-parent = <&wkup_gpio0>; - interrupts = <81 IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <33000000>; - }; -}; - -/* Aquila UART_4 */ -&mcu_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_uart0_rx>, <&pinctrl_mcu_uart0_tx>; - status = "disabled"; -}; - -&mhdp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_dp0_hpd>; - phy-names = "dpphy"; - phys = <&serdes4_dp0_link>; - status = "disabled"; -}; - -/* Aquila QSPI_1 */ -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_ospi0_8bit>, <&pinctrl_mcu_ospi0_cs0>; - status = "disabled"; -}; - -/* Aquila PCIE_1 */ -&pcie0_rc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0_reset>; - clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; - clock-names = "fck", "pcie_refclk"; - num-lanes = <2>; - phy-names = "pcie-phy"; - phys = <&serdes1_pcie0_2l_link>; - reset-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; - ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>; - status = "disabled"; -}; - -/* Aquila PCIE_2 */ -&pcie1_rc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1_reset>; - clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; - clock-names = "fck", "pcie_refclk"; - num-lanes = <2>; - phy-names = "pcie-phy"; - phys = <&serdes0_pcie1_2l_link>; - reset-gpios = <&main_gpio0 41 GPIO_ACTIVE_HIGH>; - ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; - status = "disabled"; -}; - -/* On-module PCIe USB Bridge */ -&pcie2_rc { - clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; - clock-names = "fck", "pcie_refclk"; - num-lanes = <1>; - phy-names = "pcie-phy"; - phys = <&serdes1_pcie2_1l_link>; - reset-gpios = <&som_gpio_expander 3 GPIO_ACTIVE_HIGH>; - ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>; - status = "okay"; - - pci@0,0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - usb@0 { - compatible = "pci104c,8241"; - reg = <0x0 0x0 0x0 0x0 0x0>; - ti,pwron-active-high; - }; - }; -}; - -/* PCIE for On-module Wi-Fi */ -&pcie3_rc { - clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; - clock-names = "fck", "pcie_refclk"; - num-lanes = <1>; - phy-names = "pcie-phy"; - phys = <&serdes0_pcie3_1l_link>; - reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_HIGH>; - ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; - status = "okay"; -}; - -&serdes0 { - status = "okay"; - - /* Aquila PCIE_2 */ - serdes0_pcie1_2l_link: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; - cdns,num-lanes = <2>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; - - /* On-module PCIe Wi-Fi */ - serdes0_pcie3_1l_link: phy@2 { - reg = <2>; - #phy-cells = <0>; - resets = <&serdes_wiz0 3>; - cdns,num-lanes = <1>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; - - /* Aquila USB0 SS */ - serdes0_usb0_ss_link: phy@3 { - reg = <3>; - #phy-cells = <0>; - resets = <&serdes_wiz0 4>; - cdns,num-lanes = <1>; - cdns,phy-type = <PHY_TYPE_USB3>; - }; -}; - -&serdes1 { - status = "okay"; - - /* Aquila PCIE_1 */ - serdes1_pcie0_2l_link: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - cdns,num-lanes = <2>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; - - /* On-module PCIe USB Bridge */ - serdes1_pcie2_1l_link: phy@2 { - reg = <2>; - #phy-cells = <0>; - resets = <&serdes_wiz1 3>; - cdns,num-lanes = <1>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; -}; - -&serdes2 { - status = "disabled"; - - /* Aquila ETH_2 xGMII */ - serdes2_sgmii_link: phy@3 { - reg = <3>; - #phy-cells = <0>; - resets = <&serdes_wiz2 4>; - cdns,num-lanes = <1>; - cdns,phy-type = <PHY_TYPE_SGMII>; - }; -}; - -&serdes4 { - status = "disabled"; - - /* Aquila DP_1 */ - serdes4_dp0_link: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, - <&serdes_wiz4 3>, <&serdes_wiz4 4>; - cdns,max-bit-rate = <5400>; - cdns,num-lanes = <4>; - cdns,phy-type = <PHY_TYPE_DP>; - }; -}; - -&serdes_refclk { - clock-frequency = <100000000>; - status = "okay"; -}; - -&serdes_ln_ctrl { - idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, /* Aquila PCIE_2 L0 */ - <J784S4_SERDES0_LANE1_PCIE1_LANE1>, /* Aquila PCIE_2 L1 */ - <J784S4_SERDES0_LANE2_PCIE3_LANE0>, /* On-module PCIe Wi-Fi */ - <J784S4_SERDES0_LANE3_USB>, /* Aquila USB0 SS */ - <J784S4_SERDES1_LANE0_PCIE0_LANE0>, /* Aquila PCIE_1 L0 */ - <J784S4_SERDES1_LANE1_PCIE0_LANE1>, /* Aquila PCIE_1 L1 */ - <J784S4_SERDES1_LANE2_PCIE2_LANE0>, /* On-module PCIe USB Bridge */ - <J784S4_SERDES1_LANE3_QSGMII_LANE2>, /* Aquila SGMII MSP_9 */ - <J784S4_SERDES2_LANE0_QSGMII_LANE5>, /* Aquila SGMII MSP_6 */ - <J784S4_SERDES2_LANE1_QSGMII_LANE6>, /* Aquila SGMII MSP_7 */ - <J784S4_SERDES2_LANE2_QSGMII_LANE7>, /* Aquila SGMII MSP_8 */ - <J784S4_SERDES2_LANE3_QSGMII_LANE8>, /* Aquila ETH_2 xGMII */ - <J784S4_SERDES4_LANE0_EDP_LANE0>, /* Aquila DP L0 */ - <J784S4_SERDES4_LANE1_EDP_LANE1>, /* Aquila DP L1 */ - <J784S4_SERDES4_LANE2_EDP_LANE2>, /* Aquila DP L2 */ - <J784S4_SERDES4_LANE3_EDP_LANE3>; /* Aquila DP L3 */ -}; - -&serdes_wiz0 { - status = "okay"; -}; - -&serdes_wiz1 { - status = "okay"; -}; - -&serdes_wiz2 { - status = "disabled"; -}; - -&serdes_wiz4 { - status = "disabled"; -}; - -/* Aquila ADC_[1-4] */ -&tscadc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_adc0>; - status = "disabled"; - - adc { - ti,adc-channels = <0 1 2 3>; - }; -}; - -&usb0 { - phys = <&serdes0_usb0_ss_link>; - phy-names = "cdns3,usb3-phy"; - dr_mode = "otg"; - maximum-speed = "super-speed"; - usb-role-switch; - status = "disabled"; -}; - -&usb_serdes_mux { - idle-states = <0>; /* USB0 to SERDES lane 3 */ -}; - -&usbss0 { - ti,vbus-divider; - status = "disabled"; -}; - -&wkup_gpio0 { - gpio-line-names = - "", /* 0 */ - "", - "", - "AQUILA_C53", - "AQUILA_B55", - "AQUILA_B56", - "AQUILA_B32", - "AQUILA_B34", - "AQUILA_C17", - "AQUILA_C16", - "AQUILA_D22", /* 10 */ - "", - "", - "", - "", - "", - "AQUILA_B65", - "AQUILA_C20", - "AQUILA_B63", - "AQUILA_B68", - "AQUILA_B67", /* 20 */ - "AQUILA_B61", - "AQUILA_B60", - "AQUILA_B70", - "AQUILA_B71", - "AQUILA_B72", - "AQUILC_B73", - "AQUILA_B66", - "AQUILA_B62", - "AQUILA_C21", - "AQUILA_C22", /* 30 */ - "AQUILA_C23", - "AQUILA_C01", - "AQUILA_C02", - "", - "AQUILA_D21", - "", - "AQUILA_C03", - "AQUILA_C24", - "AQUILA_C04", - "AQUILA_B84", /* 40 */ - "", - "AQUILA_B86", - "AQUILA_B87", - "", - "", - "AQUILA_B83", - "", - "", - "", - "", /* 50 */ - "", - "", - "", - "", - "", - "", - "", - "AQUILA_B31", - "AQUILA_B33", - "AQUILA_B50", /* 60 */ - "AQUILA_B51", - "", - "", - "", - "AQUILA_D08", - "", - "", - "", - "", - "", /* 70 */ - "AQUILA_D01", - "AQUILA_D02", - "AQUILA_D03", - "AQUILA_D04", - "AQUILA_D54", - "AQUILA_D55", - "AQUILA_C55", - "AQUILA_C56", - "", - "AQUILA_C36", /* 80 */ - "", - "", - "", - "", - "", - "", - "AQUILA_D07", - ""; - - status = "okay"; -}; - -/* On-module I2C - WKUP_I2C0 */ -&wkup_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_i2c0>; - clock-frequency = <400000>; - status = "okay"; - - som_gpio_expander: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "USB_MUX_SEL", - "COLD_RESET_REQ", - "PWR_DOWN_REQ", - "PCIE_3_RESET#", - "PCIE_4_RESET#", - "WIFI_DISABLE", - "BT_DISABLE", - "SDIO_PWR_SEL_3.3V"; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - tps62873a: regulator@40 { - compatible = "ti,tps62873"; - reg = <0x40>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <900000>; - regulator-min-microvolt = <600000>; - regulator-name = "+VDD_CPU_AVS"; - }; - - tps62873b: regulator@43 { - compatible = "ti,tps62873"; - reg = <0x43>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <840000>; - regulator-min-microvolt = <760000>; - regulator-name = "+V0.8_VDD_CORE"; - }; - - pmic_tps6594: pmic@48 { - compatible = "ti,tps6594-q1"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic_int>; - interrupt-parent = <&main_gpio0>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - #gpio-cells = <2>; - gpio-controller; - buck12-supply = <®_vin>; - buck3-supply = <®_vin>; - buck4-supply = <®_vin>; - buck5-supply = <®_vin>; - ldo1-supply = <®_vin>; - ldo2-supply = <®_vin>; - ldo3-supply = <®_vin>; - ldo4-supply = <®_vin>; - system-power-controller; - ti,primary-pmic; - - regulators { - reg_vdd_ddr: buck12 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "+V1.1_VDD_DDR (PMIC BUCK12)"; - }; - - reg_vdd_ram: buck3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; - regulator-name = "+V0.85_VDD_RAM (PMIC BUCK3)"; - }; - - reg_vdd_io: buck4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_VDD_IO (PMIC BUCK4)"; - }; - - reg_3v3_vio: buck5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_VIO (PMIC BUCK5)"; - }; - - reg_vda_phy: ldo1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_VDA_PHY (PMIC LDO1)"; - }; - - reg_2v5_eth: ldo2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <2500000>; - regulator-name = "+V2.5_ETH (PMIC LDO2)"; - }; - - reg_vda_dll: ldo3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <800000>; - regulator-min-microvolt = <800000>; - regulator-name = "+V0.8_VDA_DLL (PMIC LDO3)"; - }; - - reg_vda_pll: ldo4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V0.8_VDA_PLL (PMIC LDO4)"; - }; - }; - }; - - temperature-sensor@4f { - compatible = "ti,tmp1075"; - reg = <0x4f>; - }; - - som_eeprom: eeprom@50 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&wkup0_crit { - temperature = <105000>; -}; - -&wkup0_thermal { - trips { - wkup0_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - wkup0_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&wkup1_crit { - temperature = <105000>; -}; - -&wkup1_thermal { - trips { - wkup1_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - wkup1_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&wkup_gpio_intr { - status = "okay"; -}; - -/* Aquila UART_2 */ -&wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_uart0>; - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi new file mode 100644 index 00000000000..6d9c7a6bb06 --- /dev/null +++ b/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi @@ -0,0 +1,8786 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:56:24 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 2 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 3 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS2_PLL_FHS_CNT 5 +#define DDRSS3_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_0 27500000 +#define DDRSS_PLL_FREQUENCY_1 1066500000 +#define DDRSS_PLL_FREQUENCY_2 1066500000 + +#define MULTI_DDR_CFG_INTRLV_GRAN 0 +#define MULTI_DDR_CFG_INTRLV_SIZE 12 +#define MULTI_DDR_CFG_ECC_ENABLE 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 24 +#define MULTI_DDR_CFG_EMIFS_ACTIVE 15 + +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay +#define DDR2_CTL_NODE_STAT okay +#define DDR3_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000007 +#define DDR_REG1_SIZE_LSB 0x80000000 + + +#define DDRSS0_CTL_00_DATA 0x00000B00 +#define DDRSS0_CTL_01_DATA 0x00000000 +#define DDRSS0_CTL_02_DATA 0x00000000 +#define DDRSS0_CTL_03_DATA 0x00000000 +#define DDRSS0_CTL_04_DATA 0x00000000 +#define DDRSS0_CTL_05_DATA 0x00000000 +#define DDRSS0_CTL_06_DATA 0x00000000 +#define DDRSS0_CTL_07_DATA 0x00002AF8 +#define DDRSS0_CTL_08_DATA 0x0001ADAF +#define DDRSS0_CTL_09_DATA 0x00000005 +#define DDRSS0_CTL_10_DATA 0x0000006E +#define DDRSS0_CTL_11_DATA 0x000681C8 +#define DDRSS0_CTL_12_DATA 0x004111C9 +#define DDRSS0_CTL_13_DATA 0x00000005 +#define DDRSS0_CTL_14_DATA 0x000010A9 +#define DDRSS0_CTL_15_DATA 0x000681C8 +#define DDRSS0_CTL_16_DATA 0x004111C9 +#define DDRSS0_CTL_17_DATA 0x00000005 +#define DDRSS0_CTL_18_DATA 0x000010A9 +#define DDRSS0_CTL_19_DATA 0x01010000 +#define DDRSS0_CTL_20_DATA 0x01011001 +#define DDRSS0_CTL_21_DATA 0x02010000 +#define DDRSS0_CTL_22_DATA 0x00020100 +#define DDRSS0_CTL_23_DATA 0x0000000B +#define DDRSS0_CTL_24_DATA 0x0000001C +#define DDRSS0_CTL_25_DATA 0x00000000 +#define DDRSS0_CTL_26_DATA 0x00000000 +#define DDRSS0_CTL_27_DATA 0x03020200 +#define DDRSS0_CTL_28_DATA 0x00005656 +#define DDRSS0_CTL_29_DATA 0x00100000 +#define DDRSS0_CTL_30_DATA 0x00000000 +#define DDRSS0_CTL_31_DATA 0x00000000 +#define DDRSS0_CTL_32_DATA 0x00000000 +#define DDRSS0_CTL_33_DATA 0x00000000 +#define DDRSS0_CTL_34_DATA 0x040C0000 +#define DDRSS0_CTL_35_DATA 0x12501250 +#define DDRSS0_CTL_36_DATA 0x00050804 +#define DDRSS0_CTL_37_DATA 0x09040008 +#define DDRSS0_CTL_38_DATA 0x15000204 +#define DDRSS0_CTL_39_DATA 0x1760008B +#define DDRSS0_CTL_40_DATA 0x1500422B +#define DDRSS0_CTL_41_DATA 0x1760008B +#define DDRSS0_CTL_42_DATA 0x2000422B +#define DDRSS0_CTL_43_DATA 0x000A0A09 +#define DDRSS0_CTL_44_DATA 0x040003C5 +#define DDRSS0_CTL_45_DATA 0x1E161104 +#define DDRSS0_CTL_46_DATA 0x1000922C +#define DDRSS0_CTL_47_DATA 0x1E161110 +#define DDRSS0_CTL_48_DATA 0x1000922C +#define DDRSS0_CTL_49_DATA 0x02030410 +#define DDRSS0_CTL_50_DATA 0x2C060500 +#define DDRSS0_CTL_51_DATA 0x08292C29 +#define DDRSS0_CTL_52_DATA 0x14000E0A +#define DDRSS0_CTL_53_DATA 0x04010A0A +#define DDRSS0_CTL_54_DATA 0x01010004 +#define DDRSS0_CTL_55_DATA 0x0454540A +#define DDRSS0_CTL_56_DATA 0x04313104 +#define DDRSS0_CTL_57_DATA 0x00003131 +#define DDRSS0_CTL_58_DATA 0x00010100 +#define DDRSS0_CTL_59_DATA 0x03010000 +#define DDRSS0_CTL_60_DATA 0x00001508 +#define DDRSS0_CTL_61_DATA 0x00000068 +#define DDRSS0_CTL_62_DATA 0x0000032B +#define DDRSS0_CTL_63_DATA 0x00001035 +#define DDRSS0_CTL_64_DATA 0x0000032B +#define DDRSS0_CTL_65_DATA 0x00001035 +#define DDRSS0_CTL_66_DATA 0x00000005 +#define DDRSS0_CTL_67_DATA 0x00050000 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 +#define DDRSS0_CTL_71_DATA 0x00120103 +#define DDRSS0_CTL_72_DATA 0x00100005 +#define DDRSS0_CTL_73_DATA 0x2F080010 +#define DDRSS0_CTL_74_DATA 0x0505012F +#define DDRSS0_CTL_75_DATA 0x0401030A +#define DDRSS0_CTL_76_DATA 0x041E100B +#define DDRSS0_CTL_77_DATA 0x100B0401 +#define DDRSS0_CTL_78_DATA 0x0001041E +#define DDRSS0_CTL_79_DATA 0x00160016 +#define DDRSS0_CTL_80_DATA 0x033B033B +#define DDRSS0_CTL_81_DATA 0x033B033B +#define DDRSS0_CTL_82_DATA 0x03050505 +#define DDRSS0_CTL_83_DATA 0x03010303 +#define DDRSS0_CTL_84_DATA 0x200B100B +#define DDRSS0_CTL_85_DATA 0x04041004 +#define DDRSS0_CTL_86_DATA 0x200B100B +#define DDRSS0_CTL_87_DATA 0x04041004 +#define DDRSS0_CTL_88_DATA 0x03010000 +#define DDRSS0_CTL_89_DATA 0x00010000 +#define DDRSS0_CTL_90_DATA 0x00000000 +#define DDRSS0_CTL_91_DATA 0x00000000 +#define DDRSS0_CTL_92_DATA 0x01000000 +#define DDRSS0_CTL_93_DATA 0x80104002 +#define DDRSS0_CTL_94_DATA 0x00000000 +#define DDRSS0_CTL_95_DATA 0x00040005 +#define DDRSS0_CTL_96_DATA 0x00000000 +#define DDRSS0_CTL_97_DATA 0x00050000 +#define DDRSS0_CTL_98_DATA 0x00000004 +#define DDRSS0_CTL_99_DATA 0x00000000 +#define DDRSS0_CTL_100_DATA 0x00040005 +#define DDRSS0_CTL_101_DATA 0x00000000 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 +#define DDRSS0_CTL_107_DATA 0x00000000 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 +#define DDRSS0_CTL_114_DATA 0x00000000 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 +#define DDRSS0_CTL_121_DATA 0x00000000 +#define DDRSS0_CTL_122_DATA 0x00007173 +#define DDRSS0_CTL_123_DATA 0x00000000 +#define DDRSS0_CTL_124_DATA 0x00000000 +#define DDRSS0_CTL_125_DATA 0x00000000 +#define DDRSS0_CTL_126_DATA 0x00000000 +#define DDRSS0_CTL_127_DATA 0x00000000 +#define DDRSS0_CTL_128_DATA 0x00000000 +#define DDRSS0_CTL_129_DATA 0x00000000 +#define DDRSS0_CTL_130_DATA 0x00000000 +#define DDRSS0_CTL_131_DATA 0x0B030500 +#define DDRSS0_CTL_132_DATA 0x00040B04 +#define DDRSS0_CTL_133_DATA 0x0A090000 +#define DDRSS0_CTL_134_DATA 0x0A090701 +#define DDRSS0_CTL_135_DATA 0x0900000E +#define DDRSS0_CTL_136_DATA 0x0907010A +#define DDRSS0_CTL_137_DATA 0x00000E0A +#define DDRSS0_CTL_138_DATA 0x07010A09 +#define DDRSS0_CTL_139_DATA 0x000E0A09 +#define DDRSS0_CTL_140_DATA 0x07000401 +#define DDRSS0_CTL_141_DATA 0x00000000 +#define DDRSS0_CTL_142_DATA 0x00000000 +#define DDRSS0_CTL_143_DATA 0x00000000 +#define DDRSS0_CTL_144_DATA 0x00000000 +#define DDRSS0_CTL_145_DATA 0x00000000 +#define DDRSS0_CTL_146_DATA 0x00000000 +#define DDRSS0_CTL_147_DATA 0x00000000 +#define DDRSS0_CTL_148_DATA 0x08080000 +#define DDRSS0_CTL_149_DATA 0x01000000 +#define DDRSS0_CTL_150_DATA 0x800000C0 +#define DDRSS0_CTL_151_DATA 0x800000C0 +#define DDRSS0_CTL_152_DATA 0x800000C0 +#define DDRSS0_CTL_153_DATA 0x00000000 +#define DDRSS0_CTL_154_DATA 0x00001500 +#define DDRSS0_CTL_155_DATA 0x00000000 +#define DDRSS0_CTL_156_DATA 0x00000001 +#define DDRSS0_CTL_157_DATA 0x00000002 +#define DDRSS0_CTL_158_DATA 0x0000100E +#define DDRSS0_CTL_159_DATA 0x00000000 +#define DDRSS0_CTL_160_DATA 0x00000000 +#define DDRSS0_CTL_161_DATA 0x00000000 +#define DDRSS0_CTL_162_DATA 0x00000000 +#define DDRSS0_CTL_163_DATA 0x00000000 +#define DDRSS0_CTL_164_DATA 0x000B0000 +#define DDRSS0_CTL_165_DATA 0x000E0006 +#define DDRSS0_CTL_166_DATA 0x000E0404 +#define DDRSS0_CTL_167_DATA 0x00D601AB +#define DDRSS0_CTL_168_DATA 0x10100216 +#define DDRSS0_CTL_169_DATA 0x01AB0216 +#define DDRSS0_CTL_170_DATA 0x021600D6 +#define DDRSS0_CTL_171_DATA 0x02161010 +#define DDRSS0_CTL_172_DATA 0x00000000 +#define DDRSS0_CTL_173_DATA 0x00000000 +#define DDRSS0_CTL_174_DATA 0x00000000 +#define DDRSS0_CTL_175_DATA 0x3FF40084 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 +#define DDRSS0_CTL_178_DATA 0x35000000 +#define DDRSS0_CTL_179_DATA 0x27270035 +#define DDRSS0_CTL_180_DATA 0x0F0F0000 +#define DDRSS0_CTL_181_DATA 0x16000000 +#define DDRSS0_CTL_182_DATA 0x00841616 +#define DDRSS0_CTL_183_DATA 0x3FF43FF4 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 +#define DDRSS0_CTL_185_DATA 0x00000000 +#define DDRSS0_CTL_186_DATA 0x00353500 +#define DDRSS0_CTL_187_DATA 0x00002727 +#define DDRSS0_CTL_188_DATA 0x00000F0F +#define DDRSS0_CTL_189_DATA 0x16161600 +#define DDRSS0_CTL_190_DATA 0x00000020 +#define DDRSS0_CTL_191_DATA 0x01000000 +#define DDRSS0_CTL_192_DATA 0x00000001 +#define DDRSS0_CTL_193_DATA 0x00000000 +#define DDRSS0_CTL_194_DATA 0x01000000 +#define DDRSS0_CTL_195_DATA 0x00000001 +#define DDRSS0_CTL_196_DATA 0x00000000 +#define DDRSS0_CTL_197_DATA 0x00000000 +#define DDRSS0_CTL_198_DATA 0x00000000 +#define DDRSS0_CTL_199_DATA 0x00000000 +#define DDRSS0_CTL_200_DATA 0x00000000 +#define DDRSS0_CTL_201_DATA 0x00000000 +#define DDRSS0_CTL_202_DATA 0x00000000 +#define DDRSS0_CTL_203_DATA 0x00000000 +#define DDRSS0_CTL_204_DATA 0x00000000 +#define DDRSS0_CTL_205_DATA 0x00000000 +#define DDRSS0_CTL_206_DATA 0x02000000 +#define DDRSS0_CTL_207_DATA 0x01080101 +#define DDRSS0_CTL_208_DATA 0x00000000 +#define DDRSS0_CTL_209_DATA 0x00000000 +#define DDRSS0_CTL_210_DATA 0x00000000 +#define DDRSS0_CTL_211_DATA 0x00000000 +#define DDRSS0_CTL_212_DATA 0x00000000 +#define DDRSS0_CTL_213_DATA 0x00000000 +#define DDRSS0_CTL_214_DATA 0x00000000 +#define DDRSS0_CTL_215_DATA 0x00000000 +#define DDRSS0_CTL_216_DATA 0x00000000 +#define DDRSS0_CTL_217_DATA 0x00000000 +#define DDRSS0_CTL_218_DATA 0x00000000 +#define DDRSS0_CTL_219_DATA 0x00000000 +#define DDRSS0_CTL_220_DATA 0x00000000 +#define DDRSS0_CTL_221_DATA 0x00000000 +#define DDRSS0_CTL_222_DATA 0x00001000 +#define DDRSS0_CTL_223_DATA 0x006403E8 +#define DDRSS0_CTL_224_DATA 0x00000000 +#define DDRSS0_CTL_225_DATA 0x00000000 +#define DDRSS0_CTL_226_DATA 0x00000000 +#define DDRSS0_CTL_227_DATA 0x15110000 +#define DDRSS0_CTL_228_DATA 0x00040C18 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 +#define DDRSS0_CTL_231_DATA 0x00000000 +#define DDRSS0_CTL_232_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 +#define DDRSS0_CTL_235_DATA 0x00000000 +#define DDRSS0_CTL_236_DATA 0x00000000 +#define DDRSS0_CTL_237_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 +#define DDRSS0_CTL_240_DATA 0x00000000 +#define DDRSS0_CTL_241_DATA 0x00000000 +#define DDRSS0_CTL_242_DATA 0x00030000 +#define DDRSS0_CTL_243_DATA 0x00000000 +#define DDRSS0_CTL_244_DATA 0x00000000 +#define DDRSS0_CTL_245_DATA 0x00000000 +#define DDRSS0_CTL_246_DATA 0x00000000 +#define DDRSS0_CTL_247_DATA 0x00000000 +#define DDRSS0_CTL_248_DATA 0x00000000 +#define DDRSS0_CTL_249_DATA 0x00000000 +#define DDRSS0_CTL_250_DATA 0x00000000 +#define DDRSS0_CTL_251_DATA 0x00000000 +#define DDRSS0_CTL_252_DATA 0x00000000 +#define DDRSS0_CTL_253_DATA 0x00000000 +#define DDRSS0_CTL_254_DATA 0x00000000 +#define DDRSS0_CTL_255_DATA 0x00000000 +#define DDRSS0_CTL_256_DATA 0x00000000 +#define DDRSS0_CTL_257_DATA 0x01000200 +#define DDRSS0_CTL_258_DATA 0x00370040 +#define DDRSS0_CTL_259_DATA 0x00020008 +#define DDRSS0_CTL_260_DATA 0x00400100 +#define DDRSS0_CTL_261_DATA 0x00400855 +#define DDRSS0_CTL_262_DATA 0x01000200 +#define DDRSS0_CTL_263_DATA 0x08550040 +#define DDRSS0_CTL_264_DATA 0x00000040 +#define DDRSS0_CTL_265_DATA 0x006B0003 +#define DDRSS0_CTL_266_DATA 0x0100006B +#define DDRSS0_CTL_267_DATA 0x03030303 +#define DDRSS0_CTL_268_DATA 0x00000000 +#define DDRSS0_CTL_269_DATA 0x00000202 +#define DDRSS0_CTL_270_DATA 0x00001FFF +#define DDRSS0_CTL_271_DATA 0x3FFF2000 +#define DDRSS0_CTL_272_DATA 0x03FF0000 +#define DDRSS0_CTL_273_DATA 0x000103FF +#define DDRSS0_CTL_274_DATA 0x0FFF0B00 +#define DDRSS0_CTL_275_DATA 0x01010001 +#define DDRSS0_CTL_276_DATA 0x01010101 +#define DDRSS0_CTL_277_DATA 0x01180101 +#define DDRSS0_CTL_278_DATA 0x00030000 +#define DDRSS0_CTL_279_DATA 0x00000000 +#define DDRSS0_CTL_280_DATA 0x00000000 +#define DDRSS0_CTL_281_DATA 0x00000000 +#define DDRSS0_CTL_282_DATA 0x00000000 +#define DDRSS0_CTL_283_DATA 0x00000000 +#define DDRSS0_CTL_284_DATA 0x00000000 +#define DDRSS0_CTL_285_DATA 0x00000000 +#define DDRSS0_CTL_286_DATA 0x00040101 +#define DDRSS0_CTL_287_DATA 0x04010100 +#define DDRSS0_CTL_288_DATA 0x00000000 +#define DDRSS0_CTL_289_DATA 0x00000000 +#define DDRSS0_CTL_290_DATA 0x03030300 +#define DDRSS0_CTL_291_DATA 0x00010101 +#define DDRSS0_CTL_292_DATA 0x00000000 +#define DDRSS0_CTL_293_DATA 0x00000000 +#define DDRSS0_CTL_294_DATA 0x00000000 +#define DDRSS0_CTL_295_DATA 0x00000000 +#define DDRSS0_CTL_296_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF +#define DDRSS0_CTL_299_DATA 0x00000000 +#define DDRSS0_CTL_300_DATA 0x00000000 +#define DDRSS0_CTL_301_DATA 0x00000000 +#define DDRSS0_CTL_302_DATA 0x00000000 +#define DDRSS0_CTL_303_DATA 0x00000000 +#define DDRSS0_CTL_304_DATA 0x00000000 +#define DDRSS0_CTL_305_DATA 0x00000000 +#define DDRSS0_CTL_306_DATA 0x00000000 +#define DDRSS0_CTL_307_DATA 0x00000000 +#define DDRSS0_CTL_308_DATA 0x00000000 +#define DDRSS0_CTL_309_DATA 0x00000000 +#define DDRSS0_CTL_310_DATA 0x00000000 +#define DDRSS0_CTL_311_DATA 0x00000000 +#define DDRSS0_CTL_312_DATA 0x00000000 +#define DDRSS0_CTL_313_DATA 0x01000000 +#define DDRSS0_CTL_314_DATA 0x00020201 +#define DDRSS0_CTL_315_DATA 0x01000101 +#define DDRSS0_CTL_316_DATA 0x01010001 +#define DDRSS0_CTL_317_DATA 0x00010101 +#define DDRSS0_CTL_318_DATA 0x050A0A03 +#define DDRSS0_CTL_319_DATA 0x10082323 +#define DDRSS0_CTL_320_DATA 0x00090310 +#define DDRSS0_CTL_321_DATA 0x0B0C030F +#define DDRSS0_CTL_322_DATA 0x0B0C0306 +#define DDRSS0_CTL_323_DATA 0x0C090006 +#define DDRSS0_CTL_324_DATA 0x0100000C +#define DDRSS0_CTL_325_DATA 0x08040801 +#define DDRSS0_CTL_326_DATA 0x00000004 +#define DDRSS0_CTL_327_DATA 0x00000000 +#define DDRSS0_CTL_328_DATA 0x00010000 +#define DDRSS0_CTL_329_DATA 0x00280D00 +#define DDRSS0_CTL_330_DATA 0x00000001 +#define DDRSS0_CTL_331_DATA 0x00030001 +#define DDRSS0_CTL_332_DATA 0x00000000 +#define DDRSS0_CTL_333_DATA 0x00000000 +#define DDRSS0_CTL_334_DATA 0x00000000 +#define DDRSS0_CTL_335_DATA 0x00000000 +#define DDRSS0_CTL_336_DATA 0x00000000 +#define DDRSS0_CTL_337_DATA 0x00000000 +#define DDRSS0_CTL_338_DATA 0x00000000 +#define DDRSS0_CTL_339_DATA 0x00000000 +#define DDRSS0_CTL_340_DATA 0x01000000 +#define DDRSS0_CTL_341_DATA 0x00000001 +#define DDRSS0_CTL_342_DATA 0x00010100 +#define DDRSS0_CTL_343_DATA 0x03030000 +#define DDRSS0_CTL_344_DATA 0x00000000 +#define DDRSS0_CTL_345_DATA 0x00000000 +#define DDRSS0_CTL_346_DATA 0x00000000 +#define DDRSS0_CTL_347_DATA 0x00000000 +#define DDRSS0_CTL_348_DATA 0x00000000 +#define DDRSS0_CTL_349_DATA 0x00000000 +#define DDRSS0_CTL_350_DATA 0x00000000 +#define DDRSS0_CTL_351_DATA 0x00000000 +#define DDRSS0_CTL_352_DATA 0x00000000 +#define DDRSS0_CTL_353_DATA 0x00000000 +#define DDRSS0_CTL_354_DATA 0x00000000 +#define DDRSS0_CTL_355_DATA 0x00000000 +#define DDRSS0_CTL_356_DATA 0x00000000 +#define DDRSS0_CTL_357_DATA 0x00000000 +#define DDRSS0_CTL_358_DATA 0x00000000 +#define DDRSS0_CTL_359_DATA 0x00000000 +#define DDRSS0_CTL_360_DATA 0x000556AA +#define DDRSS0_CTL_361_DATA 0x000AAAAA +#define DDRSS0_CTL_362_DATA 0x000AA955 +#define DDRSS0_CTL_363_DATA 0x00055555 +#define DDRSS0_CTL_364_DATA 0x000B3133 +#define DDRSS0_CTL_365_DATA 0x0004CD33 +#define DDRSS0_CTL_366_DATA 0x0004CECC +#define DDRSS0_CTL_367_DATA 0x000B32CC +#define DDRSS0_CTL_368_DATA 0x00010300 +#define DDRSS0_CTL_369_DATA 0x03000100 +#define DDRSS0_CTL_370_DATA 0x00000000 +#define DDRSS0_CTL_371_DATA 0x00000000 +#define DDRSS0_CTL_372_DATA 0x00000000 +#define DDRSS0_CTL_373_DATA 0x00000000 +#define DDRSS0_CTL_374_DATA 0x00000000 +#define DDRSS0_CTL_375_DATA 0x00000000 +#define DDRSS0_CTL_376_DATA 0x00000000 +#define DDRSS0_CTL_377_DATA 0x00010000 +#define DDRSS0_CTL_378_DATA 0x00000404 +#define DDRSS0_CTL_379_DATA 0x00000000 +#define DDRSS0_CTL_380_DATA 0x00000000 +#define DDRSS0_CTL_381_DATA 0x00000000 +#define DDRSS0_CTL_382_DATA 0x00000000 +#define DDRSS0_CTL_383_DATA 0x00000000 +#define DDRSS0_CTL_384_DATA 0x00000000 +#define DDRSS0_CTL_385_DATA 0x00000000 +#define DDRSS0_CTL_386_DATA 0x00000000 +#define DDRSS0_CTL_387_DATA 0x3A3A1B00 +#define DDRSS0_CTL_388_DATA 0x000A0000 +#define DDRSS0_CTL_389_DATA 0x000000C6 +#define DDRSS0_CTL_390_DATA 0x00000200 +#define DDRSS0_CTL_391_DATA 0x00000200 +#define DDRSS0_CTL_392_DATA 0x00000200 +#define DDRSS0_CTL_393_DATA 0x00000200 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC +#define DDRSS0_CTL_396_DATA 0x00000204 +#define DDRSS0_CTL_397_DATA 0x0000206A +#define DDRSS0_CTL_398_DATA 0x00000200 +#define DDRSS0_CTL_399_DATA 0x00000200 +#define DDRSS0_CTL_400_DATA 0x00000200 +#define DDRSS0_CTL_401_DATA 0x00000200 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A +#define DDRSS0_CTL_406_DATA 0x00000200 +#define DDRSS0_CTL_407_DATA 0x00000200 +#define DDRSS0_CTL_408_DATA 0x00000200 +#define DDRSS0_CTL_409_DATA 0x00000200 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 +#define DDRSS0_CTL_413_DATA 0x03030202 +#define DDRSS0_CTL_414_DATA 0x00000022 +#define DDRSS0_CTL_415_DATA 0x00000000 +#define DDRSS0_CTL_416_DATA 0x00000000 +#define DDRSS0_CTL_417_DATA 0x00001403 +#define DDRSS0_CTL_418_DATA 0x000007D0 +#define DDRSS0_CTL_419_DATA 0x00000000 +#define DDRSS0_CTL_420_DATA 0x00000000 +#define DDRSS0_CTL_421_DATA 0x00030000 +#define DDRSS0_CTL_422_DATA 0x0007001F +#define DDRSS0_CTL_423_DATA 0x001B0033 +#define DDRSS0_CTL_424_DATA 0x001B0033 +#define DDRSS0_CTL_425_DATA 0x00000000 +#define DDRSS0_CTL_426_DATA 0x00000000 +#define DDRSS0_CTL_427_DATA 0x02000000 +#define DDRSS0_CTL_428_DATA 0x01000404 +#define DDRSS0_CTL_429_DATA 0x0B220B22 +#define DDRSS0_CTL_430_DATA 0x00000105 +#define DDRSS0_CTL_431_DATA 0x00010101 +#define DDRSS0_CTL_432_DATA 0x00010101 +#define DDRSS0_CTL_433_DATA 0x00010001 +#define DDRSS0_CTL_434_DATA 0x00000101 +#define DDRSS0_CTL_435_DATA 0x02000201 +#define DDRSS0_CTL_436_DATA 0x02010000 +#define DDRSS0_CTL_437_DATA 0x00000200 +#define DDRSS0_CTL_438_DATA 0x28060000 +#define DDRSS0_CTL_439_DATA 0x00000128 +#define DDRSS0_CTL_440_DATA 0xFFFFFFFF +#define DDRSS0_CTL_441_DATA 0xFFFFFFFF +#define DDRSS0_CTL_442_DATA 0x00000000 +#define DDRSS0_CTL_443_DATA 0x00000000 +#define DDRSS0_CTL_444_DATA 0x00000000 +#define DDRSS0_CTL_445_DATA 0x00000000 +#define DDRSS0_CTL_446_DATA 0x00000000 +#define DDRSS0_CTL_447_DATA 0x00000000 +#define DDRSS0_CTL_448_DATA 0x00000000 +#define DDRSS0_CTL_449_DATA 0x00000000 +#define DDRSS0_CTL_450_DATA 0x00000000 +#define DDRSS0_CTL_451_DATA 0x00000000 +#define DDRSS0_CTL_452_DATA 0x00000000 +#define DDRSS0_CTL_453_DATA 0x00000000 +#define DDRSS0_CTL_454_DATA 0x00000000 +#define DDRSS0_CTL_455_DATA 0x00000000 +#define DDRSS0_CTL_456_DATA 0x00000000 +#define DDRSS0_CTL_457_DATA 0x00000000 +#define DDRSS0_CTL_458_DATA 0x00000000 + +#define DDRSS0_PI_00_DATA 0x00000B00 +#define DDRSS0_PI_01_DATA 0x00000000 +#define DDRSS0_PI_02_DATA 0x00000000 +#define DDRSS0_PI_03_DATA 0x00000000 +#define DDRSS0_PI_04_DATA 0x00000000 +#define DDRSS0_PI_05_DATA 0x00000101 +#define DDRSS0_PI_06_DATA 0x00640000 +#define DDRSS0_PI_07_DATA 0x00000001 +#define DDRSS0_PI_08_DATA 0x00000000 +#define DDRSS0_PI_09_DATA 0x00000000 +#define DDRSS0_PI_10_DATA 0x00000000 +#define DDRSS0_PI_11_DATA 0x00000000 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 +#define DDRSS0_PI_14_DATA 0x0800000F +#define DDRSS0_PI_15_DATA 0x00000103 +#define DDRSS0_PI_16_DATA 0x00000005 +#define DDRSS0_PI_17_DATA 0x00000000 +#define DDRSS0_PI_18_DATA 0x00000000 +#define DDRSS0_PI_19_DATA 0x00000000 +#define DDRSS0_PI_20_DATA 0x00000000 +#define DDRSS0_PI_21_DATA 0x00000000 +#define DDRSS0_PI_22_DATA 0x00000000 +#define DDRSS0_PI_23_DATA 0x00000000 +#define DDRSS0_PI_24_DATA 0x00000000 +#define DDRSS0_PI_25_DATA 0x00000000 +#define DDRSS0_PI_26_DATA 0x00010100 +#define DDRSS0_PI_27_DATA 0x00280A00 +#define DDRSS0_PI_28_DATA 0x00000000 +#define DDRSS0_PI_29_DATA 0x0F000000 +#define DDRSS0_PI_30_DATA 0x00003200 +#define DDRSS0_PI_31_DATA 0x00000000 +#define DDRSS0_PI_32_DATA 0x00000000 +#define DDRSS0_PI_33_DATA 0x01010102 +#define DDRSS0_PI_34_DATA 0x00000000 +#define DDRSS0_PI_35_DATA 0x000000AA +#define DDRSS0_PI_36_DATA 0x00000055 +#define DDRSS0_PI_37_DATA 0x000000B5 +#define DDRSS0_PI_38_DATA 0x0000004A +#define DDRSS0_PI_39_DATA 0x00000056 +#define DDRSS0_PI_40_DATA 0x000000A9 +#define DDRSS0_PI_41_DATA 0x000000A9 +#define DDRSS0_PI_42_DATA 0x000000B5 +#define DDRSS0_PI_43_DATA 0x00000000 +#define DDRSS0_PI_44_DATA 0x00000000 +#define DDRSS0_PI_45_DATA 0x000F0F00 +#define DDRSS0_PI_46_DATA 0x0000001B +#define DDRSS0_PI_47_DATA 0x000007D0 +#define DDRSS0_PI_48_DATA 0x00000300 +#define DDRSS0_PI_49_DATA 0x00000000 +#define DDRSS0_PI_50_DATA 0x00000000 +#define DDRSS0_PI_51_DATA 0x01000000 +#define DDRSS0_PI_52_DATA 0x00010101 +#define DDRSS0_PI_53_DATA 0x00000000 +#define DDRSS0_PI_54_DATA 0x00030000 +#define DDRSS0_PI_55_DATA 0x0F000000 +#define DDRSS0_PI_56_DATA 0x00000017 +#define DDRSS0_PI_57_DATA 0x00000000 +#define DDRSS0_PI_58_DATA 0x00000000 +#define DDRSS0_PI_59_DATA 0x00000000 +#define DDRSS0_PI_60_DATA 0x0A0A140A +#define DDRSS0_PI_61_DATA 0x10020201 +#define DDRSS0_PI_62_DATA 0x00020805 +#define DDRSS0_PI_63_DATA 0x01000404 +#define DDRSS0_PI_64_DATA 0x00000000 +#define DDRSS0_PI_65_DATA 0x00000000 +#define DDRSS0_PI_66_DATA 0x00000100 +#define DDRSS0_PI_67_DATA 0x0002020F +#define DDRSS0_PI_68_DATA 0x00340000 +#define DDRSS0_PI_69_DATA 0x00000000 +#define DDRSS0_PI_70_DATA 0x00000000 +#define DDRSS0_PI_71_DATA 0x0000FFFF +#define DDRSS0_PI_72_DATA 0x01000000 +#define DDRSS0_PI_73_DATA 0x00080000 +#define DDRSS0_PI_74_DATA 0x02000200 +#define DDRSS0_PI_75_DATA 0x01000100 +#define DDRSS0_PI_76_DATA 0x01000000 +#define DDRSS0_PI_77_DATA 0x02000200 +#define DDRSS0_PI_78_DATA 0x00000200 +#define DDRSS0_PI_79_DATA 0x00000000 +#define DDRSS0_PI_80_DATA 0x00000000 +#define DDRSS0_PI_81_DATA 0x00000000 +#define DDRSS0_PI_82_DATA 0x00000000 +#define DDRSS0_PI_83_DATA 0x00000000 +#define DDRSS0_PI_84_DATA 0x00000000 +#define DDRSS0_PI_85_DATA 0x00000000 +#define DDRSS0_PI_86_DATA 0x00000000 +#define DDRSS0_PI_87_DATA 0x00000000 +#define DDRSS0_PI_88_DATA 0x00000000 +#define DDRSS0_PI_89_DATA 0x00000000 +#define DDRSS0_PI_90_DATA 0x00000000 +#define DDRSS0_PI_91_DATA 0x00000400 +#define DDRSS0_PI_92_DATA 0x02010000 +#define DDRSS0_PI_93_DATA 0x00080003 +#define DDRSS0_PI_94_DATA 0x00080000 +#define DDRSS0_PI_95_DATA 0x00000001 +#define DDRSS0_PI_96_DATA 0x00000000 +#define DDRSS0_PI_97_DATA 0x0000AA00 +#define DDRSS0_PI_98_DATA 0x00000000 +#define DDRSS0_PI_99_DATA 0x00000000 +#define DDRSS0_PI_100_DATA 0x00010000 +#define DDRSS0_PI_101_DATA 0x00000000 +#define DDRSS0_PI_102_DATA 0x00000000 +#define DDRSS0_PI_103_DATA 0x00000000 +#define DDRSS0_PI_104_DATA 0x00000000 +#define DDRSS0_PI_105_DATA 0x00000000 +#define DDRSS0_PI_106_DATA 0x00000000 +#define DDRSS0_PI_107_DATA 0x00000000 +#define DDRSS0_PI_108_DATA 0x00000000 +#define DDRSS0_PI_109_DATA 0x00000000 +#define DDRSS0_PI_110_DATA 0x00000000 +#define DDRSS0_PI_111_DATA 0x00000000 +#define DDRSS0_PI_112_DATA 0x00000000 +#define DDRSS0_PI_113_DATA 0x00000000 +#define DDRSS0_PI_114_DATA 0x00000000 +#define DDRSS0_PI_115_DATA 0x00000000 +#define DDRSS0_PI_116_DATA 0x00000000 +#define DDRSS0_PI_117_DATA 0x00000000 +#define DDRSS0_PI_118_DATA 0x00000000 +#define DDRSS0_PI_119_DATA 0x00000000 +#define DDRSS0_PI_120_DATA 0x00000000 +#define DDRSS0_PI_121_DATA 0x00000000 +#define DDRSS0_PI_122_DATA 0x00000000 +#define DDRSS0_PI_123_DATA 0x00000000 +#define DDRSS0_PI_124_DATA 0x00000000 +#define DDRSS0_PI_125_DATA 0x00000008 +#define DDRSS0_PI_126_DATA 0x00000000 +#define DDRSS0_PI_127_DATA 0x00000000 +#define DDRSS0_PI_128_DATA 0x00000000 +#define DDRSS0_PI_129_DATA 0x00000000 +#define DDRSS0_PI_130_DATA 0x00000000 +#define DDRSS0_PI_131_DATA 0x00000000 +#define DDRSS0_PI_132_DATA 0x00000000 +#define DDRSS0_PI_133_DATA 0x00000000 +#define DDRSS0_PI_134_DATA 0x00000002 +#define DDRSS0_PI_135_DATA 0x00000000 +#define DDRSS0_PI_136_DATA 0x00000000 +#define DDRSS0_PI_137_DATA 0x0000000A +#define DDRSS0_PI_138_DATA 0x00000019 +#define DDRSS0_PI_139_DATA 0x00000100 +#define DDRSS0_PI_140_DATA 0x00000000 +#define DDRSS0_PI_141_DATA 0x00000000 +#define DDRSS0_PI_142_DATA 0x00000000 +#define DDRSS0_PI_143_DATA 0x00000000 +#define DDRSS0_PI_144_DATA 0x01000000 +#define DDRSS0_PI_145_DATA 0x00010003 +#define DDRSS0_PI_146_DATA 0x02000101 +#define DDRSS0_PI_147_DATA 0x01030001 +#define DDRSS0_PI_148_DATA 0x00010400 +#define DDRSS0_PI_149_DATA 0x06000105 +#define DDRSS0_PI_150_DATA 0x01070001 +#define DDRSS0_PI_151_DATA 0x00000000 +#define DDRSS0_PI_152_DATA 0x00000000 +#define DDRSS0_PI_153_DATA 0x00000000 +#define DDRSS0_PI_154_DATA 0x00010001 +#define DDRSS0_PI_155_DATA 0x00000000 +#define DDRSS0_PI_156_DATA 0x00000000 +#define DDRSS0_PI_157_DATA 0x00000000 +#define DDRSS0_PI_158_DATA 0x00000000 +#define DDRSS0_PI_159_DATA 0x00000401 +#define DDRSS0_PI_160_DATA 0x00000000 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 +#define DDRSS0_PI_164_DATA 0x00000034 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 +#define DDRSS0_PI_167_DATA 0x02000200 +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 +#define DDRSS0_PI_171_DATA 0x0000032B +#define DDRSS0_PI_172_DATA 0x00001035 +#define DDRSS0_PI_173_DATA 0x0000032B +#define DDRSS0_PI_174_DATA 0x04001035 +#define DDRSS0_PI_175_DATA 0x01010404 +#define DDRSS0_PI_176_DATA 0x00001500 +#define DDRSS0_PI_177_DATA 0x00150015 +#define DDRSS0_PI_178_DATA 0x01000100 +#define DDRSS0_PI_179_DATA 0x00000100 +#define DDRSS0_PI_180_DATA 0x00000000 +#define DDRSS0_PI_181_DATA 0x01010101 +#define DDRSS0_PI_182_DATA 0x00000000 +#define DDRSS0_PI_183_DATA 0x00000000 +#define DDRSS0_PI_184_DATA 0x00000000 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 +#define DDRSS0_PI_187_DATA 0x00040402 +#define DDRSS0_PI_188_DATA 0x000D0035 +#define DDRSS0_PI_189_DATA 0x00218049 +#define DDRSS0_PI_190_DATA 0x00218049 +#define DDRSS0_PI_191_DATA 0x01000101 +#define DDRSS0_PI_192_DATA 0x0004000E +#define DDRSS0_PI_193_DATA 0x00040216 +#define DDRSS0_PI_194_DATA 0x01000216 +#define DDRSS0_PI_195_DATA 0x000F000F +#define DDRSS0_PI_196_DATA 0x02170100 +#define DDRSS0_PI_197_DATA 0x01000217 +#define DDRSS0_PI_198_DATA 0x02170217 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B +#define DDRSS0_PI_201_DATA 0x0A070601 +#define DDRSS0_PI_202_DATA 0x1F130A0D +#define DDRSS0_PI_203_DATA 0x1F130A14 +#define DDRSS0_PI_204_DATA 0x0000C014 +#define DDRSS0_PI_205_DATA 0x00C01000 +#define DDRSS0_PI_206_DATA 0x00C01000 +#define DDRSS0_PI_207_DATA 0x00021000 +#define DDRSS0_PI_208_DATA 0x0024000E +#define DDRSS0_PI_209_DATA 0x00240216 +#define DDRSS0_PI_210_DATA 0x00110216 +#define DDRSS0_PI_211_DATA 0x32000056 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 +#define DDRSS0_PI_214_DATA 0x03013212 +#define DDRSS0_PI_215_DATA 0x00003600 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 +#define DDRSS0_PI_220_DATA 0x0A032001 +#define DDRSS0_PI_221_DATA 0x2C31110A +#define DDRSS0_PI_222_DATA 0x00002918 +#define DDRSS0_PI_223_DATA 0x6000838E +#define DDRSS0_PI_224_DATA 0x1E202008 +#define DDRSS0_PI_225_DATA 0x2C311116 +#define DDRSS0_PI_226_DATA 0x00002918 +#define DDRSS0_PI_227_DATA 0x6000838E +#define DDRSS0_PI_228_DATA 0x1E202008 +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 +#define DDRSS0_PI_235_DATA 0x033B0016 +#define DDRSS0_PI_236_DATA 0x0303033B +#define DDRSS0_PI_237_DATA 0x002AF803 +#define DDRSS0_PI_238_DATA 0x0001ADAF +#define DDRSS0_PI_239_DATA 0x00000005 +#define DDRSS0_PI_240_DATA 0x0000006E +#define DDRSS0_PI_241_DATA 0x00000016 +#define DDRSS0_PI_242_DATA 0x000681C8 +#define DDRSS0_PI_243_DATA 0x0001ADAF +#define DDRSS0_PI_244_DATA 0x00000005 +#define DDRSS0_PI_245_DATA 0x000010A9 +#define DDRSS0_PI_246_DATA 0x0000033B +#define DDRSS0_PI_247_DATA 0x000681C8 +#define DDRSS0_PI_248_DATA 0x0001ADAF +#define DDRSS0_PI_249_DATA 0x00000005 +#define DDRSS0_PI_250_DATA 0x000010A9 +#define DDRSS0_PI_251_DATA 0x0100033B +#define DDRSS0_PI_252_DATA 0x00370040 +#define DDRSS0_PI_253_DATA 0x00010008 +#define DDRSS0_PI_254_DATA 0x08550040 +#define DDRSS0_PI_255_DATA 0x00010040 +#define DDRSS0_PI_256_DATA 0x08550040 +#define DDRSS0_PI_257_DATA 0x00000340 +#define DDRSS0_PI_258_DATA 0x006B006B +#define DDRSS0_PI_259_DATA 0x08040404 +#define DDRSS0_PI_260_DATA 0x00000055 +#define DDRSS0_PI_261_DATA 0x55083C5A +#define DDRSS0_PI_262_DATA 0x5A000000 +#define DDRSS0_PI_263_DATA 0x0055083C +#define DDRSS0_PI_264_DATA 0x3C5A0000 +#define DDRSS0_PI_265_DATA 0x00005508 +#define DDRSS0_PI_266_DATA 0x0C3C5A00 +#define DDRSS0_PI_267_DATA 0x080F0E0D +#define DDRSS0_PI_268_DATA 0x000B0A09 +#define DDRSS0_PI_269_DATA 0x00030201 +#define DDRSS0_PI_270_DATA 0x01000000 +#define DDRSS0_PI_271_DATA 0x04020201 +#define DDRSS0_PI_272_DATA 0x00080804 +#define DDRSS0_PI_273_DATA 0x00000000 +#define DDRSS0_PI_274_DATA 0x00000000 +#define DDRSS0_PI_275_DATA 0x00F30084 +#define DDRSS0_PI_276_DATA 0x00160000 +#define DDRSS0_PI_277_DATA 0x35F33FF4 +#define DDRSS0_PI_278_DATA 0x00160F27 +#define DDRSS0_PI_279_DATA 0x35F33FF4 +#define DDRSS0_PI_280_DATA 0x00160F27 +#define DDRSS0_PI_281_DATA 0x00F30084 +#define DDRSS0_PI_282_DATA 0x00160000 +#define DDRSS0_PI_283_DATA 0x35F33FF4 +#define DDRSS0_PI_284_DATA 0x00160F27 +#define DDRSS0_PI_285_DATA 0x35F33FF4 +#define DDRSS0_PI_286_DATA 0x00160F27 +#define DDRSS0_PI_287_DATA 0x00F30084 +#define DDRSS0_PI_288_DATA 0x00160000 +#define DDRSS0_PI_289_DATA 0x35F33FF4 +#define DDRSS0_PI_290_DATA 0x00160F27 +#define DDRSS0_PI_291_DATA 0x35F33FF4 +#define DDRSS0_PI_292_DATA 0x00160F27 +#define DDRSS0_PI_293_DATA 0x00F30084 +#define DDRSS0_PI_294_DATA 0x00160000 +#define DDRSS0_PI_295_DATA 0x35F33FF4 +#define DDRSS0_PI_296_DATA 0x00160F27 +#define DDRSS0_PI_297_DATA 0x35F33FF4 +#define DDRSS0_PI_298_DATA 0x00160F27 +#define DDRSS0_PI_299_DATA 0x00000000 + +#define DDRSS0_PHY_00_DATA 0x000004F0 +#define DDRSS0_PHY_01_DATA 0x00000000 +#define DDRSS0_PHY_02_DATA 0x00030200 +#define DDRSS0_PHY_03_DATA 0x00000000 +#define DDRSS0_PHY_04_DATA 0x00000000 +#define DDRSS0_PHY_05_DATA 0x01030000 +#define DDRSS0_PHY_06_DATA 0x00010000 +#define DDRSS0_PHY_07_DATA 0x01030004 +#define DDRSS0_PHY_08_DATA 0x01000000 +#define DDRSS0_PHY_09_DATA 0x00000000 +#define DDRSS0_PHY_10_DATA 0x00000000 +#define DDRSS0_PHY_11_DATA 0x01000001 +#define DDRSS0_PHY_12_DATA 0x00000200 +#define DDRSS0_PHY_13_DATA 0x000800C0 +#define DDRSS0_PHY_14_DATA 0x060100CC +#define DDRSS0_PHY_15_DATA 0x00030066 +#define DDRSS0_PHY_16_DATA 0x00000000 +#define DDRSS0_PHY_17_DATA 0x00000301 +#define DDRSS0_PHY_18_DATA 0x0000AAAA +#define DDRSS0_PHY_19_DATA 0x00005555 +#define DDRSS0_PHY_20_DATA 0x0000B5B5 +#define DDRSS0_PHY_21_DATA 0x00004A4A +#define DDRSS0_PHY_22_DATA 0x00005656 +#define DDRSS0_PHY_23_DATA 0x0000A9A9 +#define DDRSS0_PHY_24_DATA 0x0000A9A9 +#define DDRSS0_PHY_25_DATA 0x0000B5B5 +#define DDRSS0_PHY_26_DATA 0x00000000 +#define DDRSS0_PHY_27_DATA 0x00000000 +#define DDRSS0_PHY_28_DATA 0x2A000000 +#define DDRSS0_PHY_29_DATA 0x00000808 +#define DDRSS0_PHY_30_DATA 0x0F000000 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002006 +#define DDRSS0_PHY_34_DATA 0x00000000 +#define DDRSS0_PHY_35_DATA 0x00000000 +#define DDRSS0_PHY_36_DATA 0x55555555 +#define DDRSS0_PHY_37_DATA 0xAAAAAAAA +#define DDRSS0_PHY_38_DATA 0x55555555 +#define DDRSS0_PHY_39_DATA 0xAAAAAAAA +#define DDRSS0_PHY_40_DATA 0x00005555 +#define DDRSS0_PHY_41_DATA 0x01000100 +#define DDRSS0_PHY_42_DATA 0x00800180 +#define DDRSS0_PHY_43_DATA 0x00000001 +#define DDRSS0_PHY_44_DATA 0x00000000 +#define DDRSS0_PHY_45_DATA 0x00000000 +#define DDRSS0_PHY_46_DATA 0x00000000 +#define DDRSS0_PHY_47_DATA 0x00000000 +#define DDRSS0_PHY_48_DATA 0x00000000 +#define DDRSS0_PHY_49_DATA 0x00000000 +#define DDRSS0_PHY_50_DATA 0x00000000 +#define DDRSS0_PHY_51_DATA 0x00000000 +#define DDRSS0_PHY_52_DATA 0x00000000 +#define DDRSS0_PHY_53_DATA 0x00000000 +#define DDRSS0_PHY_54_DATA 0x00000000 +#define DDRSS0_PHY_55_DATA 0x00000000 +#define DDRSS0_PHY_56_DATA 0x00000000 +#define DDRSS0_PHY_57_DATA 0x00000000 +#define DDRSS0_PHY_58_DATA 0x00000000 +#define DDRSS0_PHY_59_DATA 0x00000000 +#define DDRSS0_PHY_60_DATA 0x00000000 +#define DDRSS0_PHY_61_DATA 0x00000000 +#define DDRSS0_PHY_62_DATA 0x00000000 +#define DDRSS0_PHY_63_DATA 0x00000000 +#define DDRSS0_PHY_64_DATA 0x00000000 +#define DDRSS0_PHY_65_DATA 0x00000000 +#define DDRSS0_PHY_66_DATA 0x00000104 +#define DDRSS0_PHY_67_DATA 0x00000120 +#define DDRSS0_PHY_68_DATA 0x00000000 +#define DDRSS0_PHY_69_DATA 0x00000000 +#define DDRSS0_PHY_70_DATA 0x00000000 +#define DDRSS0_PHY_71_DATA 0x00000000 +#define DDRSS0_PHY_72_DATA 0x00000000 +#define DDRSS0_PHY_73_DATA 0x00000000 +#define DDRSS0_PHY_74_DATA 0x00000000 +#define DDRSS0_PHY_75_DATA 0x00000001 +#define DDRSS0_PHY_76_DATA 0x07FF0000 +#define DDRSS0_PHY_77_DATA 0x0080081F +#define DDRSS0_PHY_78_DATA 0x00081020 +#define DDRSS0_PHY_79_DATA 0x04010000 +#define DDRSS0_PHY_80_DATA 0x00000000 +#define DDRSS0_PHY_81_DATA 0x00000000 +#define DDRSS0_PHY_82_DATA 0x00000000 +#define DDRSS0_PHY_83_DATA 0x00000100 +#define DDRSS0_PHY_84_DATA 0x01CC0C01 +#define DDRSS0_PHY_85_DATA 0x1003CC0C +#define DDRSS0_PHY_86_DATA 0x20000140 +#define DDRSS0_PHY_87_DATA 0x07FF0200 +#define DDRSS0_PHY_88_DATA 0x0000DD01 +#define DDRSS0_PHY_89_DATA 0x10100303 +#define DDRSS0_PHY_90_DATA 0x10101010 +#define DDRSS0_PHY_91_DATA 0x10101010 +#define DDRSS0_PHY_92_DATA 0x00021010 +#define DDRSS0_PHY_93_DATA 0x00100010 +#define DDRSS0_PHY_94_DATA 0x00100010 +#define DDRSS0_PHY_95_DATA 0x00100010 +#define DDRSS0_PHY_96_DATA 0x00100010 +#define DDRSS0_PHY_97_DATA 0x00050010 +#define DDRSS0_PHY_98_DATA 0x51517041 +#define DDRSS0_PHY_99_DATA 0x31C06001 +#define DDRSS0_PHY_100_DATA 0x07AB01AB +#define DDRSS0_PHY_101_DATA 0x00C0C001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 +#define DDRSS0_PHY_103_DATA 0x10001000 +#define DDRSS0_PHY_104_DATA 0x0C083E42 +#define DDRSS0_PHY_105_DATA 0x0F0C3701 +#define DDRSS0_PHY_106_DATA 0x01000140 +#define DDRSS0_PHY_107_DATA 0x0C000420 +#define DDRSS0_PHY_108_DATA 0x00000198 +#define DDRSS0_PHY_109_DATA 0x0A0000D0 +#define DDRSS0_PHY_110_DATA 0x00030200 +#define DDRSS0_PHY_111_DATA 0x02800000 +#define DDRSS0_PHY_112_DATA 0x80800000 +#define DDRSS0_PHY_113_DATA 0x000E2010 +#define DDRSS0_PHY_114_DATA 0x76543210 +#define DDRSS0_PHY_115_DATA 0x00000008 +#define DDRSS0_PHY_116_DATA 0x02800280 +#define DDRSS0_PHY_117_DATA 0x02800280 +#define DDRSS0_PHY_118_DATA 0x02800280 +#define DDRSS0_PHY_119_DATA 0x02800280 +#define DDRSS0_PHY_120_DATA 0x00000280 +#define DDRSS0_PHY_121_DATA 0x0000A000 +#define DDRSS0_PHY_122_DATA 0x00A000A0 +#define DDRSS0_PHY_123_DATA 0x00A000A0 +#define DDRSS0_PHY_124_DATA 0x00A000A0 +#define DDRSS0_PHY_125_DATA 0x00A000A0 +#define DDRSS0_PHY_126_DATA 0x00A000A0 +#define DDRSS0_PHY_127_DATA 0x00A000A0 +#define DDRSS0_PHY_128_DATA 0x00A000A0 +#define DDRSS0_PHY_129_DATA 0x00A000A0 +#define DDRSS0_PHY_130_DATA 0x01C200A0 +#define DDRSS0_PHY_131_DATA 0x01A00005 +#define DDRSS0_PHY_132_DATA 0x00000000 +#define DDRSS0_PHY_133_DATA 0x00000000 +#define DDRSS0_PHY_134_DATA 0x00080200 +#define DDRSS0_PHY_135_DATA 0x00000000 +#define DDRSS0_PHY_136_DATA 0x20202000 +#define DDRSS0_PHY_137_DATA 0x20202020 +#define DDRSS0_PHY_138_DATA 0xF0F02020 +#define DDRSS0_PHY_139_DATA 0x00000000 +#define DDRSS0_PHY_140_DATA 0x00000000 +#define DDRSS0_PHY_141_DATA 0x00000000 +#define DDRSS0_PHY_142_DATA 0x00000000 +#define DDRSS0_PHY_143_DATA 0x00000000 +#define DDRSS0_PHY_144_DATA 0x00000000 +#define DDRSS0_PHY_145_DATA 0x00000000 +#define DDRSS0_PHY_146_DATA 0x00000000 +#define DDRSS0_PHY_147_DATA 0x00000000 +#define DDRSS0_PHY_148_DATA 0x00000000 +#define DDRSS0_PHY_149_DATA 0x00000000 +#define DDRSS0_PHY_150_DATA 0x00000000 +#define DDRSS0_PHY_151_DATA 0x00000000 +#define DDRSS0_PHY_152_DATA 0x00000000 +#define DDRSS0_PHY_153_DATA 0x00000000 +#define DDRSS0_PHY_154_DATA 0x00000000 +#define DDRSS0_PHY_155_DATA 0x00000000 +#define DDRSS0_PHY_156_DATA 0x00000000 +#define DDRSS0_PHY_157_DATA 0x00000000 +#define DDRSS0_PHY_158_DATA 0x00000000 +#define DDRSS0_PHY_159_DATA 0x00000000 +#define DDRSS0_PHY_160_DATA 0x00000000 +#define DDRSS0_PHY_161_DATA 0x00000000 +#define DDRSS0_PHY_162_DATA 0x00000000 +#define DDRSS0_PHY_163_DATA 0x00000000 +#define DDRSS0_PHY_164_DATA 0x00000000 +#define DDRSS0_PHY_165_DATA 0x00000000 +#define DDRSS0_PHY_166_DATA 0x00000000 +#define DDRSS0_PHY_167_DATA 0x00000000 +#define DDRSS0_PHY_168_DATA 0x00000000 +#define DDRSS0_PHY_169_DATA 0x00000000 +#define DDRSS0_PHY_170_DATA 0x00000000 +#define DDRSS0_PHY_171_DATA 0x00000000 +#define DDRSS0_PHY_172_DATA 0x00000000 +#define DDRSS0_PHY_173_DATA 0x00000000 +#define DDRSS0_PHY_174_DATA 0x00000000 +#define DDRSS0_PHY_175_DATA 0x00000000 +#define DDRSS0_PHY_176_DATA 0x00000000 +#define DDRSS0_PHY_177_DATA 0x00000000 +#define DDRSS0_PHY_178_DATA 0x00000000 +#define DDRSS0_PHY_179_DATA 0x00000000 +#define DDRSS0_PHY_180_DATA 0x00000000 +#define DDRSS0_PHY_181_DATA 0x00000000 +#define DDRSS0_PHY_182_DATA 0x00000000 +#define DDRSS0_PHY_183_DATA 0x00000000 +#define DDRSS0_PHY_184_DATA 0x00000000 +#define DDRSS0_PHY_185_DATA 0x00000000 +#define DDRSS0_PHY_186_DATA 0x00000000 +#define DDRSS0_PHY_187_DATA 0x00000000 +#define DDRSS0_PHY_188_DATA 0x00000000 +#define DDRSS0_PHY_189_DATA 0x00000000 +#define DDRSS0_PHY_190_DATA 0x00000000 +#define DDRSS0_PHY_191_DATA 0x00000000 +#define DDRSS0_PHY_192_DATA 0x00000000 +#define DDRSS0_PHY_193_DATA 0x00000000 +#define DDRSS0_PHY_194_DATA 0x00000000 +#define DDRSS0_PHY_195_DATA 0x00000000 +#define DDRSS0_PHY_196_DATA 0x00000000 +#define DDRSS0_PHY_197_DATA 0x00000000 +#define DDRSS0_PHY_198_DATA 0x00000000 +#define DDRSS0_PHY_199_DATA 0x00000000 +#define DDRSS0_PHY_200_DATA 0x00000000 +#define DDRSS0_PHY_201_DATA 0x00000000 +#define DDRSS0_PHY_202_DATA 0x00000000 +#define DDRSS0_PHY_203_DATA 0x00000000 +#define DDRSS0_PHY_204_DATA 0x00000000 +#define DDRSS0_PHY_205_DATA 0x00000000 +#define DDRSS0_PHY_206_DATA 0x00000000 +#define DDRSS0_PHY_207_DATA 0x00000000 +#define DDRSS0_PHY_208_DATA 0x00000000 +#define DDRSS0_PHY_209_DATA 0x00000000 +#define DDRSS0_PHY_210_DATA 0x00000000 +#define DDRSS0_PHY_211_DATA 0x00000000 +#define DDRSS0_PHY_212_DATA 0x00000000 +#define DDRSS0_PHY_213_DATA 0x00000000 +#define DDRSS0_PHY_214_DATA 0x00000000 +#define DDRSS0_PHY_215_DATA 0x00000000 +#define DDRSS0_PHY_216_DATA 0x00000000 +#define DDRSS0_PHY_217_DATA 0x00000000 +#define DDRSS0_PHY_218_DATA 0x00000000 +#define DDRSS0_PHY_219_DATA 0x00000000 +#define DDRSS0_PHY_220_DATA 0x00000000 +#define DDRSS0_PHY_221_DATA 0x00000000 +#define DDRSS0_PHY_222_DATA 0x00000000 +#define DDRSS0_PHY_223_DATA 0x00000000 +#define DDRSS0_PHY_224_DATA 0x00000000 +#define DDRSS0_PHY_225_DATA 0x00000000 +#define DDRSS0_PHY_226_DATA 0x00000000 +#define DDRSS0_PHY_227_DATA 0x00000000 +#define DDRSS0_PHY_228_DATA 0x00000000 +#define DDRSS0_PHY_229_DATA 0x00000000 +#define DDRSS0_PHY_230_DATA 0x00000000 +#define DDRSS0_PHY_231_DATA 0x00000000 +#define DDRSS0_PHY_232_DATA 0x00000000 +#define DDRSS0_PHY_233_DATA 0x00000000 +#define DDRSS0_PHY_234_DATA 0x00000000 +#define DDRSS0_PHY_235_DATA 0x00000000 +#define DDRSS0_PHY_236_DATA 0x00000000 +#define DDRSS0_PHY_237_DATA 0x00000000 +#define DDRSS0_PHY_238_DATA 0x00000000 +#define DDRSS0_PHY_239_DATA 0x00000000 +#define DDRSS0_PHY_240_DATA 0x00000000 +#define DDRSS0_PHY_241_DATA 0x00000000 +#define DDRSS0_PHY_242_DATA 0x00000000 +#define DDRSS0_PHY_243_DATA 0x00000000 +#define DDRSS0_PHY_244_DATA 0x00000000 +#define DDRSS0_PHY_245_DATA 0x00000000 +#define DDRSS0_PHY_246_DATA 0x00000000 +#define DDRSS0_PHY_247_DATA 0x00000000 +#define DDRSS0_PHY_248_DATA 0x00000000 +#define DDRSS0_PHY_249_DATA 0x00000000 +#define DDRSS0_PHY_250_DATA 0x00000000 +#define DDRSS0_PHY_251_DATA 0x00000000 +#define DDRSS0_PHY_252_DATA 0x00000000 +#define DDRSS0_PHY_253_DATA 0x00000000 +#define DDRSS0_PHY_254_DATA 0x00000000 +#define DDRSS0_PHY_255_DATA 0x00000000 +#define DDRSS0_PHY_256_DATA 0x000004F0 +#define DDRSS0_PHY_257_DATA 0x00000000 +#define DDRSS0_PHY_258_DATA 0x00030200 +#define DDRSS0_PHY_259_DATA 0x00000000 +#define DDRSS0_PHY_260_DATA 0x00000000 +#define DDRSS0_PHY_261_DATA 0x01030000 +#define DDRSS0_PHY_262_DATA 0x00010000 +#define DDRSS0_PHY_263_DATA 0x01030004 +#define DDRSS0_PHY_264_DATA 0x01000000 +#define DDRSS0_PHY_265_DATA 0x00000000 +#define DDRSS0_PHY_266_DATA 0x00000000 +#define DDRSS0_PHY_267_DATA 0x01000001 +#define DDRSS0_PHY_268_DATA 0x00000200 +#define DDRSS0_PHY_269_DATA 0x000800C0 +#define DDRSS0_PHY_270_DATA 0x060100CC +#define DDRSS0_PHY_271_DATA 0x00030066 +#define DDRSS0_PHY_272_DATA 0x00000000 +#define DDRSS0_PHY_273_DATA 0x00000301 +#define DDRSS0_PHY_274_DATA 0x0000AAAA +#define DDRSS0_PHY_275_DATA 0x00005555 +#define DDRSS0_PHY_276_DATA 0x0000B5B5 +#define DDRSS0_PHY_277_DATA 0x00004A4A +#define DDRSS0_PHY_278_DATA 0x00005656 +#define DDRSS0_PHY_279_DATA 0x0000A9A9 +#define DDRSS0_PHY_280_DATA 0x0000A9A9 +#define DDRSS0_PHY_281_DATA 0x0000B5B5 +#define DDRSS0_PHY_282_DATA 0x00000000 +#define DDRSS0_PHY_283_DATA 0x00000000 +#define DDRSS0_PHY_284_DATA 0x2A000000 +#define DDRSS0_PHY_285_DATA 0x00000808 +#define DDRSS0_PHY_286_DATA 0x0F000000 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002006 +#define DDRSS0_PHY_290_DATA 0x00000000 +#define DDRSS0_PHY_291_DATA 0x00000000 +#define DDRSS0_PHY_292_DATA 0x55555555 +#define DDRSS0_PHY_293_DATA 0xAAAAAAAA +#define DDRSS0_PHY_294_DATA 0x55555555 +#define DDRSS0_PHY_295_DATA 0xAAAAAAAA +#define DDRSS0_PHY_296_DATA 0x00005555 +#define DDRSS0_PHY_297_DATA 0x01000100 +#define DDRSS0_PHY_298_DATA 0x00800180 +#define DDRSS0_PHY_299_DATA 0x00000000 +#define DDRSS0_PHY_300_DATA 0x00000000 +#define DDRSS0_PHY_301_DATA 0x00000000 +#define DDRSS0_PHY_302_DATA 0x00000000 +#define DDRSS0_PHY_303_DATA 0x00000000 +#define DDRSS0_PHY_304_DATA 0x00000000 +#define DDRSS0_PHY_305_DATA 0x00000000 +#define DDRSS0_PHY_306_DATA 0x00000000 +#define DDRSS0_PHY_307_DATA 0x00000000 +#define DDRSS0_PHY_308_DATA 0x00000000 +#define DDRSS0_PHY_309_DATA 0x00000000 +#define DDRSS0_PHY_310_DATA 0x00000000 +#define DDRSS0_PHY_311_DATA 0x00000000 +#define DDRSS0_PHY_312_DATA 0x00000000 +#define DDRSS0_PHY_313_DATA 0x00000000 +#define DDRSS0_PHY_314_DATA 0x00000000 +#define DDRSS0_PHY_315_DATA 0x00000000 +#define DDRSS0_PHY_316_DATA 0x00000000 +#define DDRSS0_PHY_317_DATA 0x00000000 +#define DDRSS0_PHY_318_DATA 0x00000000 +#define DDRSS0_PHY_319_DATA 0x00000000 +#define DDRSS0_PHY_320_DATA 0x00000000 +#define DDRSS0_PHY_321_DATA 0x00000000 +#define DDRSS0_PHY_322_DATA 0x00000104 +#define DDRSS0_PHY_323_DATA 0x00000120 +#define DDRSS0_PHY_324_DATA 0x00000000 +#define DDRSS0_PHY_325_DATA 0x00000000 +#define DDRSS0_PHY_326_DATA 0x00000000 +#define DDRSS0_PHY_327_DATA 0x00000000 +#define DDRSS0_PHY_328_DATA 0x00000000 +#define DDRSS0_PHY_329_DATA 0x00000000 +#define DDRSS0_PHY_330_DATA 0x00000000 +#define DDRSS0_PHY_331_DATA 0x00000001 +#define DDRSS0_PHY_332_DATA 0x07FF0000 +#define DDRSS0_PHY_333_DATA 0x0080081F +#define DDRSS0_PHY_334_DATA 0x00081020 +#define DDRSS0_PHY_335_DATA 0x04010000 +#define DDRSS0_PHY_336_DATA 0x00000000 +#define DDRSS0_PHY_337_DATA 0x00000000 +#define DDRSS0_PHY_338_DATA 0x00000000 +#define DDRSS0_PHY_339_DATA 0x00000100 +#define DDRSS0_PHY_340_DATA 0x01CC0C01 +#define DDRSS0_PHY_341_DATA 0x1003CC0C +#define DDRSS0_PHY_342_DATA 0x20000140 +#define DDRSS0_PHY_343_DATA 0x07FF0200 +#define DDRSS0_PHY_344_DATA 0x0000DD01 +#define DDRSS0_PHY_345_DATA 0x10100303 +#define DDRSS0_PHY_346_DATA 0x10101010 +#define DDRSS0_PHY_347_DATA 0x10101010 +#define DDRSS0_PHY_348_DATA 0x00021010 +#define DDRSS0_PHY_349_DATA 0x00100010 +#define DDRSS0_PHY_350_DATA 0x00100010 +#define DDRSS0_PHY_351_DATA 0x00100010 +#define DDRSS0_PHY_352_DATA 0x00100010 +#define DDRSS0_PHY_353_DATA 0x00050010 +#define DDRSS0_PHY_354_DATA 0x51517041 +#define DDRSS0_PHY_355_DATA 0x31C06001 +#define DDRSS0_PHY_356_DATA 0x07AB01AB +#define DDRSS0_PHY_357_DATA 0x00C0C001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 +#define DDRSS0_PHY_359_DATA 0x10001000 +#define DDRSS0_PHY_360_DATA 0x0C083E42 +#define DDRSS0_PHY_361_DATA 0x0F0C3701 +#define DDRSS0_PHY_362_DATA 0x01000140 +#define DDRSS0_PHY_363_DATA 0x0C000420 +#define DDRSS0_PHY_364_DATA 0x00000198 +#define DDRSS0_PHY_365_DATA 0x0A0000D0 +#define DDRSS0_PHY_366_DATA 0x00030200 +#define DDRSS0_PHY_367_DATA 0x02800000 +#define DDRSS0_PHY_368_DATA 0x80800000 +#define DDRSS0_PHY_369_DATA 0x000E2010 +#define DDRSS0_PHY_370_DATA 0x76543210 +#define DDRSS0_PHY_371_DATA 0x00000008 +#define DDRSS0_PHY_372_DATA 0x02800280 +#define DDRSS0_PHY_373_DATA 0x02800280 +#define DDRSS0_PHY_374_DATA 0x02800280 +#define DDRSS0_PHY_375_DATA 0x02800280 +#define DDRSS0_PHY_376_DATA 0x00000280 +#define DDRSS0_PHY_377_DATA 0x0000A000 +#define DDRSS0_PHY_378_DATA 0x00A000A0 +#define DDRSS0_PHY_379_DATA 0x00A000A0 +#define DDRSS0_PHY_380_DATA 0x00A000A0 +#define DDRSS0_PHY_381_DATA 0x00A000A0 +#define DDRSS0_PHY_382_DATA 0x00A000A0 +#define DDRSS0_PHY_383_DATA 0x00A000A0 +#define DDRSS0_PHY_384_DATA 0x00A000A0 +#define DDRSS0_PHY_385_DATA 0x00A000A0 +#define DDRSS0_PHY_386_DATA 0x01C200A0 +#define DDRSS0_PHY_387_DATA 0x01A00005 +#define DDRSS0_PHY_388_DATA 0x00000000 +#define DDRSS0_PHY_389_DATA 0x00000000 +#define DDRSS0_PHY_390_DATA 0x00080200 +#define DDRSS0_PHY_391_DATA 0x00000000 +#define DDRSS0_PHY_392_DATA 0x20202000 +#define DDRSS0_PHY_393_DATA 0x20202020 +#define DDRSS0_PHY_394_DATA 0xF0F02020 +#define DDRSS0_PHY_395_DATA 0x00000000 +#define DDRSS0_PHY_396_DATA 0x00000000 +#define DDRSS0_PHY_397_DATA 0x00000000 +#define DDRSS0_PHY_398_DATA 0x00000000 +#define DDRSS0_PHY_399_DATA 0x00000000 +#define DDRSS0_PHY_400_DATA 0x00000000 +#define DDRSS0_PHY_401_DATA 0x00000000 +#define DDRSS0_PHY_402_DATA 0x00000000 +#define DDRSS0_PHY_403_DATA 0x00000000 +#define DDRSS0_PHY_404_DATA 0x00000000 +#define DDRSS0_PHY_405_DATA 0x00000000 +#define DDRSS0_PHY_406_DATA 0x00000000 +#define DDRSS0_PHY_407_DATA 0x00000000 +#define DDRSS0_PHY_408_DATA 0x00000000 +#define DDRSS0_PHY_409_DATA 0x00000000 +#define DDRSS0_PHY_410_DATA 0x00000000 +#define DDRSS0_PHY_411_DATA 0x00000000 +#define DDRSS0_PHY_412_DATA 0x00000000 +#define DDRSS0_PHY_413_DATA 0x00000000 +#define DDRSS0_PHY_414_DATA 0x00000000 +#define DDRSS0_PHY_415_DATA 0x00000000 +#define DDRSS0_PHY_416_DATA 0x00000000 +#define DDRSS0_PHY_417_DATA 0x00000000 +#define DDRSS0_PHY_418_DATA 0x00000000 +#define DDRSS0_PHY_419_DATA 0x00000000 +#define DDRSS0_PHY_420_DATA 0x00000000 +#define DDRSS0_PHY_421_DATA 0x00000000 +#define DDRSS0_PHY_422_DATA 0x00000000 +#define DDRSS0_PHY_423_DATA 0x00000000 +#define DDRSS0_PHY_424_DATA 0x00000000 +#define DDRSS0_PHY_425_DATA 0x00000000 +#define DDRSS0_PHY_426_DATA 0x00000000 +#define DDRSS0_PHY_427_DATA 0x00000000 +#define DDRSS0_PHY_428_DATA 0x00000000 +#define DDRSS0_PHY_429_DATA 0x00000000 +#define DDRSS0_PHY_430_DATA 0x00000000 +#define DDRSS0_PHY_431_DATA 0x00000000 +#define DDRSS0_PHY_432_DATA 0x00000000 +#define DDRSS0_PHY_433_DATA 0x00000000 +#define DDRSS0_PHY_434_DATA 0x00000000 +#define DDRSS0_PHY_435_DATA 0x00000000 +#define DDRSS0_PHY_436_DATA 0x00000000 +#define DDRSS0_PHY_437_DATA 0x00000000 +#define DDRSS0_PHY_438_DATA 0x00000000 +#define DDRSS0_PHY_439_DATA 0x00000000 +#define DDRSS0_PHY_440_DATA 0x00000000 +#define DDRSS0_PHY_441_DATA 0x00000000 +#define DDRSS0_PHY_442_DATA 0x00000000 +#define DDRSS0_PHY_443_DATA 0x00000000 +#define DDRSS0_PHY_444_DATA 0x00000000 +#define DDRSS0_PHY_445_DATA 0x00000000 +#define DDRSS0_PHY_446_DATA 0x00000000 +#define DDRSS0_PHY_447_DATA 0x00000000 +#define DDRSS0_PHY_448_DATA 0x00000000 +#define DDRSS0_PHY_449_DATA 0x00000000 +#define DDRSS0_PHY_450_DATA 0x00000000 +#define DDRSS0_PHY_451_DATA 0x00000000 +#define DDRSS0_PHY_452_DATA 0x00000000 +#define DDRSS0_PHY_453_DATA 0x00000000 +#define DDRSS0_PHY_454_DATA 0x00000000 +#define DDRSS0_PHY_455_DATA 0x00000000 +#define DDRSS0_PHY_456_DATA 0x00000000 +#define DDRSS0_PHY_457_DATA 0x00000000 +#define DDRSS0_PHY_458_DATA 0x00000000 +#define DDRSS0_PHY_459_DATA 0x00000000 +#define DDRSS0_PHY_460_DATA 0x00000000 +#define DDRSS0_PHY_461_DATA 0x00000000 +#define DDRSS0_PHY_462_DATA 0x00000000 +#define DDRSS0_PHY_463_DATA 0x00000000 +#define DDRSS0_PHY_464_DATA 0x00000000 +#define DDRSS0_PHY_465_DATA 0x00000000 +#define DDRSS0_PHY_466_DATA 0x00000000 +#define DDRSS0_PHY_467_DATA 0x00000000 +#define DDRSS0_PHY_468_DATA 0x00000000 +#define DDRSS0_PHY_469_DATA 0x00000000 +#define DDRSS0_PHY_470_DATA 0x00000000 +#define DDRSS0_PHY_471_DATA 0x00000000 +#define DDRSS0_PHY_472_DATA 0x00000000 +#define DDRSS0_PHY_473_DATA 0x00000000 +#define DDRSS0_PHY_474_DATA 0x00000000 +#define DDRSS0_PHY_475_DATA 0x00000000 +#define DDRSS0_PHY_476_DATA 0x00000000 +#define DDRSS0_PHY_477_DATA 0x00000000 +#define DDRSS0_PHY_478_DATA 0x00000000 +#define DDRSS0_PHY_479_DATA 0x00000000 +#define DDRSS0_PHY_480_DATA 0x00000000 +#define DDRSS0_PHY_481_DATA 0x00000000 +#define DDRSS0_PHY_482_DATA 0x00000000 +#define DDRSS0_PHY_483_DATA 0x00000000 +#define DDRSS0_PHY_484_DATA 0x00000000 +#define DDRSS0_PHY_485_DATA 0x00000000 +#define DDRSS0_PHY_486_DATA 0x00000000 +#define DDRSS0_PHY_487_DATA 0x00000000 +#define DDRSS0_PHY_488_DATA 0x00000000 +#define DDRSS0_PHY_489_DATA 0x00000000 +#define DDRSS0_PHY_490_DATA 0x00000000 +#define DDRSS0_PHY_491_DATA 0x00000000 +#define DDRSS0_PHY_492_DATA 0x00000000 +#define DDRSS0_PHY_493_DATA 0x00000000 +#define DDRSS0_PHY_494_DATA 0x00000000 +#define DDRSS0_PHY_495_DATA 0x00000000 +#define DDRSS0_PHY_496_DATA 0x00000000 +#define DDRSS0_PHY_497_DATA 0x00000000 +#define DDRSS0_PHY_498_DATA 0x00000000 +#define DDRSS0_PHY_499_DATA 0x00000000 +#define DDRSS0_PHY_500_DATA 0x00000000 +#define DDRSS0_PHY_501_DATA 0x00000000 +#define DDRSS0_PHY_502_DATA 0x00000000 +#define DDRSS0_PHY_503_DATA 0x00000000 +#define DDRSS0_PHY_504_DATA 0x00000000 +#define DDRSS0_PHY_505_DATA 0x00000000 +#define DDRSS0_PHY_506_DATA 0x00000000 +#define DDRSS0_PHY_507_DATA 0x00000000 +#define DDRSS0_PHY_508_DATA 0x00000000 +#define DDRSS0_PHY_509_DATA 0x00000000 +#define DDRSS0_PHY_510_DATA 0x00000000 +#define DDRSS0_PHY_511_DATA 0x00000000 +#define DDRSS0_PHY_512_DATA 0x000004F0 +#define DDRSS0_PHY_513_DATA 0x00000000 +#define DDRSS0_PHY_514_DATA 0x00030200 +#define DDRSS0_PHY_515_DATA 0x00000000 +#define DDRSS0_PHY_516_DATA 0x00000000 +#define DDRSS0_PHY_517_DATA 0x01030000 +#define DDRSS0_PHY_518_DATA 0x00010000 +#define DDRSS0_PHY_519_DATA 0x01030004 +#define DDRSS0_PHY_520_DATA 0x01000000 +#define DDRSS0_PHY_521_DATA 0x00000000 +#define DDRSS0_PHY_522_DATA 0x00000000 +#define DDRSS0_PHY_523_DATA 0x01000001 +#define DDRSS0_PHY_524_DATA 0x00000200 +#define DDRSS0_PHY_525_DATA 0x000800C0 +#define DDRSS0_PHY_526_DATA 0x060100CC +#define DDRSS0_PHY_527_DATA 0x00030066 +#define DDRSS0_PHY_528_DATA 0x00000000 +#define DDRSS0_PHY_529_DATA 0x00000301 +#define DDRSS0_PHY_530_DATA 0x0000AAAA +#define DDRSS0_PHY_531_DATA 0x00005555 +#define DDRSS0_PHY_532_DATA 0x0000B5B5 +#define DDRSS0_PHY_533_DATA 0x00004A4A +#define DDRSS0_PHY_534_DATA 0x00005656 +#define DDRSS0_PHY_535_DATA 0x0000A9A9 +#define DDRSS0_PHY_536_DATA 0x0000A9A9 +#define DDRSS0_PHY_537_DATA 0x0000B5B5 +#define DDRSS0_PHY_538_DATA 0x00000000 +#define DDRSS0_PHY_539_DATA 0x00000000 +#define DDRSS0_PHY_540_DATA 0x2A000000 +#define DDRSS0_PHY_541_DATA 0x00000808 +#define DDRSS0_PHY_542_DATA 0x0F000000 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002006 +#define DDRSS0_PHY_546_DATA 0x00000000 +#define DDRSS0_PHY_547_DATA 0x00000000 +#define DDRSS0_PHY_548_DATA 0x55555555 +#define DDRSS0_PHY_549_DATA 0xAAAAAAAA +#define DDRSS0_PHY_550_DATA 0x55555555 +#define DDRSS0_PHY_551_DATA 0xAAAAAAAA +#define DDRSS0_PHY_552_DATA 0x00005555 +#define DDRSS0_PHY_553_DATA 0x01000100 +#define DDRSS0_PHY_554_DATA 0x00800180 +#define DDRSS0_PHY_555_DATA 0x00000001 +#define DDRSS0_PHY_556_DATA 0x00000000 +#define DDRSS0_PHY_557_DATA 0x00000000 +#define DDRSS0_PHY_558_DATA 0x00000000 +#define DDRSS0_PHY_559_DATA 0x00000000 +#define DDRSS0_PHY_560_DATA 0x00000000 +#define DDRSS0_PHY_561_DATA 0x00000000 +#define DDRSS0_PHY_562_DATA 0x00000000 +#define DDRSS0_PHY_563_DATA 0x00000000 +#define DDRSS0_PHY_564_DATA 0x00000000 +#define DDRSS0_PHY_565_DATA 0x00000000 +#define DDRSS0_PHY_566_DATA 0x00000000 +#define DDRSS0_PHY_567_DATA 0x00000000 +#define DDRSS0_PHY_568_DATA 0x00000000 +#define DDRSS0_PHY_569_DATA 0x00000000 +#define DDRSS0_PHY_570_DATA 0x00000000 +#define DDRSS0_PHY_571_DATA 0x00000000 +#define DDRSS0_PHY_572_DATA 0x00000000 +#define DDRSS0_PHY_573_DATA 0x00000000 +#define DDRSS0_PHY_574_DATA 0x00000000 +#define DDRSS0_PHY_575_DATA 0x00000000 +#define DDRSS0_PHY_576_DATA 0x00000000 +#define DDRSS0_PHY_577_DATA 0x00000000 +#define DDRSS0_PHY_578_DATA 0x00000104 +#define DDRSS0_PHY_579_DATA 0x00000120 +#define DDRSS0_PHY_580_DATA 0x00000000 +#define DDRSS0_PHY_581_DATA 0x00000000 +#define DDRSS0_PHY_582_DATA 0x00000000 +#define DDRSS0_PHY_583_DATA 0x00000000 +#define DDRSS0_PHY_584_DATA 0x00000000 +#define DDRSS0_PHY_585_DATA 0x00000000 +#define DDRSS0_PHY_586_DATA 0x00000000 +#define DDRSS0_PHY_587_DATA 0x00000001 +#define DDRSS0_PHY_588_DATA 0x07FF0000 +#define DDRSS0_PHY_589_DATA 0x0080081F +#define DDRSS0_PHY_590_DATA 0x00081020 +#define DDRSS0_PHY_591_DATA 0x04010000 +#define DDRSS0_PHY_592_DATA 0x00000000 +#define DDRSS0_PHY_593_DATA 0x00000000 +#define DDRSS0_PHY_594_DATA 0x00000000 +#define DDRSS0_PHY_595_DATA 0x00000100 +#define DDRSS0_PHY_596_DATA 0x01CC0C01 +#define DDRSS0_PHY_597_DATA 0x1003CC0C +#define DDRSS0_PHY_598_DATA 0x20000140 +#define DDRSS0_PHY_599_DATA 0x07FF0200 +#define DDRSS0_PHY_600_DATA 0x0000DD01 +#define DDRSS0_PHY_601_DATA 0x10100303 +#define DDRSS0_PHY_602_DATA 0x10101010 +#define DDRSS0_PHY_603_DATA 0x10101010 +#define DDRSS0_PHY_604_DATA 0x00021010 +#define DDRSS0_PHY_605_DATA 0x00100010 +#define DDRSS0_PHY_606_DATA 0x00100010 +#define DDRSS0_PHY_607_DATA 0x00100010 +#define DDRSS0_PHY_608_DATA 0x00100010 +#define DDRSS0_PHY_609_DATA 0x00050010 +#define DDRSS0_PHY_610_DATA 0x51517041 +#define DDRSS0_PHY_611_DATA 0x31C06001 +#define DDRSS0_PHY_612_DATA 0x07AB01AB +#define DDRSS0_PHY_613_DATA 0x00C0C001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 +#define DDRSS0_PHY_615_DATA 0x10001000 +#define DDRSS0_PHY_616_DATA 0x0C083E42 +#define DDRSS0_PHY_617_DATA 0x0F0C3701 +#define DDRSS0_PHY_618_DATA 0x01000140 +#define DDRSS0_PHY_619_DATA 0x0C000420 +#define DDRSS0_PHY_620_DATA 0x00000198 +#define DDRSS0_PHY_621_DATA 0x0A0000D0 +#define DDRSS0_PHY_622_DATA 0x00030200 +#define DDRSS0_PHY_623_DATA 0x02800000 +#define DDRSS0_PHY_624_DATA 0x80800000 +#define DDRSS0_PHY_625_DATA 0x000E2010 +#define DDRSS0_PHY_626_DATA 0x76543210 +#define DDRSS0_PHY_627_DATA 0x00000008 +#define DDRSS0_PHY_628_DATA 0x02800280 +#define DDRSS0_PHY_629_DATA 0x02800280 +#define DDRSS0_PHY_630_DATA 0x02800280 +#define DDRSS0_PHY_631_DATA 0x02800280 +#define DDRSS0_PHY_632_DATA 0x00000280 +#define DDRSS0_PHY_633_DATA 0x0000A000 +#define DDRSS0_PHY_634_DATA 0x00A000A0 +#define DDRSS0_PHY_635_DATA 0x00A000A0 +#define DDRSS0_PHY_636_DATA 0x00A000A0 +#define DDRSS0_PHY_637_DATA 0x00A000A0 +#define DDRSS0_PHY_638_DATA 0x00A000A0 +#define DDRSS0_PHY_639_DATA 0x00A000A0 +#define DDRSS0_PHY_640_DATA 0x00A000A0 +#define DDRSS0_PHY_641_DATA 0x00A000A0 +#define DDRSS0_PHY_642_DATA 0x01C200A0 +#define DDRSS0_PHY_643_DATA 0x01A00005 +#define DDRSS0_PHY_644_DATA 0x00000000 +#define DDRSS0_PHY_645_DATA 0x00000000 +#define DDRSS0_PHY_646_DATA 0x00080200 +#define DDRSS0_PHY_647_DATA 0x00000000 +#define DDRSS0_PHY_648_DATA 0x20202000 +#define DDRSS0_PHY_649_DATA 0x20202020 +#define DDRSS0_PHY_650_DATA 0xF0F02020 +#define DDRSS0_PHY_651_DATA 0x00000000 +#define DDRSS0_PHY_652_DATA 0x00000000 +#define DDRSS0_PHY_653_DATA 0x00000000 +#define DDRSS0_PHY_654_DATA 0x00000000 +#define DDRSS0_PHY_655_DATA 0x00000000 +#define DDRSS0_PHY_656_DATA 0x00000000 +#define DDRSS0_PHY_657_DATA 0x00000000 +#define DDRSS0_PHY_658_DATA 0x00000000 +#define DDRSS0_PHY_659_DATA 0x00000000 +#define DDRSS0_PHY_660_DATA 0x00000000 +#define DDRSS0_PHY_661_DATA 0x00000000 +#define DDRSS0_PHY_662_DATA 0x00000000 +#define DDRSS0_PHY_663_DATA 0x00000000 +#define DDRSS0_PHY_664_DATA 0x00000000 +#define DDRSS0_PHY_665_DATA 0x00000000 +#define DDRSS0_PHY_666_DATA 0x00000000 +#define DDRSS0_PHY_667_DATA 0x00000000 +#define DDRSS0_PHY_668_DATA 0x00000000 +#define DDRSS0_PHY_669_DATA 0x00000000 +#define DDRSS0_PHY_670_DATA 0x00000000 +#define DDRSS0_PHY_671_DATA 0x00000000 +#define DDRSS0_PHY_672_DATA 0x00000000 +#define DDRSS0_PHY_673_DATA 0x00000000 +#define DDRSS0_PHY_674_DATA 0x00000000 +#define DDRSS0_PHY_675_DATA 0x00000000 +#define DDRSS0_PHY_676_DATA 0x00000000 +#define DDRSS0_PHY_677_DATA 0x00000000 +#define DDRSS0_PHY_678_DATA 0x00000000 +#define DDRSS0_PHY_679_DATA 0x00000000 +#define DDRSS0_PHY_680_DATA 0x00000000 +#define DDRSS0_PHY_681_DATA 0x00000000 +#define DDRSS0_PHY_682_DATA 0x00000000 +#define DDRSS0_PHY_683_DATA 0x00000000 +#define DDRSS0_PHY_684_DATA 0x00000000 +#define DDRSS0_PHY_685_DATA 0x00000000 +#define DDRSS0_PHY_686_DATA 0x00000000 +#define DDRSS0_PHY_687_DATA 0x00000000 +#define DDRSS0_PHY_688_DATA 0x00000000 +#define DDRSS0_PHY_689_DATA 0x00000000 +#define DDRSS0_PHY_690_DATA 0x00000000 +#define DDRSS0_PHY_691_DATA 0x00000000 +#define DDRSS0_PHY_692_DATA 0x00000000 +#define DDRSS0_PHY_693_DATA 0x00000000 +#define DDRSS0_PHY_694_DATA 0x00000000 +#define DDRSS0_PHY_695_DATA 0x00000000 +#define DDRSS0_PHY_696_DATA 0x00000000 +#define DDRSS0_PHY_697_DATA 0x00000000 +#define DDRSS0_PHY_698_DATA 0x00000000 +#define DDRSS0_PHY_699_DATA 0x00000000 +#define DDRSS0_PHY_700_DATA 0x00000000 +#define DDRSS0_PHY_701_DATA 0x00000000 +#define DDRSS0_PHY_702_DATA 0x00000000 +#define DDRSS0_PHY_703_DATA 0x00000000 +#define DDRSS0_PHY_704_DATA 0x00000000 +#define DDRSS0_PHY_705_DATA 0x00000000 +#define DDRSS0_PHY_706_DATA 0x00000000 +#define DDRSS0_PHY_707_DATA 0x00000000 +#define DDRSS0_PHY_708_DATA 0x00000000 +#define DDRSS0_PHY_709_DATA 0x00000000 +#define DDRSS0_PHY_710_DATA 0x00000000 +#define DDRSS0_PHY_711_DATA 0x00000000 +#define DDRSS0_PHY_712_DATA 0x00000000 +#define DDRSS0_PHY_713_DATA 0x00000000 +#define DDRSS0_PHY_714_DATA 0x00000000 +#define DDRSS0_PHY_715_DATA 0x00000000 +#define DDRSS0_PHY_716_DATA 0x00000000 +#define DDRSS0_PHY_717_DATA 0x00000000 +#define DDRSS0_PHY_718_DATA 0x00000000 +#define DDRSS0_PHY_719_DATA 0x00000000 +#define DDRSS0_PHY_720_DATA 0x00000000 +#define DDRSS0_PHY_721_DATA 0x00000000 +#define DDRSS0_PHY_722_DATA 0x00000000 +#define DDRSS0_PHY_723_DATA 0x00000000 +#define DDRSS0_PHY_724_DATA 0x00000000 +#define DDRSS0_PHY_725_DATA 0x00000000 +#define DDRSS0_PHY_726_DATA 0x00000000 +#define DDRSS0_PHY_727_DATA 0x00000000 +#define DDRSS0_PHY_728_DATA 0x00000000 +#define DDRSS0_PHY_729_DATA 0x00000000 +#define DDRSS0_PHY_730_DATA 0x00000000 +#define DDRSS0_PHY_731_DATA 0x00000000 +#define DDRSS0_PHY_732_DATA 0x00000000 +#define DDRSS0_PHY_733_DATA 0x00000000 +#define DDRSS0_PHY_734_DATA 0x00000000 +#define DDRSS0_PHY_735_DATA 0x00000000 +#define DDRSS0_PHY_736_DATA 0x00000000 +#define DDRSS0_PHY_737_DATA 0x00000000 +#define DDRSS0_PHY_738_DATA 0x00000000 +#define DDRSS0_PHY_739_DATA 0x00000000 +#define DDRSS0_PHY_740_DATA 0x00000000 +#define DDRSS0_PHY_741_DATA 0x00000000 +#define DDRSS0_PHY_742_DATA 0x00000000 +#define DDRSS0_PHY_743_DATA 0x00000000 +#define DDRSS0_PHY_744_DATA 0x00000000 +#define DDRSS0_PHY_745_DATA 0x00000000 +#define DDRSS0_PHY_746_DATA 0x00000000 +#define DDRSS0_PHY_747_DATA 0x00000000 +#define DDRSS0_PHY_748_DATA 0x00000000 +#define DDRSS0_PHY_749_DATA 0x00000000 +#define DDRSS0_PHY_750_DATA 0x00000000 +#define DDRSS0_PHY_751_DATA 0x00000000 +#define DDRSS0_PHY_752_DATA 0x00000000 +#define DDRSS0_PHY_753_DATA 0x00000000 +#define DDRSS0_PHY_754_DATA 0x00000000 +#define DDRSS0_PHY_755_DATA 0x00000000 +#define DDRSS0_PHY_756_DATA 0x00000000 +#define DDRSS0_PHY_757_DATA 0x00000000 +#define DDRSS0_PHY_758_DATA 0x00000000 +#define DDRSS0_PHY_759_DATA 0x00000000 +#define DDRSS0_PHY_760_DATA 0x00000000 +#define DDRSS0_PHY_761_DATA 0x00000000 +#define DDRSS0_PHY_762_DATA 0x00000000 +#define DDRSS0_PHY_763_DATA 0x00000000 +#define DDRSS0_PHY_764_DATA 0x00000000 +#define DDRSS0_PHY_765_DATA 0x00000000 +#define DDRSS0_PHY_766_DATA 0x00000000 +#define DDRSS0_PHY_767_DATA 0x00000000 +#define DDRSS0_PHY_768_DATA 0x000004F0 +#define DDRSS0_PHY_769_DATA 0x00000000 +#define DDRSS0_PHY_770_DATA 0x00030200 +#define DDRSS0_PHY_771_DATA 0x00000000 +#define DDRSS0_PHY_772_DATA 0x00000000 +#define DDRSS0_PHY_773_DATA 0x01030000 +#define DDRSS0_PHY_774_DATA 0x00010000 +#define DDRSS0_PHY_775_DATA 0x01030004 +#define DDRSS0_PHY_776_DATA 0x01000000 +#define DDRSS0_PHY_777_DATA 0x00000000 +#define DDRSS0_PHY_778_DATA 0x00000000 +#define DDRSS0_PHY_779_DATA 0x01000001 +#define DDRSS0_PHY_780_DATA 0x00000200 +#define DDRSS0_PHY_781_DATA 0x000800C0 +#define DDRSS0_PHY_782_DATA 0x060100CC +#define DDRSS0_PHY_783_DATA 0x00030066 +#define DDRSS0_PHY_784_DATA 0x00000000 +#define DDRSS0_PHY_785_DATA 0x00000301 +#define DDRSS0_PHY_786_DATA 0x0000AAAA +#define DDRSS0_PHY_787_DATA 0x00005555 +#define DDRSS0_PHY_788_DATA 0x0000B5B5 +#define DDRSS0_PHY_789_DATA 0x00004A4A +#define DDRSS0_PHY_790_DATA 0x00005656 +#define DDRSS0_PHY_791_DATA 0x0000A9A9 +#define DDRSS0_PHY_792_DATA 0x0000A9A9 +#define DDRSS0_PHY_793_DATA 0x0000B5B5 +#define DDRSS0_PHY_794_DATA 0x00000000 +#define DDRSS0_PHY_795_DATA 0x00000000 +#define DDRSS0_PHY_796_DATA 0x2A000000 +#define DDRSS0_PHY_797_DATA 0x00000808 +#define DDRSS0_PHY_798_DATA 0x0F000000 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002006 +#define DDRSS0_PHY_802_DATA 0x00000000 +#define DDRSS0_PHY_803_DATA 0x00000000 +#define DDRSS0_PHY_804_DATA 0x55555555 +#define DDRSS0_PHY_805_DATA 0xAAAAAAAA +#define DDRSS0_PHY_806_DATA 0x55555555 +#define DDRSS0_PHY_807_DATA 0xAAAAAAAA +#define DDRSS0_PHY_808_DATA 0x00005555 +#define DDRSS0_PHY_809_DATA 0x01000100 +#define DDRSS0_PHY_810_DATA 0x00800180 +#define DDRSS0_PHY_811_DATA 0x00000000 +#define DDRSS0_PHY_812_DATA 0x00000000 +#define DDRSS0_PHY_813_DATA 0x00000000 +#define DDRSS0_PHY_814_DATA 0x00000000 +#define DDRSS0_PHY_815_DATA 0x00000000 +#define DDRSS0_PHY_816_DATA 0x00000000 +#define DDRSS0_PHY_817_DATA 0x00000000 +#define DDRSS0_PHY_818_DATA 0x00000000 +#define DDRSS0_PHY_819_DATA 0x00000000 +#define DDRSS0_PHY_820_DATA 0x00000000 +#define DDRSS0_PHY_821_DATA 0x00000000 +#define DDRSS0_PHY_822_DATA 0x00000000 +#define DDRSS0_PHY_823_DATA 0x00000000 +#define DDRSS0_PHY_824_DATA 0x00000000 +#define DDRSS0_PHY_825_DATA 0x00000000 +#define DDRSS0_PHY_826_DATA 0x00000000 +#define DDRSS0_PHY_827_DATA 0x00000000 +#define DDRSS0_PHY_828_DATA 0x00000000 +#define DDRSS0_PHY_829_DATA 0x00000000 +#define DDRSS0_PHY_830_DATA 0x00000000 +#define DDRSS0_PHY_831_DATA 0x00000000 +#define DDRSS0_PHY_832_DATA 0x00000000 +#define DDRSS0_PHY_833_DATA 0x00000000 +#define DDRSS0_PHY_834_DATA 0x00000104 +#define DDRSS0_PHY_835_DATA 0x00000120 +#define DDRSS0_PHY_836_DATA 0x00000000 +#define DDRSS0_PHY_837_DATA 0x00000000 +#define DDRSS0_PHY_838_DATA 0x00000000 +#define DDRSS0_PHY_839_DATA 0x00000000 +#define DDRSS0_PHY_840_DATA 0x00000000 +#define DDRSS0_PHY_841_DATA 0x00000000 +#define DDRSS0_PHY_842_DATA 0x00000000 +#define DDRSS0_PHY_843_DATA 0x00000001 +#define DDRSS0_PHY_844_DATA 0x07FF0000 +#define DDRSS0_PHY_845_DATA 0x0080081F +#define DDRSS0_PHY_846_DATA 0x00081020 +#define DDRSS0_PHY_847_DATA 0x04010000 +#define DDRSS0_PHY_848_DATA 0x00000000 +#define DDRSS0_PHY_849_DATA 0x00000000 +#define DDRSS0_PHY_850_DATA 0x00000000 +#define DDRSS0_PHY_851_DATA 0x00000100 +#define DDRSS0_PHY_852_DATA 0x01CC0C01 +#define DDRSS0_PHY_853_DATA 0x1003CC0C +#define DDRSS0_PHY_854_DATA 0x20000140 +#define DDRSS0_PHY_855_DATA 0x07FF0200 +#define DDRSS0_PHY_856_DATA 0x0000DD01 +#define DDRSS0_PHY_857_DATA 0x10100303 +#define DDRSS0_PHY_858_DATA 0x10101010 +#define DDRSS0_PHY_859_DATA 0x10101010 +#define DDRSS0_PHY_860_DATA 0x00021010 +#define DDRSS0_PHY_861_DATA 0x00100010 +#define DDRSS0_PHY_862_DATA 0x00100010 +#define DDRSS0_PHY_863_DATA 0x00100010 +#define DDRSS0_PHY_864_DATA 0x00100010 +#define DDRSS0_PHY_865_DATA 0x00050010 +#define DDRSS0_PHY_866_DATA 0x51517041 +#define DDRSS0_PHY_867_DATA 0x31C06001 +#define DDRSS0_PHY_868_DATA 0x07AB01AB +#define DDRSS0_PHY_869_DATA 0x00C0C001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 +#define DDRSS0_PHY_871_DATA 0x10001000 +#define DDRSS0_PHY_872_DATA 0x0C083E42 +#define DDRSS0_PHY_873_DATA 0x0F0C3701 +#define DDRSS0_PHY_874_DATA 0x01000140 +#define DDRSS0_PHY_875_DATA 0x0C000420 +#define DDRSS0_PHY_876_DATA 0x00000198 +#define DDRSS0_PHY_877_DATA 0x0A0000D0 +#define DDRSS0_PHY_878_DATA 0x00030200 +#define DDRSS0_PHY_879_DATA 0x02800000 +#define DDRSS0_PHY_880_DATA 0x80800000 +#define DDRSS0_PHY_881_DATA 0x000E2010 +#define DDRSS0_PHY_882_DATA 0x76543210 +#define DDRSS0_PHY_883_DATA 0x00000008 +#define DDRSS0_PHY_884_DATA 0x02800280 +#define DDRSS0_PHY_885_DATA 0x02800280 +#define DDRSS0_PHY_886_DATA 0x02800280 +#define DDRSS0_PHY_887_DATA 0x02800280 +#define DDRSS0_PHY_888_DATA 0x00000280 +#define DDRSS0_PHY_889_DATA 0x0000A000 +#define DDRSS0_PHY_890_DATA 0x00A000A0 +#define DDRSS0_PHY_891_DATA 0x00A000A0 +#define DDRSS0_PHY_892_DATA 0x00A000A0 +#define DDRSS0_PHY_893_DATA 0x00A000A0 +#define DDRSS0_PHY_894_DATA 0x00A000A0 +#define DDRSS0_PHY_895_DATA 0x00A000A0 +#define DDRSS0_PHY_896_DATA 0x00A000A0 +#define DDRSS0_PHY_897_DATA 0x00A000A0 +#define DDRSS0_PHY_898_DATA 0x01C200A0 +#define DDRSS0_PHY_899_DATA 0x01A00005 +#define DDRSS0_PHY_900_DATA 0x00000000 +#define DDRSS0_PHY_901_DATA 0x00000000 +#define DDRSS0_PHY_902_DATA 0x00080200 +#define DDRSS0_PHY_903_DATA 0x00000000 +#define DDRSS0_PHY_904_DATA 0x20202000 +#define DDRSS0_PHY_905_DATA 0x20202020 +#define DDRSS0_PHY_906_DATA 0xF0F02020 +#define DDRSS0_PHY_907_DATA 0x00000000 +#define DDRSS0_PHY_908_DATA 0x00000000 +#define DDRSS0_PHY_909_DATA 0x00000000 +#define DDRSS0_PHY_910_DATA 0x00000000 +#define DDRSS0_PHY_911_DATA 0x00000000 +#define DDRSS0_PHY_912_DATA 0x00000000 +#define DDRSS0_PHY_913_DATA 0x00000000 +#define DDRSS0_PHY_914_DATA 0x00000000 +#define DDRSS0_PHY_915_DATA 0x00000000 +#define DDRSS0_PHY_916_DATA 0x00000000 +#define DDRSS0_PHY_917_DATA 0x00000000 +#define DDRSS0_PHY_918_DATA 0x00000000 +#define DDRSS0_PHY_919_DATA 0x00000000 +#define DDRSS0_PHY_920_DATA 0x00000000 +#define DDRSS0_PHY_921_DATA 0x00000000 +#define DDRSS0_PHY_922_DATA 0x00000000 +#define DDRSS0_PHY_923_DATA 0x00000000 +#define DDRSS0_PHY_924_DATA 0x00000000 +#define DDRSS0_PHY_925_DATA 0x00000000 +#define DDRSS0_PHY_926_DATA 0x00000000 +#define DDRSS0_PHY_927_DATA 0x00000000 +#define DDRSS0_PHY_928_DATA 0x00000000 +#define DDRSS0_PHY_929_DATA 0x00000000 +#define DDRSS0_PHY_930_DATA 0x00000000 +#define DDRSS0_PHY_931_DATA 0x00000000 +#define DDRSS0_PHY_932_DATA 0x00000000 +#define DDRSS0_PHY_933_DATA 0x00000000 +#define DDRSS0_PHY_934_DATA 0x00000000 +#define DDRSS0_PHY_935_DATA 0x00000000 +#define DDRSS0_PHY_936_DATA 0x00000000 +#define DDRSS0_PHY_937_DATA 0x00000000 +#define DDRSS0_PHY_938_DATA 0x00000000 +#define DDRSS0_PHY_939_DATA 0x00000000 +#define DDRSS0_PHY_940_DATA 0x00000000 +#define DDRSS0_PHY_941_DATA 0x00000000 +#define DDRSS0_PHY_942_DATA 0x00000000 +#define DDRSS0_PHY_943_DATA 0x00000000 +#define DDRSS0_PHY_944_DATA 0x00000000 +#define DDRSS0_PHY_945_DATA 0x00000000 +#define DDRSS0_PHY_946_DATA 0x00000000 +#define DDRSS0_PHY_947_DATA 0x00000000 +#define DDRSS0_PHY_948_DATA 0x00000000 +#define DDRSS0_PHY_949_DATA 0x00000000 +#define DDRSS0_PHY_950_DATA 0x00000000 +#define DDRSS0_PHY_951_DATA 0x00000000 +#define DDRSS0_PHY_952_DATA 0x00000000 +#define DDRSS0_PHY_953_DATA 0x00000000 +#define DDRSS0_PHY_954_DATA 0x00000000 +#define DDRSS0_PHY_955_DATA 0x00000000 +#define DDRSS0_PHY_956_DATA 0x00000000 +#define DDRSS0_PHY_957_DATA 0x00000000 +#define DDRSS0_PHY_958_DATA 0x00000000 +#define DDRSS0_PHY_959_DATA 0x00000000 +#define DDRSS0_PHY_960_DATA 0x00000000 +#define DDRSS0_PHY_961_DATA 0x00000000 +#define DDRSS0_PHY_962_DATA 0x00000000 +#define DDRSS0_PHY_963_DATA 0x00000000 +#define DDRSS0_PHY_964_DATA 0x00000000 +#define DDRSS0_PHY_965_DATA 0x00000000 +#define DDRSS0_PHY_966_DATA 0x00000000 +#define DDRSS0_PHY_967_DATA 0x00000000 +#define DDRSS0_PHY_968_DATA 0x00000000 +#define DDRSS0_PHY_969_DATA 0x00000000 +#define DDRSS0_PHY_970_DATA 0x00000000 +#define DDRSS0_PHY_971_DATA 0x00000000 +#define DDRSS0_PHY_972_DATA 0x00000000 +#define DDRSS0_PHY_973_DATA 0x00000000 +#define DDRSS0_PHY_974_DATA 0x00000000 +#define DDRSS0_PHY_975_DATA 0x00000000 +#define DDRSS0_PHY_976_DATA 0x00000000 +#define DDRSS0_PHY_977_DATA 0x00000000 +#define DDRSS0_PHY_978_DATA 0x00000000 +#define DDRSS0_PHY_979_DATA 0x00000000 +#define DDRSS0_PHY_980_DATA 0x00000000 +#define DDRSS0_PHY_981_DATA 0x00000000 +#define DDRSS0_PHY_982_DATA 0x00000000 +#define DDRSS0_PHY_983_DATA 0x00000000 +#define DDRSS0_PHY_984_DATA 0x00000000 +#define DDRSS0_PHY_985_DATA 0x00000000 +#define DDRSS0_PHY_986_DATA 0x00000000 +#define DDRSS0_PHY_987_DATA 0x00000000 +#define DDRSS0_PHY_988_DATA 0x00000000 +#define DDRSS0_PHY_989_DATA 0x00000000 +#define DDRSS0_PHY_990_DATA 0x00000000 +#define DDRSS0_PHY_991_DATA 0x00000000 +#define DDRSS0_PHY_992_DATA 0x00000000 +#define DDRSS0_PHY_993_DATA 0x00000000 +#define DDRSS0_PHY_994_DATA 0x00000000 +#define DDRSS0_PHY_995_DATA 0x00000000 +#define DDRSS0_PHY_996_DATA 0x00000000 +#define DDRSS0_PHY_997_DATA 0x00000000 +#define DDRSS0_PHY_998_DATA 0x00000000 +#define DDRSS0_PHY_999_DATA 0x00000000 +#define DDRSS0_PHY_1000_DATA 0x00000000 +#define DDRSS0_PHY_1001_DATA 0x00000000 +#define DDRSS0_PHY_1002_DATA 0x00000000 +#define DDRSS0_PHY_1003_DATA 0x00000000 +#define DDRSS0_PHY_1004_DATA 0x00000000 +#define DDRSS0_PHY_1005_DATA 0x00000000 +#define DDRSS0_PHY_1006_DATA 0x00000000 +#define DDRSS0_PHY_1007_DATA 0x00000000 +#define DDRSS0_PHY_1008_DATA 0x00000000 +#define DDRSS0_PHY_1009_DATA 0x00000000 +#define DDRSS0_PHY_1010_DATA 0x00000000 +#define DDRSS0_PHY_1011_DATA 0x00000000 +#define DDRSS0_PHY_1012_DATA 0x00000000 +#define DDRSS0_PHY_1013_DATA 0x00000000 +#define DDRSS0_PHY_1014_DATA 0x00000000 +#define DDRSS0_PHY_1015_DATA 0x00000000 +#define DDRSS0_PHY_1016_DATA 0x00000000 +#define DDRSS0_PHY_1017_DATA 0x00000000 +#define DDRSS0_PHY_1018_DATA 0x00000000 +#define DDRSS0_PHY_1019_DATA 0x00000000 +#define DDRSS0_PHY_1020_DATA 0x00000000 +#define DDRSS0_PHY_1021_DATA 0x00000000 +#define DDRSS0_PHY_1022_DATA 0x00000000 +#define DDRSS0_PHY_1023_DATA 0x00000000 +#define DDRSS0_PHY_1024_DATA 0x00000000 +#define DDRSS0_PHY_1025_DATA 0x00000000 +#define DDRSS0_PHY_1026_DATA 0x00000000 +#define DDRSS0_PHY_1027_DATA 0x00000000 +#define DDRSS0_PHY_1028_DATA 0x00000000 +#define DDRSS0_PHY_1029_DATA 0x00000100 +#define DDRSS0_PHY_1030_DATA 0x00000200 +#define DDRSS0_PHY_1031_DATA 0x00000000 +#define DDRSS0_PHY_1032_DATA 0x00000000 +#define DDRSS0_PHY_1033_DATA 0x00000000 +#define DDRSS0_PHY_1034_DATA 0x00000000 +#define DDRSS0_PHY_1035_DATA 0x00400000 +#define DDRSS0_PHY_1036_DATA 0x00000080 +#define DDRSS0_PHY_1037_DATA 0x00DCBA98 +#define DDRSS0_PHY_1038_DATA 0x03000000 +#define DDRSS0_PHY_1039_DATA 0x00200000 +#define DDRSS0_PHY_1040_DATA 0x00000000 +#define DDRSS0_PHY_1041_DATA 0x00000000 +#define DDRSS0_PHY_1042_DATA 0x00000000 +#define DDRSS0_PHY_1043_DATA 0x00000000 +#define DDRSS0_PHY_1044_DATA 0x00000000 +#define DDRSS0_PHY_1045_DATA 0x0000002A +#define DDRSS0_PHY_1046_DATA 0x00000015 +#define DDRSS0_PHY_1047_DATA 0x00000015 +#define DDRSS0_PHY_1048_DATA 0x0000002A +#define DDRSS0_PHY_1049_DATA 0x00000033 +#define DDRSS0_PHY_1050_DATA 0x0000000C +#define DDRSS0_PHY_1051_DATA 0x0000000C +#define DDRSS0_PHY_1052_DATA 0x00000033 +#define DDRSS0_PHY_1053_DATA 0x00543210 +#define DDRSS0_PHY_1054_DATA 0x003F0000 +#define DDRSS0_PHY_1055_DATA 0x000F3F3F +#define DDRSS0_PHY_1056_DATA 0x20202003 +#define DDRSS0_PHY_1057_DATA 0x00202020 +#define DDRSS0_PHY_1058_DATA 0x20008008 +#define DDRSS0_PHY_1059_DATA 0x00000810 +#define DDRSS0_PHY_1060_DATA 0x00000F00 +#define DDRSS0_PHY_1061_DATA 0x00000000 +#define DDRSS0_PHY_1062_DATA 0x00000000 +#define DDRSS0_PHY_1063_DATA 0x00000000 +#define DDRSS0_PHY_1064_DATA 0x000305CC +#define DDRSS0_PHY_1065_DATA 0x00030000 +#define DDRSS0_PHY_1066_DATA 0x00000300 +#define DDRSS0_PHY_1067_DATA 0x00000300 +#define DDRSS0_PHY_1068_DATA 0x00000300 +#define DDRSS0_PHY_1069_DATA 0x00000300 +#define DDRSS0_PHY_1070_DATA 0x00000300 +#define DDRSS0_PHY_1071_DATA 0x42080010 +#define DDRSS0_PHY_1072_DATA 0x0000803E +#define DDRSS0_PHY_1073_DATA 0x00000001 +#define DDRSS0_PHY_1074_DATA 0x01000102 +#define DDRSS0_PHY_1075_DATA 0x00008000 +#define DDRSS0_PHY_1076_DATA 0x00000000 +#define DDRSS0_PHY_1077_DATA 0x00000000 +#define DDRSS0_PHY_1078_DATA 0x00000000 +#define DDRSS0_PHY_1079_DATA 0x00000000 +#define DDRSS0_PHY_1080_DATA 0x00000000 +#define DDRSS0_PHY_1081_DATA 0x00000000 +#define DDRSS0_PHY_1082_DATA 0x00000000 +#define DDRSS0_PHY_1083_DATA 0x00000000 +#define DDRSS0_PHY_1084_DATA 0x00000000 +#define DDRSS0_PHY_1085_DATA 0x00000000 +#define DDRSS0_PHY_1086_DATA 0x00000000 +#define DDRSS0_PHY_1087_DATA 0x00000000 +#define DDRSS0_PHY_1088_DATA 0x00000000 +#define DDRSS0_PHY_1089_DATA 0x00000000 +#define DDRSS0_PHY_1090_DATA 0x00000000 +#define DDRSS0_PHY_1091_DATA 0x00000000 +#define DDRSS0_PHY_1092_DATA 0x00000000 +#define DDRSS0_PHY_1093_DATA 0x00000000 +#define DDRSS0_PHY_1094_DATA 0x00000000 +#define DDRSS0_PHY_1095_DATA 0x00000000 +#define DDRSS0_PHY_1096_DATA 0x00000000 +#define DDRSS0_PHY_1097_DATA 0x00000000 +#define DDRSS0_PHY_1098_DATA 0x00000000 +#define DDRSS0_PHY_1099_DATA 0x00000000 +#define DDRSS0_PHY_1100_DATA 0x00000000 +#define DDRSS0_PHY_1101_DATA 0x00000000 +#define DDRSS0_PHY_1102_DATA 0x00000000 +#define DDRSS0_PHY_1103_DATA 0x00000000 +#define DDRSS0_PHY_1104_DATA 0x00000000 +#define DDRSS0_PHY_1105_DATA 0x00000000 +#define DDRSS0_PHY_1106_DATA 0x00000000 +#define DDRSS0_PHY_1107_DATA 0x00000000 +#define DDRSS0_PHY_1108_DATA 0x00000000 +#define DDRSS0_PHY_1109_DATA 0x00000000 +#define DDRSS0_PHY_1110_DATA 0x00000000 +#define DDRSS0_PHY_1111_DATA 0x00000000 +#define DDRSS0_PHY_1112_DATA 0x00000000 +#define DDRSS0_PHY_1113_DATA 0x00000000 +#define DDRSS0_PHY_1114_DATA 0x00000000 +#define DDRSS0_PHY_1115_DATA 0x00000000 +#define DDRSS0_PHY_1116_DATA 0x00000000 +#define DDRSS0_PHY_1117_DATA 0x00000000 +#define DDRSS0_PHY_1118_DATA 0x00000000 +#define DDRSS0_PHY_1119_DATA 0x00000000 +#define DDRSS0_PHY_1120_DATA 0x00000000 +#define DDRSS0_PHY_1121_DATA 0x00000000 +#define DDRSS0_PHY_1122_DATA 0x00000000 +#define DDRSS0_PHY_1123_DATA 0x00000000 +#define DDRSS0_PHY_1124_DATA 0x00000000 +#define DDRSS0_PHY_1125_DATA 0x00000000 +#define DDRSS0_PHY_1126_DATA 0x00000000 +#define DDRSS0_PHY_1127_DATA 0x00000000 +#define DDRSS0_PHY_1128_DATA 0x00000000 +#define DDRSS0_PHY_1129_DATA 0x00000000 +#define DDRSS0_PHY_1130_DATA 0x00000000 +#define DDRSS0_PHY_1131_DATA 0x00000000 +#define DDRSS0_PHY_1132_DATA 0x00000000 +#define DDRSS0_PHY_1133_DATA 0x00000000 +#define DDRSS0_PHY_1134_DATA 0x00000000 +#define DDRSS0_PHY_1135_DATA 0x00000000 +#define DDRSS0_PHY_1136_DATA 0x00000000 +#define DDRSS0_PHY_1137_DATA 0x00000000 +#define DDRSS0_PHY_1138_DATA 0x00000000 +#define DDRSS0_PHY_1139_DATA 0x00000000 +#define DDRSS0_PHY_1140_DATA 0x00000000 +#define DDRSS0_PHY_1141_DATA 0x00000000 +#define DDRSS0_PHY_1142_DATA 0x00000000 +#define DDRSS0_PHY_1143_DATA 0x00000000 +#define DDRSS0_PHY_1144_DATA 0x00000000 +#define DDRSS0_PHY_1145_DATA 0x00000000 +#define DDRSS0_PHY_1146_DATA 0x00000000 +#define DDRSS0_PHY_1147_DATA 0x00000000 +#define DDRSS0_PHY_1148_DATA 0x00000000 +#define DDRSS0_PHY_1149_DATA 0x00000000 +#define DDRSS0_PHY_1150_DATA 0x00000000 +#define DDRSS0_PHY_1151_DATA 0x00000000 +#define DDRSS0_PHY_1152_DATA 0x00000000 +#define DDRSS0_PHY_1153_DATA 0x00000000 +#define DDRSS0_PHY_1154_DATA 0x00000000 +#define DDRSS0_PHY_1155_DATA 0x00000000 +#define DDRSS0_PHY_1156_DATA 0x00000000 +#define DDRSS0_PHY_1157_DATA 0x00000000 +#define DDRSS0_PHY_1158_DATA 0x00000000 +#define DDRSS0_PHY_1159_DATA 0x00000000 +#define DDRSS0_PHY_1160_DATA 0x00000000 +#define DDRSS0_PHY_1161_DATA 0x00000000 +#define DDRSS0_PHY_1162_DATA 0x00000000 +#define DDRSS0_PHY_1163_DATA 0x00000000 +#define DDRSS0_PHY_1164_DATA 0x00000000 +#define DDRSS0_PHY_1165_DATA 0x00000000 +#define DDRSS0_PHY_1166_DATA 0x00000000 +#define DDRSS0_PHY_1167_DATA 0x00000000 +#define DDRSS0_PHY_1168_DATA 0x00000000 +#define DDRSS0_PHY_1169_DATA 0x00000000 +#define DDRSS0_PHY_1170_DATA 0x00000000 +#define DDRSS0_PHY_1171_DATA 0x00000000 +#define DDRSS0_PHY_1172_DATA 0x00000000 +#define DDRSS0_PHY_1173_DATA 0x00000000 +#define DDRSS0_PHY_1174_DATA 0x00000000 +#define DDRSS0_PHY_1175_DATA 0x00000000 +#define DDRSS0_PHY_1176_DATA 0x00000000 +#define DDRSS0_PHY_1177_DATA 0x00000000 +#define DDRSS0_PHY_1178_DATA 0x00000000 +#define DDRSS0_PHY_1179_DATA 0x00000000 +#define DDRSS0_PHY_1180_DATA 0x00000000 +#define DDRSS0_PHY_1181_DATA 0x00000000 +#define DDRSS0_PHY_1182_DATA 0x00000000 +#define DDRSS0_PHY_1183_DATA 0x00000000 +#define DDRSS0_PHY_1184_DATA 0x00000000 +#define DDRSS0_PHY_1185_DATA 0x00000000 +#define DDRSS0_PHY_1186_DATA 0x00000000 +#define DDRSS0_PHY_1187_DATA 0x00000000 +#define DDRSS0_PHY_1188_DATA 0x00000000 +#define DDRSS0_PHY_1189_DATA 0x00000000 +#define DDRSS0_PHY_1190_DATA 0x00000000 +#define DDRSS0_PHY_1191_DATA 0x00000000 +#define DDRSS0_PHY_1192_DATA 0x00000000 +#define DDRSS0_PHY_1193_DATA 0x00000000 +#define DDRSS0_PHY_1194_DATA 0x00000000 +#define DDRSS0_PHY_1195_DATA 0x00000000 +#define DDRSS0_PHY_1196_DATA 0x00000000 +#define DDRSS0_PHY_1197_DATA 0x00000000 +#define DDRSS0_PHY_1198_DATA 0x00000000 +#define DDRSS0_PHY_1199_DATA 0x00000000 +#define DDRSS0_PHY_1200_DATA 0x00000000 +#define DDRSS0_PHY_1201_DATA 0x00000000 +#define DDRSS0_PHY_1202_DATA 0x00000000 +#define DDRSS0_PHY_1203_DATA 0x00000000 +#define DDRSS0_PHY_1204_DATA 0x00000000 +#define DDRSS0_PHY_1205_DATA 0x00000000 +#define DDRSS0_PHY_1206_DATA 0x00000000 +#define DDRSS0_PHY_1207_DATA 0x00000000 +#define DDRSS0_PHY_1208_DATA 0x00000000 +#define DDRSS0_PHY_1209_DATA 0x00000000 +#define DDRSS0_PHY_1210_DATA 0x00000000 +#define DDRSS0_PHY_1211_DATA 0x00000000 +#define DDRSS0_PHY_1212_DATA 0x00000000 +#define DDRSS0_PHY_1213_DATA 0x00000000 +#define DDRSS0_PHY_1214_DATA 0x00000000 +#define DDRSS0_PHY_1215_DATA 0x00000000 +#define DDRSS0_PHY_1216_DATA 0x00000000 +#define DDRSS0_PHY_1217_DATA 0x00000000 +#define DDRSS0_PHY_1218_DATA 0x00000000 +#define DDRSS0_PHY_1219_DATA 0x00000000 +#define DDRSS0_PHY_1220_DATA 0x00000000 +#define DDRSS0_PHY_1221_DATA 0x00000000 +#define DDRSS0_PHY_1222_DATA 0x00000000 +#define DDRSS0_PHY_1223_DATA 0x00000000 +#define DDRSS0_PHY_1224_DATA 0x00000000 +#define DDRSS0_PHY_1225_DATA 0x00000000 +#define DDRSS0_PHY_1226_DATA 0x00000000 +#define DDRSS0_PHY_1227_DATA 0x00000000 +#define DDRSS0_PHY_1228_DATA 0x00000000 +#define DDRSS0_PHY_1229_DATA 0x00000000 +#define DDRSS0_PHY_1230_DATA 0x00000000 +#define DDRSS0_PHY_1231_DATA 0x00000000 +#define DDRSS0_PHY_1232_DATA 0x00000000 +#define DDRSS0_PHY_1233_DATA 0x00000000 +#define DDRSS0_PHY_1234_DATA 0x00000000 +#define DDRSS0_PHY_1235_DATA 0x00000000 +#define DDRSS0_PHY_1236_DATA 0x00000000 +#define DDRSS0_PHY_1237_DATA 0x00000000 +#define DDRSS0_PHY_1238_DATA 0x00000000 +#define DDRSS0_PHY_1239_DATA 0x00000000 +#define DDRSS0_PHY_1240_DATA 0x00000000 +#define DDRSS0_PHY_1241_DATA 0x00000000 +#define DDRSS0_PHY_1242_DATA 0x00000000 +#define DDRSS0_PHY_1243_DATA 0x00000000 +#define DDRSS0_PHY_1244_DATA 0x00000000 +#define DDRSS0_PHY_1245_DATA 0x00000000 +#define DDRSS0_PHY_1246_DATA 0x00000000 +#define DDRSS0_PHY_1247_DATA 0x00000000 +#define DDRSS0_PHY_1248_DATA 0x00000000 +#define DDRSS0_PHY_1249_DATA 0x00000000 +#define DDRSS0_PHY_1250_DATA 0x00000000 +#define DDRSS0_PHY_1251_DATA 0x00000000 +#define DDRSS0_PHY_1252_DATA 0x00000000 +#define DDRSS0_PHY_1253_DATA 0x00000000 +#define DDRSS0_PHY_1254_DATA 0x00000000 +#define DDRSS0_PHY_1255_DATA 0x00000000 +#define DDRSS0_PHY_1256_DATA 0x00000000 +#define DDRSS0_PHY_1257_DATA 0x00000000 +#define DDRSS0_PHY_1258_DATA 0x00000000 +#define DDRSS0_PHY_1259_DATA 0x00000000 +#define DDRSS0_PHY_1260_DATA 0x00000000 +#define DDRSS0_PHY_1261_DATA 0x00000000 +#define DDRSS0_PHY_1262_DATA 0x00000000 +#define DDRSS0_PHY_1263_DATA 0x00000000 +#define DDRSS0_PHY_1264_DATA 0x00000000 +#define DDRSS0_PHY_1265_DATA 0x00000000 +#define DDRSS0_PHY_1266_DATA 0x00000000 +#define DDRSS0_PHY_1267_DATA 0x00000000 +#define DDRSS0_PHY_1268_DATA 0x00000000 +#define DDRSS0_PHY_1269_DATA 0x00000000 +#define DDRSS0_PHY_1270_DATA 0x00000000 +#define DDRSS0_PHY_1271_DATA 0x00000000 +#define DDRSS0_PHY_1272_DATA 0x00000000 +#define DDRSS0_PHY_1273_DATA 0x00000000 +#define DDRSS0_PHY_1274_DATA 0x00000000 +#define DDRSS0_PHY_1275_DATA 0x00000000 +#define DDRSS0_PHY_1276_DATA 0x00000000 +#define DDRSS0_PHY_1277_DATA 0x00000000 +#define DDRSS0_PHY_1278_DATA 0x00000000 +#define DDRSS0_PHY_1279_DATA 0x00000000 +#define DDRSS0_PHY_1280_DATA 0x00000000 +#define DDRSS0_PHY_1281_DATA 0x00010100 +#define DDRSS0_PHY_1282_DATA 0x00000000 +#define DDRSS0_PHY_1283_DATA 0x00000000 +#define DDRSS0_PHY_1284_DATA 0x00050000 +#define DDRSS0_PHY_1285_DATA 0x04000000 +#define DDRSS0_PHY_1286_DATA 0x00000055 +#define DDRSS0_PHY_1287_DATA 0x00000000 +#define DDRSS0_PHY_1288_DATA 0x00000000 +#define DDRSS0_PHY_1289_DATA 0x00000000 +#define DDRSS0_PHY_1290_DATA 0x00000000 +#define DDRSS0_PHY_1291_DATA 0x00002001 +#define DDRSS0_PHY_1292_DATA 0x0000400F +#define DDRSS0_PHY_1293_DATA 0x50020028 +#define DDRSS0_PHY_1294_DATA 0x01010000 +#define DDRSS0_PHY_1295_DATA 0x80080001 +#define DDRSS0_PHY_1296_DATA 0x10200000 +#define DDRSS0_PHY_1297_DATA 0x00000008 +#define DDRSS0_PHY_1298_DATA 0x00000000 +#define DDRSS0_PHY_1299_DATA 0x01090E00 +#define DDRSS0_PHY_1300_DATA 0x00040101 +#define DDRSS0_PHY_1301_DATA 0x0000010F +#define DDRSS0_PHY_1302_DATA 0x00000000 +#define DDRSS0_PHY_1303_DATA 0x00000064 +#define DDRSS0_PHY_1304_DATA 0x00000000 +#define DDRSS0_PHY_1305_DATA 0x01010000 +#define DDRSS0_PHY_1306_DATA 0x01080402 +#define DDRSS0_PHY_1307_DATA 0x01200F02 +#define DDRSS0_PHY_1308_DATA 0x00194280 +#define DDRSS0_PHY_1309_DATA 0x00000004 +#define DDRSS0_PHY_1310_DATA 0x00042000 +#define DDRSS0_PHY_1311_DATA 0x00000000 +#define DDRSS0_PHY_1312_DATA 0x00000000 +#define DDRSS0_PHY_1313_DATA 0x00000000 +#define DDRSS0_PHY_1314_DATA 0x00000000 +#define DDRSS0_PHY_1315_DATA 0x00000000 +#define DDRSS0_PHY_1316_DATA 0x00000000 +#define DDRSS0_PHY_1317_DATA 0x01000000 +#define DDRSS0_PHY_1318_DATA 0x00000705 +#define DDRSS0_PHY_1319_DATA 0x00000054 +#define DDRSS0_PHY_1320_DATA 0x00030820 +#define DDRSS0_PHY_1321_DATA 0x00010820 +#define DDRSS0_PHY_1322_DATA 0x00010820 +#define DDRSS0_PHY_1323_DATA 0x00010820 +#define DDRSS0_PHY_1324_DATA 0x00010820 +#define DDRSS0_PHY_1325_DATA 0x00010820 +#define DDRSS0_PHY_1326_DATA 0x00010820 +#define DDRSS0_PHY_1327_DATA 0x00010820 +#define DDRSS0_PHY_1328_DATA 0x00010820 +#define DDRSS0_PHY_1329_DATA 0x00000000 +#define DDRSS0_PHY_1330_DATA 0x00000074 +#define DDRSS0_PHY_1331_DATA 0x00000400 +#define DDRSS0_PHY_1332_DATA 0x00000108 +#define DDRSS0_PHY_1333_DATA 0x00000000 +#define DDRSS0_PHY_1334_DATA 0x00000000 +#define DDRSS0_PHY_1335_DATA 0x00000000 +#define DDRSS0_PHY_1336_DATA 0x00000000 +#define DDRSS0_PHY_1337_DATA 0x00000000 +#define DDRSS0_PHY_1338_DATA 0x03000000 +#define DDRSS0_PHY_1339_DATA 0x00000000 +#define DDRSS0_PHY_1340_DATA 0x00000000 +#define DDRSS0_PHY_1341_DATA 0x00000000 +#define DDRSS0_PHY_1342_DATA 0x04102006 +#define DDRSS0_PHY_1343_DATA 0x00041020 +#define DDRSS0_PHY_1344_DATA 0x01C98C98 +#define DDRSS0_PHY_1345_DATA 0x3F400000 +#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS0_PHY_1347_DATA 0x0000001F +#define DDRSS0_PHY_1348_DATA 0x00000000 +#define DDRSS0_PHY_1349_DATA 0x00000000 +#define DDRSS0_PHY_1350_DATA 0x00000000 +#define DDRSS0_PHY_1351_DATA 0x00010000 +#define DDRSS0_PHY_1352_DATA 0x00000000 +#define DDRSS0_PHY_1353_DATA 0x00000000 +#define DDRSS0_PHY_1354_DATA 0x00000000 +#define DDRSS0_PHY_1355_DATA 0x00000000 +#define DDRSS0_PHY_1356_DATA 0x76543210 +#define DDRSS0_PHY_1357_DATA 0x00010198 +#define DDRSS0_PHY_1358_DATA 0x00000000 +#define DDRSS0_PHY_1359_DATA 0x00000000 +#define DDRSS0_PHY_1360_DATA 0x00000000 +#define DDRSS0_PHY_1361_DATA 0x00040700 +#define DDRSS0_PHY_1362_DATA 0x00000000 +#define DDRSS0_PHY_1363_DATA 0x00000000 +#define DDRSS0_PHY_1364_DATA 0x00000000 +#define DDRSS0_PHY_1365_DATA 0x00000000 +#define DDRSS0_PHY_1366_DATA 0x00000000 +#define DDRSS0_PHY_1367_DATA 0x00000002 +#define DDRSS0_PHY_1368_DATA 0x00000000 +#define DDRSS0_PHY_1369_DATA 0x00000000 +#define DDRSS0_PHY_1370_DATA 0x00000000 +#define DDRSS0_PHY_1371_DATA 0x00000000 +#define DDRSS0_PHY_1372_DATA 0x00000000 +#define DDRSS0_PHY_1373_DATA 0x00000000 +#define DDRSS0_PHY_1374_DATA 0x00080000 +#define DDRSS0_PHY_1375_DATA 0x000007FF +#define DDRSS0_PHY_1376_DATA 0x00000000 +#define DDRSS0_PHY_1377_DATA 0x00000000 +#define DDRSS0_PHY_1378_DATA 0x00000000 +#define DDRSS0_PHY_1379_DATA 0x00000000 +#define DDRSS0_PHY_1380_DATA 0x00000000 +#define DDRSS0_PHY_1381_DATA 0x00000000 +#define DDRSS0_PHY_1382_DATA 0x000FFFFF +#define DDRSS0_PHY_1383_DATA 0x000FFFFF +#define DDRSS0_PHY_1384_DATA 0x0000FFFF +#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS0_PHY_1386_DATA 0x030FFFFF +#define DDRSS0_PHY_1387_DATA 0x01FFFFFF +#define DDRSS0_PHY_1388_DATA 0x0000FFFF +#define DDRSS0_PHY_1389_DATA 0x00000000 +#define DDRSS0_PHY_1390_DATA 0x00000000 +#define DDRSS0_PHY_1391_DATA 0x00000000 +#define DDRSS0_PHY_1392_DATA 0x00000000 +#define DDRSS0_PHY_1393_DATA 0x0001F7C0 +#define DDRSS0_PHY_1394_DATA 0x00000003 +#define DDRSS0_PHY_1395_DATA 0x00000000 +#define DDRSS0_PHY_1396_DATA 0x00001142 +#define DDRSS0_PHY_1397_DATA 0x040207AB +#define DDRSS0_PHY_1398_DATA 0x01000080 +#define DDRSS0_PHY_1399_DATA 0x03900390 +#define DDRSS0_PHY_1400_DATA 0x03900390 +#define DDRSS0_PHY_1401_DATA 0x00000390 +#define DDRSS0_PHY_1402_DATA 0x00000390 +#define DDRSS0_PHY_1403_DATA 0x00000390 +#define DDRSS0_PHY_1404_DATA 0x00000390 +#define DDRSS0_PHY_1405_DATA 0x00000005 +#define DDRSS0_PHY_1406_DATA 0x01813FCC +#define DDRSS0_PHY_1407_DATA 0x000000CC +#define DDRSS0_PHY_1408_DATA 0x0C000DFF +#define DDRSS0_PHY_1409_DATA 0x30000DFF +#define DDRSS0_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1411_DATA 0x000100F0 +#define DDRSS0_PHY_1412_DATA 0x780DFFCC +#define DDRSS0_PHY_1413_DATA 0x00007E31 +#define DDRSS0_PHY_1414_DATA 0x000CBF11 +#define DDRSS0_PHY_1415_DATA 0x01990010 +#define DDRSS0_PHY_1416_DATA 0x000CBF11 +#define DDRSS0_PHY_1417_DATA 0x01990010 +#define DDRSS0_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1419_DATA 0x00EF00F0 +#define DDRSS0_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1421_DATA 0x01FF00F0 +#define DDRSS0_PHY_1422_DATA 0x20040006 + +#define DDRSS1_CTL_00_DATA 0x00000B00 +#define DDRSS1_CTL_01_DATA 0x00000000 +#define DDRSS1_CTL_02_DATA 0x00000000 +#define DDRSS1_CTL_03_DATA 0x00000000 +#define DDRSS1_CTL_04_DATA 0x00000000 +#define DDRSS1_CTL_05_DATA 0x00000000 +#define DDRSS1_CTL_06_DATA 0x00000000 +#define DDRSS1_CTL_07_DATA 0x00002AF8 +#define DDRSS1_CTL_08_DATA 0x0001ADAF +#define DDRSS1_CTL_09_DATA 0x00000005 +#define DDRSS1_CTL_10_DATA 0x0000006E +#define DDRSS1_CTL_11_DATA 0x000681C8 +#define DDRSS1_CTL_12_DATA 0x004111C9 +#define DDRSS1_CTL_13_DATA 0x00000005 +#define DDRSS1_CTL_14_DATA 0x000010A9 +#define DDRSS1_CTL_15_DATA 0x000681C8 +#define DDRSS1_CTL_16_DATA 0x004111C9 +#define DDRSS1_CTL_17_DATA 0x00000005 +#define DDRSS1_CTL_18_DATA 0x000010A9 +#define DDRSS1_CTL_19_DATA 0x01010000 +#define DDRSS1_CTL_20_DATA 0x01011001 +#define DDRSS1_CTL_21_DATA 0x02010000 +#define DDRSS1_CTL_22_DATA 0x00020100 +#define DDRSS1_CTL_23_DATA 0x0000000B +#define DDRSS1_CTL_24_DATA 0x0000001C +#define DDRSS1_CTL_25_DATA 0x00000000 +#define DDRSS1_CTL_26_DATA 0x00000000 +#define DDRSS1_CTL_27_DATA 0x03020200 +#define DDRSS1_CTL_28_DATA 0x00005656 +#define DDRSS1_CTL_29_DATA 0x00100000 +#define DDRSS1_CTL_30_DATA 0x00000000 +#define DDRSS1_CTL_31_DATA 0x00000000 +#define DDRSS1_CTL_32_DATA 0x00000000 +#define DDRSS1_CTL_33_DATA 0x00000000 +#define DDRSS1_CTL_34_DATA 0x040C0000 +#define DDRSS1_CTL_35_DATA 0x12501250 +#define DDRSS1_CTL_36_DATA 0x00050804 +#define DDRSS1_CTL_37_DATA 0x09040008 +#define DDRSS1_CTL_38_DATA 0x15000204 +#define DDRSS1_CTL_39_DATA 0x1760008B +#define DDRSS1_CTL_40_DATA 0x1500422B +#define DDRSS1_CTL_41_DATA 0x1760008B +#define DDRSS1_CTL_42_DATA 0x2000422B +#define DDRSS1_CTL_43_DATA 0x000A0A09 +#define DDRSS1_CTL_44_DATA 0x040003C5 +#define DDRSS1_CTL_45_DATA 0x1E161104 +#define DDRSS1_CTL_46_DATA 0x1000922C +#define DDRSS1_CTL_47_DATA 0x1E161110 +#define DDRSS1_CTL_48_DATA 0x1000922C +#define DDRSS1_CTL_49_DATA 0x02030410 +#define DDRSS1_CTL_50_DATA 0x2C060500 +#define DDRSS1_CTL_51_DATA 0x08292C29 +#define DDRSS1_CTL_52_DATA 0x14000E0A +#define DDRSS1_CTL_53_DATA 0x04010A0A +#define DDRSS1_CTL_54_DATA 0x01010004 +#define DDRSS1_CTL_55_DATA 0x0454540A +#define DDRSS1_CTL_56_DATA 0x04313104 +#define DDRSS1_CTL_57_DATA 0x00003131 +#define DDRSS1_CTL_58_DATA 0x00010100 +#define DDRSS1_CTL_59_DATA 0x03010000 +#define DDRSS1_CTL_60_DATA 0x00001508 +#define DDRSS1_CTL_61_DATA 0x00000068 +#define DDRSS1_CTL_62_DATA 0x0000032B +#define DDRSS1_CTL_63_DATA 0x00001035 +#define DDRSS1_CTL_64_DATA 0x0000032B +#define DDRSS1_CTL_65_DATA 0x00001035 +#define DDRSS1_CTL_66_DATA 0x00000005 +#define DDRSS1_CTL_67_DATA 0x00050000 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 +#define DDRSS1_CTL_71_DATA 0x00120103 +#define DDRSS1_CTL_72_DATA 0x00100005 +#define DDRSS1_CTL_73_DATA 0x2F080010 +#define DDRSS1_CTL_74_DATA 0x0505012F +#define DDRSS1_CTL_75_DATA 0x0401030A +#define DDRSS1_CTL_76_DATA 0x041E100B +#define DDRSS1_CTL_77_DATA 0x100B0401 +#define DDRSS1_CTL_78_DATA 0x0001041E +#define DDRSS1_CTL_79_DATA 0x00160016 +#define DDRSS1_CTL_80_DATA 0x033B033B +#define DDRSS1_CTL_81_DATA 0x033B033B +#define DDRSS1_CTL_82_DATA 0x03050505 +#define DDRSS1_CTL_83_DATA 0x03010303 +#define DDRSS1_CTL_84_DATA 0x200B100B +#define DDRSS1_CTL_85_DATA 0x04041004 +#define DDRSS1_CTL_86_DATA 0x200B100B +#define DDRSS1_CTL_87_DATA 0x04041004 +#define DDRSS1_CTL_88_DATA 0x03010000 +#define DDRSS1_CTL_89_DATA 0x00010000 +#define DDRSS1_CTL_90_DATA 0x00000000 +#define DDRSS1_CTL_91_DATA 0x00000000 +#define DDRSS1_CTL_92_DATA 0x01000000 +#define DDRSS1_CTL_93_DATA 0x80104002 +#define DDRSS1_CTL_94_DATA 0x00000000 +#define DDRSS1_CTL_95_DATA 0x00040005 +#define DDRSS1_CTL_96_DATA 0x00000000 +#define DDRSS1_CTL_97_DATA 0x00050000 +#define DDRSS1_CTL_98_DATA 0x00000004 +#define DDRSS1_CTL_99_DATA 0x00000000 +#define DDRSS1_CTL_100_DATA 0x00040005 +#define DDRSS1_CTL_101_DATA 0x00000000 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 +#define DDRSS1_CTL_107_DATA 0x00000000 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 +#define DDRSS1_CTL_114_DATA 0x00000000 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 +#define DDRSS1_CTL_121_DATA 0x00000000 +#define DDRSS1_CTL_122_DATA 0x00007173 +#define DDRSS1_CTL_123_DATA 0x00000000 +#define DDRSS1_CTL_124_DATA 0x00000000 +#define DDRSS1_CTL_125_DATA 0x00000000 +#define DDRSS1_CTL_126_DATA 0x00000000 +#define DDRSS1_CTL_127_DATA 0x00000000 +#define DDRSS1_CTL_128_DATA 0x00000000 +#define DDRSS1_CTL_129_DATA 0x00000000 +#define DDRSS1_CTL_130_DATA 0x00000000 +#define DDRSS1_CTL_131_DATA 0x0B030500 +#define DDRSS1_CTL_132_DATA 0x00040B04 +#define DDRSS1_CTL_133_DATA 0x0A090000 +#define DDRSS1_CTL_134_DATA 0x0A090701 +#define DDRSS1_CTL_135_DATA 0x0900000E +#define DDRSS1_CTL_136_DATA 0x0907010A +#define DDRSS1_CTL_137_DATA 0x00000E0A +#define DDRSS1_CTL_138_DATA 0x07010A09 +#define DDRSS1_CTL_139_DATA 0x000E0A09 +#define DDRSS1_CTL_140_DATA 0x07000401 +#define DDRSS1_CTL_141_DATA 0x00000000 +#define DDRSS1_CTL_142_DATA 0x00000000 +#define DDRSS1_CTL_143_DATA 0x00000000 +#define DDRSS1_CTL_144_DATA 0x00000000 +#define DDRSS1_CTL_145_DATA 0x00000000 +#define DDRSS1_CTL_146_DATA 0x00000000 +#define DDRSS1_CTL_147_DATA 0x00000000 +#define DDRSS1_CTL_148_DATA 0x08080000 +#define DDRSS1_CTL_149_DATA 0x01000000 +#define DDRSS1_CTL_150_DATA 0x800000C0 +#define DDRSS1_CTL_151_DATA 0x800000C0 +#define DDRSS1_CTL_152_DATA 0x800000C0 +#define DDRSS1_CTL_153_DATA 0x00000000 +#define DDRSS1_CTL_154_DATA 0x00001500 +#define DDRSS1_CTL_155_DATA 0x00000000 +#define DDRSS1_CTL_156_DATA 0x00000001 +#define DDRSS1_CTL_157_DATA 0x00000002 +#define DDRSS1_CTL_158_DATA 0x0000100E +#define DDRSS1_CTL_159_DATA 0x00000000 +#define DDRSS1_CTL_160_DATA 0x00000000 +#define DDRSS1_CTL_161_DATA 0x00000000 +#define DDRSS1_CTL_162_DATA 0x00000000 +#define DDRSS1_CTL_163_DATA 0x00000000 +#define DDRSS1_CTL_164_DATA 0x000B0000 +#define DDRSS1_CTL_165_DATA 0x000E0006 +#define DDRSS1_CTL_166_DATA 0x000E0404 +#define DDRSS1_CTL_167_DATA 0x00D601AB +#define DDRSS1_CTL_168_DATA 0x10100216 +#define DDRSS1_CTL_169_DATA 0x01AB0216 +#define DDRSS1_CTL_170_DATA 0x021600D6 +#define DDRSS1_CTL_171_DATA 0x02161010 +#define DDRSS1_CTL_172_DATA 0x00000000 +#define DDRSS1_CTL_173_DATA 0x00000000 +#define DDRSS1_CTL_174_DATA 0x00000000 +#define DDRSS1_CTL_175_DATA 0x3FF40084 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x35000000 +#define DDRSS1_CTL_179_DATA 0x27270035 +#define DDRSS1_CTL_180_DATA 0x0F0F0000 +#define DDRSS1_CTL_181_DATA 0x16000000 +#define DDRSS1_CTL_182_DATA 0x00841616 +#define DDRSS1_CTL_183_DATA 0x3FF43FF4 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 +#define DDRSS1_CTL_185_DATA 0x00000000 +#define DDRSS1_CTL_186_DATA 0x00353500 +#define DDRSS1_CTL_187_DATA 0x00002727 +#define DDRSS1_CTL_188_DATA 0x00000F0F +#define DDRSS1_CTL_189_DATA 0x16161600 +#define DDRSS1_CTL_190_DATA 0x00000020 +#define DDRSS1_CTL_191_DATA 0x01000000 +#define DDRSS1_CTL_192_DATA 0x00000001 +#define DDRSS1_CTL_193_DATA 0x00000000 +#define DDRSS1_CTL_194_DATA 0x01000000 +#define DDRSS1_CTL_195_DATA 0x00000001 +#define DDRSS1_CTL_196_DATA 0x00000000 +#define DDRSS1_CTL_197_DATA 0x00000000 +#define DDRSS1_CTL_198_DATA 0x00000000 +#define DDRSS1_CTL_199_DATA 0x00000000 +#define DDRSS1_CTL_200_DATA 0x00000000 +#define DDRSS1_CTL_201_DATA 0x00000000 +#define DDRSS1_CTL_202_DATA 0x00000000 +#define DDRSS1_CTL_203_DATA 0x00000000 +#define DDRSS1_CTL_204_DATA 0x00000000 +#define DDRSS1_CTL_205_DATA 0x00000000 +#define DDRSS1_CTL_206_DATA 0x02000000 +#define DDRSS1_CTL_207_DATA 0x01080101 +#define DDRSS1_CTL_208_DATA 0x00000000 +#define DDRSS1_CTL_209_DATA 0x00000000 +#define DDRSS1_CTL_210_DATA 0x00000000 +#define DDRSS1_CTL_211_DATA 0x00000000 +#define DDRSS1_CTL_212_DATA 0x00000000 +#define DDRSS1_CTL_213_DATA 0x00000000 +#define DDRSS1_CTL_214_DATA 0x00000000 +#define DDRSS1_CTL_215_DATA 0x00000000 +#define DDRSS1_CTL_216_DATA 0x00000000 +#define DDRSS1_CTL_217_DATA 0x00000000 +#define DDRSS1_CTL_218_DATA 0x00000000 +#define DDRSS1_CTL_219_DATA 0x00000000 +#define DDRSS1_CTL_220_DATA 0x00000000 +#define DDRSS1_CTL_221_DATA 0x00000000 +#define DDRSS1_CTL_222_DATA 0x00001000 +#define DDRSS1_CTL_223_DATA 0x006403E8 +#define DDRSS1_CTL_224_DATA 0x00000000 +#define DDRSS1_CTL_225_DATA 0x00000000 +#define DDRSS1_CTL_226_DATA 0x00000000 +#define DDRSS1_CTL_227_DATA 0x15110000 +#define DDRSS1_CTL_228_DATA 0x00040C18 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 +#define DDRSS1_CTL_231_DATA 0x00000000 +#define DDRSS1_CTL_232_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 +#define DDRSS1_CTL_235_DATA 0x00000000 +#define DDRSS1_CTL_236_DATA 0x00000000 +#define DDRSS1_CTL_237_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 +#define DDRSS1_CTL_240_DATA 0x00000000 +#define DDRSS1_CTL_241_DATA 0x00000000 +#define DDRSS1_CTL_242_DATA 0x00030000 +#define DDRSS1_CTL_243_DATA 0x00000000 +#define DDRSS1_CTL_244_DATA 0x00000000 +#define DDRSS1_CTL_245_DATA 0x00000000 +#define DDRSS1_CTL_246_DATA 0x00000000 +#define DDRSS1_CTL_247_DATA 0x00000000 +#define DDRSS1_CTL_248_DATA 0x00000000 +#define DDRSS1_CTL_249_DATA 0x00000000 +#define DDRSS1_CTL_250_DATA 0x00000000 +#define DDRSS1_CTL_251_DATA 0x00000000 +#define DDRSS1_CTL_252_DATA 0x00000000 +#define DDRSS1_CTL_253_DATA 0x00000000 +#define DDRSS1_CTL_254_DATA 0x00000000 +#define DDRSS1_CTL_255_DATA 0x00000000 +#define DDRSS1_CTL_256_DATA 0x00000000 +#define DDRSS1_CTL_257_DATA 0x01000200 +#define DDRSS1_CTL_258_DATA 0x00370040 +#define DDRSS1_CTL_259_DATA 0x00020008 +#define DDRSS1_CTL_260_DATA 0x00400100 +#define DDRSS1_CTL_261_DATA 0x00400855 +#define DDRSS1_CTL_262_DATA 0x01000200 +#define DDRSS1_CTL_263_DATA 0x08550040 +#define DDRSS1_CTL_264_DATA 0x00000040 +#define DDRSS1_CTL_265_DATA 0x006B0003 +#define DDRSS1_CTL_266_DATA 0x0100006B +#define DDRSS1_CTL_267_DATA 0x03030303 +#define DDRSS1_CTL_268_DATA 0x00000000 +#define DDRSS1_CTL_269_DATA 0x00000202 +#define DDRSS1_CTL_270_DATA 0x00001FFF +#define DDRSS1_CTL_271_DATA 0x3FFF2000 +#define DDRSS1_CTL_272_DATA 0x03FF0000 +#define DDRSS1_CTL_273_DATA 0x000103FF +#define DDRSS1_CTL_274_DATA 0x0FFF0B00 +#define DDRSS1_CTL_275_DATA 0x01010001 +#define DDRSS1_CTL_276_DATA 0x01010101 +#define DDRSS1_CTL_277_DATA 0x01180101 +#define DDRSS1_CTL_278_DATA 0x00030000 +#define DDRSS1_CTL_279_DATA 0x00000000 +#define DDRSS1_CTL_280_DATA 0x00000000 +#define DDRSS1_CTL_281_DATA 0x00000000 +#define DDRSS1_CTL_282_DATA 0x00000000 +#define DDRSS1_CTL_283_DATA 0x00000000 +#define DDRSS1_CTL_284_DATA 0x00000000 +#define DDRSS1_CTL_285_DATA 0x00000000 +#define DDRSS1_CTL_286_DATA 0x00040101 +#define DDRSS1_CTL_287_DATA 0x04010100 +#define DDRSS1_CTL_288_DATA 0x00000000 +#define DDRSS1_CTL_289_DATA 0x00000000 +#define DDRSS1_CTL_290_DATA 0x03030300 +#define DDRSS1_CTL_291_DATA 0x00010101 +#define DDRSS1_CTL_292_DATA 0x00000000 +#define DDRSS1_CTL_293_DATA 0x00000000 +#define DDRSS1_CTL_294_DATA 0x00000000 +#define DDRSS1_CTL_295_DATA 0x00000000 +#define DDRSS1_CTL_296_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF +#define DDRSS1_CTL_299_DATA 0x00000000 +#define DDRSS1_CTL_300_DATA 0x00000000 +#define DDRSS1_CTL_301_DATA 0x00000000 +#define DDRSS1_CTL_302_DATA 0x00000000 +#define DDRSS1_CTL_303_DATA 0x00000000 +#define DDRSS1_CTL_304_DATA 0x00000000 +#define DDRSS1_CTL_305_DATA 0x00000000 +#define DDRSS1_CTL_306_DATA 0x00000000 +#define DDRSS1_CTL_307_DATA 0x00000000 +#define DDRSS1_CTL_308_DATA 0x00000000 +#define DDRSS1_CTL_309_DATA 0x00000000 +#define DDRSS1_CTL_310_DATA 0x00000000 +#define DDRSS1_CTL_311_DATA 0x00000000 +#define DDRSS1_CTL_312_DATA 0x00000000 +#define DDRSS1_CTL_313_DATA 0x01000000 +#define DDRSS1_CTL_314_DATA 0x00020201 +#define DDRSS1_CTL_315_DATA 0x01000101 +#define DDRSS1_CTL_316_DATA 0x01010001 +#define DDRSS1_CTL_317_DATA 0x00010101 +#define DDRSS1_CTL_318_DATA 0x050A0A03 +#define DDRSS1_CTL_319_DATA 0x10082323 +#define DDRSS1_CTL_320_DATA 0x00090310 +#define DDRSS1_CTL_321_DATA 0x0B0C030F +#define DDRSS1_CTL_322_DATA 0x0B0C0306 +#define DDRSS1_CTL_323_DATA 0x0C090006 +#define DDRSS1_CTL_324_DATA 0x0100000C +#define DDRSS1_CTL_325_DATA 0x08040801 +#define DDRSS1_CTL_326_DATA 0x00000004 +#define DDRSS1_CTL_327_DATA 0x00000000 +#define DDRSS1_CTL_328_DATA 0x00010000 +#define DDRSS1_CTL_329_DATA 0x00280D00 +#define DDRSS1_CTL_330_DATA 0x00000001 +#define DDRSS1_CTL_331_DATA 0x00030001 +#define DDRSS1_CTL_332_DATA 0x00000000 +#define DDRSS1_CTL_333_DATA 0x00000000 +#define DDRSS1_CTL_334_DATA 0x00000000 +#define DDRSS1_CTL_335_DATA 0x00000000 +#define DDRSS1_CTL_336_DATA 0x00000000 +#define DDRSS1_CTL_337_DATA 0x00000000 +#define DDRSS1_CTL_338_DATA 0x00000000 +#define DDRSS1_CTL_339_DATA 0x00000000 +#define DDRSS1_CTL_340_DATA 0x01000000 +#define DDRSS1_CTL_341_DATA 0x00000001 +#define DDRSS1_CTL_342_DATA 0x00010100 +#define DDRSS1_CTL_343_DATA 0x03030000 +#define DDRSS1_CTL_344_DATA 0x00000000 +#define DDRSS1_CTL_345_DATA 0x00000000 +#define DDRSS1_CTL_346_DATA 0x00000000 +#define DDRSS1_CTL_347_DATA 0x00000000 +#define DDRSS1_CTL_348_DATA 0x00000000 +#define DDRSS1_CTL_349_DATA 0x00000000 +#define DDRSS1_CTL_350_DATA 0x00000000 +#define DDRSS1_CTL_351_DATA 0x00000000 +#define DDRSS1_CTL_352_DATA 0x00000000 +#define DDRSS1_CTL_353_DATA 0x00000000 +#define DDRSS1_CTL_354_DATA 0x00000000 +#define DDRSS1_CTL_355_DATA 0x00000000 +#define DDRSS1_CTL_356_DATA 0x00000000 +#define DDRSS1_CTL_357_DATA 0x00000000 +#define DDRSS1_CTL_358_DATA 0x00000000 +#define DDRSS1_CTL_359_DATA 0x00000000 +#define DDRSS1_CTL_360_DATA 0x000556AA +#define DDRSS1_CTL_361_DATA 0x000AAAAA +#define DDRSS1_CTL_362_DATA 0x000AA955 +#define DDRSS1_CTL_363_DATA 0x00055555 +#define DDRSS1_CTL_364_DATA 0x000B3133 +#define DDRSS1_CTL_365_DATA 0x0004CD33 +#define DDRSS1_CTL_366_DATA 0x0004CECC +#define DDRSS1_CTL_367_DATA 0x000B32CC +#define DDRSS1_CTL_368_DATA 0x00010300 +#define DDRSS1_CTL_369_DATA 0x03000100 +#define DDRSS1_CTL_370_DATA 0x00000000 +#define DDRSS1_CTL_371_DATA 0x00000000 +#define DDRSS1_CTL_372_DATA 0x00000000 +#define DDRSS1_CTL_373_DATA 0x00000000 +#define DDRSS1_CTL_374_DATA 0x00000000 +#define DDRSS1_CTL_375_DATA 0x00000000 +#define DDRSS1_CTL_376_DATA 0x00000000 +#define DDRSS1_CTL_377_DATA 0x00010000 +#define DDRSS1_CTL_378_DATA 0x00000404 +#define DDRSS1_CTL_379_DATA 0x00000000 +#define DDRSS1_CTL_380_DATA 0x00000000 +#define DDRSS1_CTL_381_DATA 0x00000000 +#define DDRSS1_CTL_382_DATA 0x00000000 +#define DDRSS1_CTL_383_DATA 0x00000000 +#define DDRSS1_CTL_384_DATA 0x00000000 +#define DDRSS1_CTL_385_DATA 0x00000000 +#define DDRSS1_CTL_386_DATA 0x00000000 +#define DDRSS1_CTL_387_DATA 0x3A3A1B00 +#define DDRSS1_CTL_388_DATA 0x000A0000 +#define DDRSS1_CTL_389_DATA 0x000000C6 +#define DDRSS1_CTL_390_DATA 0x00000200 +#define DDRSS1_CTL_391_DATA 0x00000200 +#define DDRSS1_CTL_392_DATA 0x00000200 +#define DDRSS1_CTL_393_DATA 0x00000200 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC +#define DDRSS1_CTL_396_DATA 0x00000204 +#define DDRSS1_CTL_397_DATA 0x0000206A +#define DDRSS1_CTL_398_DATA 0x00000200 +#define DDRSS1_CTL_399_DATA 0x00000200 +#define DDRSS1_CTL_400_DATA 0x00000200 +#define DDRSS1_CTL_401_DATA 0x00000200 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A +#define DDRSS1_CTL_406_DATA 0x00000200 +#define DDRSS1_CTL_407_DATA 0x00000200 +#define DDRSS1_CTL_408_DATA 0x00000200 +#define DDRSS1_CTL_409_DATA 0x00000200 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 +#define DDRSS1_CTL_413_DATA 0x03030202 +#define DDRSS1_CTL_414_DATA 0x00000022 +#define DDRSS1_CTL_415_DATA 0x00000000 +#define DDRSS1_CTL_416_DATA 0x00000000 +#define DDRSS1_CTL_417_DATA 0x00001403 +#define DDRSS1_CTL_418_DATA 0x000007D0 +#define DDRSS1_CTL_419_DATA 0x00000000 +#define DDRSS1_CTL_420_DATA 0x00000000 +#define DDRSS1_CTL_421_DATA 0x00030000 +#define DDRSS1_CTL_422_DATA 0x0007001F +#define DDRSS1_CTL_423_DATA 0x001B0033 +#define DDRSS1_CTL_424_DATA 0x001B0033 +#define DDRSS1_CTL_425_DATA 0x00000000 +#define DDRSS1_CTL_426_DATA 0x00000000 +#define DDRSS1_CTL_427_DATA 0x02000000 +#define DDRSS1_CTL_428_DATA 0x01000404 +#define DDRSS1_CTL_429_DATA 0x0B220B22 +#define DDRSS1_CTL_430_DATA 0x00000105 +#define DDRSS1_CTL_431_DATA 0x00010101 +#define DDRSS1_CTL_432_DATA 0x00010101 +#define DDRSS1_CTL_433_DATA 0x00010001 +#define DDRSS1_CTL_434_DATA 0x00000101 +#define DDRSS1_CTL_435_DATA 0x02000201 +#define DDRSS1_CTL_436_DATA 0x02010000 +#define DDRSS1_CTL_437_DATA 0x00000200 +#define DDRSS1_CTL_438_DATA 0x28060000 +#define DDRSS1_CTL_439_DATA 0x00000128 +#define DDRSS1_CTL_440_DATA 0xFFFFFFFF +#define DDRSS1_CTL_441_DATA 0xFFFFFFFF +#define DDRSS1_CTL_442_DATA 0x00000000 +#define DDRSS1_CTL_443_DATA 0x00000000 +#define DDRSS1_CTL_444_DATA 0x00000000 +#define DDRSS1_CTL_445_DATA 0x00000000 +#define DDRSS1_CTL_446_DATA 0x00000000 +#define DDRSS1_CTL_447_DATA 0x00000000 +#define DDRSS1_CTL_448_DATA 0x00000000 +#define DDRSS1_CTL_449_DATA 0x00000000 +#define DDRSS1_CTL_450_DATA 0x00000000 +#define DDRSS1_CTL_451_DATA 0x00000000 +#define DDRSS1_CTL_452_DATA 0x00000000 +#define DDRSS1_CTL_453_DATA 0x00000000 +#define DDRSS1_CTL_454_DATA 0x00000000 +#define DDRSS1_CTL_455_DATA 0x00000000 +#define DDRSS1_CTL_456_DATA 0x00000000 +#define DDRSS1_CTL_457_DATA 0x00000000 +#define DDRSS1_CTL_458_DATA 0x00000000 + +#define DDRSS1_PI_00_DATA 0x00000B00 +#define DDRSS1_PI_01_DATA 0x00000000 +#define DDRSS1_PI_02_DATA 0x00000000 +#define DDRSS1_PI_03_DATA 0x00000000 +#define DDRSS1_PI_04_DATA 0x00000000 +#define DDRSS1_PI_05_DATA 0x00000101 +#define DDRSS1_PI_06_DATA 0x00640000 +#define DDRSS1_PI_07_DATA 0x00000001 +#define DDRSS1_PI_08_DATA 0x00000000 +#define DDRSS1_PI_09_DATA 0x00000000 +#define DDRSS1_PI_10_DATA 0x00000000 +#define DDRSS1_PI_11_DATA 0x00000000 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 +#define DDRSS1_PI_14_DATA 0x0800000F +#define DDRSS1_PI_15_DATA 0x00000103 +#define DDRSS1_PI_16_DATA 0x00000005 +#define DDRSS1_PI_17_DATA 0x00000000 +#define DDRSS1_PI_18_DATA 0x00000000 +#define DDRSS1_PI_19_DATA 0x00000000 +#define DDRSS1_PI_20_DATA 0x00000000 +#define DDRSS1_PI_21_DATA 0x00000000 +#define DDRSS1_PI_22_DATA 0x00000000 +#define DDRSS1_PI_23_DATA 0x00000000 +#define DDRSS1_PI_24_DATA 0x00000000 +#define DDRSS1_PI_25_DATA 0x00000000 +#define DDRSS1_PI_26_DATA 0x00010100 +#define DDRSS1_PI_27_DATA 0x00280A00 +#define DDRSS1_PI_28_DATA 0x00000000 +#define DDRSS1_PI_29_DATA 0x0F000000 +#define DDRSS1_PI_30_DATA 0x00003200 +#define DDRSS1_PI_31_DATA 0x00000000 +#define DDRSS1_PI_32_DATA 0x00000000 +#define DDRSS1_PI_33_DATA 0x01010102 +#define DDRSS1_PI_34_DATA 0x00000000 +#define DDRSS1_PI_35_DATA 0x000000AA +#define DDRSS1_PI_36_DATA 0x00000055 +#define DDRSS1_PI_37_DATA 0x000000B5 +#define DDRSS1_PI_38_DATA 0x0000004A +#define DDRSS1_PI_39_DATA 0x00000056 +#define DDRSS1_PI_40_DATA 0x000000A9 +#define DDRSS1_PI_41_DATA 0x000000A9 +#define DDRSS1_PI_42_DATA 0x000000B5 +#define DDRSS1_PI_43_DATA 0x00000000 +#define DDRSS1_PI_44_DATA 0x00000000 +#define DDRSS1_PI_45_DATA 0x000F0F00 +#define DDRSS1_PI_46_DATA 0x0000001B +#define DDRSS1_PI_47_DATA 0x000007D0 +#define DDRSS1_PI_48_DATA 0x00000300 +#define DDRSS1_PI_49_DATA 0x00000000 +#define DDRSS1_PI_50_DATA 0x00000000 +#define DDRSS1_PI_51_DATA 0x01000000 +#define DDRSS1_PI_52_DATA 0x00010101 +#define DDRSS1_PI_53_DATA 0x00000000 +#define DDRSS1_PI_54_DATA 0x00030000 +#define DDRSS1_PI_55_DATA 0x0F000000 +#define DDRSS1_PI_56_DATA 0x00000017 +#define DDRSS1_PI_57_DATA 0x00000000 +#define DDRSS1_PI_58_DATA 0x00000000 +#define DDRSS1_PI_59_DATA 0x00000000 +#define DDRSS1_PI_60_DATA 0x0A0A140A +#define DDRSS1_PI_61_DATA 0x10020201 +#define DDRSS1_PI_62_DATA 0x00020805 +#define DDRSS1_PI_63_DATA 0x01000404 +#define DDRSS1_PI_64_DATA 0x00000000 +#define DDRSS1_PI_65_DATA 0x00000000 +#define DDRSS1_PI_66_DATA 0x00000100 +#define DDRSS1_PI_67_DATA 0x0002020F +#define DDRSS1_PI_68_DATA 0x00340000 +#define DDRSS1_PI_69_DATA 0x00000000 +#define DDRSS1_PI_70_DATA 0x00000000 +#define DDRSS1_PI_71_DATA 0x0000FFFF +#define DDRSS1_PI_72_DATA 0x01000000 +#define DDRSS1_PI_73_DATA 0x00080000 +#define DDRSS1_PI_74_DATA 0x02000200 +#define DDRSS1_PI_75_DATA 0x01000100 +#define DDRSS1_PI_76_DATA 0x01000000 +#define DDRSS1_PI_77_DATA 0x02000200 +#define DDRSS1_PI_78_DATA 0x00000200 +#define DDRSS1_PI_79_DATA 0x00000000 +#define DDRSS1_PI_80_DATA 0x00000000 +#define DDRSS1_PI_81_DATA 0x00000000 +#define DDRSS1_PI_82_DATA 0x00000000 +#define DDRSS1_PI_83_DATA 0x00000000 +#define DDRSS1_PI_84_DATA 0x00000000 +#define DDRSS1_PI_85_DATA 0x00000000 +#define DDRSS1_PI_86_DATA 0x00000000 +#define DDRSS1_PI_87_DATA 0x00000000 +#define DDRSS1_PI_88_DATA 0x00000000 +#define DDRSS1_PI_89_DATA 0x00000000 +#define DDRSS1_PI_90_DATA 0x00000000 +#define DDRSS1_PI_91_DATA 0x00000400 +#define DDRSS1_PI_92_DATA 0x02010000 +#define DDRSS1_PI_93_DATA 0x00080003 +#define DDRSS1_PI_94_DATA 0x00080000 +#define DDRSS1_PI_95_DATA 0x00000001 +#define DDRSS1_PI_96_DATA 0x00000000 +#define DDRSS1_PI_97_DATA 0x0000AA00 +#define DDRSS1_PI_98_DATA 0x00000000 +#define DDRSS1_PI_99_DATA 0x00000000 +#define DDRSS1_PI_100_DATA 0x00010000 +#define DDRSS1_PI_101_DATA 0x00000000 +#define DDRSS1_PI_102_DATA 0x00000000 +#define DDRSS1_PI_103_DATA 0x00000000 +#define DDRSS1_PI_104_DATA 0x00000000 +#define DDRSS1_PI_105_DATA 0x00000000 +#define DDRSS1_PI_106_DATA 0x00000000 +#define DDRSS1_PI_107_DATA 0x00000000 +#define DDRSS1_PI_108_DATA 0x00000000 +#define DDRSS1_PI_109_DATA 0x00000000 +#define DDRSS1_PI_110_DATA 0x00000000 +#define DDRSS1_PI_111_DATA 0x00000000 +#define DDRSS1_PI_112_DATA 0x00000000 +#define DDRSS1_PI_113_DATA 0x00000000 +#define DDRSS1_PI_114_DATA 0x00000000 +#define DDRSS1_PI_115_DATA 0x00000000 +#define DDRSS1_PI_116_DATA 0x00000000 +#define DDRSS1_PI_117_DATA 0x00000000 +#define DDRSS1_PI_118_DATA 0x00000000 +#define DDRSS1_PI_119_DATA 0x00000000 +#define DDRSS1_PI_120_DATA 0x00000000 +#define DDRSS1_PI_121_DATA 0x00000000 +#define DDRSS1_PI_122_DATA 0x00000000 +#define DDRSS1_PI_123_DATA 0x00000000 +#define DDRSS1_PI_124_DATA 0x00000000 +#define DDRSS1_PI_125_DATA 0x00000008 +#define DDRSS1_PI_126_DATA 0x00000000 +#define DDRSS1_PI_127_DATA 0x00000000 +#define DDRSS1_PI_128_DATA 0x00000000 +#define DDRSS1_PI_129_DATA 0x00000000 +#define DDRSS1_PI_130_DATA 0x00000000 +#define DDRSS1_PI_131_DATA 0x00000000 +#define DDRSS1_PI_132_DATA 0x00000000 +#define DDRSS1_PI_133_DATA 0x00000000 +#define DDRSS1_PI_134_DATA 0x00000002 +#define DDRSS1_PI_135_DATA 0x00000000 +#define DDRSS1_PI_136_DATA 0x00000000 +#define DDRSS1_PI_137_DATA 0x0000000A +#define DDRSS1_PI_138_DATA 0x00000019 +#define DDRSS1_PI_139_DATA 0x00000100 +#define DDRSS1_PI_140_DATA 0x00000000 +#define DDRSS1_PI_141_DATA 0x00000000 +#define DDRSS1_PI_142_DATA 0x00000000 +#define DDRSS1_PI_143_DATA 0x00000000 +#define DDRSS1_PI_144_DATA 0x01000000 +#define DDRSS1_PI_145_DATA 0x00010003 +#define DDRSS1_PI_146_DATA 0x02000101 +#define DDRSS1_PI_147_DATA 0x01030001 +#define DDRSS1_PI_148_DATA 0x00010400 +#define DDRSS1_PI_149_DATA 0x06000105 +#define DDRSS1_PI_150_DATA 0x01070001 +#define DDRSS1_PI_151_DATA 0x00000000 +#define DDRSS1_PI_152_DATA 0x00000000 +#define DDRSS1_PI_153_DATA 0x00000000 +#define DDRSS1_PI_154_DATA 0x00010001 +#define DDRSS1_PI_155_DATA 0x00000000 +#define DDRSS1_PI_156_DATA 0x00000000 +#define DDRSS1_PI_157_DATA 0x00000000 +#define DDRSS1_PI_158_DATA 0x00000000 +#define DDRSS1_PI_159_DATA 0x00000401 +#define DDRSS1_PI_160_DATA 0x00000000 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 +#define DDRSS1_PI_164_DATA 0x00000034 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 +#define DDRSS1_PI_167_DATA 0x02000200 +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 +#define DDRSS1_PI_171_DATA 0x0000032B +#define DDRSS1_PI_172_DATA 0x00001035 +#define DDRSS1_PI_173_DATA 0x0000032B +#define DDRSS1_PI_174_DATA 0x04001035 +#define DDRSS1_PI_175_DATA 0x01010404 +#define DDRSS1_PI_176_DATA 0x00001500 +#define DDRSS1_PI_177_DATA 0x00150015 +#define DDRSS1_PI_178_DATA 0x01000100 +#define DDRSS1_PI_179_DATA 0x00000100 +#define DDRSS1_PI_180_DATA 0x00000000 +#define DDRSS1_PI_181_DATA 0x01010101 +#define DDRSS1_PI_182_DATA 0x00000000 +#define DDRSS1_PI_183_DATA 0x00000000 +#define DDRSS1_PI_184_DATA 0x00000000 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 +#define DDRSS1_PI_187_DATA 0x00040402 +#define DDRSS1_PI_188_DATA 0x000D0035 +#define DDRSS1_PI_189_DATA 0x00218049 +#define DDRSS1_PI_190_DATA 0x00218049 +#define DDRSS1_PI_191_DATA 0x01000101 +#define DDRSS1_PI_192_DATA 0x0004000E +#define DDRSS1_PI_193_DATA 0x00040216 +#define DDRSS1_PI_194_DATA 0x01000216 +#define DDRSS1_PI_195_DATA 0x000F000F +#define DDRSS1_PI_196_DATA 0x02170100 +#define DDRSS1_PI_197_DATA 0x01000217 +#define DDRSS1_PI_198_DATA 0x02170217 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B +#define DDRSS1_PI_201_DATA 0x0A070601 +#define DDRSS1_PI_202_DATA 0x1F130A0D +#define DDRSS1_PI_203_DATA 0x1F130A14 +#define DDRSS1_PI_204_DATA 0x0000C014 +#define DDRSS1_PI_205_DATA 0x00C01000 +#define DDRSS1_PI_206_DATA 0x00C01000 +#define DDRSS1_PI_207_DATA 0x00021000 +#define DDRSS1_PI_208_DATA 0x0024000E +#define DDRSS1_PI_209_DATA 0x00240216 +#define DDRSS1_PI_210_DATA 0x00110216 +#define DDRSS1_PI_211_DATA 0x32000056 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 +#define DDRSS1_PI_214_DATA 0x03013212 +#define DDRSS1_PI_215_DATA 0x00003600 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 +#define DDRSS1_PI_220_DATA 0x0A032001 +#define DDRSS1_PI_221_DATA 0x2C31110A +#define DDRSS1_PI_222_DATA 0x00002918 +#define DDRSS1_PI_223_DATA 0x6000838E +#define DDRSS1_PI_224_DATA 0x1E202008 +#define DDRSS1_PI_225_DATA 0x2C311116 +#define DDRSS1_PI_226_DATA 0x00002918 +#define DDRSS1_PI_227_DATA 0x6000838E +#define DDRSS1_PI_228_DATA 0x1E202008 +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 +#define DDRSS1_PI_235_DATA 0x033B0016 +#define DDRSS1_PI_236_DATA 0x0303033B +#define DDRSS1_PI_237_DATA 0x002AF803 +#define DDRSS1_PI_238_DATA 0x0001ADAF +#define DDRSS1_PI_239_DATA 0x00000005 +#define DDRSS1_PI_240_DATA 0x0000006E +#define DDRSS1_PI_241_DATA 0x00000016 +#define DDRSS1_PI_242_DATA 0x000681C8 +#define DDRSS1_PI_243_DATA 0x0001ADAF +#define DDRSS1_PI_244_DATA 0x00000005 +#define DDRSS1_PI_245_DATA 0x000010A9 +#define DDRSS1_PI_246_DATA 0x0000033B +#define DDRSS1_PI_247_DATA 0x000681C8 +#define DDRSS1_PI_248_DATA 0x0001ADAF +#define DDRSS1_PI_249_DATA 0x00000005 +#define DDRSS1_PI_250_DATA 0x000010A9 +#define DDRSS1_PI_251_DATA 0x0100033B +#define DDRSS1_PI_252_DATA 0x00370040 +#define DDRSS1_PI_253_DATA 0x00010008 +#define DDRSS1_PI_254_DATA 0x08550040 +#define DDRSS1_PI_255_DATA 0x00010040 +#define DDRSS1_PI_256_DATA 0x08550040 +#define DDRSS1_PI_257_DATA 0x00000340 +#define DDRSS1_PI_258_DATA 0x006B006B +#define DDRSS1_PI_259_DATA 0x08040404 +#define DDRSS1_PI_260_DATA 0x00000055 +#define DDRSS1_PI_261_DATA 0x55083C5A +#define DDRSS1_PI_262_DATA 0x5A000000 +#define DDRSS1_PI_263_DATA 0x0055083C +#define DDRSS1_PI_264_DATA 0x3C5A0000 +#define DDRSS1_PI_265_DATA 0x00005508 +#define DDRSS1_PI_266_DATA 0x0C3C5A00 +#define DDRSS1_PI_267_DATA 0x080F0E0D +#define DDRSS1_PI_268_DATA 0x000B0A09 +#define DDRSS1_PI_269_DATA 0x00030201 +#define DDRSS1_PI_270_DATA 0x01000000 +#define DDRSS1_PI_271_DATA 0x04020201 +#define DDRSS1_PI_272_DATA 0x00080804 +#define DDRSS1_PI_273_DATA 0x00000000 +#define DDRSS1_PI_274_DATA 0x00000000 +#define DDRSS1_PI_275_DATA 0x00F30084 +#define DDRSS1_PI_276_DATA 0x00160000 +#define DDRSS1_PI_277_DATA 0x35F33FF4 +#define DDRSS1_PI_278_DATA 0x00160F27 +#define DDRSS1_PI_279_DATA 0x35F33FF4 +#define DDRSS1_PI_280_DATA 0x00160F27 +#define DDRSS1_PI_281_DATA 0x00F30084 +#define DDRSS1_PI_282_DATA 0x00160000 +#define DDRSS1_PI_283_DATA 0x35F33FF4 +#define DDRSS1_PI_284_DATA 0x00160F27 +#define DDRSS1_PI_285_DATA 0x35F33FF4 +#define DDRSS1_PI_286_DATA 0x00160F27 +#define DDRSS1_PI_287_DATA 0x00F30084 +#define DDRSS1_PI_288_DATA 0x00160000 +#define DDRSS1_PI_289_DATA 0x35F33FF4 +#define DDRSS1_PI_290_DATA 0x00160F27 +#define DDRSS1_PI_291_DATA 0x35F33FF4 +#define DDRSS1_PI_292_DATA 0x00160F27 +#define DDRSS1_PI_293_DATA 0x00F30084 +#define DDRSS1_PI_294_DATA 0x00160000 +#define DDRSS1_PI_295_DATA 0x35F33FF4 +#define DDRSS1_PI_296_DATA 0x00160F27 +#define DDRSS1_PI_297_DATA 0x35F33FF4 +#define DDRSS1_PI_298_DATA 0x00160F27 +#define DDRSS1_PI_299_DATA 0x00000000 + +#define DDRSS1_PHY_00_DATA 0x000004F0 +#define DDRSS1_PHY_01_DATA 0x00000000 +#define DDRSS1_PHY_02_DATA 0x00030200 +#define DDRSS1_PHY_03_DATA 0x00000000 +#define DDRSS1_PHY_04_DATA 0x00000000 +#define DDRSS1_PHY_05_DATA 0x01030000 +#define DDRSS1_PHY_06_DATA 0x00010000 +#define DDRSS1_PHY_07_DATA 0x01030004 +#define DDRSS1_PHY_08_DATA 0x01000000 +#define DDRSS1_PHY_09_DATA 0x00000000 +#define DDRSS1_PHY_10_DATA 0x00000000 +#define DDRSS1_PHY_11_DATA 0x01000001 +#define DDRSS1_PHY_12_DATA 0x00000200 +#define DDRSS1_PHY_13_DATA 0x000800C0 +#define DDRSS1_PHY_14_DATA 0x060100CC +#define DDRSS1_PHY_15_DATA 0x00030066 +#define DDRSS1_PHY_16_DATA 0x00000000 +#define DDRSS1_PHY_17_DATA 0x00000301 +#define DDRSS1_PHY_18_DATA 0x0000AAAA +#define DDRSS1_PHY_19_DATA 0x00005555 +#define DDRSS1_PHY_20_DATA 0x0000B5B5 +#define DDRSS1_PHY_21_DATA 0x00004A4A +#define DDRSS1_PHY_22_DATA 0x00005656 +#define DDRSS1_PHY_23_DATA 0x0000A9A9 +#define DDRSS1_PHY_24_DATA 0x0000A9A9 +#define DDRSS1_PHY_25_DATA 0x0000B5B5 +#define DDRSS1_PHY_26_DATA 0x00000000 +#define DDRSS1_PHY_27_DATA 0x00000000 +#define DDRSS1_PHY_28_DATA 0x2A000000 +#define DDRSS1_PHY_29_DATA 0x00000808 +#define DDRSS1_PHY_30_DATA 0x0F000000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 +#define DDRSS1_PHY_33_DATA 0x0C002006 +#define DDRSS1_PHY_34_DATA 0x00000000 +#define DDRSS1_PHY_35_DATA 0x00000000 +#define DDRSS1_PHY_36_DATA 0x55555555 +#define DDRSS1_PHY_37_DATA 0xAAAAAAAA +#define DDRSS1_PHY_38_DATA 0x55555555 +#define DDRSS1_PHY_39_DATA 0xAAAAAAAA +#define DDRSS1_PHY_40_DATA 0x00005555 +#define DDRSS1_PHY_41_DATA 0x01000100 +#define DDRSS1_PHY_42_DATA 0x00800180 +#define DDRSS1_PHY_43_DATA 0x00000001 +#define DDRSS1_PHY_44_DATA 0x00000000 +#define DDRSS1_PHY_45_DATA 0x00000000 +#define DDRSS1_PHY_46_DATA 0x00000000 +#define DDRSS1_PHY_47_DATA 0x00000000 +#define DDRSS1_PHY_48_DATA 0x00000000 +#define DDRSS1_PHY_49_DATA 0x00000000 +#define DDRSS1_PHY_50_DATA 0x00000000 +#define DDRSS1_PHY_51_DATA 0x00000000 +#define DDRSS1_PHY_52_DATA 0x00000000 +#define DDRSS1_PHY_53_DATA 0x00000000 +#define DDRSS1_PHY_54_DATA 0x00000000 +#define DDRSS1_PHY_55_DATA 0x00000000 +#define DDRSS1_PHY_56_DATA 0x00000000 +#define DDRSS1_PHY_57_DATA 0x00000000 +#define DDRSS1_PHY_58_DATA 0x00000000 +#define DDRSS1_PHY_59_DATA 0x00000000 +#define DDRSS1_PHY_60_DATA 0x00000000 +#define DDRSS1_PHY_61_DATA 0x00000000 +#define DDRSS1_PHY_62_DATA 0x00000000 +#define DDRSS1_PHY_63_DATA 0x00000000 +#define DDRSS1_PHY_64_DATA 0x00000000 +#define DDRSS1_PHY_65_DATA 0x00000000 +#define DDRSS1_PHY_66_DATA 0x00000104 +#define DDRSS1_PHY_67_DATA 0x00000120 +#define DDRSS1_PHY_68_DATA 0x00000000 +#define DDRSS1_PHY_69_DATA 0x00000000 +#define DDRSS1_PHY_70_DATA 0x00000000 +#define DDRSS1_PHY_71_DATA 0x00000000 +#define DDRSS1_PHY_72_DATA 0x00000000 +#define DDRSS1_PHY_73_DATA 0x00000000 +#define DDRSS1_PHY_74_DATA 0x00000000 +#define DDRSS1_PHY_75_DATA 0x00000001 +#define DDRSS1_PHY_76_DATA 0x07FF0000 +#define DDRSS1_PHY_77_DATA 0x0080081F +#define DDRSS1_PHY_78_DATA 0x00081020 +#define DDRSS1_PHY_79_DATA 0x04010000 +#define DDRSS1_PHY_80_DATA 0x00000000 +#define DDRSS1_PHY_81_DATA 0x00000000 +#define DDRSS1_PHY_82_DATA 0x00000000 +#define DDRSS1_PHY_83_DATA 0x00000100 +#define DDRSS1_PHY_84_DATA 0x01CC0C01 +#define DDRSS1_PHY_85_DATA 0x1003CC0C +#define DDRSS1_PHY_86_DATA 0x20000140 +#define DDRSS1_PHY_87_DATA 0x07FF0200 +#define DDRSS1_PHY_88_DATA 0x0000DD01 +#define DDRSS1_PHY_89_DATA 0x10100303 +#define DDRSS1_PHY_90_DATA 0x10101010 +#define DDRSS1_PHY_91_DATA 0x10101010 +#define DDRSS1_PHY_92_DATA 0x00021010 +#define DDRSS1_PHY_93_DATA 0x00100010 +#define DDRSS1_PHY_94_DATA 0x00100010 +#define DDRSS1_PHY_95_DATA 0x00100010 +#define DDRSS1_PHY_96_DATA 0x00100010 +#define DDRSS1_PHY_97_DATA 0x00050010 +#define DDRSS1_PHY_98_DATA 0x51517041 +#define DDRSS1_PHY_99_DATA 0x31C06001 +#define DDRSS1_PHY_100_DATA 0x07AB01AB +#define DDRSS1_PHY_101_DATA 0x00C0C001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 +#define DDRSS1_PHY_103_DATA 0x10001000 +#define DDRSS1_PHY_104_DATA 0x0C083E42 +#define DDRSS1_PHY_105_DATA 0x0F0C3701 +#define DDRSS1_PHY_106_DATA 0x01000140 +#define DDRSS1_PHY_107_DATA 0x0C000420 +#define DDRSS1_PHY_108_DATA 0x00000198 +#define DDRSS1_PHY_109_DATA 0x0A0000D0 +#define DDRSS1_PHY_110_DATA 0x00030200 +#define DDRSS1_PHY_111_DATA 0x02800000 +#define DDRSS1_PHY_112_DATA 0x80800000 +#define DDRSS1_PHY_113_DATA 0x000E2010 +#define DDRSS1_PHY_114_DATA 0x76543210 +#define DDRSS1_PHY_115_DATA 0x00000008 +#define DDRSS1_PHY_116_DATA 0x02800280 +#define DDRSS1_PHY_117_DATA 0x02800280 +#define DDRSS1_PHY_118_DATA 0x02800280 +#define DDRSS1_PHY_119_DATA 0x02800280 +#define DDRSS1_PHY_120_DATA 0x00000280 +#define DDRSS1_PHY_121_DATA 0x0000A000 +#define DDRSS1_PHY_122_DATA 0x00A000A0 +#define DDRSS1_PHY_123_DATA 0x00A000A0 +#define DDRSS1_PHY_124_DATA 0x00A000A0 +#define DDRSS1_PHY_125_DATA 0x00A000A0 +#define DDRSS1_PHY_126_DATA 0x00A000A0 +#define DDRSS1_PHY_127_DATA 0x00A000A0 +#define DDRSS1_PHY_128_DATA 0x00A000A0 +#define DDRSS1_PHY_129_DATA 0x00A000A0 +#define DDRSS1_PHY_130_DATA 0x01C200A0 +#define DDRSS1_PHY_131_DATA 0x01A00005 +#define DDRSS1_PHY_132_DATA 0x00000000 +#define DDRSS1_PHY_133_DATA 0x00000000 +#define DDRSS1_PHY_134_DATA 0x00080200 +#define DDRSS1_PHY_135_DATA 0x00000000 +#define DDRSS1_PHY_136_DATA 0x20202000 +#define DDRSS1_PHY_137_DATA 0x20202020 +#define DDRSS1_PHY_138_DATA 0xF0F02020 +#define DDRSS1_PHY_139_DATA 0x00000000 +#define DDRSS1_PHY_140_DATA 0x00000000 +#define DDRSS1_PHY_141_DATA 0x00000000 +#define DDRSS1_PHY_142_DATA 0x00000000 +#define DDRSS1_PHY_143_DATA 0x00000000 +#define DDRSS1_PHY_144_DATA 0x00000000 +#define DDRSS1_PHY_145_DATA 0x00000000 +#define DDRSS1_PHY_146_DATA 0x00000000 +#define DDRSS1_PHY_147_DATA 0x00000000 +#define DDRSS1_PHY_148_DATA 0x00000000 +#define DDRSS1_PHY_149_DATA 0x00000000 +#define DDRSS1_PHY_150_DATA 0x00000000 +#define DDRSS1_PHY_151_DATA 0x00000000 +#define DDRSS1_PHY_152_DATA 0x00000000 +#define DDRSS1_PHY_153_DATA 0x00000000 +#define DDRSS1_PHY_154_DATA 0x00000000 +#define DDRSS1_PHY_155_DATA 0x00000000 +#define DDRSS1_PHY_156_DATA 0x00000000 +#define DDRSS1_PHY_157_DATA 0x00000000 +#define DDRSS1_PHY_158_DATA 0x00000000 +#define DDRSS1_PHY_159_DATA 0x00000000 +#define DDRSS1_PHY_160_DATA 0x00000000 +#define DDRSS1_PHY_161_DATA 0x00000000 +#define DDRSS1_PHY_162_DATA 0x00000000 +#define DDRSS1_PHY_163_DATA 0x00000000 +#define DDRSS1_PHY_164_DATA 0x00000000 +#define DDRSS1_PHY_165_DATA 0x00000000 +#define DDRSS1_PHY_166_DATA 0x00000000 +#define DDRSS1_PHY_167_DATA 0x00000000 +#define DDRSS1_PHY_168_DATA 0x00000000 +#define DDRSS1_PHY_169_DATA 0x00000000 +#define DDRSS1_PHY_170_DATA 0x00000000 +#define DDRSS1_PHY_171_DATA 0x00000000 +#define DDRSS1_PHY_172_DATA 0x00000000 +#define DDRSS1_PHY_173_DATA 0x00000000 +#define DDRSS1_PHY_174_DATA 0x00000000 +#define DDRSS1_PHY_175_DATA 0x00000000 +#define DDRSS1_PHY_176_DATA 0x00000000 +#define DDRSS1_PHY_177_DATA 0x00000000 +#define DDRSS1_PHY_178_DATA 0x00000000 +#define DDRSS1_PHY_179_DATA 0x00000000 +#define DDRSS1_PHY_180_DATA 0x00000000 +#define DDRSS1_PHY_181_DATA 0x00000000 +#define DDRSS1_PHY_182_DATA 0x00000000 +#define DDRSS1_PHY_183_DATA 0x00000000 +#define DDRSS1_PHY_184_DATA 0x00000000 +#define DDRSS1_PHY_185_DATA 0x00000000 +#define DDRSS1_PHY_186_DATA 0x00000000 +#define DDRSS1_PHY_187_DATA 0x00000000 +#define DDRSS1_PHY_188_DATA 0x00000000 +#define DDRSS1_PHY_189_DATA 0x00000000 +#define DDRSS1_PHY_190_DATA 0x00000000 +#define DDRSS1_PHY_191_DATA 0x00000000 +#define DDRSS1_PHY_192_DATA 0x00000000 +#define DDRSS1_PHY_193_DATA 0x00000000 +#define DDRSS1_PHY_194_DATA 0x00000000 +#define DDRSS1_PHY_195_DATA 0x00000000 +#define DDRSS1_PHY_196_DATA 0x00000000 +#define DDRSS1_PHY_197_DATA 0x00000000 +#define DDRSS1_PHY_198_DATA 0x00000000 +#define DDRSS1_PHY_199_DATA 0x00000000 +#define DDRSS1_PHY_200_DATA 0x00000000 +#define DDRSS1_PHY_201_DATA 0x00000000 +#define DDRSS1_PHY_202_DATA 0x00000000 +#define DDRSS1_PHY_203_DATA 0x00000000 +#define DDRSS1_PHY_204_DATA 0x00000000 +#define DDRSS1_PHY_205_DATA 0x00000000 +#define DDRSS1_PHY_206_DATA 0x00000000 +#define DDRSS1_PHY_207_DATA 0x00000000 +#define DDRSS1_PHY_208_DATA 0x00000000 +#define DDRSS1_PHY_209_DATA 0x00000000 +#define DDRSS1_PHY_210_DATA 0x00000000 +#define DDRSS1_PHY_211_DATA 0x00000000 +#define DDRSS1_PHY_212_DATA 0x00000000 +#define DDRSS1_PHY_213_DATA 0x00000000 +#define DDRSS1_PHY_214_DATA 0x00000000 +#define DDRSS1_PHY_215_DATA 0x00000000 +#define DDRSS1_PHY_216_DATA 0x00000000 +#define DDRSS1_PHY_217_DATA 0x00000000 +#define DDRSS1_PHY_218_DATA 0x00000000 +#define DDRSS1_PHY_219_DATA 0x00000000 +#define DDRSS1_PHY_220_DATA 0x00000000 +#define DDRSS1_PHY_221_DATA 0x00000000 +#define DDRSS1_PHY_222_DATA 0x00000000 +#define DDRSS1_PHY_223_DATA 0x00000000 +#define DDRSS1_PHY_224_DATA 0x00000000 +#define DDRSS1_PHY_225_DATA 0x00000000 +#define DDRSS1_PHY_226_DATA 0x00000000 +#define DDRSS1_PHY_227_DATA 0x00000000 +#define DDRSS1_PHY_228_DATA 0x00000000 +#define DDRSS1_PHY_229_DATA 0x00000000 +#define DDRSS1_PHY_230_DATA 0x00000000 +#define DDRSS1_PHY_231_DATA 0x00000000 +#define DDRSS1_PHY_232_DATA 0x00000000 +#define DDRSS1_PHY_233_DATA 0x00000000 +#define DDRSS1_PHY_234_DATA 0x00000000 +#define DDRSS1_PHY_235_DATA 0x00000000 +#define DDRSS1_PHY_236_DATA 0x00000000 +#define DDRSS1_PHY_237_DATA 0x00000000 +#define DDRSS1_PHY_238_DATA 0x00000000 +#define DDRSS1_PHY_239_DATA 0x00000000 +#define DDRSS1_PHY_240_DATA 0x00000000 +#define DDRSS1_PHY_241_DATA 0x00000000 +#define DDRSS1_PHY_242_DATA 0x00000000 +#define DDRSS1_PHY_243_DATA 0x00000000 +#define DDRSS1_PHY_244_DATA 0x00000000 +#define DDRSS1_PHY_245_DATA 0x00000000 +#define DDRSS1_PHY_246_DATA 0x00000000 +#define DDRSS1_PHY_247_DATA 0x00000000 +#define DDRSS1_PHY_248_DATA 0x00000000 +#define DDRSS1_PHY_249_DATA 0x00000000 +#define DDRSS1_PHY_250_DATA 0x00000000 +#define DDRSS1_PHY_251_DATA 0x00000000 +#define DDRSS1_PHY_252_DATA 0x00000000 +#define DDRSS1_PHY_253_DATA 0x00000000 +#define DDRSS1_PHY_254_DATA 0x00000000 +#define DDRSS1_PHY_255_DATA 0x00000000 +#define DDRSS1_PHY_256_DATA 0x000004F0 +#define DDRSS1_PHY_257_DATA 0x00000000 +#define DDRSS1_PHY_258_DATA 0x00030200 +#define DDRSS1_PHY_259_DATA 0x00000000 +#define DDRSS1_PHY_260_DATA 0x00000000 +#define DDRSS1_PHY_261_DATA 0x01030000 +#define DDRSS1_PHY_262_DATA 0x00010000 +#define DDRSS1_PHY_263_DATA 0x01030004 +#define DDRSS1_PHY_264_DATA 0x01000000 +#define DDRSS1_PHY_265_DATA 0x00000000 +#define DDRSS1_PHY_266_DATA 0x00000000 +#define DDRSS1_PHY_267_DATA 0x01000001 +#define DDRSS1_PHY_268_DATA 0x00000200 +#define DDRSS1_PHY_269_DATA 0x000800C0 +#define DDRSS1_PHY_270_DATA 0x060100CC +#define DDRSS1_PHY_271_DATA 0x00030066 +#define DDRSS1_PHY_272_DATA 0x00000000 +#define DDRSS1_PHY_273_DATA 0x00000301 +#define DDRSS1_PHY_274_DATA 0x0000AAAA +#define DDRSS1_PHY_275_DATA 0x00005555 +#define DDRSS1_PHY_276_DATA 0x0000B5B5 +#define DDRSS1_PHY_277_DATA 0x00004A4A +#define DDRSS1_PHY_278_DATA 0x00005656 +#define DDRSS1_PHY_279_DATA 0x0000A9A9 +#define DDRSS1_PHY_280_DATA 0x0000A9A9 +#define DDRSS1_PHY_281_DATA 0x0000B5B5 +#define DDRSS1_PHY_282_DATA 0x00000000 +#define DDRSS1_PHY_283_DATA 0x00000000 +#define DDRSS1_PHY_284_DATA 0x2A000000 +#define DDRSS1_PHY_285_DATA 0x00000808 +#define DDRSS1_PHY_286_DATA 0x0F000000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 +#define DDRSS1_PHY_289_DATA 0x0C002006 +#define DDRSS1_PHY_290_DATA 0x00000000 +#define DDRSS1_PHY_291_DATA 0x00000000 +#define DDRSS1_PHY_292_DATA 0x55555555 +#define DDRSS1_PHY_293_DATA 0xAAAAAAAA +#define DDRSS1_PHY_294_DATA 0x55555555 +#define DDRSS1_PHY_295_DATA 0xAAAAAAAA +#define DDRSS1_PHY_296_DATA 0x00005555 +#define DDRSS1_PHY_297_DATA 0x01000100 +#define DDRSS1_PHY_298_DATA 0x00800180 +#define DDRSS1_PHY_299_DATA 0x00000000 +#define DDRSS1_PHY_300_DATA 0x00000000 +#define DDRSS1_PHY_301_DATA 0x00000000 +#define DDRSS1_PHY_302_DATA 0x00000000 +#define DDRSS1_PHY_303_DATA 0x00000000 +#define DDRSS1_PHY_304_DATA 0x00000000 +#define DDRSS1_PHY_305_DATA 0x00000000 +#define DDRSS1_PHY_306_DATA 0x00000000 +#define DDRSS1_PHY_307_DATA 0x00000000 +#define DDRSS1_PHY_308_DATA 0x00000000 +#define DDRSS1_PHY_309_DATA 0x00000000 +#define DDRSS1_PHY_310_DATA 0x00000000 +#define DDRSS1_PHY_311_DATA 0x00000000 +#define DDRSS1_PHY_312_DATA 0x00000000 +#define DDRSS1_PHY_313_DATA 0x00000000 +#define DDRSS1_PHY_314_DATA 0x00000000 +#define DDRSS1_PHY_315_DATA 0x00000000 +#define DDRSS1_PHY_316_DATA 0x00000000 +#define DDRSS1_PHY_317_DATA 0x00000000 +#define DDRSS1_PHY_318_DATA 0x00000000 +#define DDRSS1_PHY_319_DATA 0x00000000 +#define DDRSS1_PHY_320_DATA 0x00000000 +#define DDRSS1_PHY_321_DATA 0x00000000 +#define DDRSS1_PHY_322_DATA 0x00000104 +#define DDRSS1_PHY_323_DATA 0x00000120 +#define DDRSS1_PHY_324_DATA 0x00000000 +#define DDRSS1_PHY_325_DATA 0x00000000 +#define DDRSS1_PHY_326_DATA 0x00000000 +#define DDRSS1_PHY_327_DATA 0x00000000 +#define DDRSS1_PHY_328_DATA 0x00000000 +#define DDRSS1_PHY_329_DATA 0x00000000 +#define DDRSS1_PHY_330_DATA 0x00000000 +#define DDRSS1_PHY_331_DATA 0x00000001 +#define DDRSS1_PHY_332_DATA 0x07FF0000 +#define DDRSS1_PHY_333_DATA 0x0080081F +#define DDRSS1_PHY_334_DATA 0x00081020 +#define DDRSS1_PHY_335_DATA 0x04010000 +#define DDRSS1_PHY_336_DATA 0x00000000 +#define DDRSS1_PHY_337_DATA 0x00000000 +#define DDRSS1_PHY_338_DATA 0x00000000 +#define DDRSS1_PHY_339_DATA 0x00000100 +#define DDRSS1_PHY_340_DATA 0x01CC0C01 +#define DDRSS1_PHY_341_DATA 0x1003CC0C +#define DDRSS1_PHY_342_DATA 0x20000140 +#define DDRSS1_PHY_343_DATA 0x07FF0200 +#define DDRSS1_PHY_344_DATA 0x0000DD01 +#define DDRSS1_PHY_345_DATA 0x10100303 +#define DDRSS1_PHY_346_DATA 0x10101010 +#define DDRSS1_PHY_347_DATA 0x10101010 +#define DDRSS1_PHY_348_DATA 0x00021010 +#define DDRSS1_PHY_349_DATA 0x00100010 +#define DDRSS1_PHY_350_DATA 0x00100010 +#define DDRSS1_PHY_351_DATA 0x00100010 +#define DDRSS1_PHY_352_DATA 0x00100010 +#define DDRSS1_PHY_353_DATA 0x00050010 +#define DDRSS1_PHY_354_DATA 0x51517041 +#define DDRSS1_PHY_355_DATA 0x31C06001 +#define DDRSS1_PHY_356_DATA 0x07AB01AB +#define DDRSS1_PHY_357_DATA 0x00C0C001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 +#define DDRSS1_PHY_359_DATA 0x10001000 +#define DDRSS1_PHY_360_DATA 0x0C083E42 +#define DDRSS1_PHY_361_DATA 0x0F0C3701 +#define DDRSS1_PHY_362_DATA 0x01000140 +#define DDRSS1_PHY_363_DATA 0x0C000420 +#define DDRSS1_PHY_364_DATA 0x00000198 +#define DDRSS1_PHY_365_DATA 0x0A0000D0 +#define DDRSS1_PHY_366_DATA 0x00030200 +#define DDRSS1_PHY_367_DATA 0x02800000 +#define DDRSS1_PHY_368_DATA 0x80800000 +#define DDRSS1_PHY_369_DATA 0x000E2010 +#define DDRSS1_PHY_370_DATA 0x76543210 +#define DDRSS1_PHY_371_DATA 0x00000008 +#define DDRSS1_PHY_372_DATA 0x02800280 +#define DDRSS1_PHY_373_DATA 0x02800280 +#define DDRSS1_PHY_374_DATA 0x02800280 +#define DDRSS1_PHY_375_DATA 0x02800280 +#define DDRSS1_PHY_376_DATA 0x00000280 +#define DDRSS1_PHY_377_DATA 0x0000A000 +#define DDRSS1_PHY_378_DATA 0x00A000A0 +#define DDRSS1_PHY_379_DATA 0x00A000A0 +#define DDRSS1_PHY_380_DATA 0x00A000A0 +#define DDRSS1_PHY_381_DATA 0x00A000A0 +#define DDRSS1_PHY_382_DATA 0x00A000A0 +#define DDRSS1_PHY_383_DATA 0x00A000A0 +#define DDRSS1_PHY_384_DATA 0x00A000A0 +#define DDRSS1_PHY_385_DATA 0x00A000A0 +#define DDRSS1_PHY_386_DATA 0x01C200A0 +#define DDRSS1_PHY_387_DATA 0x01A00005 +#define DDRSS1_PHY_388_DATA 0x00000000 +#define DDRSS1_PHY_389_DATA 0x00000000 +#define DDRSS1_PHY_390_DATA 0x00080200 +#define DDRSS1_PHY_391_DATA 0x00000000 +#define DDRSS1_PHY_392_DATA 0x20202000 +#define DDRSS1_PHY_393_DATA 0x20202020 +#define DDRSS1_PHY_394_DATA 0xF0F02020 +#define DDRSS1_PHY_395_DATA 0x00000000 +#define DDRSS1_PHY_396_DATA 0x00000000 +#define DDRSS1_PHY_397_DATA 0x00000000 +#define DDRSS1_PHY_398_DATA 0x00000000 +#define DDRSS1_PHY_399_DATA 0x00000000 +#define DDRSS1_PHY_400_DATA 0x00000000 +#define DDRSS1_PHY_401_DATA 0x00000000 +#define DDRSS1_PHY_402_DATA 0x00000000 +#define DDRSS1_PHY_403_DATA 0x00000000 +#define DDRSS1_PHY_404_DATA 0x00000000 +#define DDRSS1_PHY_405_DATA 0x00000000 +#define DDRSS1_PHY_406_DATA 0x00000000 +#define DDRSS1_PHY_407_DATA 0x00000000 +#define DDRSS1_PHY_408_DATA 0x00000000 +#define DDRSS1_PHY_409_DATA 0x00000000 +#define DDRSS1_PHY_410_DATA 0x00000000 +#define DDRSS1_PHY_411_DATA 0x00000000 +#define DDRSS1_PHY_412_DATA 0x00000000 +#define DDRSS1_PHY_413_DATA 0x00000000 +#define DDRSS1_PHY_414_DATA 0x00000000 +#define DDRSS1_PHY_415_DATA 0x00000000 +#define DDRSS1_PHY_416_DATA 0x00000000 +#define DDRSS1_PHY_417_DATA 0x00000000 +#define DDRSS1_PHY_418_DATA 0x00000000 +#define DDRSS1_PHY_419_DATA 0x00000000 +#define DDRSS1_PHY_420_DATA 0x00000000 +#define DDRSS1_PHY_421_DATA 0x00000000 +#define DDRSS1_PHY_422_DATA 0x00000000 +#define DDRSS1_PHY_423_DATA 0x00000000 +#define DDRSS1_PHY_424_DATA 0x00000000 +#define DDRSS1_PHY_425_DATA 0x00000000 +#define DDRSS1_PHY_426_DATA 0x00000000 +#define DDRSS1_PHY_427_DATA 0x00000000 +#define DDRSS1_PHY_428_DATA 0x00000000 +#define DDRSS1_PHY_429_DATA 0x00000000 +#define DDRSS1_PHY_430_DATA 0x00000000 +#define DDRSS1_PHY_431_DATA 0x00000000 +#define DDRSS1_PHY_432_DATA 0x00000000 +#define DDRSS1_PHY_433_DATA 0x00000000 +#define DDRSS1_PHY_434_DATA 0x00000000 +#define DDRSS1_PHY_435_DATA 0x00000000 +#define DDRSS1_PHY_436_DATA 0x00000000 +#define DDRSS1_PHY_437_DATA 0x00000000 +#define DDRSS1_PHY_438_DATA 0x00000000 +#define DDRSS1_PHY_439_DATA 0x00000000 +#define DDRSS1_PHY_440_DATA 0x00000000 +#define DDRSS1_PHY_441_DATA 0x00000000 +#define DDRSS1_PHY_442_DATA 0x00000000 +#define DDRSS1_PHY_443_DATA 0x00000000 +#define DDRSS1_PHY_444_DATA 0x00000000 +#define DDRSS1_PHY_445_DATA 0x00000000 +#define DDRSS1_PHY_446_DATA 0x00000000 +#define DDRSS1_PHY_447_DATA 0x00000000 +#define DDRSS1_PHY_448_DATA 0x00000000 +#define DDRSS1_PHY_449_DATA 0x00000000 +#define DDRSS1_PHY_450_DATA 0x00000000 +#define DDRSS1_PHY_451_DATA 0x00000000 +#define DDRSS1_PHY_452_DATA 0x00000000 +#define DDRSS1_PHY_453_DATA 0x00000000 +#define DDRSS1_PHY_454_DATA 0x00000000 +#define DDRSS1_PHY_455_DATA 0x00000000 +#define DDRSS1_PHY_456_DATA 0x00000000 +#define DDRSS1_PHY_457_DATA 0x00000000 +#define DDRSS1_PHY_458_DATA 0x00000000 +#define DDRSS1_PHY_459_DATA 0x00000000 +#define DDRSS1_PHY_460_DATA 0x00000000 +#define DDRSS1_PHY_461_DATA 0x00000000 +#define DDRSS1_PHY_462_DATA 0x00000000 +#define DDRSS1_PHY_463_DATA 0x00000000 +#define DDRSS1_PHY_464_DATA 0x00000000 +#define DDRSS1_PHY_465_DATA 0x00000000 +#define DDRSS1_PHY_466_DATA 0x00000000 +#define DDRSS1_PHY_467_DATA 0x00000000 +#define DDRSS1_PHY_468_DATA 0x00000000 +#define DDRSS1_PHY_469_DATA 0x00000000 +#define DDRSS1_PHY_470_DATA 0x00000000 +#define DDRSS1_PHY_471_DATA 0x00000000 +#define DDRSS1_PHY_472_DATA 0x00000000 +#define DDRSS1_PHY_473_DATA 0x00000000 +#define DDRSS1_PHY_474_DATA 0x00000000 +#define DDRSS1_PHY_475_DATA 0x00000000 +#define DDRSS1_PHY_476_DATA 0x00000000 +#define DDRSS1_PHY_477_DATA 0x00000000 +#define DDRSS1_PHY_478_DATA 0x00000000 +#define DDRSS1_PHY_479_DATA 0x00000000 +#define DDRSS1_PHY_480_DATA 0x00000000 +#define DDRSS1_PHY_481_DATA 0x00000000 +#define DDRSS1_PHY_482_DATA 0x00000000 +#define DDRSS1_PHY_483_DATA 0x00000000 +#define DDRSS1_PHY_484_DATA 0x00000000 +#define DDRSS1_PHY_485_DATA 0x00000000 +#define DDRSS1_PHY_486_DATA 0x00000000 +#define DDRSS1_PHY_487_DATA 0x00000000 +#define DDRSS1_PHY_488_DATA 0x00000000 +#define DDRSS1_PHY_489_DATA 0x00000000 +#define DDRSS1_PHY_490_DATA 0x00000000 +#define DDRSS1_PHY_491_DATA 0x00000000 +#define DDRSS1_PHY_492_DATA 0x00000000 +#define DDRSS1_PHY_493_DATA 0x00000000 +#define DDRSS1_PHY_494_DATA 0x00000000 +#define DDRSS1_PHY_495_DATA 0x00000000 +#define DDRSS1_PHY_496_DATA 0x00000000 +#define DDRSS1_PHY_497_DATA 0x00000000 +#define DDRSS1_PHY_498_DATA 0x00000000 +#define DDRSS1_PHY_499_DATA 0x00000000 +#define DDRSS1_PHY_500_DATA 0x00000000 +#define DDRSS1_PHY_501_DATA 0x00000000 +#define DDRSS1_PHY_502_DATA 0x00000000 +#define DDRSS1_PHY_503_DATA 0x00000000 +#define DDRSS1_PHY_504_DATA 0x00000000 +#define DDRSS1_PHY_505_DATA 0x00000000 +#define DDRSS1_PHY_506_DATA 0x00000000 +#define DDRSS1_PHY_507_DATA 0x00000000 +#define DDRSS1_PHY_508_DATA 0x00000000 +#define DDRSS1_PHY_509_DATA 0x00000000 +#define DDRSS1_PHY_510_DATA 0x00000000 +#define DDRSS1_PHY_511_DATA 0x00000000 +#define DDRSS1_PHY_512_DATA 0x000004F0 +#define DDRSS1_PHY_513_DATA 0x00000000 +#define DDRSS1_PHY_514_DATA 0x00030200 +#define DDRSS1_PHY_515_DATA 0x00000000 +#define DDRSS1_PHY_516_DATA 0x00000000 +#define DDRSS1_PHY_517_DATA 0x01030000 +#define DDRSS1_PHY_518_DATA 0x00010000 +#define DDRSS1_PHY_519_DATA 0x01030004 +#define DDRSS1_PHY_520_DATA 0x01000000 +#define DDRSS1_PHY_521_DATA 0x00000000 +#define DDRSS1_PHY_522_DATA 0x00000000 +#define DDRSS1_PHY_523_DATA 0x01000001 +#define DDRSS1_PHY_524_DATA 0x00000200 +#define DDRSS1_PHY_525_DATA 0x000800C0 +#define DDRSS1_PHY_526_DATA 0x060100CC +#define DDRSS1_PHY_527_DATA 0x00030066 +#define DDRSS1_PHY_528_DATA 0x00000000 +#define DDRSS1_PHY_529_DATA 0x00000301 +#define DDRSS1_PHY_530_DATA 0x0000AAAA +#define DDRSS1_PHY_531_DATA 0x00005555 +#define DDRSS1_PHY_532_DATA 0x0000B5B5 +#define DDRSS1_PHY_533_DATA 0x00004A4A +#define DDRSS1_PHY_534_DATA 0x00005656 +#define DDRSS1_PHY_535_DATA 0x0000A9A9 +#define DDRSS1_PHY_536_DATA 0x0000A9A9 +#define DDRSS1_PHY_537_DATA 0x0000B5B5 +#define DDRSS1_PHY_538_DATA 0x00000000 +#define DDRSS1_PHY_539_DATA 0x00000000 +#define DDRSS1_PHY_540_DATA 0x2A000000 +#define DDRSS1_PHY_541_DATA 0x00000808 +#define DDRSS1_PHY_542_DATA 0x0F000000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 +#define DDRSS1_PHY_545_DATA 0x0C002006 +#define DDRSS1_PHY_546_DATA 0x00000000 +#define DDRSS1_PHY_547_DATA 0x00000000 +#define DDRSS1_PHY_548_DATA 0x55555555 +#define DDRSS1_PHY_549_DATA 0xAAAAAAAA +#define DDRSS1_PHY_550_DATA 0x55555555 +#define DDRSS1_PHY_551_DATA 0xAAAAAAAA +#define DDRSS1_PHY_552_DATA 0x00005555 +#define DDRSS1_PHY_553_DATA 0x01000100 +#define DDRSS1_PHY_554_DATA 0x00800180 +#define DDRSS1_PHY_555_DATA 0x00000001 +#define DDRSS1_PHY_556_DATA 0x00000000 +#define DDRSS1_PHY_557_DATA 0x00000000 +#define DDRSS1_PHY_558_DATA 0x00000000 +#define DDRSS1_PHY_559_DATA 0x00000000 +#define DDRSS1_PHY_560_DATA 0x00000000 +#define DDRSS1_PHY_561_DATA 0x00000000 +#define DDRSS1_PHY_562_DATA 0x00000000 +#define DDRSS1_PHY_563_DATA 0x00000000 +#define DDRSS1_PHY_564_DATA 0x00000000 +#define DDRSS1_PHY_565_DATA 0x00000000 +#define DDRSS1_PHY_566_DATA 0x00000000 +#define DDRSS1_PHY_567_DATA 0x00000000 +#define DDRSS1_PHY_568_DATA 0x00000000 +#define DDRSS1_PHY_569_DATA 0x00000000 +#define DDRSS1_PHY_570_DATA 0x00000000 +#define DDRSS1_PHY_571_DATA 0x00000000 +#define DDRSS1_PHY_572_DATA 0x00000000 +#define DDRSS1_PHY_573_DATA 0x00000000 +#define DDRSS1_PHY_574_DATA 0x00000000 +#define DDRSS1_PHY_575_DATA 0x00000000 +#define DDRSS1_PHY_576_DATA 0x00000000 +#define DDRSS1_PHY_577_DATA 0x00000000 +#define DDRSS1_PHY_578_DATA 0x00000104 +#define DDRSS1_PHY_579_DATA 0x00000120 +#define DDRSS1_PHY_580_DATA 0x00000000 +#define DDRSS1_PHY_581_DATA 0x00000000 +#define DDRSS1_PHY_582_DATA 0x00000000 +#define DDRSS1_PHY_583_DATA 0x00000000 +#define DDRSS1_PHY_584_DATA 0x00000000 +#define DDRSS1_PHY_585_DATA 0x00000000 +#define DDRSS1_PHY_586_DATA 0x00000000 +#define DDRSS1_PHY_587_DATA 0x00000001 +#define DDRSS1_PHY_588_DATA 0x07FF0000 +#define DDRSS1_PHY_589_DATA 0x0080081F +#define DDRSS1_PHY_590_DATA 0x00081020 +#define DDRSS1_PHY_591_DATA 0x04010000 +#define DDRSS1_PHY_592_DATA 0x00000000 +#define DDRSS1_PHY_593_DATA 0x00000000 +#define DDRSS1_PHY_594_DATA 0x00000000 +#define DDRSS1_PHY_595_DATA 0x00000100 +#define DDRSS1_PHY_596_DATA 0x01CC0C01 +#define DDRSS1_PHY_597_DATA 0x1003CC0C +#define DDRSS1_PHY_598_DATA 0x20000140 +#define DDRSS1_PHY_599_DATA 0x07FF0200 +#define DDRSS1_PHY_600_DATA 0x0000DD01 +#define DDRSS1_PHY_601_DATA 0x10100303 +#define DDRSS1_PHY_602_DATA 0x10101010 +#define DDRSS1_PHY_603_DATA 0x10101010 +#define DDRSS1_PHY_604_DATA 0x00021010 +#define DDRSS1_PHY_605_DATA 0x00100010 +#define DDRSS1_PHY_606_DATA 0x00100010 +#define DDRSS1_PHY_607_DATA 0x00100010 +#define DDRSS1_PHY_608_DATA 0x00100010 +#define DDRSS1_PHY_609_DATA 0x00050010 +#define DDRSS1_PHY_610_DATA 0x51517041 +#define DDRSS1_PHY_611_DATA 0x31C06001 +#define DDRSS1_PHY_612_DATA 0x07AB01AB +#define DDRSS1_PHY_613_DATA 0x00C0C001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 +#define DDRSS1_PHY_615_DATA 0x10001000 +#define DDRSS1_PHY_616_DATA 0x0C083E42 +#define DDRSS1_PHY_617_DATA 0x0F0C3701 +#define DDRSS1_PHY_618_DATA 0x01000140 +#define DDRSS1_PHY_619_DATA 0x0C000420 +#define DDRSS1_PHY_620_DATA 0x00000198 +#define DDRSS1_PHY_621_DATA 0x0A0000D0 +#define DDRSS1_PHY_622_DATA 0x00030200 +#define DDRSS1_PHY_623_DATA 0x02800000 +#define DDRSS1_PHY_624_DATA 0x80800000 +#define DDRSS1_PHY_625_DATA 0x000E2010 +#define DDRSS1_PHY_626_DATA 0x76543210 +#define DDRSS1_PHY_627_DATA 0x00000008 +#define DDRSS1_PHY_628_DATA 0x02800280 +#define DDRSS1_PHY_629_DATA 0x02800280 +#define DDRSS1_PHY_630_DATA 0x02800280 +#define DDRSS1_PHY_631_DATA 0x02800280 +#define DDRSS1_PHY_632_DATA 0x00000280 +#define DDRSS1_PHY_633_DATA 0x0000A000 +#define DDRSS1_PHY_634_DATA 0x00A000A0 +#define DDRSS1_PHY_635_DATA 0x00A000A0 +#define DDRSS1_PHY_636_DATA 0x00A000A0 +#define DDRSS1_PHY_637_DATA 0x00A000A0 +#define DDRSS1_PHY_638_DATA 0x00A000A0 +#define DDRSS1_PHY_639_DATA 0x00A000A0 +#define DDRSS1_PHY_640_DATA 0x00A000A0 +#define DDRSS1_PHY_641_DATA 0x00A000A0 +#define DDRSS1_PHY_642_DATA 0x01C200A0 +#define DDRSS1_PHY_643_DATA 0x01A00005 +#define DDRSS1_PHY_644_DATA 0x00000000 +#define DDRSS1_PHY_645_DATA 0x00000000 +#define DDRSS1_PHY_646_DATA 0x00080200 +#define DDRSS1_PHY_647_DATA 0x00000000 +#define DDRSS1_PHY_648_DATA 0x20202000 +#define DDRSS1_PHY_649_DATA 0x20202020 +#define DDRSS1_PHY_650_DATA 0xF0F02020 +#define DDRSS1_PHY_651_DATA 0x00000000 +#define DDRSS1_PHY_652_DATA 0x00000000 +#define DDRSS1_PHY_653_DATA 0x00000000 +#define DDRSS1_PHY_654_DATA 0x00000000 +#define DDRSS1_PHY_655_DATA 0x00000000 +#define DDRSS1_PHY_656_DATA 0x00000000 +#define DDRSS1_PHY_657_DATA 0x00000000 +#define DDRSS1_PHY_658_DATA 0x00000000 +#define DDRSS1_PHY_659_DATA 0x00000000 +#define DDRSS1_PHY_660_DATA 0x00000000 +#define DDRSS1_PHY_661_DATA 0x00000000 +#define DDRSS1_PHY_662_DATA 0x00000000 +#define DDRSS1_PHY_663_DATA 0x00000000 +#define DDRSS1_PHY_664_DATA 0x00000000 +#define DDRSS1_PHY_665_DATA 0x00000000 +#define DDRSS1_PHY_666_DATA 0x00000000 +#define DDRSS1_PHY_667_DATA 0x00000000 +#define DDRSS1_PHY_668_DATA 0x00000000 +#define DDRSS1_PHY_669_DATA 0x00000000 +#define DDRSS1_PHY_670_DATA 0x00000000 +#define DDRSS1_PHY_671_DATA 0x00000000 +#define DDRSS1_PHY_672_DATA 0x00000000 +#define DDRSS1_PHY_673_DATA 0x00000000 +#define DDRSS1_PHY_674_DATA 0x00000000 +#define DDRSS1_PHY_675_DATA 0x00000000 +#define DDRSS1_PHY_676_DATA 0x00000000 +#define DDRSS1_PHY_677_DATA 0x00000000 +#define DDRSS1_PHY_678_DATA 0x00000000 +#define DDRSS1_PHY_679_DATA 0x00000000 +#define DDRSS1_PHY_680_DATA 0x00000000 +#define DDRSS1_PHY_681_DATA 0x00000000 +#define DDRSS1_PHY_682_DATA 0x00000000 +#define DDRSS1_PHY_683_DATA 0x00000000 +#define DDRSS1_PHY_684_DATA 0x00000000 +#define DDRSS1_PHY_685_DATA 0x00000000 +#define DDRSS1_PHY_686_DATA 0x00000000 +#define DDRSS1_PHY_687_DATA 0x00000000 +#define DDRSS1_PHY_688_DATA 0x00000000 +#define DDRSS1_PHY_689_DATA 0x00000000 +#define DDRSS1_PHY_690_DATA 0x00000000 +#define DDRSS1_PHY_691_DATA 0x00000000 +#define DDRSS1_PHY_692_DATA 0x00000000 +#define DDRSS1_PHY_693_DATA 0x00000000 +#define DDRSS1_PHY_694_DATA 0x00000000 +#define DDRSS1_PHY_695_DATA 0x00000000 +#define DDRSS1_PHY_696_DATA 0x00000000 +#define DDRSS1_PHY_697_DATA 0x00000000 +#define DDRSS1_PHY_698_DATA 0x00000000 +#define DDRSS1_PHY_699_DATA 0x00000000 +#define DDRSS1_PHY_700_DATA 0x00000000 +#define DDRSS1_PHY_701_DATA 0x00000000 +#define DDRSS1_PHY_702_DATA 0x00000000 +#define DDRSS1_PHY_703_DATA 0x00000000 +#define DDRSS1_PHY_704_DATA 0x00000000 +#define DDRSS1_PHY_705_DATA 0x00000000 +#define DDRSS1_PHY_706_DATA 0x00000000 +#define DDRSS1_PHY_707_DATA 0x00000000 +#define DDRSS1_PHY_708_DATA 0x00000000 +#define DDRSS1_PHY_709_DATA 0x00000000 +#define DDRSS1_PHY_710_DATA 0x00000000 +#define DDRSS1_PHY_711_DATA 0x00000000 +#define DDRSS1_PHY_712_DATA 0x00000000 +#define DDRSS1_PHY_713_DATA 0x00000000 +#define DDRSS1_PHY_714_DATA 0x00000000 +#define DDRSS1_PHY_715_DATA 0x00000000 +#define DDRSS1_PHY_716_DATA 0x00000000 +#define DDRSS1_PHY_717_DATA 0x00000000 +#define DDRSS1_PHY_718_DATA 0x00000000 +#define DDRSS1_PHY_719_DATA 0x00000000 +#define DDRSS1_PHY_720_DATA 0x00000000 +#define DDRSS1_PHY_721_DATA 0x00000000 +#define DDRSS1_PHY_722_DATA 0x00000000 +#define DDRSS1_PHY_723_DATA 0x00000000 +#define DDRSS1_PHY_724_DATA 0x00000000 +#define DDRSS1_PHY_725_DATA 0x00000000 +#define DDRSS1_PHY_726_DATA 0x00000000 +#define DDRSS1_PHY_727_DATA 0x00000000 +#define DDRSS1_PHY_728_DATA 0x00000000 +#define DDRSS1_PHY_729_DATA 0x00000000 +#define DDRSS1_PHY_730_DATA 0x00000000 +#define DDRSS1_PHY_731_DATA 0x00000000 +#define DDRSS1_PHY_732_DATA 0x00000000 +#define DDRSS1_PHY_733_DATA 0x00000000 +#define DDRSS1_PHY_734_DATA 0x00000000 +#define DDRSS1_PHY_735_DATA 0x00000000 +#define DDRSS1_PHY_736_DATA 0x00000000 +#define DDRSS1_PHY_737_DATA 0x00000000 +#define DDRSS1_PHY_738_DATA 0x00000000 +#define DDRSS1_PHY_739_DATA 0x00000000 +#define DDRSS1_PHY_740_DATA 0x00000000 +#define DDRSS1_PHY_741_DATA 0x00000000 +#define DDRSS1_PHY_742_DATA 0x00000000 +#define DDRSS1_PHY_743_DATA 0x00000000 +#define DDRSS1_PHY_744_DATA 0x00000000 +#define DDRSS1_PHY_745_DATA 0x00000000 +#define DDRSS1_PHY_746_DATA 0x00000000 +#define DDRSS1_PHY_747_DATA 0x00000000 +#define DDRSS1_PHY_748_DATA 0x00000000 +#define DDRSS1_PHY_749_DATA 0x00000000 +#define DDRSS1_PHY_750_DATA 0x00000000 +#define DDRSS1_PHY_751_DATA 0x00000000 +#define DDRSS1_PHY_752_DATA 0x00000000 +#define DDRSS1_PHY_753_DATA 0x00000000 +#define DDRSS1_PHY_754_DATA 0x00000000 +#define DDRSS1_PHY_755_DATA 0x00000000 +#define DDRSS1_PHY_756_DATA 0x00000000 +#define DDRSS1_PHY_757_DATA 0x00000000 +#define DDRSS1_PHY_758_DATA 0x00000000 +#define DDRSS1_PHY_759_DATA 0x00000000 +#define DDRSS1_PHY_760_DATA 0x00000000 +#define DDRSS1_PHY_761_DATA 0x00000000 +#define DDRSS1_PHY_762_DATA 0x00000000 +#define DDRSS1_PHY_763_DATA 0x00000000 +#define DDRSS1_PHY_764_DATA 0x00000000 +#define DDRSS1_PHY_765_DATA 0x00000000 +#define DDRSS1_PHY_766_DATA 0x00000000 +#define DDRSS1_PHY_767_DATA 0x00000000 +#define DDRSS1_PHY_768_DATA 0x000004F0 +#define DDRSS1_PHY_769_DATA 0x00000000 +#define DDRSS1_PHY_770_DATA 0x00030200 +#define DDRSS1_PHY_771_DATA 0x00000000 +#define DDRSS1_PHY_772_DATA 0x00000000 +#define DDRSS1_PHY_773_DATA 0x01030000 +#define DDRSS1_PHY_774_DATA 0x00010000 +#define DDRSS1_PHY_775_DATA 0x01030004 +#define DDRSS1_PHY_776_DATA 0x01000000 +#define DDRSS1_PHY_777_DATA 0x00000000 +#define DDRSS1_PHY_778_DATA 0x00000000 +#define DDRSS1_PHY_779_DATA 0x01000001 +#define DDRSS1_PHY_780_DATA 0x00000200 +#define DDRSS1_PHY_781_DATA 0x000800C0 +#define DDRSS1_PHY_782_DATA 0x060100CC +#define DDRSS1_PHY_783_DATA 0x00030066 +#define DDRSS1_PHY_784_DATA 0x00000000 +#define DDRSS1_PHY_785_DATA 0x00000301 +#define DDRSS1_PHY_786_DATA 0x0000AAAA +#define DDRSS1_PHY_787_DATA 0x00005555 +#define DDRSS1_PHY_788_DATA 0x0000B5B5 +#define DDRSS1_PHY_789_DATA 0x00004A4A +#define DDRSS1_PHY_790_DATA 0x00005656 +#define DDRSS1_PHY_791_DATA 0x0000A9A9 +#define DDRSS1_PHY_792_DATA 0x0000A9A9 +#define DDRSS1_PHY_793_DATA 0x0000B5B5 +#define DDRSS1_PHY_794_DATA 0x00000000 +#define DDRSS1_PHY_795_DATA 0x00000000 +#define DDRSS1_PHY_796_DATA 0x2A000000 +#define DDRSS1_PHY_797_DATA 0x00000808 +#define DDRSS1_PHY_798_DATA 0x0F000000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 +#define DDRSS1_PHY_801_DATA 0x0C002006 +#define DDRSS1_PHY_802_DATA 0x00000000 +#define DDRSS1_PHY_803_DATA 0x00000000 +#define DDRSS1_PHY_804_DATA 0x55555555 +#define DDRSS1_PHY_805_DATA 0xAAAAAAAA +#define DDRSS1_PHY_806_DATA 0x55555555 +#define DDRSS1_PHY_807_DATA 0xAAAAAAAA +#define DDRSS1_PHY_808_DATA 0x00005555 +#define DDRSS1_PHY_809_DATA 0x01000100 +#define DDRSS1_PHY_810_DATA 0x00800180 +#define DDRSS1_PHY_811_DATA 0x00000000 +#define DDRSS1_PHY_812_DATA 0x00000000 +#define DDRSS1_PHY_813_DATA 0x00000000 +#define DDRSS1_PHY_814_DATA 0x00000000 +#define DDRSS1_PHY_815_DATA 0x00000000 +#define DDRSS1_PHY_816_DATA 0x00000000 +#define DDRSS1_PHY_817_DATA 0x00000000 +#define DDRSS1_PHY_818_DATA 0x00000000 +#define DDRSS1_PHY_819_DATA 0x00000000 +#define DDRSS1_PHY_820_DATA 0x00000000 +#define DDRSS1_PHY_821_DATA 0x00000000 +#define DDRSS1_PHY_822_DATA 0x00000000 +#define DDRSS1_PHY_823_DATA 0x00000000 +#define DDRSS1_PHY_824_DATA 0x00000000 +#define DDRSS1_PHY_825_DATA 0x00000000 +#define DDRSS1_PHY_826_DATA 0x00000000 +#define DDRSS1_PHY_827_DATA 0x00000000 +#define DDRSS1_PHY_828_DATA 0x00000000 +#define DDRSS1_PHY_829_DATA 0x00000000 +#define DDRSS1_PHY_830_DATA 0x00000000 +#define DDRSS1_PHY_831_DATA 0x00000000 +#define DDRSS1_PHY_832_DATA 0x00000000 +#define DDRSS1_PHY_833_DATA 0x00000000 +#define DDRSS1_PHY_834_DATA 0x00000104 +#define DDRSS1_PHY_835_DATA 0x00000120 +#define DDRSS1_PHY_836_DATA 0x00000000 +#define DDRSS1_PHY_837_DATA 0x00000000 +#define DDRSS1_PHY_838_DATA 0x00000000 +#define DDRSS1_PHY_839_DATA 0x00000000 +#define DDRSS1_PHY_840_DATA 0x00000000 +#define DDRSS1_PHY_841_DATA 0x00000000 +#define DDRSS1_PHY_842_DATA 0x00000000 +#define DDRSS1_PHY_843_DATA 0x00000001 +#define DDRSS1_PHY_844_DATA 0x07FF0000 +#define DDRSS1_PHY_845_DATA 0x0080081F +#define DDRSS1_PHY_846_DATA 0x00081020 +#define DDRSS1_PHY_847_DATA 0x04010000 +#define DDRSS1_PHY_848_DATA 0x00000000 +#define DDRSS1_PHY_849_DATA 0x00000000 +#define DDRSS1_PHY_850_DATA 0x00000000 +#define DDRSS1_PHY_851_DATA 0x00000100 +#define DDRSS1_PHY_852_DATA 0x01CC0C01 +#define DDRSS1_PHY_853_DATA 0x1003CC0C +#define DDRSS1_PHY_854_DATA 0x20000140 +#define DDRSS1_PHY_855_DATA 0x07FF0200 +#define DDRSS1_PHY_856_DATA 0x0000DD01 +#define DDRSS1_PHY_857_DATA 0x10100303 +#define DDRSS1_PHY_858_DATA 0x10101010 +#define DDRSS1_PHY_859_DATA 0x10101010 +#define DDRSS1_PHY_860_DATA 0x00021010 +#define DDRSS1_PHY_861_DATA 0x00100010 +#define DDRSS1_PHY_862_DATA 0x00100010 +#define DDRSS1_PHY_863_DATA 0x00100010 +#define DDRSS1_PHY_864_DATA 0x00100010 +#define DDRSS1_PHY_865_DATA 0x00050010 +#define DDRSS1_PHY_866_DATA 0x51517041 +#define DDRSS1_PHY_867_DATA 0x31C06001 +#define DDRSS1_PHY_868_DATA 0x07AB01AB +#define DDRSS1_PHY_869_DATA 0x00C0C001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 +#define DDRSS1_PHY_871_DATA 0x10001000 +#define DDRSS1_PHY_872_DATA 0x0C083E42 +#define DDRSS1_PHY_873_DATA 0x0F0C3701 +#define DDRSS1_PHY_874_DATA 0x01000140 +#define DDRSS1_PHY_875_DATA 0x0C000420 +#define DDRSS1_PHY_876_DATA 0x00000198 +#define DDRSS1_PHY_877_DATA 0x0A0000D0 +#define DDRSS1_PHY_878_DATA 0x00030200 +#define DDRSS1_PHY_879_DATA 0x02800000 +#define DDRSS1_PHY_880_DATA 0x80800000 +#define DDRSS1_PHY_881_DATA 0x000E2010 +#define DDRSS1_PHY_882_DATA 0x76543210 +#define DDRSS1_PHY_883_DATA 0x00000008 +#define DDRSS1_PHY_884_DATA 0x02800280 +#define DDRSS1_PHY_885_DATA 0x02800280 +#define DDRSS1_PHY_886_DATA 0x02800280 +#define DDRSS1_PHY_887_DATA 0x02800280 +#define DDRSS1_PHY_888_DATA 0x00000280 +#define DDRSS1_PHY_889_DATA 0x0000A000 +#define DDRSS1_PHY_890_DATA 0x00A000A0 +#define DDRSS1_PHY_891_DATA 0x00A000A0 +#define DDRSS1_PHY_892_DATA 0x00A000A0 +#define DDRSS1_PHY_893_DATA 0x00A000A0 +#define DDRSS1_PHY_894_DATA 0x00A000A0 +#define DDRSS1_PHY_895_DATA 0x00A000A0 +#define DDRSS1_PHY_896_DATA 0x00A000A0 +#define DDRSS1_PHY_897_DATA 0x00A000A0 +#define DDRSS1_PHY_898_DATA 0x01C200A0 +#define DDRSS1_PHY_899_DATA 0x01A00005 +#define DDRSS1_PHY_900_DATA 0x00000000 +#define DDRSS1_PHY_901_DATA 0x00000000 +#define DDRSS1_PHY_902_DATA 0x00080200 +#define DDRSS1_PHY_903_DATA 0x00000000 +#define DDRSS1_PHY_904_DATA 0x20202000 +#define DDRSS1_PHY_905_DATA 0x20202020 +#define DDRSS1_PHY_906_DATA 0xF0F02020 +#define DDRSS1_PHY_907_DATA 0x00000000 +#define DDRSS1_PHY_908_DATA 0x00000000 +#define DDRSS1_PHY_909_DATA 0x00000000 +#define DDRSS1_PHY_910_DATA 0x00000000 +#define DDRSS1_PHY_911_DATA 0x00000000 +#define DDRSS1_PHY_912_DATA 0x00000000 +#define DDRSS1_PHY_913_DATA 0x00000000 +#define DDRSS1_PHY_914_DATA 0x00000000 +#define DDRSS1_PHY_915_DATA 0x00000000 +#define DDRSS1_PHY_916_DATA 0x00000000 +#define DDRSS1_PHY_917_DATA 0x00000000 +#define DDRSS1_PHY_918_DATA 0x00000000 +#define DDRSS1_PHY_919_DATA 0x00000000 +#define DDRSS1_PHY_920_DATA 0x00000000 +#define DDRSS1_PHY_921_DATA 0x00000000 +#define DDRSS1_PHY_922_DATA 0x00000000 +#define DDRSS1_PHY_923_DATA 0x00000000 +#define DDRSS1_PHY_924_DATA 0x00000000 +#define DDRSS1_PHY_925_DATA 0x00000000 +#define DDRSS1_PHY_926_DATA 0x00000000 +#define DDRSS1_PHY_927_DATA 0x00000000 +#define DDRSS1_PHY_928_DATA 0x00000000 +#define DDRSS1_PHY_929_DATA 0x00000000 +#define DDRSS1_PHY_930_DATA 0x00000000 +#define DDRSS1_PHY_931_DATA 0x00000000 +#define DDRSS1_PHY_932_DATA 0x00000000 +#define DDRSS1_PHY_933_DATA 0x00000000 +#define DDRSS1_PHY_934_DATA 0x00000000 +#define DDRSS1_PHY_935_DATA 0x00000000 +#define DDRSS1_PHY_936_DATA 0x00000000 +#define DDRSS1_PHY_937_DATA 0x00000000 +#define DDRSS1_PHY_938_DATA 0x00000000 +#define DDRSS1_PHY_939_DATA 0x00000000 +#define DDRSS1_PHY_940_DATA 0x00000000 +#define DDRSS1_PHY_941_DATA 0x00000000 +#define DDRSS1_PHY_942_DATA 0x00000000 +#define DDRSS1_PHY_943_DATA 0x00000000 +#define DDRSS1_PHY_944_DATA 0x00000000 +#define DDRSS1_PHY_945_DATA 0x00000000 +#define DDRSS1_PHY_946_DATA 0x00000000 +#define DDRSS1_PHY_947_DATA 0x00000000 +#define DDRSS1_PHY_948_DATA 0x00000000 +#define DDRSS1_PHY_949_DATA 0x00000000 +#define DDRSS1_PHY_950_DATA 0x00000000 +#define DDRSS1_PHY_951_DATA 0x00000000 +#define DDRSS1_PHY_952_DATA 0x00000000 +#define DDRSS1_PHY_953_DATA 0x00000000 +#define DDRSS1_PHY_954_DATA 0x00000000 +#define DDRSS1_PHY_955_DATA 0x00000000 +#define DDRSS1_PHY_956_DATA 0x00000000 +#define DDRSS1_PHY_957_DATA 0x00000000 +#define DDRSS1_PHY_958_DATA 0x00000000 +#define DDRSS1_PHY_959_DATA 0x00000000 +#define DDRSS1_PHY_960_DATA 0x00000000 +#define DDRSS1_PHY_961_DATA 0x00000000 +#define DDRSS1_PHY_962_DATA 0x00000000 +#define DDRSS1_PHY_963_DATA 0x00000000 +#define DDRSS1_PHY_964_DATA 0x00000000 +#define DDRSS1_PHY_965_DATA 0x00000000 +#define DDRSS1_PHY_966_DATA 0x00000000 +#define DDRSS1_PHY_967_DATA 0x00000000 +#define DDRSS1_PHY_968_DATA 0x00000000 +#define DDRSS1_PHY_969_DATA 0x00000000 +#define DDRSS1_PHY_970_DATA 0x00000000 +#define DDRSS1_PHY_971_DATA 0x00000000 +#define DDRSS1_PHY_972_DATA 0x00000000 +#define DDRSS1_PHY_973_DATA 0x00000000 +#define DDRSS1_PHY_974_DATA 0x00000000 +#define DDRSS1_PHY_975_DATA 0x00000000 +#define DDRSS1_PHY_976_DATA 0x00000000 +#define DDRSS1_PHY_977_DATA 0x00000000 +#define DDRSS1_PHY_978_DATA 0x00000000 +#define DDRSS1_PHY_979_DATA 0x00000000 +#define DDRSS1_PHY_980_DATA 0x00000000 +#define DDRSS1_PHY_981_DATA 0x00000000 +#define DDRSS1_PHY_982_DATA 0x00000000 +#define DDRSS1_PHY_983_DATA 0x00000000 +#define DDRSS1_PHY_984_DATA 0x00000000 +#define DDRSS1_PHY_985_DATA 0x00000000 +#define DDRSS1_PHY_986_DATA 0x00000000 +#define DDRSS1_PHY_987_DATA 0x00000000 +#define DDRSS1_PHY_988_DATA 0x00000000 +#define DDRSS1_PHY_989_DATA 0x00000000 +#define DDRSS1_PHY_990_DATA 0x00000000 +#define DDRSS1_PHY_991_DATA 0x00000000 +#define DDRSS1_PHY_992_DATA 0x00000000 +#define DDRSS1_PHY_993_DATA 0x00000000 +#define DDRSS1_PHY_994_DATA 0x00000000 +#define DDRSS1_PHY_995_DATA 0x00000000 +#define DDRSS1_PHY_996_DATA 0x00000000 +#define DDRSS1_PHY_997_DATA 0x00000000 +#define DDRSS1_PHY_998_DATA 0x00000000 +#define DDRSS1_PHY_999_DATA 0x00000000 +#define DDRSS1_PHY_1000_DATA 0x00000000 +#define DDRSS1_PHY_1001_DATA 0x00000000 +#define DDRSS1_PHY_1002_DATA 0x00000000 +#define DDRSS1_PHY_1003_DATA 0x00000000 +#define DDRSS1_PHY_1004_DATA 0x00000000 +#define DDRSS1_PHY_1005_DATA 0x00000000 +#define DDRSS1_PHY_1006_DATA 0x00000000 +#define DDRSS1_PHY_1007_DATA 0x00000000 +#define DDRSS1_PHY_1008_DATA 0x00000000 +#define DDRSS1_PHY_1009_DATA 0x00000000 +#define DDRSS1_PHY_1010_DATA 0x00000000 +#define DDRSS1_PHY_1011_DATA 0x00000000 +#define DDRSS1_PHY_1012_DATA 0x00000000 +#define DDRSS1_PHY_1013_DATA 0x00000000 +#define DDRSS1_PHY_1014_DATA 0x00000000 +#define DDRSS1_PHY_1015_DATA 0x00000000 +#define DDRSS1_PHY_1016_DATA 0x00000000 +#define DDRSS1_PHY_1017_DATA 0x00000000 +#define DDRSS1_PHY_1018_DATA 0x00000000 +#define DDRSS1_PHY_1019_DATA 0x00000000 +#define DDRSS1_PHY_1020_DATA 0x00000000 +#define DDRSS1_PHY_1021_DATA 0x00000000 +#define DDRSS1_PHY_1022_DATA 0x00000000 +#define DDRSS1_PHY_1023_DATA 0x00000000 +#define DDRSS1_PHY_1024_DATA 0x00000000 +#define DDRSS1_PHY_1025_DATA 0x00000000 +#define DDRSS1_PHY_1026_DATA 0x00000000 +#define DDRSS1_PHY_1027_DATA 0x00000000 +#define DDRSS1_PHY_1028_DATA 0x00000000 +#define DDRSS1_PHY_1029_DATA 0x00000100 +#define DDRSS1_PHY_1030_DATA 0x00000200 +#define DDRSS1_PHY_1031_DATA 0x00000000 +#define DDRSS1_PHY_1032_DATA 0x00000000 +#define DDRSS1_PHY_1033_DATA 0x00000000 +#define DDRSS1_PHY_1034_DATA 0x00000000 +#define DDRSS1_PHY_1035_DATA 0x00400000 +#define DDRSS1_PHY_1036_DATA 0x00000080 +#define DDRSS1_PHY_1037_DATA 0x00DCBA98 +#define DDRSS1_PHY_1038_DATA 0x03000000 +#define DDRSS1_PHY_1039_DATA 0x00200000 +#define DDRSS1_PHY_1040_DATA 0x00000000 +#define DDRSS1_PHY_1041_DATA 0x00000000 +#define DDRSS1_PHY_1042_DATA 0x00000000 +#define DDRSS1_PHY_1043_DATA 0x00000000 +#define DDRSS1_PHY_1044_DATA 0x00000000 +#define DDRSS1_PHY_1045_DATA 0x0000002A +#define DDRSS1_PHY_1046_DATA 0x00000015 +#define DDRSS1_PHY_1047_DATA 0x00000015 +#define DDRSS1_PHY_1048_DATA 0x0000002A +#define DDRSS1_PHY_1049_DATA 0x00000033 +#define DDRSS1_PHY_1050_DATA 0x0000000C +#define DDRSS1_PHY_1051_DATA 0x0000000C +#define DDRSS1_PHY_1052_DATA 0x00000033 +#define DDRSS1_PHY_1053_DATA 0x00543210 +#define DDRSS1_PHY_1054_DATA 0x003F0000 +#define DDRSS1_PHY_1055_DATA 0x000F3F3F +#define DDRSS1_PHY_1056_DATA 0x20202003 +#define DDRSS1_PHY_1057_DATA 0x00202020 +#define DDRSS1_PHY_1058_DATA 0x20008008 +#define DDRSS1_PHY_1059_DATA 0x00000810 +#define DDRSS1_PHY_1060_DATA 0x00000F00 +#define DDRSS1_PHY_1061_DATA 0x00000000 +#define DDRSS1_PHY_1062_DATA 0x00000000 +#define DDRSS1_PHY_1063_DATA 0x00000000 +#define DDRSS1_PHY_1064_DATA 0x000305CC +#define DDRSS1_PHY_1065_DATA 0x00030000 +#define DDRSS1_PHY_1066_DATA 0x00000300 +#define DDRSS1_PHY_1067_DATA 0x00000300 +#define DDRSS1_PHY_1068_DATA 0x00000300 +#define DDRSS1_PHY_1069_DATA 0x00000300 +#define DDRSS1_PHY_1070_DATA 0x00000300 +#define DDRSS1_PHY_1071_DATA 0x42080010 +#define DDRSS1_PHY_1072_DATA 0x0000803E +#define DDRSS1_PHY_1073_DATA 0x00000001 +#define DDRSS1_PHY_1074_DATA 0x01000102 +#define DDRSS1_PHY_1075_DATA 0x00008000 +#define DDRSS1_PHY_1076_DATA 0x00000000 +#define DDRSS1_PHY_1077_DATA 0x00000000 +#define DDRSS1_PHY_1078_DATA 0x00000000 +#define DDRSS1_PHY_1079_DATA 0x00000000 +#define DDRSS1_PHY_1080_DATA 0x00000000 +#define DDRSS1_PHY_1081_DATA 0x00000000 +#define DDRSS1_PHY_1082_DATA 0x00000000 +#define DDRSS1_PHY_1083_DATA 0x00000000 +#define DDRSS1_PHY_1084_DATA 0x00000000 +#define DDRSS1_PHY_1085_DATA 0x00000000 +#define DDRSS1_PHY_1086_DATA 0x00000000 +#define DDRSS1_PHY_1087_DATA 0x00000000 +#define DDRSS1_PHY_1088_DATA 0x00000000 +#define DDRSS1_PHY_1089_DATA 0x00000000 +#define DDRSS1_PHY_1090_DATA 0x00000000 +#define DDRSS1_PHY_1091_DATA 0x00000000 +#define DDRSS1_PHY_1092_DATA 0x00000000 +#define DDRSS1_PHY_1093_DATA 0x00000000 +#define DDRSS1_PHY_1094_DATA 0x00000000 +#define DDRSS1_PHY_1095_DATA 0x00000000 +#define DDRSS1_PHY_1096_DATA 0x00000000 +#define DDRSS1_PHY_1097_DATA 0x00000000 +#define DDRSS1_PHY_1098_DATA 0x00000000 +#define DDRSS1_PHY_1099_DATA 0x00000000 +#define DDRSS1_PHY_1100_DATA 0x00000000 +#define DDRSS1_PHY_1101_DATA 0x00000000 +#define DDRSS1_PHY_1102_DATA 0x00000000 +#define DDRSS1_PHY_1103_DATA 0x00000000 +#define DDRSS1_PHY_1104_DATA 0x00000000 +#define DDRSS1_PHY_1105_DATA 0x00000000 +#define DDRSS1_PHY_1106_DATA 0x00000000 +#define DDRSS1_PHY_1107_DATA 0x00000000 +#define DDRSS1_PHY_1108_DATA 0x00000000 +#define DDRSS1_PHY_1109_DATA 0x00000000 +#define DDRSS1_PHY_1110_DATA 0x00000000 +#define DDRSS1_PHY_1111_DATA 0x00000000 +#define DDRSS1_PHY_1112_DATA 0x00000000 +#define DDRSS1_PHY_1113_DATA 0x00000000 +#define DDRSS1_PHY_1114_DATA 0x00000000 +#define DDRSS1_PHY_1115_DATA 0x00000000 +#define DDRSS1_PHY_1116_DATA 0x00000000 +#define DDRSS1_PHY_1117_DATA 0x00000000 +#define DDRSS1_PHY_1118_DATA 0x00000000 +#define DDRSS1_PHY_1119_DATA 0x00000000 +#define DDRSS1_PHY_1120_DATA 0x00000000 +#define DDRSS1_PHY_1121_DATA 0x00000000 +#define DDRSS1_PHY_1122_DATA 0x00000000 +#define DDRSS1_PHY_1123_DATA 0x00000000 +#define DDRSS1_PHY_1124_DATA 0x00000000 +#define DDRSS1_PHY_1125_DATA 0x00000000 +#define DDRSS1_PHY_1126_DATA 0x00000000 +#define DDRSS1_PHY_1127_DATA 0x00000000 +#define DDRSS1_PHY_1128_DATA 0x00000000 +#define DDRSS1_PHY_1129_DATA 0x00000000 +#define DDRSS1_PHY_1130_DATA 0x00000000 +#define DDRSS1_PHY_1131_DATA 0x00000000 +#define DDRSS1_PHY_1132_DATA 0x00000000 +#define DDRSS1_PHY_1133_DATA 0x00000000 +#define DDRSS1_PHY_1134_DATA 0x00000000 +#define DDRSS1_PHY_1135_DATA 0x00000000 +#define DDRSS1_PHY_1136_DATA 0x00000000 +#define DDRSS1_PHY_1137_DATA 0x00000000 +#define DDRSS1_PHY_1138_DATA 0x00000000 +#define DDRSS1_PHY_1139_DATA 0x00000000 +#define DDRSS1_PHY_1140_DATA 0x00000000 +#define DDRSS1_PHY_1141_DATA 0x00000000 +#define DDRSS1_PHY_1142_DATA 0x00000000 +#define DDRSS1_PHY_1143_DATA 0x00000000 +#define DDRSS1_PHY_1144_DATA 0x00000000 +#define DDRSS1_PHY_1145_DATA 0x00000000 +#define DDRSS1_PHY_1146_DATA 0x00000000 +#define DDRSS1_PHY_1147_DATA 0x00000000 +#define DDRSS1_PHY_1148_DATA 0x00000000 +#define DDRSS1_PHY_1149_DATA 0x00000000 +#define DDRSS1_PHY_1150_DATA 0x00000000 +#define DDRSS1_PHY_1151_DATA 0x00000000 +#define DDRSS1_PHY_1152_DATA 0x00000000 +#define DDRSS1_PHY_1153_DATA 0x00000000 +#define DDRSS1_PHY_1154_DATA 0x00000000 +#define DDRSS1_PHY_1155_DATA 0x00000000 +#define DDRSS1_PHY_1156_DATA 0x00000000 +#define DDRSS1_PHY_1157_DATA 0x00000000 +#define DDRSS1_PHY_1158_DATA 0x00000000 +#define DDRSS1_PHY_1159_DATA 0x00000000 +#define DDRSS1_PHY_1160_DATA 0x00000000 +#define DDRSS1_PHY_1161_DATA 0x00000000 +#define DDRSS1_PHY_1162_DATA 0x00000000 +#define DDRSS1_PHY_1163_DATA 0x00000000 +#define DDRSS1_PHY_1164_DATA 0x00000000 +#define DDRSS1_PHY_1165_DATA 0x00000000 +#define DDRSS1_PHY_1166_DATA 0x00000000 +#define DDRSS1_PHY_1167_DATA 0x00000000 +#define DDRSS1_PHY_1168_DATA 0x00000000 +#define DDRSS1_PHY_1169_DATA 0x00000000 +#define DDRSS1_PHY_1170_DATA 0x00000000 +#define DDRSS1_PHY_1171_DATA 0x00000000 +#define DDRSS1_PHY_1172_DATA 0x00000000 +#define DDRSS1_PHY_1173_DATA 0x00000000 +#define DDRSS1_PHY_1174_DATA 0x00000000 +#define DDRSS1_PHY_1175_DATA 0x00000000 +#define DDRSS1_PHY_1176_DATA 0x00000000 +#define DDRSS1_PHY_1177_DATA 0x00000000 +#define DDRSS1_PHY_1178_DATA 0x00000000 +#define DDRSS1_PHY_1179_DATA 0x00000000 +#define DDRSS1_PHY_1180_DATA 0x00000000 +#define DDRSS1_PHY_1181_DATA 0x00000000 +#define DDRSS1_PHY_1182_DATA 0x00000000 +#define DDRSS1_PHY_1183_DATA 0x00000000 +#define DDRSS1_PHY_1184_DATA 0x00000000 +#define DDRSS1_PHY_1185_DATA 0x00000000 +#define DDRSS1_PHY_1186_DATA 0x00000000 +#define DDRSS1_PHY_1187_DATA 0x00000000 +#define DDRSS1_PHY_1188_DATA 0x00000000 +#define DDRSS1_PHY_1189_DATA 0x00000000 +#define DDRSS1_PHY_1190_DATA 0x00000000 +#define DDRSS1_PHY_1191_DATA 0x00000000 +#define DDRSS1_PHY_1192_DATA 0x00000000 +#define DDRSS1_PHY_1193_DATA 0x00000000 +#define DDRSS1_PHY_1194_DATA 0x00000000 +#define DDRSS1_PHY_1195_DATA 0x00000000 +#define DDRSS1_PHY_1196_DATA 0x00000000 +#define DDRSS1_PHY_1197_DATA 0x00000000 +#define DDRSS1_PHY_1198_DATA 0x00000000 +#define DDRSS1_PHY_1199_DATA 0x00000000 +#define DDRSS1_PHY_1200_DATA 0x00000000 +#define DDRSS1_PHY_1201_DATA 0x00000000 +#define DDRSS1_PHY_1202_DATA 0x00000000 +#define DDRSS1_PHY_1203_DATA 0x00000000 +#define DDRSS1_PHY_1204_DATA 0x00000000 +#define DDRSS1_PHY_1205_DATA 0x00000000 +#define DDRSS1_PHY_1206_DATA 0x00000000 +#define DDRSS1_PHY_1207_DATA 0x00000000 +#define DDRSS1_PHY_1208_DATA 0x00000000 +#define DDRSS1_PHY_1209_DATA 0x00000000 +#define DDRSS1_PHY_1210_DATA 0x00000000 +#define DDRSS1_PHY_1211_DATA 0x00000000 +#define DDRSS1_PHY_1212_DATA 0x00000000 +#define DDRSS1_PHY_1213_DATA 0x00000000 +#define DDRSS1_PHY_1214_DATA 0x00000000 +#define DDRSS1_PHY_1215_DATA 0x00000000 +#define DDRSS1_PHY_1216_DATA 0x00000000 +#define DDRSS1_PHY_1217_DATA 0x00000000 +#define DDRSS1_PHY_1218_DATA 0x00000000 +#define DDRSS1_PHY_1219_DATA 0x00000000 +#define DDRSS1_PHY_1220_DATA 0x00000000 +#define DDRSS1_PHY_1221_DATA 0x00000000 +#define DDRSS1_PHY_1222_DATA 0x00000000 +#define DDRSS1_PHY_1223_DATA 0x00000000 +#define DDRSS1_PHY_1224_DATA 0x00000000 +#define DDRSS1_PHY_1225_DATA 0x00000000 +#define DDRSS1_PHY_1226_DATA 0x00000000 +#define DDRSS1_PHY_1227_DATA 0x00000000 +#define DDRSS1_PHY_1228_DATA 0x00000000 +#define DDRSS1_PHY_1229_DATA 0x00000000 +#define DDRSS1_PHY_1230_DATA 0x00000000 +#define DDRSS1_PHY_1231_DATA 0x00000000 +#define DDRSS1_PHY_1232_DATA 0x00000000 +#define DDRSS1_PHY_1233_DATA 0x00000000 +#define DDRSS1_PHY_1234_DATA 0x00000000 +#define DDRSS1_PHY_1235_DATA 0x00000000 +#define DDRSS1_PHY_1236_DATA 0x00000000 +#define DDRSS1_PHY_1237_DATA 0x00000000 +#define DDRSS1_PHY_1238_DATA 0x00000000 +#define DDRSS1_PHY_1239_DATA 0x00000000 +#define DDRSS1_PHY_1240_DATA 0x00000000 +#define DDRSS1_PHY_1241_DATA 0x00000000 +#define DDRSS1_PHY_1242_DATA 0x00000000 +#define DDRSS1_PHY_1243_DATA 0x00000000 +#define DDRSS1_PHY_1244_DATA 0x00000000 +#define DDRSS1_PHY_1245_DATA 0x00000000 +#define DDRSS1_PHY_1246_DATA 0x00000000 +#define DDRSS1_PHY_1247_DATA 0x00000000 +#define DDRSS1_PHY_1248_DATA 0x00000000 +#define DDRSS1_PHY_1249_DATA 0x00000000 +#define DDRSS1_PHY_1250_DATA 0x00000000 +#define DDRSS1_PHY_1251_DATA 0x00000000 +#define DDRSS1_PHY_1252_DATA 0x00000000 +#define DDRSS1_PHY_1253_DATA 0x00000000 +#define DDRSS1_PHY_1254_DATA 0x00000000 +#define DDRSS1_PHY_1255_DATA 0x00000000 +#define DDRSS1_PHY_1256_DATA 0x00000000 +#define DDRSS1_PHY_1257_DATA 0x00000000 +#define DDRSS1_PHY_1258_DATA 0x00000000 +#define DDRSS1_PHY_1259_DATA 0x00000000 +#define DDRSS1_PHY_1260_DATA 0x00000000 +#define DDRSS1_PHY_1261_DATA 0x00000000 +#define DDRSS1_PHY_1262_DATA 0x00000000 +#define DDRSS1_PHY_1263_DATA 0x00000000 +#define DDRSS1_PHY_1264_DATA 0x00000000 +#define DDRSS1_PHY_1265_DATA 0x00000000 +#define DDRSS1_PHY_1266_DATA 0x00000000 +#define DDRSS1_PHY_1267_DATA 0x00000000 +#define DDRSS1_PHY_1268_DATA 0x00000000 +#define DDRSS1_PHY_1269_DATA 0x00000000 +#define DDRSS1_PHY_1270_DATA 0x00000000 +#define DDRSS1_PHY_1271_DATA 0x00000000 +#define DDRSS1_PHY_1272_DATA 0x00000000 +#define DDRSS1_PHY_1273_DATA 0x00000000 +#define DDRSS1_PHY_1274_DATA 0x00000000 +#define DDRSS1_PHY_1275_DATA 0x00000000 +#define DDRSS1_PHY_1276_DATA 0x00000000 +#define DDRSS1_PHY_1277_DATA 0x00000000 +#define DDRSS1_PHY_1278_DATA 0x00000000 +#define DDRSS1_PHY_1279_DATA 0x00000000 +#define DDRSS1_PHY_1280_DATA 0x00000000 +#define DDRSS1_PHY_1281_DATA 0x00010100 +#define DDRSS1_PHY_1282_DATA 0x00000000 +#define DDRSS1_PHY_1283_DATA 0x00000000 +#define DDRSS1_PHY_1284_DATA 0x00050000 +#define DDRSS1_PHY_1285_DATA 0x04000000 +#define DDRSS1_PHY_1286_DATA 0x00000055 +#define DDRSS1_PHY_1287_DATA 0x00000000 +#define DDRSS1_PHY_1288_DATA 0x00000000 +#define DDRSS1_PHY_1289_DATA 0x00000000 +#define DDRSS1_PHY_1290_DATA 0x00000000 +#define DDRSS1_PHY_1291_DATA 0x00002001 +#define DDRSS1_PHY_1292_DATA 0x0000400F +#define DDRSS1_PHY_1293_DATA 0x50020028 +#define DDRSS1_PHY_1294_DATA 0x01010000 +#define DDRSS1_PHY_1295_DATA 0x80080001 +#define DDRSS1_PHY_1296_DATA 0x10200000 +#define DDRSS1_PHY_1297_DATA 0x00000008 +#define DDRSS1_PHY_1298_DATA 0x00000000 +#define DDRSS1_PHY_1299_DATA 0x01090E00 +#define DDRSS1_PHY_1300_DATA 0x00040101 +#define DDRSS1_PHY_1301_DATA 0x0000010F +#define DDRSS1_PHY_1302_DATA 0x00000000 +#define DDRSS1_PHY_1303_DATA 0x00000064 +#define DDRSS1_PHY_1304_DATA 0x00000000 +#define DDRSS1_PHY_1305_DATA 0x01010000 +#define DDRSS1_PHY_1306_DATA 0x01080402 +#define DDRSS1_PHY_1307_DATA 0x01200F02 +#define DDRSS1_PHY_1308_DATA 0x00194280 +#define DDRSS1_PHY_1309_DATA 0x00000004 +#define DDRSS1_PHY_1310_DATA 0x00042000 +#define DDRSS1_PHY_1311_DATA 0x00000000 +#define DDRSS1_PHY_1312_DATA 0x00000000 +#define DDRSS1_PHY_1313_DATA 0x00000000 +#define DDRSS1_PHY_1314_DATA 0x00000000 +#define DDRSS1_PHY_1315_DATA 0x00000000 +#define DDRSS1_PHY_1316_DATA 0x00000000 +#define DDRSS1_PHY_1317_DATA 0x01000000 +#define DDRSS1_PHY_1318_DATA 0x00000705 +#define DDRSS1_PHY_1319_DATA 0x00000054 +#define DDRSS1_PHY_1320_DATA 0x00030820 +#define DDRSS1_PHY_1321_DATA 0x00010820 +#define DDRSS1_PHY_1322_DATA 0x00010820 +#define DDRSS1_PHY_1323_DATA 0x00010820 +#define DDRSS1_PHY_1324_DATA 0x00010820 +#define DDRSS1_PHY_1325_DATA 0x00010820 +#define DDRSS1_PHY_1326_DATA 0x00010820 +#define DDRSS1_PHY_1327_DATA 0x00010820 +#define DDRSS1_PHY_1328_DATA 0x00010820 +#define DDRSS1_PHY_1329_DATA 0x00000000 +#define DDRSS1_PHY_1330_DATA 0x00000074 +#define DDRSS1_PHY_1331_DATA 0x00000400 +#define DDRSS1_PHY_1332_DATA 0x00000108 +#define DDRSS1_PHY_1333_DATA 0x00000000 +#define DDRSS1_PHY_1334_DATA 0x00000000 +#define DDRSS1_PHY_1335_DATA 0x00000000 +#define DDRSS1_PHY_1336_DATA 0x00000000 +#define DDRSS1_PHY_1337_DATA 0x00000000 +#define DDRSS1_PHY_1338_DATA 0x03000000 +#define DDRSS1_PHY_1339_DATA 0x00000000 +#define DDRSS1_PHY_1340_DATA 0x00000000 +#define DDRSS1_PHY_1341_DATA 0x00000000 +#define DDRSS1_PHY_1342_DATA 0x04102006 +#define DDRSS1_PHY_1343_DATA 0x00041020 +#define DDRSS1_PHY_1344_DATA 0x01C98C98 +#define DDRSS1_PHY_1345_DATA 0x3F400000 +#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS1_PHY_1347_DATA 0x0000001F +#define DDRSS1_PHY_1348_DATA 0x00000000 +#define DDRSS1_PHY_1349_DATA 0x00000000 +#define DDRSS1_PHY_1350_DATA 0x00000000 +#define DDRSS1_PHY_1351_DATA 0x00010000 +#define DDRSS1_PHY_1352_DATA 0x00000000 +#define DDRSS1_PHY_1353_DATA 0x00000000 +#define DDRSS1_PHY_1354_DATA 0x00000000 +#define DDRSS1_PHY_1355_DATA 0x00000000 +#define DDRSS1_PHY_1356_DATA 0x76543210 +#define DDRSS1_PHY_1357_DATA 0x00010198 +#define DDRSS1_PHY_1358_DATA 0x00000000 +#define DDRSS1_PHY_1359_DATA 0x00000000 +#define DDRSS1_PHY_1360_DATA 0x00000000 +#define DDRSS1_PHY_1361_DATA 0x00040700 +#define DDRSS1_PHY_1362_DATA 0x00000000 +#define DDRSS1_PHY_1363_DATA 0x00000000 +#define DDRSS1_PHY_1364_DATA 0x00000000 +#define DDRSS1_PHY_1365_DATA 0x00000000 +#define DDRSS1_PHY_1366_DATA 0x00000000 +#define DDRSS1_PHY_1367_DATA 0x00000002 +#define DDRSS1_PHY_1368_DATA 0x00000000 +#define DDRSS1_PHY_1369_DATA 0x00000000 +#define DDRSS1_PHY_1370_DATA 0x00000000 +#define DDRSS1_PHY_1371_DATA 0x00000000 +#define DDRSS1_PHY_1372_DATA 0x00000000 +#define DDRSS1_PHY_1373_DATA 0x00000000 +#define DDRSS1_PHY_1374_DATA 0x00080000 +#define DDRSS1_PHY_1375_DATA 0x000007FF +#define DDRSS1_PHY_1376_DATA 0x00000000 +#define DDRSS1_PHY_1377_DATA 0x00000000 +#define DDRSS1_PHY_1378_DATA 0x00000000 +#define DDRSS1_PHY_1379_DATA 0x00000000 +#define DDRSS1_PHY_1380_DATA 0x00000000 +#define DDRSS1_PHY_1381_DATA 0x00000000 +#define DDRSS1_PHY_1382_DATA 0x000FFFFF +#define DDRSS1_PHY_1383_DATA 0x000FFFFF +#define DDRSS1_PHY_1384_DATA 0x0000FFFF +#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS1_PHY_1386_DATA 0x030FFFFF +#define DDRSS1_PHY_1387_DATA 0x01FFFFFF +#define DDRSS1_PHY_1388_DATA 0x0000FFFF +#define DDRSS1_PHY_1389_DATA 0x00000000 +#define DDRSS1_PHY_1390_DATA 0x00000000 +#define DDRSS1_PHY_1391_DATA 0x00000000 +#define DDRSS1_PHY_1392_DATA 0x00000000 +#define DDRSS1_PHY_1393_DATA 0x0001F7C0 +#define DDRSS1_PHY_1394_DATA 0x00000003 +#define DDRSS1_PHY_1395_DATA 0x00000000 +#define DDRSS1_PHY_1396_DATA 0x00001142 +#define DDRSS1_PHY_1397_DATA 0x040207AB +#define DDRSS1_PHY_1398_DATA 0x01000080 +#define DDRSS1_PHY_1399_DATA 0x03900390 +#define DDRSS1_PHY_1400_DATA 0x03900390 +#define DDRSS1_PHY_1401_DATA 0x00000390 +#define DDRSS1_PHY_1402_DATA 0x00000390 +#define DDRSS1_PHY_1403_DATA 0x00000390 +#define DDRSS1_PHY_1404_DATA 0x00000390 +#define DDRSS1_PHY_1405_DATA 0x00000005 +#define DDRSS1_PHY_1406_DATA 0x01813FCC +#define DDRSS1_PHY_1407_DATA 0x000000CC +#define DDRSS1_PHY_1408_DATA 0x0C000DFF +#define DDRSS1_PHY_1409_DATA 0x30000DFF +#define DDRSS1_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1411_DATA 0x000100F0 +#define DDRSS1_PHY_1412_DATA 0x780DFFCC +#define DDRSS1_PHY_1413_DATA 0x00007E31 +#define DDRSS1_PHY_1414_DATA 0x000CBF11 +#define DDRSS1_PHY_1415_DATA 0x01990010 +#define DDRSS1_PHY_1416_DATA 0x000CBF11 +#define DDRSS1_PHY_1417_DATA 0x01990010 +#define DDRSS1_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1419_DATA 0x00EF00F0 +#define DDRSS1_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1421_DATA 0x01FF00F0 +#define DDRSS1_PHY_1422_DATA 0x20040006 + +#define DDRSS2_CTL_00_DATA 0x00000B00 +#define DDRSS2_CTL_01_DATA 0x00000000 +#define DDRSS2_CTL_02_DATA 0x00000000 +#define DDRSS2_CTL_03_DATA 0x00000000 +#define DDRSS2_CTL_04_DATA 0x00000000 +#define DDRSS2_CTL_05_DATA 0x00000000 +#define DDRSS2_CTL_06_DATA 0x00000000 +#define DDRSS2_CTL_07_DATA 0x00002AF8 +#define DDRSS2_CTL_08_DATA 0x0001ADAF +#define DDRSS2_CTL_09_DATA 0x00000005 +#define DDRSS2_CTL_10_DATA 0x0000006E +#define DDRSS2_CTL_11_DATA 0x000681C8 +#define DDRSS2_CTL_12_DATA 0x004111C9 +#define DDRSS2_CTL_13_DATA 0x00000005 +#define DDRSS2_CTL_14_DATA 0x000010A9 +#define DDRSS2_CTL_15_DATA 0x000681C8 +#define DDRSS2_CTL_16_DATA 0x004111C9 +#define DDRSS2_CTL_17_DATA 0x00000005 +#define DDRSS2_CTL_18_DATA 0x000010A9 +#define DDRSS2_CTL_19_DATA 0x01010000 +#define DDRSS2_CTL_20_DATA 0x01011001 +#define DDRSS2_CTL_21_DATA 0x02010000 +#define DDRSS2_CTL_22_DATA 0x00020100 +#define DDRSS2_CTL_23_DATA 0x0000000B +#define DDRSS2_CTL_24_DATA 0x0000001C +#define DDRSS2_CTL_25_DATA 0x00000000 +#define DDRSS2_CTL_26_DATA 0x00000000 +#define DDRSS2_CTL_27_DATA 0x03020200 +#define DDRSS2_CTL_28_DATA 0x00005656 +#define DDRSS2_CTL_29_DATA 0x00100000 +#define DDRSS2_CTL_30_DATA 0x00000000 +#define DDRSS2_CTL_31_DATA 0x00000000 +#define DDRSS2_CTL_32_DATA 0x00000000 +#define DDRSS2_CTL_33_DATA 0x00000000 +#define DDRSS2_CTL_34_DATA 0x040C0000 +#define DDRSS2_CTL_35_DATA 0x12501250 +#define DDRSS2_CTL_36_DATA 0x00050804 +#define DDRSS2_CTL_37_DATA 0x09040008 +#define DDRSS2_CTL_38_DATA 0x15000204 +#define DDRSS2_CTL_39_DATA 0x1760008B +#define DDRSS2_CTL_40_DATA 0x1500422B +#define DDRSS2_CTL_41_DATA 0x1760008B +#define DDRSS2_CTL_42_DATA 0x2000422B +#define DDRSS2_CTL_43_DATA 0x000A0A09 +#define DDRSS2_CTL_44_DATA 0x040003C5 +#define DDRSS2_CTL_45_DATA 0x1E161104 +#define DDRSS2_CTL_46_DATA 0x1000922C +#define DDRSS2_CTL_47_DATA 0x1E161110 +#define DDRSS2_CTL_48_DATA 0x1000922C +#define DDRSS2_CTL_49_DATA 0x02030410 +#define DDRSS2_CTL_50_DATA 0x2C060500 +#define DDRSS2_CTL_51_DATA 0x08292C29 +#define DDRSS2_CTL_52_DATA 0x14000E0A +#define DDRSS2_CTL_53_DATA 0x04010A0A +#define DDRSS2_CTL_54_DATA 0x01010004 +#define DDRSS2_CTL_55_DATA 0x0454540A +#define DDRSS2_CTL_56_DATA 0x04313104 +#define DDRSS2_CTL_57_DATA 0x00003131 +#define DDRSS2_CTL_58_DATA 0x00010100 +#define DDRSS2_CTL_59_DATA 0x03010000 +#define DDRSS2_CTL_60_DATA 0x00001508 +#define DDRSS2_CTL_61_DATA 0x00000068 +#define DDRSS2_CTL_62_DATA 0x0000032B +#define DDRSS2_CTL_63_DATA 0x00001035 +#define DDRSS2_CTL_64_DATA 0x0000032B +#define DDRSS2_CTL_65_DATA 0x00001035 +#define DDRSS2_CTL_66_DATA 0x00000005 +#define DDRSS2_CTL_67_DATA 0x00050000 +#define DDRSS2_CTL_68_DATA 0x00CB0005 +#define DDRSS2_CTL_69_DATA 0x00CB0200 +#define DDRSS2_CTL_70_DATA 0x00400200 +#define DDRSS2_CTL_71_DATA 0x00120103 +#define DDRSS2_CTL_72_DATA 0x00100005 +#define DDRSS2_CTL_73_DATA 0x2F080010 +#define DDRSS2_CTL_74_DATA 0x0505012F +#define DDRSS2_CTL_75_DATA 0x0401030A +#define DDRSS2_CTL_76_DATA 0x041E100B +#define DDRSS2_CTL_77_DATA 0x100B0401 +#define DDRSS2_CTL_78_DATA 0x0001041E +#define DDRSS2_CTL_79_DATA 0x00160016 +#define DDRSS2_CTL_80_DATA 0x033B033B +#define DDRSS2_CTL_81_DATA 0x033B033B +#define DDRSS2_CTL_82_DATA 0x03050505 +#define DDRSS2_CTL_83_DATA 0x03010303 +#define DDRSS2_CTL_84_DATA 0x200B100B +#define DDRSS2_CTL_85_DATA 0x04041004 +#define DDRSS2_CTL_86_DATA 0x200B100B +#define DDRSS2_CTL_87_DATA 0x04041004 +#define DDRSS2_CTL_88_DATA 0x03010000 +#define DDRSS2_CTL_89_DATA 0x00010000 +#define DDRSS2_CTL_90_DATA 0x00000000 +#define DDRSS2_CTL_91_DATA 0x00000000 +#define DDRSS2_CTL_92_DATA 0x01000000 +#define DDRSS2_CTL_93_DATA 0x80104002 +#define DDRSS2_CTL_94_DATA 0x00000000 +#define DDRSS2_CTL_95_DATA 0x00040005 +#define DDRSS2_CTL_96_DATA 0x00000000 +#define DDRSS2_CTL_97_DATA 0x00050000 +#define DDRSS2_CTL_98_DATA 0x00000004 +#define DDRSS2_CTL_99_DATA 0x00000000 +#define DDRSS2_CTL_100_DATA 0x00040005 +#define DDRSS2_CTL_101_DATA 0x00000000 +#define DDRSS2_CTL_102_DATA 0x000018C0 +#define DDRSS2_CTL_103_DATA 0x000018C0 +#define DDRSS2_CTL_104_DATA 0x000018C0 +#define DDRSS2_CTL_105_DATA 0x000018C0 +#define DDRSS2_CTL_106_DATA 0x000018C0 +#define DDRSS2_CTL_107_DATA 0x00000000 +#define DDRSS2_CTL_108_DATA 0x000002B5 +#define DDRSS2_CTL_109_DATA 0x00040D40 +#define DDRSS2_CTL_110_DATA 0x00040D40 +#define DDRSS2_CTL_111_DATA 0x00040D40 +#define DDRSS2_CTL_112_DATA 0x00040D40 +#define DDRSS2_CTL_113_DATA 0x00040D40 +#define DDRSS2_CTL_114_DATA 0x00000000 +#define DDRSS2_CTL_115_DATA 0x00007173 +#define DDRSS2_CTL_116_DATA 0x00040D40 +#define DDRSS2_CTL_117_DATA 0x00040D40 +#define DDRSS2_CTL_118_DATA 0x00040D40 +#define DDRSS2_CTL_119_DATA 0x00040D40 +#define DDRSS2_CTL_120_DATA 0x00040D40 +#define DDRSS2_CTL_121_DATA 0x00000000 +#define DDRSS2_CTL_122_DATA 0x00007173 +#define DDRSS2_CTL_123_DATA 0x00000000 +#define DDRSS2_CTL_124_DATA 0x00000000 +#define DDRSS2_CTL_125_DATA 0x00000000 +#define DDRSS2_CTL_126_DATA 0x00000000 +#define DDRSS2_CTL_127_DATA 0x00000000 +#define DDRSS2_CTL_128_DATA 0x00000000 +#define DDRSS2_CTL_129_DATA 0x00000000 +#define DDRSS2_CTL_130_DATA 0x00000000 +#define DDRSS2_CTL_131_DATA 0x0B030500 +#define DDRSS2_CTL_132_DATA 0x00040B04 +#define DDRSS2_CTL_133_DATA 0x0A090000 +#define DDRSS2_CTL_134_DATA 0x0A090701 +#define DDRSS2_CTL_135_DATA 0x0900000E +#define DDRSS2_CTL_136_DATA 0x0907010A +#define DDRSS2_CTL_137_DATA 0x00000E0A +#define DDRSS2_CTL_138_DATA 0x07010A09 +#define DDRSS2_CTL_139_DATA 0x000E0A09 +#define DDRSS2_CTL_140_DATA 0x07000401 +#define DDRSS2_CTL_141_DATA 0x00000000 +#define DDRSS2_CTL_142_DATA 0x00000000 +#define DDRSS2_CTL_143_DATA 0x00000000 +#define DDRSS2_CTL_144_DATA 0x00000000 +#define DDRSS2_CTL_145_DATA 0x00000000 +#define DDRSS2_CTL_146_DATA 0x00000000 +#define DDRSS2_CTL_147_DATA 0x00000000 +#define DDRSS2_CTL_148_DATA 0x08080000 +#define DDRSS2_CTL_149_DATA 0x01000000 +#define DDRSS2_CTL_150_DATA 0x800000C0 +#define DDRSS2_CTL_151_DATA 0x800000C0 +#define DDRSS2_CTL_152_DATA 0x800000C0 +#define DDRSS2_CTL_153_DATA 0x00000000 +#define DDRSS2_CTL_154_DATA 0x00001500 +#define DDRSS2_CTL_155_DATA 0x00000000 +#define DDRSS2_CTL_156_DATA 0x00000001 +#define DDRSS2_CTL_157_DATA 0x00000002 +#define DDRSS2_CTL_158_DATA 0x0000100E +#define DDRSS2_CTL_159_DATA 0x00000000 +#define DDRSS2_CTL_160_DATA 0x00000000 +#define DDRSS2_CTL_161_DATA 0x00000000 +#define DDRSS2_CTL_162_DATA 0x00000000 +#define DDRSS2_CTL_163_DATA 0x00000000 +#define DDRSS2_CTL_164_DATA 0x000B0000 +#define DDRSS2_CTL_165_DATA 0x000E0006 +#define DDRSS2_CTL_166_DATA 0x000E0404 +#define DDRSS2_CTL_167_DATA 0x00D601AB +#define DDRSS2_CTL_168_DATA 0x10100216 +#define DDRSS2_CTL_169_DATA 0x01AB0216 +#define DDRSS2_CTL_170_DATA 0x021600D6 +#define DDRSS2_CTL_171_DATA 0x02161010 +#define DDRSS2_CTL_172_DATA 0x00000000 +#define DDRSS2_CTL_173_DATA 0x00000000 +#define DDRSS2_CTL_174_DATA 0x00000000 +#define DDRSS2_CTL_175_DATA 0x3FF40084 +#define DDRSS2_CTL_176_DATA 0xF3003FF4 +#define DDRSS2_CTL_177_DATA 0x0000F3F3 +#define DDRSS2_CTL_178_DATA 0x35000000 +#define DDRSS2_CTL_179_DATA 0x27270035 +#define DDRSS2_CTL_180_DATA 0x0F0F0000 +#define DDRSS2_CTL_181_DATA 0x16000000 +#define DDRSS2_CTL_182_DATA 0x00841616 +#define DDRSS2_CTL_183_DATA 0x3FF43FF4 +#define DDRSS2_CTL_184_DATA 0xF3F3F300 +#define DDRSS2_CTL_185_DATA 0x00000000 +#define DDRSS2_CTL_186_DATA 0x00353500 +#define DDRSS2_CTL_187_DATA 0x00002727 +#define DDRSS2_CTL_188_DATA 0x00000F0F +#define DDRSS2_CTL_189_DATA 0x16161600 +#define DDRSS2_CTL_190_DATA 0x00000020 +#define DDRSS2_CTL_191_DATA 0x01000000 +#define DDRSS2_CTL_192_DATA 0x00000001 +#define DDRSS2_CTL_193_DATA 0x00000000 +#define DDRSS2_CTL_194_DATA 0x01000000 +#define DDRSS2_CTL_195_DATA 0x00000001 +#define DDRSS2_CTL_196_DATA 0x00000000 +#define DDRSS2_CTL_197_DATA 0x00000000 +#define DDRSS2_CTL_198_DATA 0x00000000 +#define DDRSS2_CTL_199_DATA 0x00000000 +#define DDRSS2_CTL_200_DATA 0x00000000 +#define DDRSS2_CTL_201_DATA 0x00000000 +#define DDRSS2_CTL_202_DATA 0x00000000 +#define DDRSS2_CTL_203_DATA 0x00000000 +#define DDRSS2_CTL_204_DATA 0x00000000 +#define DDRSS2_CTL_205_DATA 0x00000000 +#define DDRSS2_CTL_206_DATA 0x02000000 +#define DDRSS2_CTL_207_DATA 0x01080101 +#define DDRSS2_CTL_208_DATA 0x00000000 +#define DDRSS2_CTL_209_DATA 0x00000000 +#define DDRSS2_CTL_210_DATA 0x00000000 +#define DDRSS2_CTL_211_DATA 0x00000000 +#define DDRSS2_CTL_212_DATA 0x00000000 +#define DDRSS2_CTL_213_DATA 0x00000000 +#define DDRSS2_CTL_214_DATA 0x00000000 +#define DDRSS2_CTL_215_DATA 0x00000000 +#define DDRSS2_CTL_216_DATA 0x00000000 +#define DDRSS2_CTL_217_DATA 0x00000000 +#define DDRSS2_CTL_218_DATA 0x00000000 +#define DDRSS2_CTL_219_DATA 0x00000000 +#define DDRSS2_CTL_220_DATA 0x00000000 +#define DDRSS2_CTL_221_DATA 0x00000000 +#define DDRSS2_CTL_222_DATA 0x00001000 +#define DDRSS2_CTL_223_DATA 0x006403E8 +#define DDRSS2_CTL_224_DATA 0x00000000 +#define DDRSS2_CTL_225_DATA 0x00000000 +#define DDRSS2_CTL_226_DATA 0x00000000 +#define DDRSS2_CTL_227_DATA 0x15110000 +#define DDRSS2_CTL_228_DATA 0x00040C18 +#define DDRSS2_CTL_229_DATA 0xF000C000 +#define DDRSS2_CTL_230_DATA 0x0000F000 +#define DDRSS2_CTL_231_DATA 0x00000000 +#define DDRSS2_CTL_232_DATA 0x00000000 +#define DDRSS2_CTL_233_DATA 0xC0000000 +#define DDRSS2_CTL_234_DATA 0xF000F000 +#define DDRSS2_CTL_235_DATA 0x00000000 +#define DDRSS2_CTL_236_DATA 0x00000000 +#define DDRSS2_CTL_237_DATA 0x00000000 +#define DDRSS2_CTL_238_DATA 0xF000C000 +#define DDRSS2_CTL_239_DATA 0x0000F000 +#define DDRSS2_CTL_240_DATA 0x00000000 +#define DDRSS2_CTL_241_DATA 0x00000000 +#define DDRSS2_CTL_242_DATA 0x00030000 +#define DDRSS2_CTL_243_DATA 0x00000000 +#define DDRSS2_CTL_244_DATA 0x00000000 +#define DDRSS2_CTL_245_DATA 0x00000000 +#define DDRSS2_CTL_246_DATA 0x00000000 +#define DDRSS2_CTL_247_DATA 0x00000000 +#define DDRSS2_CTL_248_DATA 0x00000000 +#define DDRSS2_CTL_249_DATA 0x00000000 +#define DDRSS2_CTL_250_DATA 0x00000000 +#define DDRSS2_CTL_251_DATA 0x00000000 +#define DDRSS2_CTL_252_DATA 0x00000000 +#define DDRSS2_CTL_253_DATA 0x00000000 +#define DDRSS2_CTL_254_DATA 0x00000000 +#define DDRSS2_CTL_255_DATA 0x00000000 +#define DDRSS2_CTL_256_DATA 0x00000000 +#define DDRSS2_CTL_257_DATA 0x01000200 +#define DDRSS2_CTL_258_DATA 0x00370040 +#define DDRSS2_CTL_259_DATA 0x00020008 +#define DDRSS2_CTL_260_DATA 0x00400100 +#define DDRSS2_CTL_261_DATA 0x00400855 +#define DDRSS2_CTL_262_DATA 0x01000200 +#define DDRSS2_CTL_263_DATA 0x08550040 +#define DDRSS2_CTL_264_DATA 0x00000040 +#define DDRSS2_CTL_265_DATA 0x006B0003 +#define DDRSS2_CTL_266_DATA 0x0100006B +#define DDRSS2_CTL_267_DATA 0x03030303 +#define DDRSS2_CTL_268_DATA 0x00000000 +#define DDRSS2_CTL_269_DATA 0x00000202 +#define DDRSS2_CTL_270_DATA 0x00001FFF +#define DDRSS2_CTL_271_DATA 0x3FFF2000 +#define DDRSS2_CTL_272_DATA 0x03FF0000 +#define DDRSS2_CTL_273_DATA 0x000103FF +#define DDRSS2_CTL_274_DATA 0x0FFF0B00 +#define DDRSS2_CTL_275_DATA 0x01010001 +#define DDRSS2_CTL_276_DATA 0x01010101 +#define DDRSS2_CTL_277_DATA 0x01180101 +#define DDRSS2_CTL_278_DATA 0x00030000 +#define DDRSS2_CTL_279_DATA 0x00000000 +#define DDRSS2_CTL_280_DATA 0x00000000 +#define DDRSS2_CTL_281_DATA 0x00000000 +#define DDRSS2_CTL_282_DATA 0x00000000 +#define DDRSS2_CTL_283_DATA 0x00000000 +#define DDRSS2_CTL_284_DATA 0x00000000 +#define DDRSS2_CTL_285_DATA 0x00000000 +#define DDRSS2_CTL_286_DATA 0x00040101 +#define DDRSS2_CTL_287_DATA 0x04010100 +#define DDRSS2_CTL_288_DATA 0x00000000 +#define DDRSS2_CTL_289_DATA 0x00000000 +#define DDRSS2_CTL_290_DATA 0x03030300 +#define DDRSS2_CTL_291_DATA 0x00010101 +#define DDRSS2_CTL_292_DATA 0x00000000 +#define DDRSS2_CTL_293_DATA 0x00000000 +#define DDRSS2_CTL_294_DATA 0x00000000 +#define DDRSS2_CTL_295_DATA 0x00000000 +#define DDRSS2_CTL_296_DATA 0x00000000 +#define DDRSS2_CTL_297_DATA 0xFFFFFFFF +#define DDRSS2_CTL_298_DATA 0x00000FFF +#define DDRSS2_CTL_299_DATA 0x00000000 +#define DDRSS2_CTL_300_DATA 0x00000000 +#define DDRSS2_CTL_301_DATA 0x00000000 +#define DDRSS2_CTL_302_DATA 0x00000000 +#define DDRSS2_CTL_303_DATA 0x00000000 +#define DDRSS2_CTL_304_DATA 0x00000000 +#define DDRSS2_CTL_305_DATA 0x00000000 +#define DDRSS2_CTL_306_DATA 0x00000000 +#define DDRSS2_CTL_307_DATA 0x00000000 +#define DDRSS2_CTL_308_DATA 0x00000000 +#define DDRSS2_CTL_309_DATA 0x00000000 +#define DDRSS2_CTL_310_DATA 0x00000000 +#define DDRSS2_CTL_311_DATA 0x00000000 +#define DDRSS2_CTL_312_DATA 0x00000000 +#define DDRSS2_CTL_313_DATA 0x01000000 +#define DDRSS2_CTL_314_DATA 0x00020201 +#define DDRSS2_CTL_315_DATA 0x01000101 +#define DDRSS2_CTL_316_DATA 0x01010001 +#define DDRSS2_CTL_317_DATA 0x00010101 +#define DDRSS2_CTL_318_DATA 0x050A0A03 +#define DDRSS2_CTL_319_DATA 0x10082323 +#define DDRSS2_CTL_320_DATA 0x00090310 +#define DDRSS2_CTL_321_DATA 0x0B0C030F +#define DDRSS2_CTL_322_DATA 0x0B0C0306 +#define DDRSS2_CTL_323_DATA 0x0C090006 +#define DDRSS2_CTL_324_DATA 0x0100000C +#define DDRSS2_CTL_325_DATA 0x08040801 +#define DDRSS2_CTL_326_DATA 0x00000004 +#define DDRSS2_CTL_327_DATA 0x00000000 +#define DDRSS2_CTL_328_DATA 0x00010000 +#define DDRSS2_CTL_329_DATA 0x00280D00 +#define DDRSS2_CTL_330_DATA 0x00000001 +#define DDRSS2_CTL_331_DATA 0x00030001 +#define DDRSS2_CTL_332_DATA 0x00000000 +#define DDRSS2_CTL_333_DATA 0x00000000 +#define DDRSS2_CTL_334_DATA 0x00000000 +#define DDRSS2_CTL_335_DATA 0x00000000 +#define DDRSS2_CTL_336_DATA 0x00000000 +#define DDRSS2_CTL_337_DATA 0x00000000 +#define DDRSS2_CTL_338_DATA 0x00000000 +#define DDRSS2_CTL_339_DATA 0x00000000 +#define DDRSS2_CTL_340_DATA 0x01000000 +#define DDRSS2_CTL_341_DATA 0x00000001 +#define DDRSS2_CTL_342_DATA 0x00010100 +#define DDRSS2_CTL_343_DATA 0x03030000 +#define DDRSS2_CTL_344_DATA 0x00000000 +#define DDRSS2_CTL_345_DATA 0x00000000 +#define DDRSS2_CTL_346_DATA 0x00000000 +#define DDRSS2_CTL_347_DATA 0x00000000 +#define DDRSS2_CTL_348_DATA 0x00000000 +#define DDRSS2_CTL_349_DATA 0x00000000 +#define DDRSS2_CTL_350_DATA 0x00000000 +#define DDRSS2_CTL_351_DATA 0x00000000 +#define DDRSS2_CTL_352_DATA 0x00000000 +#define DDRSS2_CTL_353_DATA 0x00000000 +#define DDRSS2_CTL_354_DATA 0x00000000 +#define DDRSS2_CTL_355_DATA 0x00000000 +#define DDRSS2_CTL_356_DATA 0x00000000 +#define DDRSS2_CTL_357_DATA 0x00000000 +#define DDRSS2_CTL_358_DATA 0x00000000 +#define DDRSS2_CTL_359_DATA 0x00000000 +#define DDRSS2_CTL_360_DATA 0x000556AA +#define DDRSS2_CTL_361_DATA 0x000AAAAA +#define DDRSS2_CTL_362_DATA 0x000AA955 +#define DDRSS2_CTL_363_DATA 0x00055555 +#define DDRSS2_CTL_364_DATA 0x000B3133 +#define DDRSS2_CTL_365_DATA 0x0004CD33 +#define DDRSS2_CTL_366_DATA 0x0004CECC +#define DDRSS2_CTL_367_DATA 0x000B32CC +#define DDRSS2_CTL_368_DATA 0x00010300 +#define DDRSS2_CTL_369_DATA 0x03000100 +#define DDRSS2_CTL_370_DATA 0x00000000 +#define DDRSS2_CTL_371_DATA 0x00000000 +#define DDRSS2_CTL_372_DATA 0x00000000 +#define DDRSS2_CTL_373_DATA 0x00000000 +#define DDRSS2_CTL_374_DATA 0x00000000 +#define DDRSS2_CTL_375_DATA 0x00000000 +#define DDRSS2_CTL_376_DATA 0x00000000 +#define DDRSS2_CTL_377_DATA 0x00010000 +#define DDRSS2_CTL_378_DATA 0x00000404 +#define DDRSS2_CTL_379_DATA 0x00000000 +#define DDRSS2_CTL_380_DATA 0x00000000 +#define DDRSS2_CTL_381_DATA 0x00000000 +#define DDRSS2_CTL_382_DATA 0x00000000 +#define DDRSS2_CTL_383_DATA 0x00000000 +#define DDRSS2_CTL_384_DATA 0x00000000 +#define DDRSS2_CTL_385_DATA 0x00000000 +#define DDRSS2_CTL_386_DATA 0x00000000 +#define DDRSS2_CTL_387_DATA 0x3A3A1B00 +#define DDRSS2_CTL_388_DATA 0x000A0000 +#define DDRSS2_CTL_389_DATA 0x000000C6 +#define DDRSS2_CTL_390_DATA 0x00000200 +#define DDRSS2_CTL_391_DATA 0x00000200 +#define DDRSS2_CTL_392_DATA 0x00000200 +#define DDRSS2_CTL_393_DATA 0x00000200 +#define DDRSS2_CTL_394_DATA 0x00000270 +#define DDRSS2_CTL_395_DATA 0x000007BC +#define DDRSS2_CTL_396_DATA 0x00000204 +#define DDRSS2_CTL_397_DATA 0x0000206A +#define DDRSS2_CTL_398_DATA 0x00000200 +#define DDRSS2_CTL_399_DATA 0x00000200 +#define DDRSS2_CTL_400_DATA 0x00000200 +#define DDRSS2_CTL_401_DATA 0x00000200 +#define DDRSS2_CTL_402_DATA 0x0000613E +#define DDRSS2_CTL_403_DATA 0x00014424 +#define DDRSS2_CTL_404_DATA 0x00000E19 +#define DDRSS2_CTL_405_DATA 0x0000206A +#define DDRSS2_CTL_406_DATA 0x00000200 +#define DDRSS2_CTL_407_DATA 0x00000200 +#define DDRSS2_CTL_408_DATA 0x00000200 +#define DDRSS2_CTL_409_DATA 0x00000200 +#define DDRSS2_CTL_410_DATA 0x0000613E +#define DDRSS2_CTL_411_DATA 0x00014424 +#define DDRSS2_CTL_412_DATA 0x02020E19 +#define DDRSS2_CTL_413_DATA 0x03030202 +#define DDRSS2_CTL_414_DATA 0x00000022 +#define DDRSS2_CTL_415_DATA 0x00000000 +#define DDRSS2_CTL_416_DATA 0x00000000 +#define DDRSS2_CTL_417_DATA 0x00001403 +#define DDRSS2_CTL_418_DATA 0x000007D0 +#define DDRSS2_CTL_419_DATA 0x00000000 +#define DDRSS2_CTL_420_DATA 0x00000000 +#define DDRSS2_CTL_421_DATA 0x00030000 +#define DDRSS2_CTL_422_DATA 0x0007001F +#define DDRSS2_CTL_423_DATA 0x001B0033 +#define DDRSS2_CTL_424_DATA 0x001B0033 +#define DDRSS2_CTL_425_DATA 0x00000000 +#define DDRSS2_CTL_426_DATA 0x00000000 +#define DDRSS2_CTL_427_DATA 0x02000000 +#define DDRSS2_CTL_428_DATA 0x01000404 +#define DDRSS2_CTL_429_DATA 0x0B220B22 +#define DDRSS2_CTL_430_DATA 0x00000105 +#define DDRSS2_CTL_431_DATA 0x00010101 +#define DDRSS2_CTL_432_DATA 0x00010101 +#define DDRSS2_CTL_433_DATA 0x00010001 +#define DDRSS2_CTL_434_DATA 0x00000101 +#define DDRSS2_CTL_435_DATA 0x02000201 +#define DDRSS2_CTL_436_DATA 0x02010000 +#define DDRSS2_CTL_437_DATA 0x00000200 +#define DDRSS2_CTL_438_DATA 0x28060000 +#define DDRSS2_CTL_439_DATA 0x00000128 +#define DDRSS2_CTL_440_DATA 0xFFFFFFFF +#define DDRSS2_CTL_441_DATA 0xFFFFFFFF +#define DDRSS2_CTL_442_DATA 0x00000000 +#define DDRSS2_CTL_443_DATA 0x00000000 +#define DDRSS2_CTL_444_DATA 0x00000000 +#define DDRSS2_CTL_445_DATA 0x00000000 +#define DDRSS2_CTL_446_DATA 0x00000000 +#define DDRSS2_CTL_447_DATA 0x00000000 +#define DDRSS2_CTL_448_DATA 0x00000000 +#define DDRSS2_CTL_449_DATA 0x00000000 +#define DDRSS2_CTL_450_DATA 0x00000000 +#define DDRSS2_CTL_451_DATA 0x00000000 +#define DDRSS2_CTL_452_DATA 0x00000000 +#define DDRSS2_CTL_453_DATA 0x00000000 +#define DDRSS2_CTL_454_DATA 0x00000000 +#define DDRSS2_CTL_455_DATA 0x00000000 +#define DDRSS2_CTL_456_DATA 0x00000000 +#define DDRSS2_CTL_457_DATA 0x00000000 +#define DDRSS2_CTL_458_DATA 0x00000000 + +#define DDRSS2_PI_00_DATA 0x00000B00 +#define DDRSS2_PI_01_DATA 0x00000000 +#define DDRSS2_PI_02_DATA 0x00000000 +#define DDRSS2_PI_03_DATA 0x00000000 +#define DDRSS2_PI_04_DATA 0x00000000 +#define DDRSS2_PI_05_DATA 0x00000101 +#define DDRSS2_PI_06_DATA 0x00640000 +#define DDRSS2_PI_07_DATA 0x00000001 +#define DDRSS2_PI_08_DATA 0x00000000 +#define DDRSS2_PI_09_DATA 0x00000000 +#define DDRSS2_PI_10_DATA 0x00000000 +#define DDRSS2_PI_11_DATA 0x00000000 +#define DDRSS2_PI_12_DATA 0x00000003 +#define DDRSS2_PI_13_DATA 0x00010001 +#define DDRSS2_PI_14_DATA 0x0800000F +#define DDRSS2_PI_15_DATA 0x00000103 +#define DDRSS2_PI_16_DATA 0x00000005 +#define DDRSS2_PI_17_DATA 0x00000000 +#define DDRSS2_PI_18_DATA 0x00000000 +#define DDRSS2_PI_19_DATA 0x00000000 +#define DDRSS2_PI_20_DATA 0x00000000 +#define DDRSS2_PI_21_DATA 0x00000000 +#define DDRSS2_PI_22_DATA 0x00000000 +#define DDRSS2_PI_23_DATA 0x00000000 +#define DDRSS2_PI_24_DATA 0x00000000 +#define DDRSS2_PI_25_DATA 0x00000000 +#define DDRSS2_PI_26_DATA 0x00010100 +#define DDRSS2_PI_27_DATA 0x00280A00 +#define DDRSS2_PI_28_DATA 0x00000000 +#define DDRSS2_PI_29_DATA 0x0F000000 +#define DDRSS2_PI_30_DATA 0x00003200 +#define DDRSS2_PI_31_DATA 0x00000000 +#define DDRSS2_PI_32_DATA 0x00000000 +#define DDRSS2_PI_33_DATA 0x01010102 +#define DDRSS2_PI_34_DATA 0x00000000 +#define DDRSS2_PI_35_DATA 0x000000AA +#define DDRSS2_PI_36_DATA 0x00000055 +#define DDRSS2_PI_37_DATA 0x000000B5 +#define DDRSS2_PI_38_DATA 0x0000004A +#define DDRSS2_PI_39_DATA 0x00000056 +#define DDRSS2_PI_40_DATA 0x000000A9 +#define DDRSS2_PI_41_DATA 0x000000A9 +#define DDRSS2_PI_42_DATA 0x000000B5 +#define DDRSS2_PI_43_DATA 0x00000000 +#define DDRSS2_PI_44_DATA 0x00000000 +#define DDRSS2_PI_45_DATA 0x000F0F00 +#define DDRSS2_PI_46_DATA 0x0000001B +#define DDRSS2_PI_47_DATA 0x000007D0 +#define DDRSS2_PI_48_DATA 0x00000300 +#define DDRSS2_PI_49_DATA 0x00000000 +#define DDRSS2_PI_50_DATA 0x00000000 +#define DDRSS2_PI_51_DATA 0x01000000 +#define DDRSS2_PI_52_DATA 0x00010101 +#define DDRSS2_PI_53_DATA 0x00000000 +#define DDRSS2_PI_54_DATA 0x00030000 +#define DDRSS2_PI_55_DATA 0x0F000000 +#define DDRSS2_PI_56_DATA 0x00000017 +#define DDRSS2_PI_57_DATA 0x00000000 +#define DDRSS2_PI_58_DATA 0x00000000 +#define DDRSS2_PI_59_DATA 0x00000000 +#define DDRSS2_PI_60_DATA 0x0A0A140A +#define DDRSS2_PI_61_DATA 0x10020201 +#define DDRSS2_PI_62_DATA 0x00020805 +#define DDRSS2_PI_63_DATA 0x01000404 +#define DDRSS2_PI_64_DATA 0x00000000 +#define DDRSS2_PI_65_DATA 0x00000000 +#define DDRSS2_PI_66_DATA 0x00000100 +#define DDRSS2_PI_67_DATA 0x0002020F +#define DDRSS2_PI_68_DATA 0x00340000 +#define DDRSS2_PI_69_DATA 0x00000000 +#define DDRSS2_PI_70_DATA 0x00000000 +#define DDRSS2_PI_71_DATA 0x0000FFFF +#define DDRSS2_PI_72_DATA 0x01000000 +#define DDRSS2_PI_73_DATA 0x00080000 +#define DDRSS2_PI_74_DATA 0x02000200 +#define DDRSS2_PI_75_DATA 0x01000100 +#define DDRSS2_PI_76_DATA 0x01000000 +#define DDRSS2_PI_77_DATA 0x02000200 +#define DDRSS2_PI_78_DATA 0x00000200 +#define DDRSS2_PI_79_DATA 0x00000000 +#define DDRSS2_PI_80_DATA 0x00000000 +#define DDRSS2_PI_81_DATA 0x00000000 +#define DDRSS2_PI_82_DATA 0x00000000 +#define DDRSS2_PI_83_DATA 0x00000000 +#define DDRSS2_PI_84_DATA 0x00000000 +#define DDRSS2_PI_85_DATA 0x00000000 +#define DDRSS2_PI_86_DATA 0x00000000 +#define DDRSS2_PI_87_DATA 0x00000000 +#define DDRSS2_PI_88_DATA 0x00000000 +#define DDRSS2_PI_89_DATA 0x00000000 +#define DDRSS2_PI_90_DATA 0x00000000 +#define DDRSS2_PI_91_DATA 0x00000400 +#define DDRSS2_PI_92_DATA 0x02010000 +#define DDRSS2_PI_93_DATA 0x00080003 +#define DDRSS2_PI_94_DATA 0x00080000 +#define DDRSS2_PI_95_DATA 0x00000001 +#define DDRSS2_PI_96_DATA 0x00000000 +#define DDRSS2_PI_97_DATA 0x0000AA00 +#define DDRSS2_PI_98_DATA 0x00000000 +#define DDRSS2_PI_99_DATA 0x00000000 +#define DDRSS2_PI_100_DATA 0x00010000 +#define DDRSS2_PI_101_DATA 0x00000000 +#define DDRSS2_PI_102_DATA 0x00000000 +#define DDRSS2_PI_103_DATA 0x00000000 +#define DDRSS2_PI_104_DATA 0x00000000 +#define DDRSS2_PI_105_DATA 0x00000000 +#define DDRSS2_PI_106_DATA 0x00000000 +#define DDRSS2_PI_107_DATA 0x00000000 +#define DDRSS2_PI_108_DATA 0x00000000 +#define DDRSS2_PI_109_DATA 0x00000000 +#define DDRSS2_PI_110_DATA 0x00000000 +#define DDRSS2_PI_111_DATA 0x00000000 +#define DDRSS2_PI_112_DATA 0x00000000 +#define DDRSS2_PI_113_DATA 0x00000000 +#define DDRSS2_PI_114_DATA 0x00000000 +#define DDRSS2_PI_115_DATA 0x00000000 +#define DDRSS2_PI_116_DATA 0x00000000 +#define DDRSS2_PI_117_DATA 0x00000000 +#define DDRSS2_PI_118_DATA 0x00000000 +#define DDRSS2_PI_119_DATA 0x00000000 +#define DDRSS2_PI_120_DATA 0x00000000 +#define DDRSS2_PI_121_DATA 0x00000000 +#define DDRSS2_PI_122_DATA 0x00000000 +#define DDRSS2_PI_123_DATA 0x00000000 +#define DDRSS2_PI_124_DATA 0x00000000 +#define DDRSS2_PI_125_DATA 0x00000008 +#define DDRSS2_PI_126_DATA 0x00000000 +#define DDRSS2_PI_127_DATA 0x00000000 +#define DDRSS2_PI_128_DATA 0x00000000 +#define DDRSS2_PI_129_DATA 0x00000000 +#define DDRSS2_PI_130_DATA 0x00000000 +#define DDRSS2_PI_131_DATA 0x00000000 +#define DDRSS2_PI_132_DATA 0x00000000 +#define DDRSS2_PI_133_DATA 0x00000000 +#define DDRSS2_PI_134_DATA 0x00000002 +#define DDRSS2_PI_135_DATA 0x00000000 +#define DDRSS2_PI_136_DATA 0x00000000 +#define DDRSS2_PI_137_DATA 0x0000000A +#define DDRSS2_PI_138_DATA 0x00000019 +#define DDRSS2_PI_139_DATA 0x00000100 +#define DDRSS2_PI_140_DATA 0x00000000 +#define DDRSS2_PI_141_DATA 0x00000000 +#define DDRSS2_PI_142_DATA 0x00000000 +#define DDRSS2_PI_143_DATA 0x00000000 +#define DDRSS2_PI_144_DATA 0x01000000 +#define DDRSS2_PI_145_DATA 0x00010003 +#define DDRSS2_PI_146_DATA 0x02000101 +#define DDRSS2_PI_147_DATA 0x01030001 +#define DDRSS2_PI_148_DATA 0x00010400 +#define DDRSS2_PI_149_DATA 0x06000105 +#define DDRSS2_PI_150_DATA 0x01070001 +#define DDRSS2_PI_151_DATA 0x00000000 +#define DDRSS2_PI_152_DATA 0x00000000 +#define DDRSS2_PI_153_DATA 0x00000000 +#define DDRSS2_PI_154_DATA 0x00010001 +#define DDRSS2_PI_155_DATA 0x00000000 +#define DDRSS2_PI_156_DATA 0x00000000 +#define DDRSS2_PI_157_DATA 0x00000000 +#define DDRSS2_PI_158_DATA 0x00000000 +#define DDRSS2_PI_159_DATA 0x00000401 +#define DDRSS2_PI_160_DATA 0x00000000 +#define DDRSS2_PI_161_DATA 0x05010000 +#define DDRSS2_PI_162_DATA 0x00000001 +#define DDRSS2_PI_163_DATA 0x2B2B0201 +#define DDRSS2_PI_164_DATA 0x00000034 +#define DDRSS2_PI_165_DATA 0x00000068 +#define DDRSS2_PI_166_DATA 0x00020068 +#define DDRSS2_PI_167_DATA 0x02000200 +#define DDRSS2_PI_168_DATA 0x50120C04 +#define DDRSS2_PI_169_DATA 0x00155012 +#define DDRSS2_PI_170_DATA 0x00000068 +#define DDRSS2_PI_171_DATA 0x0000032B +#define DDRSS2_PI_172_DATA 0x00001035 +#define DDRSS2_PI_173_DATA 0x0000032B +#define DDRSS2_PI_174_DATA 0x04001035 +#define DDRSS2_PI_175_DATA 0x01010404 +#define DDRSS2_PI_176_DATA 0x00001500 +#define DDRSS2_PI_177_DATA 0x00150015 +#define DDRSS2_PI_178_DATA 0x01000100 +#define DDRSS2_PI_179_DATA 0x00000100 +#define DDRSS2_PI_180_DATA 0x00000000 +#define DDRSS2_PI_181_DATA 0x01010101 +#define DDRSS2_PI_182_DATA 0x00000000 +#define DDRSS2_PI_183_DATA 0x00000000 +#define DDRSS2_PI_184_DATA 0x00000000 +#define DDRSS2_PI_185_DATA 0x19040000 +#define DDRSS2_PI_186_DATA 0x0E0E0219 +#define DDRSS2_PI_187_DATA 0x00040402 +#define DDRSS2_PI_188_DATA 0x000D0035 +#define DDRSS2_PI_189_DATA 0x00218049 +#define DDRSS2_PI_190_DATA 0x00218049 +#define DDRSS2_PI_191_DATA 0x01000101 +#define DDRSS2_PI_192_DATA 0x0004000E +#define DDRSS2_PI_193_DATA 0x00040216 +#define DDRSS2_PI_194_DATA 0x01000216 +#define DDRSS2_PI_195_DATA 0x000F000F +#define DDRSS2_PI_196_DATA 0x02170100 +#define DDRSS2_PI_197_DATA 0x01000217 +#define DDRSS2_PI_198_DATA 0x02170217 +#define DDRSS2_PI_199_DATA 0x2F1B3200 +#define DDRSS2_PI_200_DATA 0x01012F1B +#define DDRSS2_PI_201_DATA 0x0A070601 +#define DDRSS2_PI_202_DATA 0x1F130A0D +#define DDRSS2_PI_203_DATA 0x1F130A14 +#define DDRSS2_PI_204_DATA 0x0000C014 +#define DDRSS2_PI_205_DATA 0x00C01000 +#define DDRSS2_PI_206_DATA 0x00C01000 +#define DDRSS2_PI_207_DATA 0x00021000 +#define DDRSS2_PI_208_DATA 0x0024000E +#define DDRSS2_PI_209_DATA 0x00240216 +#define DDRSS2_PI_210_DATA 0x00110216 +#define DDRSS2_PI_211_DATA 0x32000056 +#define DDRSS2_PI_212_DATA 0x00000101 +#define DDRSS2_PI_213_DATA 0x005F0036 +#define DDRSS2_PI_214_DATA 0x03013212 +#define DDRSS2_PI_215_DATA 0x00003600 +#define DDRSS2_PI_216_DATA 0x3212005F +#define DDRSS2_PI_217_DATA 0x09000001 +#define DDRSS2_PI_218_DATA 0x06010504 +#define DDRSS2_PI_219_DATA 0x04000364 +#define DDRSS2_PI_220_DATA 0x0A032001 +#define DDRSS2_PI_221_DATA 0x2C31110A +#define DDRSS2_PI_222_DATA 0x00002918 +#define DDRSS2_PI_223_DATA 0x6000838E +#define DDRSS2_PI_224_DATA 0x1E202008 +#define DDRSS2_PI_225_DATA 0x2C311116 +#define DDRSS2_PI_226_DATA 0x00002918 +#define DDRSS2_PI_227_DATA 0x6000838E +#define DDRSS2_PI_228_DATA 0x1E202008 +#define DDRSS2_PI_229_DATA 0x0000C616 +#define DDRSS2_PI_230_DATA 0x000007BC +#define DDRSS2_PI_231_DATA 0x0000206A +#define DDRSS2_PI_232_DATA 0x00014424 +#define DDRSS2_PI_233_DATA 0x0000206A +#define DDRSS2_PI_234_DATA 0x00014424 +#define DDRSS2_PI_235_DATA 0x033B0016 +#define DDRSS2_PI_236_DATA 0x0303033B +#define DDRSS2_PI_237_DATA 0x002AF803 +#define DDRSS2_PI_238_DATA 0x0001ADAF +#define DDRSS2_PI_239_DATA 0x00000005 +#define DDRSS2_PI_240_DATA 0x0000006E +#define DDRSS2_PI_241_DATA 0x00000016 +#define DDRSS2_PI_242_DATA 0x000681C8 +#define DDRSS2_PI_243_DATA 0x0001ADAF +#define DDRSS2_PI_244_DATA 0x00000005 +#define DDRSS2_PI_245_DATA 0x000010A9 +#define DDRSS2_PI_246_DATA 0x0000033B +#define DDRSS2_PI_247_DATA 0x000681C8 +#define DDRSS2_PI_248_DATA 0x0001ADAF +#define DDRSS2_PI_249_DATA 0x00000005 +#define DDRSS2_PI_250_DATA 0x000010A9 +#define DDRSS2_PI_251_DATA 0x0100033B +#define DDRSS2_PI_252_DATA 0x00370040 +#define DDRSS2_PI_253_DATA 0x00010008 +#define DDRSS2_PI_254_DATA 0x08550040 +#define DDRSS2_PI_255_DATA 0x00010040 +#define DDRSS2_PI_256_DATA 0x08550040 +#define DDRSS2_PI_257_DATA 0x00000340 +#define DDRSS2_PI_258_DATA 0x006B006B +#define DDRSS2_PI_259_DATA 0x08040404 +#define DDRSS2_PI_260_DATA 0x00000055 +#define DDRSS2_PI_261_DATA 0x55083C5A +#define DDRSS2_PI_262_DATA 0x5A000000 +#define DDRSS2_PI_263_DATA 0x0055083C +#define DDRSS2_PI_264_DATA 0x3C5A0000 +#define DDRSS2_PI_265_DATA 0x00005508 +#define DDRSS2_PI_266_DATA 0x0C3C5A00 +#define DDRSS2_PI_267_DATA 0x080F0E0D +#define DDRSS2_PI_268_DATA 0x000B0A09 +#define DDRSS2_PI_269_DATA 0x00030201 +#define DDRSS2_PI_270_DATA 0x01000000 +#define DDRSS2_PI_271_DATA 0x04020201 +#define DDRSS2_PI_272_DATA 0x00080804 +#define DDRSS2_PI_273_DATA 0x00000000 +#define DDRSS2_PI_274_DATA 0x00000000 +#define DDRSS2_PI_275_DATA 0x00F30084 +#define DDRSS2_PI_276_DATA 0x00160000 +#define DDRSS2_PI_277_DATA 0x35F33FF4 +#define DDRSS2_PI_278_DATA 0x00160F27 +#define DDRSS2_PI_279_DATA 0x35F33FF4 +#define DDRSS2_PI_280_DATA 0x00160F27 +#define DDRSS2_PI_281_DATA 0x00F30084 +#define DDRSS2_PI_282_DATA 0x00160000 +#define DDRSS2_PI_283_DATA 0x35F33FF4 +#define DDRSS2_PI_284_DATA 0x00160F27 +#define DDRSS2_PI_285_DATA 0x35F33FF4 +#define DDRSS2_PI_286_DATA 0x00160F27 +#define DDRSS2_PI_287_DATA 0x00F30084 +#define DDRSS2_PI_288_DATA 0x00160000 +#define DDRSS2_PI_289_DATA 0x35F33FF4 +#define DDRSS2_PI_290_DATA 0x00160F27 +#define DDRSS2_PI_291_DATA 0x35F33FF4 +#define DDRSS2_PI_292_DATA 0x00160F27 +#define DDRSS2_PI_293_DATA 0x00F30084 +#define DDRSS2_PI_294_DATA 0x00160000 +#define DDRSS2_PI_295_DATA 0x35F33FF4 +#define DDRSS2_PI_296_DATA 0x00160F27 +#define DDRSS2_PI_297_DATA 0x35F33FF4 +#define DDRSS2_PI_298_DATA 0x00160F27 +#define DDRSS2_PI_299_DATA 0x00000000 + +#define DDRSS2_PHY_00_DATA 0x000004F0 +#define DDRSS2_PHY_01_DATA 0x00000000 +#define DDRSS2_PHY_02_DATA 0x00030200 +#define DDRSS2_PHY_03_DATA 0x00000000 +#define DDRSS2_PHY_04_DATA 0x00000000 +#define DDRSS2_PHY_05_DATA 0x01030000 +#define DDRSS2_PHY_06_DATA 0x00010000 +#define DDRSS2_PHY_07_DATA 0x01030004 +#define DDRSS2_PHY_08_DATA 0x01000000 +#define DDRSS2_PHY_09_DATA 0x00000000 +#define DDRSS2_PHY_10_DATA 0x00000000 +#define DDRSS2_PHY_11_DATA 0x01000001 +#define DDRSS2_PHY_12_DATA 0x00000200 +#define DDRSS2_PHY_13_DATA 0x000800C0 +#define DDRSS2_PHY_14_DATA 0x060100CC +#define DDRSS2_PHY_15_DATA 0x00030066 +#define DDRSS2_PHY_16_DATA 0x00000000 +#define DDRSS2_PHY_17_DATA 0x00000301 +#define DDRSS2_PHY_18_DATA 0x0000AAAA +#define DDRSS2_PHY_19_DATA 0x00005555 +#define DDRSS2_PHY_20_DATA 0x0000B5B5 +#define DDRSS2_PHY_21_DATA 0x00004A4A +#define DDRSS2_PHY_22_DATA 0x00005656 +#define DDRSS2_PHY_23_DATA 0x0000A9A9 +#define DDRSS2_PHY_24_DATA 0x0000A9A9 +#define DDRSS2_PHY_25_DATA 0x0000B5B5 +#define DDRSS2_PHY_26_DATA 0x00000000 +#define DDRSS2_PHY_27_DATA 0x00000000 +#define DDRSS2_PHY_28_DATA 0x2A000000 +#define DDRSS2_PHY_29_DATA 0x00000808 +#define DDRSS2_PHY_30_DATA 0x0F000000 +#define DDRSS2_PHY_31_DATA 0x00000F08 +#define DDRSS2_PHY_32_DATA 0x10400000 +#define DDRSS2_PHY_33_DATA 0x0C002006 +#define DDRSS2_PHY_34_DATA 0x00000000 +#define DDRSS2_PHY_35_DATA 0x00000000 +#define DDRSS2_PHY_36_DATA 0x55555555 +#define DDRSS2_PHY_37_DATA 0xAAAAAAAA +#define DDRSS2_PHY_38_DATA 0x55555555 +#define DDRSS2_PHY_39_DATA 0xAAAAAAAA +#define DDRSS2_PHY_40_DATA 0x00005555 +#define DDRSS2_PHY_41_DATA 0x01000100 +#define DDRSS2_PHY_42_DATA 0x00800180 +#define DDRSS2_PHY_43_DATA 0x00000001 +#define DDRSS2_PHY_44_DATA 0x00000000 +#define DDRSS2_PHY_45_DATA 0x00000000 +#define DDRSS2_PHY_46_DATA 0x00000000 +#define DDRSS2_PHY_47_DATA 0x00000000 +#define DDRSS2_PHY_48_DATA 0x00000000 +#define DDRSS2_PHY_49_DATA 0x00000000 +#define DDRSS2_PHY_50_DATA 0x00000000 +#define DDRSS2_PHY_51_DATA 0x00000000 +#define DDRSS2_PHY_52_DATA 0x00000000 +#define DDRSS2_PHY_53_DATA 0x00000000 +#define DDRSS2_PHY_54_DATA 0x00000000 +#define DDRSS2_PHY_55_DATA 0x00000000 +#define DDRSS2_PHY_56_DATA 0x00000000 +#define DDRSS2_PHY_57_DATA 0x00000000 +#define DDRSS2_PHY_58_DATA 0x00000000 +#define DDRSS2_PHY_59_DATA 0x00000000 +#define DDRSS2_PHY_60_DATA 0x00000000 +#define DDRSS2_PHY_61_DATA 0x00000000 +#define DDRSS2_PHY_62_DATA 0x00000000 +#define DDRSS2_PHY_63_DATA 0x00000000 +#define DDRSS2_PHY_64_DATA 0x00000000 +#define DDRSS2_PHY_65_DATA 0x00000000 +#define DDRSS2_PHY_66_DATA 0x00000104 +#define DDRSS2_PHY_67_DATA 0x00000120 +#define DDRSS2_PHY_68_DATA 0x00000000 +#define DDRSS2_PHY_69_DATA 0x00000000 +#define DDRSS2_PHY_70_DATA 0x00000000 +#define DDRSS2_PHY_71_DATA 0x00000000 +#define DDRSS2_PHY_72_DATA 0x00000000 +#define DDRSS2_PHY_73_DATA 0x00000000 +#define DDRSS2_PHY_74_DATA 0x00000000 +#define DDRSS2_PHY_75_DATA 0x00000001 +#define DDRSS2_PHY_76_DATA 0x07FF0000 +#define DDRSS2_PHY_77_DATA 0x0080081F +#define DDRSS2_PHY_78_DATA 0x00081020 +#define DDRSS2_PHY_79_DATA 0x04010000 +#define DDRSS2_PHY_80_DATA 0x00000000 +#define DDRSS2_PHY_81_DATA 0x00000000 +#define DDRSS2_PHY_82_DATA 0x00000000 +#define DDRSS2_PHY_83_DATA 0x00000100 +#define DDRSS2_PHY_84_DATA 0x01CC0C01 +#define DDRSS2_PHY_85_DATA 0x1003CC0C +#define DDRSS2_PHY_86_DATA 0x20000140 +#define DDRSS2_PHY_87_DATA 0x07FF0200 +#define DDRSS2_PHY_88_DATA 0x0000DD01 +#define DDRSS2_PHY_89_DATA 0x10100303 +#define DDRSS2_PHY_90_DATA 0x10101010 +#define DDRSS2_PHY_91_DATA 0x10101010 +#define DDRSS2_PHY_92_DATA 0x00021010 +#define DDRSS2_PHY_93_DATA 0x00100010 +#define DDRSS2_PHY_94_DATA 0x00100010 +#define DDRSS2_PHY_95_DATA 0x00100010 +#define DDRSS2_PHY_96_DATA 0x00100010 +#define DDRSS2_PHY_97_DATA 0x00050010 +#define DDRSS2_PHY_98_DATA 0x51517041 +#define DDRSS2_PHY_99_DATA 0x31C06001 +#define DDRSS2_PHY_100_DATA 0x07AB01AB +#define DDRSS2_PHY_101_DATA 0x00C0C001 +#define DDRSS2_PHY_102_DATA 0x0E0D0101 +#define DDRSS2_PHY_103_DATA 0x10001000 +#define DDRSS2_PHY_104_DATA 0x0C083E42 +#define DDRSS2_PHY_105_DATA 0x0F0C3701 +#define DDRSS2_PHY_106_DATA 0x01000140 +#define DDRSS2_PHY_107_DATA 0x0C000420 +#define DDRSS2_PHY_108_DATA 0x00000198 +#define DDRSS2_PHY_109_DATA 0x0A0000D0 +#define DDRSS2_PHY_110_DATA 0x00030200 +#define DDRSS2_PHY_111_DATA 0x02800000 +#define DDRSS2_PHY_112_DATA 0x80800000 +#define DDRSS2_PHY_113_DATA 0x000E2010 +#define DDRSS2_PHY_114_DATA 0x76543210 +#define DDRSS2_PHY_115_DATA 0x00000008 +#define DDRSS2_PHY_116_DATA 0x02800280 +#define DDRSS2_PHY_117_DATA 0x02800280 +#define DDRSS2_PHY_118_DATA 0x02800280 +#define DDRSS2_PHY_119_DATA 0x02800280 +#define DDRSS2_PHY_120_DATA 0x00000280 +#define DDRSS2_PHY_121_DATA 0x0000A000 +#define DDRSS2_PHY_122_DATA 0x00A000A0 +#define DDRSS2_PHY_123_DATA 0x00A000A0 +#define DDRSS2_PHY_124_DATA 0x00A000A0 +#define DDRSS2_PHY_125_DATA 0x00A000A0 +#define DDRSS2_PHY_126_DATA 0x00A000A0 +#define DDRSS2_PHY_127_DATA 0x00A000A0 +#define DDRSS2_PHY_128_DATA 0x00A000A0 +#define DDRSS2_PHY_129_DATA 0x00A000A0 +#define DDRSS2_PHY_130_DATA 0x01C200A0 +#define DDRSS2_PHY_131_DATA 0x01A00005 +#define DDRSS2_PHY_132_DATA 0x00000000 +#define DDRSS2_PHY_133_DATA 0x00000000 +#define DDRSS2_PHY_134_DATA 0x00080200 +#define DDRSS2_PHY_135_DATA 0x00000000 +#define DDRSS2_PHY_136_DATA 0x20202000 +#define DDRSS2_PHY_137_DATA 0x20202020 +#define DDRSS2_PHY_138_DATA 0xF0F02020 +#define DDRSS2_PHY_139_DATA 0x00000000 +#define DDRSS2_PHY_140_DATA 0x00000000 +#define DDRSS2_PHY_141_DATA 0x00000000 +#define DDRSS2_PHY_142_DATA 0x00000000 +#define DDRSS2_PHY_143_DATA 0x00000000 +#define DDRSS2_PHY_144_DATA 0x00000000 +#define DDRSS2_PHY_145_DATA 0x00000000 +#define DDRSS2_PHY_146_DATA 0x00000000 +#define DDRSS2_PHY_147_DATA 0x00000000 +#define DDRSS2_PHY_148_DATA 0x00000000 +#define DDRSS2_PHY_149_DATA 0x00000000 +#define DDRSS2_PHY_150_DATA 0x00000000 +#define DDRSS2_PHY_151_DATA 0x00000000 +#define DDRSS2_PHY_152_DATA 0x00000000 +#define DDRSS2_PHY_153_DATA 0x00000000 +#define DDRSS2_PHY_154_DATA 0x00000000 +#define DDRSS2_PHY_155_DATA 0x00000000 +#define DDRSS2_PHY_156_DATA 0x00000000 +#define DDRSS2_PHY_157_DATA 0x00000000 +#define DDRSS2_PHY_158_DATA 0x00000000 +#define DDRSS2_PHY_159_DATA 0x00000000 +#define DDRSS2_PHY_160_DATA 0x00000000 +#define DDRSS2_PHY_161_DATA 0x00000000 +#define DDRSS2_PHY_162_DATA 0x00000000 +#define DDRSS2_PHY_163_DATA 0x00000000 +#define DDRSS2_PHY_164_DATA 0x00000000 +#define DDRSS2_PHY_165_DATA 0x00000000 +#define DDRSS2_PHY_166_DATA 0x00000000 +#define DDRSS2_PHY_167_DATA 0x00000000 +#define DDRSS2_PHY_168_DATA 0x00000000 +#define DDRSS2_PHY_169_DATA 0x00000000 +#define DDRSS2_PHY_170_DATA 0x00000000 +#define DDRSS2_PHY_171_DATA 0x00000000 +#define DDRSS2_PHY_172_DATA 0x00000000 +#define DDRSS2_PHY_173_DATA 0x00000000 +#define DDRSS2_PHY_174_DATA 0x00000000 +#define DDRSS2_PHY_175_DATA 0x00000000 +#define DDRSS2_PHY_176_DATA 0x00000000 +#define DDRSS2_PHY_177_DATA 0x00000000 +#define DDRSS2_PHY_178_DATA 0x00000000 +#define DDRSS2_PHY_179_DATA 0x00000000 +#define DDRSS2_PHY_180_DATA 0x00000000 +#define DDRSS2_PHY_181_DATA 0x00000000 +#define DDRSS2_PHY_182_DATA 0x00000000 +#define DDRSS2_PHY_183_DATA 0x00000000 +#define DDRSS2_PHY_184_DATA 0x00000000 +#define DDRSS2_PHY_185_DATA 0x00000000 +#define DDRSS2_PHY_186_DATA 0x00000000 +#define DDRSS2_PHY_187_DATA 0x00000000 +#define DDRSS2_PHY_188_DATA 0x00000000 +#define DDRSS2_PHY_189_DATA 0x00000000 +#define DDRSS2_PHY_190_DATA 0x00000000 +#define DDRSS2_PHY_191_DATA 0x00000000 +#define DDRSS2_PHY_192_DATA 0x00000000 +#define DDRSS2_PHY_193_DATA 0x00000000 +#define DDRSS2_PHY_194_DATA 0x00000000 +#define DDRSS2_PHY_195_DATA 0x00000000 +#define DDRSS2_PHY_196_DATA 0x00000000 +#define DDRSS2_PHY_197_DATA 0x00000000 +#define DDRSS2_PHY_198_DATA 0x00000000 +#define DDRSS2_PHY_199_DATA 0x00000000 +#define DDRSS2_PHY_200_DATA 0x00000000 +#define DDRSS2_PHY_201_DATA 0x00000000 +#define DDRSS2_PHY_202_DATA 0x00000000 +#define DDRSS2_PHY_203_DATA 0x00000000 +#define DDRSS2_PHY_204_DATA 0x00000000 +#define DDRSS2_PHY_205_DATA 0x00000000 +#define DDRSS2_PHY_206_DATA 0x00000000 +#define DDRSS2_PHY_207_DATA 0x00000000 +#define DDRSS2_PHY_208_DATA 0x00000000 +#define DDRSS2_PHY_209_DATA 0x00000000 +#define DDRSS2_PHY_210_DATA 0x00000000 +#define DDRSS2_PHY_211_DATA 0x00000000 +#define DDRSS2_PHY_212_DATA 0x00000000 +#define DDRSS2_PHY_213_DATA 0x00000000 +#define DDRSS2_PHY_214_DATA 0x00000000 +#define DDRSS2_PHY_215_DATA 0x00000000 +#define DDRSS2_PHY_216_DATA 0x00000000 +#define DDRSS2_PHY_217_DATA 0x00000000 +#define DDRSS2_PHY_218_DATA 0x00000000 +#define DDRSS2_PHY_219_DATA 0x00000000 +#define DDRSS2_PHY_220_DATA 0x00000000 +#define DDRSS2_PHY_221_DATA 0x00000000 +#define DDRSS2_PHY_222_DATA 0x00000000 +#define DDRSS2_PHY_223_DATA 0x00000000 +#define DDRSS2_PHY_224_DATA 0x00000000 +#define DDRSS2_PHY_225_DATA 0x00000000 +#define DDRSS2_PHY_226_DATA 0x00000000 +#define DDRSS2_PHY_227_DATA 0x00000000 +#define DDRSS2_PHY_228_DATA 0x00000000 +#define DDRSS2_PHY_229_DATA 0x00000000 +#define DDRSS2_PHY_230_DATA 0x00000000 +#define DDRSS2_PHY_231_DATA 0x00000000 +#define DDRSS2_PHY_232_DATA 0x00000000 +#define DDRSS2_PHY_233_DATA 0x00000000 +#define DDRSS2_PHY_234_DATA 0x00000000 +#define DDRSS2_PHY_235_DATA 0x00000000 +#define DDRSS2_PHY_236_DATA 0x00000000 +#define DDRSS2_PHY_237_DATA 0x00000000 +#define DDRSS2_PHY_238_DATA 0x00000000 +#define DDRSS2_PHY_239_DATA 0x00000000 +#define DDRSS2_PHY_240_DATA 0x00000000 +#define DDRSS2_PHY_241_DATA 0x00000000 +#define DDRSS2_PHY_242_DATA 0x00000000 +#define DDRSS2_PHY_243_DATA 0x00000000 +#define DDRSS2_PHY_244_DATA 0x00000000 +#define DDRSS2_PHY_245_DATA 0x00000000 +#define DDRSS2_PHY_246_DATA 0x00000000 +#define DDRSS2_PHY_247_DATA 0x00000000 +#define DDRSS2_PHY_248_DATA 0x00000000 +#define DDRSS2_PHY_249_DATA 0x00000000 +#define DDRSS2_PHY_250_DATA 0x00000000 +#define DDRSS2_PHY_251_DATA 0x00000000 +#define DDRSS2_PHY_252_DATA 0x00000000 +#define DDRSS2_PHY_253_DATA 0x00000000 +#define DDRSS2_PHY_254_DATA 0x00000000 +#define DDRSS2_PHY_255_DATA 0x00000000 +#define DDRSS2_PHY_256_DATA 0x000004F0 +#define DDRSS2_PHY_257_DATA 0x00000000 +#define DDRSS2_PHY_258_DATA 0x00030200 +#define DDRSS2_PHY_259_DATA 0x00000000 +#define DDRSS2_PHY_260_DATA 0x00000000 +#define DDRSS2_PHY_261_DATA 0x01030000 +#define DDRSS2_PHY_262_DATA 0x00010000 +#define DDRSS2_PHY_263_DATA 0x01030004 +#define DDRSS2_PHY_264_DATA 0x01000000 +#define DDRSS2_PHY_265_DATA 0x00000000 +#define DDRSS2_PHY_266_DATA 0x00000000 +#define DDRSS2_PHY_267_DATA 0x01000001 +#define DDRSS2_PHY_268_DATA 0x00000200 +#define DDRSS2_PHY_269_DATA 0x000800C0 +#define DDRSS2_PHY_270_DATA 0x060100CC +#define DDRSS2_PHY_271_DATA 0x00030066 +#define DDRSS2_PHY_272_DATA 0x00000000 +#define DDRSS2_PHY_273_DATA 0x00000301 +#define DDRSS2_PHY_274_DATA 0x0000AAAA +#define DDRSS2_PHY_275_DATA 0x00005555 +#define DDRSS2_PHY_276_DATA 0x0000B5B5 +#define DDRSS2_PHY_277_DATA 0x00004A4A +#define DDRSS2_PHY_278_DATA 0x00005656 +#define DDRSS2_PHY_279_DATA 0x0000A9A9 +#define DDRSS2_PHY_280_DATA 0x0000A9A9 +#define DDRSS2_PHY_281_DATA 0x0000B5B5 +#define DDRSS2_PHY_282_DATA 0x00000000 +#define DDRSS2_PHY_283_DATA 0x00000000 +#define DDRSS2_PHY_284_DATA 0x2A000000 +#define DDRSS2_PHY_285_DATA 0x00000808 +#define DDRSS2_PHY_286_DATA 0x0F000000 +#define DDRSS2_PHY_287_DATA 0x00000F08 +#define DDRSS2_PHY_288_DATA 0x10400000 +#define DDRSS2_PHY_289_DATA 0x0C002006 +#define DDRSS2_PHY_290_DATA 0x00000000 +#define DDRSS2_PHY_291_DATA 0x00000000 +#define DDRSS2_PHY_292_DATA 0x55555555 +#define DDRSS2_PHY_293_DATA 0xAAAAAAAA +#define DDRSS2_PHY_294_DATA 0x55555555 +#define DDRSS2_PHY_295_DATA 0xAAAAAAAA +#define DDRSS2_PHY_296_DATA 0x00005555 +#define DDRSS2_PHY_297_DATA 0x01000100 +#define DDRSS2_PHY_298_DATA 0x00800180 +#define DDRSS2_PHY_299_DATA 0x00000000 +#define DDRSS2_PHY_300_DATA 0x00000000 +#define DDRSS2_PHY_301_DATA 0x00000000 +#define DDRSS2_PHY_302_DATA 0x00000000 +#define DDRSS2_PHY_303_DATA 0x00000000 +#define DDRSS2_PHY_304_DATA 0x00000000 +#define DDRSS2_PHY_305_DATA 0x00000000 +#define DDRSS2_PHY_306_DATA 0x00000000 +#define DDRSS2_PHY_307_DATA 0x00000000 +#define DDRSS2_PHY_308_DATA 0x00000000 +#define DDRSS2_PHY_309_DATA 0x00000000 +#define DDRSS2_PHY_310_DATA 0x00000000 +#define DDRSS2_PHY_311_DATA 0x00000000 +#define DDRSS2_PHY_312_DATA 0x00000000 +#define DDRSS2_PHY_313_DATA 0x00000000 +#define DDRSS2_PHY_314_DATA 0x00000000 +#define DDRSS2_PHY_315_DATA 0x00000000 +#define DDRSS2_PHY_316_DATA 0x00000000 +#define DDRSS2_PHY_317_DATA 0x00000000 +#define DDRSS2_PHY_318_DATA 0x00000000 +#define DDRSS2_PHY_319_DATA 0x00000000 +#define DDRSS2_PHY_320_DATA 0x00000000 +#define DDRSS2_PHY_321_DATA 0x00000000 +#define DDRSS2_PHY_322_DATA 0x00000104 +#define DDRSS2_PHY_323_DATA 0x00000120 +#define DDRSS2_PHY_324_DATA 0x00000000 +#define DDRSS2_PHY_325_DATA 0x00000000 +#define DDRSS2_PHY_326_DATA 0x00000000 +#define DDRSS2_PHY_327_DATA 0x00000000 +#define DDRSS2_PHY_328_DATA 0x00000000 +#define DDRSS2_PHY_329_DATA 0x00000000 +#define DDRSS2_PHY_330_DATA 0x00000000 +#define DDRSS2_PHY_331_DATA 0x00000001 +#define DDRSS2_PHY_332_DATA 0x07FF0000 +#define DDRSS2_PHY_333_DATA 0x0080081F +#define DDRSS2_PHY_334_DATA 0x00081020 +#define DDRSS2_PHY_335_DATA 0x04010000 +#define DDRSS2_PHY_336_DATA 0x00000000 +#define DDRSS2_PHY_337_DATA 0x00000000 +#define DDRSS2_PHY_338_DATA 0x00000000 +#define DDRSS2_PHY_339_DATA 0x00000100 +#define DDRSS2_PHY_340_DATA 0x01CC0C01 +#define DDRSS2_PHY_341_DATA 0x1003CC0C +#define DDRSS2_PHY_342_DATA 0x20000140 +#define DDRSS2_PHY_343_DATA 0x07FF0200 +#define DDRSS2_PHY_344_DATA 0x0000DD01 +#define DDRSS2_PHY_345_DATA 0x10100303 +#define DDRSS2_PHY_346_DATA 0x10101010 +#define DDRSS2_PHY_347_DATA 0x10101010 +#define DDRSS2_PHY_348_DATA 0x00021010 +#define DDRSS2_PHY_349_DATA 0x00100010 +#define DDRSS2_PHY_350_DATA 0x00100010 +#define DDRSS2_PHY_351_DATA 0x00100010 +#define DDRSS2_PHY_352_DATA 0x00100010 +#define DDRSS2_PHY_353_DATA 0x00050010 +#define DDRSS2_PHY_354_DATA 0x51517041 +#define DDRSS2_PHY_355_DATA 0x31C06001 +#define DDRSS2_PHY_356_DATA 0x07AB01AB +#define DDRSS2_PHY_357_DATA 0x00C0C001 +#define DDRSS2_PHY_358_DATA 0x0E0D0101 +#define DDRSS2_PHY_359_DATA 0x10001000 +#define DDRSS2_PHY_360_DATA 0x0C083E42 +#define DDRSS2_PHY_361_DATA 0x0F0C3701 +#define DDRSS2_PHY_362_DATA 0x01000140 +#define DDRSS2_PHY_363_DATA 0x0C000420 +#define DDRSS2_PHY_364_DATA 0x00000198 +#define DDRSS2_PHY_365_DATA 0x0A0000D0 +#define DDRSS2_PHY_366_DATA 0x00030200 +#define DDRSS2_PHY_367_DATA 0x02800000 +#define DDRSS2_PHY_368_DATA 0x80800000 +#define DDRSS2_PHY_369_DATA 0x000E2010 +#define DDRSS2_PHY_370_DATA 0x76543210 +#define DDRSS2_PHY_371_DATA 0x00000008 +#define DDRSS2_PHY_372_DATA 0x02800280 +#define DDRSS2_PHY_373_DATA 0x02800280 +#define DDRSS2_PHY_374_DATA 0x02800280 +#define DDRSS2_PHY_375_DATA 0x02800280 +#define DDRSS2_PHY_376_DATA 0x00000280 +#define DDRSS2_PHY_377_DATA 0x0000A000 +#define DDRSS2_PHY_378_DATA 0x00A000A0 +#define DDRSS2_PHY_379_DATA 0x00A000A0 +#define DDRSS2_PHY_380_DATA 0x00A000A0 +#define DDRSS2_PHY_381_DATA 0x00A000A0 +#define DDRSS2_PHY_382_DATA 0x00A000A0 +#define DDRSS2_PHY_383_DATA 0x00A000A0 +#define DDRSS2_PHY_384_DATA 0x00A000A0 +#define DDRSS2_PHY_385_DATA 0x00A000A0 +#define DDRSS2_PHY_386_DATA 0x01C200A0 +#define DDRSS2_PHY_387_DATA 0x01A00005 +#define DDRSS2_PHY_388_DATA 0x00000000 +#define DDRSS2_PHY_389_DATA 0x00000000 +#define DDRSS2_PHY_390_DATA 0x00080200 +#define DDRSS2_PHY_391_DATA 0x00000000 +#define DDRSS2_PHY_392_DATA 0x20202000 +#define DDRSS2_PHY_393_DATA 0x20202020 +#define DDRSS2_PHY_394_DATA 0xF0F02020 +#define DDRSS2_PHY_395_DATA 0x00000000 +#define DDRSS2_PHY_396_DATA 0x00000000 +#define DDRSS2_PHY_397_DATA 0x00000000 +#define DDRSS2_PHY_398_DATA 0x00000000 +#define DDRSS2_PHY_399_DATA 0x00000000 +#define DDRSS2_PHY_400_DATA 0x00000000 +#define DDRSS2_PHY_401_DATA 0x00000000 +#define DDRSS2_PHY_402_DATA 0x00000000 +#define DDRSS2_PHY_403_DATA 0x00000000 +#define DDRSS2_PHY_404_DATA 0x00000000 +#define DDRSS2_PHY_405_DATA 0x00000000 +#define DDRSS2_PHY_406_DATA 0x00000000 +#define DDRSS2_PHY_407_DATA 0x00000000 +#define DDRSS2_PHY_408_DATA 0x00000000 +#define DDRSS2_PHY_409_DATA 0x00000000 +#define DDRSS2_PHY_410_DATA 0x00000000 +#define DDRSS2_PHY_411_DATA 0x00000000 +#define DDRSS2_PHY_412_DATA 0x00000000 +#define DDRSS2_PHY_413_DATA 0x00000000 +#define DDRSS2_PHY_414_DATA 0x00000000 +#define DDRSS2_PHY_415_DATA 0x00000000 +#define DDRSS2_PHY_416_DATA 0x00000000 +#define DDRSS2_PHY_417_DATA 0x00000000 +#define DDRSS2_PHY_418_DATA 0x00000000 +#define DDRSS2_PHY_419_DATA 0x00000000 +#define DDRSS2_PHY_420_DATA 0x00000000 +#define DDRSS2_PHY_421_DATA 0x00000000 +#define DDRSS2_PHY_422_DATA 0x00000000 +#define DDRSS2_PHY_423_DATA 0x00000000 +#define DDRSS2_PHY_424_DATA 0x00000000 +#define DDRSS2_PHY_425_DATA 0x00000000 +#define DDRSS2_PHY_426_DATA 0x00000000 +#define DDRSS2_PHY_427_DATA 0x00000000 +#define DDRSS2_PHY_428_DATA 0x00000000 +#define DDRSS2_PHY_429_DATA 0x00000000 +#define DDRSS2_PHY_430_DATA 0x00000000 +#define DDRSS2_PHY_431_DATA 0x00000000 +#define DDRSS2_PHY_432_DATA 0x00000000 +#define DDRSS2_PHY_433_DATA 0x00000000 +#define DDRSS2_PHY_434_DATA 0x00000000 +#define DDRSS2_PHY_435_DATA 0x00000000 +#define DDRSS2_PHY_436_DATA 0x00000000 +#define DDRSS2_PHY_437_DATA 0x00000000 +#define DDRSS2_PHY_438_DATA 0x00000000 +#define DDRSS2_PHY_439_DATA 0x00000000 +#define DDRSS2_PHY_440_DATA 0x00000000 +#define DDRSS2_PHY_441_DATA 0x00000000 +#define DDRSS2_PHY_442_DATA 0x00000000 +#define DDRSS2_PHY_443_DATA 0x00000000 +#define DDRSS2_PHY_444_DATA 0x00000000 +#define DDRSS2_PHY_445_DATA 0x00000000 +#define DDRSS2_PHY_446_DATA 0x00000000 +#define DDRSS2_PHY_447_DATA 0x00000000 +#define DDRSS2_PHY_448_DATA 0x00000000 +#define DDRSS2_PHY_449_DATA 0x00000000 +#define DDRSS2_PHY_450_DATA 0x00000000 +#define DDRSS2_PHY_451_DATA 0x00000000 +#define DDRSS2_PHY_452_DATA 0x00000000 +#define DDRSS2_PHY_453_DATA 0x00000000 +#define DDRSS2_PHY_454_DATA 0x00000000 +#define DDRSS2_PHY_455_DATA 0x00000000 +#define DDRSS2_PHY_456_DATA 0x00000000 +#define DDRSS2_PHY_457_DATA 0x00000000 +#define DDRSS2_PHY_458_DATA 0x00000000 +#define DDRSS2_PHY_459_DATA 0x00000000 +#define DDRSS2_PHY_460_DATA 0x00000000 +#define DDRSS2_PHY_461_DATA 0x00000000 +#define DDRSS2_PHY_462_DATA 0x00000000 +#define DDRSS2_PHY_463_DATA 0x00000000 +#define DDRSS2_PHY_464_DATA 0x00000000 +#define DDRSS2_PHY_465_DATA 0x00000000 +#define DDRSS2_PHY_466_DATA 0x00000000 +#define DDRSS2_PHY_467_DATA 0x00000000 +#define DDRSS2_PHY_468_DATA 0x00000000 +#define DDRSS2_PHY_469_DATA 0x00000000 +#define DDRSS2_PHY_470_DATA 0x00000000 +#define DDRSS2_PHY_471_DATA 0x00000000 +#define DDRSS2_PHY_472_DATA 0x00000000 +#define DDRSS2_PHY_473_DATA 0x00000000 +#define DDRSS2_PHY_474_DATA 0x00000000 +#define DDRSS2_PHY_475_DATA 0x00000000 +#define DDRSS2_PHY_476_DATA 0x00000000 +#define DDRSS2_PHY_477_DATA 0x00000000 +#define DDRSS2_PHY_478_DATA 0x00000000 +#define DDRSS2_PHY_479_DATA 0x00000000 +#define DDRSS2_PHY_480_DATA 0x00000000 +#define DDRSS2_PHY_481_DATA 0x00000000 +#define DDRSS2_PHY_482_DATA 0x00000000 +#define DDRSS2_PHY_483_DATA 0x00000000 +#define DDRSS2_PHY_484_DATA 0x00000000 +#define DDRSS2_PHY_485_DATA 0x00000000 +#define DDRSS2_PHY_486_DATA 0x00000000 +#define DDRSS2_PHY_487_DATA 0x00000000 +#define DDRSS2_PHY_488_DATA 0x00000000 +#define DDRSS2_PHY_489_DATA 0x00000000 +#define DDRSS2_PHY_490_DATA 0x00000000 +#define DDRSS2_PHY_491_DATA 0x00000000 +#define DDRSS2_PHY_492_DATA 0x00000000 +#define DDRSS2_PHY_493_DATA 0x00000000 +#define DDRSS2_PHY_494_DATA 0x00000000 +#define DDRSS2_PHY_495_DATA 0x00000000 +#define DDRSS2_PHY_496_DATA 0x00000000 +#define DDRSS2_PHY_497_DATA 0x00000000 +#define DDRSS2_PHY_498_DATA 0x00000000 +#define DDRSS2_PHY_499_DATA 0x00000000 +#define DDRSS2_PHY_500_DATA 0x00000000 +#define DDRSS2_PHY_501_DATA 0x00000000 +#define DDRSS2_PHY_502_DATA 0x00000000 +#define DDRSS2_PHY_503_DATA 0x00000000 +#define DDRSS2_PHY_504_DATA 0x00000000 +#define DDRSS2_PHY_505_DATA 0x00000000 +#define DDRSS2_PHY_506_DATA 0x00000000 +#define DDRSS2_PHY_507_DATA 0x00000000 +#define DDRSS2_PHY_508_DATA 0x00000000 +#define DDRSS2_PHY_509_DATA 0x00000000 +#define DDRSS2_PHY_510_DATA 0x00000000 +#define DDRSS2_PHY_511_DATA 0x00000000 +#define DDRSS2_PHY_512_DATA 0x000004F0 +#define DDRSS2_PHY_513_DATA 0x00000000 +#define DDRSS2_PHY_514_DATA 0x00030200 +#define DDRSS2_PHY_515_DATA 0x00000000 +#define DDRSS2_PHY_516_DATA 0x00000000 +#define DDRSS2_PHY_517_DATA 0x01030000 +#define DDRSS2_PHY_518_DATA 0x00010000 +#define DDRSS2_PHY_519_DATA 0x01030004 +#define DDRSS2_PHY_520_DATA 0x01000000 +#define DDRSS2_PHY_521_DATA 0x00000000 +#define DDRSS2_PHY_522_DATA 0x00000000 +#define DDRSS2_PHY_523_DATA 0x01000001 +#define DDRSS2_PHY_524_DATA 0x00000200 +#define DDRSS2_PHY_525_DATA 0x000800C0 +#define DDRSS2_PHY_526_DATA 0x060100CC +#define DDRSS2_PHY_527_DATA 0x00030066 +#define DDRSS2_PHY_528_DATA 0x00000000 +#define DDRSS2_PHY_529_DATA 0x00000301 +#define DDRSS2_PHY_530_DATA 0x0000AAAA +#define DDRSS2_PHY_531_DATA 0x00005555 +#define DDRSS2_PHY_532_DATA 0x0000B5B5 +#define DDRSS2_PHY_533_DATA 0x00004A4A +#define DDRSS2_PHY_534_DATA 0x00005656 +#define DDRSS2_PHY_535_DATA 0x0000A9A9 +#define DDRSS2_PHY_536_DATA 0x0000A9A9 +#define DDRSS2_PHY_537_DATA 0x0000B5B5 +#define DDRSS2_PHY_538_DATA 0x00000000 +#define DDRSS2_PHY_539_DATA 0x00000000 +#define DDRSS2_PHY_540_DATA 0x2A000000 +#define DDRSS2_PHY_541_DATA 0x00000808 +#define DDRSS2_PHY_542_DATA 0x0F000000 +#define DDRSS2_PHY_543_DATA 0x00000F08 +#define DDRSS2_PHY_544_DATA 0x10400000 +#define DDRSS2_PHY_545_DATA 0x0C002006 +#define DDRSS2_PHY_546_DATA 0x00000000 +#define DDRSS2_PHY_547_DATA 0x00000000 +#define DDRSS2_PHY_548_DATA 0x55555555 +#define DDRSS2_PHY_549_DATA 0xAAAAAAAA +#define DDRSS2_PHY_550_DATA 0x55555555 +#define DDRSS2_PHY_551_DATA 0xAAAAAAAA +#define DDRSS2_PHY_552_DATA 0x00005555 +#define DDRSS2_PHY_553_DATA 0x01000100 +#define DDRSS2_PHY_554_DATA 0x00800180 +#define DDRSS2_PHY_555_DATA 0x00000001 +#define DDRSS2_PHY_556_DATA 0x00000000 +#define DDRSS2_PHY_557_DATA 0x00000000 +#define DDRSS2_PHY_558_DATA 0x00000000 +#define DDRSS2_PHY_559_DATA 0x00000000 +#define DDRSS2_PHY_560_DATA 0x00000000 +#define DDRSS2_PHY_561_DATA 0x00000000 +#define DDRSS2_PHY_562_DATA 0x00000000 +#define DDRSS2_PHY_563_DATA 0x00000000 +#define DDRSS2_PHY_564_DATA 0x00000000 +#define DDRSS2_PHY_565_DATA 0x00000000 +#define DDRSS2_PHY_566_DATA 0x00000000 +#define DDRSS2_PHY_567_DATA 0x00000000 +#define DDRSS2_PHY_568_DATA 0x00000000 +#define DDRSS2_PHY_569_DATA 0x00000000 +#define DDRSS2_PHY_570_DATA 0x00000000 +#define DDRSS2_PHY_571_DATA 0x00000000 +#define DDRSS2_PHY_572_DATA 0x00000000 +#define DDRSS2_PHY_573_DATA 0x00000000 +#define DDRSS2_PHY_574_DATA 0x00000000 +#define DDRSS2_PHY_575_DATA 0x00000000 +#define DDRSS2_PHY_576_DATA 0x00000000 +#define DDRSS2_PHY_577_DATA 0x00000000 +#define DDRSS2_PHY_578_DATA 0x00000104 +#define DDRSS2_PHY_579_DATA 0x00000120 +#define DDRSS2_PHY_580_DATA 0x00000000 +#define DDRSS2_PHY_581_DATA 0x00000000 +#define DDRSS2_PHY_582_DATA 0x00000000 +#define DDRSS2_PHY_583_DATA 0x00000000 +#define DDRSS2_PHY_584_DATA 0x00000000 +#define DDRSS2_PHY_585_DATA 0x00000000 +#define DDRSS2_PHY_586_DATA 0x00000000 +#define DDRSS2_PHY_587_DATA 0x00000001 +#define DDRSS2_PHY_588_DATA 0x07FF0000 +#define DDRSS2_PHY_589_DATA 0x0080081F +#define DDRSS2_PHY_590_DATA 0x00081020 +#define DDRSS2_PHY_591_DATA 0x04010000 +#define DDRSS2_PHY_592_DATA 0x00000000 +#define DDRSS2_PHY_593_DATA 0x00000000 +#define DDRSS2_PHY_594_DATA 0x00000000 +#define DDRSS2_PHY_595_DATA 0x00000100 +#define DDRSS2_PHY_596_DATA 0x01CC0C01 +#define DDRSS2_PHY_597_DATA 0x1003CC0C +#define DDRSS2_PHY_598_DATA 0x20000140 +#define DDRSS2_PHY_599_DATA 0x07FF0200 +#define DDRSS2_PHY_600_DATA 0x0000DD01 +#define DDRSS2_PHY_601_DATA 0x10100303 +#define DDRSS2_PHY_602_DATA 0x10101010 +#define DDRSS2_PHY_603_DATA 0x10101010 +#define DDRSS2_PHY_604_DATA 0x00021010 +#define DDRSS2_PHY_605_DATA 0x00100010 +#define DDRSS2_PHY_606_DATA 0x00100010 +#define DDRSS2_PHY_607_DATA 0x00100010 +#define DDRSS2_PHY_608_DATA 0x00100010 +#define DDRSS2_PHY_609_DATA 0x00050010 +#define DDRSS2_PHY_610_DATA 0x51517041 +#define DDRSS2_PHY_611_DATA 0x31C06001 +#define DDRSS2_PHY_612_DATA 0x07AB01AB +#define DDRSS2_PHY_613_DATA 0x00C0C001 +#define DDRSS2_PHY_614_DATA 0x0E0D0101 +#define DDRSS2_PHY_615_DATA 0x10001000 +#define DDRSS2_PHY_616_DATA 0x0C083E42 +#define DDRSS2_PHY_617_DATA 0x0F0C3701 +#define DDRSS2_PHY_618_DATA 0x01000140 +#define DDRSS2_PHY_619_DATA 0x0C000420 +#define DDRSS2_PHY_620_DATA 0x00000198 +#define DDRSS2_PHY_621_DATA 0x0A0000D0 +#define DDRSS2_PHY_622_DATA 0x00030200 +#define DDRSS2_PHY_623_DATA 0x02800000 +#define DDRSS2_PHY_624_DATA 0x80800000 +#define DDRSS2_PHY_625_DATA 0x000E2010 +#define DDRSS2_PHY_626_DATA 0x76543210 +#define DDRSS2_PHY_627_DATA 0x00000008 +#define DDRSS2_PHY_628_DATA 0x02800280 +#define DDRSS2_PHY_629_DATA 0x02800280 +#define DDRSS2_PHY_630_DATA 0x02800280 +#define DDRSS2_PHY_631_DATA 0x02800280 +#define DDRSS2_PHY_632_DATA 0x00000280 +#define DDRSS2_PHY_633_DATA 0x0000A000 +#define DDRSS2_PHY_634_DATA 0x00A000A0 +#define DDRSS2_PHY_635_DATA 0x00A000A0 +#define DDRSS2_PHY_636_DATA 0x00A000A0 +#define DDRSS2_PHY_637_DATA 0x00A000A0 +#define DDRSS2_PHY_638_DATA 0x00A000A0 +#define DDRSS2_PHY_639_DATA 0x00A000A0 +#define DDRSS2_PHY_640_DATA 0x00A000A0 +#define DDRSS2_PHY_641_DATA 0x00A000A0 +#define DDRSS2_PHY_642_DATA 0x01C200A0 +#define DDRSS2_PHY_643_DATA 0x01A00005 +#define DDRSS2_PHY_644_DATA 0x00000000 +#define DDRSS2_PHY_645_DATA 0x00000000 +#define DDRSS2_PHY_646_DATA 0x00080200 +#define DDRSS2_PHY_647_DATA 0x00000000 +#define DDRSS2_PHY_648_DATA 0x20202000 +#define DDRSS2_PHY_649_DATA 0x20202020 +#define DDRSS2_PHY_650_DATA 0xF0F02020 +#define DDRSS2_PHY_651_DATA 0x00000000 +#define DDRSS2_PHY_652_DATA 0x00000000 +#define DDRSS2_PHY_653_DATA 0x00000000 +#define DDRSS2_PHY_654_DATA 0x00000000 +#define DDRSS2_PHY_655_DATA 0x00000000 +#define DDRSS2_PHY_656_DATA 0x00000000 +#define DDRSS2_PHY_657_DATA 0x00000000 +#define DDRSS2_PHY_658_DATA 0x00000000 +#define DDRSS2_PHY_659_DATA 0x00000000 +#define DDRSS2_PHY_660_DATA 0x00000000 +#define DDRSS2_PHY_661_DATA 0x00000000 +#define DDRSS2_PHY_662_DATA 0x00000000 +#define DDRSS2_PHY_663_DATA 0x00000000 +#define DDRSS2_PHY_664_DATA 0x00000000 +#define DDRSS2_PHY_665_DATA 0x00000000 +#define DDRSS2_PHY_666_DATA 0x00000000 +#define DDRSS2_PHY_667_DATA 0x00000000 +#define DDRSS2_PHY_668_DATA 0x00000000 +#define DDRSS2_PHY_669_DATA 0x00000000 +#define DDRSS2_PHY_670_DATA 0x00000000 +#define DDRSS2_PHY_671_DATA 0x00000000 +#define DDRSS2_PHY_672_DATA 0x00000000 +#define DDRSS2_PHY_673_DATA 0x00000000 +#define DDRSS2_PHY_674_DATA 0x00000000 +#define DDRSS2_PHY_675_DATA 0x00000000 +#define DDRSS2_PHY_676_DATA 0x00000000 +#define DDRSS2_PHY_677_DATA 0x00000000 +#define DDRSS2_PHY_678_DATA 0x00000000 +#define DDRSS2_PHY_679_DATA 0x00000000 +#define DDRSS2_PHY_680_DATA 0x00000000 +#define DDRSS2_PHY_681_DATA 0x00000000 +#define DDRSS2_PHY_682_DATA 0x00000000 +#define DDRSS2_PHY_683_DATA 0x00000000 +#define DDRSS2_PHY_684_DATA 0x00000000 +#define DDRSS2_PHY_685_DATA 0x00000000 +#define DDRSS2_PHY_686_DATA 0x00000000 +#define DDRSS2_PHY_687_DATA 0x00000000 +#define DDRSS2_PHY_688_DATA 0x00000000 +#define DDRSS2_PHY_689_DATA 0x00000000 +#define DDRSS2_PHY_690_DATA 0x00000000 +#define DDRSS2_PHY_691_DATA 0x00000000 +#define DDRSS2_PHY_692_DATA 0x00000000 +#define DDRSS2_PHY_693_DATA 0x00000000 +#define DDRSS2_PHY_694_DATA 0x00000000 +#define DDRSS2_PHY_695_DATA 0x00000000 +#define DDRSS2_PHY_696_DATA 0x00000000 +#define DDRSS2_PHY_697_DATA 0x00000000 +#define DDRSS2_PHY_698_DATA 0x00000000 +#define DDRSS2_PHY_699_DATA 0x00000000 +#define DDRSS2_PHY_700_DATA 0x00000000 +#define DDRSS2_PHY_701_DATA 0x00000000 +#define DDRSS2_PHY_702_DATA 0x00000000 +#define DDRSS2_PHY_703_DATA 0x00000000 +#define DDRSS2_PHY_704_DATA 0x00000000 +#define DDRSS2_PHY_705_DATA 0x00000000 +#define DDRSS2_PHY_706_DATA 0x00000000 +#define DDRSS2_PHY_707_DATA 0x00000000 +#define DDRSS2_PHY_708_DATA 0x00000000 +#define DDRSS2_PHY_709_DATA 0x00000000 +#define DDRSS2_PHY_710_DATA 0x00000000 +#define DDRSS2_PHY_711_DATA 0x00000000 +#define DDRSS2_PHY_712_DATA 0x00000000 +#define DDRSS2_PHY_713_DATA 0x00000000 +#define DDRSS2_PHY_714_DATA 0x00000000 +#define DDRSS2_PHY_715_DATA 0x00000000 +#define DDRSS2_PHY_716_DATA 0x00000000 +#define DDRSS2_PHY_717_DATA 0x00000000 +#define DDRSS2_PHY_718_DATA 0x00000000 +#define DDRSS2_PHY_719_DATA 0x00000000 +#define DDRSS2_PHY_720_DATA 0x00000000 +#define DDRSS2_PHY_721_DATA 0x00000000 +#define DDRSS2_PHY_722_DATA 0x00000000 +#define DDRSS2_PHY_723_DATA 0x00000000 +#define DDRSS2_PHY_724_DATA 0x00000000 +#define DDRSS2_PHY_725_DATA 0x00000000 +#define DDRSS2_PHY_726_DATA 0x00000000 +#define DDRSS2_PHY_727_DATA 0x00000000 +#define DDRSS2_PHY_728_DATA 0x00000000 +#define DDRSS2_PHY_729_DATA 0x00000000 +#define DDRSS2_PHY_730_DATA 0x00000000 +#define DDRSS2_PHY_731_DATA 0x00000000 +#define DDRSS2_PHY_732_DATA 0x00000000 +#define DDRSS2_PHY_733_DATA 0x00000000 +#define DDRSS2_PHY_734_DATA 0x00000000 +#define DDRSS2_PHY_735_DATA 0x00000000 +#define DDRSS2_PHY_736_DATA 0x00000000 +#define DDRSS2_PHY_737_DATA 0x00000000 +#define DDRSS2_PHY_738_DATA 0x00000000 +#define DDRSS2_PHY_739_DATA 0x00000000 +#define DDRSS2_PHY_740_DATA 0x00000000 +#define DDRSS2_PHY_741_DATA 0x00000000 +#define DDRSS2_PHY_742_DATA 0x00000000 +#define DDRSS2_PHY_743_DATA 0x00000000 +#define DDRSS2_PHY_744_DATA 0x00000000 +#define DDRSS2_PHY_745_DATA 0x00000000 +#define DDRSS2_PHY_746_DATA 0x00000000 +#define DDRSS2_PHY_747_DATA 0x00000000 +#define DDRSS2_PHY_748_DATA 0x00000000 +#define DDRSS2_PHY_749_DATA 0x00000000 +#define DDRSS2_PHY_750_DATA 0x00000000 +#define DDRSS2_PHY_751_DATA 0x00000000 +#define DDRSS2_PHY_752_DATA 0x00000000 +#define DDRSS2_PHY_753_DATA 0x00000000 +#define DDRSS2_PHY_754_DATA 0x00000000 +#define DDRSS2_PHY_755_DATA 0x00000000 +#define DDRSS2_PHY_756_DATA 0x00000000 +#define DDRSS2_PHY_757_DATA 0x00000000 +#define DDRSS2_PHY_758_DATA 0x00000000 +#define DDRSS2_PHY_759_DATA 0x00000000 +#define DDRSS2_PHY_760_DATA 0x00000000 +#define DDRSS2_PHY_761_DATA 0x00000000 +#define DDRSS2_PHY_762_DATA 0x00000000 +#define DDRSS2_PHY_763_DATA 0x00000000 +#define DDRSS2_PHY_764_DATA 0x00000000 +#define DDRSS2_PHY_765_DATA 0x00000000 +#define DDRSS2_PHY_766_DATA 0x00000000 +#define DDRSS2_PHY_767_DATA 0x00000000 +#define DDRSS2_PHY_768_DATA 0x000004F0 +#define DDRSS2_PHY_769_DATA 0x00000000 +#define DDRSS2_PHY_770_DATA 0x00030200 +#define DDRSS2_PHY_771_DATA 0x00000000 +#define DDRSS2_PHY_772_DATA 0x00000000 +#define DDRSS2_PHY_773_DATA 0x01030000 +#define DDRSS2_PHY_774_DATA 0x00010000 +#define DDRSS2_PHY_775_DATA 0x01030004 +#define DDRSS2_PHY_776_DATA 0x01000000 +#define DDRSS2_PHY_777_DATA 0x00000000 +#define DDRSS2_PHY_778_DATA 0x00000000 +#define DDRSS2_PHY_779_DATA 0x01000001 +#define DDRSS2_PHY_780_DATA 0x00000200 +#define DDRSS2_PHY_781_DATA 0x000800C0 +#define DDRSS2_PHY_782_DATA 0x060100CC +#define DDRSS2_PHY_783_DATA 0x00030066 +#define DDRSS2_PHY_784_DATA 0x00000000 +#define DDRSS2_PHY_785_DATA 0x00000301 +#define DDRSS2_PHY_786_DATA 0x0000AAAA +#define DDRSS2_PHY_787_DATA 0x00005555 +#define DDRSS2_PHY_788_DATA 0x0000B5B5 +#define DDRSS2_PHY_789_DATA 0x00004A4A +#define DDRSS2_PHY_790_DATA 0x00005656 +#define DDRSS2_PHY_791_DATA 0x0000A9A9 +#define DDRSS2_PHY_792_DATA 0x0000A9A9 +#define DDRSS2_PHY_793_DATA 0x0000B5B5 +#define DDRSS2_PHY_794_DATA 0x00000000 +#define DDRSS2_PHY_795_DATA 0x00000000 +#define DDRSS2_PHY_796_DATA 0x2A000000 +#define DDRSS2_PHY_797_DATA 0x00000808 +#define DDRSS2_PHY_798_DATA 0x0F000000 +#define DDRSS2_PHY_799_DATA 0x00000F08 +#define DDRSS2_PHY_800_DATA 0x10400000 +#define DDRSS2_PHY_801_DATA 0x0C002006 +#define DDRSS2_PHY_802_DATA 0x00000000 +#define DDRSS2_PHY_803_DATA 0x00000000 +#define DDRSS2_PHY_804_DATA 0x55555555 +#define DDRSS2_PHY_805_DATA 0xAAAAAAAA +#define DDRSS2_PHY_806_DATA 0x55555555 +#define DDRSS2_PHY_807_DATA 0xAAAAAAAA +#define DDRSS2_PHY_808_DATA 0x00005555 +#define DDRSS2_PHY_809_DATA 0x01000100 +#define DDRSS2_PHY_810_DATA 0x00800180 +#define DDRSS2_PHY_811_DATA 0x00000000 +#define DDRSS2_PHY_812_DATA 0x00000000 +#define DDRSS2_PHY_813_DATA 0x00000000 +#define DDRSS2_PHY_814_DATA 0x00000000 +#define DDRSS2_PHY_815_DATA 0x00000000 +#define DDRSS2_PHY_816_DATA 0x00000000 +#define DDRSS2_PHY_817_DATA 0x00000000 +#define DDRSS2_PHY_818_DATA 0x00000000 +#define DDRSS2_PHY_819_DATA 0x00000000 +#define DDRSS2_PHY_820_DATA 0x00000000 +#define DDRSS2_PHY_821_DATA 0x00000000 +#define DDRSS2_PHY_822_DATA 0x00000000 +#define DDRSS2_PHY_823_DATA 0x00000000 +#define DDRSS2_PHY_824_DATA 0x00000000 +#define DDRSS2_PHY_825_DATA 0x00000000 +#define DDRSS2_PHY_826_DATA 0x00000000 +#define DDRSS2_PHY_827_DATA 0x00000000 +#define DDRSS2_PHY_828_DATA 0x00000000 +#define DDRSS2_PHY_829_DATA 0x00000000 +#define DDRSS2_PHY_830_DATA 0x00000000 +#define DDRSS2_PHY_831_DATA 0x00000000 +#define DDRSS2_PHY_832_DATA 0x00000000 +#define DDRSS2_PHY_833_DATA 0x00000000 +#define DDRSS2_PHY_834_DATA 0x00000104 +#define DDRSS2_PHY_835_DATA 0x00000120 +#define DDRSS2_PHY_836_DATA 0x00000000 +#define DDRSS2_PHY_837_DATA 0x00000000 +#define DDRSS2_PHY_838_DATA 0x00000000 +#define DDRSS2_PHY_839_DATA 0x00000000 +#define DDRSS2_PHY_840_DATA 0x00000000 +#define DDRSS2_PHY_841_DATA 0x00000000 +#define DDRSS2_PHY_842_DATA 0x00000000 +#define DDRSS2_PHY_843_DATA 0x00000001 +#define DDRSS2_PHY_844_DATA 0x07FF0000 +#define DDRSS2_PHY_845_DATA 0x0080081F +#define DDRSS2_PHY_846_DATA 0x00081020 +#define DDRSS2_PHY_847_DATA 0x04010000 +#define DDRSS2_PHY_848_DATA 0x00000000 +#define DDRSS2_PHY_849_DATA 0x00000000 +#define DDRSS2_PHY_850_DATA 0x00000000 +#define DDRSS2_PHY_851_DATA 0x00000100 +#define DDRSS2_PHY_852_DATA 0x01CC0C01 +#define DDRSS2_PHY_853_DATA 0x1003CC0C +#define DDRSS2_PHY_854_DATA 0x20000140 +#define DDRSS2_PHY_855_DATA 0x07FF0200 +#define DDRSS2_PHY_856_DATA 0x0000DD01 +#define DDRSS2_PHY_857_DATA 0x10100303 +#define DDRSS2_PHY_858_DATA 0x10101010 +#define DDRSS2_PHY_859_DATA 0x10101010 +#define DDRSS2_PHY_860_DATA 0x00021010 +#define DDRSS2_PHY_861_DATA 0x00100010 +#define DDRSS2_PHY_862_DATA 0x00100010 +#define DDRSS2_PHY_863_DATA 0x00100010 +#define DDRSS2_PHY_864_DATA 0x00100010 +#define DDRSS2_PHY_865_DATA 0x00050010 +#define DDRSS2_PHY_866_DATA 0x51517041 +#define DDRSS2_PHY_867_DATA 0x31C06001 +#define DDRSS2_PHY_868_DATA 0x07AB01AB +#define DDRSS2_PHY_869_DATA 0x00C0C001 +#define DDRSS2_PHY_870_DATA 0x0E0D0101 +#define DDRSS2_PHY_871_DATA 0x10001000 +#define DDRSS2_PHY_872_DATA 0x0C083E42 +#define DDRSS2_PHY_873_DATA 0x0F0C3701 +#define DDRSS2_PHY_874_DATA 0x01000140 +#define DDRSS2_PHY_875_DATA 0x0C000420 +#define DDRSS2_PHY_876_DATA 0x00000198 +#define DDRSS2_PHY_877_DATA 0x0A0000D0 +#define DDRSS2_PHY_878_DATA 0x00030200 +#define DDRSS2_PHY_879_DATA 0x02800000 +#define DDRSS2_PHY_880_DATA 0x80800000 +#define DDRSS2_PHY_881_DATA 0x000E2010 +#define DDRSS2_PHY_882_DATA 0x76543210 +#define DDRSS2_PHY_883_DATA 0x00000008 +#define DDRSS2_PHY_884_DATA 0x02800280 +#define DDRSS2_PHY_885_DATA 0x02800280 +#define DDRSS2_PHY_886_DATA 0x02800280 +#define DDRSS2_PHY_887_DATA 0x02800280 +#define DDRSS2_PHY_888_DATA 0x00000280 +#define DDRSS2_PHY_889_DATA 0x0000A000 +#define DDRSS2_PHY_890_DATA 0x00A000A0 +#define DDRSS2_PHY_891_DATA 0x00A000A0 +#define DDRSS2_PHY_892_DATA 0x00A000A0 +#define DDRSS2_PHY_893_DATA 0x00A000A0 +#define DDRSS2_PHY_894_DATA 0x00A000A0 +#define DDRSS2_PHY_895_DATA 0x00A000A0 +#define DDRSS2_PHY_896_DATA 0x00A000A0 +#define DDRSS2_PHY_897_DATA 0x00A000A0 +#define DDRSS2_PHY_898_DATA 0x01C200A0 +#define DDRSS2_PHY_899_DATA 0x01A00005 +#define DDRSS2_PHY_900_DATA 0x00000000 +#define DDRSS2_PHY_901_DATA 0x00000000 +#define DDRSS2_PHY_902_DATA 0x00080200 +#define DDRSS2_PHY_903_DATA 0x00000000 +#define DDRSS2_PHY_904_DATA 0x20202000 +#define DDRSS2_PHY_905_DATA 0x20202020 +#define DDRSS2_PHY_906_DATA 0xF0F02020 +#define DDRSS2_PHY_907_DATA 0x00000000 +#define DDRSS2_PHY_908_DATA 0x00000000 +#define DDRSS2_PHY_909_DATA 0x00000000 +#define DDRSS2_PHY_910_DATA 0x00000000 +#define DDRSS2_PHY_911_DATA 0x00000000 +#define DDRSS2_PHY_912_DATA 0x00000000 +#define DDRSS2_PHY_913_DATA 0x00000000 +#define DDRSS2_PHY_914_DATA 0x00000000 +#define DDRSS2_PHY_915_DATA 0x00000000 +#define DDRSS2_PHY_916_DATA 0x00000000 +#define DDRSS2_PHY_917_DATA 0x00000000 +#define DDRSS2_PHY_918_DATA 0x00000000 +#define DDRSS2_PHY_919_DATA 0x00000000 +#define DDRSS2_PHY_920_DATA 0x00000000 +#define DDRSS2_PHY_921_DATA 0x00000000 +#define DDRSS2_PHY_922_DATA 0x00000000 +#define DDRSS2_PHY_923_DATA 0x00000000 +#define DDRSS2_PHY_924_DATA 0x00000000 +#define DDRSS2_PHY_925_DATA 0x00000000 +#define DDRSS2_PHY_926_DATA 0x00000000 +#define DDRSS2_PHY_927_DATA 0x00000000 +#define DDRSS2_PHY_928_DATA 0x00000000 +#define DDRSS2_PHY_929_DATA 0x00000000 +#define DDRSS2_PHY_930_DATA 0x00000000 +#define DDRSS2_PHY_931_DATA 0x00000000 +#define DDRSS2_PHY_932_DATA 0x00000000 +#define DDRSS2_PHY_933_DATA 0x00000000 +#define DDRSS2_PHY_934_DATA 0x00000000 +#define DDRSS2_PHY_935_DATA 0x00000000 +#define DDRSS2_PHY_936_DATA 0x00000000 +#define DDRSS2_PHY_937_DATA 0x00000000 +#define DDRSS2_PHY_938_DATA 0x00000000 +#define DDRSS2_PHY_939_DATA 0x00000000 +#define DDRSS2_PHY_940_DATA 0x00000000 +#define DDRSS2_PHY_941_DATA 0x00000000 +#define DDRSS2_PHY_942_DATA 0x00000000 +#define DDRSS2_PHY_943_DATA 0x00000000 +#define DDRSS2_PHY_944_DATA 0x00000000 +#define DDRSS2_PHY_945_DATA 0x00000000 +#define DDRSS2_PHY_946_DATA 0x00000000 +#define DDRSS2_PHY_947_DATA 0x00000000 +#define DDRSS2_PHY_948_DATA 0x00000000 +#define DDRSS2_PHY_949_DATA 0x00000000 +#define DDRSS2_PHY_950_DATA 0x00000000 +#define DDRSS2_PHY_951_DATA 0x00000000 +#define DDRSS2_PHY_952_DATA 0x00000000 +#define DDRSS2_PHY_953_DATA 0x00000000 +#define DDRSS2_PHY_954_DATA 0x00000000 +#define DDRSS2_PHY_955_DATA 0x00000000 +#define DDRSS2_PHY_956_DATA 0x00000000 +#define DDRSS2_PHY_957_DATA 0x00000000 +#define DDRSS2_PHY_958_DATA 0x00000000 +#define DDRSS2_PHY_959_DATA 0x00000000 +#define DDRSS2_PHY_960_DATA 0x00000000 +#define DDRSS2_PHY_961_DATA 0x00000000 +#define DDRSS2_PHY_962_DATA 0x00000000 +#define DDRSS2_PHY_963_DATA 0x00000000 +#define DDRSS2_PHY_964_DATA 0x00000000 +#define DDRSS2_PHY_965_DATA 0x00000000 +#define DDRSS2_PHY_966_DATA 0x00000000 +#define DDRSS2_PHY_967_DATA 0x00000000 +#define DDRSS2_PHY_968_DATA 0x00000000 +#define DDRSS2_PHY_969_DATA 0x00000000 +#define DDRSS2_PHY_970_DATA 0x00000000 +#define DDRSS2_PHY_971_DATA 0x00000000 +#define DDRSS2_PHY_972_DATA 0x00000000 +#define DDRSS2_PHY_973_DATA 0x00000000 +#define DDRSS2_PHY_974_DATA 0x00000000 +#define DDRSS2_PHY_975_DATA 0x00000000 +#define DDRSS2_PHY_976_DATA 0x00000000 +#define DDRSS2_PHY_977_DATA 0x00000000 +#define DDRSS2_PHY_978_DATA 0x00000000 +#define DDRSS2_PHY_979_DATA 0x00000000 +#define DDRSS2_PHY_980_DATA 0x00000000 +#define DDRSS2_PHY_981_DATA 0x00000000 +#define DDRSS2_PHY_982_DATA 0x00000000 +#define DDRSS2_PHY_983_DATA 0x00000000 +#define DDRSS2_PHY_984_DATA 0x00000000 +#define DDRSS2_PHY_985_DATA 0x00000000 +#define DDRSS2_PHY_986_DATA 0x00000000 +#define DDRSS2_PHY_987_DATA 0x00000000 +#define DDRSS2_PHY_988_DATA 0x00000000 +#define DDRSS2_PHY_989_DATA 0x00000000 +#define DDRSS2_PHY_990_DATA 0x00000000 +#define DDRSS2_PHY_991_DATA 0x00000000 +#define DDRSS2_PHY_992_DATA 0x00000000 +#define DDRSS2_PHY_993_DATA 0x00000000 +#define DDRSS2_PHY_994_DATA 0x00000000 +#define DDRSS2_PHY_995_DATA 0x00000000 +#define DDRSS2_PHY_996_DATA 0x00000000 +#define DDRSS2_PHY_997_DATA 0x00000000 +#define DDRSS2_PHY_998_DATA 0x00000000 +#define DDRSS2_PHY_999_DATA 0x00000000 +#define DDRSS2_PHY_1000_DATA 0x00000000 +#define DDRSS2_PHY_1001_DATA 0x00000000 +#define DDRSS2_PHY_1002_DATA 0x00000000 +#define DDRSS2_PHY_1003_DATA 0x00000000 +#define DDRSS2_PHY_1004_DATA 0x00000000 +#define DDRSS2_PHY_1005_DATA 0x00000000 +#define DDRSS2_PHY_1006_DATA 0x00000000 +#define DDRSS2_PHY_1007_DATA 0x00000000 +#define DDRSS2_PHY_1008_DATA 0x00000000 +#define DDRSS2_PHY_1009_DATA 0x00000000 +#define DDRSS2_PHY_1010_DATA 0x00000000 +#define DDRSS2_PHY_1011_DATA 0x00000000 +#define DDRSS2_PHY_1012_DATA 0x00000000 +#define DDRSS2_PHY_1013_DATA 0x00000000 +#define DDRSS2_PHY_1014_DATA 0x00000000 +#define DDRSS2_PHY_1015_DATA 0x00000000 +#define DDRSS2_PHY_1016_DATA 0x00000000 +#define DDRSS2_PHY_1017_DATA 0x00000000 +#define DDRSS2_PHY_1018_DATA 0x00000000 +#define DDRSS2_PHY_1019_DATA 0x00000000 +#define DDRSS2_PHY_1020_DATA 0x00000000 +#define DDRSS2_PHY_1021_DATA 0x00000000 +#define DDRSS2_PHY_1022_DATA 0x00000000 +#define DDRSS2_PHY_1023_DATA 0x00000000 +#define DDRSS2_PHY_1024_DATA 0x00000000 +#define DDRSS2_PHY_1025_DATA 0x00000000 +#define DDRSS2_PHY_1026_DATA 0x00000000 +#define DDRSS2_PHY_1027_DATA 0x00000000 +#define DDRSS2_PHY_1028_DATA 0x00000000 +#define DDRSS2_PHY_1029_DATA 0x00000100 +#define DDRSS2_PHY_1030_DATA 0x00000200 +#define DDRSS2_PHY_1031_DATA 0x00000000 +#define DDRSS2_PHY_1032_DATA 0x00000000 +#define DDRSS2_PHY_1033_DATA 0x00000000 +#define DDRSS2_PHY_1034_DATA 0x00000000 +#define DDRSS2_PHY_1035_DATA 0x00400000 +#define DDRSS2_PHY_1036_DATA 0x00000080 +#define DDRSS2_PHY_1037_DATA 0x00DCBA98 +#define DDRSS2_PHY_1038_DATA 0x03000000 +#define DDRSS2_PHY_1039_DATA 0x00200000 +#define DDRSS2_PHY_1040_DATA 0x00000000 +#define DDRSS2_PHY_1041_DATA 0x00000000 +#define DDRSS2_PHY_1042_DATA 0x00000000 +#define DDRSS2_PHY_1043_DATA 0x00000000 +#define DDRSS2_PHY_1044_DATA 0x00000000 +#define DDRSS2_PHY_1045_DATA 0x0000002A +#define DDRSS2_PHY_1046_DATA 0x00000015 +#define DDRSS2_PHY_1047_DATA 0x00000015 +#define DDRSS2_PHY_1048_DATA 0x0000002A +#define DDRSS2_PHY_1049_DATA 0x00000033 +#define DDRSS2_PHY_1050_DATA 0x0000000C +#define DDRSS2_PHY_1051_DATA 0x0000000C +#define DDRSS2_PHY_1052_DATA 0x00000033 +#define DDRSS2_PHY_1053_DATA 0x00543210 +#define DDRSS2_PHY_1054_DATA 0x003F0000 +#define DDRSS2_PHY_1055_DATA 0x000F3F3F +#define DDRSS2_PHY_1056_DATA 0x20202003 +#define DDRSS2_PHY_1057_DATA 0x00202020 +#define DDRSS2_PHY_1058_DATA 0x20008008 +#define DDRSS2_PHY_1059_DATA 0x00000810 +#define DDRSS2_PHY_1060_DATA 0x00000F00 +#define DDRSS2_PHY_1061_DATA 0x00000000 +#define DDRSS2_PHY_1062_DATA 0x00000000 +#define DDRSS2_PHY_1063_DATA 0x00000000 +#define DDRSS2_PHY_1064_DATA 0x000305CC +#define DDRSS2_PHY_1065_DATA 0x00030000 +#define DDRSS2_PHY_1066_DATA 0x00000300 +#define DDRSS2_PHY_1067_DATA 0x00000300 +#define DDRSS2_PHY_1068_DATA 0x00000300 +#define DDRSS2_PHY_1069_DATA 0x00000300 +#define DDRSS2_PHY_1070_DATA 0x00000300 +#define DDRSS2_PHY_1071_DATA 0x42080010 +#define DDRSS2_PHY_1072_DATA 0x0000803E +#define DDRSS2_PHY_1073_DATA 0x00000001 +#define DDRSS2_PHY_1074_DATA 0x01000102 +#define DDRSS2_PHY_1075_DATA 0x00008000 +#define DDRSS2_PHY_1076_DATA 0x00000000 +#define DDRSS2_PHY_1077_DATA 0x00000000 +#define DDRSS2_PHY_1078_DATA 0x00000000 +#define DDRSS2_PHY_1079_DATA 0x00000000 +#define DDRSS2_PHY_1080_DATA 0x00000000 +#define DDRSS2_PHY_1081_DATA 0x00000000 +#define DDRSS2_PHY_1082_DATA 0x00000000 +#define DDRSS2_PHY_1083_DATA 0x00000000 +#define DDRSS2_PHY_1084_DATA 0x00000000 +#define DDRSS2_PHY_1085_DATA 0x00000000 +#define DDRSS2_PHY_1086_DATA 0x00000000 +#define DDRSS2_PHY_1087_DATA 0x00000000 +#define DDRSS2_PHY_1088_DATA 0x00000000 +#define DDRSS2_PHY_1089_DATA 0x00000000 +#define DDRSS2_PHY_1090_DATA 0x00000000 +#define DDRSS2_PHY_1091_DATA 0x00000000 +#define DDRSS2_PHY_1092_DATA 0x00000000 +#define DDRSS2_PHY_1093_DATA 0x00000000 +#define DDRSS2_PHY_1094_DATA 0x00000000 +#define DDRSS2_PHY_1095_DATA 0x00000000 +#define DDRSS2_PHY_1096_DATA 0x00000000 +#define DDRSS2_PHY_1097_DATA 0x00000000 +#define DDRSS2_PHY_1098_DATA 0x00000000 +#define DDRSS2_PHY_1099_DATA 0x00000000 +#define DDRSS2_PHY_1100_DATA 0x00000000 +#define DDRSS2_PHY_1101_DATA 0x00000000 +#define DDRSS2_PHY_1102_DATA 0x00000000 +#define DDRSS2_PHY_1103_DATA 0x00000000 +#define DDRSS2_PHY_1104_DATA 0x00000000 +#define DDRSS2_PHY_1105_DATA 0x00000000 +#define DDRSS2_PHY_1106_DATA 0x00000000 +#define DDRSS2_PHY_1107_DATA 0x00000000 +#define DDRSS2_PHY_1108_DATA 0x00000000 +#define DDRSS2_PHY_1109_DATA 0x00000000 +#define DDRSS2_PHY_1110_DATA 0x00000000 +#define DDRSS2_PHY_1111_DATA 0x00000000 +#define DDRSS2_PHY_1112_DATA 0x00000000 +#define DDRSS2_PHY_1113_DATA 0x00000000 +#define DDRSS2_PHY_1114_DATA 0x00000000 +#define DDRSS2_PHY_1115_DATA 0x00000000 +#define DDRSS2_PHY_1116_DATA 0x00000000 +#define DDRSS2_PHY_1117_DATA 0x00000000 +#define DDRSS2_PHY_1118_DATA 0x00000000 +#define DDRSS2_PHY_1119_DATA 0x00000000 +#define DDRSS2_PHY_1120_DATA 0x00000000 +#define DDRSS2_PHY_1121_DATA 0x00000000 +#define DDRSS2_PHY_1122_DATA 0x00000000 +#define DDRSS2_PHY_1123_DATA 0x00000000 +#define DDRSS2_PHY_1124_DATA 0x00000000 +#define DDRSS2_PHY_1125_DATA 0x00000000 +#define DDRSS2_PHY_1126_DATA 0x00000000 +#define DDRSS2_PHY_1127_DATA 0x00000000 +#define DDRSS2_PHY_1128_DATA 0x00000000 +#define DDRSS2_PHY_1129_DATA 0x00000000 +#define DDRSS2_PHY_1130_DATA 0x00000000 +#define DDRSS2_PHY_1131_DATA 0x00000000 +#define DDRSS2_PHY_1132_DATA 0x00000000 +#define DDRSS2_PHY_1133_DATA 0x00000000 +#define DDRSS2_PHY_1134_DATA 0x00000000 +#define DDRSS2_PHY_1135_DATA 0x00000000 +#define DDRSS2_PHY_1136_DATA 0x00000000 +#define DDRSS2_PHY_1137_DATA 0x00000000 +#define DDRSS2_PHY_1138_DATA 0x00000000 +#define DDRSS2_PHY_1139_DATA 0x00000000 +#define DDRSS2_PHY_1140_DATA 0x00000000 +#define DDRSS2_PHY_1141_DATA 0x00000000 +#define DDRSS2_PHY_1142_DATA 0x00000000 +#define DDRSS2_PHY_1143_DATA 0x00000000 +#define DDRSS2_PHY_1144_DATA 0x00000000 +#define DDRSS2_PHY_1145_DATA 0x00000000 +#define DDRSS2_PHY_1146_DATA 0x00000000 +#define DDRSS2_PHY_1147_DATA 0x00000000 +#define DDRSS2_PHY_1148_DATA 0x00000000 +#define DDRSS2_PHY_1149_DATA 0x00000000 +#define DDRSS2_PHY_1150_DATA 0x00000000 +#define DDRSS2_PHY_1151_DATA 0x00000000 +#define DDRSS2_PHY_1152_DATA 0x00000000 +#define DDRSS2_PHY_1153_DATA 0x00000000 +#define DDRSS2_PHY_1154_DATA 0x00000000 +#define DDRSS2_PHY_1155_DATA 0x00000000 +#define DDRSS2_PHY_1156_DATA 0x00000000 +#define DDRSS2_PHY_1157_DATA 0x00000000 +#define DDRSS2_PHY_1158_DATA 0x00000000 +#define DDRSS2_PHY_1159_DATA 0x00000000 +#define DDRSS2_PHY_1160_DATA 0x00000000 +#define DDRSS2_PHY_1161_DATA 0x00000000 +#define DDRSS2_PHY_1162_DATA 0x00000000 +#define DDRSS2_PHY_1163_DATA 0x00000000 +#define DDRSS2_PHY_1164_DATA 0x00000000 +#define DDRSS2_PHY_1165_DATA 0x00000000 +#define DDRSS2_PHY_1166_DATA 0x00000000 +#define DDRSS2_PHY_1167_DATA 0x00000000 +#define DDRSS2_PHY_1168_DATA 0x00000000 +#define DDRSS2_PHY_1169_DATA 0x00000000 +#define DDRSS2_PHY_1170_DATA 0x00000000 +#define DDRSS2_PHY_1171_DATA 0x00000000 +#define DDRSS2_PHY_1172_DATA 0x00000000 +#define DDRSS2_PHY_1173_DATA 0x00000000 +#define DDRSS2_PHY_1174_DATA 0x00000000 +#define DDRSS2_PHY_1175_DATA 0x00000000 +#define DDRSS2_PHY_1176_DATA 0x00000000 +#define DDRSS2_PHY_1177_DATA 0x00000000 +#define DDRSS2_PHY_1178_DATA 0x00000000 +#define DDRSS2_PHY_1179_DATA 0x00000000 +#define DDRSS2_PHY_1180_DATA 0x00000000 +#define DDRSS2_PHY_1181_DATA 0x00000000 +#define DDRSS2_PHY_1182_DATA 0x00000000 +#define DDRSS2_PHY_1183_DATA 0x00000000 +#define DDRSS2_PHY_1184_DATA 0x00000000 +#define DDRSS2_PHY_1185_DATA 0x00000000 +#define DDRSS2_PHY_1186_DATA 0x00000000 +#define DDRSS2_PHY_1187_DATA 0x00000000 +#define DDRSS2_PHY_1188_DATA 0x00000000 +#define DDRSS2_PHY_1189_DATA 0x00000000 +#define DDRSS2_PHY_1190_DATA 0x00000000 +#define DDRSS2_PHY_1191_DATA 0x00000000 +#define DDRSS2_PHY_1192_DATA 0x00000000 +#define DDRSS2_PHY_1193_DATA 0x00000000 +#define DDRSS2_PHY_1194_DATA 0x00000000 +#define DDRSS2_PHY_1195_DATA 0x00000000 +#define DDRSS2_PHY_1196_DATA 0x00000000 +#define DDRSS2_PHY_1197_DATA 0x00000000 +#define DDRSS2_PHY_1198_DATA 0x00000000 +#define DDRSS2_PHY_1199_DATA 0x00000000 +#define DDRSS2_PHY_1200_DATA 0x00000000 +#define DDRSS2_PHY_1201_DATA 0x00000000 +#define DDRSS2_PHY_1202_DATA 0x00000000 +#define DDRSS2_PHY_1203_DATA 0x00000000 +#define DDRSS2_PHY_1204_DATA 0x00000000 +#define DDRSS2_PHY_1205_DATA 0x00000000 +#define DDRSS2_PHY_1206_DATA 0x00000000 +#define DDRSS2_PHY_1207_DATA 0x00000000 +#define DDRSS2_PHY_1208_DATA 0x00000000 +#define DDRSS2_PHY_1209_DATA 0x00000000 +#define DDRSS2_PHY_1210_DATA 0x00000000 +#define DDRSS2_PHY_1211_DATA 0x00000000 +#define DDRSS2_PHY_1212_DATA 0x00000000 +#define DDRSS2_PHY_1213_DATA 0x00000000 +#define DDRSS2_PHY_1214_DATA 0x00000000 +#define DDRSS2_PHY_1215_DATA 0x00000000 +#define DDRSS2_PHY_1216_DATA 0x00000000 +#define DDRSS2_PHY_1217_DATA 0x00000000 +#define DDRSS2_PHY_1218_DATA 0x00000000 +#define DDRSS2_PHY_1219_DATA 0x00000000 +#define DDRSS2_PHY_1220_DATA 0x00000000 +#define DDRSS2_PHY_1221_DATA 0x00000000 +#define DDRSS2_PHY_1222_DATA 0x00000000 +#define DDRSS2_PHY_1223_DATA 0x00000000 +#define DDRSS2_PHY_1224_DATA 0x00000000 +#define DDRSS2_PHY_1225_DATA 0x00000000 +#define DDRSS2_PHY_1226_DATA 0x00000000 +#define DDRSS2_PHY_1227_DATA 0x00000000 +#define DDRSS2_PHY_1228_DATA 0x00000000 +#define DDRSS2_PHY_1229_DATA 0x00000000 +#define DDRSS2_PHY_1230_DATA 0x00000000 +#define DDRSS2_PHY_1231_DATA 0x00000000 +#define DDRSS2_PHY_1232_DATA 0x00000000 +#define DDRSS2_PHY_1233_DATA 0x00000000 +#define DDRSS2_PHY_1234_DATA 0x00000000 +#define DDRSS2_PHY_1235_DATA 0x00000000 +#define DDRSS2_PHY_1236_DATA 0x00000000 +#define DDRSS2_PHY_1237_DATA 0x00000000 +#define DDRSS2_PHY_1238_DATA 0x00000000 +#define DDRSS2_PHY_1239_DATA 0x00000000 +#define DDRSS2_PHY_1240_DATA 0x00000000 +#define DDRSS2_PHY_1241_DATA 0x00000000 +#define DDRSS2_PHY_1242_DATA 0x00000000 +#define DDRSS2_PHY_1243_DATA 0x00000000 +#define DDRSS2_PHY_1244_DATA 0x00000000 +#define DDRSS2_PHY_1245_DATA 0x00000000 +#define DDRSS2_PHY_1246_DATA 0x00000000 +#define DDRSS2_PHY_1247_DATA 0x00000000 +#define DDRSS2_PHY_1248_DATA 0x00000000 +#define DDRSS2_PHY_1249_DATA 0x00000000 +#define DDRSS2_PHY_1250_DATA 0x00000000 +#define DDRSS2_PHY_1251_DATA 0x00000000 +#define DDRSS2_PHY_1252_DATA 0x00000000 +#define DDRSS2_PHY_1253_DATA 0x00000000 +#define DDRSS2_PHY_1254_DATA 0x00000000 +#define DDRSS2_PHY_1255_DATA 0x00000000 +#define DDRSS2_PHY_1256_DATA 0x00000000 +#define DDRSS2_PHY_1257_DATA 0x00000000 +#define DDRSS2_PHY_1258_DATA 0x00000000 +#define DDRSS2_PHY_1259_DATA 0x00000000 +#define DDRSS2_PHY_1260_DATA 0x00000000 +#define DDRSS2_PHY_1261_DATA 0x00000000 +#define DDRSS2_PHY_1262_DATA 0x00000000 +#define DDRSS2_PHY_1263_DATA 0x00000000 +#define DDRSS2_PHY_1264_DATA 0x00000000 +#define DDRSS2_PHY_1265_DATA 0x00000000 +#define DDRSS2_PHY_1266_DATA 0x00000000 +#define DDRSS2_PHY_1267_DATA 0x00000000 +#define DDRSS2_PHY_1268_DATA 0x00000000 +#define DDRSS2_PHY_1269_DATA 0x00000000 +#define DDRSS2_PHY_1270_DATA 0x00000000 +#define DDRSS2_PHY_1271_DATA 0x00000000 +#define DDRSS2_PHY_1272_DATA 0x00000000 +#define DDRSS2_PHY_1273_DATA 0x00000000 +#define DDRSS2_PHY_1274_DATA 0x00000000 +#define DDRSS2_PHY_1275_DATA 0x00000000 +#define DDRSS2_PHY_1276_DATA 0x00000000 +#define DDRSS2_PHY_1277_DATA 0x00000000 +#define DDRSS2_PHY_1278_DATA 0x00000000 +#define DDRSS2_PHY_1279_DATA 0x00000000 +#define DDRSS2_PHY_1280_DATA 0x00000000 +#define DDRSS2_PHY_1281_DATA 0x00010100 +#define DDRSS2_PHY_1282_DATA 0x00000000 +#define DDRSS2_PHY_1283_DATA 0x00000000 +#define DDRSS2_PHY_1284_DATA 0x00050000 +#define DDRSS2_PHY_1285_DATA 0x04000000 +#define DDRSS2_PHY_1286_DATA 0x00000055 +#define DDRSS2_PHY_1287_DATA 0x00000000 +#define DDRSS2_PHY_1288_DATA 0x00000000 +#define DDRSS2_PHY_1289_DATA 0x00000000 +#define DDRSS2_PHY_1290_DATA 0x00000000 +#define DDRSS2_PHY_1291_DATA 0x00002001 +#define DDRSS2_PHY_1292_DATA 0x0000400F +#define DDRSS2_PHY_1293_DATA 0x50020028 +#define DDRSS2_PHY_1294_DATA 0x01010000 +#define DDRSS2_PHY_1295_DATA 0x80080001 +#define DDRSS2_PHY_1296_DATA 0x10200000 +#define DDRSS2_PHY_1297_DATA 0x00000008 +#define DDRSS2_PHY_1298_DATA 0x00000000 +#define DDRSS2_PHY_1299_DATA 0x01090E00 +#define DDRSS2_PHY_1300_DATA 0x00040101 +#define DDRSS2_PHY_1301_DATA 0x0000010F +#define DDRSS2_PHY_1302_DATA 0x00000000 +#define DDRSS2_PHY_1303_DATA 0x00000064 +#define DDRSS2_PHY_1304_DATA 0x00000000 +#define DDRSS2_PHY_1305_DATA 0x01010000 +#define DDRSS2_PHY_1306_DATA 0x01080402 +#define DDRSS2_PHY_1307_DATA 0x01200F02 +#define DDRSS2_PHY_1308_DATA 0x00194280 +#define DDRSS2_PHY_1309_DATA 0x00000004 +#define DDRSS2_PHY_1310_DATA 0x00042000 +#define DDRSS2_PHY_1311_DATA 0x00000000 +#define DDRSS2_PHY_1312_DATA 0x00000000 +#define DDRSS2_PHY_1313_DATA 0x00000000 +#define DDRSS2_PHY_1314_DATA 0x00000000 +#define DDRSS2_PHY_1315_DATA 0x00000000 +#define DDRSS2_PHY_1316_DATA 0x00000000 +#define DDRSS2_PHY_1317_DATA 0x01000000 +#define DDRSS2_PHY_1318_DATA 0x00000705 +#define DDRSS2_PHY_1319_DATA 0x00000054 +#define DDRSS2_PHY_1320_DATA 0x00030820 +#define DDRSS2_PHY_1321_DATA 0x00010820 +#define DDRSS2_PHY_1322_DATA 0x00010820 +#define DDRSS2_PHY_1323_DATA 0x00010820 +#define DDRSS2_PHY_1324_DATA 0x00010820 +#define DDRSS2_PHY_1325_DATA 0x00010820 +#define DDRSS2_PHY_1326_DATA 0x00010820 +#define DDRSS2_PHY_1327_DATA 0x00010820 +#define DDRSS2_PHY_1328_DATA 0x00010820 +#define DDRSS2_PHY_1329_DATA 0x00000000 +#define DDRSS2_PHY_1330_DATA 0x00000074 +#define DDRSS2_PHY_1331_DATA 0x00000400 +#define DDRSS2_PHY_1332_DATA 0x00000108 +#define DDRSS2_PHY_1333_DATA 0x00000000 +#define DDRSS2_PHY_1334_DATA 0x00000000 +#define DDRSS2_PHY_1335_DATA 0x00000000 +#define DDRSS2_PHY_1336_DATA 0x00000000 +#define DDRSS2_PHY_1337_DATA 0x00000000 +#define DDRSS2_PHY_1338_DATA 0x03000000 +#define DDRSS2_PHY_1339_DATA 0x00000000 +#define DDRSS2_PHY_1340_DATA 0x00000000 +#define DDRSS2_PHY_1341_DATA 0x00000000 +#define DDRSS2_PHY_1342_DATA 0x04102006 +#define DDRSS2_PHY_1343_DATA 0x00041020 +#define DDRSS2_PHY_1344_DATA 0x01C98C98 +#define DDRSS2_PHY_1345_DATA 0x3F400000 +#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS2_PHY_1347_DATA 0x0000001F +#define DDRSS2_PHY_1348_DATA 0x00000000 +#define DDRSS2_PHY_1349_DATA 0x00000000 +#define DDRSS2_PHY_1350_DATA 0x00000000 +#define DDRSS2_PHY_1351_DATA 0x00010000 +#define DDRSS2_PHY_1352_DATA 0x00000000 +#define DDRSS2_PHY_1353_DATA 0x00000000 +#define DDRSS2_PHY_1354_DATA 0x00000000 +#define DDRSS2_PHY_1355_DATA 0x00000000 +#define DDRSS2_PHY_1356_DATA 0x76543210 +#define DDRSS2_PHY_1357_DATA 0x00010198 +#define DDRSS2_PHY_1358_DATA 0x00000000 +#define DDRSS2_PHY_1359_DATA 0x00000000 +#define DDRSS2_PHY_1360_DATA 0x00000000 +#define DDRSS2_PHY_1361_DATA 0x00040700 +#define DDRSS2_PHY_1362_DATA 0x00000000 +#define DDRSS2_PHY_1363_DATA 0x00000000 +#define DDRSS2_PHY_1364_DATA 0x00000000 +#define DDRSS2_PHY_1365_DATA 0x00000000 +#define DDRSS2_PHY_1366_DATA 0x00000000 +#define DDRSS2_PHY_1367_DATA 0x00000002 +#define DDRSS2_PHY_1368_DATA 0x00000000 +#define DDRSS2_PHY_1369_DATA 0x00000000 +#define DDRSS2_PHY_1370_DATA 0x00000000 +#define DDRSS2_PHY_1371_DATA 0x00000000 +#define DDRSS2_PHY_1372_DATA 0x00000000 +#define DDRSS2_PHY_1373_DATA 0x00000000 +#define DDRSS2_PHY_1374_DATA 0x00080000 +#define DDRSS2_PHY_1375_DATA 0x000007FF +#define DDRSS2_PHY_1376_DATA 0x00000000 +#define DDRSS2_PHY_1377_DATA 0x00000000 +#define DDRSS2_PHY_1378_DATA 0x00000000 +#define DDRSS2_PHY_1379_DATA 0x00000000 +#define DDRSS2_PHY_1380_DATA 0x00000000 +#define DDRSS2_PHY_1381_DATA 0x00000000 +#define DDRSS2_PHY_1382_DATA 0x000FFFFF +#define DDRSS2_PHY_1383_DATA 0x000FFFFF +#define DDRSS2_PHY_1384_DATA 0x0000FFFF +#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS2_PHY_1386_DATA 0x030FFFFF +#define DDRSS2_PHY_1387_DATA 0x01FFFFFF +#define DDRSS2_PHY_1388_DATA 0x0000FFFF +#define DDRSS2_PHY_1389_DATA 0x00000000 +#define DDRSS2_PHY_1390_DATA 0x00000000 +#define DDRSS2_PHY_1391_DATA 0x00000000 +#define DDRSS2_PHY_1392_DATA 0x00000000 +#define DDRSS2_PHY_1393_DATA 0x0001F7C0 +#define DDRSS2_PHY_1394_DATA 0x00000003 +#define DDRSS2_PHY_1395_DATA 0x00000000 +#define DDRSS2_PHY_1396_DATA 0x00001142 +#define DDRSS2_PHY_1397_DATA 0x040207AB +#define DDRSS2_PHY_1398_DATA 0x01000080 +#define DDRSS2_PHY_1399_DATA 0x03900390 +#define DDRSS2_PHY_1400_DATA 0x03900390 +#define DDRSS2_PHY_1401_DATA 0x00000390 +#define DDRSS2_PHY_1402_DATA 0x00000390 +#define DDRSS2_PHY_1403_DATA 0x00000390 +#define DDRSS2_PHY_1404_DATA 0x00000390 +#define DDRSS2_PHY_1405_DATA 0x00000005 +#define DDRSS2_PHY_1406_DATA 0x01813FCC +#define DDRSS2_PHY_1407_DATA 0x000000CC +#define DDRSS2_PHY_1408_DATA 0x0C000DFF +#define DDRSS2_PHY_1409_DATA 0x30000DFF +#define DDRSS2_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1411_DATA 0x000100F0 +#define DDRSS2_PHY_1412_DATA 0x780DFFCC +#define DDRSS2_PHY_1413_DATA 0x00007E31 +#define DDRSS2_PHY_1414_DATA 0x000CBF11 +#define DDRSS2_PHY_1415_DATA 0x01990010 +#define DDRSS2_PHY_1416_DATA 0x000CBF11 +#define DDRSS2_PHY_1417_DATA 0x01990010 +#define DDRSS2_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1419_DATA 0x00EF00F0 +#define DDRSS2_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1421_DATA 0x01FF00F0 +#define DDRSS2_PHY_1422_DATA 0x20040006 + +#define DDRSS3_CTL_00_DATA 0x00000B00 +#define DDRSS3_CTL_01_DATA 0x00000000 +#define DDRSS3_CTL_02_DATA 0x00000000 +#define DDRSS3_CTL_03_DATA 0x00000000 +#define DDRSS3_CTL_04_DATA 0x00000000 +#define DDRSS3_CTL_05_DATA 0x00000000 +#define DDRSS3_CTL_06_DATA 0x00000000 +#define DDRSS3_CTL_07_DATA 0x00002AF8 +#define DDRSS3_CTL_08_DATA 0x0001ADAF +#define DDRSS3_CTL_09_DATA 0x00000005 +#define DDRSS3_CTL_10_DATA 0x0000006E +#define DDRSS3_CTL_11_DATA 0x000681C8 +#define DDRSS3_CTL_12_DATA 0x004111C9 +#define DDRSS3_CTL_13_DATA 0x00000005 +#define DDRSS3_CTL_14_DATA 0x000010A9 +#define DDRSS3_CTL_15_DATA 0x000681C8 +#define DDRSS3_CTL_16_DATA 0x004111C9 +#define DDRSS3_CTL_17_DATA 0x00000005 +#define DDRSS3_CTL_18_DATA 0x000010A9 +#define DDRSS3_CTL_19_DATA 0x01010000 +#define DDRSS3_CTL_20_DATA 0x01011001 +#define DDRSS3_CTL_21_DATA 0x02010000 +#define DDRSS3_CTL_22_DATA 0x00020100 +#define DDRSS3_CTL_23_DATA 0x0000000B +#define DDRSS3_CTL_24_DATA 0x0000001C +#define DDRSS3_CTL_25_DATA 0x00000000 +#define DDRSS3_CTL_26_DATA 0x00000000 +#define DDRSS3_CTL_27_DATA 0x03020200 +#define DDRSS3_CTL_28_DATA 0x00005656 +#define DDRSS3_CTL_29_DATA 0x00100000 +#define DDRSS3_CTL_30_DATA 0x00000000 +#define DDRSS3_CTL_31_DATA 0x00000000 +#define DDRSS3_CTL_32_DATA 0x00000000 +#define DDRSS3_CTL_33_DATA 0x00000000 +#define DDRSS3_CTL_34_DATA 0x040C0000 +#define DDRSS3_CTL_35_DATA 0x12501250 +#define DDRSS3_CTL_36_DATA 0x00050804 +#define DDRSS3_CTL_37_DATA 0x09040008 +#define DDRSS3_CTL_38_DATA 0x15000204 +#define DDRSS3_CTL_39_DATA 0x1760008B +#define DDRSS3_CTL_40_DATA 0x1500422B +#define DDRSS3_CTL_41_DATA 0x1760008B +#define DDRSS3_CTL_42_DATA 0x2000422B +#define DDRSS3_CTL_43_DATA 0x000A0A09 +#define DDRSS3_CTL_44_DATA 0x040003C5 +#define DDRSS3_CTL_45_DATA 0x1E161104 +#define DDRSS3_CTL_46_DATA 0x1000922C +#define DDRSS3_CTL_47_DATA 0x1E161110 +#define DDRSS3_CTL_48_DATA 0x1000922C +#define DDRSS3_CTL_49_DATA 0x02030410 +#define DDRSS3_CTL_50_DATA 0x2C060500 +#define DDRSS3_CTL_51_DATA 0x08292C29 +#define DDRSS3_CTL_52_DATA 0x14000E0A +#define DDRSS3_CTL_53_DATA 0x04010A0A +#define DDRSS3_CTL_54_DATA 0x01010004 +#define DDRSS3_CTL_55_DATA 0x0454540A +#define DDRSS3_CTL_56_DATA 0x04313104 +#define DDRSS3_CTL_57_DATA 0x00003131 +#define DDRSS3_CTL_58_DATA 0x00010100 +#define DDRSS3_CTL_59_DATA 0x03010000 +#define DDRSS3_CTL_60_DATA 0x00001508 +#define DDRSS3_CTL_61_DATA 0x00000068 +#define DDRSS3_CTL_62_DATA 0x0000032B +#define DDRSS3_CTL_63_DATA 0x00001035 +#define DDRSS3_CTL_64_DATA 0x0000032B +#define DDRSS3_CTL_65_DATA 0x00001035 +#define DDRSS3_CTL_66_DATA 0x00000005 +#define DDRSS3_CTL_67_DATA 0x00050000 +#define DDRSS3_CTL_68_DATA 0x00CB0005 +#define DDRSS3_CTL_69_DATA 0x00CB0200 +#define DDRSS3_CTL_70_DATA 0x00400200 +#define DDRSS3_CTL_71_DATA 0x00120103 +#define DDRSS3_CTL_72_DATA 0x00100005 +#define DDRSS3_CTL_73_DATA 0x2F080010 +#define DDRSS3_CTL_74_DATA 0x0505012F +#define DDRSS3_CTL_75_DATA 0x0401030A +#define DDRSS3_CTL_76_DATA 0x041E100B +#define DDRSS3_CTL_77_DATA 0x100B0401 +#define DDRSS3_CTL_78_DATA 0x0001041E +#define DDRSS3_CTL_79_DATA 0x00160016 +#define DDRSS3_CTL_80_DATA 0x033B033B +#define DDRSS3_CTL_81_DATA 0x033B033B +#define DDRSS3_CTL_82_DATA 0x03050505 +#define DDRSS3_CTL_83_DATA 0x03010303 +#define DDRSS3_CTL_84_DATA 0x200B100B +#define DDRSS3_CTL_85_DATA 0x04041004 +#define DDRSS3_CTL_86_DATA 0x200B100B +#define DDRSS3_CTL_87_DATA 0x04041004 +#define DDRSS3_CTL_88_DATA 0x03010000 +#define DDRSS3_CTL_89_DATA 0x00010000 +#define DDRSS3_CTL_90_DATA 0x00000000 +#define DDRSS3_CTL_91_DATA 0x00000000 +#define DDRSS3_CTL_92_DATA 0x01000000 +#define DDRSS3_CTL_93_DATA 0x80104002 +#define DDRSS3_CTL_94_DATA 0x00000000 +#define DDRSS3_CTL_95_DATA 0x00040005 +#define DDRSS3_CTL_96_DATA 0x00000000 +#define DDRSS3_CTL_97_DATA 0x00050000 +#define DDRSS3_CTL_98_DATA 0x00000004 +#define DDRSS3_CTL_99_DATA 0x00000000 +#define DDRSS3_CTL_100_DATA 0x00040005 +#define DDRSS3_CTL_101_DATA 0x00000000 +#define DDRSS3_CTL_102_DATA 0x000018C0 +#define DDRSS3_CTL_103_DATA 0x000018C0 +#define DDRSS3_CTL_104_DATA 0x000018C0 +#define DDRSS3_CTL_105_DATA 0x000018C0 +#define DDRSS3_CTL_106_DATA 0x000018C0 +#define DDRSS3_CTL_107_DATA 0x00000000 +#define DDRSS3_CTL_108_DATA 0x000002B5 +#define DDRSS3_CTL_109_DATA 0x00040D40 +#define DDRSS3_CTL_110_DATA 0x00040D40 +#define DDRSS3_CTL_111_DATA 0x00040D40 +#define DDRSS3_CTL_112_DATA 0x00040D40 +#define DDRSS3_CTL_113_DATA 0x00040D40 +#define DDRSS3_CTL_114_DATA 0x00000000 +#define DDRSS3_CTL_115_DATA 0x00007173 +#define DDRSS3_CTL_116_DATA 0x00040D40 +#define DDRSS3_CTL_117_DATA 0x00040D40 +#define DDRSS3_CTL_118_DATA 0x00040D40 +#define DDRSS3_CTL_119_DATA 0x00040D40 +#define DDRSS3_CTL_120_DATA 0x00040D40 +#define DDRSS3_CTL_121_DATA 0x00000000 +#define DDRSS3_CTL_122_DATA 0x00007173 +#define DDRSS3_CTL_123_DATA 0x00000000 +#define DDRSS3_CTL_124_DATA 0x00000000 +#define DDRSS3_CTL_125_DATA 0x00000000 +#define DDRSS3_CTL_126_DATA 0x00000000 +#define DDRSS3_CTL_127_DATA 0x00000000 +#define DDRSS3_CTL_128_DATA 0x00000000 +#define DDRSS3_CTL_129_DATA 0x00000000 +#define DDRSS3_CTL_130_DATA 0x00000000 +#define DDRSS3_CTL_131_DATA 0x0B030500 +#define DDRSS3_CTL_132_DATA 0x00040B04 +#define DDRSS3_CTL_133_DATA 0x0A090000 +#define DDRSS3_CTL_134_DATA 0x0A090701 +#define DDRSS3_CTL_135_DATA 0x0900000E +#define DDRSS3_CTL_136_DATA 0x0907010A +#define DDRSS3_CTL_137_DATA 0x00000E0A +#define DDRSS3_CTL_138_DATA 0x07010A09 +#define DDRSS3_CTL_139_DATA 0x000E0A09 +#define DDRSS3_CTL_140_DATA 0x07000401 +#define DDRSS3_CTL_141_DATA 0x00000000 +#define DDRSS3_CTL_142_DATA 0x00000000 +#define DDRSS3_CTL_143_DATA 0x00000000 +#define DDRSS3_CTL_144_DATA 0x00000000 +#define DDRSS3_CTL_145_DATA 0x00000000 +#define DDRSS3_CTL_146_DATA 0x00000000 +#define DDRSS3_CTL_147_DATA 0x00000000 +#define DDRSS3_CTL_148_DATA 0x08080000 +#define DDRSS3_CTL_149_DATA 0x01000000 +#define DDRSS3_CTL_150_DATA 0x800000C0 +#define DDRSS3_CTL_151_DATA 0x800000C0 +#define DDRSS3_CTL_152_DATA 0x800000C0 +#define DDRSS3_CTL_153_DATA 0x00000000 +#define DDRSS3_CTL_154_DATA 0x00001500 +#define DDRSS3_CTL_155_DATA 0x00000000 +#define DDRSS3_CTL_156_DATA 0x00000001 +#define DDRSS3_CTL_157_DATA 0x00000002 +#define DDRSS3_CTL_158_DATA 0x0000100E +#define DDRSS3_CTL_159_DATA 0x00000000 +#define DDRSS3_CTL_160_DATA 0x00000000 +#define DDRSS3_CTL_161_DATA 0x00000000 +#define DDRSS3_CTL_162_DATA 0x00000000 +#define DDRSS3_CTL_163_DATA 0x00000000 +#define DDRSS3_CTL_164_DATA 0x000B0000 +#define DDRSS3_CTL_165_DATA 0x000E0006 +#define DDRSS3_CTL_166_DATA 0x000E0404 +#define DDRSS3_CTL_167_DATA 0x00D601AB +#define DDRSS3_CTL_168_DATA 0x10100216 +#define DDRSS3_CTL_169_DATA 0x01AB0216 +#define DDRSS3_CTL_170_DATA 0x021600D6 +#define DDRSS3_CTL_171_DATA 0x02161010 +#define DDRSS3_CTL_172_DATA 0x00000000 +#define DDRSS3_CTL_173_DATA 0x00000000 +#define DDRSS3_CTL_174_DATA 0x00000000 +#define DDRSS3_CTL_175_DATA 0x3FF40084 +#define DDRSS3_CTL_176_DATA 0xF3003FF4 +#define DDRSS3_CTL_177_DATA 0x0000F3F3 +#define DDRSS3_CTL_178_DATA 0x35350000 +#define DDRSS3_CTL_179_DATA 0x27270035 +#define DDRSS3_CTL_180_DATA 0x0F0F0000 +#define DDRSS3_CTL_181_DATA 0x16000000 +#define DDRSS3_CTL_182_DATA 0x00841616 +#define DDRSS3_CTL_183_DATA 0x3FF43FF4 +#define DDRSS3_CTL_184_DATA 0xF3F3F300 +#define DDRSS3_CTL_185_DATA 0x00000000 +#define DDRSS3_CTL_186_DATA 0x00353535 +#define DDRSS3_CTL_187_DATA 0x00002727 +#define DDRSS3_CTL_188_DATA 0x00000F0F +#define DDRSS3_CTL_189_DATA 0x16161600 +#define DDRSS3_CTL_190_DATA 0x00000020 +#define DDRSS3_CTL_191_DATA 0x01000000 +#define DDRSS3_CTL_192_DATA 0x00000001 +#define DDRSS3_CTL_193_DATA 0x00000000 +#define DDRSS3_CTL_194_DATA 0x01000000 +#define DDRSS3_CTL_195_DATA 0x00000001 +#define DDRSS3_CTL_196_DATA 0x00000000 +#define DDRSS3_CTL_197_DATA 0x00000000 +#define DDRSS3_CTL_198_DATA 0x00000000 +#define DDRSS3_CTL_199_DATA 0x00000000 +#define DDRSS3_CTL_200_DATA 0x00000000 +#define DDRSS3_CTL_201_DATA 0x00000000 +#define DDRSS3_CTL_202_DATA 0x00000000 +#define DDRSS3_CTL_203_DATA 0x00000000 +#define DDRSS3_CTL_204_DATA 0x00000000 +#define DDRSS3_CTL_205_DATA 0x00000000 +#define DDRSS3_CTL_206_DATA 0x02000000 +#define DDRSS3_CTL_207_DATA 0x01080101 +#define DDRSS3_CTL_208_DATA 0x00000000 +#define DDRSS3_CTL_209_DATA 0x00000000 +#define DDRSS3_CTL_210_DATA 0x00000000 +#define DDRSS3_CTL_211_DATA 0x00000000 +#define DDRSS3_CTL_212_DATA 0x00000000 +#define DDRSS3_CTL_213_DATA 0x00000000 +#define DDRSS3_CTL_214_DATA 0x00000000 +#define DDRSS3_CTL_215_DATA 0x00000000 +#define DDRSS3_CTL_216_DATA 0x00000000 +#define DDRSS3_CTL_217_DATA 0x00000000 +#define DDRSS3_CTL_218_DATA 0x00000000 +#define DDRSS3_CTL_219_DATA 0x00000000 +#define DDRSS3_CTL_220_DATA 0x00000000 +#define DDRSS3_CTL_221_DATA 0x00000000 +#define DDRSS3_CTL_222_DATA 0x00001000 +#define DDRSS3_CTL_223_DATA 0x006403E8 +#define DDRSS3_CTL_224_DATA 0x00000000 +#define DDRSS3_CTL_225_DATA 0x00000000 +#define DDRSS3_CTL_226_DATA 0x00000000 +#define DDRSS3_CTL_227_DATA 0x15110000 +#define DDRSS3_CTL_228_DATA 0x00040C18 +#define DDRSS3_CTL_229_DATA 0xF000C000 +#define DDRSS3_CTL_230_DATA 0x0000F000 +#define DDRSS3_CTL_231_DATA 0x00000000 +#define DDRSS3_CTL_232_DATA 0x00000000 +#define DDRSS3_CTL_233_DATA 0xC0000000 +#define DDRSS3_CTL_234_DATA 0xF000F000 +#define DDRSS3_CTL_235_DATA 0x00000000 +#define DDRSS3_CTL_236_DATA 0x00000000 +#define DDRSS3_CTL_237_DATA 0x00000000 +#define DDRSS3_CTL_238_DATA 0xF000C000 +#define DDRSS3_CTL_239_DATA 0x0000F000 +#define DDRSS3_CTL_240_DATA 0x00000000 +#define DDRSS3_CTL_241_DATA 0x00000000 +#define DDRSS3_CTL_242_DATA 0x00030000 +#define DDRSS3_CTL_243_DATA 0x00000000 +#define DDRSS3_CTL_244_DATA 0x00000000 +#define DDRSS3_CTL_245_DATA 0x00000000 +#define DDRSS3_CTL_246_DATA 0x00000000 +#define DDRSS3_CTL_247_DATA 0x00000000 +#define DDRSS3_CTL_248_DATA 0x00000000 +#define DDRSS3_CTL_249_DATA 0x00000000 +#define DDRSS3_CTL_250_DATA 0x00000000 +#define DDRSS3_CTL_251_DATA 0x00000000 +#define DDRSS3_CTL_252_DATA 0x00000000 +#define DDRSS3_CTL_253_DATA 0x00000000 +#define DDRSS3_CTL_254_DATA 0x00000000 +#define DDRSS3_CTL_255_DATA 0x00000000 +#define DDRSS3_CTL_256_DATA 0x00000000 +#define DDRSS3_CTL_257_DATA 0x01000200 +#define DDRSS3_CTL_258_DATA 0x00370040 +#define DDRSS3_CTL_259_DATA 0x00020008 +#define DDRSS3_CTL_260_DATA 0x00400100 +#define DDRSS3_CTL_261_DATA 0x00400855 +#define DDRSS3_CTL_262_DATA 0x01000200 +#define DDRSS3_CTL_263_DATA 0x08550040 +#define DDRSS3_CTL_264_DATA 0x00000040 +#define DDRSS3_CTL_265_DATA 0x006B0003 +#define DDRSS3_CTL_266_DATA 0x0100006B +#define DDRSS3_CTL_267_DATA 0x03030303 +#define DDRSS3_CTL_268_DATA 0x00000000 +#define DDRSS3_CTL_269_DATA 0x00000202 +#define DDRSS3_CTL_270_DATA 0x00001FFF +#define DDRSS3_CTL_271_DATA 0x3FFF2000 +#define DDRSS3_CTL_272_DATA 0x03FF0000 +#define DDRSS3_CTL_273_DATA 0x000103FF +#define DDRSS3_CTL_274_DATA 0x0FFF0B00 +#define DDRSS3_CTL_275_DATA 0x01010001 +#define DDRSS3_CTL_276_DATA 0x01010101 +#define DDRSS3_CTL_277_DATA 0x01180101 +#define DDRSS3_CTL_278_DATA 0x00030000 +#define DDRSS3_CTL_279_DATA 0x00000000 +#define DDRSS3_CTL_280_DATA 0x00000000 +#define DDRSS3_CTL_281_DATA 0x00000000 +#define DDRSS3_CTL_282_DATA 0x00000000 +#define DDRSS3_CTL_283_DATA 0x00000000 +#define DDRSS3_CTL_284_DATA 0x00000000 +#define DDRSS3_CTL_285_DATA 0x00000000 +#define DDRSS3_CTL_286_DATA 0x00040101 +#define DDRSS3_CTL_287_DATA 0x04010100 +#define DDRSS3_CTL_288_DATA 0x00000000 +#define DDRSS3_CTL_289_DATA 0x00000000 +#define DDRSS3_CTL_290_DATA 0x03030300 +#define DDRSS3_CTL_291_DATA 0x00010101 +#define DDRSS3_CTL_292_DATA 0x00000000 +#define DDRSS3_CTL_293_DATA 0x00000000 +#define DDRSS3_CTL_294_DATA 0x00000000 +#define DDRSS3_CTL_295_DATA 0x00000000 +#define DDRSS3_CTL_296_DATA 0x00000000 +#define DDRSS3_CTL_297_DATA 0xFFFFFFFF +#define DDRSS3_CTL_298_DATA 0x00000FFF +#define DDRSS3_CTL_299_DATA 0x00000000 +#define DDRSS3_CTL_300_DATA 0x00000000 +#define DDRSS3_CTL_301_DATA 0x00000000 +#define DDRSS3_CTL_302_DATA 0x00000000 +#define DDRSS3_CTL_303_DATA 0x00000000 +#define DDRSS3_CTL_304_DATA 0x00000000 +#define DDRSS3_CTL_305_DATA 0x00000000 +#define DDRSS3_CTL_306_DATA 0x00000000 +#define DDRSS3_CTL_307_DATA 0x00000000 +#define DDRSS3_CTL_308_DATA 0x00000000 +#define DDRSS3_CTL_309_DATA 0x00000000 +#define DDRSS3_CTL_310_DATA 0x00000000 +#define DDRSS3_CTL_311_DATA 0x00000000 +#define DDRSS3_CTL_312_DATA 0x00000000 +#define DDRSS3_CTL_313_DATA 0x01000000 +#define DDRSS3_CTL_314_DATA 0x00020201 +#define DDRSS3_CTL_315_DATA 0x01000101 +#define DDRSS3_CTL_316_DATA 0x01010001 +#define DDRSS3_CTL_317_DATA 0x00010101 +#define DDRSS3_CTL_318_DATA 0x050A0A03 +#define DDRSS3_CTL_319_DATA 0x10082323 +#define DDRSS3_CTL_320_DATA 0x00090310 +#define DDRSS3_CTL_321_DATA 0x0B0C030F +#define DDRSS3_CTL_322_DATA 0x0B0C0306 +#define DDRSS3_CTL_323_DATA 0x0C090006 +#define DDRSS3_CTL_324_DATA 0x0100000C +#define DDRSS3_CTL_325_DATA 0x08040801 +#define DDRSS3_CTL_326_DATA 0x00000004 +#define DDRSS3_CTL_327_DATA 0x00000000 +#define DDRSS3_CTL_328_DATA 0x00010000 +#define DDRSS3_CTL_329_DATA 0x00280D00 +#define DDRSS3_CTL_330_DATA 0x00000001 +#define DDRSS3_CTL_331_DATA 0x00030001 +#define DDRSS3_CTL_332_DATA 0x00000000 +#define DDRSS3_CTL_333_DATA 0x00000000 +#define DDRSS3_CTL_334_DATA 0x00000000 +#define DDRSS3_CTL_335_DATA 0x00000000 +#define DDRSS3_CTL_336_DATA 0x00000000 +#define DDRSS3_CTL_337_DATA 0x00000000 +#define DDRSS3_CTL_338_DATA 0x00000000 +#define DDRSS3_CTL_339_DATA 0x00000000 +#define DDRSS3_CTL_340_DATA 0x01000000 +#define DDRSS3_CTL_341_DATA 0x00000001 +#define DDRSS3_CTL_342_DATA 0x00010100 +#define DDRSS3_CTL_343_DATA 0x03030000 +#define DDRSS3_CTL_344_DATA 0x00000000 +#define DDRSS3_CTL_345_DATA 0x00000000 +#define DDRSS3_CTL_346_DATA 0x00000000 +#define DDRSS3_CTL_347_DATA 0x00000000 +#define DDRSS3_CTL_348_DATA 0x00000000 +#define DDRSS3_CTL_349_DATA 0x00000000 +#define DDRSS3_CTL_350_DATA 0x00000000 +#define DDRSS3_CTL_351_DATA 0x00000000 +#define DDRSS3_CTL_352_DATA 0x00000000 +#define DDRSS3_CTL_353_DATA 0x00000000 +#define DDRSS3_CTL_354_DATA 0x00000000 +#define DDRSS3_CTL_355_DATA 0x00000000 +#define DDRSS3_CTL_356_DATA 0x00000000 +#define DDRSS3_CTL_357_DATA 0x00000000 +#define DDRSS3_CTL_358_DATA 0x00000000 +#define DDRSS3_CTL_359_DATA 0x00000000 +#define DDRSS3_CTL_360_DATA 0x000556AA +#define DDRSS3_CTL_361_DATA 0x000AAAAA +#define DDRSS3_CTL_362_DATA 0x000AA955 +#define DDRSS3_CTL_363_DATA 0x00055555 +#define DDRSS3_CTL_364_DATA 0x000B3133 +#define DDRSS3_CTL_365_DATA 0x0004CD33 +#define DDRSS3_CTL_366_DATA 0x0004CECC +#define DDRSS3_CTL_367_DATA 0x000B32CC +#define DDRSS3_CTL_368_DATA 0x00010300 +#define DDRSS3_CTL_369_DATA 0x03000100 +#define DDRSS3_CTL_370_DATA 0x00000000 +#define DDRSS3_CTL_371_DATA 0x00000000 +#define DDRSS3_CTL_372_DATA 0x00000000 +#define DDRSS3_CTL_373_DATA 0x00000000 +#define DDRSS3_CTL_374_DATA 0x00000000 +#define DDRSS3_CTL_375_DATA 0x00000000 +#define DDRSS3_CTL_376_DATA 0x00000000 +#define DDRSS3_CTL_377_DATA 0x00010000 +#define DDRSS3_CTL_378_DATA 0x00000404 +#define DDRSS3_CTL_379_DATA 0x00000000 +#define DDRSS3_CTL_380_DATA 0x00000000 +#define DDRSS3_CTL_381_DATA 0x00000000 +#define DDRSS3_CTL_382_DATA 0x00000000 +#define DDRSS3_CTL_383_DATA 0x00000000 +#define DDRSS3_CTL_384_DATA 0x00000000 +#define DDRSS3_CTL_385_DATA 0x00000000 +#define DDRSS3_CTL_386_DATA 0x00000000 +#define DDRSS3_CTL_387_DATA 0x3A3A1B00 +#define DDRSS3_CTL_388_DATA 0x000A0000 +#define DDRSS3_CTL_389_DATA 0x000000C6 +#define DDRSS3_CTL_390_DATA 0x00000200 +#define DDRSS3_CTL_391_DATA 0x00000200 +#define DDRSS3_CTL_392_DATA 0x00000200 +#define DDRSS3_CTL_393_DATA 0x00000200 +#define DDRSS3_CTL_394_DATA 0x00000270 +#define DDRSS3_CTL_395_DATA 0x000007BC +#define DDRSS3_CTL_396_DATA 0x00000204 +#define DDRSS3_CTL_397_DATA 0x0000206A +#define DDRSS3_CTL_398_DATA 0x00000200 +#define DDRSS3_CTL_399_DATA 0x00000200 +#define DDRSS3_CTL_400_DATA 0x00000200 +#define DDRSS3_CTL_401_DATA 0x00000200 +#define DDRSS3_CTL_402_DATA 0x0000613E +#define DDRSS3_CTL_403_DATA 0x00014424 +#define DDRSS3_CTL_404_DATA 0x00000E19 +#define DDRSS3_CTL_405_DATA 0x0000206A +#define DDRSS3_CTL_406_DATA 0x00000200 +#define DDRSS3_CTL_407_DATA 0x00000200 +#define DDRSS3_CTL_408_DATA 0x00000200 +#define DDRSS3_CTL_409_DATA 0x00000200 +#define DDRSS3_CTL_410_DATA 0x0000613E +#define DDRSS3_CTL_411_DATA 0x00014424 +#define DDRSS3_CTL_412_DATA 0x02020E19 +#define DDRSS3_CTL_413_DATA 0x03030202 +#define DDRSS3_CTL_414_DATA 0x00000022 +#define DDRSS3_CTL_415_DATA 0x00000000 +#define DDRSS3_CTL_416_DATA 0x00000000 +#define DDRSS3_CTL_417_DATA 0x00001403 +#define DDRSS3_CTL_418_DATA 0x000007D0 +#define DDRSS3_CTL_419_DATA 0x00000000 +#define DDRSS3_CTL_420_DATA 0x00000000 +#define DDRSS3_CTL_421_DATA 0x00030000 +#define DDRSS3_CTL_422_DATA 0x0007001F +#define DDRSS3_CTL_423_DATA 0x001B0033 +#define DDRSS3_CTL_424_DATA 0x001B0033 +#define DDRSS3_CTL_425_DATA 0x00000000 +#define DDRSS3_CTL_426_DATA 0x00000000 +#define DDRSS3_CTL_427_DATA 0x02000000 +#define DDRSS3_CTL_428_DATA 0x01000404 +#define DDRSS3_CTL_429_DATA 0x0B220B22 +#define DDRSS3_CTL_430_DATA 0x00000105 +#define DDRSS3_CTL_431_DATA 0x00010101 +#define DDRSS3_CTL_432_DATA 0x00010101 +#define DDRSS3_CTL_433_DATA 0x00010001 +#define DDRSS3_CTL_434_DATA 0x00000101 +#define DDRSS3_CTL_435_DATA 0x02000201 +#define DDRSS3_CTL_436_DATA 0x02010000 +#define DDRSS3_CTL_437_DATA 0x00000200 +#define DDRSS3_CTL_438_DATA 0x28060000 +#define DDRSS3_CTL_439_DATA 0x00000128 +#define DDRSS3_CTL_440_DATA 0xFFFFFFFF +#define DDRSS3_CTL_441_DATA 0xFFFFFFFF +#define DDRSS3_CTL_442_DATA 0x00000000 +#define DDRSS3_CTL_443_DATA 0x00000000 +#define DDRSS3_CTL_444_DATA 0x00000000 +#define DDRSS3_CTL_445_DATA 0x00000000 +#define DDRSS3_CTL_446_DATA 0x00000000 +#define DDRSS3_CTL_447_DATA 0x00000000 +#define DDRSS3_CTL_448_DATA 0x00000000 +#define DDRSS3_CTL_449_DATA 0x00000000 +#define DDRSS3_CTL_450_DATA 0x00000000 +#define DDRSS3_CTL_451_DATA 0x00000000 +#define DDRSS3_CTL_452_DATA 0x00000000 +#define DDRSS3_CTL_453_DATA 0x00000000 +#define DDRSS3_CTL_454_DATA 0x00000000 +#define DDRSS3_CTL_455_DATA 0x00000000 +#define DDRSS3_CTL_456_DATA 0x00000000 +#define DDRSS3_CTL_457_DATA 0x00000000 +#define DDRSS3_CTL_458_DATA 0x00000000 + +#define DDRSS3_PI_00_DATA 0x00000B00 +#define DDRSS3_PI_01_DATA 0x00000000 +#define DDRSS3_PI_02_DATA 0x00000000 +#define DDRSS3_PI_03_DATA 0x00000000 +#define DDRSS3_PI_04_DATA 0x00000000 +#define DDRSS3_PI_05_DATA 0x00000101 +#define DDRSS3_PI_06_DATA 0x00640000 +#define DDRSS3_PI_07_DATA 0x00000001 +#define DDRSS3_PI_08_DATA 0x00000000 +#define DDRSS3_PI_09_DATA 0x00000000 +#define DDRSS3_PI_10_DATA 0x00000000 +#define DDRSS3_PI_11_DATA 0x00000000 +#define DDRSS3_PI_12_DATA 0x00000003 +#define DDRSS3_PI_13_DATA 0x00010001 +#define DDRSS3_PI_14_DATA 0x0800000F +#define DDRSS3_PI_15_DATA 0x00000103 +#define DDRSS3_PI_16_DATA 0x00000005 +#define DDRSS3_PI_17_DATA 0x00000000 +#define DDRSS3_PI_18_DATA 0x00000000 +#define DDRSS3_PI_19_DATA 0x00000000 +#define DDRSS3_PI_20_DATA 0x00000000 +#define DDRSS3_PI_21_DATA 0x00000000 +#define DDRSS3_PI_22_DATA 0x00000000 +#define DDRSS3_PI_23_DATA 0x00000000 +#define DDRSS3_PI_24_DATA 0x00000000 +#define DDRSS3_PI_25_DATA 0x00000000 +#define DDRSS3_PI_26_DATA 0x00010100 +#define DDRSS3_PI_27_DATA 0x00280A00 +#define DDRSS3_PI_28_DATA 0x00000000 +#define DDRSS3_PI_29_DATA 0x0F000000 +#define DDRSS3_PI_30_DATA 0x00003200 +#define DDRSS3_PI_31_DATA 0x00000000 +#define DDRSS3_PI_32_DATA 0x00000000 +#define DDRSS3_PI_33_DATA 0x01010102 +#define DDRSS3_PI_34_DATA 0x00000000 +#define DDRSS3_PI_35_DATA 0x000000AA +#define DDRSS3_PI_36_DATA 0x00000055 +#define DDRSS3_PI_37_DATA 0x000000B5 +#define DDRSS3_PI_38_DATA 0x0000004A +#define DDRSS3_PI_39_DATA 0x00000056 +#define DDRSS3_PI_40_DATA 0x000000A9 +#define DDRSS3_PI_41_DATA 0x000000A9 +#define DDRSS3_PI_42_DATA 0x000000B5 +#define DDRSS3_PI_43_DATA 0x00000000 +#define DDRSS3_PI_44_DATA 0x00000000 +#define DDRSS3_PI_45_DATA 0x000F0F00 +#define DDRSS3_PI_46_DATA 0x0000001B +#define DDRSS3_PI_47_DATA 0x000007D0 +#define DDRSS3_PI_48_DATA 0x00000300 +#define DDRSS3_PI_49_DATA 0x00000000 +#define DDRSS3_PI_50_DATA 0x00000000 +#define DDRSS3_PI_51_DATA 0x01000000 +#define DDRSS3_PI_52_DATA 0x00010101 +#define DDRSS3_PI_53_DATA 0x00000000 +#define DDRSS3_PI_54_DATA 0x00030000 +#define DDRSS3_PI_55_DATA 0x0F000000 +#define DDRSS3_PI_56_DATA 0x00000017 +#define DDRSS3_PI_57_DATA 0x00000000 +#define DDRSS3_PI_58_DATA 0x00000000 +#define DDRSS3_PI_59_DATA 0x00000000 +#define DDRSS3_PI_60_DATA 0x0A0A140A +#define DDRSS3_PI_61_DATA 0x10020201 +#define DDRSS3_PI_62_DATA 0x00020805 +#define DDRSS3_PI_63_DATA 0x01000404 +#define DDRSS3_PI_64_DATA 0x00000000 +#define DDRSS3_PI_65_DATA 0x00000000 +#define DDRSS3_PI_66_DATA 0x00000100 +#define DDRSS3_PI_67_DATA 0x0002020F +#define DDRSS3_PI_68_DATA 0x00340000 +#define DDRSS3_PI_69_DATA 0x00000000 +#define DDRSS3_PI_70_DATA 0x00000000 +#define DDRSS3_PI_71_DATA 0x0000FFFF +#define DDRSS3_PI_72_DATA 0x01000000 +#define DDRSS3_PI_73_DATA 0x00080000 +#define DDRSS3_PI_74_DATA 0x02000200 +#define DDRSS3_PI_75_DATA 0x01000100 +#define DDRSS3_PI_76_DATA 0x01000000 +#define DDRSS3_PI_77_DATA 0x02000200 +#define DDRSS3_PI_78_DATA 0x00000200 +#define DDRSS3_PI_79_DATA 0x00000000 +#define DDRSS3_PI_80_DATA 0x00000000 +#define DDRSS3_PI_81_DATA 0x00000000 +#define DDRSS3_PI_82_DATA 0x00000000 +#define DDRSS3_PI_83_DATA 0x00000000 +#define DDRSS3_PI_84_DATA 0x00000000 +#define DDRSS3_PI_85_DATA 0x00000000 +#define DDRSS3_PI_86_DATA 0x00000000 +#define DDRSS3_PI_87_DATA 0x00000000 +#define DDRSS3_PI_88_DATA 0x00000000 +#define DDRSS3_PI_89_DATA 0x00000000 +#define DDRSS3_PI_90_DATA 0x00000000 +#define DDRSS3_PI_91_DATA 0x00000400 +#define DDRSS3_PI_92_DATA 0x02010000 +#define DDRSS3_PI_93_DATA 0x00080003 +#define DDRSS3_PI_94_DATA 0x00080000 +#define DDRSS3_PI_95_DATA 0x00000001 +#define DDRSS3_PI_96_DATA 0x00000000 +#define DDRSS3_PI_97_DATA 0x0000AA00 +#define DDRSS3_PI_98_DATA 0x00000000 +#define DDRSS3_PI_99_DATA 0x00000000 +#define DDRSS3_PI_100_DATA 0x00010000 +#define DDRSS3_PI_101_DATA 0x00000000 +#define DDRSS3_PI_102_DATA 0x00000000 +#define DDRSS3_PI_103_DATA 0x00000000 +#define DDRSS3_PI_104_DATA 0x00000000 +#define DDRSS3_PI_105_DATA 0x00000000 +#define DDRSS3_PI_106_DATA 0x00000000 +#define DDRSS3_PI_107_DATA 0x00000000 +#define DDRSS3_PI_108_DATA 0x00000000 +#define DDRSS3_PI_109_DATA 0x00000000 +#define DDRSS3_PI_110_DATA 0x00000000 +#define DDRSS3_PI_111_DATA 0x00000000 +#define DDRSS3_PI_112_DATA 0x00000000 +#define DDRSS3_PI_113_DATA 0x00000000 +#define DDRSS3_PI_114_DATA 0x00000000 +#define DDRSS3_PI_115_DATA 0x00000000 +#define DDRSS3_PI_116_DATA 0x00000000 +#define DDRSS3_PI_117_DATA 0x00000000 +#define DDRSS3_PI_118_DATA 0x00000000 +#define DDRSS3_PI_119_DATA 0x00000000 +#define DDRSS3_PI_120_DATA 0x00000000 +#define DDRSS3_PI_121_DATA 0x00000000 +#define DDRSS3_PI_122_DATA 0x00000000 +#define DDRSS3_PI_123_DATA 0x00000000 +#define DDRSS3_PI_124_DATA 0x00000000 +#define DDRSS3_PI_125_DATA 0x00000008 +#define DDRSS3_PI_126_DATA 0x00000000 +#define DDRSS3_PI_127_DATA 0x00000000 +#define DDRSS3_PI_128_DATA 0x00000000 +#define DDRSS3_PI_129_DATA 0x00000000 +#define DDRSS3_PI_130_DATA 0x00000000 +#define DDRSS3_PI_131_DATA 0x00000000 +#define DDRSS3_PI_132_DATA 0x00000000 +#define DDRSS3_PI_133_DATA 0x00000000 +#define DDRSS3_PI_134_DATA 0x00000002 +#define DDRSS3_PI_135_DATA 0x00000000 +#define DDRSS3_PI_136_DATA 0x00000000 +#define DDRSS3_PI_137_DATA 0x0000000A +#define DDRSS3_PI_138_DATA 0x00000019 +#define DDRSS3_PI_139_DATA 0x00000100 +#define DDRSS3_PI_140_DATA 0x00000000 +#define DDRSS3_PI_141_DATA 0x00000000 +#define DDRSS3_PI_142_DATA 0x00000000 +#define DDRSS3_PI_143_DATA 0x00000000 +#define DDRSS3_PI_144_DATA 0x01000000 +#define DDRSS3_PI_145_DATA 0x00010003 +#define DDRSS3_PI_146_DATA 0x02000101 +#define DDRSS3_PI_147_DATA 0x01030001 +#define DDRSS3_PI_148_DATA 0x00010400 +#define DDRSS3_PI_149_DATA 0x06000105 +#define DDRSS3_PI_150_DATA 0x01070001 +#define DDRSS3_PI_151_DATA 0x00000000 +#define DDRSS3_PI_152_DATA 0x00000000 +#define DDRSS3_PI_153_DATA 0x00000000 +#define DDRSS3_PI_154_DATA 0x00010001 +#define DDRSS3_PI_155_DATA 0x00000000 +#define DDRSS3_PI_156_DATA 0x00000000 +#define DDRSS3_PI_157_DATA 0x00000000 +#define DDRSS3_PI_158_DATA 0x00000000 +#define DDRSS3_PI_159_DATA 0x00000401 +#define DDRSS3_PI_160_DATA 0x00000000 +#define DDRSS3_PI_161_DATA 0x05010000 +#define DDRSS3_PI_162_DATA 0x00000001 +#define DDRSS3_PI_163_DATA 0x2B2B0201 +#define DDRSS3_PI_164_DATA 0x00000034 +#define DDRSS3_PI_165_DATA 0x00000068 +#define DDRSS3_PI_166_DATA 0x00020068 +#define DDRSS3_PI_167_DATA 0x02000200 +#define DDRSS3_PI_168_DATA 0x50120C04 +#define DDRSS3_PI_169_DATA 0x00155012 +#define DDRSS3_PI_170_DATA 0x00000068 +#define DDRSS3_PI_171_DATA 0x0000032B +#define DDRSS3_PI_172_DATA 0x00001035 +#define DDRSS3_PI_173_DATA 0x0000032B +#define DDRSS3_PI_174_DATA 0x04001035 +#define DDRSS3_PI_175_DATA 0x01010404 +#define DDRSS3_PI_176_DATA 0x00001500 +#define DDRSS3_PI_177_DATA 0x00150015 +#define DDRSS3_PI_178_DATA 0x01000100 +#define DDRSS3_PI_179_DATA 0x00000100 +#define DDRSS3_PI_180_DATA 0x00000000 +#define DDRSS3_PI_181_DATA 0x01010101 +#define DDRSS3_PI_182_DATA 0x00000000 +#define DDRSS3_PI_183_DATA 0x00000000 +#define DDRSS3_PI_184_DATA 0x00000000 +#define DDRSS3_PI_185_DATA 0x19040000 +#define DDRSS3_PI_186_DATA 0x0E0E0219 +#define DDRSS3_PI_187_DATA 0x00040402 +#define DDRSS3_PI_188_DATA 0x000D0035 +#define DDRSS3_PI_189_DATA 0x00218049 +#define DDRSS3_PI_190_DATA 0x00218049 +#define DDRSS3_PI_191_DATA 0x01000101 +#define DDRSS3_PI_192_DATA 0x0004000E +#define DDRSS3_PI_193_DATA 0x00040216 +#define DDRSS3_PI_194_DATA 0x01000216 +#define DDRSS3_PI_195_DATA 0x000F000F +#define DDRSS3_PI_196_DATA 0x02170100 +#define DDRSS3_PI_197_DATA 0x01000217 +#define DDRSS3_PI_198_DATA 0x02170217 +#define DDRSS3_PI_199_DATA 0x2F1B3200 +#define DDRSS3_PI_200_DATA 0x01012F1B +#define DDRSS3_PI_201_DATA 0x0A070601 +#define DDRSS3_PI_202_DATA 0x1F130A0D +#define DDRSS3_PI_203_DATA 0x1F130A14 +#define DDRSS3_PI_204_DATA 0x0000C014 +#define DDRSS3_PI_205_DATA 0x00C01000 +#define DDRSS3_PI_206_DATA 0x00C01000 +#define DDRSS3_PI_207_DATA 0x00021000 +#define DDRSS3_PI_208_DATA 0x0024000E +#define DDRSS3_PI_209_DATA 0x00240216 +#define DDRSS3_PI_210_DATA 0x00110216 +#define DDRSS3_PI_211_DATA 0x32000056 +#define DDRSS3_PI_212_DATA 0x00000101 +#define DDRSS3_PI_213_DATA 0x005F0036 +#define DDRSS3_PI_214_DATA 0x03013212 +#define DDRSS3_PI_215_DATA 0x00003600 +#define DDRSS3_PI_216_DATA 0x3212005F +#define DDRSS3_PI_217_DATA 0x09000001 +#define DDRSS3_PI_218_DATA 0x06010504 +#define DDRSS3_PI_219_DATA 0x04000364 +#define DDRSS3_PI_220_DATA 0x0A032001 +#define DDRSS3_PI_221_DATA 0x2C31110A +#define DDRSS3_PI_222_DATA 0x00002918 +#define DDRSS3_PI_223_DATA 0x6000838E +#define DDRSS3_PI_224_DATA 0x1E202008 +#define DDRSS3_PI_225_DATA 0x2C311116 +#define DDRSS3_PI_226_DATA 0x00002918 +#define DDRSS3_PI_227_DATA 0x6000838E +#define DDRSS3_PI_228_DATA 0x1E202008 +#define DDRSS3_PI_229_DATA 0x0000C616 +#define DDRSS3_PI_230_DATA 0x000007BC +#define DDRSS3_PI_231_DATA 0x0000206A +#define DDRSS3_PI_232_DATA 0x00014424 +#define DDRSS3_PI_233_DATA 0x0000206A +#define DDRSS3_PI_234_DATA 0x00014424 +#define DDRSS3_PI_235_DATA 0x033B0016 +#define DDRSS3_PI_236_DATA 0x0303033B +#define DDRSS3_PI_237_DATA 0x002AF803 +#define DDRSS3_PI_238_DATA 0x0001ADAF +#define DDRSS3_PI_239_DATA 0x00000005 +#define DDRSS3_PI_240_DATA 0x0000006E +#define DDRSS3_PI_241_DATA 0x00000016 +#define DDRSS3_PI_242_DATA 0x000681C8 +#define DDRSS3_PI_243_DATA 0x0001ADAF +#define DDRSS3_PI_244_DATA 0x00000005 +#define DDRSS3_PI_245_DATA 0x000010A9 +#define DDRSS3_PI_246_DATA 0x0000033B +#define DDRSS3_PI_247_DATA 0x000681C8 +#define DDRSS3_PI_248_DATA 0x0001ADAF +#define DDRSS3_PI_249_DATA 0x00000005 +#define DDRSS3_PI_250_DATA 0x000010A9 +#define DDRSS3_PI_251_DATA 0x0100033B +#define DDRSS3_PI_252_DATA 0x00370040 +#define DDRSS3_PI_253_DATA 0x00010008 +#define DDRSS3_PI_254_DATA 0x08550040 +#define DDRSS3_PI_255_DATA 0x00010040 +#define DDRSS3_PI_256_DATA 0x08550040 +#define DDRSS3_PI_257_DATA 0x00000340 +#define DDRSS3_PI_258_DATA 0x006B006B +#define DDRSS3_PI_259_DATA 0x08040404 +#define DDRSS3_PI_260_DATA 0x00000055 +#define DDRSS3_PI_261_DATA 0x55083C5A +#define DDRSS3_PI_262_DATA 0x5A000000 +#define DDRSS3_PI_263_DATA 0x0055083C +#define DDRSS3_PI_264_DATA 0x3C5A0000 +#define DDRSS3_PI_265_DATA 0x00005508 +#define DDRSS3_PI_266_DATA 0x0C3C5A00 +#define DDRSS3_PI_267_DATA 0x080F0E0D +#define DDRSS3_PI_268_DATA 0x000B0A09 +#define DDRSS3_PI_269_DATA 0x00030201 +#define DDRSS3_PI_270_DATA 0x01000000 +#define DDRSS3_PI_271_DATA 0x04020201 +#define DDRSS3_PI_272_DATA 0x00080804 +#define DDRSS3_PI_273_DATA 0x00000000 +#define DDRSS3_PI_274_DATA 0x00000000 +#define DDRSS3_PI_275_DATA 0x35F30084 +#define DDRSS3_PI_276_DATA 0x00160000 +#define DDRSS3_PI_277_DATA 0x35F33FF4 +#define DDRSS3_PI_278_DATA 0x00160F27 +#define DDRSS3_PI_279_DATA 0x35F33FF4 +#define DDRSS3_PI_280_DATA 0x00160F27 +#define DDRSS3_PI_281_DATA 0x35F30084 +#define DDRSS3_PI_282_DATA 0x00160000 +#define DDRSS3_PI_283_DATA 0x35F33FF4 +#define DDRSS3_PI_284_DATA 0x00160F27 +#define DDRSS3_PI_285_DATA 0x35F33FF4 +#define DDRSS3_PI_286_DATA 0x00160F27 +#define DDRSS3_PI_287_DATA 0x35F30084 +#define DDRSS3_PI_288_DATA 0x00160000 +#define DDRSS3_PI_289_DATA 0x35F33FF4 +#define DDRSS3_PI_290_DATA 0x00160F27 +#define DDRSS3_PI_291_DATA 0x35F33FF4 +#define DDRSS3_PI_292_DATA 0x00160F27 +#define DDRSS3_PI_293_DATA 0x35F30084 +#define DDRSS3_PI_294_DATA 0x00160000 +#define DDRSS3_PI_295_DATA 0x35F33FF4 +#define DDRSS3_PI_296_DATA 0x00160F27 +#define DDRSS3_PI_297_DATA 0x35F33FF4 +#define DDRSS3_PI_298_DATA 0x00160F27 +#define DDRSS3_PI_299_DATA 0x00000000 + +#define DDRSS3_PHY_00_DATA 0x000004F0 +#define DDRSS3_PHY_01_DATA 0x00000000 +#define DDRSS3_PHY_02_DATA 0x00030200 +#define DDRSS3_PHY_03_DATA 0x00000000 +#define DDRSS3_PHY_04_DATA 0x00000000 +#define DDRSS3_PHY_05_DATA 0x01030000 +#define DDRSS3_PHY_06_DATA 0x00010000 +#define DDRSS3_PHY_07_DATA 0x01030004 +#define DDRSS3_PHY_08_DATA 0x01000000 +#define DDRSS3_PHY_09_DATA 0x00000000 +#define DDRSS3_PHY_10_DATA 0x00000000 +#define DDRSS3_PHY_11_DATA 0x01000001 +#define DDRSS3_PHY_12_DATA 0x00000200 +#define DDRSS3_PHY_13_DATA 0x000800C0 +#define DDRSS3_PHY_14_DATA 0x060100CC +#define DDRSS3_PHY_15_DATA 0x00030066 +#define DDRSS3_PHY_16_DATA 0x00000000 +#define DDRSS3_PHY_17_DATA 0x00000301 +#define DDRSS3_PHY_18_DATA 0x0000AAAA +#define DDRSS3_PHY_19_DATA 0x00005555 +#define DDRSS3_PHY_20_DATA 0x0000B5B5 +#define DDRSS3_PHY_21_DATA 0x00004A4A +#define DDRSS3_PHY_22_DATA 0x00005656 +#define DDRSS3_PHY_23_DATA 0x0000A9A9 +#define DDRSS3_PHY_24_DATA 0x0000A9A9 +#define DDRSS3_PHY_25_DATA 0x0000B5B5 +#define DDRSS3_PHY_26_DATA 0x00000000 +#define DDRSS3_PHY_27_DATA 0x00000000 +#define DDRSS3_PHY_28_DATA 0x2A000000 +#define DDRSS3_PHY_29_DATA 0x00000808 +#define DDRSS3_PHY_30_DATA 0x0F000000 +#define DDRSS3_PHY_31_DATA 0x00000F08 +#define DDRSS3_PHY_32_DATA 0x10400000 +#define DDRSS3_PHY_33_DATA 0x0C002006 +#define DDRSS3_PHY_34_DATA 0x00000000 +#define DDRSS3_PHY_35_DATA 0x00000000 +#define DDRSS3_PHY_36_DATA 0x55555555 +#define DDRSS3_PHY_37_DATA 0xAAAAAAAA +#define DDRSS3_PHY_38_DATA 0x55555555 +#define DDRSS3_PHY_39_DATA 0xAAAAAAAA +#define DDRSS3_PHY_40_DATA 0x00005555 +#define DDRSS3_PHY_41_DATA 0x01000100 +#define DDRSS3_PHY_42_DATA 0x00800180 +#define DDRSS3_PHY_43_DATA 0x00000001 +#define DDRSS3_PHY_44_DATA 0x00000000 +#define DDRSS3_PHY_45_DATA 0x00000000 +#define DDRSS3_PHY_46_DATA 0x00000000 +#define DDRSS3_PHY_47_DATA 0x00000000 +#define DDRSS3_PHY_48_DATA 0x00000000 +#define DDRSS3_PHY_49_DATA 0x00000000 +#define DDRSS3_PHY_50_DATA 0x00000000 +#define DDRSS3_PHY_51_DATA 0x00000000 +#define DDRSS3_PHY_52_DATA 0x00000000 +#define DDRSS3_PHY_53_DATA 0x00000000 +#define DDRSS3_PHY_54_DATA 0x00000000 +#define DDRSS3_PHY_55_DATA 0x00000000 +#define DDRSS3_PHY_56_DATA 0x00000000 +#define DDRSS3_PHY_57_DATA 0x00000000 +#define DDRSS3_PHY_58_DATA 0x00000000 +#define DDRSS3_PHY_59_DATA 0x00000000 +#define DDRSS3_PHY_60_DATA 0x00000000 +#define DDRSS3_PHY_61_DATA 0x00000000 +#define DDRSS3_PHY_62_DATA 0x00000000 +#define DDRSS3_PHY_63_DATA 0x00000000 +#define DDRSS3_PHY_64_DATA 0x00000000 +#define DDRSS3_PHY_65_DATA 0x00000000 +#define DDRSS3_PHY_66_DATA 0x00000104 +#define DDRSS3_PHY_67_DATA 0x00000120 +#define DDRSS3_PHY_68_DATA 0x00000000 +#define DDRSS3_PHY_69_DATA 0x00000000 +#define DDRSS3_PHY_70_DATA 0x00000000 +#define DDRSS3_PHY_71_DATA 0x00000000 +#define DDRSS3_PHY_72_DATA 0x00000000 +#define DDRSS3_PHY_73_DATA 0x00000000 +#define DDRSS3_PHY_74_DATA 0x00000000 +#define DDRSS3_PHY_75_DATA 0x00000001 +#define DDRSS3_PHY_76_DATA 0x07FF0000 +#define DDRSS3_PHY_77_DATA 0x0080081F +#define DDRSS3_PHY_78_DATA 0x00081020 +#define DDRSS3_PHY_79_DATA 0x04010000 +#define DDRSS3_PHY_80_DATA 0x00000000 +#define DDRSS3_PHY_81_DATA 0x00000000 +#define DDRSS3_PHY_82_DATA 0x00000000 +#define DDRSS3_PHY_83_DATA 0x00000100 +#define DDRSS3_PHY_84_DATA 0x01CC0C01 +#define DDRSS3_PHY_85_DATA 0x1003CC0C +#define DDRSS3_PHY_86_DATA 0x20000140 +#define DDRSS3_PHY_87_DATA 0x07FF0200 +#define DDRSS3_PHY_88_DATA 0x0000DD01 +#define DDRSS3_PHY_89_DATA 0x10100303 +#define DDRSS3_PHY_90_DATA 0x10101010 +#define DDRSS3_PHY_91_DATA 0x10101010 +#define DDRSS3_PHY_92_DATA 0x00021010 +#define DDRSS3_PHY_93_DATA 0x00100010 +#define DDRSS3_PHY_94_DATA 0x00100010 +#define DDRSS3_PHY_95_DATA 0x00100010 +#define DDRSS3_PHY_96_DATA 0x00100010 +#define DDRSS3_PHY_97_DATA 0x00050010 +#define DDRSS3_PHY_98_DATA 0x51517041 +#define DDRSS3_PHY_99_DATA 0x31C06001 +#define DDRSS3_PHY_100_DATA 0x07AB01AB +#define DDRSS3_PHY_101_DATA 0x00C0C001 +#define DDRSS3_PHY_102_DATA 0x0E0D0101 +#define DDRSS3_PHY_103_DATA 0x10001000 +#define DDRSS3_PHY_104_DATA 0x0C083E42 +#define DDRSS3_PHY_105_DATA 0x0F0C3701 +#define DDRSS3_PHY_106_DATA 0x01000140 +#define DDRSS3_PHY_107_DATA 0x0C000420 +#define DDRSS3_PHY_108_DATA 0x00000198 +#define DDRSS3_PHY_109_DATA 0x0A0000D0 +#define DDRSS3_PHY_110_DATA 0x00030200 +#define DDRSS3_PHY_111_DATA 0x02800000 +#define DDRSS3_PHY_112_DATA 0x80800000 +#define DDRSS3_PHY_113_DATA 0x000E2010 +#define DDRSS3_PHY_114_DATA 0x76543210 +#define DDRSS3_PHY_115_DATA 0x00000008 +#define DDRSS3_PHY_116_DATA 0x02800280 +#define DDRSS3_PHY_117_DATA 0x02800280 +#define DDRSS3_PHY_118_DATA 0x02800280 +#define DDRSS3_PHY_119_DATA 0x02800280 +#define DDRSS3_PHY_120_DATA 0x00000280 +#define DDRSS3_PHY_121_DATA 0x0000A000 +#define DDRSS3_PHY_122_DATA 0x00A000A0 +#define DDRSS3_PHY_123_DATA 0x00A000A0 +#define DDRSS3_PHY_124_DATA 0x00A000A0 +#define DDRSS3_PHY_125_DATA 0x00A000A0 +#define DDRSS3_PHY_126_DATA 0x00A000A0 +#define DDRSS3_PHY_127_DATA 0x00A000A0 +#define DDRSS3_PHY_128_DATA 0x00A000A0 +#define DDRSS3_PHY_129_DATA 0x00A000A0 +#define DDRSS3_PHY_130_DATA 0x01C200A0 +#define DDRSS3_PHY_131_DATA 0x01A00005 +#define DDRSS3_PHY_132_DATA 0x00000000 +#define DDRSS3_PHY_133_DATA 0x00000000 +#define DDRSS3_PHY_134_DATA 0x00080200 +#define DDRSS3_PHY_135_DATA 0x00000000 +#define DDRSS3_PHY_136_DATA 0x20202000 +#define DDRSS3_PHY_137_DATA 0x20202020 +#define DDRSS3_PHY_138_DATA 0xF0F02020 +#define DDRSS3_PHY_139_DATA 0x00000000 +#define DDRSS3_PHY_140_DATA 0x00000000 +#define DDRSS3_PHY_141_DATA 0x00000000 +#define DDRSS3_PHY_142_DATA 0x00000000 +#define DDRSS3_PHY_143_DATA 0x00000000 +#define DDRSS3_PHY_144_DATA 0x00000000 +#define DDRSS3_PHY_145_DATA 0x00000000 +#define DDRSS3_PHY_146_DATA 0x00000000 +#define DDRSS3_PHY_147_DATA 0x00000000 +#define DDRSS3_PHY_148_DATA 0x00000000 +#define DDRSS3_PHY_149_DATA 0x00000000 +#define DDRSS3_PHY_150_DATA 0x00000000 +#define DDRSS3_PHY_151_DATA 0x00000000 +#define DDRSS3_PHY_152_DATA 0x00000000 +#define DDRSS3_PHY_153_DATA 0x00000000 +#define DDRSS3_PHY_154_DATA 0x00000000 +#define DDRSS3_PHY_155_DATA 0x00000000 +#define DDRSS3_PHY_156_DATA 0x00000000 +#define DDRSS3_PHY_157_DATA 0x00000000 +#define DDRSS3_PHY_158_DATA 0x00000000 +#define DDRSS3_PHY_159_DATA 0x00000000 +#define DDRSS3_PHY_160_DATA 0x00000000 +#define DDRSS3_PHY_161_DATA 0x00000000 +#define DDRSS3_PHY_162_DATA 0x00000000 +#define DDRSS3_PHY_163_DATA 0x00000000 +#define DDRSS3_PHY_164_DATA 0x00000000 +#define DDRSS3_PHY_165_DATA 0x00000000 +#define DDRSS3_PHY_166_DATA 0x00000000 +#define DDRSS3_PHY_167_DATA 0x00000000 +#define DDRSS3_PHY_168_DATA 0x00000000 +#define DDRSS3_PHY_169_DATA 0x00000000 +#define DDRSS3_PHY_170_DATA 0x00000000 +#define DDRSS3_PHY_171_DATA 0x00000000 +#define DDRSS3_PHY_172_DATA 0x00000000 +#define DDRSS3_PHY_173_DATA 0x00000000 +#define DDRSS3_PHY_174_DATA 0x00000000 +#define DDRSS3_PHY_175_DATA 0x00000000 +#define DDRSS3_PHY_176_DATA 0x00000000 +#define DDRSS3_PHY_177_DATA 0x00000000 +#define DDRSS3_PHY_178_DATA 0x00000000 +#define DDRSS3_PHY_179_DATA 0x00000000 +#define DDRSS3_PHY_180_DATA 0x00000000 +#define DDRSS3_PHY_181_DATA 0x00000000 +#define DDRSS3_PHY_182_DATA 0x00000000 +#define DDRSS3_PHY_183_DATA 0x00000000 +#define DDRSS3_PHY_184_DATA 0x00000000 +#define DDRSS3_PHY_185_DATA 0x00000000 +#define DDRSS3_PHY_186_DATA 0x00000000 +#define DDRSS3_PHY_187_DATA 0x00000000 +#define DDRSS3_PHY_188_DATA 0x00000000 +#define DDRSS3_PHY_189_DATA 0x00000000 +#define DDRSS3_PHY_190_DATA 0x00000000 +#define DDRSS3_PHY_191_DATA 0x00000000 +#define DDRSS3_PHY_192_DATA 0x00000000 +#define DDRSS3_PHY_193_DATA 0x00000000 +#define DDRSS3_PHY_194_DATA 0x00000000 +#define DDRSS3_PHY_195_DATA 0x00000000 +#define DDRSS3_PHY_196_DATA 0x00000000 +#define DDRSS3_PHY_197_DATA 0x00000000 +#define DDRSS3_PHY_198_DATA 0x00000000 +#define DDRSS3_PHY_199_DATA 0x00000000 +#define DDRSS3_PHY_200_DATA 0x00000000 +#define DDRSS3_PHY_201_DATA 0x00000000 +#define DDRSS3_PHY_202_DATA 0x00000000 +#define DDRSS3_PHY_203_DATA 0x00000000 +#define DDRSS3_PHY_204_DATA 0x00000000 +#define DDRSS3_PHY_205_DATA 0x00000000 +#define DDRSS3_PHY_206_DATA 0x00000000 +#define DDRSS3_PHY_207_DATA 0x00000000 +#define DDRSS3_PHY_208_DATA 0x00000000 +#define DDRSS3_PHY_209_DATA 0x00000000 +#define DDRSS3_PHY_210_DATA 0x00000000 +#define DDRSS3_PHY_211_DATA 0x00000000 +#define DDRSS3_PHY_212_DATA 0x00000000 +#define DDRSS3_PHY_213_DATA 0x00000000 +#define DDRSS3_PHY_214_DATA 0x00000000 +#define DDRSS3_PHY_215_DATA 0x00000000 +#define DDRSS3_PHY_216_DATA 0x00000000 +#define DDRSS3_PHY_217_DATA 0x00000000 +#define DDRSS3_PHY_218_DATA 0x00000000 +#define DDRSS3_PHY_219_DATA 0x00000000 +#define DDRSS3_PHY_220_DATA 0x00000000 +#define DDRSS3_PHY_221_DATA 0x00000000 +#define DDRSS3_PHY_222_DATA 0x00000000 +#define DDRSS3_PHY_223_DATA 0x00000000 +#define DDRSS3_PHY_224_DATA 0x00000000 +#define DDRSS3_PHY_225_DATA 0x00000000 +#define DDRSS3_PHY_226_DATA 0x00000000 +#define DDRSS3_PHY_227_DATA 0x00000000 +#define DDRSS3_PHY_228_DATA 0x00000000 +#define DDRSS3_PHY_229_DATA 0x00000000 +#define DDRSS3_PHY_230_DATA 0x00000000 +#define DDRSS3_PHY_231_DATA 0x00000000 +#define DDRSS3_PHY_232_DATA 0x00000000 +#define DDRSS3_PHY_233_DATA 0x00000000 +#define DDRSS3_PHY_234_DATA 0x00000000 +#define DDRSS3_PHY_235_DATA 0x00000000 +#define DDRSS3_PHY_236_DATA 0x00000000 +#define DDRSS3_PHY_237_DATA 0x00000000 +#define DDRSS3_PHY_238_DATA 0x00000000 +#define DDRSS3_PHY_239_DATA 0x00000000 +#define DDRSS3_PHY_240_DATA 0x00000000 +#define DDRSS3_PHY_241_DATA 0x00000000 +#define DDRSS3_PHY_242_DATA 0x00000000 +#define DDRSS3_PHY_243_DATA 0x00000000 +#define DDRSS3_PHY_244_DATA 0x00000000 +#define DDRSS3_PHY_245_DATA 0x00000000 +#define DDRSS3_PHY_246_DATA 0x00000000 +#define DDRSS3_PHY_247_DATA 0x00000000 +#define DDRSS3_PHY_248_DATA 0x00000000 +#define DDRSS3_PHY_249_DATA 0x00000000 +#define DDRSS3_PHY_250_DATA 0x00000000 +#define DDRSS3_PHY_251_DATA 0x00000000 +#define DDRSS3_PHY_252_DATA 0x00000000 +#define DDRSS3_PHY_253_DATA 0x00000000 +#define DDRSS3_PHY_254_DATA 0x00000000 +#define DDRSS3_PHY_255_DATA 0x00000000 +#define DDRSS3_PHY_256_DATA 0x000004F0 +#define DDRSS3_PHY_257_DATA 0x00000000 +#define DDRSS3_PHY_258_DATA 0x00030200 +#define DDRSS3_PHY_259_DATA 0x00000000 +#define DDRSS3_PHY_260_DATA 0x00000000 +#define DDRSS3_PHY_261_DATA 0x01030000 +#define DDRSS3_PHY_262_DATA 0x00010000 +#define DDRSS3_PHY_263_DATA 0x01030004 +#define DDRSS3_PHY_264_DATA 0x01000000 +#define DDRSS3_PHY_265_DATA 0x00000000 +#define DDRSS3_PHY_266_DATA 0x00000000 +#define DDRSS3_PHY_267_DATA 0x01000001 +#define DDRSS3_PHY_268_DATA 0x00000200 +#define DDRSS3_PHY_269_DATA 0x000800C0 +#define DDRSS3_PHY_270_DATA 0x060100CC +#define DDRSS3_PHY_271_DATA 0x00030066 +#define DDRSS3_PHY_272_DATA 0x00000000 +#define DDRSS3_PHY_273_DATA 0x00000301 +#define DDRSS3_PHY_274_DATA 0x0000AAAA +#define DDRSS3_PHY_275_DATA 0x00005555 +#define DDRSS3_PHY_276_DATA 0x0000B5B5 +#define DDRSS3_PHY_277_DATA 0x00004A4A +#define DDRSS3_PHY_278_DATA 0x00005656 +#define DDRSS3_PHY_279_DATA 0x0000A9A9 +#define DDRSS3_PHY_280_DATA 0x0000A9A9 +#define DDRSS3_PHY_281_DATA 0x0000B5B5 +#define DDRSS3_PHY_282_DATA 0x00000000 +#define DDRSS3_PHY_283_DATA 0x00000000 +#define DDRSS3_PHY_284_DATA 0x2A000000 +#define DDRSS3_PHY_285_DATA 0x00000808 +#define DDRSS3_PHY_286_DATA 0x0F000000 +#define DDRSS3_PHY_287_DATA 0x00000F08 +#define DDRSS3_PHY_288_DATA 0x10400000 +#define DDRSS3_PHY_289_DATA 0x0C002006 +#define DDRSS3_PHY_290_DATA 0x00000000 +#define DDRSS3_PHY_291_DATA 0x00000000 +#define DDRSS3_PHY_292_DATA 0x55555555 +#define DDRSS3_PHY_293_DATA 0xAAAAAAAA +#define DDRSS3_PHY_294_DATA 0x55555555 +#define DDRSS3_PHY_295_DATA 0xAAAAAAAA +#define DDRSS3_PHY_296_DATA 0x00005555 +#define DDRSS3_PHY_297_DATA 0x01000100 +#define DDRSS3_PHY_298_DATA 0x00800180 +#define DDRSS3_PHY_299_DATA 0x00000000 +#define DDRSS3_PHY_300_DATA 0x00000000 +#define DDRSS3_PHY_301_DATA 0x00000000 +#define DDRSS3_PHY_302_DATA 0x00000000 +#define DDRSS3_PHY_303_DATA 0x00000000 +#define DDRSS3_PHY_304_DATA 0x00000000 +#define DDRSS3_PHY_305_DATA 0x00000000 +#define DDRSS3_PHY_306_DATA 0x00000000 +#define DDRSS3_PHY_307_DATA 0x00000000 +#define DDRSS3_PHY_308_DATA 0x00000000 +#define DDRSS3_PHY_309_DATA 0x00000000 +#define DDRSS3_PHY_310_DATA 0x00000000 +#define DDRSS3_PHY_311_DATA 0x00000000 +#define DDRSS3_PHY_312_DATA 0x00000000 +#define DDRSS3_PHY_313_DATA 0x00000000 +#define DDRSS3_PHY_314_DATA 0x00000000 +#define DDRSS3_PHY_315_DATA 0x00000000 +#define DDRSS3_PHY_316_DATA 0x00000000 +#define DDRSS3_PHY_317_DATA 0x00000000 +#define DDRSS3_PHY_318_DATA 0x00000000 +#define DDRSS3_PHY_319_DATA 0x00000000 +#define DDRSS3_PHY_320_DATA 0x00000000 +#define DDRSS3_PHY_321_DATA 0x00000000 +#define DDRSS3_PHY_322_DATA 0x00000104 +#define DDRSS3_PHY_323_DATA 0x00000120 +#define DDRSS3_PHY_324_DATA 0x00000000 +#define DDRSS3_PHY_325_DATA 0x00000000 +#define DDRSS3_PHY_326_DATA 0x00000000 +#define DDRSS3_PHY_327_DATA 0x00000000 +#define DDRSS3_PHY_328_DATA 0x00000000 +#define DDRSS3_PHY_329_DATA 0x00000000 +#define DDRSS3_PHY_330_DATA 0x00000000 +#define DDRSS3_PHY_331_DATA 0x00000001 +#define DDRSS3_PHY_332_DATA 0x07FF0000 +#define DDRSS3_PHY_333_DATA 0x0080081F +#define DDRSS3_PHY_334_DATA 0x00081020 +#define DDRSS3_PHY_335_DATA 0x04010000 +#define DDRSS3_PHY_336_DATA 0x00000000 +#define DDRSS3_PHY_337_DATA 0x00000000 +#define DDRSS3_PHY_338_DATA 0x00000000 +#define DDRSS3_PHY_339_DATA 0x00000100 +#define DDRSS3_PHY_340_DATA 0x01CC0C01 +#define DDRSS3_PHY_341_DATA 0x1003CC0C +#define DDRSS3_PHY_342_DATA 0x20000140 +#define DDRSS3_PHY_343_DATA 0x07FF0200 +#define DDRSS3_PHY_344_DATA 0x0000DD01 +#define DDRSS3_PHY_345_DATA 0x10100303 +#define DDRSS3_PHY_346_DATA 0x10101010 +#define DDRSS3_PHY_347_DATA 0x10101010 +#define DDRSS3_PHY_348_DATA 0x00021010 +#define DDRSS3_PHY_349_DATA 0x00100010 +#define DDRSS3_PHY_350_DATA 0x00100010 +#define DDRSS3_PHY_351_DATA 0x00100010 +#define DDRSS3_PHY_352_DATA 0x00100010 +#define DDRSS3_PHY_353_DATA 0x00050010 +#define DDRSS3_PHY_354_DATA 0x51517041 +#define DDRSS3_PHY_355_DATA 0x31C06001 +#define DDRSS3_PHY_356_DATA 0x07AB01AB +#define DDRSS3_PHY_357_DATA 0x00C0C001 +#define DDRSS3_PHY_358_DATA 0x0E0D0101 +#define DDRSS3_PHY_359_DATA 0x10001000 +#define DDRSS3_PHY_360_DATA 0x0C083E42 +#define DDRSS3_PHY_361_DATA 0x0F0C3701 +#define DDRSS3_PHY_362_DATA 0x01000140 +#define DDRSS3_PHY_363_DATA 0x0C000420 +#define DDRSS3_PHY_364_DATA 0x00000198 +#define DDRSS3_PHY_365_DATA 0x0A0000D0 +#define DDRSS3_PHY_366_DATA 0x00030200 +#define DDRSS3_PHY_367_DATA 0x02800000 +#define DDRSS3_PHY_368_DATA 0x80800000 +#define DDRSS3_PHY_369_DATA 0x000E2010 +#define DDRSS3_PHY_370_DATA 0x76543210 +#define DDRSS3_PHY_371_DATA 0x00000008 +#define DDRSS3_PHY_372_DATA 0x02800280 +#define DDRSS3_PHY_373_DATA 0x02800280 +#define DDRSS3_PHY_374_DATA 0x02800280 +#define DDRSS3_PHY_375_DATA 0x02800280 +#define DDRSS3_PHY_376_DATA 0x00000280 +#define DDRSS3_PHY_377_DATA 0x0000A000 +#define DDRSS3_PHY_378_DATA 0x00A000A0 +#define DDRSS3_PHY_379_DATA 0x00A000A0 +#define DDRSS3_PHY_380_DATA 0x00A000A0 +#define DDRSS3_PHY_381_DATA 0x00A000A0 +#define DDRSS3_PHY_382_DATA 0x00A000A0 +#define DDRSS3_PHY_383_DATA 0x00A000A0 +#define DDRSS3_PHY_384_DATA 0x00A000A0 +#define DDRSS3_PHY_385_DATA 0x00A000A0 +#define DDRSS3_PHY_386_DATA 0x01C200A0 +#define DDRSS3_PHY_387_DATA 0x01A00005 +#define DDRSS3_PHY_388_DATA 0x00000000 +#define DDRSS3_PHY_389_DATA 0x00000000 +#define DDRSS3_PHY_390_DATA 0x00080200 +#define DDRSS3_PHY_391_DATA 0x00000000 +#define DDRSS3_PHY_392_DATA 0x20202000 +#define DDRSS3_PHY_393_DATA 0x20202020 +#define DDRSS3_PHY_394_DATA 0xF0F02020 +#define DDRSS3_PHY_395_DATA 0x00000000 +#define DDRSS3_PHY_396_DATA 0x00000000 +#define DDRSS3_PHY_397_DATA 0x00000000 +#define DDRSS3_PHY_398_DATA 0x00000000 +#define DDRSS3_PHY_399_DATA 0x00000000 +#define DDRSS3_PHY_400_DATA 0x00000000 +#define DDRSS3_PHY_401_DATA 0x00000000 +#define DDRSS3_PHY_402_DATA 0x00000000 +#define DDRSS3_PHY_403_DATA 0x00000000 +#define DDRSS3_PHY_404_DATA 0x00000000 +#define DDRSS3_PHY_405_DATA 0x00000000 +#define DDRSS3_PHY_406_DATA 0x00000000 +#define DDRSS3_PHY_407_DATA 0x00000000 +#define DDRSS3_PHY_408_DATA 0x00000000 +#define DDRSS3_PHY_409_DATA 0x00000000 +#define DDRSS3_PHY_410_DATA 0x00000000 +#define DDRSS3_PHY_411_DATA 0x00000000 +#define DDRSS3_PHY_412_DATA 0x00000000 +#define DDRSS3_PHY_413_DATA 0x00000000 +#define DDRSS3_PHY_414_DATA 0x00000000 +#define DDRSS3_PHY_415_DATA 0x00000000 +#define DDRSS3_PHY_416_DATA 0x00000000 +#define DDRSS3_PHY_417_DATA 0x00000000 +#define DDRSS3_PHY_418_DATA 0x00000000 +#define DDRSS3_PHY_419_DATA 0x00000000 +#define DDRSS3_PHY_420_DATA 0x00000000 +#define DDRSS3_PHY_421_DATA 0x00000000 +#define DDRSS3_PHY_422_DATA 0x00000000 +#define DDRSS3_PHY_423_DATA 0x00000000 +#define DDRSS3_PHY_424_DATA 0x00000000 +#define DDRSS3_PHY_425_DATA 0x00000000 +#define DDRSS3_PHY_426_DATA 0x00000000 +#define DDRSS3_PHY_427_DATA 0x00000000 +#define DDRSS3_PHY_428_DATA 0x00000000 +#define DDRSS3_PHY_429_DATA 0x00000000 +#define DDRSS3_PHY_430_DATA 0x00000000 +#define DDRSS3_PHY_431_DATA 0x00000000 +#define DDRSS3_PHY_432_DATA 0x00000000 +#define DDRSS3_PHY_433_DATA 0x00000000 +#define DDRSS3_PHY_434_DATA 0x00000000 +#define DDRSS3_PHY_435_DATA 0x00000000 +#define DDRSS3_PHY_436_DATA 0x00000000 +#define DDRSS3_PHY_437_DATA 0x00000000 +#define DDRSS3_PHY_438_DATA 0x00000000 +#define DDRSS3_PHY_439_DATA 0x00000000 +#define DDRSS3_PHY_440_DATA 0x00000000 +#define DDRSS3_PHY_441_DATA 0x00000000 +#define DDRSS3_PHY_442_DATA 0x00000000 +#define DDRSS3_PHY_443_DATA 0x00000000 +#define DDRSS3_PHY_444_DATA 0x00000000 +#define DDRSS3_PHY_445_DATA 0x00000000 +#define DDRSS3_PHY_446_DATA 0x00000000 +#define DDRSS3_PHY_447_DATA 0x00000000 +#define DDRSS3_PHY_448_DATA 0x00000000 +#define DDRSS3_PHY_449_DATA 0x00000000 +#define DDRSS3_PHY_450_DATA 0x00000000 +#define DDRSS3_PHY_451_DATA 0x00000000 +#define DDRSS3_PHY_452_DATA 0x00000000 +#define DDRSS3_PHY_453_DATA 0x00000000 +#define DDRSS3_PHY_454_DATA 0x00000000 +#define DDRSS3_PHY_455_DATA 0x00000000 +#define DDRSS3_PHY_456_DATA 0x00000000 +#define DDRSS3_PHY_457_DATA 0x00000000 +#define DDRSS3_PHY_458_DATA 0x00000000 +#define DDRSS3_PHY_459_DATA 0x00000000 +#define DDRSS3_PHY_460_DATA 0x00000000 +#define DDRSS3_PHY_461_DATA 0x00000000 +#define DDRSS3_PHY_462_DATA 0x00000000 +#define DDRSS3_PHY_463_DATA 0x00000000 +#define DDRSS3_PHY_464_DATA 0x00000000 +#define DDRSS3_PHY_465_DATA 0x00000000 +#define DDRSS3_PHY_466_DATA 0x00000000 +#define DDRSS3_PHY_467_DATA 0x00000000 +#define DDRSS3_PHY_468_DATA 0x00000000 +#define DDRSS3_PHY_469_DATA 0x00000000 +#define DDRSS3_PHY_470_DATA 0x00000000 +#define DDRSS3_PHY_471_DATA 0x00000000 +#define DDRSS3_PHY_472_DATA 0x00000000 +#define DDRSS3_PHY_473_DATA 0x00000000 +#define DDRSS3_PHY_474_DATA 0x00000000 +#define DDRSS3_PHY_475_DATA 0x00000000 +#define DDRSS3_PHY_476_DATA 0x00000000 +#define DDRSS3_PHY_477_DATA 0x00000000 +#define DDRSS3_PHY_478_DATA 0x00000000 +#define DDRSS3_PHY_479_DATA 0x00000000 +#define DDRSS3_PHY_480_DATA 0x00000000 +#define DDRSS3_PHY_481_DATA 0x00000000 +#define DDRSS3_PHY_482_DATA 0x00000000 +#define DDRSS3_PHY_483_DATA 0x00000000 +#define DDRSS3_PHY_484_DATA 0x00000000 +#define DDRSS3_PHY_485_DATA 0x00000000 +#define DDRSS3_PHY_486_DATA 0x00000000 +#define DDRSS3_PHY_487_DATA 0x00000000 +#define DDRSS3_PHY_488_DATA 0x00000000 +#define DDRSS3_PHY_489_DATA 0x00000000 +#define DDRSS3_PHY_490_DATA 0x00000000 +#define DDRSS3_PHY_491_DATA 0x00000000 +#define DDRSS3_PHY_492_DATA 0x00000000 +#define DDRSS3_PHY_493_DATA 0x00000000 +#define DDRSS3_PHY_494_DATA 0x00000000 +#define DDRSS3_PHY_495_DATA 0x00000000 +#define DDRSS3_PHY_496_DATA 0x00000000 +#define DDRSS3_PHY_497_DATA 0x00000000 +#define DDRSS3_PHY_498_DATA 0x00000000 +#define DDRSS3_PHY_499_DATA 0x00000000 +#define DDRSS3_PHY_500_DATA 0x00000000 +#define DDRSS3_PHY_501_DATA 0x00000000 +#define DDRSS3_PHY_502_DATA 0x00000000 +#define DDRSS3_PHY_503_DATA 0x00000000 +#define DDRSS3_PHY_504_DATA 0x00000000 +#define DDRSS3_PHY_505_DATA 0x00000000 +#define DDRSS3_PHY_506_DATA 0x00000000 +#define DDRSS3_PHY_507_DATA 0x00000000 +#define DDRSS3_PHY_508_DATA 0x00000000 +#define DDRSS3_PHY_509_DATA 0x00000000 +#define DDRSS3_PHY_510_DATA 0x00000000 +#define DDRSS3_PHY_511_DATA 0x00000000 +#define DDRSS3_PHY_512_DATA 0x000004F0 +#define DDRSS3_PHY_513_DATA 0x00000000 +#define DDRSS3_PHY_514_DATA 0x00030200 +#define DDRSS3_PHY_515_DATA 0x00000000 +#define DDRSS3_PHY_516_DATA 0x00000000 +#define DDRSS3_PHY_517_DATA 0x01030000 +#define DDRSS3_PHY_518_DATA 0x00010000 +#define DDRSS3_PHY_519_DATA 0x01030004 +#define DDRSS3_PHY_520_DATA 0x01000000 +#define DDRSS3_PHY_521_DATA 0x00000000 +#define DDRSS3_PHY_522_DATA 0x00000000 +#define DDRSS3_PHY_523_DATA 0x01000001 +#define DDRSS3_PHY_524_DATA 0x00000200 +#define DDRSS3_PHY_525_DATA 0x000800C0 +#define DDRSS3_PHY_526_DATA 0x060100CC +#define DDRSS3_PHY_527_DATA 0x00030066 +#define DDRSS3_PHY_528_DATA 0x00000000 +#define DDRSS3_PHY_529_DATA 0x00000301 +#define DDRSS3_PHY_530_DATA 0x0000AAAA +#define DDRSS3_PHY_531_DATA 0x00005555 +#define DDRSS3_PHY_532_DATA 0x0000B5B5 +#define DDRSS3_PHY_533_DATA 0x00004A4A +#define DDRSS3_PHY_534_DATA 0x00005656 +#define DDRSS3_PHY_535_DATA 0x0000A9A9 +#define DDRSS3_PHY_536_DATA 0x0000A9A9 +#define DDRSS3_PHY_537_DATA 0x0000B5B5 +#define DDRSS3_PHY_538_DATA 0x00000000 +#define DDRSS3_PHY_539_DATA 0x00000000 +#define DDRSS3_PHY_540_DATA 0x2A000000 +#define DDRSS3_PHY_541_DATA 0x00000808 +#define DDRSS3_PHY_542_DATA 0x0F000000 +#define DDRSS3_PHY_543_DATA 0x00000F08 +#define DDRSS3_PHY_544_DATA 0x10400000 +#define DDRSS3_PHY_545_DATA 0x0C002006 +#define DDRSS3_PHY_546_DATA 0x00000000 +#define DDRSS3_PHY_547_DATA 0x00000000 +#define DDRSS3_PHY_548_DATA 0x55555555 +#define DDRSS3_PHY_549_DATA 0xAAAAAAAA +#define DDRSS3_PHY_550_DATA 0x55555555 +#define DDRSS3_PHY_551_DATA 0xAAAAAAAA +#define DDRSS3_PHY_552_DATA 0x00005555 +#define DDRSS3_PHY_553_DATA 0x01000100 +#define DDRSS3_PHY_554_DATA 0x00800180 +#define DDRSS3_PHY_555_DATA 0x00000001 +#define DDRSS3_PHY_556_DATA 0x00000000 +#define DDRSS3_PHY_557_DATA 0x00000000 +#define DDRSS3_PHY_558_DATA 0x00000000 +#define DDRSS3_PHY_559_DATA 0x00000000 +#define DDRSS3_PHY_560_DATA 0x00000000 +#define DDRSS3_PHY_561_DATA 0x00000000 +#define DDRSS3_PHY_562_DATA 0x00000000 +#define DDRSS3_PHY_563_DATA 0x00000000 +#define DDRSS3_PHY_564_DATA 0x00000000 +#define DDRSS3_PHY_565_DATA 0x00000000 +#define DDRSS3_PHY_566_DATA 0x00000000 +#define DDRSS3_PHY_567_DATA 0x00000000 +#define DDRSS3_PHY_568_DATA 0x00000000 +#define DDRSS3_PHY_569_DATA 0x00000000 +#define DDRSS3_PHY_570_DATA 0x00000000 +#define DDRSS3_PHY_571_DATA 0x00000000 +#define DDRSS3_PHY_572_DATA 0x00000000 +#define DDRSS3_PHY_573_DATA 0x00000000 +#define DDRSS3_PHY_574_DATA 0x00000000 +#define DDRSS3_PHY_575_DATA 0x00000000 +#define DDRSS3_PHY_576_DATA 0x00000000 +#define DDRSS3_PHY_577_DATA 0x00000000 +#define DDRSS3_PHY_578_DATA 0x00000104 +#define DDRSS3_PHY_579_DATA 0x00000120 +#define DDRSS3_PHY_580_DATA 0x00000000 +#define DDRSS3_PHY_581_DATA 0x00000000 +#define DDRSS3_PHY_582_DATA 0x00000000 +#define DDRSS3_PHY_583_DATA 0x00000000 +#define DDRSS3_PHY_584_DATA 0x00000000 +#define DDRSS3_PHY_585_DATA 0x00000000 +#define DDRSS3_PHY_586_DATA 0x00000000 +#define DDRSS3_PHY_587_DATA 0x00000001 +#define DDRSS3_PHY_588_DATA 0x07FF0000 +#define DDRSS3_PHY_589_DATA 0x0080081F +#define DDRSS3_PHY_590_DATA 0x00081020 +#define DDRSS3_PHY_591_DATA 0x04010000 +#define DDRSS3_PHY_592_DATA 0x00000000 +#define DDRSS3_PHY_593_DATA 0x00000000 +#define DDRSS3_PHY_594_DATA 0x00000000 +#define DDRSS3_PHY_595_DATA 0x00000100 +#define DDRSS3_PHY_596_DATA 0x01CC0C01 +#define DDRSS3_PHY_597_DATA 0x1003CC0C +#define DDRSS3_PHY_598_DATA 0x20000140 +#define DDRSS3_PHY_599_DATA 0x07FF0200 +#define DDRSS3_PHY_600_DATA 0x0000DD01 +#define DDRSS3_PHY_601_DATA 0x10100303 +#define DDRSS3_PHY_602_DATA 0x10101010 +#define DDRSS3_PHY_603_DATA 0x10101010 +#define DDRSS3_PHY_604_DATA 0x00021010 +#define DDRSS3_PHY_605_DATA 0x00100010 +#define DDRSS3_PHY_606_DATA 0x00100010 +#define DDRSS3_PHY_607_DATA 0x00100010 +#define DDRSS3_PHY_608_DATA 0x00100010 +#define DDRSS3_PHY_609_DATA 0x00050010 +#define DDRSS3_PHY_610_DATA 0x51517041 +#define DDRSS3_PHY_611_DATA 0x31C06001 +#define DDRSS3_PHY_612_DATA 0x07AB01AB +#define DDRSS3_PHY_613_DATA 0x00C0C001 +#define DDRSS3_PHY_614_DATA 0x0E0D0101 +#define DDRSS3_PHY_615_DATA 0x10001000 +#define DDRSS3_PHY_616_DATA 0x0C083E42 +#define DDRSS3_PHY_617_DATA 0x0F0C3701 +#define DDRSS3_PHY_618_DATA 0x01000140 +#define DDRSS3_PHY_619_DATA 0x0C000420 +#define DDRSS3_PHY_620_DATA 0x00000198 +#define DDRSS3_PHY_621_DATA 0x0A0000D0 +#define DDRSS3_PHY_622_DATA 0x00030200 +#define DDRSS3_PHY_623_DATA 0x02800000 +#define DDRSS3_PHY_624_DATA 0x80800000 +#define DDRSS3_PHY_625_DATA 0x000E2010 +#define DDRSS3_PHY_626_DATA 0x76543210 +#define DDRSS3_PHY_627_DATA 0x00000008 +#define DDRSS3_PHY_628_DATA 0x02800280 +#define DDRSS3_PHY_629_DATA 0x02800280 +#define DDRSS3_PHY_630_DATA 0x02800280 +#define DDRSS3_PHY_631_DATA 0x02800280 +#define DDRSS3_PHY_632_DATA 0x00000280 +#define DDRSS3_PHY_633_DATA 0x0000A000 +#define DDRSS3_PHY_634_DATA 0x00A000A0 +#define DDRSS3_PHY_635_DATA 0x00A000A0 +#define DDRSS3_PHY_636_DATA 0x00A000A0 +#define DDRSS3_PHY_637_DATA 0x00A000A0 +#define DDRSS3_PHY_638_DATA 0x00A000A0 +#define DDRSS3_PHY_639_DATA 0x00A000A0 +#define DDRSS3_PHY_640_DATA 0x00A000A0 +#define DDRSS3_PHY_641_DATA 0x00A000A0 +#define DDRSS3_PHY_642_DATA 0x01C200A0 +#define DDRSS3_PHY_643_DATA 0x01A00005 +#define DDRSS3_PHY_644_DATA 0x00000000 +#define DDRSS3_PHY_645_DATA 0x00000000 +#define DDRSS3_PHY_646_DATA 0x00080200 +#define DDRSS3_PHY_647_DATA 0x00000000 +#define DDRSS3_PHY_648_DATA 0x20202000 +#define DDRSS3_PHY_649_DATA 0x20202020 +#define DDRSS3_PHY_650_DATA 0xF0F02020 +#define DDRSS3_PHY_651_DATA 0x00000000 +#define DDRSS3_PHY_652_DATA 0x00000000 +#define DDRSS3_PHY_653_DATA 0x00000000 +#define DDRSS3_PHY_654_DATA 0x00000000 +#define DDRSS3_PHY_655_DATA 0x00000000 +#define DDRSS3_PHY_656_DATA 0x00000000 +#define DDRSS3_PHY_657_DATA 0x00000000 +#define DDRSS3_PHY_658_DATA 0x00000000 +#define DDRSS3_PHY_659_DATA 0x00000000 +#define DDRSS3_PHY_660_DATA 0x00000000 +#define DDRSS3_PHY_661_DATA 0x00000000 +#define DDRSS3_PHY_662_DATA 0x00000000 +#define DDRSS3_PHY_663_DATA 0x00000000 +#define DDRSS3_PHY_664_DATA 0x00000000 +#define DDRSS3_PHY_665_DATA 0x00000000 +#define DDRSS3_PHY_666_DATA 0x00000000 +#define DDRSS3_PHY_667_DATA 0x00000000 +#define DDRSS3_PHY_668_DATA 0x00000000 +#define DDRSS3_PHY_669_DATA 0x00000000 +#define DDRSS3_PHY_670_DATA 0x00000000 +#define DDRSS3_PHY_671_DATA 0x00000000 +#define DDRSS3_PHY_672_DATA 0x00000000 +#define DDRSS3_PHY_673_DATA 0x00000000 +#define DDRSS3_PHY_674_DATA 0x00000000 +#define DDRSS3_PHY_675_DATA 0x00000000 +#define DDRSS3_PHY_676_DATA 0x00000000 +#define DDRSS3_PHY_677_DATA 0x00000000 +#define DDRSS3_PHY_678_DATA 0x00000000 +#define DDRSS3_PHY_679_DATA 0x00000000 +#define DDRSS3_PHY_680_DATA 0x00000000 +#define DDRSS3_PHY_681_DATA 0x00000000 +#define DDRSS3_PHY_682_DATA 0x00000000 +#define DDRSS3_PHY_683_DATA 0x00000000 +#define DDRSS3_PHY_684_DATA 0x00000000 +#define DDRSS3_PHY_685_DATA 0x00000000 +#define DDRSS3_PHY_686_DATA 0x00000000 +#define DDRSS3_PHY_687_DATA 0x00000000 +#define DDRSS3_PHY_688_DATA 0x00000000 +#define DDRSS3_PHY_689_DATA 0x00000000 +#define DDRSS3_PHY_690_DATA 0x00000000 +#define DDRSS3_PHY_691_DATA 0x00000000 +#define DDRSS3_PHY_692_DATA 0x00000000 +#define DDRSS3_PHY_693_DATA 0x00000000 +#define DDRSS3_PHY_694_DATA 0x00000000 +#define DDRSS3_PHY_695_DATA 0x00000000 +#define DDRSS3_PHY_696_DATA 0x00000000 +#define DDRSS3_PHY_697_DATA 0x00000000 +#define DDRSS3_PHY_698_DATA 0x00000000 +#define DDRSS3_PHY_699_DATA 0x00000000 +#define DDRSS3_PHY_700_DATA 0x00000000 +#define DDRSS3_PHY_701_DATA 0x00000000 +#define DDRSS3_PHY_702_DATA 0x00000000 +#define DDRSS3_PHY_703_DATA 0x00000000 +#define DDRSS3_PHY_704_DATA 0x00000000 +#define DDRSS3_PHY_705_DATA 0x00000000 +#define DDRSS3_PHY_706_DATA 0x00000000 +#define DDRSS3_PHY_707_DATA 0x00000000 +#define DDRSS3_PHY_708_DATA 0x00000000 +#define DDRSS3_PHY_709_DATA 0x00000000 +#define DDRSS3_PHY_710_DATA 0x00000000 +#define DDRSS3_PHY_711_DATA 0x00000000 +#define DDRSS3_PHY_712_DATA 0x00000000 +#define DDRSS3_PHY_713_DATA 0x00000000 +#define DDRSS3_PHY_714_DATA 0x00000000 +#define DDRSS3_PHY_715_DATA 0x00000000 +#define DDRSS3_PHY_716_DATA 0x00000000 +#define DDRSS3_PHY_717_DATA 0x00000000 +#define DDRSS3_PHY_718_DATA 0x00000000 +#define DDRSS3_PHY_719_DATA 0x00000000 +#define DDRSS3_PHY_720_DATA 0x00000000 +#define DDRSS3_PHY_721_DATA 0x00000000 +#define DDRSS3_PHY_722_DATA 0x00000000 +#define DDRSS3_PHY_723_DATA 0x00000000 +#define DDRSS3_PHY_724_DATA 0x00000000 +#define DDRSS3_PHY_725_DATA 0x00000000 +#define DDRSS3_PHY_726_DATA 0x00000000 +#define DDRSS3_PHY_727_DATA 0x00000000 +#define DDRSS3_PHY_728_DATA 0x00000000 +#define DDRSS3_PHY_729_DATA 0x00000000 +#define DDRSS3_PHY_730_DATA 0x00000000 +#define DDRSS3_PHY_731_DATA 0x00000000 +#define DDRSS3_PHY_732_DATA 0x00000000 +#define DDRSS3_PHY_733_DATA 0x00000000 +#define DDRSS3_PHY_734_DATA 0x00000000 +#define DDRSS3_PHY_735_DATA 0x00000000 +#define DDRSS3_PHY_736_DATA 0x00000000 +#define DDRSS3_PHY_737_DATA 0x00000000 +#define DDRSS3_PHY_738_DATA 0x00000000 +#define DDRSS3_PHY_739_DATA 0x00000000 +#define DDRSS3_PHY_740_DATA 0x00000000 +#define DDRSS3_PHY_741_DATA 0x00000000 +#define DDRSS3_PHY_742_DATA 0x00000000 +#define DDRSS3_PHY_743_DATA 0x00000000 +#define DDRSS3_PHY_744_DATA 0x00000000 +#define DDRSS3_PHY_745_DATA 0x00000000 +#define DDRSS3_PHY_746_DATA 0x00000000 +#define DDRSS3_PHY_747_DATA 0x00000000 +#define DDRSS3_PHY_748_DATA 0x00000000 +#define DDRSS3_PHY_749_DATA 0x00000000 +#define DDRSS3_PHY_750_DATA 0x00000000 +#define DDRSS3_PHY_751_DATA 0x00000000 +#define DDRSS3_PHY_752_DATA 0x00000000 +#define DDRSS3_PHY_753_DATA 0x00000000 +#define DDRSS3_PHY_754_DATA 0x00000000 +#define DDRSS3_PHY_755_DATA 0x00000000 +#define DDRSS3_PHY_756_DATA 0x00000000 +#define DDRSS3_PHY_757_DATA 0x00000000 +#define DDRSS3_PHY_758_DATA 0x00000000 +#define DDRSS3_PHY_759_DATA 0x00000000 +#define DDRSS3_PHY_760_DATA 0x00000000 +#define DDRSS3_PHY_761_DATA 0x00000000 +#define DDRSS3_PHY_762_DATA 0x00000000 +#define DDRSS3_PHY_763_DATA 0x00000000 +#define DDRSS3_PHY_764_DATA 0x00000000 +#define DDRSS3_PHY_765_DATA 0x00000000 +#define DDRSS3_PHY_766_DATA 0x00000000 +#define DDRSS3_PHY_767_DATA 0x00000000 +#define DDRSS3_PHY_768_DATA 0x000004F0 +#define DDRSS3_PHY_769_DATA 0x00000000 +#define DDRSS3_PHY_770_DATA 0x00030200 +#define DDRSS3_PHY_771_DATA 0x00000000 +#define DDRSS3_PHY_772_DATA 0x00000000 +#define DDRSS3_PHY_773_DATA 0x01030000 +#define DDRSS3_PHY_774_DATA 0x00010000 +#define DDRSS3_PHY_775_DATA 0x01030004 +#define DDRSS3_PHY_776_DATA 0x01000000 +#define DDRSS3_PHY_777_DATA 0x00000000 +#define DDRSS3_PHY_778_DATA 0x00000000 +#define DDRSS3_PHY_779_DATA 0x01000001 +#define DDRSS3_PHY_780_DATA 0x00000200 +#define DDRSS3_PHY_781_DATA 0x000800C0 +#define DDRSS3_PHY_782_DATA 0x060100CC +#define DDRSS3_PHY_783_DATA 0x00030066 +#define DDRSS3_PHY_784_DATA 0x00000000 +#define DDRSS3_PHY_785_DATA 0x00000301 +#define DDRSS3_PHY_786_DATA 0x0000AAAA +#define DDRSS3_PHY_787_DATA 0x00005555 +#define DDRSS3_PHY_788_DATA 0x0000B5B5 +#define DDRSS3_PHY_789_DATA 0x00004A4A +#define DDRSS3_PHY_790_DATA 0x00005656 +#define DDRSS3_PHY_791_DATA 0x0000A9A9 +#define DDRSS3_PHY_792_DATA 0x0000A9A9 +#define DDRSS3_PHY_793_DATA 0x0000B5B5 +#define DDRSS3_PHY_794_DATA 0x00000000 +#define DDRSS3_PHY_795_DATA 0x00000000 +#define DDRSS3_PHY_796_DATA 0x2A000000 +#define DDRSS3_PHY_797_DATA 0x00000808 +#define DDRSS3_PHY_798_DATA 0x0F000000 +#define DDRSS3_PHY_799_DATA 0x00000F08 +#define DDRSS3_PHY_800_DATA 0x10400000 +#define DDRSS3_PHY_801_DATA 0x0C002006 +#define DDRSS3_PHY_802_DATA 0x00000000 +#define DDRSS3_PHY_803_DATA 0x00000000 +#define DDRSS3_PHY_804_DATA 0x55555555 +#define DDRSS3_PHY_805_DATA 0xAAAAAAAA +#define DDRSS3_PHY_806_DATA 0x55555555 +#define DDRSS3_PHY_807_DATA 0xAAAAAAAA +#define DDRSS3_PHY_808_DATA 0x00005555 +#define DDRSS3_PHY_809_DATA 0x01000100 +#define DDRSS3_PHY_810_DATA 0x00800180 +#define DDRSS3_PHY_811_DATA 0x00000000 +#define DDRSS3_PHY_812_DATA 0x00000000 +#define DDRSS3_PHY_813_DATA 0x00000000 +#define DDRSS3_PHY_814_DATA 0x00000000 +#define DDRSS3_PHY_815_DATA 0x00000000 +#define DDRSS3_PHY_816_DATA 0x00000000 +#define DDRSS3_PHY_817_DATA 0x00000000 +#define DDRSS3_PHY_818_DATA 0x00000000 +#define DDRSS3_PHY_819_DATA 0x00000000 +#define DDRSS3_PHY_820_DATA 0x00000000 +#define DDRSS3_PHY_821_DATA 0x00000000 +#define DDRSS3_PHY_822_DATA 0x00000000 +#define DDRSS3_PHY_823_DATA 0x00000000 +#define DDRSS3_PHY_824_DATA 0x00000000 +#define DDRSS3_PHY_825_DATA 0x00000000 +#define DDRSS3_PHY_826_DATA 0x00000000 +#define DDRSS3_PHY_827_DATA 0x00000000 +#define DDRSS3_PHY_828_DATA 0x00000000 +#define DDRSS3_PHY_829_DATA 0x00000000 +#define DDRSS3_PHY_830_DATA 0x00000000 +#define DDRSS3_PHY_831_DATA 0x00000000 +#define DDRSS3_PHY_832_DATA 0x00000000 +#define DDRSS3_PHY_833_DATA 0x00000000 +#define DDRSS3_PHY_834_DATA 0x00000104 +#define DDRSS3_PHY_835_DATA 0x00000120 +#define DDRSS3_PHY_836_DATA 0x00000000 +#define DDRSS3_PHY_837_DATA 0x00000000 +#define DDRSS3_PHY_838_DATA 0x00000000 +#define DDRSS3_PHY_839_DATA 0x00000000 +#define DDRSS3_PHY_840_DATA 0x00000000 +#define DDRSS3_PHY_841_DATA 0x00000000 +#define DDRSS3_PHY_842_DATA 0x00000000 +#define DDRSS3_PHY_843_DATA 0x00000001 +#define DDRSS3_PHY_844_DATA 0x07FF0000 +#define DDRSS3_PHY_845_DATA 0x0080081F +#define DDRSS3_PHY_846_DATA 0x00081020 +#define DDRSS3_PHY_847_DATA 0x04010000 +#define DDRSS3_PHY_848_DATA 0x00000000 +#define DDRSS3_PHY_849_DATA 0x00000000 +#define DDRSS3_PHY_850_DATA 0x00000000 +#define DDRSS3_PHY_851_DATA 0x00000100 +#define DDRSS3_PHY_852_DATA 0x01CC0C01 +#define DDRSS3_PHY_853_DATA 0x1003CC0C +#define DDRSS3_PHY_854_DATA 0x20000140 +#define DDRSS3_PHY_855_DATA 0x07FF0200 +#define DDRSS3_PHY_856_DATA 0x0000DD01 +#define DDRSS3_PHY_857_DATA 0x10100303 +#define DDRSS3_PHY_858_DATA 0x10101010 +#define DDRSS3_PHY_859_DATA 0x10101010 +#define DDRSS3_PHY_860_DATA 0x00021010 +#define DDRSS3_PHY_861_DATA 0x00100010 +#define DDRSS3_PHY_862_DATA 0x00100010 +#define DDRSS3_PHY_863_DATA 0x00100010 +#define DDRSS3_PHY_864_DATA 0x00100010 +#define DDRSS3_PHY_865_DATA 0x00050010 +#define DDRSS3_PHY_866_DATA 0x51517041 +#define DDRSS3_PHY_867_DATA 0x31C06001 +#define DDRSS3_PHY_868_DATA 0x07AB01AB +#define DDRSS3_PHY_869_DATA 0x00C0C001 +#define DDRSS3_PHY_870_DATA 0x0E0D0101 +#define DDRSS3_PHY_871_DATA 0x10001000 +#define DDRSS3_PHY_872_DATA 0x0C083E42 +#define DDRSS3_PHY_873_DATA 0x0F0C3701 +#define DDRSS3_PHY_874_DATA 0x01000140 +#define DDRSS3_PHY_875_DATA 0x0C000420 +#define DDRSS3_PHY_876_DATA 0x00000198 +#define DDRSS3_PHY_877_DATA 0x0A0000D0 +#define DDRSS3_PHY_878_DATA 0x00030200 +#define DDRSS3_PHY_879_DATA 0x02800000 +#define DDRSS3_PHY_880_DATA 0x80800000 +#define DDRSS3_PHY_881_DATA 0x000E2010 +#define DDRSS3_PHY_882_DATA 0x76543210 +#define DDRSS3_PHY_883_DATA 0x00000008 +#define DDRSS3_PHY_884_DATA 0x02800280 +#define DDRSS3_PHY_885_DATA 0x02800280 +#define DDRSS3_PHY_886_DATA 0x02800280 +#define DDRSS3_PHY_887_DATA 0x02800280 +#define DDRSS3_PHY_888_DATA 0x00000280 +#define DDRSS3_PHY_889_DATA 0x0000A000 +#define DDRSS3_PHY_890_DATA 0x00A000A0 +#define DDRSS3_PHY_891_DATA 0x00A000A0 +#define DDRSS3_PHY_892_DATA 0x00A000A0 +#define DDRSS3_PHY_893_DATA 0x00A000A0 +#define DDRSS3_PHY_894_DATA 0x00A000A0 +#define DDRSS3_PHY_895_DATA 0x00A000A0 +#define DDRSS3_PHY_896_DATA 0x00A000A0 +#define DDRSS3_PHY_897_DATA 0x00A000A0 +#define DDRSS3_PHY_898_DATA 0x01C200A0 +#define DDRSS3_PHY_899_DATA 0x01A00005 +#define DDRSS3_PHY_900_DATA 0x00000000 +#define DDRSS3_PHY_901_DATA 0x00000000 +#define DDRSS3_PHY_902_DATA 0x00080200 +#define DDRSS3_PHY_903_DATA 0x00000000 +#define DDRSS3_PHY_904_DATA 0x20202000 +#define DDRSS3_PHY_905_DATA 0x20202020 +#define DDRSS3_PHY_906_DATA 0xF0F02020 +#define DDRSS3_PHY_907_DATA 0x00000000 +#define DDRSS3_PHY_908_DATA 0x00000000 +#define DDRSS3_PHY_909_DATA 0x00000000 +#define DDRSS3_PHY_910_DATA 0x00000000 +#define DDRSS3_PHY_911_DATA 0x00000000 +#define DDRSS3_PHY_912_DATA 0x00000000 +#define DDRSS3_PHY_913_DATA 0x00000000 +#define DDRSS3_PHY_914_DATA 0x00000000 +#define DDRSS3_PHY_915_DATA 0x00000000 +#define DDRSS3_PHY_916_DATA 0x00000000 +#define DDRSS3_PHY_917_DATA 0x00000000 +#define DDRSS3_PHY_918_DATA 0x00000000 +#define DDRSS3_PHY_919_DATA 0x00000000 +#define DDRSS3_PHY_920_DATA 0x00000000 +#define DDRSS3_PHY_921_DATA 0x00000000 +#define DDRSS3_PHY_922_DATA 0x00000000 +#define DDRSS3_PHY_923_DATA 0x00000000 +#define DDRSS3_PHY_924_DATA 0x00000000 +#define DDRSS3_PHY_925_DATA 0x00000000 +#define DDRSS3_PHY_926_DATA 0x00000000 +#define DDRSS3_PHY_927_DATA 0x00000000 +#define DDRSS3_PHY_928_DATA 0x00000000 +#define DDRSS3_PHY_929_DATA 0x00000000 +#define DDRSS3_PHY_930_DATA 0x00000000 +#define DDRSS3_PHY_931_DATA 0x00000000 +#define DDRSS3_PHY_932_DATA 0x00000000 +#define DDRSS3_PHY_933_DATA 0x00000000 +#define DDRSS3_PHY_934_DATA 0x00000000 +#define DDRSS3_PHY_935_DATA 0x00000000 +#define DDRSS3_PHY_936_DATA 0x00000000 +#define DDRSS3_PHY_937_DATA 0x00000000 +#define DDRSS3_PHY_938_DATA 0x00000000 +#define DDRSS3_PHY_939_DATA 0x00000000 +#define DDRSS3_PHY_940_DATA 0x00000000 +#define DDRSS3_PHY_941_DATA 0x00000000 +#define DDRSS3_PHY_942_DATA 0x00000000 +#define DDRSS3_PHY_943_DATA 0x00000000 +#define DDRSS3_PHY_944_DATA 0x00000000 +#define DDRSS3_PHY_945_DATA 0x00000000 +#define DDRSS3_PHY_946_DATA 0x00000000 +#define DDRSS3_PHY_947_DATA 0x00000000 +#define DDRSS3_PHY_948_DATA 0x00000000 +#define DDRSS3_PHY_949_DATA 0x00000000 +#define DDRSS3_PHY_950_DATA 0x00000000 +#define DDRSS3_PHY_951_DATA 0x00000000 +#define DDRSS3_PHY_952_DATA 0x00000000 +#define DDRSS3_PHY_953_DATA 0x00000000 +#define DDRSS3_PHY_954_DATA 0x00000000 +#define DDRSS3_PHY_955_DATA 0x00000000 +#define DDRSS3_PHY_956_DATA 0x00000000 +#define DDRSS3_PHY_957_DATA 0x00000000 +#define DDRSS3_PHY_958_DATA 0x00000000 +#define DDRSS3_PHY_959_DATA 0x00000000 +#define DDRSS3_PHY_960_DATA 0x00000000 +#define DDRSS3_PHY_961_DATA 0x00000000 +#define DDRSS3_PHY_962_DATA 0x00000000 +#define DDRSS3_PHY_963_DATA 0x00000000 +#define DDRSS3_PHY_964_DATA 0x00000000 +#define DDRSS3_PHY_965_DATA 0x00000000 +#define DDRSS3_PHY_966_DATA 0x00000000 +#define DDRSS3_PHY_967_DATA 0x00000000 +#define DDRSS3_PHY_968_DATA 0x00000000 +#define DDRSS3_PHY_969_DATA 0x00000000 +#define DDRSS3_PHY_970_DATA 0x00000000 +#define DDRSS3_PHY_971_DATA 0x00000000 +#define DDRSS3_PHY_972_DATA 0x00000000 +#define DDRSS3_PHY_973_DATA 0x00000000 +#define DDRSS3_PHY_974_DATA 0x00000000 +#define DDRSS3_PHY_975_DATA 0x00000000 +#define DDRSS3_PHY_976_DATA 0x00000000 +#define DDRSS3_PHY_977_DATA 0x00000000 +#define DDRSS3_PHY_978_DATA 0x00000000 +#define DDRSS3_PHY_979_DATA 0x00000000 +#define DDRSS3_PHY_980_DATA 0x00000000 +#define DDRSS3_PHY_981_DATA 0x00000000 +#define DDRSS3_PHY_982_DATA 0x00000000 +#define DDRSS3_PHY_983_DATA 0x00000000 +#define DDRSS3_PHY_984_DATA 0x00000000 +#define DDRSS3_PHY_985_DATA 0x00000000 +#define DDRSS3_PHY_986_DATA 0x00000000 +#define DDRSS3_PHY_987_DATA 0x00000000 +#define DDRSS3_PHY_988_DATA 0x00000000 +#define DDRSS3_PHY_989_DATA 0x00000000 +#define DDRSS3_PHY_990_DATA 0x00000000 +#define DDRSS3_PHY_991_DATA 0x00000000 +#define DDRSS3_PHY_992_DATA 0x00000000 +#define DDRSS3_PHY_993_DATA 0x00000000 +#define DDRSS3_PHY_994_DATA 0x00000000 +#define DDRSS3_PHY_995_DATA 0x00000000 +#define DDRSS3_PHY_996_DATA 0x00000000 +#define DDRSS3_PHY_997_DATA 0x00000000 +#define DDRSS3_PHY_998_DATA 0x00000000 +#define DDRSS3_PHY_999_DATA 0x00000000 +#define DDRSS3_PHY_1000_DATA 0x00000000 +#define DDRSS3_PHY_1001_DATA 0x00000000 +#define DDRSS3_PHY_1002_DATA 0x00000000 +#define DDRSS3_PHY_1003_DATA 0x00000000 +#define DDRSS3_PHY_1004_DATA 0x00000000 +#define DDRSS3_PHY_1005_DATA 0x00000000 +#define DDRSS3_PHY_1006_DATA 0x00000000 +#define DDRSS3_PHY_1007_DATA 0x00000000 +#define DDRSS3_PHY_1008_DATA 0x00000000 +#define DDRSS3_PHY_1009_DATA 0x00000000 +#define DDRSS3_PHY_1010_DATA 0x00000000 +#define DDRSS3_PHY_1011_DATA 0x00000000 +#define DDRSS3_PHY_1012_DATA 0x00000000 +#define DDRSS3_PHY_1013_DATA 0x00000000 +#define DDRSS3_PHY_1014_DATA 0x00000000 +#define DDRSS3_PHY_1015_DATA 0x00000000 +#define DDRSS3_PHY_1016_DATA 0x00000000 +#define DDRSS3_PHY_1017_DATA 0x00000000 +#define DDRSS3_PHY_1018_DATA 0x00000000 +#define DDRSS3_PHY_1019_DATA 0x00000000 +#define DDRSS3_PHY_1020_DATA 0x00000000 +#define DDRSS3_PHY_1021_DATA 0x00000000 +#define DDRSS3_PHY_1022_DATA 0x00000000 +#define DDRSS3_PHY_1023_DATA 0x00000000 +#define DDRSS3_PHY_1024_DATA 0x00000000 +#define DDRSS3_PHY_1025_DATA 0x00000000 +#define DDRSS3_PHY_1026_DATA 0x00000000 +#define DDRSS3_PHY_1027_DATA 0x00000000 +#define DDRSS3_PHY_1028_DATA 0x00000000 +#define DDRSS3_PHY_1029_DATA 0x00000100 +#define DDRSS3_PHY_1030_DATA 0x00000200 +#define DDRSS3_PHY_1031_DATA 0x00000000 +#define DDRSS3_PHY_1032_DATA 0x00000000 +#define DDRSS3_PHY_1033_DATA 0x00000000 +#define DDRSS3_PHY_1034_DATA 0x00000000 +#define DDRSS3_PHY_1035_DATA 0x00400000 +#define DDRSS3_PHY_1036_DATA 0x00000080 +#define DDRSS3_PHY_1037_DATA 0x00DCBA98 +#define DDRSS3_PHY_1038_DATA 0x03000000 +#define DDRSS3_PHY_1039_DATA 0x00200000 +#define DDRSS3_PHY_1040_DATA 0x00000000 +#define DDRSS3_PHY_1041_DATA 0x00000000 +#define DDRSS3_PHY_1042_DATA 0x00000000 +#define DDRSS3_PHY_1043_DATA 0x00000000 +#define DDRSS3_PHY_1044_DATA 0x00000000 +#define DDRSS3_PHY_1045_DATA 0x0000002A +#define DDRSS3_PHY_1046_DATA 0x00000015 +#define DDRSS3_PHY_1047_DATA 0x00000015 +#define DDRSS3_PHY_1048_DATA 0x0000002A +#define DDRSS3_PHY_1049_DATA 0x00000033 +#define DDRSS3_PHY_1050_DATA 0x0000000C +#define DDRSS3_PHY_1051_DATA 0x0000000C +#define DDRSS3_PHY_1052_DATA 0x00000033 +#define DDRSS3_PHY_1053_DATA 0x00543210 +#define DDRSS3_PHY_1054_DATA 0x003F0000 +#define DDRSS3_PHY_1055_DATA 0x000F3F3F +#define DDRSS3_PHY_1056_DATA 0x20202003 +#define DDRSS3_PHY_1057_DATA 0x00202020 +#define DDRSS3_PHY_1058_DATA 0x20008008 +#define DDRSS3_PHY_1059_DATA 0x00000810 +#define DDRSS3_PHY_1060_DATA 0x00000F00 +#define DDRSS3_PHY_1061_DATA 0x00000000 +#define DDRSS3_PHY_1062_DATA 0x00000000 +#define DDRSS3_PHY_1063_DATA 0x00000000 +#define DDRSS3_PHY_1064_DATA 0x000305CC +#define DDRSS3_PHY_1065_DATA 0x00030000 +#define DDRSS3_PHY_1066_DATA 0x00000300 +#define DDRSS3_PHY_1067_DATA 0x00000300 +#define DDRSS3_PHY_1068_DATA 0x00000300 +#define DDRSS3_PHY_1069_DATA 0x00000300 +#define DDRSS3_PHY_1070_DATA 0x00000300 +#define DDRSS3_PHY_1071_DATA 0x42080010 +#define DDRSS3_PHY_1072_DATA 0x0000803E +#define DDRSS3_PHY_1073_DATA 0x00000001 +#define DDRSS3_PHY_1074_DATA 0x01000102 +#define DDRSS3_PHY_1075_DATA 0x00008000 +#define DDRSS3_PHY_1076_DATA 0x00000000 +#define DDRSS3_PHY_1077_DATA 0x00000000 +#define DDRSS3_PHY_1078_DATA 0x00000000 +#define DDRSS3_PHY_1079_DATA 0x00000000 +#define DDRSS3_PHY_1080_DATA 0x00000000 +#define DDRSS3_PHY_1081_DATA 0x00000000 +#define DDRSS3_PHY_1082_DATA 0x00000000 +#define DDRSS3_PHY_1083_DATA 0x00000000 +#define DDRSS3_PHY_1084_DATA 0x00000000 +#define DDRSS3_PHY_1085_DATA 0x00000000 +#define DDRSS3_PHY_1086_DATA 0x00000000 +#define DDRSS3_PHY_1087_DATA 0x00000000 +#define DDRSS3_PHY_1088_DATA 0x00000000 +#define DDRSS3_PHY_1089_DATA 0x00000000 +#define DDRSS3_PHY_1090_DATA 0x00000000 +#define DDRSS3_PHY_1091_DATA 0x00000000 +#define DDRSS3_PHY_1092_DATA 0x00000000 +#define DDRSS3_PHY_1093_DATA 0x00000000 +#define DDRSS3_PHY_1094_DATA 0x00000000 +#define DDRSS3_PHY_1095_DATA 0x00000000 +#define DDRSS3_PHY_1096_DATA 0x00000000 +#define DDRSS3_PHY_1097_DATA 0x00000000 +#define DDRSS3_PHY_1098_DATA 0x00000000 +#define DDRSS3_PHY_1099_DATA 0x00000000 +#define DDRSS3_PHY_1100_DATA 0x00000000 +#define DDRSS3_PHY_1101_DATA 0x00000000 +#define DDRSS3_PHY_1102_DATA 0x00000000 +#define DDRSS3_PHY_1103_DATA 0x00000000 +#define DDRSS3_PHY_1104_DATA 0x00000000 +#define DDRSS3_PHY_1105_DATA 0x00000000 +#define DDRSS3_PHY_1106_DATA 0x00000000 +#define DDRSS3_PHY_1107_DATA 0x00000000 +#define DDRSS3_PHY_1108_DATA 0x00000000 +#define DDRSS3_PHY_1109_DATA 0x00000000 +#define DDRSS3_PHY_1110_DATA 0x00000000 +#define DDRSS3_PHY_1111_DATA 0x00000000 +#define DDRSS3_PHY_1112_DATA 0x00000000 +#define DDRSS3_PHY_1113_DATA 0x00000000 +#define DDRSS3_PHY_1114_DATA 0x00000000 +#define DDRSS3_PHY_1115_DATA 0x00000000 +#define DDRSS3_PHY_1116_DATA 0x00000000 +#define DDRSS3_PHY_1117_DATA 0x00000000 +#define DDRSS3_PHY_1118_DATA 0x00000000 +#define DDRSS3_PHY_1119_DATA 0x00000000 +#define DDRSS3_PHY_1120_DATA 0x00000000 +#define DDRSS3_PHY_1121_DATA 0x00000000 +#define DDRSS3_PHY_1122_DATA 0x00000000 +#define DDRSS3_PHY_1123_DATA 0x00000000 +#define DDRSS3_PHY_1124_DATA 0x00000000 +#define DDRSS3_PHY_1125_DATA 0x00000000 +#define DDRSS3_PHY_1126_DATA 0x00000000 +#define DDRSS3_PHY_1127_DATA 0x00000000 +#define DDRSS3_PHY_1128_DATA 0x00000000 +#define DDRSS3_PHY_1129_DATA 0x00000000 +#define DDRSS3_PHY_1130_DATA 0x00000000 +#define DDRSS3_PHY_1131_DATA 0x00000000 +#define DDRSS3_PHY_1132_DATA 0x00000000 +#define DDRSS3_PHY_1133_DATA 0x00000000 +#define DDRSS3_PHY_1134_DATA 0x00000000 +#define DDRSS3_PHY_1135_DATA 0x00000000 +#define DDRSS3_PHY_1136_DATA 0x00000000 +#define DDRSS3_PHY_1137_DATA 0x00000000 +#define DDRSS3_PHY_1138_DATA 0x00000000 +#define DDRSS3_PHY_1139_DATA 0x00000000 +#define DDRSS3_PHY_1140_DATA 0x00000000 +#define DDRSS3_PHY_1141_DATA 0x00000000 +#define DDRSS3_PHY_1142_DATA 0x00000000 +#define DDRSS3_PHY_1143_DATA 0x00000000 +#define DDRSS3_PHY_1144_DATA 0x00000000 +#define DDRSS3_PHY_1145_DATA 0x00000000 +#define DDRSS3_PHY_1146_DATA 0x00000000 +#define DDRSS3_PHY_1147_DATA 0x00000000 +#define DDRSS3_PHY_1148_DATA 0x00000000 +#define DDRSS3_PHY_1149_DATA 0x00000000 +#define DDRSS3_PHY_1150_DATA 0x00000000 +#define DDRSS3_PHY_1151_DATA 0x00000000 +#define DDRSS3_PHY_1152_DATA 0x00000000 +#define DDRSS3_PHY_1153_DATA 0x00000000 +#define DDRSS3_PHY_1154_DATA 0x00000000 +#define DDRSS3_PHY_1155_DATA 0x00000000 +#define DDRSS3_PHY_1156_DATA 0x00000000 +#define DDRSS3_PHY_1157_DATA 0x00000000 +#define DDRSS3_PHY_1158_DATA 0x00000000 +#define DDRSS3_PHY_1159_DATA 0x00000000 +#define DDRSS3_PHY_1160_DATA 0x00000000 +#define DDRSS3_PHY_1161_DATA 0x00000000 +#define DDRSS3_PHY_1162_DATA 0x00000000 +#define DDRSS3_PHY_1163_DATA 0x00000000 +#define DDRSS3_PHY_1164_DATA 0x00000000 +#define DDRSS3_PHY_1165_DATA 0x00000000 +#define DDRSS3_PHY_1166_DATA 0x00000000 +#define DDRSS3_PHY_1167_DATA 0x00000000 +#define DDRSS3_PHY_1168_DATA 0x00000000 +#define DDRSS3_PHY_1169_DATA 0x00000000 +#define DDRSS3_PHY_1170_DATA 0x00000000 +#define DDRSS3_PHY_1171_DATA 0x00000000 +#define DDRSS3_PHY_1172_DATA 0x00000000 +#define DDRSS3_PHY_1173_DATA 0x00000000 +#define DDRSS3_PHY_1174_DATA 0x00000000 +#define DDRSS3_PHY_1175_DATA 0x00000000 +#define DDRSS3_PHY_1176_DATA 0x00000000 +#define DDRSS3_PHY_1177_DATA 0x00000000 +#define DDRSS3_PHY_1178_DATA 0x00000000 +#define DDRSS3_PHY_1179_DATA 0x00000000 +#define DDRSS3_PHY_1180_DATA 0x00000000 +#define DDRSS3_PHY_1181_DATA 0x00000000 +#define DDRSS3_PHY_1182_DATA 0x00000000 +#define DDRSS3_PHY_1183_DATA 0x00000000 +#define DDRSS3_PHY_1184_DATA 0x00000000 +#define DDRSS3_PHY_1185_DATA 0x00000000 +#define DDRSS3_PHY_1186_DATA 0x00000000 +#define DDRSS3_PHY_1187_DATA 0x00000000 +#define DDRSS3_PHY_1188_DATA 0x00000000 +#define DDRSS3_PHY_1189_DATA 0x00000000 +#define DDRSS3_PHY_1190_DATA 0x00000000 +#define DDRSS3_PHY_1191_DATA 0x00000000 +#define DDRSS3_PHY_1192_DATA 0x00000000 +#define DDRSS3_PHY_1193_DATA 0x00000000 +#define DDRSS3_PHY_1194_DATA 0x00000000 +#define DDRSS3_PHY_1195_DATA 0x00000000 +#define DDRSS3_PHY_1196_DATA 0x00000000 +#define DDRSS3_PHY_1197_DATA 0x00000000 +#define DDRSS3_PHY_1198_DATA 0x00000000 +#define DDRSS3_PHY_1199_DATA 0x00000000 +#define DDRSS3_PHY_1200_DATA 0x00000000 +#define DDRSS3_PHY_1201_DATA 0x00000000 +#define DDRSS3_PHY_1202_DATA 0x00000000 +#define DDRSS3_PHY_1203_DATA 0x00000000 +#define DDRSS3_PHY_1204_DATA 0x00000000 +#define DDRSS3_PHY_1205_DATA 0x00000000 +#define DDRSS3_PHY_1206_DATA 0x00000000 +#define DDRSS3_PHY_1207_DATA 0x00000000 +#define DDRSS3_PHY_1208_DATA 0x00000000 +#define DDRSS3_PHY_1209_DATA 0x00000000 +#define DDRSS3_PHY_1210_DATA 0x00000000 +#define DDRSS3_PHY_1211_DATA 0x00000000 +#define DDRSS3_PHY_1212_DATA 0x00000000 +#define DDRSS3_PHY_1213_DATA 0x00000000 +#define DDRSS3_PHY_1214_DATA 0x00000000 +#define DDRSS3_PHY_1215_DATA 0x00000000 +#define DDRSS3_PHY_1216_DATA 0x00000000 +#define DDRSS3_PHY_1217_DATA 0x00000000 +#define DDRSS3_PHY_1218_DATA 0x00000000 +#define DDRSS3_PHY_1219_DATA 0x00000000 +#define DDRSS3_PHY_1220_DATA 0x00000000 +#define DDRSS3_PHY_1221_DATA 0x00000000 +#define DDRSS3_PHY_1222_DATA 0x00000000 +#define DDRSS3_PHY_1223_DATA 0x00000000 +#define DDRSS3_PHY_1224_DATA 0x00000000 +#define DDRSS3_PHY_1225_DATA 0x00000000 +#define DDRSS3_PHY_1226_DATA 0x00000000 +#define DDRSS3_PHY_1227_DATA 0x00000000 +#define DDRSS3_PHY_1228_DATA 0x00000000 +#define DDRSS3_PHY_1229_DATA 0x00000000 +#define DDRSS3_PHY_1230_DATA 0x00000000 +#define DDRSS3_PHY_1231_DATA 0x00000000 +#define DDRSS3_PHY_1232_DATA 0x00000000 +#define DDRSS3_PHY_1233_DATA 0x00000000 +#define DDRSS3_PHY_1234_DATA 0x00000000 +#define DDRSS3_PHY_1235_DATA 0x00000000 +#define DDRSS3_PHY_1236_DATA 0x00000000 +#define DDRSS3_PHY_1237_DATA 0x00000000 +#define DDRSS3_PHY_1238_DATA 0x00000000 +#define DDRSS3_PHY_1239_DATA 0x00000000 +#define DDRSS3_PHY_1240_DATA 0x00000000 +#define DDRSS3_PHY_1241_DATA 0x00000000 +#define DDRSS3_PHY_1242_DATA 0x00000000 +#define DDRSS3_PHY_1243_DATA 0x00000000 +#define DDRSS3_PHY_1244_DATA 0x00000000 +#define DDRSS3_PHY_1245_DATA 0x00000000 +#define DDRSS3_PHY_1246_DATA 0x00000000 +#define DDRSS3_PHY_1247_DATA 0x00000000 +#define DDRSS3_PHY_1248_DATA 0x00000000 +#define DDRSS3_PHY_1249_DATA 0x00000000 +#define DDRSS3_PHY_1250_DATA 0x00000000 +#define DDRSS3_PHY_1251_DATA 0x00000000 +#define DDRSS3_PHY_1252_DATA 0x00000000 +#define DDRSS3_PHY_1253_DATA 0x00000000 +#define DDRSS3_PHY_1254_DATA 0x00000000 +#define DDRSS3_PHY_1255_DATA 0x00000000 +#define DDRSS3_PHY_1256_DATA 0x00000000 +#define DDRSS3_PHY_1257_DATA 0x00000000 +#define DDRSS3_PHY_1258_DATA 0x00000000 +#define DDRSS3_PHY_1259_DATA 0x00000000 +#define DDRSS3_PHY_1260_DATA 0x00000000 +#define DDRSS3_PHY_1261_DATA 0x00000000 +#define DDRSS3_PHY_1262_DATA 0x00000000 +#define DDRSS3_PHY_1263_DATA 0x00000000 +#define DDRSS3_PHY_1264_DATA 0x00000000 +#define DDRSS3_PHY_1265_DATA 0x00000000 +#define DDRSS3_PHY_1266_DATA 0x00000000 +#define DDRSS3_PHY_1267_DATA 0x00000000 +#define DDRSS3_PHY_1268_DATA 0x00000000 +#define DDRSS3_PHY_1269_DATA 0x00000000 +#define DDRSS3_PHY_1270_DATA 0x00000000 +#define DDRSS3_PHY_1271_DATA 0x00000000 +#define DDRSS3_PHY_1272_DATA 0x00000000 +#define DDRSS3_PHY_1273_DATA 0x00000000 +#define DDRSS3_PHY_1274_DATA 0x00000000 +#define DDRSS3_PHY_1275_DATA 0x00000000 +#define DDRSS3_PHY_1276_DATA 0x00000000 +#define DDRSS3_PHY_1277_DATA 0x00000000 +#define DDRSS3_PHY_1278_DATA 0x00000000 +#define DDRSS3_PHY_1279_DATA 0x00000000 +#define DDRSS3_PHY_1280_DATA 0x00000000 +#define DDRSS3_PHY_1281_DATA 0x00010100 +#define DDRSS3_PHY_1282_DATA 0x00000000 +#define DDRSS3_PHY_1283_DATA 0x00000000 +#define DDRSS3_PHY_1284_DATA 0x00050000 +#define DDRSS3_PHY_1285_DATA 0x04000000 +#define DDRSS3_PHY_1286_DATA 0x00000055 +#define DDRSS3_PHY_1287_DATA 0x00000000 +#define DDRSS3_PHY_1288_DATA 0x00000000 +#define DDRSS3_PHY_1289_DATA 0x00000000 +#define DDRSS3_PHY_1290_DATA 0x00000000 +#define DDRSS3_PHY_1291_DATA 0x00002001 +#define DDRSS3_PHY_1292_DATA 0x0000400F +#define DDRSS3_PHY_1293_DATA 0x50020028 +#define DDRSS3_PHY_1294_DATA 0x01010000 +#define DDRSS3_PHY_1295_DATA 0x80080001 +#define DDRSS3_PHY_1296_DATA 0x10200000 +#define DDRSS3_PHY_1297_DATA 0x00000008 +#define DDRSS3_PHY_1298_DATA 0x00000000 +#define DDRSS3_PHY_1299_DATA 0x01090E00 +#define DDRSS3_PHY_1300_DATA 0x00040101 +#define DDRSS3_PHY_1301_DATA 0x0000010F +#define DDRSS3_PHY_1302_DATA 0x00000000 +#define DDRSS3_PHY_1303_DATA 0x00000064 +#define DDRSS3_PHY_1304_DATA 0x00000000 +#define DDRSS3_PHY_1305_DATA 0x01010000 +#define DDRSS3_PHY_1306_DATA 0x01080402 +#define DDRSS3_PHY_1307_DATA 0x01200F02 +#define DDRSS3_PHY_1308_DATA 0x00194280 +#define DDRSS3_PHY_1309_DATA 0x00000004 +#define DDRSS3_PHY_1310_DATA 0x00042000 +#define DDRSS3_PHY_1311_DATA 0x00000000 +#define DDRSS3_PHY_1312_DATA 0x00000000 +#define DDRSS3_PHY_1313_DATA 0x00000000 +#define DDRSS3_PHY_1314_DATA 0x00000000 +#define DDRSS3_PHY_1315_DATA 0x00000000 +#define DDRSS3_PHY_1316_DATA 0x00000000 +#define DDRSS3_PHY_1317_DATA 0x01000000 +#define DDRSS3_PHY_1318_DATA 0x00000705 +#define DDRSS3_PHY_1319_DATA 0x00000054 +#define DDRSS3_PHY_1320_DATA 0x00030820 +#define DDRSS3_PHY_1321_DATA 0x00010820 +#define DDRSS3_PHY_1322_DATA 0x00010820 +#define DDRSS3_PHY_1323_DATA 0x00010820 +#define DDRSS3_PHY_1324_DATA 0x00010820 +#define DDRSS3_PHY_1325_DATA 0x00010820 +#define DDRSS3_PHY_1326_DATA 0x00010820 +#define DDRSS3_PHY_1327_DATA 0x00010820 +#define DDRSS3_PHY_1328_DATA 0x00010820 +#define DDRSS3_PHY_1329_DATA 0x00000000 +#define DDRSS3_PHY_1330_DATA 0x00000074 +#define DDRSS3_PHY_1331_DATA 0x00000400 +#define DDRSS3_PHY_1332_DATA 0x00000108 +#define DDRSS3_PHY_1333_DATA 0x00000000 +#define DDRSS3_PHY_1334_DATA 0x00000000 +#define DDRSS3_PHY_1335_DATA 0x00000000 +#define DDRSS3_PHY_1336_DATA 0x00000000 +#define DDRSS3_PHY_1337_DATA 0x00000000 +#define DDRSS3_PHY_1338_DATA 0x03000000 +#define DDRSS3_PHY_1339_DATA 0x00000000 +#define DDRSS3_PHY_1340_DATA 0x00000000 +#define DDRSS3_PHY_1341_DATA 0x00000000 +#define DDRSS3_PHY_1342_DATA 0x04102006 +#define DDRSS3_PHY_1343_DATA 0x00041020 +#define DDRSS3_PHY_1344_DATA 0x01C98C98 +#define DDRSS3_PHY_1345_DATA 0x3F400000 +#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS3_PHY_1347_DATA 0x0000001F +#define DDRSS3_PHY_1348_DATA 0x00000000 +#define DDRSS3_PHY_1349_DATA 0x00000000 +#define DDRSS3_PHY_1350_DATA 0x00000000 +#define DDRSS3_PHY_1351_DATA 0x00010000 +#define DDRSS3_PHY_1352_DATA 0x00000000 +#define DDRSS3_PHY_1353_DATA 0x00000000 +#define DDRSS3_PHY_1354_DATA 0x00000000 +#define DDRSS3_PHY_1355_DATA 0x00000000 +#define DDRSS3_PHY_1356_DATA 0x76543210 +#define DDRSS3_PHY_1357_DATA 0x00010198 +#define DDRSS3_PHY_1358_DATA 0x00000000 +#define DDRSS3_PHY_1359_DATA 0x00000000 +#define DDRSS3_PHY_1360_DATA 0x00000000 +#define DDRSS3_PHY_1361_DATA 0x00040700 +#define DDRSS3_PHY_1362_DATA 0x00000000 +#define DDRSS3_PHY_1363_DATA 0x00000000 +#define DDRSS3_PHY_1364_DATA 0x00000000 +#define DDRSS3_PHY_1365_DATA 0x00000000 +#define DDRSS3_PHY_1366_DATA 0x00000000 +#define DDRSS3_PHY_1367_DATA 0x00000002 +#define DDRSS3_PHY_1368_DATA 0x00000000 +#define DDRSS3_PHY_1369_DATA 0x00000000 +#define DDRSS3_PHY_1370_DATA 0x00000000 +#define DDRSS3_PHY_1371_DATA 0x00000000 +#define DDRSS3_PHY_1372_DATA 0x00000000 +#define DDRSS3_PHY_1373_DATA 0x00000000 +#define DDRSS3_PHY_1374_DATA 0x00080000 +#define DDRSS3_PHY_1375_DATA 0x000007FF +#define DDRSS3_PHY_1376_DATA 0x00000000 +#define DDRSS3_PHY_1377_DATA 0x00000000 +#define DDRSS3_PHY_1378_DATA 0x00000000 +#define DDRSS3_PHY_1379_DATA 0x00000000 +#define DDRSS3_PHY_1380_DATA 0x00000000 +#define DDRSS3_PHY_1381_DATA 0x00000000 +#define DDRSS3_PHY_1382_DATA 0x000FFFFF +#define DDRSS3_PHY_1383_DATA 0x000FFFFF +#define DDRSS3_PHY_1384_DATA 0x0000FFFF +#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS3_PHY_1386_DATA 0x030FFFFF +#define DDRSS3_PHY_1387_DATA 0x01FFFFFF +#define DDRSS3_PHY_1388_DATA 0x0000FFFF +#define DDRSS3_PHY_1389_DATA 0x00000000 +#define DDRSS3_PHY_1390_DATA 0x00000000 +#define DDRSS3_PHY_1391_DATA 0x00000000 +#define DDRSS3_PHY_1392_DATA 0x00000000 +#define DDRSS3_PHY_1393_DATA 0x0001F7C0 +#define DDRSS3_PHY_1394_DATA 0x00000003 +#define DDRSS3_PHY_1395_DATA 0x00000000 +#define DDRSS3_PHY_1396_DATA 0x00001142 +#define DDRSS3_PHY_1397_DATA 0x040207AB +#define DDRSS3_PHY_1398_DATA 0x01000080 +#define DDRSS3_PHY_1399_DATA 0x03900390 +#define DDRSS3_PHY_1400_DATA 0x03900390 +#define DDRSS3_PHY_1401_DATA 0x00000390 +#define DDRSS3_PHY_1402_DATA 0x00000390 +#define DDRSS3_PHY_1403_DATA 0x00000390 +#define DDRSS3_PHY_1404_DATA 0x00000390 +#define DDRSS3_PHY_1405_DATA 0x00000005 +#define DDRSS3_PHY_1406_DATA 0x01813FCC +#define DDRSS3_PHY_1407_DATA 0x000000CC +#define DDRSS3_PHY_1408_DATA 0x0C000DFF +#define DDRSS3_PHY_1409_DATA 0x30000DFF +#define DDRSS3_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1411_DATA 0x000100F0 +#define DDRSS3_PHY_1412_DATA 0x780DFFCC +#define DDRSS3_PHY_1413_DATA 0x00007E31 +#define DDRSS3_PHY_1414_DATA 0x000CBF11 +#define DDRSS3_PHY_1415_DATA 0x01990010 +#define DDRSS3_PHY_1416_DATA 0x000CBF11 +#define DDRSS3_PHY_1417_DATA 0x01990010 +#define DDRSS3_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1419_DATA 0x00EF00F0 +#define DDRSS3_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1421_DATA 0x01FF00F0 +#define DDRSS3_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts index e8362647c5d..036d3d9d250 100644 --- a/arch/arm/dts/k3-am69-r5-sk.dts +++ b/arch/arm/dts/k3-am69-r5-sk.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-am69-sk.dts" -#include "k3-j784s4-ddr-evm-lp4-4266.dtsi" +#include "k3-am69-ddr-sk-lp4-4266.dtsi" #include "k3-j784s4-ddr.dtsi" #include "k3-am69-sk-u-boot.dtsi" #include "k3-j784s4-r5.dtsi" diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi index f0683088cf6..810415494ce 100644 --- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi +++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi @@ -1,14 +1,22 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0 - * This file was generated on 06/01/2021 + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 13:11:41 GMT+0530 (India Standard Time) */ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 -#define DDRSS_PLL_FREQUENCY_1 666500000 -#define DDRSS_PLL_FREQUENCY_2 666500000 +#define DDRSS_PLL_FREQUENCY_1 800000000 +#define DDRSS_PLL_FREQUENCY_2 800000000 + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000000 +#define DDR_REG1_SIZE_LSB 0x80000000 + #define DDRSS_CTL_00_DATA 0x00000B00 #define DDRSS_CTL_01_DATA 0x00000000 @@ -21,16 +29,16 @@ #define DDRSS_CTL_08_DATA 0x0001ADAF #define DDRSS_CTL_09_DATA 0x00000005 #define DDRSS_CTL_10_DATA 0x0000006E -#define DDRSS_CTL_11_DATA 0x000411AB -#define DDRSS_CTL_12_DATA 0x0028B0AB +#define DDRSS_CTL_11_DATA 0x0004E200 +#define DDRSS_CTL_12_DATA 0x0030D400 #define DDRSS_CTL_13_DATA 0x00000005 -#define DDRSS_CTL_14_DATA 0x00000A6B -#define DDRSS_CTL_15_DATA 0x000411AB -#define DDRSS_CTL_16_DATA 0x0028B0AB +#define DDRSS_CTL_14_DATA 0x00000C80 +#define DDRSS_CTL_15_DATA 0x0004E200 +#define DDRSS_CTL_16_DATA 0x0030D400 #define DDRSS_CTL_17_DATA 0x00000005 -#define DDRSS_CTL_18_DATA 0x00000A6B +#define DDRSS_CTL_18_DATA 0x00000C80 #define DDRSS_CTL_19_DATA 0x01010000 -#define DDRSS_CTL_20_DATA 0x02011001 +#define DDRSS_CTL_20_DATA 0x01011001 #define DDRSS_CTL_21_DATA 0x02010000 #define DDRSS_CTL_22_DATA 0x00020100 #define DDRSS_CTL_23_DATA 0x0000000B @@ -38,66 +46,66 @@ #define DDRSS_CTL_25_DATA 0x00000000 #define DDRSS_CTL_26_DATA 0x00000000 #define DDRSS_CTL_27_DATA 0x03020200 -#define DDRSS_CTL_28_DATA 0x00003636 +#define DDRSS_CTL_28_DATA 0x00004040 #define DDRSS_CTL_29_DATA 0x00100000 #define DDRSS_CTL_30_DATA 0x00000000 #define DDRSS_CTL_31_DATA 0x00000000 #define DDRSS_CTL_32_DATA 0x00000000 #define DDRSS_CTL_33_DATA 0x00000000 #define DDRSS_CTL_34_DATA 0x040C0000 -#define DDRSS_CTL_35_DATA 0x0C300C30 +#define DDRSS_CTL_35_DATA 0x0E400E40 #define DDRSS_CTL_36_DATA 0x00050804 #define DDRSS_CTL_37_DATA 0x09040008 -#define DDRSS_CTL_38_DATA 0x0D000204 -#define DDRSS_CTL_39_DATA 0x113C0057 -#define DDRSS_CTL_40_DATA 0x0D00291B -#define DDRSS_CTL_41_DATA 0x113C0057 -#define DDRSS_CTL_42_DATA 0x2000291B +#define DDRSS_CTL_38_DATA 0x14000304 +#define DDRSS_CTL_39_DATA 0x15480068 +#define DDRSS_CTL_40_DATA 0x14004220 +#define DDRSS_CTL_41_DATA 0x15480068 +#define DDRSS_CTL_42_DATA 0x20004220 #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x0400078A -#define DDRSS_CTL_45_DATA 0x130E0B04 -#define DDRSS_CTL_46_DATA 0x0A00B6D0 -#define DDRSS_CTL_47_DATA 0x130E0B0A -#define DDRSS_CTL_48_DATA 0x0A00B6D0 -#define DDRSS_CTL_49_DATA 0x0203040A -#define DDRSS_CTL_50_DATA 0x1C040500 -#define DDRSS_CTL_51_DATA 0x081D1C1D +#define DDRSS_CTL_44_DATA 0x040003C5 +#define DDRSS_CTL_45_DATA 0x17100D04 +#define DDRSS_CTL_46_DATA 0x0C006DB0 +#define DDRSS_CTL_47_DATA 0x17100D0C +#define DDRSS_CTL_48_DATA 0x0C006DB0 +#define DDRSS_CTL_49_DATA 0x0203040C +#define DDRSS_CTL_50_DATA 0x21060500 +#define DDRSS_CTL_51_DATA 0x08222122 #define DDRSS_CTL_52_DATA 0x14000E0A -#define DDRSS_CTL_53_DATA 0x02010A0A -#define DDRSS_CTL_54_DATA 0x01010002 -#define DDRSS_CTL_55_DATA 0x04383808 -#define DDRSS_CTL_56_DATA 0x041F1F04 -#define DDRSS_CTL_57_DATA 0x00001F1F +#define DDRSS_CTL_53_DATA 0x03010A0A +#define DDRSS_CTL_54_DATA 0x01010003 +#define DDRSS_CTL_55_DATA 0x0442420A +#define DDRSS_CTL_56_DATA 0x04252504 +#define DDRSS_CTL_57_DATA 0x00002525 #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 #define DDRSS_CTL_60_DATA 0x00001008 -#define DDRSS_CTL_61_DATA 0x000000CE -#define DDRSS_CTL_62_DATA 0x00000176 -#define DDRSS_CTL_63_DATA 0x00001448 -#define DDRSS_CTL_64_DATA 0x00000176 -#define DDRSS_CTL_65_DATA 0x00001448 +#define DDRSS_CTL_61_DATA 0x00000068 +#define DDRSS_CTL_62_DATA 0x000001C0 +#define DDRSS_CTL_63_DATA 0x00000C28 +#define DDRSS_CTL_64_DATA 0x000001C0 +#define DDRSS_CTL_65_DATA 0x00000C28 #define DDRSS_CTL_66_DATA 0x00000005 #define DDRSS_CTL_67_DATA 0x00040000 -#define DDRSS_CTL_68_DATA 0x005D0012 -#define DDRSS_CTL_69_DATA 0x005D0282 -#define DDRSS_CTL_70_DATA 0x00400282 +#define DDRSS_CTL_68_DATA 0x00700005 +#define DDRSS_CTL_69_DATA 0x0070017E +#define DDRSS_CTL_70_DATA 0x0040017E #define DDRSS_CTL_71_DATA 0x00120103 -#define DDRSS_CTL_72_DATA 0x000A0005 -#define DDRSS_CTL_73_DATA 0x1F08000A -#define DDRSS_CTL_74_DATA 0x0505011F +#define DDRSS_CTL_72_DATA 0x000C0005 +#define DDRSS_CTL_73_DATA 0x2408000C +#define DDRSS_CTL_74_DATA 0x05050124 #define DDRSS_CTL_75_DATA 0x0301030A -#define DDRSS_CTL_76_DATA 0x03130A07 -#define DDRSS_CTL_77_DATA 0x0A070301 -#define DDRSS_CTL_78_DATA 0x00010313 +#define DDRSS_CTL_76_DATA 0x03170C08 +#define DDRSS_CTL_77_DATA 0x0C080301 +#define DDRSS_CTL_78_DATA 0x00010317 #define DDRSS_CTL_79_DATA 0x00100010 -#define DDRSS_CTL_80_DATA 0x01800180 -#define DDRSS_CTL_81_DATA 0x01800180 +#define DDRSS_CTL_80_DATA 0x01CC01CC +#define DDRSS_CTL_81_DATA 0x01CC01CC #define DDRSS_CTL_82_DATA 0x03050505 #define DDRSS_CTL_83_DATA 0x03010303 -#define DDRSS_CTL_84_DATA 0x14070A07 -#define DDRSS_CTL_85_DATA 0x03030A03 -#define DDRSS_CTL_86_DATA 0x14070A07 -#define DDRSS_CTL_87_DATA 0x03030A03 +#define DDRSS_CTL_84_DATA 0x18080C08 +#define DDRSS_CTL_85_DATA 0x03030C03 +#define DDRSS_CTL_86_DATA 0x18080C08 +#define DDRSS_CTL_87_DATA 0x03030C03 #define DDRSS_CTL_88_DATA 0x03010000 #define DDRSS_CTL_89_DATA 0x00010000 #define DDRSS_CTL_90_DATA 0x00000000 @@ -112,27 +120,27 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x00003380 -#define DDRSS_CTL_103_DATA 0x00003380 -#define DDRSS_CTL_104_DATA 0x00003380 -#define DDRSS_CTL_105_DATA 0x00003380 -#define DDRSS_CTL_106_DATA 0x00003380 +#define DDRSS_CTL_102_DATA 0x000018C0 +#define DDRSS_CTL_103_DATA 0x000018C0 +#define DDRSS_CTL_104_DATA 0x000018C0 +#define DDRSS_CTL_105_DATA 0x000018C0 +#define DDRSS_CTL_106_DATA 0x000018C0 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x000005A2 -#define DDRSS_CTL_109_DATA 0x00051200 -#define DDRSS_CTL_110_DATA 0x00051200 -#define DDRSS_CTL_111_DATA 0x00051200 -#define DDRSS_CTL_112_DATA 0x00051200 -#define DDRSS_CTL_113_DATA 0x00051200 +#define DDRSS_CTL_108_DATA 0x000002B5 +#define DDRSS_CTL_109_DATA 0x00030A00 +#define DDRSS_CTL_110_DATA 0x00030A00 +#define DDRSS_CTL_111_DATA 0x00030A00 +#define DDRSS_CTL_112_DATA 0x00030A00 +#define DDRSS_CTL_113_DATA 0x00030A00 #define DDRSS_CTL_114_DATA 0x00000000 -#define DDRSS_CTL_115_DATA 0x00008DF8 -#define DDRSS_CTL_116_DATA 0x00051200 -#define DDRSS_CTL_117_DATA 0x00051200 -#define DDRSS_CTL_118_DATA 0x00051200 -#define DDRSS_CTL_119_DATA 0x00051200 -#define DDRSS_CTL_120_DATA 0x00051200 +#define DDRSS_CTL_115_DATA 0x00005518 +#define DDRSS_CTL_116_DATA 0x00030A00 +#define DDRSS_CTL_117_DATA 0x00030A00 +#define DDRSS_CTL_118_DATA 0x00030A00 +#define DDRSS_CTL_119_DATA 0x00030A00 +#define DDRSS_CTL_120_DATA 0x00030A00 #define DDRSS_CTL_121_DATA 0x00000000 -#define DDRSS_CTL_122_DATA 0x00008DF8 +#define DDRSS_CTL_122_DATA 0x00005518 #define DDRSS_CTL_123_DATA 0x00000000 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x00000000 @@ -141,8 +149,8 @@ #define DDRSS_CTL_128_DATA 0x00000000 #define DDRSS_CTL_129_DATA 0x00000000 #define DDRSS_CTL_130_DATA 0x00000000 -#define DDRSS_CTL_131_DATA 0x07030500 -#define DDRSS_CTL_132_DATA 0x00030703 +#define DDRSS_CTL_131_DATA 0x08030500 +#define DDRSS_CTL_132_DATA 0x00030803 #define DDRSS_CTL_133_DATA 0x0A090000 #define DDRSS_CTL_134_DATA 0x0A090701 #define DDRSS_CTL_135_DATA 0x0900000E @@ -177,31 +185,31 @@ #define DDRSS_CTL_164_DATA 0x000B0000 #define DDRSS_CTL_165_DATA 0x000E0006 #define DDRSS_CTL_166_DATA 0x000E0404 -#define DDRSS_CTL_167_DATA 0x0086010B -#define DDRSS_CTL_168_DATA 0x0A0A014E -#define DDRSS_CTL_169_DATA 0x010B014E -#define DDRSS_CTL_170_DATA 0x014E0086 -#define DDRSS_CTL_171_DATA 0x014E0A0A +#define DDRSS_CTL_167_DATA 0x00A00140 +#define DDRSS_CTL_168_DATA 0x0C0C0190 +#define DDRSS_CTL_169_DATA 0x01400190 +#define DDRSS_CTL_170_DATA 0x019000A0 +#define DDRSS_CTL_171_DATA 0x01900C0C #define DDRSS_CTL_172_DATA 0x00000000 #define DDRSS_CTL_173_DATA 0x00000000 #define DDRSS_CTL_174_DATA 0x00000000 -#define DDRSS_CTL_175_DATA 0x24C40084 -#define DDRSS_CTL_176_DATA 0x2B0024C4 -#define DDRSS_CTL_177_DATA 0x00002B2B +#define DDRSS_CTL_175_DATA 0x2DD40084 +#define DDRSS_CTL_176_DATA 0xEB002DD4 +#define DDRSS_CTL_177_DATA 0x0000EBEB #define DDRSS_CTL_178_DATA 0x36000000 #define DDRSS_CTL_179_DATA 0x27270036 #define DDRSS_CTL_180_DATA 0x0F0F0000 #define DDRSS_CTL_181_DATA 0x15000000 #define DDRSS_CTL_182_DATA 0x00841515 -#define DDRSS_CTL_183_DATA 0x24C424C4 -#define DDRSS_CTL_184_DATA 0x2B2B2B00 +#define DDRSS_CTL_183_DATA 0x2DD42DD4 +#define DDRSS_CTL_184_DATA 0xEBEBEB00 #define DDRSS_CTL_185_DATA 0x00000000 #define DDRSS_CTL_186_DATA 0x00363600 #define DDRSS_CTL_187_DATA 0x00002727 #define DDRSS_CTL_188_DATA 0x00000F0F #define DDRSS_CTL_189_DATA 0x15151500 #define DDRSS_CTL_190_DATA 0x00000020 -#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x01000000 #define DDRSS_CTL_192_DATA 0x00000001 #define DDRSS_CTL_193_DATA 0x00000000 #define DDRSS_CTL_194_DATA 0x01000000 @@ -239,17 +247,17 @@ #define DDRSS_CTL_226_DATA 0x00000000 #define DDRSS_CTL_227_DATA 0x15110000 #define DDRSS_CTL_228_DATA 0x00040C18 -#define DDRSS_CTL_229_DATA 0x00000000 -#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_229_DATA 0xF000C000 +#define DDRSS_CTL_230_DATA 0x0000F000 #define DDRSS_CTL_231_DATA 0x00000000 #define DDRSS_CTL_232_DATA 0x00000000 -#define DDRSS_CTL_233_DATA 0x00000000 -#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0xC0000000 +#define DDRSS_CTL_234_DATA 0xF000F000 #define DDRSS_CTL_235_DATA 0x00000000 #define DDRSS_CTL_236_DATA 0x00000000 #define DDRSS_CTL_237_DATA 0x00000000 -#define DDRSS_CTL_238_DATA 0x00000000 -#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0xF000C000 +#define DDRSS_CTL_239_DATA 0x0000F000 #define DDRSS_CTL_240_DATA 0x00000000 #define DDRSS_CTL_241_DATA 0x00000000 #define DDRSS_CTL_242_DATA 0x00030000 @@ -271,13 +279,13 @@ #define DDRSS_CTL_258_DATA 0x00370040 #define DDRSS_CTL_259_DATA 0x00020008 #define DDRSS_CTL_260_DATA 0x00400100 -#define DDRSS_CTL_261_DATA 0x00280536 +#define DDRSS_CTL_261_DATA 0x00300640 #define DDRSS_CTL_262_DATA 0x01000200 -#define DDRSS_CTL_263_DATA 0x05360040 -#define DDRSS_CTL_264_DATA 0x00000028 -#define DDRSS_CTL_265_DATA 0x00430003 -#define DDRSS_CTL_266_DATA 0x01000043 -#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x06400040 +#define DDRSS_CTL_264_DATA 0x00000030 +#define DDRSS_CTL_265_DATA 0x00500003 +#define DDRSS_CTL_266_DATA 0x01000050 +#define DDRSS_CTL_267_DATA 0x03030303 #define DDRSS_CTL_268_DATA 0x01010000 #define DDRSS_CTL_269_DATA 0x00000202 #define DDRSS_CTL_270_DATA 0x00000FFF @@ -301,14 +309,14 @@ #define DDRSS_CTL_288_DATA 0x00000000 #define DDRSS_CTL_289_DATA 0x00000000 #define DDRSS_CTL_290_DATA 0x03030300 -#define DDRSS_CTL_291_DATA 0x00000001 +#define DDRSS_CTL_291_DATA 0x00010101 #define DDRSS_CTL_292_DATA 0x00000000 #define DDRSS_CTL_293_DATA 0x00000000 #define DDRSS_CTL_294_DATA 0x00000000 #define DDRSS_CTL_295_DATA 0x00000000 #define DDRSS_CTL_296_DATA 0x00000000 -#define DDRSS_CTL_297_DATA 0x00000000 -#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0xFFFFFFFF +#define DDRSS_CTL_298_DATA 0x00000FFF #define DDRSS_CTL_299_DATA 0x00000000 #define DDRSS_CTL_300_DATA 0x00000000 #define DDRSS_CTL_301_DATA 0x00000000 @@ -328,15 +336,15 @@ #define DDRSS_CTL_315_DATA 0x01000101 #define DDRSS_CTL_316_DATA 0x01010001 #define DDRSS_CTL_317_DATA 0x00010101 -#define DDRSS_CTL_318_DATA 0x05070703 -#define DDRSS_CTL_319_DATA 0x0A081414 -#define DDRSS_CTL_320_DATA 0x0009030A -#define DDRSS_CTL_321_DATA 0x080C030F -#define DDRSS_CTL_322_DATA 0x080C0306 -#define DDRSS_CTL_323_DATA 0x0C090006 -#define DDRSS_CTL_324_DATA 0x0100000C -#define DDRSS_CTL_325_DATA 0x05020501 -#define DDRSS_CTL_326_DATA 0x00000002 +#define DDRSS_CTL_318_DATA 0x05080803 +#define DDRSS_CTL_319_DATA 0x0C081C1C +#define DDRSS_CTL_320_DATA 0x0009030C +#define DDRSS_CTL_321_DATA 0x090B030F +#define DDRSS_CTL_322_DATA 0x090B0306 +#define DDRSS_CTL_323_DATA 0x0B090006 +#define DDRSS_CTL_324_DATA 0x0100000B +#define DDRSS_CTL_325_DATA 0x06030601 +#define DDRSS_CTL_326_DATA 0x00000003 #define DDRSS_CTL_327_DATA 0x00000000 #define DDRSS_CTL_328_DATA 0x00010000 #define DDRSS_CTL_329_DATA 0x00280D00 @@ -397,32 +405,32 @@ #define DDRSS_CTL_384_DATA 0x00000000 #define DDRSS_CTL_385_DATA 0x00000000 #define DDRSS_CTL_386_DATA 0x00000000 -#define DDRSS_CTL_387_DATA 0x2E2E1B00 +#define DDRSS_CTL_387_DATA 0x33331B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x0000019C +#define DDRSS_CTL_389_DATA 0x000000C6 #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x000004D4 -#define DDRSS_CTL_395_DATA 0x00001018 +#define DDRSS_CTL_394_DATA 0x00000270 +#define DDRSS_CTL_395_DATA 0x000007BC #define DDRSS_CTL_396_DATA 0x00000204 -#define DDRSS_CTL_397_DATA 0x00002890 +#define DDRSS_CTL_397_DATA 0x00001850 #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x00000200 #define DDRSS_CTL_400_DATA 0x00000200 #define DDRSS_CTL_401_DATA 0x00000200 -#define DDRSS_CTL_402_DATA 0x000079B0 -#define DDRSS_CTL_403_DATA 0x000195A0 -#define DDRSS_CTL_404_DATA 0x0000080E -#define DDRSS_CTL_405_DATA 0x00002890 +#define DDRSS_CTL_402_DATA 0x000048F0 +#define DDRSS_CTL_403_DATA 0x0000F320 +#define DDRSS_CTL_404_DATA 0x00000A14 +#define DDRSS_CTL_405_DATA 0x00001850 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 #define DDRSS_CTL_409_DATA 0x00000200 -#define DDRSS_CTL_410_DATA 0x000079B0 -#define DDRSS_CTL_411_DATA 0x000195A0 -#define DDRSS_CTL_412_DATA 0x0202080E +#define DDRSS_CTL_410_DATA 0x000048F0 +#define DDRSS_CTL_411_DATA 0x0000F320 +#define DDRSS_CTL_412_DATA 0x02020A14 #define DDRSS_CTL_413_DATA 0x03030202 #define DDRSS_CTL_414_DATA 0x00000022 #define DDRSS_CTL_415_DATA 0x00000000 @@ -433,13 +441,13 @@ #define DDRSS_CTL_420_DATA 0x00000000 #define DDRSS_CTL_421_DATA 0x00030000 #define DDRSS_CTL_422_DATA 0x0007001F -#define DDRSS_CTL_423_DATA 0x0013002B -#define DDRSS_CTL_424_DATA 0x0013002B +#define DDRSS_CTL_423_DATA 0x0016002E +#define DDRSS_CTL_424_DATA 0x0016002E #define DDRSS_CTL_425_DATA 0x00000000 #define DDRSS_CTL_426_DATA 0x00000000 #define DDRSS_CTL_427_DATA 0x02000000 #define DDRSS_CTL_428_DATA 0x01000404 -#define DDRSS_CTL_429_DATA 0x05120512 +#define DDRSS_CTL_429_DATA 0x071A071A #define DDRSS_CTL_430_DATA 0x00000105 #define DDRSS_CTL_431_DATA 0x00010101 #define DDRSS_CTL_432_DATA 0x00010101 @@ -448,8 +456,8 @@ #define DDRSS_CTL_435_DATA 0x02000201 #define DDRSS_CTL_436_DATA 0x02010000 #define DDRSS_CTL_437_DATA 0x00000200 -#define DDRSS_CTL_438_DATA 0x18060000 -#define DDRSS_CTL_439_DATA 0x00000118 +#define DDRSS_CTL_438_DATA 0x1E060000 +#define DDRSS_CTL_439_DATA 0x0000011E #define DDRSS_CTL_440_DATA 0xFFFFFFFF #define DDRSS_CTL_441_DATA 0xFFFFFFFF #define DDRSS_CTL_442_DATA 0x00000000 @@ -482,8 +490,8 @@ #define DDRSS_PI_09_DATA 0x00000000 #define DDRSS_PI_10_DATA 0x00000000 #define DDRSS_PI_11_DATA 0x00000000 -#define DDRSS_PI_12_DATA 0x00000007 -#define DDRSS_PI_13_DATA 0x00010002 +#define DDRSS_PI_12_DATA 0x00000003 +#define DDRSS_PI_13_DATA 0x00010001 #define DDRSS_PI_14_DATA 0x0800000F #define DDRSS_PI_15_DATA 0x00000103 #define DDRSS_PI_16_DATA 0x00000005 @@ -516,7 +524,7 @@ #define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x000F0F00 -#define DDRSS_PI_46_DATA 0x00000017 +#define DDRSS_PI_46_DATA 0x00000019 #define DDRSS_PI_47_DATA 0x000007D0 #define DDRSS_PI_48_DATA 0x00000300 #define DDRSS_PI_49_DATA 0x00000000 @@ -531,18 +539,18 @@ #define DDRSS_PI_58_DATA 0x00000000 #define DDRSS_PI_59_DATA 0x00000000 #define DDRSS_PI_60_DATA 0x0A0A140A -#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_61_DATA 0x10020201 #define DDRSS_PI_62_DATA 0x00020805 #define DDRSS_PI_63_DATA 0x01000404 #define DDRSS_PI_64_DATA 0x00000000 #define DDRSS_PI_65_DATA 0x00000000 -#define DDRSS_PI_66_DATA 0x00000100 -#define DDRSS_PI_67_DATA 0x0001010F +#define DDRSS_PI_66_DATA 0x01000100 +#define DDRSS_PI_67_DATA 0x0102020F #define DDRSS_PI_68_DATA 0x00340000 #define DDRSS_PI_69_DATA 0x00000000 #define DDRSS_PI_70_DATA 0x00000000 #define DDRSS_PI_71_DATA 0x0000FFFF -#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_72_DATA 0x01000000 #define DDRSS_PI_73_DATA 0x00080100 #define DDRSS_PI_74_DATA 0x02000200 #define DDRSS_PI_75_DATA 0x01000100 @@ -631,104 +639,104 @@ #define DDRSS_PI_158_DATA 0x00000000 #define DDRSS_PI_159_DATA 0x00000401 #define DDRSS_PI_160_DATA 0x00000000 -#define DDRSS_PI_161_DATA 0x00010000 -#define DDRSS_PI_162_DATA 0x00000000 -#define DDRSS_PI_163_DATA 0x1B1B0200 +#define DDRSS_PI_161_DATA 0x05010000 +#define DDRSS_PI_162_DATA 0x00000001 +#define DDRSS_PI_163_DATA 0x20200201 #define DDRSS_PI_164_DATA 0x00000034 -#define DDRSS_PI_165_DATA 0x00000051 -#define DDRSS_PI_166_DATA 0x00020051 +#define DDRSS_PI_165_DATA 0x0000005C +#define DDRSS_PI_166_DATA 0x0002005C #define DDRSS_PI_167_DATA 0x02000200 -#define DDRSS_PI_168_DATA 0x300C0C04 -#define DDRSS_PI_169_DATA 0x0010300C -#define DDRSS_PI_170_DATA 0x000000CE -#define DDRSS_PI_171_DATA 0x00000176 -#define DDRSS_PI_172_DATA 0x00001448 -#define DDRSS_PI_173_DATA 0x00000176 -#define DDRSS_PI_174_DATA 0x04001448 +#define DDRSS_PI_168_DATA 0x400E0C04 +#define DDRSS_PI_169_DATA 0x0010400E +#define DDRSS_PI_170_DATA 0x00000068 +#define DDRSS_PI_171_DATA 0x000001C0 +#define DDRSS_PI_172_DATA 0x00000C28 +#define DDRSS_PI_173_DATA 0x000001C0 +#define DDRSS_PI_174_DATA 0x04000C28 #define DDRSS_PI_175_DATA 0x01010404 -#define DDRSS_PI_176_DATA 0x00001501 +#define DDRSS_PI_176_DATA 0x00001500 #define DDRSS_PI_177_DATA 0x00150015 #define DDRSS_PI_178_DATA 0x01000100 #define DDRSS_PI_179_DATA 0x00000100 #define DDRSS_PI_180_DATA 0x00000000 #define DDRSS_PI_181_DATA 0x01010101 -#define DDRSS_PI_182_DATA 0x00000101 -#define DDRSS_PI_183_DATA 0x00000100 -#define DDRSS_PI_184_DATA 0x00000100 -#define DDRSS_PI_185_DATA 0x0E040100 -#define DDRSS_PI_186_DATA 0x0808020E +#define DDRSS_PI_182_DATA 0x00010000 +#define DDRSS_PI_183_DATA 0x00010100 +#define DDRSS_PI_184_DATA 0x00010100 +#define DDRSS_PI_185_DATA 0x14040100 +#define DDRSS_PI_186_DATA 0x0A0A0214 #define DDRSS_PI_187_DATA 0x00040402 #define DDRSS_PI_188_DATA 0x000D0035 -#define DDRSS_PI_189_DATA 0x00198041 -#define DDRSS_PI_190_DATA 0x00198041 -#define DDRSS_PI_191_DATA 0x01010101 -#define DDRSS_PI_192_DATA 0x0002000E -#define DDRSS_PI_193_DATA 0x0002014E -#define DDRSS_PI_194_DATA 0x0100014E +#define DDRSS_PI_189_DATA 0x001C0044 +#define DDRSS_PI_190_DATA 0x001C0044 +#define DDRSS_PI_191_DATA 0x01000101 +#define DDRSS_PI_192_DATA 0x0003000E +#define DDRSS_PI_193_DATA 0x00030190 +#define DDRSS_PI_194_DATA 0x01000190 #define DDRSS_PI_195_DATA 0x000F000F -#define DDRSS_PI_196_DATA 0x014F0100 -#define DDRSS_PI_197_DATA 0x0100014F -#define DDRSS_PI_198_DATA 0x014F014F -#define DDRSS_PI_199_DATA 0x32103200 -#define DDRSS_PI_200_DATA 0x01013210 +#define DDRSS_PI_196_DATA 0x01910100 +#define DDRSS_PI_197_DATA 0x01000191 +#define DDRSS_PI_198_DATA 0x01910191 +#define DDRSS_PI_199_DATA 0x2F1B3200 +#define DDRSS_PI_200_DATA 0x01012F1B #define DDRSS_PI_201_DATA 0x0A070601 -#define DDRSS_PI_202_DATA 0x140D080D -#define DDRSS_PI_203_DATA 0x140D0810 -#define DDRSS_PI_204_DATA 0x0000C010 +#define DDRSS_PI_202_DATA 0x180F090D +#define DDRSS_PI_203_DATA 0x180F0911 +#define DDRSS_PI_204_DATA 0x0000C011 #define DDRSS_PI_205_DATA 0x00C01000 #define DDRSS_PI_206_DATA 0x00C01000 #define DDRSS_PI_207_DATA 0x00021000 -#define DDRSS_PI_208_DATA 0x001C000E -#define DDRSS_PI_209_DATA 0x001C014E -#define DDRSS_PI_210_DATA 0x0011014E +#define DDRSS_PI_208_DATA 0x001E000E +#define DDRSS_PI_209_DATA 0x001E0190 +#define DDRSS_PI_210_DATA 0x00110190 #define DDRSS_PI_211_DATA 0x32000056 -#define DDRSS_PI_212_DATA 0x00000301 -#define DDRSS_PI_213_DATA 0x005A002A +#define DDRSS_PI_212_DATA 0x00000101 +#define DDRSS_PI_213_DATA 0x005E0030 #define DDRSS_PI_214_DATA 0x03013212 -#define DDRSS_PI_215_DATA 0x00002A00 -#define DDRSS_PI_216_DATA 0x3212005A -#define DDRSS_PI_217_DATA 0x09000301 -#define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x040006C9 +#define DDRSS_PI_215_DATA 0x00003000 +#define DDRSS_PI_216_DATA 0x3212005E +#define DDRSS_PI_217_DATA 0x09000001 +#define DDRSS_PI_218_DATA 0x06010504 +#define DDRSS_PI_219_DATA 0x04000364 #define DDRSS_PI_220_DATA 0x0A032001 -#define DDRSS_PI_221_DATA 0x1C1F0B0A -#define DDRSS_PI_222_DATA 0x00001D12 -#define DDRSS_PI_223_DATA 0x3C00A488 -#define DDRSS_PI_224_DATA 0x13142005 -#define DDRSS_PI_225_DATA 0x1C1F0B0E -#define DDRSS_PI_226_DATA 0x00001D12 -#define DDRSS_PI_227_DATA 0x3C00A488 -#define DDRSS_PI_228_DATA 0x13142005 -#define DDRSS_PI_229_DATA 0x00019C0E -#define DDRSS_PI_230_DATA 0x00001018 -#define DDRSS_PI_231_DATA 0x00002890 -#define DDRSS_PI_232_DATA 0x000195A0 -#define DDRSS_PI_233_DATA 0x00002890 -#define DDRSS_PI_234_DATA 0x000195A0 -#define DDRSS_PI_235_DATA 0x01800010 -#define DDRSS_PI_236_DATA 0x03030180 +#define DDRSS_PI_221_DATA 0x21250D0A +#define DDRSS_PI_222_DATA 0x00002216 +#define DDRSS_PI_223_DATA 0x480062B8 +#define DDRSS_PI_224_DATA 0x17182006 +#define DDRSS_PI_225_DATA 0x21250D10 +#define DDRSS_PI_226_DATA 0x00002216 +#define DDRSS_PI_227_DATA 0x480062B8 +#define DDRSS_PI_228_DATA 0x17182006 +#define DDRSS_PI_229_DATA 0x0000C610 +#define DDRSS_PI_230_DATA 0x000007BC +#define DDRSS_PI_231_DATA 0x00001850 +#define DDRSS_PI_232_DATA 0x0000F320 +#define DDRSS_PI_233_DATA 0x00001850 +#define DDRSS_PI_234_DATA 0x0000F320 +#define DDRSS_PI_235_DATA 0x01CC0010 +#define DDRSS_PI_236_DATA 0x030301CC #define DDRSS_PI_237_DATA 0x002AF803 #define DDRSS_PI_238_DATA 0x0001ADAF #define DDRSS_PI_239_DATA 0x00000005 #define DDRSS_PI_240_DATA 0x0000006E #define DDRSS_PI_241_DATA 0x00000010 -#define DDRSS_PI_242_DATA 0x000411AB +#define DDRSS_PI_242_DATA 0x0004E200 #define DDRSS_PI_243_DATA 0x0001ADAF #define DDRSS_PI_244_DATA 0x00000005 -#define DDRSS_PI_245_DATA 0x00000A6B -#define DDRSS_PI_246_DATA 0x00000180 -#define DDRSS_PI_247_DATA 0x000411AB +#define DDRSS_PI_245_DATA 0x00000C80 +#define DDRSS_PI_246_DATA 0x000001CC +#define DDRSS_PI_247_DATA 0x0004E200 #define DDRSS_PI_248_DATA 0x0001ADAF #define DDRSS_PI_249_DATA 0x00000005 -#define DDRSS_PI_250_DATA 0x00000A6B -#define DDRSS_PI_251_DATA 0x01000180 +#define DDRSS_PI_250_DATA 0x00000C80 +#define DDRSS_PI_251_DATA 0x010001CC #define DDRSS_PI_252_DATA 0x00370040 #define DDRSS_PI_253_DATA 0x00010008 -#define DDRSS_PI_254_DATA 0x05360040 -#define DDRSS_PI_255_DATA 0x00010028 -#define DDRSS_PI_256_DATA 0x05360040 -#define DDRSS_PI_257_DATA 0x00000328 -#define DDRSS_PI_258_DATA 0x00430043 +#define DDRSS_PI_254_DATA 0x06400040 +#define DDRSS_PI_255_DATA 0x00010030 +#define DDRSS_PI_256_DATA 0x06400040 +#define DDRSS_PI_257_DATA 0x00000330 +#define DDRSS_PI_258_DATA 0x00500050 #define DDRSS_PI_259_DATA 0x08040404 #define DDRSS_PI_260_DATA 0x00000055 #define DDRSS_PI_261_DATA 0x55083C5A @@ -745,29 +753,29 @@ #define DDRSS_PI_272_DATA 0x00080804 #define DDRSS_PI_273_DATA 0x00000000 #define DDRSS_PI_274_DATA 0x00000000 -#define DDRSS_PI_275_DATA 0x002B0084 +#define DDRSS_PI_275_DATA 0x00EB0084 #define DDRSS_PI_276_DATA 0x00150000 -#define DDRSS_PI_277_DATA 0x362B24C4 +#define DDRSS_PI_277_DATA 0x36EB2DD4 #define DDRSS_PI_278_DATA 0x00150F27 -#define DDRSS_PI_279_DATA 0x362B24C4 +#define DDRSS_PI_279_DATA 0x36EB2DD4 #define DDRSS_PI_280_DATA 0x00150F27 -#define DDRSS_PI_281_DATA 0x002B0084 +#define DDRSS_PI_281_DATA 0x00EB0084 #define DDRSS_PI_282_DATA 0x00150000 -#define DDRSS_PI_283_DATA 0x362B24C4 +#define DDRSS_PI_283_DATA 0x36EB2DD4 #define DDRSS_PI_284_DATA 0x00150F27 -#define DDRSS_PI_285_DATA 0x362B24C4 +#define DDRSS_PI_285_DATA 0x36EB2DD4 #define DDRSS_PI_286_DATA 0x00150F27 -#define DDRSS_PI_287_DATA 0x002B0084 +#define DDRSS_PI_287_DATA 0x00EB0084 #define DDRSS_PI_288_DATA 0x00150000 -#define DDRSS_PI_289_DATA 0x362B24C4 +#define DDRSS_PI_289_DATA 0x36EB2DD4 #define DDRSS_PI_290_DATA 0x00150F27 -#define DDRSS_PI_291_DATA 0x362B24C4 +#define DDRSS_PI_291_DATA 0x36EB2DD4 #define DDRSS_PI_292_DATA 0x00150F27 -#define DDRSS_PI_293_DATA 0x002B0084 +#define DDRSS_PI_293_DATA 0x00EB0084 #define DDRSS_PI_294_DATA 0x00150000 -#define DDRSS_PI_295_DATA 0x362B24C4 +#define DDRSS_PI_295_DATA 0x36EB2DD4 #define DDRSS_PI_296_DATA 0x00150F27 -#define DDRSS_PI_297_DATA 0x362B24C4 +#define DDRSS_PI_297_DATA 0x36EB2DD4 #define DDRSS_PI_298_DATA 0x00150F27 #define DDRSS_PI_299_DATA 0x00000000 @@ -783,7 +791,7 @@ #define DDRSS_PHY_09_DATA 0x00000000 #define DDRSS_PHY_10_DATA 0x00000000 #define DDRSS_PHY_11_DATA 0x01000001 -#define DDRSS_PHY_12_DATA 0x00000100 +#define DDRSS_PHY_12_DATA 0x00000200 #define DDRSS_PHY_13_DATA 0x000800C0 #define DDRSS_PHY_14_DATA 0x060100CC #define DDRSS_PHY_15_DATA 0x00030066 @@ -802,9 +810,9 @@ #define DDRSS_PHY_28_DATA 0x2A000000 #define DDRSS_PHY_29_DATA 0x00000808 #define DDRSS_PHY_30_DATA 0x0F000000 -#define DDRSS_PHY_31_DATA 0x00000F0F -#define DDRSS_PHY_32_DATA 0x10200000 -#define DDRSS_PHY_33_DATA 0x0C002007 +#define DDRSS_PHY_31_DATA 0x00000F08 +#define DDRSS_PHY_32_DATA 0x10400000 +#define DDRSS_PHY_33_DATA 0x0C002006 #define DDRSS_PHY_34_DATA 0x00000000 #define DDRSS_PHY_35_DATA 0x00000000 #define DDRSS_PHY_36_DATA 0x55555555 @@ -871,20 +879,20 @@ #define DDRSS_PHY_97_DATA 0x00050010 #define DDRSS_PHY_98_DATA 0x51517041 #define DDRSS_PHY_99_DATA 0x31C06000 -#define DDRSS_PHY_100_DATA 0x07AB0340 +#define DDRSS_PHY_100_DATA 0x07AB01AB #define DDRSS_PHY_101_DATA 0x00C0C001 -#define DDRSS_PHY_102_DATA 0x09080001 +#define DDRSS_PHY_102_DATA 0x0B0A0101 #define DDRSS_PHY_103_DATA 0x10001000 -#define DDRSS_PHY_104_DATA 0x0C063E42 -#define DDRSS_PHY_105_DATA 0x0F0C2701 +#define DDRSS_PHY_104_DATA 0x0C073E42 +#define DDRSS_PHY_105_DATA 0x0F0C2D01 #define DDRSS_PHY_106_DATA 0x01000140 -#define DDRSS_PHY_107_DATA 0x04000420 +#define DDRSS_PHY_107_DATA 0x0C000420 #define DDRSS_PHY_108_DATA 0x00000198 #define DDRSS_PHY_109_DATA 0x0A0000D0 #define DDRSS_PHY_110_DATA 0x00030200 #define DDRSS_PHY_111_DATA 0x02800000 #define DDRSS_PHY_112_DATA 0x80800000 -#define DDRSS_PHY_113_DATA 0x00092010 +#define DDRSS_PHY_113_DATA 0x000B2010 #define DDRSS_PHY_114_DATA 0x76543210 #define DDRSS_PHY_115_DATA 0x00000008 #define DDRSS_PHY_116_DATA 0x02800280 @@ -901,8 +909,8 @@ #define DDRSS_PHY_127_DATA 0x00A000A0 #define DDRSS_PHY_128_DATA 0x00A000A0 #define DDRSS_PHY_129_DATA 0x00A000A0 -#define DDRSS_PHY_130_DATA 0x01C400A0 -#define DDRSS_PHY_131_DATA 0x01A00003 +#define DDRSS_PHY_130_DATA 0x011900A0 +#define DDRSS_PHY_131_DATA 0x01A00004 #define DDRSS_PHY_132_DATA 0x00000000 #define DDRSS_PHY_133_DATA 0x00000000 #define DDRSS_PHY_134_DATA 0x00080200 @@ -1039,7 +1047,7 @@ #define DDRSS_PHY_265_DATA 0x00000000 #define DDRSS_PHY_266_DATA 0x00000000 #define DDRSS_PHY_267_DATA 0x01000001 -#define DDRSS_PHY_268_DATA 0x00000100 +#define DDRSS_PHY_268_DATA 0x00000200 #define DDRSS_PHY_269_DATA 0x000800C0 #define DDRSS_PHY_270_DATA 0x060100CC #define DDRSS_PHY_271_DATA 0x00030066 @@ -1058,9 +1066,9 @@ #define DDRSS_PHY_284_DATA 0x2A000000 #define DDRSS_PHY_285_DATA 0x00000808 #define DDRSS_PHY_286_DATA 0x0F000000 -#define DDRSS_PHY_287_DATA 0x00000F0F -#define DDRSS_PHY_288_DATA 0x10200000 -#define DDRSS_PHY_289_DATA 0x0C002007 +#define DDRSS_PHY_287_DATA 0x00000F08 +#define DDRSS_PHY_288_DATA 0x10400000 +#define DDRSS_PHY_289_DATA 0x0C002006 #define DDRSS_PHY_290_DATA 0x00000000 #define DDRSS_PHY_291_DATA 0x00000000 #define DDRSS_PHY_292_DATA 0x55555555 @@ -1127,20 +1135,20 @@ #define DDRSS_PHY_353_DATA 0x00050010 #define DDRSS_PHY_354_DATA 0x51517041 #define DDRSS_PHY_355_DATA 0x31C06000 -#define DDRSS_PHY_356_DATA 0x07AB0340 +#define DDRSS_PHY_356_DATA 0x07AB01AB #define DDRSS_PHY_357_DATA 0x00C0C001 -#define DDRSS_PHY_358_DATA 0x09080001 +#define DDRSS_PHY_358_DATA 0x0B0A0101 #define DDRSS_PHY_359_DATA 0x10001000 -#define DDRSS_PHY_360_DATA 0x0C063E42 -#define DDRSS_PHY_361_DATA 0x0F0C2701 +#define DDRSS_PHY_360_DATA 0x0C073E42 +#define DDRSS_PHY_361_DATA 0x0F0C2D01 #define DDRSS_PHY_362_DATA 0x01000140 -#define DDRSS_PHY_363_DATA 0x04000420 +#define DDRSS_PHY_363_DATA 0x0C000420 #define DDRSS_PHY_364_DATA 0x00000198 #define DDRSS_PHY_365_DATA 0x0A0000D0 #define DDRSS_PHY_366_DATA 0x00030200 #define DDRSS_PHY_367_DATA 0x02800000 #define DDRSS_PHY_368_DATA 0x80800000 -#define DDRSS_PHY_369_DATA 0x00092010 +#define DDRSS_PHY_369_DATA 0x000B2010 #define DDRSS_PHY_370_DATA 0x76543210 #define DDRSS_PHY_371_DATA 0x00000008 #define DDRSS_PHY_372_DATA 0x02800280 @@ -1157,8 +1165,8 @@ #define DDRSS_PHY_383_DATA 0x00A000A0 #define DDRSS_PHY_384_DATA 0x00A000A0 #define DDRSS_PHY_385_DATA 0x00A000A0 -#define DDRSS_PHY_386_DATA 0x01C400A0 -#define DDRSS_PHY_387_DATA 0x01A00003 +#define DDRSS_PHY_386_DATA 0x011900A0 +#define DDRSS_PHY_387_DATA 0x01A00004 #define DDRSS_PHY_388_DATA 0x00000000 #define DDRSS_PHY_389_DATA 0x00000000 #define DDRSS_PHY_390_DATA 0x00080200 @@ -1295,7 +1303,7 @@ #define DDRSS_PHY_521_DATA 0x00000000 #define DDRSS_PHY_522_DATA 0x00000000 #define DDRSS_PHY_523_DATA 0x01000001 -#define DDRSS_PHY_524_DATA 0x00000100 +#define DDRSS_PHY_524_DATA 0x00000200 #define DDRSS_PHY_525_DATA 0x000800C0 #define DDRSS_PHY_526_DATA 0x060100CC #define DDRSS_PHY_527_DATA 0x00030066 @@ -1314,9 +1322,9 @@ #define DDRSS_PHY_540_DATA 0x2A000000 #define DDRSS_PHY_541_DATA 0x00000808 #define DDRSS_PHY_542_DATA 0x0F000000 -#define DDRSS_PHY_543_DATA 0x00000F0F -#define DDRSS_PHY_544_DATA 0x10200000 -#define DDRSS_PHY_545_DATA 0x0C002007 +#define DDRSS_PHY_543_DATA 0x00000F08 +#define DDRSS_PHY_544_DATA 0x10400000 +#define DDRSS_PHY_545_DATA 0x0C002006 #define DDRSS_PHY_546_DATA 0x00000000 #define DDRSS_PHY_547_DATA 0x00000000 #define DDRSS_PHY_548_DATA 0x55555555 @@ -1383,20 +1391,20 @@ #define DDRSS_PHY_609_DATA 0x00050010 #define DDRSS_PHY_610_DATA 0x51517041 #define DDRSS_PHY_611_DATA 0x31C06000 -#define DDRSS_PHY_612_DATA 0x07AB0340 +#define DDRSS_PHY_612_DATA 0x07AB01AB #define DDRSS_PHY_613_DATA 0x00C0C001 -#define DDRSS_PHY_614_DATA 0x09080001 +#define DDRSS_PHY_614_DATA 0x0B0A0101 #define DDRSS_PHY_615_DATA 0x10001000 -#define DDRSS_PHY_616_DATA 0x0C063E42 -#define DDRSS_PHY_617_DATA 0x0F0C2701 +#define DDRSS_PHY_616_DATA 0x0C073E42 +#define DDRSS_PHY_617_DATA 0x0F0C2D01 #define DDRSS_PHY_618_DATA 0x01000140 -#define DDRSS_PHY_619_DATA 0x04000420 +#define DDRSS_PHY_619_DATA 0x0C000420 #define DDRSS_PHY_620_DATA 0x00000198 #define DDRSS_PHY_621_DATA 0x0A0000D0 #define DDRSS_PHY_622_DATA 0x00030200 #define DDRSS_PHY_623_DATA 0x02800000 #define DDRSS_PHY_624_DATA 0x80800000 -#define DDRSS_PHY_625_DATA 0x00092010 +#define DDRSS_PHY_625_DATA 0x000B2010 #define DDRSS_PHY_626_DATA 0x76543210 #define DDRSS_PHY_627_DATA 0x00000008 #define DDRSS_PHY_628_DATA 0x02800280 @@ -1413,8 +1421,8 @@ #define DDRSS_PHY_639_DATA 0x00A000A0 #define DDRSS_PHY_640_DATA 0x00A000A0 #define DDRSS_PHY_641_DATA 0x00A000A0 -#define DDRSS_PHY_642_DATA 0x01C400A0 -#define DDRSS_PHY_643_DATA 0x01A00003 +#define DDRSS_PHY_642_DATA 0x011900A0 +#define DDRSS_PHY_643_DATA 0x01A00004 #define DDRSS_PHY_644_DATA 0x00000000 #define DDRSS_PHY_645_DATA 0x00000000 #define DDRSS_PHY_646_DATA 0x00080200 @@ -1551,7 +1559,7 @@ #define DDRSS_PHY_777_DATA 0x00000000 #define DDRSS_PHY_778_DATA 0x00000000 #define DDRSS_PHY_779_DATA 0x01000001 -#define DDRSS_PHY_780_DATA 0x00000100 +#define DDRSS_PHY_780_DATA 0x00000200 #define DDRSS_PHY_781_DATA 0x000800C0 #define DDRSS_PHY_782_DATA 0x060100CC #define DDRSS_PHY_783_DATA 0x00030066 @@ -1570,9 +1578,9 @@ #define DDRSS_PHY_796_DATA 0x2A000000 #define DDRSS_PHY_797_DATA 0x00000808 #define DDRSS_PHY_798_DATA 0x0F000000 -#define DDRSS_PHY_799_DATA 0x00000F0F -#define DDRSS_PHY_800_DATA 0x10200000 -#define DDRSS_PHY_801_DATA 0x0C002007 +#define DDRSS_PHY_799_DATA 0x00000F08 +#define DDRSS_PHY_800_DATA 0x10400000 +#define DDRSS_PHY_801_DATA 0x0C002006 #define DDRSS_PHY_802_DATA 0x00000000 #define DDRSS_PHY_803_DATA 0x00000000 #define DDRSS_PHY_804_DATA 0x55555555 @@ -1639,20 +1647,20 @@ #define DDRSS_PHY_865_DATA 0x00050010 #define DDRSS_PHY_866_DATA 0x51517041 #define DDRSS_PHY_867_DATA 0x31C06000 -#define DDRSS_PHY_868_DATA 0x07AB0340 +#define DDRSS_PHY_868_DATA 0x07AB01AB #define DDRSS_PHY_869_DATA 0x00C0C001 -#define DDRSS_PHY_870_DATA 0x09080001 +#define DDRSS_PHY_870_DATA 0x0B0A0101 #define DDRSS_PHY_871_DATA 0x10001000 -#define DDRSS_PHY_872_DATA 0x0C063E42 -#define DDRSS_PHY_873_DATA 0x0F0C2701 +#define DDRSS_PHY_872_DATA 0x0C073E42 +#define DDRSS_PHY_873_DATA 0x0F0C2D01 #define DDRSS_PHY_874_DATA 0x01000140 -#define DDRSS_PHY_875_DATA 0x04000420 +#define DDRSS_PHY_875_DATA 0x0C000420 #define DDRSS_PHY_876_DATA 0x00000198 #define DDRSS_PHY_877_DATA 0x0A0000D0 #define DDRSS_PHY_878_DATA 0x00030200 #define DDRSS_PHY_879_DATA 0x02800000 #define DDRSS_PHY_880_DATA 0x80800000 -#define DDRSS_PHY_881_DATA 0x00092010 +#define DDRSS_PHY_881_DATA 0x000B2010 #define DDRSS_PHY_882_DATA 0x76543210 #define DDRSS_PHY_883_DATA 0x00000008 #define DDRSS_PHY_884_DATA 0x02800280 @@ -1669,8 +1677,8 @@ #define DDRSS_PHY_895_DATA 0x00A000A0 #define DDRSS_PHY_896_DATA 0x00A000A0 #define DDRSS_PHY_897_DATA 0x00A000A0 -#define DDRSS_PHY_898_DATA 0x01C400A0 -#define DDRSS_PHY_899_DATA 0x01A00003 +#define DDRSS_PHY_898_DATA 0x011900A0 +#define DDRSS_PHY_899_DATA 0x01A00004 #define DDRSS_PHY_900_DATA 0x00000000 #define DDRSS_PHY_901_DATA 0x00000000 #define DDRSS_PHY_902_DATA 0x00080200 @@ -1810,7 +1818,7 @@ #define DDRSS_PHY_1036_DATA 0x00000080 #define DDRSS_PHY_1037_DATA 0x00DCBA98 #define DDRSS_PHY_1038_DATA 0x03000000 -#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1039_DATA 0x00200001 #define DDRSS_PHY_1040_DATA 0x00000000 #define DDRSS_PHY_1041_DATA 0x00000000 #define DDRSS_PHY_1042_DATA 0x00000000 @@ -1826,7 +1834,7 @@ #define DDRSS_PHY_1052_DATA 0x00000033 #define DDRSS_PHY_1053_DATA 0x00543210 #define DDRSS_PHY_1054_DATA 0x003F0000 -#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1055_DATA 0x000F3F3F #define DDRSS_PHY_1056_DATA 0x20202003 #define DDRSS_PHY_1057_DATA 0x00202020 #define DDRSS_PHY_1058_DATA 0x20008008 @@ -1835,7 +1843,7 @@ #define DDRSS_PHY_1061_DATA 0x00000000 #define DDRSS_PHY_1062_DATA 0x00000000 #define DDRSS_PHY_1063_DATA 0x00000000 -#define DDRSS_PHY_1064_DATA 0x000205BB +#define DDRSS_PHY_1064_DATA 0x000305CC #define DDRSS_PHY_1065_DATA 0x00030000 #define DDRSS_PHY_1066_DATA 0x00000300 #define DDRSS_PHY_1067_DATA 0x00000300 @@ -1844,8 +1852,8 @@ #define DDRSS_PHY_1070_DATA 0x00000300 #define DDRSS_PHY_1071_DATA 0x42080010 #define DDRSS_PHY_1072_DATA 0x0000803E -#define DDRSS_PHY_1073_DATA 0x00000001 -#define DDRSS_PHY_1074_DATA 0x01000102 +#define DDRSS_PHY_1073_DATA 0x00000004 +#define DDRSS_PHY_1074_DATA 0x01000002 #define DDRSS_PHY_1075_DATA 0x00008000 #define DDRSS_PHY_1076_DATA 0x00000000 #define DDRSS_PHY_1077_DATA 0x00000000 @@ -2074,14 +2082,14 @@ #define DDRSS_PHY_1300_DATA 0x00040101 #define DDRSS_PHY_1301_DATA 0x0000010F #define DDRSS_PHY_1302_DATA 0x00000000 -#define DDRSS_PHY_1303_DATA 0x0000FFFF +#define DDRSS_PHY_1303_DATA 0x00000064 #define DDRSS_PHY_1304_DATA 0x00000000 #define DDRSS_PHY_1305_DATA 0x01010000 #define DDRSS_PHY_1306_DATA 0x01080402 #define DDRSS_PHY_1307_DATA 0x01200F02 #define DDRSS_PHY_1308_DATA 0x00194280 #define DDRSS_PHY_1309_DATA 0x00000004 -#define DDRSS_PHY_1310_DATA 0x00052000 +#define DDRSS_PHY_1310_DATA 0x00042000 #define DDRSS_PHY_1311_DATA 0x00000000 #define DDRSS_PHY_1312_DATA 0x00000000 #define DDRSS_PHY_1313_DATA 0x00000000 @@ -2165,10 +2173,10 @@ #define DDRSS_PHY_1391_DATA 0x00000000 #define DDRSS_PHY_1392_DATA 0x00000000 #define DDRSS_PHY_1393_DATA 0x0001F7C0 -#define DDRSS_PHY_1394_DATA 0x00000002 +#define DDRSS_PHY_1394_DATA 0x00000003 #define DDRSS_PHY_1395_DATA 0x00000000 #define DDRSS_PHY_1396_DATA 0x00001142 -#define DDRSS_PHY_1397_DATA 0x010207AB +#define DDRSS_PHY_1397_DATA 0x040207AB #define DDRSS_PHY_1398_DATA 0x01000080 #define DDRSS_PHY_1399_DATA 0x03900390 #define DDRSS_PHY_1400_DATA 0x03900390 @@ -2177,20 +2185,23 @@ #define DDRSS_PHY_1403_DATA 0x00000390 #define DDRSS_PHY_1404_DATA 0x00000390 #define DDRSS_PHY_1405_DATA 0x00000005 -#define DDRSS_PHY_1406_DATA 0x01813FBB -#define DDRSS_PHY_1407_DATA 0x000000BB +#define DDRSS_PHY_1406_DATA 0x01813FCC +#define DDRSS_PHY_1407_DATA 0x000000CC #define DDRSS_PHY_1408_DATA 0x0C000DFF #define DDRSS_PHY_1409_DATA 0x30000DFF #define DDRSS_PHY_1410_DATA 0x3F0DFF11 #define DDRSS_PHY_1411_DATA 0x000100F0 -#define DDRSS_PHY_1412_DATA 0x780DFFBB +#define DDRSS_PHY_1412_DATA 0x780DFFCC #define DDRSS_PHY_1413_DATA 0x00007E31 #define DDRSS_PHY_1414_DATA 0x000CBF11 -#define DDRSS_PHY_1415_DATA 0x01770010 +#define DDRSS_PHY_1415_DATA 0x01990010 #define DDRSS_PHY_1416_DATA 0x000CBF11 -#define DDRSS_PHY_1417_DATA 0x01770010 +#define DDRSS_PHY_1417_DATA 0x01990010 #define DDRSS_PHY_1418_DATA 0x3F0DFF11 -#define DDRSS_PHY_1419_DATA 0x017700F0 +#define DDRSS_PHY_1419_DATA 0x00EF00F0 #define DDRSS_PHY_1420_DATA 0x3F0DFF11 #define DDRSS_PHY_1421_DATA 0x01FF00F0 #define DDRSS_PHY_1422_DATA 0x20040006 + + + diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index b0e73fe72c4..8de96ad5c9e 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-j7200-common-proc-board.dts" -#include "k3-j7200-ddr-evm-lp4-2666.dtsi" +#include "k3-j7200-ddr-evm-lp4-3200.dtsi" #include "k3-j721e-ddr.dtsi" #include "k3-j7200-common-proc-board-u-boot.dtsi" #include "k3-j7200-r5.dtsi" diff --git a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi index c91576bf093..ecd42b1cf4d 100644 --- a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.7.0 - * This file was generated on 10/14/2021 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:46:29 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -16,6 +28,15 @@ #define MULTI_DDR_CFG_HYBRID_SELECT 0 #define MULTI_DDR_CFG_EMIFS_ACTIVE 3 +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000003 +#define DDR_REG1_SIZE_LSB 0x80000000 + + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -36,7 +57,7 @@ #define DDRSS0_CTL_17_DATA 0x00000005 #define DDRSS0_CTL_18_DATA 0x000010A9 #define DDRSS0_CTL_19_DATA 0x01010000 -#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_20_DATA 0x01011001 #define DDRSS0_CTL_21_DATA 0x02010000 #define DDRSS0_CTL_22_DATA 0x00020100 #define DDRSS0_CTL_23_DATA 0x0000000B @@ -51,7 +72,7 @@ #define DDRSS0_CTL_32_DATA 0x00000000 #define DDRSS0_CTL_33_DATA 0x00000000 #define DDRSS0_CTL_34_DATA 0x040C0000 -#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_35_DATA 0x12501250 #define DDRSS0_CTL_36_DATA 0x00050804 #define DDRSS0_CTL_37_DATA 0x09040008 #define DDRSS0_CTL_38_DATA 0x15000204 @@ -60,33 +81,33 @@ #define DDRSS0_CTL_41_DATA 0x1760008B #define DDRSS0_CTL_42_DATA 0x2000422B #define DDRSS0_CTL_43_DATA 0x000A0A09 -#define DDRSS0_CTL_44_DATA 0x0400078A +#define DDRSS0_CTL_44_DATA 0x040003C5 #define DDRSS0_CTL_45_DATA 0x1E161104 -#define DDRSS0_CTL_46_DATA 0x10012458 +#define DDRSS0_CTL_46_DATA 0x1000922C #define DDRSS0_CTL_47_DATA 0x1E161110 -#define DDRSS0_CTL_48_DATA 0x10012458 +#define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 -#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_50_DATA 0x2C060500 #define DDRSS0_CTL_51_DATA 0x08292C29 #define DDRSS0_CTL_52_DATA 0x14000E0A #define DDRSS0_CTL_53_DATA 0x04010A0A #define DDRSS0_CTL_54_DATA 0x01010004 -#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_55_DATA 0x0454540A #define DDRSS0_CTL_56_DATA 0x04313104 #define DDRSS0_CTL_57_DATA 0x00003131 #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x000000CE +#define DDRSS0_CTL_61_DATA 0x00000068 #define DDRSS0_CTL_62_DATA 0x0000032B -#define DDRSS0_CTL_63_DATA 0x00002073 +#define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B -#define DDRSS0_CTL_65_DATA 0x00002073 +#define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 -#define DDRSS0_CTL_68_DATA 0x00CB0012 -#define DDRSS0_CTL_69_DATA 0x00CB0408 -#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 #define DDRSS0_CTL_71_DATA 0x00120103 #define DDRSS0_CTL_72_DATA 0x00100005 #define DDRSS0_CTL_73_DATA 0x2F080010 @@ -118,27 +139,27 @@ #define DDRSS0_CTL_99_DATA 0x00000000 #define DDRSS0_CTL_100_DATA 0x00040005 #define DDRSS0_CTL_101_DATA 0x00000000 -#define DDRSS0_CTL_102_DATA 0x00003380 -#define DDRSS0_CTL_103_DATA 0x00003380 -#define DDRSS0_CTL_104_DATA 0x00003380 -#define DDRSS0_CTL_105_DATA 0x00003380 -#define DDRSS0_CTL_106_DATA 0x00003380 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 #define DDRSS0_CTL_107_DATA 0x00000000 -#define DDRSS0_CTL_108_DATA 0x000005A2 -#define DDRSS0_CTL_109_DATA 0x00081CC0 -#define DDRSS0_CTL_110_DATA 0x00081CC0 -#define DDRSS0_CTL_111_DATA 0x00081CC0 -#define DDRSS0_CTL_112_DATA 0x00081CC0 -#define DDRSS0_CTL_113_DATA 0x00081CC0 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 #define DDRSS0_CTL_114_DATA 0x00000000 -#define DDRSS0_CTL_115_DATA 0x0000E325 -#define DDRSS0_CTL_116_DATA 0x00081CC0 -#define DDRSS0_CTL_117_DATA 0x00081CC0 -#define DDRSS0_CTL_118_DATA 0x00081CC0 -#define DDRSS0_CTL_119_DATA 0x00081CC0 -#define DDRSS0_CTL_120_DATA 0x00081CC0 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 #define DDRSS0_CTL_121_DATA 0x00000000 -#define DDRSS0_CTL_122_DATA 0x0000E325 +#define DDRSS0_CTL_122_DATA 0x00007173 #define DDRSS0_CTL_123_DATA 0x00000000 #define DDRSS0_CTL_124_DATA 0x00000000 #define DDRSS0_CTL_125_DATA 0x00000000 @@ -192,22 +213,22 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 -#define DDRSS0_CTL_178_DATA 0x56000000 -#define DDRSS0_CTL_179_DATA 0x27270056 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 +#define DDRSS0_CTL_178_DATA 0x36000000 +#define DDRSS0_CTL_179_DATA 0x27270036 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 #define DDRSS0_CTL_185_DATA 0x00000000 -#define DDRSS0_CTL_186_DATA 0x00565600 +#define DDRSS0_CTL_186_DATA 0x00363600 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 #define DDRSS0_CTL_190_DATA 0x00000020 -#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_191_DATA 0x01000000 #define DDRSS0_CTL_192_DATA 0x00000001 #define DDRSS0_CTL_193_DATA 0x00000000 #define DDRSS0_CTL_194_DATA 0x01000000 @@ -245,17 +266,17 @@ #define DDRSS0_CTL_226_DATA 0x00000000 #define DDRSS0_CTL_227_DATA 0x15110000 #define DDRSS0_CTL_228_DATA 0x00040C18 -#define DDRSS0_CTL_229_DATA 0x00000000 -#define DDRSS0_CTL_230_DATA 0x00000000 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 #define DDRSS0_CTL_231_DATA 0x00000000 #define DDRSS0_CTL_232_DATA 0x00000000 -#define DDRSS0_CTL_233_DATA 0x00000000 -#define DDRSS0_CTL_234_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 #define DDRSS0_CTL_235_DATA 0x00000000 #define DDRSS0_CTL_236_DATA 0x00000000 #define DDRSS0_CTL_237_DATA 0x00000000 -#define DDRSS0_CTL_238_DATA 0x00000000 -#define DDRSS0_CTL_239_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 #define DDRSS0_CTL_240_DATA 0x00000000 #define DDRSS0_CTL_241_DATA 0x00000000 #define DDRSS0_CTL_242_DATA 0x00030000 @@ -283,7 +304,7 @@ #define DDRSS0_CTL_264_DATA 0x00000040 #define DDRSS0_CTL_265_DATA 0x006B0003 #define DDRSS0_CTL_266_DATA 0x0100006B -#define DDRSS0_CTL_267_DATA 0x00000000 +#define DDRSS0_CTL_267_DATA 0x03030303 #define DDRSS0_CTL_268_DATA 0x00000000 #define DDRSS0_CTL_269_DATA 0x00000202 #define DDRSS0_CTL_270_DATA 0x00001FFF @@ -307,14 +328,14 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00010101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 #define DDRSS0_CTL_295_DATA 0x00000000 #define DDRSS0_CTL_296_DATA 0x00000000 -#define DDRSS0_CTL_297_DATA 0x00000000 -#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF #define DDRSS0_CTL_299_DATA 0x00000000 #define DDRSS0_CTL_300_DATA 0x00000000 #define DDRSS0_CTL_301_DATA 0x00000000 @@ -335,7 +356,7 @@ #define DDRSS0_CTL_316_DATA 0x01010001 #define DDRSS0_CTL_317_DATA 0x00010101 #define DDRSS0_CTL_318_DATA 0x050A0A03 -#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_319_DATA 0x10082323 #define DDRSS0_CTL_320_DATA 0x00090310 #define DDRSS0_CTL_321_DATA 0x0B0C030F #define DDRSS0_CTL_322_DATA 0x0B0C0306 @@ -405,30 +426,30 @@ #define DDRSS0_CTL_386_DATA 0x00000000 #define DDRSS0_CTL_387_DATA 0x3A3A1B00 #define DDRSS0_CTL_388_DATA 0x000A0000 -#define DDRSS0_CTL_389_DATA 0x0000019C +#define DDRSS0_CTL_389_DATA 0x000000C6 #define DDRSS0_CTL_390_DATA 0x00000200 #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x000004D4 -#define DDRSS0_CTL_395_DATA 0x00001018 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 -#define DDRSS0_CTL_397_DATA 0x000040E6 +#define DDRSS0_CTL_397_DATA 0x0000206A #define DDRSS0_CTL_398_DATA 0x00000200 #define DDRSS0_CTL_399_DATA 0x00000200 #define DDRSS0_CTL_400_DATA 0x00000200 #define DDRSS0_CTL_401_DATA 0x00000200 -#define DDRSS0_CTL_402_DATA 0x0000C2B2 -#define DDRSS0_CTL_403_DATA 0x000288FC -#define DDRSS0_CTL_404_DATA 0x00000E15 -#define DDRSS0_CTL_405_DATA 0x000040E6 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 #define DDRSS0_CTL_408_DATA 0x00000200 #define DDRSS0_CTL_409_DATA 0x00000200 -#define DDRSS0_CTL_410_DATA 0x0000C2B2 -#define DDRSS0_CTL_411_DATA 0x000288FC -#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 #define DDRSS0_CTL_415_DATA 0x00000000 @@ -445,7 +466,7 @@ #define DDRSS0_CTL_426_DATA 0x00000000 #define DDRSS0_CTL_427_DATA 0x02000000 #define DDRSS0_CTL_428_DATA 0x01000404 -#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_429_DATA 0x0B220B22 #define DDRSS0_CTL_430_DATA 0x00000105 #define DDRSS0_CTL_431_DATA 0x00010101 #define DDRSS0_CTL_432_DATA 0x00010101 @@ -488,8 +509,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -537,18 +558,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 -#define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_66_DATA 0x01000100 +#define DDRSS0_PI_67_DATA 0x0102020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -637,37 +658,37 @@ #define DDRSS0_PI_158_DATA 0x00000000 #define DDRSS0_PI_159_DATA 0x00000401 #define DDRSS0_PI_160_DATA 0x00000000 -#define DDRSS0_PI_161_DATA 0x00010000 -#define DDRSS0_PI_162_DATA 0x00000000 -#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 #define DDRSS0_PI_164_DATA 0x00000034 -#define DDRSS0_PI_165_DATA 0x00000064 -#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 #define DDRSS0_PI_167_DATA 0x02000200 -#define DDRSS0_PI_168_DATA 0x48120C04 -#define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x000000CE +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 #define DDRSS0_PI_171_DATA 0x0000032B -#define DDRSS0_PI_172_DATA 0x00002073 +#define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B -#define DDRSS0_PI_174_DATA 0x04002073 +#define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 -#define DDRSS0_PI_185_DATA 0x15040000 -#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 #define DDRSS0_PI_187_DATA 0x00040402 #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -675,8 +696,8 @@ #define DDRSS0_PI_196_DATA 0x02170100 #define DDRSS0_PI_197_DATA 0x01000217 #define DDRSS0_PI_198_DATA 0x02170217 -#define DDRSS0_PI_199_DATA 0x32103200 -#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B #define DDRSS0_PI_201_DATA 0x0A070601 #define DDRSS0_PI_202_DATA 0x1F130A0D #define DDRSS0_PI_203_DATA 0x1F130A14 @@ -688,29 +709,29 @@ #define DDRSS0_PI_209_DATA 0x00240216 #define DDRSS0_PI_210_DATA 0x00110216 #define DDRSS0_PI_211_DATA 0x32000056 -#define DDRSS0_PI_212_DATA 0x00000301 -#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 -#define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 -#define DDRSS0_PI_218_DATA 0x04010504 -#define DDRSS0_PI_219_DATA 0x040006C9 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A #define DDRSS0_PI_222_DATA 0x00002918 -#define DDRSS0_PI_223_DATA 0x6001071C +#define DDRSS0_PI_223_DATA 0x6000838E #define DDRSS0_PI_224_DATA 0x1E202008 #define DDRSS0_PI_225_DATA 0x2C311116 #define DDRSS0_PI_226_DATA 0x00002918 -#define DDRSS0_PI_227_DATA 0x6001071C +#define DDRSS0_PI_227_DATA 0x6000838E #define DDRSS0_PI_228_DATA 0x1E202008 -#define DDRSS0_PI_229_DATA 0x00019C16 -#define DDRSS0_PI_230_DATA 0x00001018 -#define DDRSS0_PI_231_DATA 0x000040E6 -#define DDRSS0_PI_232_DATA 0x000288FC -#define DDRSS0_PI_233_DATA 0x000040E6 -#define DDRSS0_PI_234_DATA 0x000288FC +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 #define DDRSS0_PI_235_DATA 0x033B0016 #define DDRSS0_PI_236_DATA 0x0303033B #define DDRSS0_PI_237_DATA 0x002AF803 @@ -751,29 +772,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00F30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x56333FF4 +#define DDRSS0_PI_277_DATA 0x36F33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x56333FF4 +#define DDRSS0_PI_279_DATA 0x36F33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00F30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x56333FF4 +#define DDRSS0_PI_283_DATA 0x36F33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x56333FF4 +#define DDRSS0_PI_285_DATA 0x36F33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00F30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x56333FF4 +#define DDRSS0_PI_289_DATA 0x36F33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x56333FF4 +#define DDRSS0_PI_291_DATA 0x36F33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00F30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x56333FF4 +#define DDRSS0_PI_295_DATA 0x36F33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x56333FF4 +#define DDRSS0_PI_297_DATA 0x36F33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -789,7 +810,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -808,9 +829,9 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F -#define DDRSS0_PHY_32_DATA 0x10200000 -#define DDRSS0_PHY_33_DATA 0x0C002006 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002002 #define DDRSS0_PHY_34_DATA 0x00000000 #define DDRSS0_PHY_35_DATA 0x00000000 #define DDRSS0_PHY_36_DATA 0x55555555 @@ -877,9 +898,9 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 -#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 #define DDRSS0_PHY_103_DATA 0x10001000 #define DDRSS0_PHY_104_DATA 0x0C083E42 #define DDRSS0_PHY_105_DATA 0x0F0C3701 @@ -913,7 +934,7 @@ #define DDRSS0_PHY_133_DATA 0x00000000 #define DDRSS0_PHY_134_DATA 0x00080200 #define DDRSS0_PHY_135_DATA 0x00000000 -#define DDRSS0_PHY_136_DATA 0x20202000 +#define DDRSS0_PHY_136_DATA 0x20202020 #define DDRSS0_PHY_137_DATA 0x20202020 #define DDRSS0_PHY_138_DATA 0xF0F02020 #define DDRSS0_PHY_139_DATA 0x00000000 @@ -1045,7 +1066,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1064,9 +1085,9 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F -#define DDRSS0_PHY_288_DATA 0x10200000 -#define DDRSS0_PHY_289_DATA 0x0C002006 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002002 #define DDRSS0_PHY_290_DATA 0x00000000 #define DDRSS0_PHY_291_DATA 0x00000000 #define DDRSS0_PHY_292_DATA 0x55555555 @@ -1133,9 +1154,9 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 -#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 #define DDRSS0_PHY_359_DATA 0x10001000 #define DDRSS0_PHY_360_DATA 0x0C083E42 #define DDRSS0_PHY_361_DATA 0x0F0C3701 @@ -1169,7 +1190,7 @@ #define DDRSS0_PHY_389_DATA 0x00000000 #define DDRSS0_PHY_390_DATA 0x00080200 #define DDRSS0_PHY_391_DATA 0x00000000 -#define DDRSS0_PHY_392_DATA 0x20202000 +#define DDRSS0_PHY_392_DATA 0x20202020 #define DDRSS0_PHY_393_DATA 0x20202020 #define DDRSS0_PHY_394_DATA 0xF0F02020 #define DDRSS0_PHY_395_DATA 0x00000000 @@ -1301,7 +1322,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1320,9 +1341,9 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F -#define DDRSS0_PHY_544_DATA 0x10200000 -#define DDRSS0_PHY_545_DATA 0x0C002006 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002002 #define DDRSS0_PHY_546_DATA 0x00000000 #define DDRSS0_PHY_547_DATA 0x00000000 #define DDRSS0_PHY_548_DATA 0x55555555 @@ -1389,9 +1410,9 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 -#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 #define DDRSS0_PHY_615_DATA 0x10001000 #define DDRSS0_PHY_616_DATA 0x0C083E42 #define DDRSS0_PHY_617_DATA 0x0F0C3701 @@ -1425,7 +1446,7 @@ #define DDRSS0_PHY_645_DATA 0x00000000 #define DDRSS0_PHY_646_DATA 0x00080200 #define DDRSS0_PHY_647_DATA 0x00000000 -#define DDRSS0_PHY_648_DATA 0x20202000 +#define DDRSS0_PHY_648_DATA 0x20202020 #define DDRSS0_PHY_649_DATA 0x20202020 #define DDRSS0_PHY_650_DATA 0xF0F02020 #define DDRSS0_PHY_651_DATA 0x00000000 @@ -1557,7 +1578,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1576,9 +1597,9 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F -#define DDRSS0_PHY_800_DATA 0x10200000 -#define DDRSS0_PHY_801_DATA 0x0C002006 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002002 #define DDRSS0_PHY_802_DATA 0x00000000 #define DDRSS0_PHY_803_DATA 0x00000000 #define DDRSS0_PHY_804_DATA 0x55555555 @@ -1645,9 +1666,9 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 -#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 #define DDRSS0_PHY_871_DATA 0x10001000 #define DDRSS0_PHY_872_DATA 0x0C083E42 #define DDRSS0_PHY_873_DATA 0x0F0C3701 @@ -1681,7 +1702,7 @@ #define DDRSS0_PHY_901_DATA 0x00000000 #define DDRSS0_PHY_902_DATA 0x00080200 #define DDRSS0_PHY_903_DATA 0x00000000 -#define DDRSS0_PHY_904_DATA 0x20202000 +#define DDRSS0_PHY_904_DATA 0x20202020 #define DDRSS0_PHY_905_DATA 0x20202020 #define DDRSS0_PHY_906_DATA 0xF0F02020 #define DDRSS0_PHY_907_DATA 0x00000000 @@ -1832,7 +1853,7 @@ #define DDRSS0_PHY_1052_DATA 0x00000033 #define DDRSS0_PHY_1053_DATA 0x00543210 #define DDRSS0_PHY_1054_DATA 0x003F0000 -#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1055_DATA 0x000F3F3F #define DDRSS0_PHY_1056_DATA 0x20202003 #define DDRSS0_PHY_1057_DATA 0x00202020 #define DDRSS0_PHY_1058_DATA 0x20008008 @@ -2080,14 +2101,14 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 #define DDRSS0_PHY_1307_DATA 0x01200F02 #define DDRSS0_PHY_1308_DATA 0x00194280 #define DDRSS0_PHY_1309_DATA 0x00000004 -#define DDRSS0_PHY_1310_DATA 0x00052000 +#define DDRSS0_PHY_1310_DATA 0x00042000 #define DDRSS0_PHY_1311_DATA 0x00000000 #define DDRSS0_PHY_1312_DATA 0x00000000 #define DDRSS0_PHY_1313_DATA 0x00000000 @@ -2174,7 +2195,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2221,7 +2242,7 @@ #define DDRSS1_CTL_17_DATA 0x00000005 #define DDRSS1_CTL_18_DATA 0x000010A9 #define DDRSS1_CTL_19_DATA 0x01010000 -#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_20_DATA 0x01011001 #define DDRSS1_CTL_21_DATA 0x02010000 #define DDRSS1_CTL_22_DATA 0x00020100 #define DDRSS1_CTL_23_DATA 0x0000000B @@ -2236,7 +2257,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2245,33 +2266,33 @@ #define DDRSS1_CTL_41_DATA 0x1760008B #define DDRSS1_CTL_42_DATA 0x2000422B #define DDRSS1_CTL_43_DATA 0x000A0A09 -#define DDRSS1_CTL_44_DATA 0x0400078A +#define DDRSS1_CTL_44_DATA 0x040003C5 #define DDRSS1_CTL_45_DATA 0x1E161104 -#define DDRSS1_CTL_46_DATA 0x10012458 +#define DDRSS1_CTL_46_DATA 0x1000922C #define DDRSS1_CTL_47_DATA 0x1E161110 -#define DDRSS1_CTL_48_DATA 0x10012458 +#define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 -#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_50_DATA 0x2C060500 #define DDRSS1_CTL_51_DATA 0x08292C29 #define DDRSS1_CTL_52_DATA 0x14000E0A #define DDRSS1_CTL_53_DATA 0x04010A0A #define DDRSS1_CTL_54_DATA 0x01010004 -#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_55_DATA 0x0454540A #define DDRSS1_CTL_56_DATA 0x04313104 #define DDRSS1_CTL_57_DATA 0x00003131 #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x000000CE +#define DDRSS1_CTL_61_DATA 0x00000068 #define DDRSS1_CTL_62_DATA 0x0000032B -#define DDRSS1_CTL_63_DATA 0x00002073 +#define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B -#define DDRSS1_CTL_65_DATA 0x00002073 +#define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 -#define DDRSS1_CTL_68_DATA 0x00CB0012 -#define DDRSS1_CTL_69_DATA 0x00CB0408 -#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 #define DDRSS1_CTL_71_DATA 0x00120103 #define DDRSS1_CTL_72_DATA 0x00100005 #define DDRSS1_CTL_73_DATA 0x2F080010 @@ -2303,27 +2324,27 @@ #define DDRSS1_CTL_99_DATA 0x00000000 #define DDRSS1_CTL_100_DATA 0x00040005 #define DDRSS1_CTL_101_DATA 0x00000000 -#define DDRSS1_CTL_102_DATA 0x00003380 -#define DDRSS1_CTL_103_DATA 0x00003380 -#define DDRSS1_CTL_104_DATA 0x00003380 -#define DDRSS1_CTL_105_DATA 0x00003380 -#define DDRSS1_CTL_106_DATA 0x00003380 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 #define DDRSS1_CTL_107_DATA 0x00000000 -#define DDRSS1_CTL_108_DATA 0x000005A2 -#define DDRSS1_CTL_109_DATA 0x00081CC0 -#define DDRSS1_CTL_110_DATA 0x00081CC0 -#define DDRSS1_CTL_111_DATA 0x00081CC0 -#define DDRSS1_CTL_112_DATA 0x00081CC0 -#define DDRSS1_CTL_113_DATA 0x00081CC0 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 #define DDRSS1_CTL_114_DATA 0x00000000 -#define DDRSS1_CTL_115_DATA 0x0000E325 -#define DDRSS1_CTL_116_DATA 0x00081CC0 -#define DDRSS1_CTL_117_DATA 0x00081CC0 -#define DDRSS1_CTL_118_DATA 0x00081CC0 -#define DDRSS1_CTL_119_DATA 0x00081CC0 -#define DDRSS1_CTL_120_DATA 0x00081CC0 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 #define DDRSS1_CTL_121_DATA 0x00000000 -#define DDRSS1_CTL_122_DATA 0x0000E325 +#define DDRSS1_CTL_122_DATA 0x00007173 #define DDRSS1_CTL_123_DATA 0x00000000 #define DDRSS1_CTL_124_DATA 0x00000000 #define DDRSS1_CTL_125_DATA 0x00000000 @@ -2377,22 +2398,22 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 -#define DDRSS1_CTL_178_DATA 0x56000000 -#define DDRSS1_CTL_179_DATA 0x27270056 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x36000000 +#define DDRSS1_CTL_179_DATA 0x27270036 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 -#define DDRSS1_CTL_186_DATA 0x00565600 +#define DDRSS1_CTL_186_DATA 0x00363600 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 #define DDRSS1_CTL_190_DATA 0x00000020 -#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_191_DATA 0x01000000 #define DDRSS1_CTL_192_DATA 0x00000001 #define DDRSS1_CTL_193_DATA 0x00000000 #define DDRSS1_CTL_194_DATA 0x01000000 @@ -2430,17 +2451,17 @@ #define DDRSS1_CTL_226_DATA 0x00000000 #define DDRSS1_CTL_227_DATA 0x15110000 #define DDRSS1_CTL_228_DATA 0x00040C18 -#define DDRSS1_CTL_229_DATA 0x00000000 -#define DDRSS1_CTL_230_DATA 0x00000000 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 #define DDRSS1_CTL_231_DATA 0x00000000 #define DDRSS1_CTL_232_DATA 0x00000000 -#define DDRSS1_CTL_233_DATA 0x00000000 -#define DDRSS1_CTL_234_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 #define DDRSS1_CTL_235_DATA 0x00000000 #define DDRSS1_CTL_236_DATA 0x00000000 #define DDRSS1_CTL_237_DATA 0x00000000 -#define DDRSS1_CTL_238_DATA 0x00000000 -#define DDRSS1_CTL_239_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 #define DDRSS1_CTL_240_DATA 0x00000000 #define DDRSS1_CTL_241_DATA 0x00000000 #define DDRSS1_CTL_242_DATA 0x00030000 @@ -2468,7 +2489,7 @@ #define DDRSS1_CTL_264_DATA 0x00000040 #define DDRSS1_CTL_265_DATA 0x006B0003 #define DDRSS1_CTL_266_DATA 0x0100006B -#define DDRSS1_CTL_267_DATA 0x00000000 +#define DDRSS1_CTL_267_DATA 0x03030303 #define DDRSS1_CTL_268_DATA 0x00000000 #define DDRSS1_CTL_269_DATA 0x00000202 #define DDRSS1_CTL_270_DATA 0x00001FFF @@ -2492,14 +2513,14 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 #define DDRSS1_CTL_295_DATA 0x00000000 #define DDRSS1_CTL_296_DATA 0x00000000 -#define DDRSS1_CTL_297_DATA 0x00000000 -#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF #define DDRSS1_CTL_299_DATA 0x00000000 #define DDRSS1_CTL_300_DATA 0x00000000 #define DDRSS1_CTL_301_DATA 0x00000000 @@ -2520,7 +2541,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2590,30 +2611,30 @@ #define DDRSS1_CTL_386_DATA 0x00000000 #define DDRSS1_CTL_387_DATA 0x3A3A1B00 #define DDRSS1_CTL_388_DATA 0x000A0000 -#define DDRSS1_CTL_389_DATA 0x0000019C +#define DDRSS1_CTL_389_DATA 0x000000C6 #define DDRSS1_CTL_390_DATA 0x00000200 #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x000004D4 -#define DDRSS1_CTL_395_DATA 0x00001018 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 -#define DDRSS1_CTL_397_DATA 0x000040E6 +#define DDRSS1_CTL_397_DATA 0x0000206A #define DDRSS1_CTL_398_DATA 0x00000200 #define DDRSS1_CTL_399_DATA 0x00000200 #define DDRSS1_CTL_400_DATA 0x00000200 #define DDRSS1_CTL_401_DATA 0x00000200 -#define DDRSS1_CTL_402_DATA 0x0000C2B2 -#define DDRSS1_CTL_403_DATA 0x000288FC -#define DDRSS1_CTL_404_DATA 0x00000E15 -#define DDRSS1_CTL_405_DATA 0x000040E6 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 #define DDRSS1_CTL_408_DATA 0x00000200 #define DDRSS1_CTL_409_DATA 0x00000200 -#define DDRSS1_CTL_410_DATA 0x0000C2B2 -#define DDRSS1_CTL_411_DATA 0x000288FC -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2630,7 +2651,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2673,8 +2694,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2722,18 +2743,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2822,37 +2843,37 @@ #define DDRSS1_PI_158_DATA 0x00000000 #define DDRSS1_PI_159_DATA 0x00000401 #define DDRSS1_PI_160_DATA 0x00000000 -#define DDRSS1_PI_161_DATA 0x00010000 -#define DDRSS1_PI_162_DATA 0x00000000 -#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x000000CE +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 #define DDRSS1_PI_171_DATA 0x0000032B -#define DDRSS1_PI_172_DATA 0x00002073 +#define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B -#define DDRSS1_PI_174_DATA 0x04002073 +#define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2860,8 +2881,8 @@ #define DDRSS1_PI_196_DATA 0x02170100 #define DDRSS1_PI_197_DATA 0x01000217 #define DDRSS1_PI_198_DATA 0x02170217 -#define DDRSS1_PI_199_DATA 0x32103200 -#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B #define DDRSS1_PI_201_DATA 0x0A070601 #define DDRSS1_PI_202_DATA 0x1F130A0D #define DDRSS1_PI_203_DATA 0x1F130A14 @@ -2873,29 +2894,29 @@ #define DDRSS1_PI_209_DATA 0x00240216 #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 -#define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 -#define DDRSS1_PI_218_DATA 0x04010504 -#define DDRSS1_PI_219_DATA 0x040006C9 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A #define DDRSS1_PI_222_DATA 0x00002918 -#define DDRSS1_PI_223_DATA 0x6001071C +#define DDRSS1_PI_223_DATA 0x6000838E #define DDRSS1_PI_224_DATA 0x1E202008 #define DDRSS1_PI_225_DATA 0x2C311116 #define DDRSS1_PI_226_DATA 0x00002918 -#define DDRSS1_PI_227_DATA 0x6001071C +#define DDRSS1_PI_227_DATA 0x6000838E #define DDRSS1_PI_228_DATA 0x1E202008 -#define DDRSS1_PI_229_DATA 0x00019C16 -#define DDRSS1_PI_230_DATA 0x00001018 -#define DDRSS1_PI_231_DATA 0x000040E6 -#define DDRSS1_PI_232_DATA 0x000288FC -#define DDRSS1_PI_233_DATA 0x000040E6 -#define DDRSS1_PI_234_DATA 0x000288FC +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 #define DDRSS1_PI_235_DATA 0x033B0016 #define DDRSS1_PI_236_DATA 0x0303033B #define DDRSS1_PI_237_DATA 0x002AF803 @@ -2936,29 +2957,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x56333FF4 +#define DDRSS1_PI_277_DATA 0x36F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x56333FF4 +#define DDRSS1_PI_279_DATA 0x36F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x56333FF4 +#define DDRSS1_PI_283_DATA 0x36F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x56333FF4 +#define DDRSS1_PI_285_DATA 0x36F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x56333FF4 +#define DDRSS1_PI_289_DATA 0x36F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x56333FF4 +#define DDRSS1_PI_291_DATA 0x36F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x56333FF4 +#define DDRSS1_PI_295_DATA 0x36F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x56333FF4 +#define DDRSS1_PI_297_DATA 0x36F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2974,7 +2995,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2993,8 +3014,8 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F -#define DDRSS1_PHY_32_DATA 0x10200000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 #define DDRSS1_PHY_35_DATA 0x00000000 @@ -3062,9 +3083,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3098,7 +3119,7 @@ #define DDRSS1_PHY_133_DATA 0x00000000 #define DDRSS1_PHY_134_DATA 0x00080200 #define DDRSS1_PHY_135_DATA 0x00000000 -#define DDRSS1_PHY_136_DATA 0x20202000 +#define DDRSS1_PHY_136_DATA 0x20202020 #define DDRSS1_PHY_137_DATA 0x20202020 #define DDRSS1_PHY_138_DATA 0xF0F02020 #define DDRSS1_PHY_139_DATA 0x00000000 @@ -3230,7 +3251,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3249,8 +3270,8 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F -#define DDRSS1_PHY_288_DATA 0x10200000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 #define DDRSS1_PHY_291_DATA 0x00000000 @@ -3318,9 +3339,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3354,7 +3375,7 @@ #define DDRSS1_PHY_389_DATA 0x00000000 #define DDRSS1_PHY_390_DATA 0x00080200 #define DDRSS1_PHY_391_DATA 0x00000000 -#define DDRSS1_PHY_392_DATA 0x20202000 +#define DDRSS1_PHY_392_DATA 0x20202020 #define DDRSS1_PHY_393_DATA 0x20202020 #define DDRSS1_PHY_394_DATA 0xF0F02020 #define DDRSS1_PHY_395_DATA 0x00000000 @@ -3486,7 +3507,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3505,8 +3526,8 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F -#define DDRSS1_PHY_544_DATA 0x10200000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 #define DDRSS1_PHY_547_DATA 0x00000000 @@ -3574,9 +3595,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3610,7 +3631,7 @@ #define DDRSS1_PHY_645_DATA 0x00000000 #define DDRSS1_PHY_646_DATA 0x00080200 #define DDRSS1_PHY_647_DATA 0x00000000 -#define DDRSS1_PHY_648_DATA 0x20202000 +#define DDRSS1_PHY_648_DATA 0x20202020 #define DDRSS1_PHY_649_DATA 0x20202020 #define DDRSS1_PHY_650_DATA 0xF0F02020 #define DDRSS1_PHY_651_DATA 0x00000000 @@ -3742,7 +3763,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3761,8 +3782,8 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F -#define DDRSS1_PHY_800_DATA 0x10200000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 #define DDRSS1_PHY_803_DATA 0x00000000 @@ -3830,9 +3851,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -3866,7 +3887,7 @@ #define DDRSS1_PHY_901_DATA 0x00000000 #define DDRSS1_PHY_902_DATA 0x00080200 #define DDRSS1_PHY_903_DATA 0x00000000 -#define DDRSS1_PHY_904_DATA 0x20202000 +#define DDRSS1_PHY_904_DATA 0x20202020 #define DDRSS1_PHY_905_DATA 0x20202020 #define DDRSS1_PHY_906_DATA 0xF0F02020 #define DDRSS1_PHY_907_DATA 0x00000000 @@ -4017,7 +4038,7 @@ #define DDRSS1_PHY_1052_DATA 0x00000033 #define DDRSS1_PHY_1053_DATA 0x00543210 #define DDRSS1_PHY_1054_DATA 0x003F0000 -#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1055_DATA 0x000F3F3F #define DDRSS1_PHY_1056_DATA 0x20202003 #define DDRSS1_PHY_1057_DATA 0x00202020 #define DDRSS1_PHY_1058_DATA 0x20008008 @@ -4265,14 +4286,14 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 #define DDRSS1_PHY_1307_DATA 0x01200F02 #define DDRSS1_PHY_1308_DATA 0x00194280 #define DDRSS1_PHY_1309_DATA 0x00000004 -#define DDRSS1_PHY_1310_DATA 0x00052000 +#define DDRSS1_PHY_1310_DATA 0x00042000 #define DDRSS1_PHY_1311_DATA 0x00000000 #define DDRSS1_PHY_1312_DATA 0x00000000 #define DDRSS1_PHY_1313_DATA 0x00000000 @@ -4359,7 +4380,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4385,3 +4406,5 @@ #define DDRSS1_PHY_1420_DATA 0x3F0DFF11 #define DDRSS1_PHY_1421_DATA 0x01FF00F0 #define DDRSS1_PHY_1422_DATA 0x20040006 + + diff --git a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi index a64d19b05f3..2cd21efbf93 100644 --- a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi @@ -1,10 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 15:02:20 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -12,9 +25,18 @@ #define MULTI_DDR_CFG_INTRLV_GRAN 0 #define MULTI_DDR_CFG_INTRLV_SIZE 11 #define MULTI_DDR_CFG_ECC_ENABLE 0 -#define MULTI_DDR_CFG_HYBRID_SELECT 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 2 #define MULTI_DDR_CFG_EMIFS_ACTIVE 3 +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000003 +#define DDR_REG1_SIZE_LSB 0x80000000 + + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -35,7 +57,7 @@ #define DDRSS0_CTL_17_DATA 0x00000005 #define DDRSS0_CTL_18_DATA 0x000010A9 #define DDRSS0_CTL_19_DATA 0x01010000 -#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_20_DATA 0x01011001 #define DDRSS0_CTL_21_DATA 0x02010000 #define DDRSS0_CTL_22_DATA 0x00020100 #define DDRSS0_CTL_23_DATA 0x0000000B @@ -50,7 +72,7 @@ #define DDRSS0_CTL_32_DATA 0x00000000 #define DDRSS0_CTL_33_DATA 0x00000000 #define DDRSS0_CTL_34_DATA 0x040C0000 -#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_35_DATA 0x12501250 #define DDRSS0_CTL_36_DATA 0x00050804 #define DDRSS0_CTL_37_DATA 0x09040008 #define DDRSS0_CTL_38_DATA 0x15000204 @@ -59,33 +81,33 @@ #define DDRSS0_CTL_41_DATA 0x1760008B #define DDRSS0_CTL_42_DATA 0x2000422B #define DDRSS0_CTL_43_DATA 0x000A0A09 -#define DDRSS0_CTL_44_DATA 0x0400078A +#define DDRSS0_CTL_44_DATA 0x040003C5 #define DDRSS0_CTL_45_DATA 0x1E161104 -#define DDRSS0_CTL_46_DATA 0x10012458 +#define DDRSS0_CTL_46_DATA 0x1000922C #define DDRSS0_CTL_47_DATA 0x1E161110 -#define DDRSS0_CTL_48_DATA 0x10012458 +#define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 -#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_50_DATA 0x2C060500 #define DDRSS0_CTL_51_DATA 0x08292C29 #define DDRSS0_CTL_52_DATA 0x14000E0A #define DDRSS0_CTL_53_DATA 0x04010A0A #define DDRSS0_CTL_54_DATA 0x01010004 -#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_55_DATA 0x0454540A #define DDRSS0_CTL_56_DATA 0x04313104 #define DDRSS0_CTL_57_DATA 0x00003131 #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x000000CE +#define DDRSS0_CTL_61_DATA 0x00000068 #define DDRSS0_CTL_62_DATA 0x0000032B -#define DDRSS0_CTL_63_DATA 0x00002073 +#define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B -#define DDRSS0_CTL_65_DATA 0x00002073 +#define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 -#define DDRSS0_CTL_68_DATA 0x00CB0012 -#define DDRSS0_CTL_69_DATA 0x00CB0408 -#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 #define DDRSS0_CTL_71_DATA 0x00120103 #define DDRSS0_CTL_72_DATA 0x00100005 #define DDRSS0_CTL_73_DATA 0x2F080010 @@ -117,27 +139,27 @@ #define DDRSS0_CTL_99_DATA 0x00000000 #define DDRSS0_CTL_100_DATA 0x00040005 #define DDRSS0_CTL_101_DATA 0x00000000 -#define DDRSS0_CTL_102_DATA 0x00003380 -#define DDRSS0_CTL_103_DATA 0x00003380 -#define DDRSS0_CTL_104_DATA 0x00003380 -#define DDRSS0_CTL_105_DATA 0x00003380 -#define DDRSS0_CTL_106_DATA 0x00003380 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 #define DDRSS0_CTL_107_DATA 0x00000000 -#define DDRSS0_CTL_108_DATA 0x000005A2 -#define DDRSS0_CTL_109_DATA 0x00081CC0 -#define DDRSS0_CTL_110_DATA 0x00081CC0 -#define DDRSS0_CTL_111_DATA 0x00081CC0 -#define DDRSS0_CTL_112_DATA 0x00081CC0 -#define DDRSS0_CTL_113_DATA 0x00081CC0 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 #define DDRSS0_CTL_114_DATA 0x00000000 -#define DDRSS0_CTL_115_DATA 0x0000E325 -#define DDRSS0_CTL_116_DATA 0x00081CC0 -#define DDRSS0_CTL_117_DATA 0x00081CC0 -#define DDRSS0_CTL_118_DATA 0x00081CC0 -#define DDRSS0_CTL_119_DATA 0x00081CC0 -#define DDRSS0_CTL_120_DATA 0x00081CC0 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 #define DDRSS0_CTL_121_DATA 0x00000000 -#define DDRSS0_CTL_122_DATA 0x0000E325 +#define DDRSS0_CTL_122_DATA 0x00007173 #define DDRSS0_CTL_123_DATA 0x00000000 #define DDRSS0_CTL_124_DATA 0x00000000 #define DDRSS0_CTL_125_DATA 0x00000000 @@ -191,22 +213,22 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 #define DDRSS0_CTL_178_DATA 0x35000000 #define DDRSS0_CTL_179_DATA 0x27270035 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 #define DDRSS0_CTL_185_DATA 0x00000000 #define DDRSS0_CTL_186_DATA 0x00353500 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 #define DDRSS0_CTL_190_DATA 0x00000020 -#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_191_DATA 0x01000000 #define DDRSS0_CTL_192_DATA 0x00000001 #define DDRSS0_CTL_193_DATA 0x00000000 #define DDRSS0_CTL_194_DATA 0x01000000 @@ -306,14 +328,14 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00010101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 #define DDRSS0_CTL_295_DATA 0x00000000 #define DDRSS0_CTL_296_DATA 0x00000000 -#define DDRSS0_CTL_297_DATA 0x00000000 -#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF #define DDRSS0_CTL_299_DATA 0x00000000 #define DDRSS0_CTL_300_DATA 0x00000000 #define DDRSS0_CTL_301_DATA 0x00000000 @@ -334,7 +356,7 @@ #define DDRSS0_CTL_316_DATA 0x01010001 #define DDRSS0_CTL_317_DATA 0x00010101 #define DDRSS0_CTL_318_DATA 0x050A0A03 -#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_319_DATA 0x10082323 #define DDRSS0_CTL_320_DATA 0x00090310 #define DDRSS0_CTL_321_DATA 0x0B0C030F #define DDRSS0_CTL_322_DATA 0x0B0C0306 @@ -404,30 +426,30 @@ #define DDRSS0_CTL_386_DATA 0x00000000 #define DDRSS0_CTL_387_DATA 0x3A3A1B00 #define DDRSS0_CTL_388_DATA 0x000A0000 -#define DDRSS0_CTL_389_DATA 0x0000019C +#define DDRSS0_CTL_389_DATA 0x000000C6 #define DDRSS0_CTL_390_DATA 0x00000200 #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x000004D4 -#define DDRSS0_CTL_395_DATA 0x00001018 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 -#define DDRSS0_CTL_397_DATA 0x000040E6 +#define DDRSS0_CTL_397_DATA 0x0000206A #define DDRSS0_CTL_398_DATA 0x00000200 #define DDRSS0_CTL_399_DATA 0x00000200 #define DDRSS0_CTL_400_DATA 0x00000200 #define DDRSS0_CTL_401_DATA 0x00000200 -#define DDRSS0_CTL_402_DATA 0x0000C2B2 -#define DDRSS0_CTL_403_DATA 0x000288FC -#define DDRSS0_CTL_404_DATA 0x00000E15 -#define DDRSS0_CTL_405_DATA 0x000040E6 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 #define DDRSS0_CTL_408_DATA 0x00000200 #define DDRSS0_CTL_409_DATA 0x00000200 -#define DDRSS0_CTL_410_DATA 0x0000C2B2 -#define DDRSS0_CTL_411_DATA 0x000288FC -#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 #define DDRSS0_CTL_415_DATA 0x00000000 @@ -444,7 +466,7 @@ #define DDRSS0_CTL_426_DATA 0x00000000 #define DDRSS0_CTL_427_DATA 0x02000000 #define DDRSS0_CTL_428_DATA 0x01000404 -#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_429_DATA 0x0B220B22 #define DDRSS0_CTL_430_DATA 0x00000105 #define DDRSS0_CTL_431_DATA 0x00010101 #define DDRSS0_CTL_432_DATA 0x00010101 @@ -487,8 +509,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -536,18 +558,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 #define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_67_DATA 0x0002020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -636,37 +658,37 @@ #define DDRSS0_PI_158_DATA 0x00000000 #define DDRSS0_PI_159_DATA 0x00000401 #define DDRSS0_PI_160_DATA 0x00000000 -#define DDRSS0_PI_161_DATA 0x00010000 -#define DDRSS0_PI_162_DATA 0x00000000 -#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 #define DDRSS0_PI_164_DATA 0x00000034 -#define DDRSS0_PI_165_DATA 0x00000064 -#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 #define DDRSS0_PI_167_DATA 0x02000200 -#define DDRSS0_PI_168_DATA 0x48120C04 -#define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x000000CE +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 #define DDRSS0_PI_171_DATA 0x0000032B -#define DDRSS0_PI_172_DATA 0x00002073 +#define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B -#define DDRSS0_PI_174_DATA 0x04002073 +#define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 -#define DDRSS0_PI_185_DATA 0x15040000 -#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 #define DDRSS0_PI_187_DATA 0x00040402 #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -674,8 +696,8 @@ #define DDRSS0_PI_196_DATA 0x02170100 #define DDRSS0_PI_197_DATA 0x01000217 #define DDRSS0_PI_198_DATA 0x02170217 -#define DDRSS0_PI_199_DATA 0x32103200 -#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B #define DDRSS0_PI_201_DATA 0x0A070601 #define DDRSS0_PI_202_DATA 0x1F130A0D #define DDRSS0_PI_203_DATA 0x1F130A14 @@ -687,29 +709,29 @@ #define DDRSS0_PI_209_DATA 0x00240216 #define DDRSS0_PI_210_DATA 0x00110216 #define DDRSS0_PI_211_DATA 0x32000056 -#define DDRSS0_PI_212_DATA 0x00000301 -#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 -#define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 -#define DDRSS0_PI_218_DATA 0x04010504 -#define DDRSS0_PI_219_DATA 0x040006C9 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A #define DDRSS0_PI_222_DATA 0x00002918 -#define DDRSS0_PI_223_DATA 0x6001071C +#define DDRSS0_PI_223_DATA 0x6000838E #define DDRSS0_PI_224_DATA 0x1E202008 #define DDRSS0_PI_225_DATA 0x2C311116 #define DDRSS0_PI_226_DATA 0x00002918 -#define DDRSS0_PI_227_DATA 0x6001071C +#define DDRSS0_PI_227_DATA 0x6000838E #define DDRSS0_PI_228_DATA 0x1E202008 -#define DDRSS0_PI_229_DATA 0x00019C16 -#define DDRSS0_PI_230_DATA 0x00001018 -#define DDRSS0_PI_231_DATA 0x000040E6 -#define DDRSS0_PI_232_DATA 0x000288FC -#define DDRSS0_PI_233_DATA 0x000040E6 -#define DDRSS0_PI_234_DATA 0x000288FC +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 #define DDRSS0_PI_235_DATA 0x033B0016 #define DDRSS0_PI_236_DATA 0x0303033B #define DDRSS0_PI_237_DATA 0x002AF803 @@ -750,29 +772,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00F30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x35333FF4 +#define DDRSS0_PI_277_DATA 0x35F33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x35333FF4 +#define DDRSS0_PI_279_DATA 0x35F33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00F30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x35333FF4 +#define DDRSS0_PI_283_DATA 0x35F33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x35333FF4 +#define DDRSS0_PI_285_DATA 0x35F33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00F30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x35333FF4 +#define DDRSS0_PI_289_DATA 0x35F33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x35333FF4 +#define DDRSS0_PI_291_DATA 0x35F33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00F30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x35333FF4 +#define DDRSS0_PI_295_DATA 0x35F33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x35333FF4 +#define DDRSS0_PI_297_DATA 0x35F33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -788,7 +810,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -807,7 +829,7 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_31_DATA 0x00000F08 #define DDRSS0_PHY_32_DATA 0x10400000 #define DDRSS0_PHY_33_DATA 0x0C002006 #define DDRSS0_PHY_34_DATA 0x00000000 @@ -876,9 +898,9 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 -#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 #define DDRSS0_PHY_103_DATA 0x10001000 #define DDRSS0_PHY_104_DATA 0x0C083E42 #define DDRSS0_PHY_105_DATA 0x0F0C3701 @@ -1044,7 +1066,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1063,7 +1085,7 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_287_DATA 0x00000F08 #define DDRSS0_PHY_288_DATA 0x10400000 #define DDRSS0_PHY_289_DATA 0x0C002006 #define DDRSS0_PHY_290_DATA 0x00000000 @@ -1132,9 +1154,9 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 -#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 #define DDRSS0_PHY_359_DATA 0x10001000 #define DDRSS0_PHY_360_DATA 0x0C083E42 #define DDRSS0_PHY_361_DATA 0x0F0C3701 @@ -1300,7 +1322,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1319,7 +1341,7 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_543_DATA 0x00000F08 #define DDRSS0_PHY_544_DATA 0x10400000 #define DDRSS0_PHY_545_DATA 0x0C002006 #define DDRSS0_PHY_546_DATA 0x00000000 @@ -1388,9 +1410,9 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 -#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 #define DDRSS0_PHY_615_DATA 0x10001000 #define DDRSS0_PHY_616_DATA 0x0C083E42 #define DDRSS0_PHY_617_DATA 0x0F0C3701 @@ -1556,7 +1578,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1575,7 +1597,7 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_799_DATA 0x00000F08 #define DDRSS0_PHY_800_DATA 0x10400000 #define DDRSS0_PHY_801_DATA 0x0C002006 #define DDRSS0_PHY_802_DATA 0x00000000 @@ -1644,9 +1666,9 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 -#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 #define DDRSS0_PHY_871_DATA 0x10001000 #define DDRSS0_PHY_872_DATA 0x0C083E42 #define DDRSS0_PHY_873_DATA 0x0F0C3701 @@ -1831,7 +1853,7 @@ #define DDRSS0_PHY_1052_DATA 0x00000033 #define DDRSS0_PHY_1053_DATA 0x00543210 #define DDRSS0_PHY_1054_DATA 0x003F0000 -#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1055_DATA 0x000F3F3F #define DDRSS0_PHY_1056_DATA 0x20202003 #define DDRSS0_PHY_1057_DATA 0x00202020 #define DDRSS0_PHY_1058_DATA 0x20008008 @@ -2079,7 +2101,7 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 @@ -2173,7 +2195,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2220,7 +2242,7 @@ #define DDRSS1_CTL_17_DATA 0x00000005 #define DDRSS1_CTL_18_DATA 0x000010A9 #define DDRSS1_CTL_19_DATA 0x01010000 -#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_20_DATA 0x01011001 #define DDRSS1_CTL_21_DATA 0x02010000 #define DDRSS1_CTL_22_DATA 0x00020100 #define DDRSS1_CTL_23_DATA 0x0000000B @@ -2235,7 +2257,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2244,33 +2266,33 @@ #define DDRSS1_CTL_41_DATA 0x1760008B #define DDRSS1_CTL_42_DATA 0x2000422B #define DDRSS1_CTL_43_DATA 0x000A0A09 -#define DDRSS1_CTL_44_DATA 0x0400078A +#define DDRSS1_CTL_44_DATA 0x040003C5 #define DDRSS1_CTL_45_DATA 0x1E161104 -#define DDRSS1_CTL_46_DATA 0x10012458 +#define DDRSS1_CTL_46_DATA 0x1000922C #define DDRSS1_CTL_47_DATA 0x1E161110 -#define DDRSS1_CTL_48_DATA 0x10012458 +#define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 -#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_50_DATA 0x2C060500 #define DDRSS1_CTL_51_DATA 0x08292C29 #define DDRSS1_CTL_52_DATA 0x14000E0A #define DDRSS1_CTL_53_DATA 0x04010A0A #define DDRSS1_CTL_54_DATA 0x01010004 -#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_55_DATA 0x0454540A #define DDRSS1_CTL_56_DATA 0x04313104 #define DDRSS1_CTL_57_DATA 0x00003131 #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x000000CE +#define DDRSS1_CTL_61_DATA 0x00000068 #define DDRSS1_CTL_62_DATA 0x0000032B -#define DDRSS1_CTL_63_DATA 0x00002073 +#define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B -#define DDRSS1_CTL_65_DATA 0x00002073 +#define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 -#define DDRSS1_CTL_68_DATA 0x00CB0012 -#define DDRSS1_CTL_69_DATA 0x00CB0408 -#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 #define DDRSS1_CTL_71_DATA 0x00120103 #define DDRSS1_CTL_72_DATA 0x00100005 #define DDRSS1_CTL_73_DATA 0x2F080010 @@ -2302,27 +2324,27 @@ #define DDRSS1_CTL_99_DATA 0x00000000 #define DDRSS1_CTL_100_DATA 0x00040005 #define DDRSS1_CTL_101_DATA 0x00000000 -#define DDRSS1_CTL_102_DATA 0x00003380 -#define DDRSS1_CTL_103_DATA 0x00003380 -#define DDRSS1_CTL_104_DATA 0x00003380 -#define DDRSS1_CTL_105_DATA 0x00003380 -#define DDRSS1_CTL_106_DATA 0x00003380 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 #define DDRSS1_CTL_107_DATA 0x00000000 -#define DDRSS1_CTL_108_DATA 0x000005A2 -#define DDRSS1_CTL_109_DATA 0x00081CC0 -#define DDRSS1_CTL_110_DATA 0x00081CC0 -#define DDRSS1_CTL_111_DATA 0x00081CC0 -#define DDRSS1_CTL_112_DATA 0x00081CC0 -#define DDRSS1_CTL_113_DATA 0x00081CC0 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 #define DDRSS1_CTL_114_DATA 0x00000000 -#define DDRSS1_CTL_115_DATA 0x0000E325 -#define DDRSS1_CTL_116_DATA 0x00081CC0 -#define DDRSS1_CTL_117_DATA 0x00081CC0 -#define DDRSS1_CTL_118_DATA 0x00081CC0 -#define DDRSS1_CTL_119_DATA 0x00081CC0 -#define DDRSS1_CTL_120_DATA 0x00081CC0 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 #define DDRSS1_CTL_121_DATA 0x00000000 -#define DDRSS1_CTL_122_DATA 0x0000E325 +#define DDRSS1_CTL_122_DATA 0x00007173 #define DDRSS1_CTL_123_DATA 0x00000000 #define DDRSS1_CTL_124_DATA 0x00000000 #define DDRSS1_CTL_125_DATA 0x00000000 @@ -2376,22 +2398,22 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 #define DDRSS1_CTL_178_DATA 0x35000000 #define DDRSS1_CTL_179_DATA 0x27270035 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 #define DDRSS1_CTL_186_DATA 0x00353500 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 #define DDRSS1_CTL_190_DATA 0x00000020 -#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_191_DATA 0x01000000 #define DDRSS1_CTL_192_DATA 0x00000001 #define DDRSS1_CTL_193_DATA 0x00000000 #define DDRSS1_CTL_194_DATA 0x01000000 @@ -2491,14 +2513,14 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 #define DDRSS1_CTL_295_DATA 0x00000000 #define DDRSS1_CTL_296_DATA 0x00000000 -#define DDRSS1_CTL_297_DATA 0x00000000 -#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF #define DDRSS1_CTL_299_DATA 0x00000000 #define DDRSS1_CTL_300_DATA 0x00000000 #define DDRSS1_CTL_301_DATA 0x00000000 @@ -2519,7 +2541,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2589,30 +2611,30 @@ #define DDRSS1_CTL_386_DATA 0x00000000 #define DDRSS1_CTL_387_DATA 0x3A3A1B00 #define DDRSS1_CTL_388_DATA 0x000A0000 -#define DDRSS1_CTL_389_DATA 0x0000019C +#define DDRSS1_CTL_389_DATA 0x000000C6 #define DDRSS1_CTL_390_DATA 0x00000200 #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x000004D4 -#define DDRSS1_CTL_395_DATA 0x00001018 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 -#define DDRSS1_CTL_397_DATA 0x000040E6 +#define DDRSS1_CTL_397_DATA 0x0000206A #define DDRSS1_CTL_398_DATA 0x00000200 #define DDRSS1_CTL_399_DATA 0x00000200 #define DDRSS1_CTL_400_DATA 0x00000200 #define DDRSS1_CTL_401_DATA 0x00000200 -#define DDRSS1_CTL_402_DATA 0x0000C2B2 -#define DDRSS1_CTL_403_DATA 0x000288FC -#define DDRSS1_CTL_404_DATA 0x00000E15 -#define DDRSS1_CTL_405_DATA 0x000040E6 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 #define DDRSS1_CTL_408_DATA 0x00000200 #define DDRSS1_CTL_409_DATA 0x00000200 -#define DDRSS1_CTL_410_DATA 0x0000C2B2 -#define DDRSS1_CTL_411_DATA 0x000288FC -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2629,7 +2651,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2672,8 +2694,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2721,18 +2743,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2821,37 +2843,37 @@ #define DDRSS1_PI_158_DATA 0x00000000 #define DDRSS1_PI_159_DATA 0x00000401 #define DDRSS1_PI_160_DATA 0x00000000 -#define DDRSS1_PI_161_DATA 0x00010000 -#define DDRSS1_PI_162_DATA 0x00000000 -#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x000000CE +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 #define DDRSS1_PI_171_DATA 0x0000032B -#define DDRSS1_PI_172_DATA 0x00002073 +#define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B -#define DDRSS1_PI_174_DATA 0x04002073 +#define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2859,8 +2881,8 @@ #define DDRSS1_PI_196_DATA 0x02170100 #define DDRSS1_PI_197_DATA 0x01000217 #define DDRSS1_PI_198_DATA 0x02170217 -#define DDRSS1_PI_199_DATA 0x32103200 -#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B #define DDRSS1_PI_201_DATA 0x0A070601 #define DDRSS1_PI_202_DATA 0x1F130A0D #define DDRSS1_PI_203_DATA 0x1F130A14 @@ -2872,29 +2894,29 @@ #define DDRSS1_PI_209_DATA 0x00240216 #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 -#define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 -#define DDRSS1_PI_218_DATA 0x04010504 -#define DDRSS1_PI_219_DATA 0x040006C9 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A #define DDRSS1_PI_222_DATA 0x00002918 -#define DDRSS1_PI_223_DATA 0x6001071C +#define DDRSS1_PI_223_DATA 0x6000838E #define DDRSS1_PI_224_DATA 0x1E202008 #define DDRSS1_PI_225_DATA 0x2C311116 #define DDRSS1_PI_226_DATA 0x00002918 -#define DDRSS1_PI_227_DATA 0x6001071C +#define DDRSS1_PI_227_DATA 0x6000838E #define DDRSS1_PI_228_DATA 0x1E202008 -#define DDRSS1_PI_229_DATA 0x00019C16 -#define DDRSS1_PI_230_DATA 0x00001018 -#define DDRSS1_PI_231_DATA 0x000040E6 -#define DDRSS1_PI_232_DATA 0x000288FC -#define DDRSS1_PI_233_DATA 0x000040E6 -#define DDRSS1_PI_234_DATA 0x000288FC +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 #define DDRSS1_PI_235_DATA 0x033B0016 #define DDRSS1_PI_236_DATA 0x0303033B #define DDRSS1_PI_237_DATA 0x002AF803 @@ -2935,29 +2957,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x35333FF4 +#define DDRSS1_PI_277_DATA 0x35F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x35333FF4 +#define DDRSS1_PI_279_DATA 0x35F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x35333FF4 +#define DDRSS1_PI_283_DATA 0x35F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x35333FF4 +#define DDRSS1_PI_285_DATA 0x35F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x35333FF4 +#define DDRSS1_PI_289_DATA 0x35F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x35333FF4 +#define DDRSS1_PI_291_DATA 0x35F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x35333FF4 +#define DDRSS1_PI_295_DATA 0x35F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x35333FF4 +#define DDRSS1_PI_297_DATA 0x35F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2973,7 +2995,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2992,7 +3014,7 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_31_DATA 0x00000F08 #define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 @@ -3061,9 +3083,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3229,7 +3251,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3248,7 +3270,7 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_287_DATA 0x00000F08 #define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 @@ -3317,9 +3339,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3485,7 +3507,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3504,7 +3526,7 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_543_DATA 0x00000F08 #define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 @@ -3573,9 +3595,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3741,7 +3763,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3760,7 +3782,7 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_799_DATA 0x00000F08 #define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 @@ -3829,9 +3851,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -4016,7 +4038,7 @@ #define DDRSS1_PHY_1052_DATA 0x00000033 #define DDRSS1_PHY_1053_DATA 0x00543210 #define DDRSS1_PHY_1054_DATA 0x003F0000 -#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1055_DATA 0x000F3F3F #define DDRSS1_PHY_1056_DATA 0x20202003 #define DDRSS1_PHY_1057_DATA 0x00202020 #define DDRSS1_PHY_1058_DATA 0x20008008 @@ -4264,7 +4286,7 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 @@ -4358,7 +4380,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4385,4372 +4407,4 @@ #define DDRSS1_PHY_1421_DATA 0x01FF00F0 #define DDRSS1_PHY_1422_DATA 0x20040006 -#define DDRSS2_CTL_00_DATA 0x00000B00 -#define DDRSS2_CTL_01_DATA 0x00000000 -#define DDRSS2_CTL_02_DATA 0x00000000 -#define DDRSS2_CTL_03_DATA 0x00000000 -#define DDRSS2_CTL_04_DATA 0x00000000 -#define DDRSS2_CTL_05_DATA 0x00000000 -#define DDRSS2_CTL_06_DATA 0x00000000 -#define DDRSS2_CTL_07_DATA 0x00002AF8 -#define DDRSS2_CTL_08_DATA 0x0001ADAF -#define DDRSS2_CTL_09_DATA 0x00000005 -#define DDRSS2_CTL_10_DATA 0x0000006E -#define DDRSS2_CTL_11_DATA 0x000681C8 -#define DDRSS2_CTL_12_DATA 0x004111C9 -#define DDRSS2_CTL_13_DATA 0x00000005 -#define DDRSS2_CTL_14_DATA 0x000010A9 -#define DDRSS2_CTL_15_DATA 0x000681C8 -#define DDRSS2_CTL_16_DATA 0x004111C9 -#define DDRSS2_CTL_17_DATA 0x00000005 -#define DDRSS2_CTL_18_DATA 0x000010A9 -#define DDRSS2_CTL_19_DATA 0x01010000 -#define DDRSS2_CTL_20_DATA 0x02011001 -#define DDRSS2_CTL_21_DATA 0x02010000 -#define DDRSS2_CTL_22_DATA 0x00020100 -#define DDRSS2_CTL_23_DATA 0x0000000B -#define DDRSS2_CTL_24_DATA 0x0000001C -#define DDRSS2_CTL_25_DATA 0x00000000 -#define DDRSS2_CTL_26_DATA 0x00000000 -#define DDRSS2_CTL_27_DATA 0x03020200 -#define DDRSS2_CTL_28_DATA 0x00005656 -#define DDRSS2_CTL_29_DATA 0x00100000 -#define DDRSS2_CTL_30_DATA 0x00000000 -#define DDRSS2_CTL_31_DATA 0x00000000 -#define DDRSS2_CTL_32_DATA 0x00000000 -#define DDRSS2_CTL_33_DATA 0x00000000 -#define DDRSS2_CTL_34_DATA 0x040C0000 -#define DDRSS2_CTL_35_DATA 0x12481248 -#define DDRSS2_CTL_36_DATA 0x00050804 -#define DDRSS2_CTL_37_DATA 0x09040008 -#define DDRSS2_CTL_38_DATA 0x15000204 -#define DDRSS2_CTL_39_DATA 0x1760008B -#define DDRSS2_CTL_40_DATA 0x1500422B -#define DDRSS2_CTL_41_DATA 0x1760008B -#define DDRSS2_CTL_42_DATA 0x2000422B -#define DDRSS2_CTL_43_DATA 0x000A0A09 -#define DDRSS2_CTL_44_DATA 0x0400078A -#define DDRSS2_CTL_45_DATA 0x1E161104 -#define DDRSS2_CTL_46_DATA 0x10012458 -#define DDRSS2_CTL_47_DATA 0x1E161110 -#define DDRSS2_CTL_48_DATA 0x10012458 -#define DDRSS2_CTL_49_DATA 0x02030410 -#define DDRSS2_CTL_50_DATA 0x2C040500 -#define DDRSS2_CTL_51_DATA 0x08292C29 -#define DDRSS2_CTL_52_DATA 0x14000E0A -#define DDRSS2_CTL_53_DATA 0x04010A0A -#define DDRSS2_CTL_54_DATA 0x01010004 -#define DDRSS2_CTL_55_DATA 0x04545408 -#define DDRSS2_CTL_56_DATA 0x04313104 -#define DDRSS2_CTL_57_DATA 0x00003131 -#define DDRSS2_CTL_58_DATA 0x00010100 -#define DDRSS2_CTL_59_DATA 0x03010000 -#define DDRSS2_CTL_60_DATA 0x00001508 -#define DDRSS2_CTL_61_DATA 0x000000CE -#define DDRSS2_CTL_62_DATA 0x0000032B -#define DDRSS2_CTL_63_DATA 0x00002073 -#define DDRSS2_CTL_64_DATA 0x0000032B -#define DDRSS2_CTL_65_DATA 0x00002073 -#define DDRSS2_CTL_66_DATA 0x00000005 -#define DDRSS2_CTL_67_DATA 0x00050000 -#define DDRSS2_CTL_68_DATA 0x00CB0012 -#define DDRSS2_CTL_69_DATA 0x00CB0408 -#define DDRSS2_CTL_70_DATA 0x00400408 -#define DDRSS2_CTL_71_DATA 0x00120103 -#define DDRSS2_CTL_72_DATA 0x00100005 -#define DDRSS2_CTL_73_DATA 0x2F080010 -#define DDRSS2_CTL_74_DATA 0x0505012F -#define DDRSS2_CTL_75_DATA 0x0401030A -#define DDRSS2_CTL_76_DATA 0x041E100B -#define DDRSS2_CTL_77_DATA 0x100B0401 -#define DDRSS2_CTL_78_DATA 0x0001041E -#define DDRSS2_CTL_79_DATA 0x00160016 -#define DDRSS2_CTL_80_DATA 0x033B033B -#define DDRSS2_CTL_81_DATA 0x033B033B -#define DDRSS2_CTL_82_DATA 0x03050505 -#define DDRSS2_CTL_83_DATA 0x03010303 -#define DDRSS2_CTL_84_DATA 0x200B100B -#define DDRSS2_CTL_85_DATA 0x04041004 -#define DDRSS2_CTL_86_DATA 0x200B100B -#define DDRSS2_CTL_87_DATA 0x04041004 -#define DDRSS2_CTL_88_DATA 0x03010000 -#define DDRSS2_CTL_89_DATA 0x00010000 -#define DDRSS2_CTL_90_DATA 0x00000000 -#define DDRSS2_CTL_91_DATA 0x00000000 -#define DDRSS2_CTL_92_DATA 0x01000000 -#define DDRSS2_CTL_93_DATA 0x80104002 -#define DDRSS2_CTL_94_DATA 0x00000000 -#define DDRSS2_CTL_95_DATA 0x00040005 -#define DDRSS2_CTL_96_DATA 0x00000000 -#define DDRSS2_CTL_97_DATA 0x00050000 -#define DDRSS2_CTL_98_DATA 0x00000004 -#define DDRSS2_CTL_99_DATA 0x00000000 -#define DDRSS2_CTL_100_DATA 0x00040005 -#define DDRSS2_CTL_101_DATA 0x00000000 -#define DDRSS2_CTL_102_DATA 0x00003380 -#define DDRSS2_CTL_103_DATA 0x00003380 -#define DDRSS2_CTL_104_DATA 0x00003380 -#define DDRSS2_CTL_105_DATA 0x00003380 -#define DDRSS2_CTL_106_DATA 0x00003380 -#define DDRSS2_CTL_107_DATA 0x00000000 -#define DDRSS2_CTL_108_DATA 0x000005A2 -#define DDRSS2_CTL_109_DATA 0x00081CC0 -#define DDRSS2_CTL_110_DATA 0x00081CC0 -#define DDRSS2_CTL_111_DATA 0x00081CC0 -#define DDRSS2_CTL_112_DATA 0x00081CC0 -#define DDRSS2_CTL_113_DATA 0x00081CC0 -#define DDRSS2_CTL_114_DATA 0x00000000 -#define DDRSS2_CTL_115_DATA 0x0000E325 -#define DDRSS2_CTL_116_DATA 0x00081CC0 -#define DDRSS2_CTL_117_DATA 0x00081CC0 -#define DDRSS2_CTL_118_DATA 0x00081CC0 -#define DDRSS2_CTL_119_DATA 0x00081CC0 -#define DDRSS2_CTL_120_DATA 0x00081CC0 -#define DDRSS2_CTL_121_DATA 0x00000000 -#define DDRSS2_CTL_122_DATA 0x0000E325 -#define DDRSS2_CTL_123_DATA 0x00000000 -#define DDRSS2_CTL_124_DATA 0x00000000 -#define DDRSS2_CTL_125_DATA 0x00000000 -#define DDRSS2_CTL_126_DATA 0x00000000 -#define DDRSS2_CTL_127_DATA 0x00000000 -#define DDRSS2_CTL_128_DATA 0x00000000 -#define DDRSS2_CTL_129_DATA 0x00000000 -#define DDRSS2_CTL_130_DATA 0x00000000 -#define DDRSS2_CTL_131_DATA 0x0B030500 -#define DDRSS2_CTL_132_DATA 0x00040B04 -#define DDRSS2_CTL_133_DATA 0x0A090000 -#define DDRSS2_CTL_134_DATA 0x0A090701 -#define DDRSS2_CTL_135_DATA 0x0900000E -#define DDRSS2_CTL_136_DATA 0x0907010A -#define DDRSS2_CTL_137_DATA 0x00000E0A -#define DDRSS2_CTL_138_DATA 0x07010A09 -#define DDRSS2_CTL_139_DATA 0x000E0A09 -#define DDRSS2_CTL_140_DATA 0x07000401 -#define DDRSS2_CTL_141_DATA 0x00000000 -#define DDRSS2_CTL_142_DATA 0x00000000 -#define DDRSS2_CTL_143_DATA 0x00000000 -#define DDRSS2_CTL_144_DATA 0x00000000 -#define DDRSS2_CTL_145_DATA 0x00000000 -#define DDRSS2_CTL_146_DATA 0x00000000 -#define DDRSS2_CTL_147_DATA 0x00000000 -#define DDRSS2_CTL_148_DATA 0x08080000 -#define DDRSS2_CTL_149_DATA 0x01000000 -#define DDRSS2_CTL_150_DATA 0x800000C0 -#define DDRSS2_CTL_151_DATA 0x800000C0 -#define DDRSS2_CTL_152_DATA 0x800000C0 -#define DDRSS2_CTL_153_DATA 0x00000000 -#define DDRSS2_CTL_154_DATA 0x00001500 -#define DDRSS2_CTL_155_DATA 0x00000000 -#define DDRSS2_CTL_156_DATA 0x00000001 -#define DDRSS2_CTL_157_DATA 0x00000002 -#define DDRSS2_CTL_158_DATA 0x0000100E -#define DDRSS2_CTL_159_DATA 0x00000000 -#define DDRSS2_CTL_160_DATA 0x00000000 -#define DDRSS2_CTL_161_DATA 0x00000000 -#define DDRSS2_CTL_162_DATA 0x00000000 -#define DDRSS2_CTL_163_DATA 0x00000000 -#define DDRSS2_CTL_164_DATA 0x000B0000 -#define DDRSS2_CTL_165_DATA 0x000E0006 -#define DDRSS2_CTL_166_DATA 0x000E0404 -#define DDRSS2_CTL_167_DATA 0x00D601AB -#define DDRSS2_CTL_168_DATA 0x10100216 -#define DDRSS2_CTL_169_DATA 0x01AB0216 -#define DDRSS2_CTL_170_DATA 0x021600D6 -#define DDRSS2_CTL_171_DATA 0x02161010 -#define DDRSS2_CTL_172_DATA 0x00000000 -#define DDRSS2_CTL_173_DATA 0x00000000 -#define DDRSS2_CTL_174_DATA 0x00000000 -#define DDRSS2_CTL_175_DATA 0x3FF40084 -#define DDRSS2_CTL_176_DATA 0x33003FF4 -#define DDRSS2_CTL_177_DATA 0x00003333 -#define DDRSS2_CTL_178_DATA 0x35000000 -#define DDRSS2_CTL_179_DATA 0x27270035 -#define DDRSS2_CTL_180_DATA 0x0F0F0000 -#define DDRSS2_CTL_181_DATA 0x16000000 -#define DDRSS2_CTL_182_DATA 0x00841616 -#define DDRSS2_CTL_183_DATA 0x3FF43FF4 -#define DDRSS2_CTL_184_DATA 0x33333300 -#define DDRSS2_CTL_185_DATA 0x00000000 -#define DDRSS2_CTL_186_DATA 0x00353500 -#define DDRSS2_CTL_187_DATA 0x00002727 -#define DDRSS2_CTL_188_DATA 0x00000F0F -#define DDRSS2_CTL_189_DATA 0x16161600 -#define DDRSS2_CTL_190_DATA 0x00000020 -#define DDRSS2_CTL_191_DATA 0x00000000 -#define DDRSS2_CTL_192_DATA 0x00000001 -#define DDRSS2_CTL_193_DATA 0x00000000 -#define DDRSS2_CTL_194_DATA 0x01000000 -#define DDRSS2_CTL_195_DATA 0x00000001 -#define DDRSS2_CTL_196_DATA 0x00000000 -#define DDRSS2_CTL_197_DATA 0x00000000 -#define DDRSS2_CTL_198_DATA 0x00000000 -#define DDRSS2_CTL_199_DATA 0x00000000 -#define DDRSS2_CTL_200_DATA 0x00000000 -#define DDRSS2_CTL_201_DATA 0x00000000 -#define DDRSS2_CTL_202_DATA 0x00000000 -#define DDRSS2_CTL_203_DATA 0x00000000 -#define DDRSS2_CTL_204_DATA 0x00000000 -#define DDRSS2_CTL_205_DATA 0x00000000 -#define DDRSS2_CTL_206_DATA 0x02000000 -#define DDRSS2_CTL_207_DATA 0x01080101 -#define DDRSS2_CTL_208_DATA 0x00000000 -#define DDRSS2_CTL_209_DATA 0x00000000 -#define DDRSS2_CTL_210_DATA 0x00000000 -#define DDRSS2_CTL_211_DATA 0x00000000 -#define DDRSS2_CTL_212_DATA 0x00000000 -#define DDRSS2_CTL_213_DATA 0x00000000 -#define DDRSS2_CTL_214_DATA 0x00000000 -#define DDRSS2_CTL_215_DATA 0x00000000 -#define DDRSS2_CTL_216_DATA 0x00000000 -#define DDRSS2_CTL_217_DATA 0x00000000 -#define DDRSS2_CTL_218_DATA 0x00000000 -#define DDRSS2_CTL_219_DATA 0x00000000 -#define DDRSS2_CTL_220_DATA 0x00000000 -#define DDRSS2_CTL_221_DATA 0x00000000 -#define DDRSS2_CTL_222_DATA 0x00001000 -#define DDRSS2_CTL_223_DATA 0x006403E8 -#define DDRSS2_CTL_224_DATA 0x00000000 -#define DDRSS2_CTL_225_DATA 0x00000000 -#define DDRSS2_CTL_226_DATA 0x00000000 -#define DDRSS2_CTL_227_DATA 0x15110000 -#define DDRSS2_CTL_228_DATA 0x00040C18 -#define DDRSS2_CTL_229_DATA 0xF000C000 -#define DDRSS2_CTL_230_DATA 0x0000F000 -#define DDRSS2_CTL_231_DATA 0x00000000 -#define DDRSS2_CTL_232_DATA 0x00000000 -#define DDRSS2_CTL_233_DATA 0xC0000000 -#define DDRSS2_CTL_234_DATA 0xF000F000 -#define DDRSS2_CTL_235_DATA 0x00000000 -#define DDRSS2_CTL_236_DATA 0x00000000 -#define DDRSS2_CTL_237_DATA 0x00000000 -#define DDRSS2_CTL_238_DATA 0xF000C000 -#define DDRSS2_CTL_239_DATA 0x0000F000 -#define DDRSS2_CTL_240_DATA 0x00000000 -#define DDRSS2_CTL_241_DATA 0x00000000 -#define DDRSS2_CTL_242_DATA 0x00030000 -#define DDRSS2_CTL_243_DATA 0x00000000 -#define DDRSS2_CTL_244_DATA 0x00000000 -#define DDRSS2_CTL_245_DATA 0x00000000 -#define DDRSS2_CTL_246_DATA 0x00000000 -#define DDRSS2_CTL_247_DATA 0x00000000 -#define DDRSS2_CTL_248_DATA 0x00000000 -#define DDRSS2_CTL_249_DATA 0x00000000 -#define DDRSS2_CTL_250_DATA 0x00000000 -#define DDRSS2_CTL_251_DATA 0x00000000 -#define DDRSS2_CTL_252_DATA 0x00000000 -#define DDRSS2_CTL_253_DATA 0x00000000 -#define DDRSS2_CTL_254_DATA 0x00000000 -#define DDRSS2_CTL_255_DATA 0x00000000 -#define DDRSS2_CTL_256_DATA 0x00000000 -#define DDRSS2_CTL_257_DATA 0x01000200 -#define DDRSS2_CTL_258_DATA 0x00370040 -#define DDRSS2_CTL_259_DATA 0x00020008 -#define DDRSS2_CTL_260_DATA 0x00400100 -#define DDRSS2_CTL_261_DATA 0x00400855 -#define DDRSS2_CTL_262_DATA 0x01000200 -#define DDRSS2_CTL_263_DATA 0x08550040 -#define DDRSS2_CTL_264_DATA 0x00000040 -#define DDRSS2_CTL_265_DATA 0x006B0003 -#define DDRSS2_CTL_266_DATA 0x0100006B -#define DDRSS2_CTL_267_DATA 0x03030303 -#define DDRSS2_CTL_268_DATA 0x00000000 -#define DDRSS2_CTL_269_DATA 0x00000202 -#define DDRSS2_CTL_270_DATA 0x00001FFF -#define DDRSS2_CTL_271_DATA 0x3FFF2000 -#define DDRSS2_CTL_272_DATA 0x03FF0000 -#define DDRSS2_CTL_273_DATA 0x000103FF -#define DDRSS2_CTL_274_DATA 0x0FFF0B00 -#define DDRSS2_CTL_275_DATA 0x01010001 -#define DDRSS2_CTL_276_DATA 0x01010101 -#define DDRSS2_CTL_277_DATA 0x01180101 -#define DDRSS2_CTL_278_DATA 0x00030000 -#define DDRSS2_CTL_279_DATA 0x00000000 -#define DDRSS2_CTL_280_DATA 0x00000000 -#define DDRSS2_CTL_281_DATA 0x00000000 -#define DDRSS2_CTL_282_DATA 0x00000000 -#define DDRSS2_CTL_283_DATA 0x00000000 -#define DDRSS2_CTL_284_DATA 0x00000000 -#define DDRSS2_CTL_285_DATA 0x00000000 -#define DDRSS2_CTL_286_DATA 0x00040101 -#define DDRSS2_CTL_287_DATA 0x04010100 -#define DDRSS2_CTL_288_DATA 0x00000000 -#define DDRSS2_CTL_289_DATA 0x00000000 -#define DDRSS2_CTL_290_DATA 0x03030300 -#define DDRSS2_CTL_291_DATA 0x00000001 -#define DDRSS2_CTL_292_DATA 0x00000000 -#define DDRSS2_CTL_293_DATA 0x00000000 -#define DDRSS2_CTL_294_DATA 0x00000000 -#define DDRSS2_CTL_295_DATA 0x00000000 -#define DDRSS2_CTL_296_DATA 0x00000000 -#define DDRSS2_CTL_297_DATA 0x00000000 -#define DDRSS2_CTL_298_DATA 0x00000000 -#define DDRSS2_CTL_299_DATA 0x00000000 -#define DDRSS2_CTL_300_DATA 0x00000000 -#define DDRSS2_CTL_301_DATA 0x00000000 -#define DDRSS2_CTL_302_DATA 0x00000000 -#define DDRSS2_CTL_303_DATA 0x00000000 -#define DDRSS2_CTL_304_DATA 0x00000000 -#define DDRSS2_CTL_305_DATA 0x00000000 -#define DDRSS2_CTL_306_DATA 0x00000000 -#define DDRSS2_CTL_307_DATA 0x00000000 -#define DDRSS2_CTL_308_DATA 0x00000000 -#define DDRSS2_CTL_309_DATA 0x00000000 -#define DDRSS2_CTL_310_DATA 0x00000000 -#define DDRSS2_CTL_311_DATA 0x00000000 -#define DDRSS2_CTL_312_DATA 0x00000000 -#define DDRSS2_CTL_313_DATA 0x01000000 -#define DDRSS2_CTL_314_DATA 0x00020201 -#define DDRSS2_CTL_315_DATA 0x01000101 -#define DDRSS2_CTL_316_DATA 0x01010001 -#define DDRSS2_CTL_317_DATA 0x00010101 -#define DDRSS2_CTL_318_DATA 0x050A0A03 -#define DDRSS2_CTL_319_DATA 0x10081F1F -#define DDRSS2_CTL_320_DATA 0x00090310 -#define DDRSS2_CTL_321_DATA 0x0B0C030F -#define DDRSS2_CTL_322_DATA 0x0B0C0306 -#define DDRSS2_CTL_323_DATA 0x0C090006 -#define DDRSS2_CTL_324_DATA 0x0100000C -#define DDRSS2_CTL_325_DATA 0x08040801 -#define DDRSS2_CTL_326_DATA 0x00000004 -#define DDRSS2_CTL_327_DATA 0x00000000 -#define DDRSS2_CTL_328_DATA 0x00010000 -#define DDRSS2_CTL_329_DATA 0x00280D00 -#define DDRSS2_CTL_330_DATA 0x00000001 -#define DDRSS2_CTL_331_DATA 0x00030001 -#define DDRSS2_CTL_332_DATA 0x00000000 -#define DDRSS2_CTL_333_DATA 0x00000000 -#define DDRSS2_CTL_334_DATA 0x00000000 -#define DDRSS2_CTL_335_DATA 0x00000000 -#define DDRSS2_CTL_336_DATA 0x00000000 -#define DDRSS2_CTL_337_DATA 0x00000000 -#define DDRSS2_CTL_338_DATA 0x00000000 -#define DDRSS2_CTL_339_DATA 0x00000000 -#define DDRSS2_CTL_340_DATA 0x01000000 -#define DDRSS2_CTL_341_DATA 0x00000001 -#define DDRSS2_CTL_342_DATA 0x00010100 -#define DDRSS2_CTL_343_DATA 0x03030000 -#define DDRSS2_CTL_344_DATA 0x00000000 -#define DDRSS2_CTL_345_DATA 0x00000000 -#define DDRSS2_CTL_346_DATA 0x00000000 -#define DDRSS2_CTL_347_DATA 0x00000000 -#define DDRSS2_CTL_348_DATA 0x00000000 -#define DDRSS2_CTL_349_DATA 0x00000000 -#define DDRSS2_CTL_350_DATA 0x00000000 -#define DDRSS2_CTL_351_DATA 0x00000000 -#define DDRSS2_CTL_352_DATA 0x00000000 -#define DDRSS2_CTL_353_DATA 0x00000000 -#define DDRSS2_CTL_354_DATA 0x00000000 -#define DDRSS2_CTL_355_DATA 0x00000000 -#define DDRSS2_CTL_356_DATA 0x00000000 -#define DDRSS2_CTL_357_DATA 0x00000000 -#define DDRSS2_CTL_358_DATA 0x00000000 -#define DDRSS2_CTL_359_DATA 0x00000000 -#define DDRSS2_CTL_360_DATA 0x000556AA -#define DDRSS2_CTL_361_DATA 0x000AAAAA -#define DDRSS2_CTL_362_DATA 0x000AA955 -#define DDRSS2_CTL_363_DATA 0x00055555 -#define DDRSS2_CTL_364_DATA 0x000B3133 -#define DDRSS2_CTL_365_DATA 0x0004CD33 -#define DDRSS2_CTL_366_DATA 0x0004CECC -#define DDRSS2_CTL_367_DATA 0x000B32CC -#define DDRSS2_CTL_368_DATA 0x00010300 -#define DDRSS2_CTL_369_DATA 0x03000100 -#define DDRSS2_CTL_370_DATA 0x00000000 -#define DDRSS2_CTL_371_DATA 0x00000000 -#define DDRSS2_CTL_372_DATA 0x00000000 -#define DDRSS2_CTL_373_DATA 0x00000000 -#define DDRSS2_CTL_374_DATA 0x00000000 -#define DDRSS2_CTL_375_DATA 0x00000000 -#define DDRSS2_CTL_376_DATA 0x00000000 -#define DDRSS2_CTL_377_DATA 0x00010000 -#define DDRSS2_CTL_378_DATA 0x00000404 -#define DDRSS2_CTL_379_DATA 0x00000000 -#define DDRSS2_CTL_380_DATA 0x00000000 -#define DDRSS2_CTL_381_DATA 0x00000000 -#define DDRSS2_CTL_382_DATA 0x00000000 -#define DDRSS2_CTL_383_DATA 0x00000000 -#define DDRSS2_CTL_384_DATA 0x00000000 -#define DDRSS2_CTL_385_DATA 0x00000000 -#define DDRSS2_CTL_386_DATA 0x00000000 -#define DDRSS2_CTL_387_DATA 0x3A3A1B00 -#define DDRSS2_CTL_388_DATA 0x000A0000 -#define DDRSS2_CTL_389_DATA 0x0000019C -#define DDRSS2_CTL_390_DATA 0x00000200 -#define DDRSS2_CTL_391_DATA 0x00000200 -#define DDRSS2_CTL_392_DATA 0x00000200 -#define DDRSS2_CTL_393_DATA 0x00000200 -#define DDRSS2_CTL_394_DATA 0x000004D4 -#define DDRSS2_CTL_395_DATA 0x00001018 -#define DDRSS2_CTL_396_DATA 0x00000204 -#define DDRSS2_CTL_397_DATA 0x000040E6 -#define DDRSS2_CTL_398_DATA 0x00000200 -#define DDRSS2_CTL_399_DATA 0x00000200 -#define DDRSS2_CTL_400_DATA 0x00000200 -#define DDRSS2_CTL_401_DATA 0x00000200 -#define DDRSS2_CTL_402_DATA 0x0000C2B2 -#define DDRSS2_CTL_403_DATA 0x000288FC -#define DDRSS2_CTL_404_DATA 0x00000E15 -#define DDRSS2_CTL_405_DATA 0x000040E6 -#define DDRSS2_CTL_406_DATA 0x00000200 -#define DDRSS2_CTL_407_DATA 0x00000200 -#define DDRSS2_CTL_408_DATA 0x00000200 -#define DDRSS2_CTL_409_DATA 0x00000200 -#define DDRSS2_CTL_410_DATA 0x0000C2B2 -#define DDRSS2_CTL_411_DATA 0x000288FC -#define DDRSS2_CTL_412_DATA 0x02020E15 -#define DDRSS2_CTL_413_DATA 0x03030202 -#define DDRSS2_CTL_414_DATA 0x00000022 -#define DDRSS2_CTL_415_DATA 0x00000000 -#define DDRSS2_CTL_416_DATA 0x00000000 -#define DDRSS2_CTL_417_DATA 0x00001403 -#define DDRSS2_CTL_418_DATA 0x000007D0 -#define DDRSS2_CTL_419_DATA 0x00000000 -#define DDRSS2_CTL_420_DATA 0x00000000 -#define DDRSS2_CTL_421_DATA 0x00030000 -#define DDRSS2_CTL_422_DATA 0x0007001F -#define DDRSS2_CTL_423_DATA 0x001B0033 -#define DDRSS2_CTL_424_DATA 0x001B0033 -#define DDRSS2_CTL_425_DATA 0x00000000 -#define DDRSS2_CTL_426_DATA 0x00000000 -#define DDRSS2_CTL_427_DATA 0x02000000 -#define DDRSS2_CTL_428_DATA 0x01000404 -#define DDRSS2_CTL_429_DATA 0x0B1E0B1E -#define DDRSS2_CTL_430_DATA 0x00000105 -#define DDRSS2_CTL_431_DATA 0x00010101 -#define DDRSS2_CTL_432_DATA 0x00010101 -#define DDRSS2_CTL_433_DATA 0x00010001 -#define DDRSS2_CTL_434_DATA 0x00000101 -#define DDRSS2_CTL_435_DATA 0x02000201 -#define DDRSS2_CTL_436_DATA 0x02010000 -#define DDRSS2_CTL_437_DATA 0x00000200 -#define DDRSS2_CTL_438_DATA 0x28060000 -#define DDRSS2_CTL_439_DATA 0x00000128 -#define DDRSS2_CTL_440_DATA 0xFFFFFFFF -#define DDRSS2_CTL_441_DATA 0xFFFFFFFF -#define DDRSS2_CTL_442_DATA 0x00000000 -#define DDRSS2_CTL_443_DATA 0x00000000 -#define DDRSS2_CTL_444_DATA 0x00000000 -#define DDRSS2_CTL_445_DATA 0x00000000 -#define DDRSS2_CTL_446_DATA 0x00000000 -#define DDRSS2_CTL_447_DATA 0x00000000 -#define DDRSS2_CTL_448_DATA 0x00000000 -#define DDRSS2_CTL_449_DATA 0x00000000 -#define DDRSS2_CTL_450_DATA 0x00000000 -#define DDRSS2_CTL_451_DATA 0x00000000 -#define DDRSS2_CTL_452_DATA 0x00000000 -#define DDRSS2_CTL_453_DATA 0x00000000 -#define DDRSS2_CTL_454_DATA 0x00000000 -#define DDRSS2_CTL_455_DATA 0x00000000 -#define DDRSS2_CTL_456_DATA 0x00000000 -#define DDRSS2_CTL_457_DATA 0x00000000 -#define DDRSS2_CTL_458_DATA 0x00000000 - -#define DDRSS2_PI_00_DATA 0x00000B00 -#define DDRSS2_PI_01_DATA 0x00000000 -#define DDRSS2_PI_02_DATA 0x00000000 -#define DDRSS2_PI_03_DATA 0x00000000 -#define DDRSS2_PI_04_DATA 0x00000000 -#define DDRSS2_PI_05_DATA 0x00000101 -#define DDRSS2_PI_06_DATA 0x00640000 -#define DDRSS2_PI_07_DATA 0x00000001 -#define DDRSS2_PI_08_DATA 0x00000000 -#define DDRSS2_PI_09_DATA 0x00000000 -#define DDRSS2_PI_10_DATA 0x00000000 -#define DDRSS2_PI_11_DATA 0x00000000 -#define DDRSS2_PI_12_DATA 0x00000007 -#define DDRSS2_PI_13_DATA 0x00010002 -#define DDRSS2_PI_14_DATA 0x0800000F -#define DDRSS2_PI_15_DATA 0x00000103 -#define DDRSS2_PI_16_DATA 0x00000005 -#define DDRSS2_PI_17_DATA 0x00000000 -#define DDRSS2_PI_18_DATA 0x00000000 -#define DDRSS2_PI_19_DATA 0x00000000 -#define DDRSS2_PI_20_DATA 0x00000000 -#define DDRSS2_PI_21_DATA 0x00000000 -#define DDRSS2_PI_22_DATA 0x00000000 -#define DDRSS2_PI_23_DATA 0x00000000 -#define DDRSS2_PI_24_DATA 0x00000000 -#define DDRSS2_PI_25_DATA 0x00000000 -#define DDRSS2_PI_26_DATA 0x00010100 -#define DDRSS2_PI_27_DATA 0x00280A00 -#define DDRSS2_PI_28_DATA 0x00000000 -#define DDRSS2_PI_29_DATA 0x0F000000 -#define DDRSS2_PI_30_DATA 0x00003200 -#define DDRSS2_PI_31_DATA 0x00000000 -#define DDRSS2_PI_32_DATA 0x00000000 -#define DDRSS2_PI_33_DATA 0x01010102 -#define DDRSS2_PI_34_DATA 0x00000000 -#define DDRSS2_PI_35_DATA 0x000000AA -#define DDRSS2_PI_36_DATA 0x00000055 -#define DDRSS2_PI_37_DATA 0x000000B5 -#define DDRSS2_PI_38_DATA 0x0000004A -#define DDRSS2_PI_39_DATA 0x00000056 -#define DDRSS2_PI_40_DATA 0x000000A9 -#define DDRSS2_PI_41_DATA 0x000000A9 -#define DDRSS2_PI_42_DATA 0x000000B5 -#define DDRSS2_PI_43_DATA 0x00000000 -#define DDRSS2_PI_44_DATA 0x00000000 -#define DDRSS2_PI_45_DATA 0x000F0F00 -#define DDRSS2_PI_46_DATA 0x0000001B -#define DDRSS2_PI_47_DATA 0x000007D0 -#define DDRSS2_PI_48_DATA 0x00000300 -#define DDRSS2_PI_49_DATA 0x00000000 -#define DDRSS2_PI_50_DATA 0x00000000 -#define DDRSS2_PI_51_DATA 0x01000000 -#define DDRSS2_PI_52_DATA 0x00010101 -#define DDRSS2_PI_53_DATA 0x00000000 -#define DDRSS2_PI_54_DATA 0x00030000 -#define DDRSS2_PI_55_DATA 0x0F000000 -#define DDRSS2_PI_56_DATA 0x00000017 -#define DDRSS2_PI_57_DATA 0x00000000 -#define DDRSS2_PI_58_DATA 0x00000000 -#define DDRSS2_PI_59_DATA 0x00000000 -#define DDRSS2_PI_60_DATA 0x0A0A140A -#define DDRSS2_PI_61_DATA 0x10020101 -#define DDRSS2_PI_62_DATA 0x00020805 -#define DDRSS2_PI_63_DATA 0x01000404 -#define DDRSS2_PI_64_DATA 0x00000000 -#define DDRSS2_PI_65_DATA 0x00000000 -#define DDRSS2_PI_66_DATA 0x00000100 -#define DDRSS2_PI_67_DATA 0x0001010F -#define DDRSS2_PI_68_DATA 0x00340000 -#define DDRSS2_PI_69_DATA 0x00000000 -#define DDRSS2_PI_70_DATA 0x00000000 -#define DDRSS2_PI_71_DATA 0x0000FFFF -#define DDRSS2_PI_72_DATA 0x00000000 -#define DDRSS2_PI_73_DATA 0x00080000 -#define DDRSS2_PI_74_DATA 0x02000200 -#define DDRSS2_PI_75_DATA 0x01000100 -#define DDRSS2_PI_76_DATA 0x01000000 -#define DDRSS2_PI_77_DATA 0x02000200 -#define DDRSS2_PI_78_DATA 0x00000200 -#define DDRSS2_PI_79_DATA 0x00000000 -#define DDRSS2_PI_80_DATA 0x00000000 -#define DDRSS2_PI_81_DATA 0x00000000 -#define DDRSS2_PI_82_DATA 0x00000000 -#define DDRSS2_PI_83_DATA 0x00000000 -#define DDRSS2_PI_84_DATA 0x00000000 -#define DDRSS2_PI_85_DATA 0x00000000 -#define DDRSS2_PI_86_DATA 0x00000000 -#define DDRSS2_PI_87_DATA 0x00000000 -#define DDRSS2_PI_88_DATA 0x00000000 -#define DDRSS2_PI_89_DATA 0x00000000 -#define DDRSS2_PI_90_DATA 0x00000000 -#define DDRSS2_PI_91_DATA 0x00000400 -#define DDRSS2_PI_92_DATA 0x02010000 -#define DDRSS2_PI_93_DATA 0x00080003 -#define DDRSS2_PI_94_DATA 0x00080000 -#define DDRSS2_PI_95_DATA 0x00000001 -#define DDRSS2_PI_96_DATA 0x00000000 -#define DDRSS2_PI_97_DATA 0x0000AA00 -#define DDRSS2_PI_98_DATA 0x00000000 -#define DDRSS2_PI_99_DATA 0x00000000 -#define DDRSS2_PI_100_DATA 0x00010000 -#define DDRSS2_PI_101_DATA 0x00000000 -#define DDRSS2_PI_102_DATA 0x00000000 -#define DDRSS2_PI_103_DATA 0x00000000 -#define DDRSS2_PI_104_DATA 0x00000000 -#define DDRSS2_PI_105_DATA 0x00000000 -#define DDRSS2_PI_106_DATA 0x00000000 -#define DDRSS2_PI_107_DATA 0x00000000 -#define DDRSS2_PI_108_DATA 0x00000000 -#define DDRSS2_PI_109_DATA 0x00000000 -#define DDRSS2_PI_110_DATA 0x00000000 -#define DDRSS2_PI_111_DATA 0x00000000 -#define DDRSS2_PI_112_DATA 0x00000000 -#define DDRSS2_PI_113_DATA 0x00000000 -#define DDRSS2_PI_114_DATA 0x00000000 -#define DDRSS2_PI_115_DATA 0x00000000 -#define DDRSS2_PI_116_DATA 0x00000000 -#define DDRSS2_PI_117_DATA 0x00000000 -#define DDRSS2_PI_118_DATA 0x00000000 -#define DDRSS2_PI_119_DATA 0x00000000 -#define DDRSS2_PI_120_DATA 0x00000000 -#define DDRSS2_PI_121_DATA 0x00000000 -#define DDRSS2_PI_122_DATA 0x00000000 -#define DDRSS2_PI_123_DATA 0x00000000 -#define DDRSS2_PI_124_DATA 0x00000000 -#define DDRSS2_PI_125_DATA 0x00000008 -#define DDRSS2_PI_126_DATA 0x00000000 -#define DDRSS2_PI_127_DATA 0x00000000 -#define DDRSS2_PI_128_DATA 0x00000000 -#define DDRSS2_PI_129_DATA 0x00000000 -#define DDRSS2_PI_130_DATA 0x00000000 -#define DDRSS2_PI_131_DATA 0x00000000 -#define DDRSS2_PI_132_DATA 0x00000000 -#define DDRSS2_PI_133_DATA 0x00000000 -#define DDRSS2_PI_134_DATA 0x00000002 -#define DDRSS2_PI_135_DATA 0x00000000 -#define DDRSS2_PI_136_DATA 0x00000000 -#define DDRSS2_PI_137_DATA 0x0000000A -#define DDRSS2_PI_138_DATA 0x00000019 -#define DDRSS2_PI_139_DATA 0x00000100 -#define DDRSS2_PI_140_DATA 0x00000000 -#define DDRSS2_PI_141_DATA 0x00000000 -#define DDRSS2_PI_142_DATA 0x00000000 -#define DDRSS2_PI_143_DATA 0x00000000 -#define DDRSS2_PI_144_DATA 0x01000000 -#define DDRSS2_PI_145_DATA 0x00010003 -#define DDRSS2_PI_146_DATA 0x02000101 -#define DDRSS2_PI_147_DATA 0x01030001 -#define DDRSS2_PI_148_DATA 0x00010400 -#define DDRSS2_PI_149_DATA 0x06000105 -#define DDRSS2_PI_150_DATA 0x01070001 -#define DDRSS2_PI_151_DATA 0x00000000 -#define DDRSS2_PI_152_DATA 0x00000000 -#define DDRSS2_PI_153_DATA 0x00000000 -#define DDRSS2_PI_154_DATA 0x00010001 -#define DDRSS2_PI_155_DATA 0x00000000 -#define DDRSS2_PI_156_DATA 0x00000000 -#define DDRSS2_PI_157_DATA 0x00000000 -#define DDRSS2_PI_158_DATA 0x00000000 -#define DDRSS2_PI_159_DATA 0x00000401 -#define DDRSS2_PI_160_DATA 0x00000000 -#define DDRSS2_PI_161_DATA 0x00010000 -#define DDRSS2_PI_162_DATA 0x00000000 -#define DDRSS2_PI_163_DATA 0x2B2B0200 -#define DDRSS2_PI_164_DATA 0x00000034 -#define DDRSS2_PI_165_DATA 0x00000064 -#define DDRSS2_PI_166_DATA 0x00020064 -#define DDRSS2_PI_167_DATA 0x02000200 -#define DDRSS2_PI_168_DATA 0x48120C04 -#define DDRSS2_PI_169_DATA 0x00154812 -#define DDRSS2_PI_170_DATA 0x000000CE -#define DDRSS2_PI_171_DATA 0x0000032B -#define DDRSS2_PI_172_DATA 0x00002073 -#define DDRSS2_PI_173_DATA 0x0000032B -#define DDRSS2_PI_174_DATA 0x04002073 -#define DDRSS2_PI_175_DATA 0x01010404 -#define DDRSS2_PI_176_DATA 0x00001501 -#define DDRSS2_PI_177_DATA 0x00150015 -#define DDRSS2_PI_178_DATA 0x01000100 -#define DDRSS2_PI_179_DATA 0x00000100 -#define DDRSS2_PI_180_DATA 0x00000000 -#define DDRSS2_PI_181_DATA 0x01010101 -#define DDRSS2_PI_182_DATA 0x00000101 -#define DDRSS2_PI_183_DATA 0x00000000 -#define DDRSS2_PI_184_DATA 0x00000000 -#define DDRSS2_PI_185_DATA 0x15040000 -#define DDRSS2_PI_186_DATA 0x0E0E0215 -#define DDRSS2_PI_187_DATA 0x00040402 -#define DDRSS2_PI_188_DATA 0x000D0035 -#define DDRSS2_PI_189_DATA 0x00218049 -#define DDRSS2_PI_190_DATA 0x00218049 -#define DDRSS2_PI_191_DATA 0x01010101 -#define DDRSS2_PI_192_DATA 0x0004000E -#define DDRSS2_PI_193_DATA 0x00040216 -#define DDRSS2_PI_194_DATA 0x01000216 -#define DDRSS2_PI_195_DATA 0x000F000F -#define DDRSS2_PI_196_DATA 0x02170100 -#define DDRSS2_PI_197_DATA 0x01000217 -#define DDRSS2_PI_198_DATA 0x02170217 -#define DDRSS2_PI_199_DATA 0x32103200 -#define DDRSS2_PI_200_DATA 0x01013210 -#define DDRSS2_PI_201_DATA 0x0A070601 -#define DDRSS2_PI_202_DATA 0x1F130A0D -#define DDRSS2_PI_203_DATA 0x1F130A14 -#define DDRSS2_PI_204_DATA 0x0000C014 -#define DDRSS2_PI_205_DATA 0x00C01000 -#define DDRSS2_PI_206_DATA 0x00C01000 -#define DDRSS2_PI_207_DATA 0x00021000 -#define DDRSS2_PI_208_DATA 0x0024000E -#define DDRSS2_PI_209_DATA 0x00240216 -#define DDRSS2_PI_210_DATA 0x00110216 -#define DDRSS2_PI_211_DATA 0x32000056 -#define DDRSS2_PI_212_DATA 0x00000301 -#define DDRSS2_PI_213_DATA 0x005B0036 -#define DDRSS2_PI_214_DATA 0x03013212 -#define DDRSS2_PI_215_DATA 0x00003600 -#define DDRSS2_PI_216_DATA 0x3212005B -#define DDRSS2_PI_217_DATA 0x09000301 -#define DDRSS2_PI_218_DATA 0x04010504 -#define DDRSS2_PI_219_DATA 0x040006C9 -#define DDRSS2_PI_220_DATA 0x0A032001 -#define DDRSS2_PI_221_DATA 0x2C31110A -#define DDRSS2_PI_222_DATA 0x00002918 -#define DDRSS2_PI_223_DATA 0x6001071C -#define DDRSS2_PI_224_DATA 0x1E202008 -#define DDRSS2_PI_225_DATA 0x2C311116 -#define DDRSS2_PI_226_DATA 0x00002918 -#define DDRSS2_PI_227_DATA 0x6001071C -#define DDRSS2_PI_228_DATA 0x1E202008 -#define DDRSS2_PI_229_DATA 0x00019C16 -#define DDRSS2_PI_230_DATA 0x00001018 -#define DDRSS2_PI_231_DATA 0x000040E6 -#define DDRSS2_PI_232_DATA 0x000288FC -#define DDRSS2_PI_233_DATA 0x000040E6 -#define DDRSS2_PI_234_DATA 0x000288FC -#define DDRSS2_PI_235_DATA 0x033B0016 -#define DDRSS2_PI_236_DATA 0x0303033B -#define DDRSS2_PI_237_DATA 0x002AF803 -#define DDRSS2_PI_238_DATA 0x0001ADAF -#define DDRSS2_PI_239_DATA 0x00000005 -#define DDRSS2_PI_240_DATA 0x0000006E -#define DDRSS2_PI_241_DATA 0x00000016 -#define DDRSS2_PI_242_DATA 0x000681C8 -#define DDRSS2_PI_243_DATA 0x0001ADAF -#define DDRSS2_PI_244_DATA 0x00000005 -#define DDRSS2_PI_245_DATA 0x000010A9 -#define DDRSS2_PI_246_DATA 0x0000033B -#define DDRSS2_PI_247_DATA 0x000681C8 -#define DDRSS2_PI_248_DATA 0x0001ADAF -#define DDRSS2_PI_249_DATA 0x00000005 -#define DDRSS2_PI_250_DATA 0x000010A9 -#define DDRSS2_PI_251_DATA 0x0100033B -#define DDRSS2_PI_252_DATA 0x00370040 -#define DDRSS2_PI_253_DATA 0x00010008 -#define DDRSS2_PI_254_DATA 0x08550040 -#define DDRSS2_PI_255_DATA 0x00010040 -#define DDRSS2_PI_256_DATA 0x08550040 -#define DDRSS2_PI_257_DATA 0x00000340 -#define DDRSS2_PI_258_DATA 0x006B006B -#define DDRSS2_PI_259_DATA 0x08040404 -#define DDRSS2_PI_260_DATA 0x00000055 -#define DDRSS2_PI_261_DATA 0x55083C5A -#define DDRSS2_PI_262_DATA 0x5A000000 -#define DDRSS2_PI_263_DATA 0x0055083C -#define DDRSS2_PI_264_DATA 0x3C5A0000 -#define DDRSS2_PI_265_DATA 0x00005508 -#define DDRSS2_PI_266_DATA 0x0C3C5A00 -#define DDRSS2_PI_267_DATA 0x080F0E0D -#define DDRSS2_PI_268_DATA 0x000B0A09 -#define DDRSS2_PI_269_DATA 0x00030201 -#define DDRSS2_PI_270_DATA 0x01000000 -#define DDRSS2_PI_271_DATA 0x04020201 -#define DDRSS2_PI_272_DATA 0x00080804 -#define DDRSS2_PI_273_DATA 0x00000000 -#define DDRSS2_PI_274_DATA 0x00000000 -#define DDRSS2_PI_275_DATA 0x00330084 -#define DDRSS2_PI_276_DATA 0x00160000 -#define DDRSS2_PI_277_DATA 0x35333FF4 -#define DDRSS2_PI_278_DATA 0x00160F27 -#define DDRSS2_PI_279_DATA 0x35333FF4 -#define DDRSS2_PI_280_DATA 0x00160F27 -#define DDRSS2_PI_281_DATA 0x00330084 -#define DDRSS2_PI_282_DATA 0x00160000 -#define DDRSS2_PI_283_DATA 0x35333FF4 -#define DDRSS2_PI_284_DATA 0x00160F27 -#define DDRSS2_PI_285_DATA 0x35333FF4 -#define DDRSS2_PI_286_DATA 0x00160F27 -#define DDRSS2_PI_287_DATA 0x00330084 -#define DDRSS2_PI_288_DATA 0x00160000 -#define DDRSS2_PI_289_DATA 0x35333FF4 -#define DDRSS2_PI_290_DATA 0x00160F27 -#define DDRSS2_PI_291_DATA 0x35333FF4 -#define DDRSS2_PI_292_DATA 0x00160F27 -#define DDRSS2_PI_293_DATA 0x00330084 -#define DDRSS2_PI_294_DATA 0x00160000 -#define DDRSS2_PI_295_DATA 0x35333FF4 -#define DDRSS2_PI_296_DATA 0x00160F27 -#define DDRSS2_PI_297_DATA 0x35333FF4 -#define DDRSS2_PI_298_DATA 0x00160F27 -#define DDRSS2_PI_299_DATA 0x00000000 - -#define DDRSS2_PHY_00_DATA 0x000004F0 -#define DDRSS2_PHY_01_DATA 0x00000000 -#define DDRSS2_PHY_02_DATA 0x00030200 -#define DDRSS2_PHY_03_DATA 0x00000000 -#define DDRSS2_PHY_04_DATA 0x00000000 -#define DDRSS2_PHY_05_DATA 0x01030000 -#define DDRSS2_PHY_06_DATA 0x00010000 -#define DDRSS2_PHY_07_DATA 0x01030004 -#define DDRSS2_PHY_08_DATA 0x01000000 -#define DDRSS2_PHY_09_DATA 0x00000000 -#define DDRSS2_PHY_10_DATA 0x00000000 -#define DDRSS2_PHY_11_DATA 0x01000001 -#define DDRSS2_PHY_12_DATA 0x00000100 -#define DDRSS2_PHY_13_DATA 0x000800C0 -#define DDRSS2_PHY_14_DATA 0x060100CC -#define DDRSS2_PHY_15_DATA 0x00030066 -#define DDRSS2_PHY_16_DATA 0x00000000 -#define DDRSS2_PHY_17_DATA 0x00000301 -#define DDRSS2_PHY_18_DATA 0x0000AAAA -#define DDRSS2_PHY_19_DATA 0x00005555 -#define DDRSS2_PHY_20_DATA 0x0000B5B5 -#define DDRSS2_PHY_21_DATA 0x00004A4A -#define DDRSS2_PHY_22_DATA 0x00005656 -#define DDRSS2_PHY_23_DATA 0x0000A9A9 -#define DDRSS2_PHY_24_DATA 0x0000A9A9 -#define DDRSS2_PHY_25_DATA 0x0000B5B5 -#define DDRSS2_PHY_26_DATA 0x00000000 -#define DDRSS2_PHY_27_DATA 0x00000000 -#define DDRSS2_PHY_28_DATA 0x2A000000 -#define DDRSS2_PHY_29_DATA 0x00000808 -#define DDRSS2_PHY_30_DATA 0x0F000000 -#define DDRSS2_PHY_31_DATA 0x00000F0F -#define DDRSS2_PHY_32_DATA 0x10400000 -#define DDRSS2_PHY_33_DATA 0x0C002006 -#define DDRSS2_PHY_34_DATA 0x00000000 -#define DDRSS2_PHY_35_DATA 0x00000000 -#define DDRSS2_PHY_36_DATA 0x55555555 -#define DDRSS2_PHY_37_DATA 0xAAAAAAAA -#define DDRSS2_PHY_38_DATA 0x55555555 -#define DDRSS2_PHY_39_DATA 0xAAAAAAAA -#define DDRSS2_PHY_40_DATA 0x00005555 -#define DDRSS2_PHY_41_DATA 0x01000100 -#define DDRSS2_PHY_42_DATA 0x00800180 -#define DDRSS2_PHY_43_DATA 0x00000001 -#define DDRSS2_PHY_44_DATA 0x00000000 -#define DDRSS2_PHY_45_DATA 0x00000000 -#define DDRSS2_PHY_46_DATA 0x00000000 -#define DDRSS2_PHY_47_DATA 0x00000000 -#define DDRSS2_PHY_48_DATA 0x00000000 -#define DDRSS2_PHY_49_DATA 0x00000000 -#define DDRSS2_PHY_50_DATA 0x00000000 -#define DDRSS2_PHY_51_DATA 0x00000000 -#define DDRSS2_PHY_52_DATA 0x00000000 -#define DDRSS2_PHY_53_DATA 0x00000000 -#define DDRSS2_PHY_54_DATA 0x00000000 -#define DDRSS2_PHY_55_DATA 0x00000000 -#define DDRSS2_PHY_56_DATA 0x00000000 -#define DDRSS2_PHY_57_DATA 0x00000000 -#define DDRSS2_PHY_58_DATA 0x00000000 -#define DDRSS2_PHY_59_DATA 0x00000000 -#define DDRSS2_PHY_60_DATA 0x00000000 -#define DDRSS2_PHY_61_DATA 0x00000000 -#define DDRSS2_PHY_62_DATA 0x00000000 -#define DDRSS2_PHY_63_DATA 0x00000000 -#define DDRSS2_PHY_64_DATA 0x00000000 -#define DDRSS2_PHY_65_DATA 0x00000000 -#define DDRSS2_PHY_66_DATA 0x00000104 -#define DDRSS2_PHY_67_DATA 0x00000120 -#define DDRSS2_PHY_68_DATA 0x00000000 -#define DDRSS2_PHY_69_DATA 0x00000000 -#define DDRSS2_PHY_70_DATA 0x00000000 -#define DDRSS2_PHY_71_DATA 0x00000000 -#define DDRSS2_PHY_72_DATA 0x00000000 -#define DDRSS2_PHY_73_DATA 0x00000000 -#define DDRSS2_PHY_74_DATA 0x00000000 -#define DDRSS2_PHY_75_DATA 0x00000001 -#define DDRSS2_PHY_76_DATA 0x07FF0000 -#define DDRSS2_PHY_77_DATA 0x0080081F -#define DDRSS2_PHY_78_DATA 0x00081020 -#define DDRSS2_PHY_79_DATA 0x04010000 -#define DDRSS2_PHY_80_DATA 0x00000000 -#define DDRSS2_PHY_81_DATA 0x00000000 -#define DDRSS2_PHY_82_DATA 0x00000000 -#define DDRSS2_PHY_83_DATA 0x00000100 -#define DDRSS2_PHY_84_DATA 0x01CC0C01 -#define DDRSS2_PHY_85_DATA 0x1003CC0C -#define DDRSS2_PHY_86_DATA 0x20000140 -#define DDRSS2_PHY_87_DATA 0x07FF0200 -#define DDRSS2_PHY_88_DATA 0x0000DD01 -#define DDRSS2_PHY_89_DATA 0x10100303 -#define DDRSS2_PHY_90_DATA 0x10101010 -#define DDRSS2_PHY_91_DATA 0x10101010 -#define DDRSS2_PHY_92_DATA 0x00021010 -#define DDRSS2_PHY_93_DATA 0x00100010 -#define DDRSS2_PHY_94_DATA 0x00100010 -#define DDRSS2_PHY_95_DATA 0x00100010 -#define DDRSS2_PHY_96_DATA 0x00100010 -#define DDRSS2_PHY_97_DATA 0x00050010 -#define DDRSS2_PHY_98_DATA 0x51517041 -#define DDRSS2_PHY_99_DATA 0x31C06001 -#define DDRSS2_PHY_100_DATA 0x07AB0340 -#define DDRSS2_PHY_101_DATA 0x00C0C001 -#define DDRSS2_PHY_102_DATA 0x0E0D0001 -#define DDRSS2_PHY_103_DATA 0x10001000 -#define DDRSS2_PHY_104_DATA 0x0C083E42 -#define DDRSS2_PHY_105_DATA 0x0F0C3701 -#define DDRSS2_PHY_106_DATA 0x01000140 -#define DDRSS2_PHY_107_DATA 0x0C000420 -#define DDRSS2_PHY_108_DATA 0x00000198 -#define DDRSS2_PHY_109_DATA 0x0A0000D0 -#define DDRSS2_PHY_110_DATA 0x00030200 -#define DDRSS2_PHY_111_DATA 0x02800000 -#define DDRSS2_PHY_112_DATA 0x80800000 -#define DDRSS2_PHY_113_DATA 0x000E2010 -#define DDRSS2_PHY_114_DATA 0x76543210 -#define DDRSS2_PHY_115_DATA 0x00000008 -#define DDRSS2_PHY_116_DATA 0x02800280 -#define DDRSS2_PHY_117_DATA 0x02800280 -#define DDRSS2_PHY_118_DATA 0x02800280 -#define DDRSS2_PHY_119_DATA 0x02800280 -#define DDRSS2_PHY_120_DATA 0x00000280 -#define DDRSS2_PHY_121_DATA 0x0000A000 -#define DDRSS2_PHY_122_DATA 0x00A000A0 -#define DDRSS2_PHY_123_DATA 0x00A000A0 -#define DDRSS2_PHY_124_DATA 0x00A000A0 -#define DDRSS2_PHY_125_DATA 0x00A000A0 -#define DDRSS2_PHY_126_DATA 0x00A000A0 -#define DDRSS2_PHY_127_DATA 0x00A000A0 -#define DDRSS2_PHY_128_DATA 0x00A000A0 -#define DDRSS2_PHY_129_DATA 0x00A000A0 -#define DDRSS2_PHY_130_DATA 0x01C200A0 -#define DDRSS2_PHY_131_DATA 0x01A00005 -#define DDRSS2_PHY_132_DATA 0x00000000 -#define DDRSS2_PHY_133_DATA 0x00000000 -#define DDRSS2_PHY_134_DATA 0x00080200 -#define DDRSS2_PHY_135_DATA 0x00000000 -#define DDRSS2_PHY_136_DATA 0x20202000 -#define DDRSS2_PHY_137_DATA 0x20202020 -#define DDRSS2_PHY_138_DATA 0xF0F02020 -#define DDRSS2_PHY_139_DATA 0x00000000 -#define DDRSS2_PHY_140_DATA 0x00000000 -#define DDRSS2_PHY_141_DATA 0x00000000 -#define DDRSS2_PHY_142_DATA 0x00000000 -#define DDRSS2_PHY_143_DATA 0x00000000 -#define DDRSS2_PHY_144_DATA 0x00000000 -#define DDRSS2_PHY_145_DATA 0x00000000 -#define DDRSS2_PHY_146_DATA 0x00000000 -#define DDRSS2_PHY_147_DATA 0x00000000 -#define DDRSS2_PHY_148_DATA 0x00000000 -#define DDRSS2_PHY_149_DATA 0x00000000 -#define DDRSS2_PHY_150_DATA 0x00000000 -#define DDRSS2_PHY_151_DATA 0x00000000 -#define DDRSS2_PHY_152_DATA 0x00000000 -#define DDRSS2_PHY_153_DATA 0x00000000 -#define DDRSS2_PHY_154_DATA 0x00000000 -#define DDRSS2_PHY_155_DATA 0x00000000 -#define DDRSS2_PHY_156_DATA 0x00000000 -#define DDRSS2_PHY_157_DATA 0x00000000 -#define DDRSS2_PHY_158_DATA 0x00000000 -#define DDRSS2_PHY_159_DATA 0x00000000 -#define DDRSS2_PHY_160_DATA 0x00000000 -#define DDRSS2_PHY_161_DATA 0x00000000 -#define DDRSS2_PHY_162_DATA 0x00000000 -#define DDRSS2_PHY_163_DATA 0x00000000 -#define DDRSS2_PHY_164_DATA 0x00000000 -#define DDRSS2_PHY_165_DATA 0x00000000 -#define DDRSS2_PHY_166_DATA 0x00000000 -#define DDRSS2_PHY_167_DATA 0x00000000 -#define DDRSS2_PHY_168_DATA 0x00000000 -#define DDRSS2_PHY_169_DATA 0x00000000 -#define DDRSS2_PHY_170_DATA 0x00000000 -#define DDRSS2_PHY_171_DATA 0x00000000 -#define DDRSS2_PHY_172_DATA 0x00000000 -#define DDRSS2_PHY_173_DATA 0x00000000 -#define DDRSS2_PHY_174_DATA 0x00000000 -#define DDRSS2_PHY_175_DATA 0x00000000 -#define DDRSS2_PHY_176_DATA 0x00000000 -#define DDRSS2_PHY_177_DATA 0x00000000 -#define DDRSS2_PHY_178_DATA 0x00000000 -#define DDRSS2_PHY_179_DATA 0x00000000 -#define DDRSS2_PHY_180_DATA 0x00000000 -#define DDRSS2_PHY_181_DATA 0x00000000 -#define DDRSS2_PHY_182_DATA 0x00000000 -#define DDRSS2_PHY_183_DATA 0x00000000 -#define DDRSS2_PHY_184_DATA 0x00000000 -#define DDRSS2_PHY_185_DATA 0x00000000 -#define DDRSS2_PHY_186_DATA 0x00000000 -#define DDRSS2_PHY_187_DATA 0x00000000 -#define DDRSS2_PHY_188_DATA 0x00000000 -#define DDRSS2_PHY_189_DATA 0x00000000 -#define DDRSS2_PHY_190_DATA 0x00000000 -#define DDRSS2_PHY_191_DATA 0x00000000 -#define DDRSS2_PHY_192_DATA 0x00000000 -#define DDRSS2_PHY_193_DATA 0x00000000 -#define DDRSS2_PHY_194_DATA 0x00000000 -#define DDRSS2_PHY_195_DATA 0x00000000 -#define DDRSS2_PHY_196_DATA 0x00000000 -#define DDRSS2_PHY_197_DATA 0x00000000 -#define DDRSS2_PHY_198_DATA 0x00000000 -#define DDRSS2_PHY_199_DATA 0x00000000 -#define DDRSS2_PHY_200_DATA 0x00000000 -#define DDRSS2_PHY_201_DATA 0x00000000 -#define DDRSS2_PHY_202_DATA 0x00000000 -#define DDRSS2_PHY_203_DATA 0x00000000 -#define DDRSS2_PHY_204_DATA 0x00000000 -#define DDRSS2_PHY_205_DATA 0x00000000 -#define DDRSS2_PHY_206_DATA 0x00000000 -#define DDRSS2_PHY_207_DATA 0x00000000 -#define DDRSS2_PHY_208_DATA 0x00000000 -#define DDRSS2_PHY_209_DATA 0x00000000 -#define DDRSS2_PHY_210_DATA 0x00000000 -#define DDRSS2_PHY_211_DATA 0x00000000 -#define DDRSS2_PHY_212_DATA 0x00000000 -#define DDRSS2_PHY_213_DATA 0x00000000 -#define DDRSS2_PHY_214_DATA 0x00000000 -#define DDRSS2_PHY_215_DATA 0x00000000 -#define DDRSS2_PHY_216_DATA 0x00000000 -#define DDRSS2_PHY_217_DATA 0x00000000 -#define DDRSS2_PHY_218_DATA 0x00000000 -#define DDRSS2_PHY_219_DATA 0x00000000 -#define DDRSS2_PHY_220_DATA 0x00000000 -#define DDRSS2_PHY_221_DATA 0x00000000 -#define DDRSS2_PHY_222_DATA 0x00000000 -#define DDRSS2_PHY_223_DATA 0x00000000 -#define DDRSS2_PHY_224_DATA 0x00000000 -#define DDRSS2_PHY_225_DATA 0x00000000 -#define DDRSS2_PHY_226_DATA 0x00000000 -#define DDRSS2_PHY_227_DATA 0x00000000 -#define DDRSS2_PHY_228_DATA 0x00000000 -#define DDRSS2_PHY_229_DATA 0x00000000 -#define DDRSS2_PHY_230_DATA 0x00000000 -#define DDRSS2_PHY_231_DATA 0x00000000 -#define DDRSS2_PHY_232_DATA 0x00000000 -#define DDRSS2_PHY_233_DATA 0x00000000 -#define DDRSS2_PHY_234_DATA 0x00000000 -#define DDRSS2_PHY_235_DATA 0x00000000 -#define DDRSS2_PHY_236_DATA 0x00000000 -#define DDRSS2_PHY_237_DATA 0x00000000 -#define DDRSS2_PHY_238_DATA 0x00000000 -#define DDRSS2_PHY_239_DATA 0x00000000 -#define DDRSS2_PHY_240_DATA 0x00000000 -#define DDRSS2_PHY_241_DATA 0x00000000 -#define DDRSS2_PHY_242_DATA 0x00000000 -#define DDRSS2_PHY_243_DATA 0x00000000 -#define DDRSS2_PHY_244_DATA 0x00000000 -#define DDRSS2_PHY_245_DATA 0x00000000 -#define DDRSS2_PHY_246_DATA 0x00000000 -#define DDRSS2_PHY_247_DATA 0x00000000 -#define DDRSS2_PHY_248_DATA 0x00000000 -#define DDRSS2_PHY_249_DATA 0x00000000 -#define DDRSS2_PHY_250_DATA 0x00000000 -#define DDRSS2_PHY_251_DATA 0x00000000 -#define DDRSS2_PHY_252_DATA 0x00000000 -#define DDRSS2_PHY_253_DATA 0x00000000 -#define DDRSS2_PHY_254_DATA 0x00000000 -#define DDRSS2_PHY_255_DATA 0x00000000 -#define DDRSS2_PHY_256_DATA 0x000004F0 -#define DDRSS2_PHY_257_DATA 0x00000000 -#define DDRSS2_PHY_258_DATA 0x00030200 -#define DDRSS2_PHY_259_DATA 0x00000000 -#define DDRSS2_PHY_260_DATA 0x00000000 -#define DDRSS2_PHY_261_DATA 0x01030000 -#define DDRSS2_PHY_262_DATA 0x00010000 -#define DDRSS2_PHY_263_DATA 0x01030004 -#define DDRSS2_PHY_264_DATA 0x01000000 -#define DDRSS2_PHY_265_DATA 0x00000000 -#define DDRSS2_PHY_266_DATA 0x00000000 -#define DDRSS2_PHY_267_DATA 0x01000001 -#define DDRSS2_PHY_268_DATA 0x00000100 -#define DDRSS2_PHY_269_DATA 0x000800C0 -#define DDRSS2_PHY_270_DATA 0x060100CC -#define DDRSS2_PHY_271_DATA 0x00030066 -#define DDRSS2_PHY_272_DATA 0x00000000 -#define DDRSS2_PHY_273_DATA 0x00000301 -#define DDRSS2_PHY_274_DATA 0x0000AAAA -#define DDRSS2_PHY_275_DATA 0x00005555 -#define DDRSS2_PHY_276_DATA 0x0000B5B5 -#define DDRSS2_PHY_277_DATA 0x00004A4A -#define DDRSS2_PHY_278_DATA 0x00005656 -#define DDRSS2_PHY_279_DATA 0x0000A9A9 -#define DDRSS2_PHY_280_DATA 0x0000A9A9 -#define DDRSS2_PHY_281_DATA 0x0000B5B5 -#define DDRSS2_PHY_282_DATA 0x00000000 -#define DDRSS2_PHY_283_DATA 0x00000000 -#define DDRSS2_PHY_284_DATA 0x2A000000 -#define DDRSS2_PHY_285_DATA 0x00000808 -#define DDRSS2_PHY_286_DATA 0x0F000000 -#define DDRSS2_PHY_287_DATA 0x00000F0F -#define DDRSS2_PHY_288_DATA 0x10400000 -#define DDRSS2_PHY_289_DATA 0x0C002006 -#define DDRSS2_PHY_290_DATA 0x00000000 -#define DDRSS2_PHY_291_DATA 0x00000000 -#define DDRSS2_PHY_292_DATA 0x55555555 -#define DDRSS2_PHY_293_DATA 0xAAAAAAAA -#define DDRSS2_PHY_294_DATA 0x55555555 -#define DDRSS2_PHY_295_DATA 0xAAAAAAAA -#define DDRSS2_PHY_296_DATA 0x00005555 -#define DDRSS2_PHY_297_DATA 0x01000100 -#define DDRSS2_PHY_298_DATA 0x00800180 -#define DDRSS2_PHY_299_DATA 0x00000000 -#define DDRSS2_PHY_300_DATA 0x00000000 -#define DDRSS2_PHY_301_DATA 0x00000000 -#define DDRSS2_PHY_302_DATA 0x00000000 -#define DDRSS2_PHY_303_DATA 0x00000000 -#define DDRSS2_PHY_304_DATA 0x00000000 -#define DDRSS2_PHY_305_DATA 0x00000000 -#define DDRSS2_PHY_306_DATA 0x00000000 -#define DDRSS2_PHY_307_DATA 0x00000000 -#define DDRSS2_PHY_308_DATA 0x00000000 -#define DDRSS2_PHY_309_DATA 0x00000000 -#define DDRSS2_PHY_310_DATA 0x00000000 -#define DDRSS2_PHY_311_DATA 0x00000000 -#define DDRSS2_PHY_312_DATA 0x00000000 -#define DDRSS2_PHY_313_DATA 0x00000000 -#define DDRSS2_PHY_314_DATA 0x00000000 -#define DDRSS2_PHY_315_DATA 0x00000000 -#define DDRSS2_PHY_316_DATA 0x00000000 -#define DDRSS2_PHY_317_DATA 0x00000000 -#define DDRSS2_PHY_318_DATA 0x00000000 -#define DDRSS2_PHY_319_DATA 0x00000000 -#define DDRSS2_PHY_320_DATA 0x00000000 -#define DDRSS2_PHY_321_DATA 0x00000000 -#define DDRSS2_PHY_322_DATA 0x00000104 -#define DDRSS2_PHY_323_DATA 0x00000120 -#define DDRSS2_PHY_324_DATA 0x00000000 -#define DDRSS2_PHY_325_DATA 0x00000000 -#define DDRSS2_PHY_326_DATA 0x00000000 -#define DDRSS2_PHY_327_DATA 0x00000000 -#define DDRSS2_PHY_328_DATA 0x00000000 -#define DDRSS2_PHY_329_DATA 0x00000000 -#define DDRSS2_PHY_330_DATA 0x00000000 -#define DDRSS2_PHY_331_DATA 0x00000001 -#define DDRSS2_PHY_332_DATA 0x07FF0000 -#define DDRSS2_PHY_333_DATA 0x0080081F -#define DDRSS2_PHY_334_DATA 0x00081020 -#define DDRSS2_PHY_335_DATA 0x04010000 -#define DDRSS2_PHY_336_DATA 0x00000000 -#define DDRSS2_PHY_337_DATA 0x00000000 -#define DDRSS2_PHY_338_DATA 0x00000000 -#define DDRSS2_PHY_339_DATA 0x00000100 -#define DDRSS2_PHY_340_DATA 0x01CC0C01 -#define DDRSS2_PHY_341_DATA 0x1003CC0C -#define DDRSS2_PHY_342_DATA 0x20000140 -#define DDRSS2_PHY_343_DATA 0x07FF0200 -#define DDRSS2_PHY_344_DATA 0x0000DD01 -#define DDRSS2_PHY_345_DATA 0x10100303 -#define DDRSS2_PHY_346_DATA 0x10101010 -#define DDRSS2_PHY_347_DATA 0x10101010 -#define DDRSS2_PHY_348_DATA 0x00021010 -#define DDRSS2_PHY_349_DATA 0x00100010 -#define DDRSS2_PHY_350_DATA 0x00100010 -#define DDRSS2_PHY_351_DATA 0x00100010 -#define DDRSS2_PHY_352_DATA 0x00100010 -#define DDRSS2_PHY_353_DATA 0x00050010 -#define DDRSS2_PHY_354_DATA 0x51517041 -#define DDRSS2_PHY_355_DATA 0x31C06001 -#define DDRSS2_PHY_356_DATA 0x07AB0340 -#define DDRSS2_PHY_357_DATA 0x00C0C001 -#define DDRSS2_PHY_358_DATA 0x0E0D0001 -#define DDRSS2_PHY_359_DATA 0x10001000 -#define DDRSS2_PHY_360_DATA 0x0C083E42 -#define DDRSS2_PHY_361_DATA 0x0F0C3701 -#define DDRSS2_PHY_362_DATA 0x01000140 -#define DDRSS2_PHY_363_DATA 0x0C000420 -#define DDRSS2_PHY_364_DATA 0x00000198 -#define DDRSS2_PHY_365_DATA 0x0A0000D0 -#define DDRSS2_PHY_366_DATA 0x00030200 -#define DDRSS2_PHY_367_DATA 0x02800000 -#define DDRSS2_PHY_368_DATA 0x80800000 -#define DDRSS2_PHY_369_DATA 0x000E2010 -#define DDRSS2_PHY_370_DATA 0x76543210 -#define DDRSS2_PHY_371_DATA 0x00000008 -#define DDRSS2_PHY_372_DATA 0x02800280 -#define DDRSS2_PHY_373_DATA 0x02800280 -#define DDRSS2_PHY_374_DATA 0x02800280 -#define DDRSS2_PHY_375_DATA 0x02800280 -#define DDRSS2_PHY_376_DATA 0x00000280 -#define DDRSS2_PHY_377_DATA 0x0000A000 -#define DDRSS2_PHY_378_DATA 0x00A000A0 -#define DDRSS2_PHY_379_DATA 0x00A000A0 -#define DDRSS2_PHY_380_DATA 0x00A000A0 -#define DDRSS2_PHY_381_DATA 0x00A000A0 -#define DDRSS2_PHY_382_DATA 0x00A000A0 -#define DDRSS2_PHY_383_DATA 0x00A000A0 -#define DDRSS2_PHY_384_DATA 0x00A000A0 -#define DDRSS2_PHY_385_DATA 0x00A000A0 -#define DDRSS2_PHY_386_DATA 0x01C200A0 -#define DDRSS2_PHY_387_DATA 0x01A00005 -#define DDRSS2_PHY_388_DATA 0x00000000 -#define DDRSS2_PHY_389_DATA 0x00000000 -#define DDRSS2_PHY_390_DATA 0x00080200 -#define DDRSS2_PHY_391_DATA 0x00000000 -#define DDRSS2_PHY_392_DATA 0x20202000 -#define DDRSS2_PHY_393_DATA 0x20202020 -#define DDRSS2_PHY_394_DATA 0xF0F02020 -#define DDRSS2_PHY_395_DATA 0x00000000 -#define DDRSS2_PHY_396_DATA 0x00000000 -#define DDRSS2_PHY_397_DATA 0x00000000 -#define DDRSS2_PHY_398_DATA 0x00000000 -#define DDRSS2_PHY_399_DATA 0x00000000 -#define DDRSS2_PHY_400_DATA 0x00000000 -#define DDRSS2_PHY_401_DATA 0x00000000 -#define DDRSS2_PHY_402_DATA 0x00000000 -#define DDRSS2_PHY_403_DATA 0x00000000 -#define DDRSS2_PHY_404_DATA 0x00000000 -#define DDRSS2_PHY_405_DATA 0x00000000 -#define DDRSS2_PHY_406_DATA 0x00000000 -#define DDRSS2_PHY_407_DATA 0x00000000 -#define DDRSS2_PHY_408_DATA 0x00000000 -#define DDRSS2_PHY_409_DATA 0x00000000 -#define DDRSS2_PHY_410_DATA 0x00000000 -#define DDRSS2_PHY_411_DATA 0x00000000 -#define DDRSS2_PHY_412_DATA 0x00000000 -#define DDRSS2_PHY_413_DATA 0x00000000 -#define DDRSS2_PHY_414_DATA 0x00000000 -#define DDRSS2_PHY_415_DATA 0x00000000 -#define DDRSS2_PHY_416_DATA 0x00000000 -#define DDRSS2_PHY_417_DATA 0x00000000 -#define DDRSS2_PHY_418_DATA 0x00000000 -#define DDRSS2_PHY_419_DATA 0x00000000 -#define DDRSS2_PHY_420_DATA 0x00000000 -#define DDRSS2_PHY_421_DATA 0x00000000 -#define DDRSS2_PHY_422_DATA 0x00000000 -#define DDRSS2_PHY_423_DATA 0x00000000 -#define DDRSS2_PHY_424_DATA 0x00000000 -#define DDRSS2_PHY_425_DATA 0x00000000 -#define DDRSS2_PHY_426_DATA 0x00000000 -#define DDRSS2_PHY_427_DATA 0x00000000 -#define DDRSS2_PHY_428_DATA 0x00000000 -#define DDRSS2_PHY_429_DATA 0x00000000 -#define DDRSS2_PHY_430_DATA 0x00000000 -#define DDRSS2_PHY_431_DATA 0x00000000 -#define DDRSS2_PHY_432_DATA 0x00000000 -#define DDRSS2_PHY_433_DATA 0x00000000 -#define DDRSS2_PHY_434_DATA 0x00000000 -#define DDRSS2_PHY_435_DATA 0x00000000 -#define DDRSS2_PHY_436_DATA 0x00000000 -#define DDRSS2_PHY_437_DATA 0x00000000 -#define DDRSS2_PHY_438_DATA 0x00000000 -#define DDRSS2_PHY_439_DATA 0x00000000 -#define DDRSS2_PHY_440_DATA 0x00000000 -#define DDRSS2_PHY_441_DATA 0x00000000 -#define DDRSS2_PHY_442_DATA 0x00000000 -#define DDRSS2_PHY_443_DATA 0x00000000 -#define DDRSS2_PHY_444_DATA 0x00000000 -#define DDRSS2_PHY_445_DATA 0x00000000 -#define DDRSS2_PHY_446_DATA 0x00000000 -#define DDRSS2_PHY_447_DATA 0x00000000 -#define DDRSS2_PHY_448_DATA 0x00000000 -#define DDRSS2_PHY_449_DATA 0x00000000 -#define DDRSS2_PHY_450_DATA 0x00000000 -#define DDRSS2_PHY_451_DATA 0x00000000 -#define DDRSS2_PHY_452_DATA 0x00000000 -#define DDRSS2_PHY_453_DATA 0x00000000 -#define DDRSS2_PHY_454_DATA 0x00000000 -#define DDRSS2_PHY_455_DATA 0x00000000 -#define DDRSS2_PHY_456_DATA 0x00000000 -#define DDRSS2_PHY_457_DATA 0x00000000 -#define DDRSS2_PHY_458_DATA 0x00000000 -#define DDRSS2_PHY_459_DATA 0x00000000 -#define DDRSS2_PHY_460_DATA 0x00000000 -#define DDRSS2_PHY_461_DATA 0x00000000 -#define DDRSS2_PHY_462_DATA 0x00000000 -#define DDRSS2_PHY_463_DATA 0x00000000 -#define DDRSS2_PHY_464_DATA 0x00000000 -#define DDRSS2_PHY_465_DATA 0x00000000 -#define DDRSS2_PHY_466_DATA 0x00000000 -#define DDRSS2_PHY_467_DATA 0x00000000 -#define DDRSS2_PHY_468_DATA 0x00000000 -#define DDRSS2_PHY_469_DATA 0x00000000 -#define DDRSS2_PHY_470_DATA 0x00000000 -#define DDRSS2_PHY_471_DATA 0x00000000 -#define DDRSS2_PHY_472_DATA 0x00000000 -#define DDRSS2_PHY_473_DATA 0x00000000 -#define DDRSS2_PHY_474_DATA 0x00000000 -#define DDRSS2_PHY_475_DATA 0x00000000 -#define DDRSS2_PHY_476_DATA 0x00000000 -#define DDRSS2_PHY_477_DATA 0x00000000 -#define DDRSS2_PHY_478_DATA 0x00000000 -#define DDRSS2_PHY_479_DATA 0x00000000 -#define DDRSS2_PHY_480_DATA 0x00000000 -#define DDRSS2_PHY_481_DATA 0x00000000 -#define DDRSS2_PHY_482_DATA 0x00000000 -#define DDRSS2_PHY_483_DATA 0x00000000 -#define DDRSS2_PHY_484_DATA 0x00000000 -#define DDRSS2_PHY_485_DATA 0x00000000 -#define DDRSS2_PHY_486_DATA 0x00000000 -#define DDRSS2_PHY_487_DATA 0x00000000 -#define DDRSS2_PHY_488_DATA 0x00000000 -#define DDRSS2_PHY_489_DATA 0x00000000 -#define DDRSS2_PHY_490_DATA 0x00000000 -#define DDRSS2_PHY_491_DATA 0x00000000 -#define DDRSS2_PHY_492_DATA 0x00000000 -#define DDRSS2_PHY_493_DATA 0x00000000 -#define DDRSS2_PHY_494_DATA 0x00000000 -#define DDRSS2_PHY_495_DATA 0x00000000 -#define DDRSS2_PHY_496_DATA 0x00000000 -#define DDRSS2_PHY_497_DATA 0x00000000 -#define DDRSS2_PHY_498_DATA 0x00000000 -#define DDRSS2_PHY_499_DATA 0x00000000 -#define DDRSS2_PHY_500_DATA 0x00000000 -#define DDRSS2_PHY_501_DATA 0x00000000 -#define DDRSS2_PHY_502_DATA 0x00000000 -#define DDRSS2_PHY_503_DATA 0x00000000 -#define DDRSS2_PHY_504_DATA 0x00000000 -#define DDRSS2_PHY_505_DATA 0x00000000 -#define DDRSS2_PHY_506_DATA 0x00000000 -#define DDRSS2_PHY_507_DATA 0x00000000 -#define DDRSS2_PHY_508_DATA 0x00000000 -#define DDRSS2_PHY_509_DATA 0x00000000 -#define DDRSS2_PHY_510_DATA 0x00000000 -#define DDRSS2_PHY_511_DATA 0x00000000 -#define DDRSS2_PHY_512_DATA 0x000004F0 -#define DDRSS2_PHY_513_DATA 0x00000000 -#define DDRSS2_PHY_514_DATA 0x00030200 -#define DDRSS2_PHY_515_DATA 0x00000000 -#define DDRSS2_PHY_516_DATA 0x00000000 -#define DDRSS2_PHY_517_DATA 0x01030000 -#define DDRSS2_PHY_518_DATA 0x00010000 -#define DDRSS2_PHY_519_DATA 0x01030004 -#define DDRSS2_PHY_520_DATA 0x01000000 -#define DDRSS2_PHY_521_DATA 0x00000000 -#define DDRSS2_PHY_522_DATA 0x00000000 -#define DDRSS2_PHY_523_DATA 0x01000001 -#define DDRSS2_PHY_524_DATA 0x00000100 -#define DDRSS2_PHY_525_DATA 0x000800C0 -#define DDRSS2_PHY_526_DATA 0x060100CC -#define DDRSS2_PHY_527_DATA 0x00030066 -#define DDRSS2_PHY_528_DATA 0x00000000 -#define DDRSS2_PHY_529_DATA 0x00000301 -#define DDRSS2_PHY_530_DATA 0x0000AAAA -#define DDRSS2_PHY_531_DATA 0x00005555 -#define DDRSS2_PHY_532_DATA 0x0000B5B5 -#define DDRSS2_PHY_533_DATA 0x00004A4A -#define DDRSS2_PHY_534_DATA 0x00005656 -#define DDRSS2_PHY_535_DATA 0x0000A9A9 -#define DDRSS2_PHY_536_DATA 0x0000A9A9 -#define DDRSS2_PHY_537_DATA 0x0000B5B5 -#define DDRSS2_PHY_538_DATA 0x00000000 -#define DDRSS2_PHY_539_DATA 0x00000000 -#define DDRSS2_PHY_540_DATA 0x2A000000 -#define DDRSS2_PHY_541_DATA 0x00000808 -#define DDRSS2_PHY_542_DATA 0x0F000000 -#define DDRSS2_PHY_543_DATA 0x00000F0F -#define DDRSS2_PHY_544_DATA 0x10400000 -#define DDRSS2_PHY_545_DATA 0x0C002006 -#define DDRSS2_PHY_546_DATA 0x00000000 -#define DDRSS2_PHY_547_DATA 0x00000000 -#define DDRSS2_PHY_548_DATA 0x55555555 -#define DDRSS2_PHY_549_DATA 0xAAAAAAAA -#define DDRSS2_PHY_550_DATA 0x55555555 -#define DDRSS2_PHY_551_DATA 0xAAAAAAAA -#define DDRSS2_PHY_552_DATA 0x00005555 -#define DDRSS2_PHY_553_DATA 0x01000100 -#define DDRSS2_PHY_554_DATA 0x00800180 -#define DDRSS2_PHY_555_DATA 0x00000001 -#define DDRSS2_PHY_556_DATA 0x00000000 -#define DDRSS2_PHY_557_DATA 0x00000000 -#define DDRSS2_PHY_558_DATA 0x00000000 -#define DDRSS2_PHY_559_DATA 0x00000000 -#define DDRSS2_PHY_560_DATA 0x00000000 -#define DDRSS2_PHY_561_DATA 0x00000000 -#define DDRSS2_PHY_562_DATA 0x00000000 -#define DDRSS2_PHY_563_DATA 0x00000000 -#define DDRSS2_PHY_564_DATA 0x00000000 -#define DDRSS2_PHY_565_DATA 0x00000000 -#define DDRSS2_PHY_566_DATA 0x00000000 -#define DDRSS2_PHY_567_DATA 0x00000000 -#define DDRSS2_PHY_568_DATA 0x00000000 -#define DDRSS2_PHY_569_DATA 0x00000000 -#define DDRSS2_PHY_570_DATA 0x00000000 -#define DDRSS2_PHY_571_DATA 0x00000000 -#define DDRSS2_PHY_572_DATA 0x00000000 -#define DDRSS2_PHY_573_DATA 0x00000000 -#define DDRSS2_PHY_574_DATA 0x00000000 -#define DDRSS2_PHY_575_DATA 0x00000000 -#define DDRSS2_PHY_576_DATA 0x00000000 -#define DDRSS2_PHY_577_DATA 0x00000000 -#define DDRSS2_PHY_578_DATA 0x00000104 -#define DDRSS2_PHY_579_DATA 0x00000120 -#define DDRSS2_PHY_580_DATA 0x00000000 -#define DDRSS2_PHY_581_DATA 0x00000000 -#define DDRSS2_PHY_582_DATA 0x00000000 -#define DDRSS2_PHY_583_DATA 0x00000000 -#define DDRSS2_PHY_584_DATA 0x00000000 -#define DDRSS2_PHY_585_DATA 0x00000000 -#define DDRSS2_PHY_586_DATA 0x00000000 -#define DDRSS2_PHY_587_DATA 0x00000001 -#define DDRSS2_PHY_588_DATA 0x07FF0000 -#define DDRSS2_PHY_589_DATA 0x0080081F -#define DDRSS2_PHY_590_DATA 0x00081020 -#define DDRSS2_PHY_591_DATA 0x04010000 -#define DDRSS2_PHY_592_DATA 0x00000000 -#define DDRSS2_PHY_593_DATA 0x00000000 -#define DDRSS2_PHY_594_DATA 0x00000000 -#define DDRSS2_PHY_595_DATA 0x00000100 -#define DDRSS2_PHY_596_DATA 0x01CC0C01 -#define DDRSS2_PHY_597_DATA 0x1003CC0C -#define DDRSS2_PHY_598_DATA 0x20000140 -#define DDRSS2_PHY_599_DATA 0x07FF0200 -#define DDRSS2_PHY_600_DATA 0x0000DD01 -#define DDRSS2_PHY_601_DATA 0x10100303 -#define DDRSS2_PHY_602_DATA 0x10101010 -#define DDRSS2_PHY_603_DATA 0x10101010 -#define DDRSS2_PHY_604_DATA 0x00021010 -#define DDRSS2_PHY_605_DATA 0x00100010 -#define DDRSS2_PHY_606_DATA 0x00100010 -#define DDRSS2_PHY_607_DATA 0x00100010 -#define DDRSS2_PHY_608_DATA 0x00100010 -#define DDRSS2_PHY_609_DATA 0x00050010 -#define DDRSS2_PHY_610_DATA 0x51517041 -#define DDRSS2_PHY_611_DATA 0x31C06001 -#define DDRSS2_PHY_612_DATA 0x07AB0340 -#define DDRSS2_PHY_613_DATA 0x00C0C001 -#define DDRSS2_PHY_614_DATA 0x0E0D0001 -#define DDRSS2_PHY_615_DATA 0x10001000 -#define DDRSS2_PHY_616_DATA 0x0C083E42 -#define DDRSS2_PHY_617_DATA 0x0F0C3701 -#define DDRSS2_PHY_618_DATA 0x01000140 -#define DDRSS2_PHY_619_DATA 0x0C000420 -#define DDRSS2_PHY_620_DATA 0x00000198 -#define DDRSS2_PHY_621_DATA 0x0A0000D0 -#define DDRSS2_PHY_622_DATA 0x00030200 -#define DDRSS2_PHY_623_DATA 0x02800000 -#define DDRSS2_PHY_624_DATA 0x80800000 -#define DDRSS2_PHY_625_DATA 0x000E2010 -#define DDRSS2_PHY_626_DATA 0x76543210 -#define DDRSS2_PHY_627_DATA 0x00000008 -#define DDRSS2_PHY_628_DATA 0x02800280 -#define DDRSS2_PHY_629_DATA 0x02800280 -#define DDRSS2_PHY_630_DATA 0x02800280 -#define DDRSS2_PHY_631_DATA 0x02800280 -#define DDRSS2_PHY_632_DATA 0x00000280 -#define DDRSS2_PHY_633_DATA 0x0000A000 -#define DDRSS2_PHY_634_DATA 0x00A000A0 -#define DDRSS2_PHY_635_DATA 0x00A000A0 -#define DDRSS2_PHY_636_DATA 0x00A000A0 -#define DDRSS2_PHY_637_DATA 0x00A000A0 -#define DDRSS2_PHY_638_DATA 0x00A000A0 -#define DDRSS2_PHY_639_DATA 0x00A000A0 -#define DDRSS2_PHY_640_DATA 0x00A000A0 -#define DDRSS2_PHY_641_DATA 0x00A000A0 -#define DDRSS2_PHY_642_DATA 0x01C200A0 -#define DDRSS2_PHY_643_DATA 0x01A00005 -#define DDRSS2_PHY_644_DATA 0x00000000 -#define DDRSS2_PHY_645_DATA 0x00000000 -#define DDRSS2_PHY_646_DATA 0x00080200 -#define DDRSS2_PHY_647_DATA 0x00000000 -#define DDRSS2_PHY_648_DATA 0x20202000 -#define DDRSS2_PHY_649_DATA 0x20202020 -#define DDRSS2_PHY_650_DATA 0xF0F02020 -#define DDRSS2_PHY_651_DATA 0x00000000 -#define DDRSS2_PHY_652_DATA 0x00000000 -#define DDRSS2_PHY_653_DATA 0x00000000 -#define DDRSS2_PHY_654_DATA 0x00000000 -#define DDRSS2_PHY_655_DATA 0x00000000 -#define DDRSS2_PHY_656_DATA 0x00000000 -#define DDRSS2_PHY_657_DATA 0x00000000 -#define DDRSS2_PHY_658_DATA 0x00000000 -#define DDRSS2_PHY_659_DATA 0x00000000 -#define DDRSS2_PHY_660_DATA 0x00000000 -#define DDRSS2_PHY_661_DATA 0x00000000 -#define DDRSS2_PHY_662_DATA 0x00000000 -#define DDRSS2_PHY_663_DATA 0x00000000 -#define DDRSS2_PHY_664_DATA 0x00000000 -#define DDRSS2_PHY_665_DATA 0x00000000 -#define DDRSS2_PHY_666_DATA 0x00000000 -#define DDRSS2_PHY_667_DATA 0x00000000 -#define DDRSS2_PHY_668_DATA 0x00000000 -#define DDRSS2_PHY_669_DATA 0x00000000 -#define DDRSS2_PHY_670_DATA 0x00000000 -#define DDRSS2_PHY_671_DATA 0x00000000 -#define DDRSS2_PHY_672_DATA 0x00000000 -#define DDRSS2_PHY_673_DATA 0x00000000 -#define DDRSS2_PHY_674_DATA 0x00000000 -#define DDRSS2_PHY_675_DATA 0x00000000 -#define DDRSS2_PHY_676_DATA 0x00000000 -#define DDRSS2_PHY_677_DATA 0x00000000 -#define DDRSS2_PHY_678_DATA 0x00000000 -#define DDRSS2_PHY_679_DATA 0x00000000 -#define DDRSS2_PHY_680_DATA 0x00000000 -#define DDRSS2_PHY_681_DATA 0x00000000 -#define DDRSS2_PHY_682_DATA 0x00000000 -#define DDRSS2_PHY_683_DATA 0x00000000 -#define DDRSS2_PHY_684_DATA 0x00000000 -#define DDRSS2_PHY_685_DATA 0x00000000 -#define DDRSS2_PHY_686_DATA 0x00000000 -#define DDRSS2_PHY_687_DATA 0x00000000 -#define DDRSS2_PHY_688_DATA 0x00000000 -#define DDRSS2_PHY_689_DATA 0x00000000 -#define DDRSS2_PHY_690_DATA 0x00000000 -#define DDRSS2_PHY_691_DATA 0x00000000 -#define DDRSS2_PHY_692_DATA 0x00000000 -#define DDRSS2_PHY_693_DATA 0x00000000 -#define DDRSS2_PHY_694_DATA 0x00000000 -#define DDRSS2_PHY_695_DATA 0x00000000 -#define DDRSS2_PHY_696_DATA 0x00000000 -#define DDRSS2_PHY_697_DATA 0x00000000 -#define DDRSS2_PHY_698_DATA 0x00000000 -#define DDRSS2_PHY_699_DATA 0x00000000 -#define DDRSS2_PHY_700_DATA 0x00000000 -#define DDRSS2_PHY_701_DATA 0x00000000 -#define DDRSS2_PHY_702_DATA 0x00000000 -#define DDRSS2_PHY_703_DATA 0x00000000 -#define DDRSS2_PHY_704_DATA 0x00000000 -#define DDRSS2_PHY_705_DATA 0x00000000 -#define DDRSS2_PHY_706_DATA 0x00000000 -#define DDRSS2_PHY_707_DATA 0x00000000 -#define DDRSS2_PHY_708_DATA 0x00000000 -#define DDRSS2_PHY_709_DATA 0x00000000 -#define DDRSS2_PHY_710_DATA 0x00000000 -#define DDRSS2_PHY_711_DATA 0x00000000 -#define DDRSS2_PHY_712_DATA 0x00000000 -#define DDRSS2_PHY_713_DATA 0x00000000 -#define DDRSS2_PHY_714_DATA 0x00000000 -#define DDRSS2_PHY_715_DATA 0x00000000 -#define DDRSS2_PHY_716_DATA 0x00000000 -#define DDRSS2_PHY_717_DATA 0x00000000 -#define DDRSS2_PHY_718_DATA 0x00000000 -#define DDRSS2_PHY_719_DATA 0x00000000 -#define DDRSS2_PHY_720_DATA 0x00000000 -#define DDRSS2_PHY_721_DATA 0x00000000 -#define DDRSS2_PHY_722_DATA 0x00000000 -#define DDRSS2_PHY_723_DATA 0x00000000 -#define DDRSS2_PHY_724_DATA 0x00000000 -#define DDRSS2_PHY_725_DATA 0x00000000 -#define DDRSS2_PHY_726_DATA 0x00000000 -#define DDRSS2_PHY_727_DATA 0x00000000 -#define DDRSS2_PHY_728_DATA 0x00000000 -#define DDRSS2_PHY_729_DATA 0x00000000 -#define DDRSS2_PHY_730_DATA 0x00000000 -#define DDRSS2_PHY_731_DATA 0x00000000 -#define DDRSS2_PHY_732_DATA 0x00000000 -#define DDRSS2_PHY_733_DATA 0x00000000 -#define DDRSS2_PHY_734_DATA 0x00000000 -#define DDRSS2_PHY_735_DATA 0x00000000 -#define DDRSS2_PHY_736_DATA 0x00000000 -#define DDRSS2_PHY_737_DATA 0x00000000 -#define DDRSS2_PHY_738_DATA 0x00000000 -#define DDRSS2_PHY_739_DATA 0x00000000 -#define DDRSS2_PHY_740_DATA 0x00000000 -#define DDRSS2_PHY_741_DATA 0x00000000 -#define DDRSS2_PHY_742_DATA 0x00000000 -#define DDRSS2_PHY_743_DATA 0x00000000 -#define DDRSS2_PHY_744_DATA 0x00000000 -#define DDRSS2_PHY_745_DATA 0x00000000 -#define DDRSS2_PHY_746_DATA 0x00000000 -#define DDRSS2_PHY_747_DATA 0x00000000 -#define DDRSS2_PHY_748_DATA 0x00000000 -#define DDRSS2_PHY_749_DATA 0x00000000 -#define DDRSS2_PHY_750_DATA 0x00000000 -#define DDRSS2_PHY_751_DATA 0x00000000 -#define DDRSS2_PHY_752_DATA 0x00000000 -#define DDRSS2_PHY_753_DATA 0x00000000 -#define DDRSS2_PHY_754_DATA 0x00000000 -#define DDRSS2_PHY_755_DATA 0x00000000 -#define DDRSS2_PHY_756_DATA 0x00000000 -#define DDRSS2_PHY_757_DATA 0x00000000 -#define DDRSS2_PHY_758_DATA 0x00000000 -#define DDRSS2_PHY_759_DATA 0x00000000 -#define DDRSS2_PHY_760_DATA 0x00000000 -#define DDRSS2_PHY_761_DATA 0x00000000 -#define DDRSS2_PHY_762_DATA 0x00000000 -#define DDRSS2_PHY_763_DATA 0x00000000 -#define DDRSS2_PHY_764_DATA 0x00000000 -#define DDRSS2_PHY_765_DATA 0x00000000 -#define DDRSS2_PHY_766_DATA 0x00000000 -#define DDRSS2_PHY_767_DATA 0x00000000 -#define DDRSS2_PHY_768_DATA 0x000004F0 -#define DDRSS2_PHY_769_DATA 0x00000000 -#define DDRSS2_PHY_770_DATA 0x00030200 -#define DDRSS2_PHY_771_DATA 0x00000000 -#define DDRSS2_PHY_772_DATA 0x00000000 -#define DDRSS2_PHY_773_DATA 0x01030000 -#define DDRSS2_PHY_774_DATA 0x00010000 -#define DDRSS2_PHY_775_DATA 0x01030004 -#define DDRSS2_PHY_776_DATA 0x01000000 -#define DDRSS2_PHY_777_DATA 0x00000000 -#define DDRSS2_PHY_778_DATA 0x00000000 -#define DDRSS2_PHY_779_DATA 0x01000001 -#define DDRSS2_PHY_780_DATA 0x00000100 -#define DDRSS2_PHY_781_DATA 0x000800C0 -#define DDRSS2_PHY_782_DATA 0x060100CC -#define DDRSS2_PHY_783_DATA 0x00030066 -#define DDRSS2_PHY_784_DATA 0x00000000 -#define DDRSS2_PHY_785_DATA 0x00000301 -#define DDRSS2_PHY_786_DATA 0x0000AAAA -#define DDRSS2_PHY_787_DATA 0x00005555 -#define DDRSS2_PHY_788_DATA 0x0000B5B5 -#define DDRSS2_PHY_789_DATA 0x00004A4A -#define DDRSS2_PHY_790_DATA 0x00005656 -#define DDRSS2_PHY_791_DATA 0x0000A9A9 -#define DDRSS2_PHY_792_DATA 0x0000A9A9 -#define DDRSS2_PHY_793_DATA 0x0000B5B5 -#define DDRSS2_PHY_794_DATA 0x00000000 -#define DDRSS2_PHY_795_DATA 0x00000000 -#define DDRSS2_PHY_796_DATA 0x2A000000 -#define DDRSS2_PHY_797_DATA 0x00000808 -#define DDRSS2_PHY_798_DATA 0x0F000000 -#define DDRSS2_PHY_799_DATA 0x00000F0F -#define DDRSS2_PHY_800_DATA 0x10400000 -#define DDRSS2_PHY_801_DATA 0x0C002006 -#define DDRSS2_PHY_802_DATA 0x00000000 -#define DDRSS2_PHY_803_DATA 0x00000000 -#define DDRSS2_PHY_804_DATA 0x55555555 -#define DDRSS2_PHY_805_DATA 0xAAAAAAAA -#define DDRSS2_PHY_806_DATA 0x55555555 -#define DDRSS2_PHY_807_DATA 0xAAAAAAAA -#define DDRSS2_PHY_808_DATA 0x00005555 -#define DDRSS2_PHY_809_DATA 0x01000100 -#define DDRSS2_PHY_810_DATA 0x00800180 -#define DDRSS2_PHY_811_DATA 0x00000000 -#define DDRSS2_PHY_812_DATA 0x00000000 -#define DDRSS2_PHY_813_DATA 0x00000000 -#define DDRSS2_PHY_814_DATA 0x00000000 -#define DDRSS2_PHY_815_DATA 0x00000000 -#define DDRSS2_PHY_816_DATA 0x00000000 -#define DDRSS2_PHY_817_DATA 0x00000000 -#define DDRSS2_PHY_818_DATA 0x00000000 -#define DDRSS2_PHY_819_DATA 0x00000000 -#define DDRSS2_PHY_820_DATA 0x00000000 -#define DDRSS2_PHY_821_DATA 0x00000000 -#define DDRSS2_PHY_822_DATA 0x00000000 -#define DDRSS2_PHY_823_DATA 0x00000000 -#define DDRSS2_PHY_824_DATA 0x00000000 -#define DDRSS2_PHY_825_DATA 0x00000000 -#define DDRSS2_PHY_826_DATA 0x00000000 -#define DDRSS2_PHY_827_DATA 0x00000000 -#define DDRSS2_PHY_828_DATA 0x00000000 -#define DDRSS2_PHY_829_DATA 0x00000000 -#define DDRSS2_PHY_830_DATA 0x00000000 -#define DDRSS2_PHY_831_DATA 0x00000000 -#define DDRSS2_PHY_832_DATA 0x00000000 -#define DDRSS2_PHY_833_DATA 0x00000000 -#define DDRSS2_PHY_834_DATA 0x00000104 -#define DDRSS2_PHY_835_DATA 0x00000120 -#define DDRSS2_PHY_836_DATA 0x00000000 -#define DDRSS2_PHY_837_DATA 0x00000000 -#define DDRSS2_PHY_838_DATA 0x00000000 -#define DDRSS2_PHY_839_DATA 0x00000000 -#define DDRSS2_PHY_840_DATA 0x00000000 -#define DDRSS2_PHY_841_DATA 0x00000000 -#define DDRSS2_PHY_842_DATA 0x00000000 -#define DDRSS2_PHY_843_DATA 0x00000001 -#define DDRSS2_PHY_844_DATA 0x07FF0000 -#define DDRSS2_PHY_845_DATA 0x0080081F -#define DDRSS2_PHY_846_DATA 0x00081020 -#define DDRSS2_PHY_847_DATA 0x04010000 -#define DDRSS2_PHY_848_DATA 0x00000000 -#define DDRSS2_PHY_849_DATA 0x00000000 -#define DDRSS2_PHY_850_DATA 0x00000000 -#define DDRSS2_PHY_851_DATA 0x00000100 -#define DDRSS2_PHY_852_DATA 0x01CC0C01 -#define DDRSS2_PHY_853_DATA 0x1003CC0C -#define DDRSS2_PHY_854_DATA 0x20000140 -#define DDRSS2_PHY_855_DATA 0x07FF0200 -#define DDRSS2_PHY_856_DATA 0x0000DD01 -#define DDRSS2_PHY_857_DATA 0x10100303 -#define DDRSS2_PHY_858_DATA 0x10101010 -#define DDRSS2_PHY_859_DATA 0x10101010 -#define DDRSS2_PHY_860_DATA 0x00021010 -#define DDRSS2_PHY_861_DATA 0x00100010 -#define DDRSS2_PHY_862_DATA 0x00100010 -#define DDRSS2_PHY_863_DATA 0x00100010 -#define DDRSS2_PHY_864_DATA 0x00100010 -#define DDRSS2_PHY_865_DATA 0x00050010 -#define DDRSS2_PHY_866_DATA 0x51517041 -#define DDRSS2_PHY_867_DATA 0x31C06001 -#define DDRSS2_PHY_868_DATA 0x07AB0340 -#define DDRSS2_PHY_869_DATA 0x00C0C001 -#define DDRSS2_PHY_870_DATA 0x0E0D0001 -#define DDRSS2_PHY_871_DATA 0x10001000 -#define DDRSS2_PHY_872_DATA 0x0C083E42 -#define DDRSS2_PHY_873_DATA 0x0F0C3701 -#define DDRSS2_PHY_874_DATA 0x01000140 -#define DDRSS2_PHY_875_DATA 0x0C000420 -#define DDRSS2_PHY_876_DATA 0x00000198 -#define DDRSS2_PHY_877_DATA 0x0A0000D0 -#define DDRSS2_PHY_878_DATA 0x00030200 -#define DDRSS2_PHY_879_DATA 0x02800000 -#define DDRSS2_PHY_880_DATA 0x80800000 -#define DDRSS2_PHY_881_DATA 0x000E2010 -#define DDRSS2_PHY_882_DATA 0x76543210 -#define DDRSS2_PHY_883_DATA 0x00000008 -#define DDRSS2_PHY_884_DATA 0x02800280 -#define DDRSS2_PHY_885_DATA 0x02800280 -#define DDRSS2_PHY_886_DATA 0x02800280 -#define DDRSS2_PHY_887_DATA 0x02800280 -#define DDRSS2_PHY_888_DATA 0x00000280 -#define DDRSS2_PHY_889_DATA 0x0000A000 -#define DDRSS2_PHY_890_DATA 0x00A000A0 -#define DDRSS2_PHY_891_DATA 0x00A000A0 -#define DDRSS2_PHY_892_DATA 0x00A000A0 -#define DDRSS2_PHY_893_DATA 0x00A000A0 -#define DDRSS2_PHY_894_DATA 0x00A000A0 -#define DDRSS2_PHY_895_DATA 0x00A000A0 -#define DDRSS2_PHY_896_DATA 0x00A000A0 -#define DDRSS2_PHY_897_DATA 0x00A000A0 -#define DDRSS2_PHY_898_DATA 0x01C200A0 -#define DDRSS2_PHY_899_DATA 0x01A00005 -#define DDRSS2_PHY_900_DATA 0x00000000 -#define DDRSS2_PHY_901_DATA 0x00000000 -#define DDRSS2_PHY_902_DATA 0x00080200 -#define DDRSS2_PHY_903_DATA 0x00000000 -#define DDRSS2_PHY_904_DATA 0x20202000 -#define DDRSS2_PHY_905_DATA 0x20202020 -#define DDRSS2_PHY_906_DATA 0xF0F02020 -#define DDRSS2_PHY_907_DATA 0x00000000 -#define DDRSS2_PHY_908_DATA 0x00000000 -#define DDRSS2_PHY_909_DATA 0x00000000 -#define DDRSS2_PHY_910_DATA 0x00000000 -#define DDRSS2_PHY_911_DATA 0x00000000 -#define DDRSS2_PHY_912_DATA 0x00000000 -#define DDRSS2_PHY_913_DATA 0x00000000 -#define DDRSS2_PHY_914_DATA 0x00000000 -#define DDRSS2_PHY_915_DATA 0x00000000 -#define DDRSS2_PHY_916_DATA 0x00000000 -#define DDRSS2_PHY_917_DATA 0x00000000 -#define DDRSS2_PHY_918_DATA 0x00000000 -#define DDRSS2_PHY_919_DATA 0x00000000 -#define DDRSS2_PHY_920_DATA 0x00000000 -#define DDRSS2_PHY_921_DATA 0x00000000 -#define DDRSS2_PHY_922_DATA 0x00000000 -#define DDRSS2_PHY_923_DATA 0x00000000 -#define DDRSS2_PHY_924_DATA 0x00000000 -#define DDRSS2_PHY_925_DATA 0x00000000 -#define DDRSS2_PHY_926_DATA 0x00000000 -#define DDRSS2_PHY_927_DATA 0x00000000 -#define DDRSS2_PHY_928_DATA 0x00000000 -#define DDRSS2_PHY_929_DATA 0x00000000 -#define DDRSS2_PHY_930_DATA 0x00000000 -#define DDRSS2_PHY_931_DATA 0x00000000 -#define DDRSS2_PHY_932_DATA 0x00000000 -#define DDRSS2_PHY_933_DATA 0x00000000 -#define DDRSS2_PHY_934_DATA 0x00000000 -#define DDRSS2_PHY_935_DATA 0x00000000 -#define DDRSS2_PHY_936_DATA 0x00000000 -#define DDRSS2_PHY_937_DATA 0x00000000 -#define DDRSS2_PHY_938_DATA 0x00000000 -#define DDRSS2_PHY_939_DATA 0x00000000 -#define DDRSS2_PHY_940_DATA 0x00000000 -#define DDRSS2_PHY_941_DATA 0x00000000 -#define DDRSS2_PHY_942_DATA 0x00000000 -#define DDRSS2_PHY_943_DATA 0x00000000 -#define DDRSS2_PHY_944_DATA 0x00000000 -#define DDRSS2_PHY_945_DATA 0x00000000 -#define DDRSS2_PHY_946_DATA 0x00000000 -#define DDRSS2_PHY_947_DATA 0x00000000 -#define DDRSS2_PHY_948_DATA 0x00000000 -#define DDRSS2_PHY_949_DATA 0x00000000 -#define DDRSS2_PHY_950_DATA 0x00000000 -#define DDRSS2_PHY_951_DATA 0x00000000 -#define DDRSS2_PHY_952_DATA 0x00000000 -#define DDRSS2_PHY_953_DATA 0x00000000 -#define DDRSS2_PHY_954_DATA 0x00000000 -#define DDRSS2_PHY_955_DATA 0x00000000 -#define DDRSS2_PHY_956_DATA 0x00000000 -#define DDRSS2_PHY_957_DATA 0x00000000 -#define DDRSS2_PHY_958_DATA 0x00000000 -#define DDRSS2_PHY_959_DATA 0x00000000 -#define DDRSS2_PHY_960_DATA 0x00000000 -#define DDRSS2_PHY_961_DATA 0x00000000 -#define DDRSS2_PHY_962_DATA 0x00000000 -#define DDRSS2_PHY_963_DATA 0x00000000 -#define DDRSS2_PHY_964_DATA 0x00000000 -#define DDRSS2_PHY_965_DATA 0x00000000 -#define DDRSS2_PHY_966_DATA 0x00000000 -#define DDRSS2_PHY_967_DATA 0x00000000 -#define DDRSS2_PHY_968_DATA 0x00000000 -#define DDRSS2_PHY_969_DATA 0x00000000 -#define DDRSS2_PHY_970_DATA 0x00000000 -#define DDRSS2_PHY_971_DATA 0x00000000 -#define DDRSS2_PHY_972_DATA 0x00000000 -#define DDRSS2_PHY_973_DATA 0x00000000 -#define DDRSS2_PHY_974_DATA 0x00000000 -#define DDRSS2_PHY_975_DATA 0x00000000 -#define DDRSS2_PHY_976_DATA 0x00000000 -#define DDRSS2_PHY_977_DATA 0x00000000 -#define DDRSS2_PHY_978_DATA 0x00000000 -#define DDRSS2_PHY_979_DATA 0x00000000 -#define DDRSS2_PHY_980_DATA 0x00000000 -#define DDRSS2_PHY_981_DATA 0x00000000 -#define DDRSS2_PHY_982_DATA 0x00000000 -#define DDRSS2_PHY_983_DATA 0x00000000 -#define DDRSS2_PHY_984_DATA 0x00000000 -#define DDRSS2_PHY_985_DATA 0x00000000 -#define DDRSS2_PHY_986_DATA 0x00000000 -#define DDRSS2_PHY_987_DATA 0x00000000 -#define DDRSS2_PHY_988_DATA 0x00000000 -#define DDRSS2_PHY_989_DATA 0x00000000 -#define DDRSS2_PHY_990_DATA 0x00000000 -#define DDRSS2_PHY_991_DATA 0x00000000 -#define DDRSS2_PHY_992_DATA 0x00000000 -#define DDRSS2_PHY_993_DATA 0x00000000 -#define DDRSS2_PHY_994_DATA 0x00000000 -#define DDRSS2_PHY_995_DATA 0x00000000 -#define DDRSS2_PHY_996_DATA 0x00000000 -#define DDRSS2_PHY_997_DATA 0x00000000 -#define DDRSS2_PHY_998_DATA 0x00000000 -#define DDRSS2_PHY_999_DATA 0x00000000 -#define DDRSS2_PHY_1000_DATA 0x00000000 -#define DDRSS2_PHY_1001_DATA 0x00000000 -#define DDRSS2_PHY_1002_DATA 0x00000000 -#define DDRSS2_PHY_1003_DATA 0x00000000 -#define DDRSS2_PHY_1004_DATA 0x00000000 -#define DDRSS2_PHY_1005_DATA 0x00000000 -#define DDRSS2_PHY_1006_DATA 0x00000000 -#define DDRSS2_PHY_1007_DATA 0x00000000 -#define DDRSS2_PHY_1008_DATA 0x00000000 -#define DDRSS2_PHY_1009_DATA 0x00000000 -#define DDRSS2_PHY_1010_DATA 0x00000000 -#define DDRSS2_PHY_1011_DATA 0x00000000 -#define DDRSS2_PHY_1012_DATA 0x00000000 -#define DDRSS2_PHY_1013_DATA 0x00000000 -#define DDRSS2_PHY_1014_DATA 0x00000000 -#define DDRSS2_PHY_1015_DATA 0x00000000 -#define DDRSS2_PHY_1016_DATA 0x00000000 -#define DDRSS2_PHY_1017_DATA 0x00000000 -#define DDRSS2_PHY_1018_DATA 0x00000000 -#define DDRSS2_PHY_1019_DATA 0x00000000 -#define DDRSS2_PHY_1020_DATA 0x00000000 -#define DDRSS2_PHY_1021_DATA 0x00000000 -#define DDRSS2_PHY_1022_DATA 0x00000000 -#define DDRSS2_PHY_1023_DATA 0x00000000 -#define DDRSS2_PHY_1024_DATA 0x00000000 -#define DDRSS2_PHY_1025_DATA 0x00000000 -#define DDRSS2_PHY_1026_DATA 0x00000000 -#define DDRSS2_PHY_1027_DATA 0x00000000 -#define DDRSS2_PHY_1028_DATA 0x00000000 -#define DDRSS2_PHY_1029_DATA 0x00000100 -#define DDRSS2_PHY_1030_DATA 0x00000200 -#define DDRSS2_PHY_1031_DATA 0x00000000 -#define DDRSS2_PHY_1032_DATA 0x00000000 -#define DDRSS2_PHY_1033_DATA 0x00000000 -#define DDRSS2_PHY_1034_DATA 0x00000000 -#define DDRSS2_PHY_1035_DATA 0x00400000 -#define DDRSS2_PHY_1036_DATA 0x00000080 -#define DDRSS2_PHY_1037_DATA 0x00DCBA98 -#define DDRSS2_PHY_1038_DATA 0x03000000 -#define DDRSS2_PHY_1039_DATA 0x00200000 -#define DDRSS2_PHY_1040_DATA 0x00000000 -#define DDRSS2_PHY_1041_DATA 0x00000000 -#define DDRSS2_PHY_1042_DATA 0x00000000 -#define DDRSS2_PHY_1043_DATA 0x00000000 -#define DDRSS2_PHY_1044_DATA 0x00000000 -#define DDRSS2_PHY_1045_DATA 0x0000002A -#define DDRSS2_PHY_1046_DATA 0x00000015 -#define DDRSS2_PHY_1047_DATA 0x00000015 -#define DDRSS2_PHY_1048_DATA 0x0000002A -#define DDRSS2_PHY_1049_DATA 0x00000033 -#define DDRSS2_PHY_1050_DATA 0x0000000C -#define DDRSS2_PHY_1051_DATA 0x0000000C -#define DDRSS2_PHY_1052_DATA 0x00000033 -#define DDRSS2_PHY_1053_DATA 0x00543210 -#define DDRSS2_PHY_1054_DATA 0x003F0000 -#define DDRSS2_PHY_1055_DATA 0x000F013F -#define DDRSS2_PHY_1056_DATA 0x20202003 -#define DDRSS2_PHY_1057_DATA 0x00202020 -#define DDRSS2_PHY_1058_DATA 0x20008008 -#define DDRSS2_PHY_1059_DATA 0x00000810 -#define DDRSS2_PHY_1060_DATA 0x00000F00 -#define DDRSS2_PHY_1061_DATA 0x00000000 -#define DDRSS2_PHY_1062_DATA 0x00000000 -#define DDRSS2_PHY_1063_DATA 0x00000000 -#define DDRSS2_PHY_1064_DATA 0x000305CC -#define DDRSS2_PHY_1065_DATA 0x00030000 -#define DDRSS2_PHY_1066_DATA 0x00000300 -#define DDRSS2_PHY_1067_DATA 0x00000300 -#define DDRSS2_PHY_1068_DATA 0x00000300 -#define DDRSS2_PHY_1069_DATA 0x00000300 -#define DDRSS2_PHY_1070_DATA 0x00000300 -#define DDRSS2_PHY_1071_DATA 0x42080010 -#define DDRSS2_PHY_1072_DATA 0x0000803E -#define DDRSS2_PHY_1073_DATA 0x00000001 -#define DDRSS2_PHY_1074_DATA 0x01000102 -#define DDRSS2_PHY_1075_DATA 0x00008000 -#define DDRSS2_PHY_1076_DATA 0x00000000 -#define DDRSS2_PHY_1077_DATA 0x00000000 -#define DDRSS2_PHY_1078_DATA 0x00000000 -#define DDRSS2_PHY_1079_DATA 0x00000000 -#define DDRSS2_PHY_1080_DATA 0x00000000 -#define DDRSS2_PHY_1081_DATA 0x00000000 -#define DDRSS2_PHY_1082_DATA 0x00000000 -#define DDRSS2_PHY_1083_DATA 0x00000000 -#define DDRSS2_PHY_1084_DATA 0x00000000 -#define DDRSS2_PHY_1085_DATA 0x00000000 -#define DDRSS2_PHY_1086_DATA 0x00000000 -#define DDRSS2_PHY_1087_DATA 0x00000000 -#define DDRSS2_PHY_1088_DATA 0x00000000 -#define DDRSS2_PHY_1089_DATA 0x00000000 -#define DDRSS2_PHY_1090_DATA 0x00000000 -#define DDRSS2_PHY_1091_DATA 0x00000000 -#define DDRSS2_PHY_1092_DATA 0x00000000 -#define DDRSS2_PHY_1093_DATA 0x00000000 -#define DDRSS2_PHY_1094_DATA 0x00000000 -#define DDRSS2_PHY_1095_DATA 0x00000000 -#define DDRSS2_PHY_1096_DATA 0x00000000 -#define DDRSS2_PHY_1097_DATA 0x00000000 -#define DDRSS2_PHY_1098_DATA 0x00000000 -#define DDRSS2_PHY_1099_DATA 0x00000000 -#define DDRSS2_PHY_1100_DATA 0x00000000 -#define DDRSS2_PHY_1101_DATA 0x00000000 -#define DDRSS2_PHY_1102_DATA 0x00000000 -#define DDRSS2_PHY_1103_DATA 0x00000000 -#define DDRSS2_PHY_1104_DATA 0x00000000 -#define DDRSS2_PHY_1105_DATA 0x00000000 -#define DDRSS2_PHY_1106_DATA 0x00000000 -#define DDRSS2_PHY_1107_DATA 0x00000000 -#define DDRSS2_PHY_1108_DATA 0x00000000 -#define DDRSS2_PHY_1109_DATA 0x00000000 -#define DDRSS2_PHY_1110_DATA 0x00000000 -#define DDRSS2_PHY_1111_DATA 0x00000000 -#define DDRSS2_PHY_1112_DATA 0x00000000 -#define DDRSS2_PHY_1113_DATA 0x00000000 -#define DDRSS2_PHY_1114_DATA 0x00000000 -#define DDRSS2_PHY_1115_DATA 0x00000000 -#define DDRSS2_PHY_1116_DATA 0x00000000 -#define DDRSS2_PHY_1117_DATA 0x00000000 -#define DDRSS2_PHY_1118_DATA 0x00000000 -#define DDRSS2_PHY_1119_DATA 0x00000000 -#define DDRSS2_PHY_1120_DATA 0x00000000 -#define DDRSS2_PHY_1121_DATA 0x00000000 -#define DDRSS2_PHY_1122_DATA 0x00000000 -#define DDRSS2_PHY_1123_DATA 0x00000000 -#define DDRSS2_PHY_1124_DATA 0x00000000 -#define DDRSS2_PHY_1125_DATA 0x00000000 -#define DDRSS2_PHY_1126_DATA 0x00000000 -#define DDRSS2_PHY_1127_DATA 0x00000000 -#define DDRSS2_PHY_1128_DATA 0x00000000 -#define DDRSS2_PHY_1129_DATA 0x00000000 -#define DDRSS2_PHY_1130_DATA 0x00000000 -#define DDRSS2_PHY_1131_DATA 0x00000000 -#define DDRSS2_PHY_1132_DATA 0x00000000 -#define DDRSS2_PHY_1133_DATA 0x00000000 -#define DDRSS2_PHY_1134_DATA 0x00000000 -#define DDRSS2_PHY_1135_DATA 0x00000000 -#define DDRSS2_PHY_1136_DATA 0x00000000 -#define DDRSS2_PHY_1137_DATA 0x00000000 -#define DDRSS2_PHY_1138_DATA 0x00000000 -#define DDRSS2_PHY_1139_DATA 0x00000000 -#define DDRSS2_PHY_1140_DATA 0x00000000 -#define DDRSS2_PHY_1141_DATA 0x00000000 -#define DDRSS2_PHY_1142_DATA 0x00000000 -#define DDRSS2_PHY_1143_DATA 0x00000000 -#define DDRSS2_PHY_1144_DATA 0x00000000 -#define DDRSS2_PHY_1145_DATA 0x00000000 -#define DDRSS2_PHY_1146_DATA 0x00000000 -#define DDRSS2_PHY_1147_DATA 0x00000000 -#define DDRSS2_PHY_1148_DATA 0x00000000 -#define DDRSS2_PHY_1149_DATA 0x00000000 -#define DDRSS2_PHY_1150_DATA 0x00000000 -#define DDRSS2_PHY_1151_DATA 0x00000000 -#define DDRSS2_PHY_1152_DATA 0x00000000 -#define DDRSS2_PHY_1153_DATA 0x00000000 -#define DDRSS2_PHY_1154_DATA 0x00000000 -#define DDRSS2_PHY_1155_DATA 0x00000000 -#define DDRSS2_PHY_1156_DATA 0x00000000 -#define DDRSS2_PHY_1157_DATA 0x00000000 -#define DDRSS2_PHY_1158_DATA 0x00000000 -#define DDRSS2_PHY_1159_DATA 0x00000000 -#define DDRSS2_PHY_1160_DATA 0x00000000 -#define DDRSS2_PHY_1161_DATA 0x00000000 -#define DDRSS2_PHY_1162_DATA 0x00000000 -#define DDRSS2_PHY_1163_DATA 0x00000000 -#define DDRSS2_PHY_1164_DATA 0x00000000 -#define DDRSS2_PHY_1165_DATA 0x00000000 -#define DDRSS2_PHY_1166_DATA 0x00000000 -#define DDRSS2_PHY_1167_DATA 0x00000000 -#define DDRSS2_PHY_1168_DATA 0x00000000 -#define DDRSS2_PHY_1169_DATA 0x00000000 -#define DDRSS2_PHY_1170_DATA 0x00000000 -#define DDRSS2_PHY_1171_DATA 0x00000000 -#define DDRSS2_PHY_1172_DATA 0x00000000 -#define DDRSS2_PHY_1173_DATA 0x00000000 -#define DDRSS2_PHY_1174_DATA 0x00000000 -#define DDRSS2_PHY_1175_DATA 0x00000000 -#define DDRSS2_PHY_1176_DATA 0x00000000 -#define DDRSS2_PHY_1177_DATA 0x00000000 -#define DDRSS2_PHY_1178_DATA 0x00000000 -#define DDRSS2_PHY_1179_DATA 0x00000000 -#define DDRSS2_PHY_1180_DATA 0x00000000 -#define DDRSS2_PHY_1181_DATA 0x00000000 -#define DDRSS2_PHY_1182_DATA 0x00000000 -#define DDRSS2_PHY_1183_DATA 0x00000000 -#define DDRSS2_PHY_1184_DATA 0x00000000 -#define DDRSS2_PHY_1185_DATA 0x00000000 -#define DDRSS2_PHY_1186_DATA 0x00000000 -#define DDRSS2_PHY_1187_DATA 0x00000000 -#define DDRSS2_PHY_1188_DATA 0x00000000 -#define DDRSS2_PHY_1189_DATA 0x00000000 -#define DDRSS2_PHY_1190_DATA 0x00000000 -#define DDRSS2_PHY_1191_DATA 0x00000000 -#define DDRSS2_PHY_1192_DATA 0x00000000 -#define DDRSS2_PHY_1193_DATA 0x00000000 -#define DDRSS2_PHY_1194_DATA 0x00000000 -#define DDRSS2_PHY_1195_DATA 0x00000000 -#define DDRSS2_PHY_1196_DATA 0x00000000 -#define DDRSS2_PHY_1197_DATA 0x00000000 -#define DDRSS2_PHY_1198_DATA 0x00000000 -#define DDRSS2_PHY_1199_DATA 0x00000000 -#define DDRSS2_PHY_1200_DATA 0x00000000 -#define DDRSS2_PHY_1201_DATA 0x00000000 -#define DDRSS2_PHY_1202_DATA 0x00000000 -#define DDRSS2_PHY_1203_DATA 0x00000000 -#define DDRSS2_PHY_1204_DATA 0x00000000 -#define DDRSS2_PHY_1205_DATA 0x00000000 -#define DDRSS2_PHY_1206_DATA 0x00000000 -#define DDRSS2_PHY_1207_DATA 0x00000000 -#define DDRSS2_PHY_1208_DATA 0x00000000 -#define DDRSS2_PHY_1209_DATA 0x00000000 -#define DDRSS2_PHY_1210_DATA 0x00000000 -#define DDRSS2_PHY_1211_DATA 0x00000000 -#define DDRSS2_PHY_1212_DATA 0x00000000 -#define DDRSS2_PHY_1213_DATA 0x00000000 -#define DDRSS2_PHY_1214_DATA 0x00000000 -#define DDRSS2_PHY_1215_DATA 0x00000000 -#define DDRSS2_PHY_1216_DATA 0x00000000 -#define DDRSS2_PHY_1217_DATA 0x00000000 -#define DDRSS2_PHY_1218_DATA 0x00000000 -#define DDRSS2_PHY_1219_DATA 0x00000000 -#define DDRSS2_PHY_1220_DATA 0x00000000 -#define DDRSS2_PHY_1221_DATA 0x00000000 -#define DDRSS2_PHY_1222_DATA 0x00000000 -#define DDRSS2_PHY_1223_DATA 0x00000000 -#define DDRSS2_PHY_1224_DATA 0x00000000 -#define DDRSS2_PHY_1225_DATA 0x00000000 -#define DDRSS2_PHY_1226_DATA 0x00000000 -#define DDRSS2_PHY_1227_DATA 0x00000000 -#define DDRSS2_PHY_1228_DATA 0x00000000 -#define DDRSS2_PHY_1229_DATA 0x00000000 -#define DDRSS2_PHY_1230_DATA 0x00000000 -#define DDRSS2_PHY_1231_DATA 0x00000000 -#define DDRSS2_PHY_1232_DATA 0x00000000 -#define DDRSS2_PHY_1233_DATA 0x00000000 -#define DDRSS2_PHY_1234_DATA 0x00000000 -#define DDRSS2_PHY_1235_DATA 0x00000000 -#define DDRSS2_PHY_1236_DATA 0x00000000 -#define DDRSS2_PHY_1237_DATA 0x00000000 -#define DDRSS2_PHY_1238_DATA 0x00000000 -#define DDRSS2_PHY_1239_DATA 0x00000000 -#define DDRSS2_PHY_1240_DATA 0x00000000 -#define DDRSS2_PHY_1241_DATA 0x00000000 -#define DDRSS2_PHY_1242_DATA 0x00000000 -#define DDRSS2_PHY_1243_DATA 0x00000000 -#define DDRSS2_PHY_1244_DATA 0x00000000 -#define DDRSS2_PHY_1245_DATA 0x00000000 -#define DDRSS2_PHY_1246_DATA 0x00000000 -#define DDRSS2_PHY_1247_DATA 0x00000000 -#define DDRSS2_PHY_1248_DATA 0x00000000 -#define DDRSS2_PHY_1249_DATA 0x00000000 -#define DDRSS2_PHY_1250_DATA 0x00000000 -#define DDRSS2_PHY_1251_DATA 0x00000000 -#define DDRSS2_PHY_1252_DATA 0x00000000 -#define DDRSS2_PHY_1253_DATA 0x00000000 -#define DDRSS2_PHY_1254_DATA 0x00000000 -#define DDRSS2_PHY_1255_DATA 0x00000000 -#define DDRSS2_PHY_1256_DATA 0x00000000 -#define DDRSS2_PHY_1257_DATA 0x00000000 -#define DDRSS2_PHY_1258_DATA 0x00000000 -#define DDRSS2_PHY_1259_DATA 0x00000000 -#define DDRSS2_PHY_1260_DATA 0x00000000 -#define DDRSS2_PHY_1261_DATA 0x00000000 -#define DDRSS2_PHY_1262_DATA 0x00000000 -#define DDRSS2_PHY_1263_DATA 0x00000000 -#define DDRSS2_PHY_1264_DATA 0x00000000 -#define DDRSS2_PHY_1265_DATA 0x00000000 -#define DDRSS2_PHY_1266_DATA 0x00000000 -#define DDRSS2_PHY_1267_DATA 0x00000000 -#define DDRSS2_PHY_1268_DATA 0x00000000 -#define DDRSS2_PHY_1269_DATA 0x00000000 -#define DDRSS2_PHY_1270_DATA 0x00000000 -#define DDRSS2_PHY_1271_DATA 0x00000000 -#define DDRSS2_PHY_1272_DATA 0x00000000 -#define DDRSS2_PHY_1273_DATA 0x00000000 -#define DDRSS2_PHY_1274_DATA 0x00000000 -#define DDRSS2_PHY_1275_DATA 0x00000000 -#define DDRSS2_PHY_1276_DATA 0x00000000 -#define DDRSS2_PHY_1277_DATA 0x00000000 -#define DDRSS2_PHY_1278_DATA 0x00000000 -#define DDRSS2_PHY_1279_DATA 0x00000000 -#define DDRSS2_PHY_1280_DATA 0x00000000 -#define DDRSS2_PHY_1281_DATA 0x00010100 -#define DDRSS2_PHY_1282_DATA 0x00000000 -#define DDRSS2_PHY_1283_DATA 0x00000000 -#define DDRSS2_PHY_1284_DATA 0x00050000 -#define DDRSS2_PHY_1285_DATA 0x04000000 -#define DDRSS2_PHY_1286_DATA 0x00000055 -#define DDRSS2_PHY_1287_DATA 0x00000000 -#define DDRSS2_PHY_1288_DATA 0x00000000 -#define DDRSS2_PHY_1289_DATA 0x00000000 -#define DDRSS2_PHY_1290_DATA 0x00000000 -#define DDRSS2_PHY_1291_DATA 0x00002001 -#define DDRSS2_PHY_1292_DATA 0x0000400F -#define DDRSS2_PHY_1293_DATA 0x50020028 -#define DDRSS2_PHY_1294_DATA 0x01010000 -#define DDRSS2_PHY_1295_DATA 0x80080001 -#define DDRSS2_PHY_1296_DATA 0x10200000 -#define DDRSS2_PHY_1297_DATA 0x00000008 -#define DDRSS2_PHY_1298_DATA 0x00000000 -#define DDRSS2_PHY_1299_DATA 0x01090E00 -#define DDRSS2_PHY_1300_DATA 0x00040101 -#define DDRSS2_PHY_1301_DATA 0x0000010F -#define DDRSS2_PHY_1302_DATA 0x00000000 -#define DDRSS2_PHY_1303_DATA 0x0000FFFF -#define DDRSS2_PHY_1304_DATA 0x00000000 -#define DDRSS2_PHY_1305_DATA 0x01010000 -#define DDRSS2_PHY_1306_DATA 0x01080402 -#define DDRSS2_PHY_1307_DATA 0x01200F02 -#define DDRSS2_PHY_1308_DATA 0x00194280 -#define DDRSS2_PHY_1309_DATA 0x00000004 -#define DDRSS2_PHY_1310_DATA 0x00042000 -#define DDRSS2_PHY_1311_DATA 0x00000000 -#define DDRSS2_PHY_1312_DATA 0x00000000 -#define DDRSS2_PHY_1313_DATA 0x00000000 -#define DDRSS2_PHY_1314_DATA 0x00000000 -#define DDRSS2_PHY_1315_DATA 0x00000000 -#define DDRSS2_PHY_1316_DATA 0x00000000 -#define DDRSS2_PHY_1317_DATA 0x01000000 -#define DDRSS2_PHY_1318_DATA 0x00000705 -#define DDRSS2_PHY_1319_DATA 0x00000054 -#define DDRSS2_PHY_1320_DATA 0x00030820 -#define DDRSS2_PHY_1321_DATA 0x00010820 -#define DDRSS2_PHY_1322_DATA 0x00010820 -#define DDRSS2_PHY_1323_DATA 0x00010820 -#define DDRSS2_PHY_1324_DATA 0x00010820 -#define DDRSS2_PHY_1325_DATA 0x00010820 -#define DDRSS2_PHY_1326_DATA 0x00010820 -#define DDRSS2_PHY_1327_DATA 0x00010820 -#define DDRSS2_PHY_1328_DATA 0x00010820 -#define DDRSS2_PHY_1329_DATA 0x00000000 -#define DDRSS2_PHY_1330_DATA 0x00000074 -#define DDRSS2_PHY_1331_DATA 0x00000400 -#define DDRSS2_PHY_1332_DATA 0x00000108 -#define DDRSS2_PHY_1333_DATA 0x00000000 -#define DDRSS2_PHY_1334_DATA 0x00000000 -#define DDRSS2_PHY_1335_DATA 0x00000000 -#define DDRSS2_PHY_1336_DATA 0x00000000 -#define DDRSS2_PHY_1337_DATA 0x00000000 -#define DDRSS2_PHY_1338_DATA 0x03000000 -#define DDRSS2_PHY_1339_DATA 0x00000000 -#define DDRSS2_PHY_1340_DATA 0x00000000 -#define DDRSS2_PHY_1341_DATA 0x00000000 -#define DDRSS2_PHY_1342_DATA 0x04102006 -#define DDRSS2_PHY_1343_DATA 0x00041020 -#define DDRSS2_PHY_1344_DATA 0x01C98C98 -#define DDRSS2_PHY_1345_DATA 0x3F400000 -#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F -#define DDRSS2_PHY_1347_DATA 0x0000001F -#define DDRSS2_PHY_1348_DATA 0x00000000 -#define DDRSS2_PHY_1349_DATA 0x00000000 -#define DDRSS2_PHY_1350_DATA 0x00000000 -#define DDRSS2_PHY_1351_DATA 0x00010000 -#define DDRSS2_PHY_1352_DATA 0x00000000 -#define DDRSS2_PHY_1353_DATA 0x00000000 -#define DDRSS2_PHY_1354_DATA 0x00000000 -#define DDRSS2_PHY_1355_DATA 0x00000000 -#define DDRSS2_PHY_1356_DATA 0x76543210 -#define DDRSS2_PHY_1357_DATA 0x00010198 -#define DDRSS2_PHY_1358_DATA 0x00000000 -#define DDRSS2_PHY_1359_DATA 0x00000000 -#define DDRSS2_PHY_1360_DATA 0x00000000 -#define DDRSS2_PHY_1361_DATA 0x00040700 -#define DDRSS2_PHY_1362_DATA 0x00000000 -#define DDRSS2_PHY_1363_DATA 0x00000000 -#define DDRSS2_PHY_1364_DATA 0x00000000 -#define DDRSS2_PHY_1365_DATA 0x00000000 -#define DDRSS2_PHY_1366_DATA 0x00000000 -#define DDRSS2_PHY_1367_DATA 0x00000002 -#define DDRSS2_PHY_1368_DATA 0x00000000 -#define DDRSS2_PHY_1369_DATA 0x00000000 -#define DDRSS2_PHY_1370_DATA 0x00000000 -#define DDRSS2_PHY_1371_DATA 0x00000000 -#define DDRSS2_PHY_1372_DATA 0x00000000 -#define DDRSS2_PHY_1373_DATA 0x00000000 -#define DDRSS2_PHY_1374_DATA 0x00080000 -#define DDRSS2_PHY_1375_DATA 0x000007FF -#define DDRSS2_PHY_1376_DATA 0x00000000 -#define DDRSS2_PHY_1377_DATA 0x00000000 -#define DDRSS2_PHY_1378_DATA 0x00000000 -#define DDRSS2_PHY_1379_DATA 0x00000000 -#define DDRSS2_PHY_1380_DATA 0x00000000 -#define DDRSS2_PHY_1381_DATA 0x00000000 -#define DDRSS2_PHY_1382_DATA 0x000FFFFF -#define DDRSS2_PHY_1383_DATA 0x000FFFFF -#define DDRSS2_PHY_1384_DATA 0x0000FFFF -#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0 -#define DDRSS2_PHY_1386_DATA 0x030FFFFF -#define DDRSS2_PHY_1387_DATA 0x01FFFFFF -#define DDRSS2_PHY_1388_DATA 0x0000FFFF -#define DDRSS2_PHY_1389_DATA 0x00000000 -#define DDRSS2_PHY_1390_DATA 0x00000000 -#define DDRSS2_PHY_1391_DATA 0x00000000 -#define DDRSS2_PHY_1392_DATA 0x00000000 -#define DDRSS2_PHY_1393_DATA 0x0001F7C0 -#define DDRSS2_PHY_1394_DATA 0x00000003 -#define DDRSS2_PHY_1395_DATA 0x00000000 -#define DDRSS2_PHY_1396_DATA 0x00001142 -#define DDRSS2_PHY_1397_DATA 0x010207AB -#define DDRSS2_PHY_1398_DATA 0x01000080 -#define DDRSS2_PHY_1399_DATA 0x03900390 -#define DDRSS2_PHY_1400_DATA 0x03900390 -#define DDRSS2_PHY_1401_DATA 0x00000390 -#define DDRSS2_PHY_1402_DATA 0x00000390 -#define DDRSS2_PHY_1403_DATA 0x00000390 -#define DDRSS2_PHY_1404_DATA 0x00000390 -#define DDRSS2_PHY_1405_DATA 0x00000005 -#define DDRSS2_PHY_1406_DATA 0x01813FCC -#define DDRSS2_PHY_1407_DATA 0x000000CC -#define DDRSS2_PHY_1408_DATA 0x0C000DFF -#define DDRSS2_PHY_1409_DATA 0x30000DFF -#define DDRSS2_PHY_1410_DATA 0x3F0DFF11 -#define DDRSS2_PHY_1411_DATA 0x000100F0 -#define DDRSS2_PHY_1412_DATA 0x780DFFCC -#define DDRSS2_PHY_1413_DATA 0x00007E31 -#define DDRSS2_PHY_1414_DATA 0x000CBF11 -#define DDRSS2_PHY_1415_DATA 0x01990010 -#define DDRSS2_PHY_1416_DATA 0x000CBF11 -#define DDRSS2_PHY_1417_DATA 0x01990010 -#define DDRSS2_PHY_1418_DATA 0x3F0DFF11 -#define DDRSS2_PHY_1419_DATA 0x00EF00F0 -#define DDRSS2_PHY_1420_DATA 0x3F0DFF11 -#define DDRSS2_PHY_1421_DATA 0x01FF00F0 -#define DDRSS2_PHY_1422_DATA 0x20040006 - -#define DDRSS3_CTL_00_DATA 0x00000B00 -#define DDRSS3_CTL_01_DATA 0x00000000 -#define DDRSS3_CTL_02_DATA 0x00000000 -#define DDRSS3_CTL_03_DATA 0x00000000 -#define DDRSS3_CTL_04_DATA 0x00000000 -#define DDRSS3_CTL_05_DATA 0x00000000 -#define DDRSS3_CTL_06_DATA 0x00000000 -#define DDRSS3_CTL_07_DATA 0x00002AF8 -#define DDRSS3_CTL_08_DATA 0x0001ADAF -#define DDRSS3_CTL_09_DATA 0x00000005 -#define DDRSS3_CTL_10_DATA 0x0000006E -#define DDRSS3_CTL_11_DATA 0x000681C8 -#define DDRSS3_CTL_12_DATA 0x004111C9 -#define DDRSS3_CTL_13_DATA 0x00000005 -#define DDRSS3_CTL_14_DATA 0x000010A9 -#define DDRSS3_CTL_15_DATA 0x000681C8 -#define DDRSS3_CTL_16_DATA 0x004111C9 -#define DDRSS3_CTL_17_DATA 0x00000005 -#define DDRSS3_CTL_18_DATA 0x000010A9 -#define DDRSS3_CTL_19_DATA 0x01010000 -#define DDRSS3_CTL_20_DATA 0x02011001 -#define DDRSS3_CTL_21_DATA 0x02010000 -#define DDRSS3_CTL_22_DATA 0x00020100 -#define DDRSS3_CTL_23_DATA 0x0000000B -#define DDRSS3_CTL_24_DATA 0x0000001C -#define DDRSS3_CTL_25_DATA 0x00000000 -#define DDRSS3_CTL_26_DATA 0x00000000 -#define DDRSS3_CTL_27_DATA 0x03020200 -#define DDRSS3_CTL_28_DATA 0x00005656 -#define DDRSS3_CTL_29_DATA 0x00100000 -#define DDRSS3_CTL_30_DATA 0x00000000 -#define DDRSS3_CTL_31_DATA 0x00000000 -#define DDRSS3_CTL_32_DATA 0x00000000 -#define DDRSS3_CTL_33_DATA 0x00000000 -#define DDRSS3_CTL_34_DATA 0x040C0000 -#define DDRSS3_CTL_35_DATA 0x12481248 -#define DDRSS3_CTL_36_DATA 0x00050804 -#define DDRSS3_CTL_37_DATA 0x09040008 -#define DDRSS3_CTL_38_DATA 0x15000204 -#define DDRSS3_CTL_39_DATA 0x1760008B -#define DDRSS3_CTL_40_DATA 0x1500422B -#define DDRSS3_CTL_41_DATA 0x1760008B -#define DDRSS3_CTL_42_DATA 0x2000422B -#define DDRSS3_CTL_43_DATA 0x000A0A09 -#define DDRSS3_CTL_44_DATA 0x0400078A -#define DDRSS3_CTL_45_DATA 0x1E161104 -#define DDRSS3_CTL_46_DATA 0x10012458 -#define DDRSS3_CTL_47_DATA 0x1E161110 -#define DDRSS3_CTL_48_DATA 0x10012458 -#define DDRSS3_CTL_49_DATA 0x02030410 -#define DDRSS3_CTL_50_DATA 0x2C040500 -#define DDRSS3_CTL_51_DATA 0x08292C29 -#define DDRSS3_CTL_52_DATA 0x14000E0A -#define DDRSS3_CTL_53_DATA 0x04010A0A -#define DDRSS3_CTL_54_DATA 0x01010004 -#define DDRSS3_CTL_55_DATA 0x04545408 -#define DDRSS3_CTL_56_DATA 0x04313104 -#define DDRSS3_CTL_57_DATA 0x00003131 -#define DDRSS3_CTL_58_DATA 0x00010100 -#define DDRSS3_CTL_59_DATA 0x03010000 -#define DDRSS3_CTL_60_DATA 0x00001508 -#define DDRSS3_CTL_61_DATA 0x000000CE -#define DDRSS3_CTL_62_DATA 0x0000032B -#define DDRSS3_CTL_63_DATA 0x00002073 -#define DDRSS3_CTL_64_DATA 0x0000032B -#define DDRSS3_CTL_65_DATA 0x00002073 -#define DDRSS3_CTL_66_DATA 0x00000005 -#define DDRSS3_CTL_67_DATA 0x00050000 -#define DDRSS3_CTL_68_DATA 0x00CB0012 -#define DDRSS3_CTL_69_DATA 0x00CB0408 -#define DDRSS3_CTL_70_DATA 0x00400408 -#define DDRSS3_CTL_71_DATA 0x00120103 -#define DDRSS3_CTL_72_DATA 0x00100005 -#define DDRSS3_CTL_73_DATA 0x2F080010 -#define DDRSS3_CTL_74_DATA 0x0505012F -#define DDRSS3_CTL_75_DATA 0x0401030A -#define DDRSS3_CTL_76_DATA 0x041E100B -#define DDRSS3_CTL_77_DATA 0x100B0401 -#define DDRSS3_CTL_78_DATA 0x0001041E -#define DDRSS3_CTL_79_DATA 0x00160016 -#define DDRSS3_CTL_80_DATA 0x033B033B -#define DDRSS3_CTL_81_DATA 0x033B033B -#define DDRSS3_CTL_82_DATA 0x03050505 -#define DDRSS3_CTL_83_DATA 0x03010303 -#define DDRSS3_CTL_84_DATA 0x200B100B -#define DDRSS3_CTL_85_DATA 0x04041004 -#define DDRSS3_CTL_86_DATA 0x200B100B -#define DDRSS3_CTL_87_DATA 0x04041004 -#define DDRSS3_CTL_88_DATA 0x03010000 -#define DDRSS3_CTL_89_DATA 0x00010000 -#define DDRSS3_CTL_90_DATA 0x00000000 -#define DDRSS3_CTL_91_DATA 0x00000000 -#define DDRSS3_CTL_92_DATA 0x01000000 -#define DDRSS3_CTL_93_DATA 0x80104002 -#define DDRSS3_CTL_94_DATA 0x00000000 -#define DDRSS3_CTL_95_DATA 0x00040005 -#define DDRSS3_CTL_96_DATA 0x00000000 -#define DDRSS3_CTL_97_DATA 0x00050000 -#define DDRSS3_CTL_98_DATA 0x00000004 -#define DDRSS3_CTL_99_DATA 0x00000000 -#define DDRSS3_CTL_100_DATA 0x00040005 -#define DDRSS3_CTL_101_DATA 0x00000000 -#define DDRSS3_CTL_102_DATA 0x00003380 -#define DDRSS3_CTL_103_DATA 0x00003380 -#define DDRSS3_CTL_104_DATA 0x00003380 -#define DDRSS3_CTL_105_DATA 0x00003380 -#define DDRSS3_CTL_106_DATA 0x00003380 -#define DDRSS3_CTL_107_DATA 0x00000000 -#define DDRSS3_CTL_108_DATA 0x000005A2 -#define DDRSS3_CTL_109_DATA 0x00081CC0 -#define DDRSS3_CTL_110_DATA 0x00081CC0 -#define DDRSS3_CTL_111_DATA 0x00081CC0 -#define DDRSS3_CTL_112_DATA 0x00081CC0 -#define DDRSS3_CTL_113_DATA 0x00081CC0 -#define DDRSS3_CTL_114_DATA 0x00000000 -#define DDRSS3_CTL_115_DATA 0x0000E325 -#define DDRSS3_CTL_116_DATA 0x00081CC0 -#define DDRSS3_CTL_117_DATA 0x00081CC0 -#define DDRSS3_CTL_118_DATA 0x00081CC0 -#define DDRSS3_CTL_119_DATA 0x00081CC0 -#define DDRSS3_CTL_120_DATA 0x00081CC0 -#define DDRSS3_CTL_121_DATA 0x00000000 -#define DDRSS3_CTL_122_DATA 0x0000E325 -#define DDRSS3_CTL_123_DATA 0x00000000 -#define DDRSS3_CTL_124_DATA 0x00000000 -#define DDRSS3_CTL_125_DATA 0x00000000 -#define DDRSS3_CTL_126_DATA 0x00000000 -#define DDRSS3_CTL_127_DATA 0x00000000 -#define DDRSS3_CTL_128_DATA 0x00000000 -#define DDRSS3_CTL_129_DATA 0x00000000 -#define DDRSS3_CTL_130_DATA 0x00000000 -#define DDRSS3_CTL_131_DATA 0x0B030500 -#define DDRSS3_CTL_132_DATA 0x00040B04 -#define DDRSS3_CTL_133_DATA 0x0A090000 -#define DDRSS3_CTL_134_DATA 0x0A090701 -#define DDRSS3_CTL_135_DATA 0x0900000E -#define DDRSS3_CTL_136_DATA 0x0907010A -#define DDRSS3_CTL_137_DATA 0x00000E0A -#define DDRSS3_CTL_138_DATA 0x07010A09 -#define DDRSS3_CTL_139_DATA 0x000E0A09 -#define DDRSS3_CTL_140_DATA 0x07000401 -#define DDRSS3_CTL_141_DATA 0x00000000 -#define DDRSS3_CTL_142_DATA 0x00000000 -#define DDRSS3_CTL_143_DATA 0x00000000 -#define DDRSS3_CTL_144_DATA 0x00000000 -#define DDRSS3_CTL_145_DATA 0x00000000 -#define DDRSS3_CTL_146_DATA 0x00000000 -#define DDRSS3_CTL_147_DATA 0x00000000 -#define DDRSS3_CTL_148_DATA 0x08080000 -#define DDRSS3_CTL_149_DATA 0x01000000 -#define DDRSS3_CTL_150_DATA 0x800000C0 -#define DDRSS3_CTL_151_DATA 0x800000C0 -#define DDRSS3_CTL_152_DATA 0x800000C0 -#define DDRSS3_CTL_153_DATA 0x00000000 -#define DDRSS3_CTL_154_DATA 0x00001500 -#define DDRSS3_CTL_155_DATA 0x00000000 -#define DDRSS3_CTL_156_DATA 0x00000001 -#define DDRSS3_CTL_157_DATA 0x00000002 -#define DDRSS3_CTL_158_DATA 0x0000100E -#define DDRSS3_CTL_159_DATA 0x00000000 -#define DDRSS3_CTL_160_DATA 0x00000000 -#define DDRSS3_CTL_161_DATA 0x00000000 -#define DDRSS3_CTL_162_DATA 0x00000000 -#define DDRSS3_CTL_163_DATA 0x00000000 -#define DDRSS3_CTL_164_DATA 0x000B0000 -#define DDRSS3_CTL_165_DATA 0x000E0006 -#define DDRSS3_CTL_166_DATA 0x000E0404 -#define DDRSS3_CTL_167_DATA 0x00D601AB -#define DDRSS3_CTL_168_DATA 0x10100216 -#define DDRSS3_CTL_169_DATA 0x01AB0216 -#define DDRSS3_CTL_170_DATA 0x021600D6 -#define DDRSS3_CTL_171_DATA 0x02161010 -#define DDRSS3_CTL_172_DATA 0x00000000 -#define DDRSS3_CTL_173_DATA 0x00000000 -#define DDRSS3_CTL_174_DATA 0x00000000 -#define DDRSS3_CTL_175_DATA 0x3FF40084 -#define DDRSS3_CTL_176_DATA 0x33003FF4 -#define DDRSS3_CTL_177_DATA 0x00003333 -#define DDRSS3_CTL_178_DATA 0x35000000 -#define DDRSS3_CTL_179_DATA 0x27270035 -#define DDRSS3_CTL_180_DATA 0x0F0F0000 -#define DDRSS3_CTL_181_DATA 0x16000000 -#define DDRSS3_CTL_182_DATA 0x00841616 -#define DDRSS3_CTL_183_DATA 0x3FF43FF4 -#define DDRSS3_CTL_184_DATA 0x33333300 -#define DDRSS3_CTL_185_DATA 0x00000000 -#define DDRSS3_CTL_186_DATA 0x00353500 -#define DDRSS3_CTL_187_DATA 0x00002727 -#define DDRSS3_CTL_188_DATA 0x00000F0F -#define DDRSS3_CTL_189_DATA 0x16161600 -#define DDRSS3_CTL_190_DATA 0x00000020 -#define DDRSS3_CTL_191_DATA 0x00000000 -#define DDRSS3_CTL_192_DATA 0x00000001 -#define DDRSS3_CTL_193_DATA 0x00000000 -#define DDRSS3_CTL_194_DATA 0x01000000 -#define DDRSS3_CTL_195_DATA 0x00000001 -#define DDRSS3_CTL_196_DATA 0x00000000 -#define DDRSS3_CTL_197_DATA 0x00000000 -#define DDRSS3_CTL_198_DATA 0x00000000 -#define DDRSS3_CTL_199_DATA 0x00000000 -#define DDRSS3_CTL_200_DATA 0x00000000 -#define DDRSS3_CTL_201_DATA 0x00000000 -#define DDRSS3_CTL_202_DATA 0x00000000 -#define DDRSS3_CTL_203_DATA 0x00000000 -#define DDRSS3_CTL_204_DATA 0x00000000 -#define DDRSS3_CTL_205_DATA 0x00000000 -#define DDRSS3_CTL_206_DATA 0x02000000 -#define DDRSS3_CTL_207_DATA 0x01080101 -#define DDRSS3_CTL_208_DATA 0x00000000 -#define DDRSS3_CTL_209_DATA 0x00000000 -#define DDRSS3_CTL_210_DATA 0x00000000 -#define DDRSS3_CTL_211_DATA 0x00000000 -#define DDRSS3_CTL_212_DATA 0x00000000 -#define DDRSS3_CTL_213_DATA 0x00000000 -#define DDRSS3_CTL_214_DATA 0x00000000 -#define DDRSS3_CTL_215_DATA 0x00000000 -#define DDRSS3_CTL_216_DATA 0x00000000 -#define DDRSS3_CTL_217_DATA 0x00000000 -#define DDRSS3_CTL_218_DATA 0x00000000 -#define DDRSS3_CTL_219_DATA 0x00000000 -#define DDRSS3_CTL_220_DATA 0x00000000 -#define DDRSS3_CTL_221_DATA 0x00000000 -#define DDRSS3_CTL_222_DATA 0x00001000 -#define DDRSS3_CTL_223_DATA 0x006403E8 -#define DDRSS3_CTL_224_DATA 0x00000000 -#define DDRSS3_CTL_225_DATA 0x00000000 -#define DDRSS3_CTL_226_DATA 0x00000000 -#define DDRSS3_CTL_227_DATA 0x15110000 -#define DDRSS3_CTL_228_DATA 0x00040C18 -#define DDRSS3_CTL_229_DATA 0xF000C000 -#define DDRSS3_CTL_230_DATA 0x0000F000 -#define DDRSS3_CTL_231_DATA 0x00000000 -#define DDRSS3_CTL_232_DATA 0x00000000 -#define DDRSS3_CTL_233_DATA 0xC0000000 -#define DDRSS3_CTL_234_DATA 0xF000F000 -#define DDRSS3_CTL_235_DATA 0x00000000 -#define DDRSS3_CTL_236_DATA 0x00000000 -#define DDRSS3_CTL_237_DATA 0x00000000 -#define DDRSS3_CTL_238_DATA 0xF000C000 -#define DDRSS3_CTL_239_DATA 0x0000F000 -#define DDRSS3_CTL_240_DATA 0x00000000 -#define DDRSS3_CTL_241_DATA 0x00000000 -#define DDRSS3_CTL_242_DATA 0x00030000 -#define DDRSS3_CTL_243_DATA 0x00000000 -#define DDRSS3_CTL_244_DATA 0x00000000 -#define DDRSS3_CTL_245_DATA 0x00000000 -#define DDRSS3_CTL_246_DATA 0x00000000 -#define DDRSS3_CTL_247_DATA 0x00000000 -#define DDRSS3_CTL_248_DATA 0x00000000 -#define DDRSS3_CTL_249_DATA 0x00000000 -#define DDRSS3_CTL_250_DATA 0x00000000 -#define DDRSS3_CTL_251_DATA 0x00000000 -#define DDRSS3_CTL_252_DATA 0x00000000 -#define DDRSS3_CTL_253_DATA 0x00000000 -#define DDRSS3_CTL_254_DATA 0x00000000 -#define DDRSS3_CTL_255_DATA 0x00000000 -#define DDRSS3_CTL_256_DATA 0x00000000 -#define DDRSS3_CTL_257_DATA 0x01000200 -#define DDRSS3_CTL_258_DATA 0x00370040 -#define DDRSS3_CTL_259_DATA 0x00020008 -#define DDRSS3_CTL_260_DATA 0x00400100 -#define DDRSS3_CTL_261_DATA 0x00400855 -#define DDRSS3_CTL_262_DATA 0x01000200 -#define DDRSS3_CTL_263_DATA 0x08550040 -#define DDRSS3_CTL_264_DATA 0x00000040 -#define DDRSS3_CTL_265_DATA 0x006B0003 -#define DDRSS3_CTL_266_DATA 0x0100006B -#define DDRSS3_CTL_267_DATA 0x03030303 -#define DDRSS3_CTL_268_DATA 0x00000000 -#define DDRSS3_CTL_269_DATA 0x00000202 -#define DDRSS3_CTL_270_DATA 0x00001FFF -#define DDRSS3_CTL_271_DATA 0x3FFF2000 -#define DDRSS3_CTL_272_DATA 0x03FF0000 -#define DDRSS3_CTL_273_DATA 0x000103FF -#define DDRSS3_CTL_274_DATA 0x0FFF0B00 -#define DDRSS3_CTL_275_DATA 0x01010001 -#define DDRSS3_CTL_276_DATA 0x01010101 -#define DDRSS3_CTL_277_DATA 0x01180101 -#define DDRSS3_CTL_278_DATA 0x00030000 -#define DDRSS3_CTL_279_DATA 0x00000000 -#define DDRSS3_CTL_280_DATA 0x00000000 -#define DDRSS3_CTL_281_DATA 0x00000000 -#define DDRSS3_CTL_282_DATA 0x00000000 -#define DDRSS3_CTL_283_DATA 0x00000000 -#define DDRSS3_CTL_284_DATA 0x00000000 -#define DDRSS3_CTL_285_DATA 0x00000000 -#define DDRSS3_CTL_286_DATA 0x00040101 -#define DDRSS3_CTL_287_DATA 0x04010100 -#define DDRSS3_CTL_288_DATA 0x00000000 -#define DDRSS3_CTL_289_DATA 0x00000000 -#define DDRSS3_CTL_290_DATA 0x03030300 -#define DDRSS3_CTL_291_DATA 0x00000001 -#define DDRSS3_CTL_292_DATA 0x00000000 -#define DDRSS3_CTL_293_DATA 0x00000000 -#define DDRSS3_CTL_294_DATA 0x00000000 -#define DDRSS3_CTL_295_DATA 0x00000000 -#define DDRSS3_CTL_296_DATA 0x00000000 -#define DDRSS3_CTL_297_DATA 0x00000000 -#define DDRSS3_CTL_298_DATA 0x00000000 -#define DDRSS3_CTL_299_DATA 0x00000000 -#define DDRSS3_CTL_300_DATA 0x00000000 -#define DDRSS3_CTL_301_DATA 0x00000000 -#define DDRSS3_CTL_302_DATA 0x00000000 -#define DDRSS3_CTL_303_DATA 0x00000000 -#define DDRSS3_CTL_304_DATA 0x00000000 -#define DDRSS3_CTL_305_DATA 0x00000000 -#define DDRSS3_CTL_306_DATA 0x00000000 -#define DDRSS3_CTL_307_DATA 0x00000000 -#define DDRSS3_CTL_308_DATA 0x00000000 -#define DDRSS3_CTL_309_DATA 0x00000000 -#define DDRSS3_CTL_310_DATA 0x00000000 -#define DDRSS3_CTL_311_DATA 0x00000000 -#define DDRSS3_CTL_312_DATA 0x00000000 -#define DDRSS3_CTL_313_DATA 0x01000000 -#define DDRSS3_CTL_314_DATA 0x00020201 -#define DDRSS3_CTL_315_DATA 0x01000101 -#define DDRSS3_CTL_316_DATA 0x01010001 -#define DDRSS3_CTL_317_DATA 0x00010101 -#define DDRSS3_CTL_318_DATA 0x050A0A03 -#define DDRSS3_CTL_319_DATA 0x10081F1F -#define DDRSS3_CTL_320_DATA 0x00090310 -#define DDRSS3_CTL_321_DATA 0x0B0C030F -#define DDRSS3_CTL_322_DATA 0x0B0C0306 -#define DDRSS3_CTL_323_DATA 0x0C090006 -#define DDRSS3_CTL_324_DATA 0x0100000C -#define DDRSS3_CTL_325_DATA 0x08040801 -#define DDRSS3_CTL_326_DATA 0x00000004 -#define DDRSS3_CTL_327_DATA 0x00000000 -#define DDRSS3_CTL_328_DATA 0x00010000 -#define DDRSS3_CTL_329_DATA 0x00280D00 -#define DDRSS3_CTL_330_DATA 0x00000001 -#define DDRSS3_CTL_331_DATA 0x00030001 -#define DDRSS3_CTL_332_DATA 0x00000000 -#define DDRSS3_CTL_333_DATA 0x00000000 -#define DDRSS3_CTL_334_DATA 0x00000000 -#define DDRSS3_CTL_335_DATA 0x00000000 -#define DDRSS3_CTL_336_DATA 0x00000000 -#define DDRSS3_CTL_337_DATA 0x00000000 -#define DDRSS3_CTL_338_DATA 0x00000000 -#define DDRSS3_CTL_339_DATA 0x00000000 -#define DDRSS3_CTL_340_DATA 0x01000000 -#define DDRSS3_CTL_341_DATA 0x00000001 -#define DDRSS3_CTL_342_DATA 0x00010100 -#define DDRSS3_CTL_343_DATA 0x03030000 -#define DDRSS3_CTL_344_DATA 0x00000000 -#define DDRSS3_CTL_345_DATA 0x00000000 -#define DDRSS3_CTL_346_DATA 0x00000000 -#define DDRSS3_CTL_347_DATA 0x00000000 -#define DDRSS3_CTL_348_DATA 0x00000000 -#define DDRSS3_CTL_349_DATA 0x00000000 -#define DDRSS3_CTL_350_DATA 0x00000000 -#define DDRSS3_CTL_351_DATA 0x00000000 -#define DDRSS3_CTL_352_DATA 0x00000000 -#define DDRSS3_CTL_353_DATA 0x00000000 -#define DDRSS3_CTL_354_DATA 0x00000000 -#define DDRSS3_CTL_355_DATA 0x00000000 -#define DDRSS3_CTL_356_DATA 0x00000000 -#define DDRSS3_CTL_357_DATA 0x00000000 -#define DDRSS3_CTL_358_DATA 0x00000000 -#define DDRSS3_CTL_359_DATA 0x00000000 -#define DDRSS3_CTL_360_DATA 0x000556AA -#define DDRSS3_CTL_361_DATA 0x000AAAAA -#define DDRSS3_CTL_362_DATA 0x000AA955 -#define DDRSS3_CTL_363_DATA 0x00055555 -#define DDRSS3_CTL_364_DATA 0x000B3133 -#define DDRSS3_CTL_365_DATA 0x0004CD33 -#define DDRSS3_CTL_366_DATA 0x0004CECC -#define DDRSS3_CTL_367_DATA 0x000B32CC -#define DDRSS3_CTL_368_DATA 0x00010300 -#define DDRSS3_CTL_369_DATA 0x03000100 -#define DDRSS3_CTL_370_DATA 0x00000000 -#define DDRSS3_CTL_371_DATA 0x00000000 -#define DDRSS3_CTL_372_DATA 0x00000000 -#define DDRSS3_CTL_373_DATA 0x00000000 -#define DDRSS3_CTL_374_DATA 0x00000000 -#define DDRSS3_CTL_375_DATA 0x00000000 -#define DDRSS3_CTL_376_DATA 0x00000000 -#define DDRSS3_CTL_377_DATA 0x00010000 -#define DDRSS3_CTL_378_DATA 0x00000404 -#define DDRSS3_CTL_379_DATA 0x00000000 -#define DDRSS3_CTL_380_DATA 0x00000000 -#define DDRSS3_CTL_381_DATA 0x00000000 -#define DDRSS3_CTL_382_DATA 0x00000000 -#define DDRSS3_CTL_383_DATA 0x00000000 -#define DDRSS3_CTL_384_DATA 0x00000000 -#define DDRSS3_CTL_385_DATA 0x00000000 -#define DDRSS3_CTL_386_DATA 0x00000000 -#define DDRSS3_CTL_387_DATA 0x3A3A1B00 -#define DDRSS3_CTL_388_DATA 0x000A0000 -#define DDRSS3_CTL_389_DATA 0x0000019C -#define DDRSS3_CTL_390_DATA 0x00000200 -#define DDRSS3_CTL_391_DATA 0x00000200 -#define DDRSS3_CTL_392_DATA 0x00000200 -#define DDRSS3_CTL_393_DATA 0x00000200 -#define DDRSS3_CTL_394_DATA 0x000004D4 -#define DDRSS3_CTL_395_DATA 0x00001018 -#define DDRSS3_CTL_396_DATA 0x00000204 -#define DDRSS3_CTL_397_DATA 0x000040E6 -#define DDRSS3_CTL_398_DATA 0x00000200 -#define DDRSS3_CTL_399_DATA 0x00000200 -#define DDRSS3_CTL_400_DATA 0x00000200 -#define DDRSS3_CTL_401_DATA 0x00000200 -#define DDRSS3_CTL_402_DATA 0x0000C2B2 -#define DDRSS3_CTL_403_DATA 0x000288FC -#define DDRSS3_CTL_404_DATA 0x00000E15 -#define DDRSS3_CTL_405_DATA 0x000040E6 -#define DDRSS3_CTL_406_DATA 0x00000200 -#define DDRSS3_CTL_407_DATA 0x00000200 -#define DDRSS3_CTL_408_DATA 0x00000200 -#define DDRSS3_CTL_409_DATA 0x00000200 -#define DDRSS3_CTL_410_DATA 0x0000C2B2 -#define DDRSS3_CTL_411_DATA 0x000288FC -#define DDRSS3_CTL_412_DATA 0x02020E15 -#define DDRSS3_CTL_413_DATA 0x03030202 -#define DDRSS3_CTL_414_DATA 0x00000022 -#define DDRSS3_CTL_415_DATA 0x00000000 -#define DDRSS3_CTL_416_DATA 0x00000000 -#define DDRSS3_CTL_417_DATA 0x00001403 -#define DDRSS3_CTL_418_DATA 0x000007D0 -#define DDRSS3_CTL_419_DATA 0x00000000 -#define DDRSS3_CTL_420_DATA 0x00000000 -#define DDRSS3_CTL_421_DATA 0x00030000 -#define DDRSS3_CTL_422_DATA 0x0007001F -#define DDRSS3_CTL_423_DATA 0x001B0033 -#define DDRSS3_CTL_424_DATA 0x001B0033 -#define DDRSS3_CTL_425_DATA 0x00000000 -#define DDRSS3_CTL_426_DATA 0x00000000 -#define DDRSS3_CTL_427_DATA 0x02000000 -#define DDRSS3_CTL_428_DATA 0x01000404 -#define DDRSS3_CTL_429_DATA 0x0B1E0B1E -#define DDRSS3_CTL_430_DATA 0x00000105 -#define DDRSS3_CTL_431_DATA 0x00010101 -#define DDRSS3_CTL_432_DATA 0x00010101 -#define DDRSS3_CTL_433_DATA 0x00010001 -#define DDRSS3_CTL_434_DATA 0x00000101 -#define DDRSS3_CTL_435_DATA 0x02000201 -#define DDRSS3_CTL_436_DATA 0x02010000 -#define DDRSS3_CTL_437_DATA 0x00000200 -#define DDRSS3_CTL_438_DATA 0x28060000 -#define DDRSS3_CTL_439_DATA 0x00000128 -#define DDRSS3_CTL_440_DATA 0xFFFFFFFF -#define DDRSS3_CTL_441_DATA 0xFFFFFFFF -#define DDRSS3_CTL_442_DATA 0x00000000 -#define DDRSS3_CTL_443_DATA 0x00000000 -#define DDRSS3_CTL_444_DATA 0x00000000 -#define DDRSS3_CTL_445_DATA 0x00000000 -#define DDRSS3_CTL_446_DATA 0x00000000 -#define DDRSS3_CTL_447_DATA 0x00000000 -#define DDRSS3_CTL_448_DATA 0x00000000 -#define DDRSS3_CTL_449_DATA 0x00000000 -#define DDRSS3_CTL_450_DATA 0x00000000 -#define DDRSS3_CTL_451_DATA 0x00000000 -#define DDRSS3_CTL_452_DATA 0x00000000 -#define DDRSS3_CTL_453_DATA 0x00000000 -#define DDRSS3_CTL_454_DATA 0x00000000 -#define DDRSS3_CTL_455_DATA 0x00000000 -#define DDRSS3_CTL_456_DATA 0x00000000 -#define DDRSS3_CTL_457_DATA 0x00000000 -#define DDRSS3_CTL_458_DATA 0x00000000 - -#define DDRSS3_PI_00_DATA 0x00000B00 -#define DDRSS3_PI_01_DATA 0x00000000 -#define DDRSS3_PI_02_DATA 0x00000000 -#define DDRSS3_PI_03_DATA 0x00000000 -#define DDRSS3_PI_04_DATA 0x00000000 -#define DDRSS3_PI_05_DATA 0x00000101 -#define DDRSS3_PI_06_DATA 0x00640000 -#define DDRSS3_PI_07_DATA 0x00000001 -#define DDRSS3_PI_08_DATA 0x00000000 -#define DDRSS3_PI_09_DATA 0x00000000 -#define DDRSS3_PI_10_DATA 0x00000000 -#define DDRSS3_PI_11_DATA 0x00000000 -#define DDRSS3_PI_12_DATA 0x00000007 -#define DDRSS3_PI_13_DATA 0x00010002 -#define DDRSS3_PI_14_DATA 0x0800000F -#define DDRSS3_PI_15_DATA 0x00000103 -#define DDRSS3_PI_16_DATA 0x00000005 -#define DDRSS3_PI_17_DATA 0x00000000 -#define DDRSS3_PI_18_DATA 0x00000000 -#define DDRSS3_PI_19_DATA 0x00000000 -#define DDRSS3_PI_20_DATA 0x00000000 -#define DDRSS3_PI_21_DATA 0x00000000 -#define DDRSS3_PI_22_DATA 0x00000000 -#define DDRSS3_PI_23_DATA 0x00000000 -#define DDRSS3_PI_24_DATA 0x00000000 -#define DDRSS3_PI_25_DATA 0x00000000 -#define DDRSS3_PI_26_DATA 0x00010100 -#define DDRSS3_PI_27_DATA 0x00280A00 -#define DDRSS3_PI_28_DATA 0x00000000 -#define DDRSS3_PI_29_DATA 0x0F000000 -#define DDRSS3_PI_30_DATA 0x00003200 -#define DDRSS3_PI_31_DATA 0x00000000 -#define DDRSS3_PI_32_DATA 0x00000000 -#define DDRSS3_PI_33_DATA 0x01010102 -#define DDRSS3_PI_34_DATA 0x00000000 -#define DDRSS3_PI_35_DATA 0x000000AA -#define DDRSS3_PI_36_DATA 0x00000055 -#define DDRSS3_PI_37_DATA 0x000000B5 -#define DDRSS3_PI_38_DATA 0x0000004A -#define DDRSS3_PI_39_DATA 0x00000056 -#define DDRSS3_PI_40_DATA 0x000000A9 -#define DDRSS3_PI_41_DATA 0x000000A9 -#define DDRSS3_PI_42_DATA 0x000000B5 -#define DDRSS3_PI_43_DATA 0x00000000 -#define DDRSS3_PI_44_DATA 0x00000000 -#define DDRSS3_PI_45_DATA 0x000F0F00 -#define DDRSS3_PI_46_DATA 0x0000001B -#define DDRSS3_PI_47_DATA 0x000007D0 -#define DDRSS3_PI_48_DATA 0x00000300 -#define DDRSS3_PI_49_DATA 0x00000000 -#define DDRSS3_PI_50_DATA 0x00000000 -#define DDRSS3_PI_51_DATA 0x01000000 -#define DDRSS3_PI_52_DATA 0x00010101 -#define DDRSS3_PI_53_DATA 0x00000000 -#define DDRSS3_PI_54_DATA 0x00030000 -#define DDRSS3_PI_55_DATA 0x0F000000 -#define DDRSS3_PI_56_DATA 0x00000017 -#define DDRSS3_PI_57_DATA 0x00000000 -#define DDRSS3_PI_58_DATA 0x00000000 -#define DDRSS3_PI_59_DATA 0x00000000 -#define DDRSS3_PI_60_DATA 0x0A0A140A -#define DDRSS3_PI_61_DATA 0x10020101 -#define DDRSS3_PI_62_DATA 0x00020805 -#define DDRSS3_PI_63_DATA 0x01000404 -#define DDRSS3_PI_64_DATA 0x00000000 -#define DDRSS3_PI_65_DATA 0x00000000 -#define DDRSS3_PI_66_DATA 0x00000100 -#define DDRSS3_PI_67_DATA 0x0001010F -#define DDRSS3_PI_68_DATA 0x00340000 -#define DDRSS3_PI_69_DATA 0x00000000 -#define DDRSS3_PI_70_DATA 0x00000000 -#define DDRSS3_PI_71_DATA 0x0000FFFF -#define DDRSS3_PI_72_DATA 0x00000000 -#define DDRSS3_PI_73_DATA 0x00080000 -#define DDRSS3_PI_74_DATA 0x02000200 -#define DDRSS3_PI_75_DATA 0x01000100 -#define DDRSS3_PI_76_DATA 0x01000000 -#define DDRSS3_PI_77_DATA 0x02000200 -#define DDRSS3_PI_78_DATA 0x00000200 -#define DDRSS3_PI_79_DATA 0x00000000 -#define DDRSS3_PI_80_DATA 0x00000000 -#define DDRSS3_PI_81_DATA 0x00000000 -#define DDRSS3_PI_82_DATA 0x00000000 -#define DDRSS3_PI_83_DATA 0x00000000 -#define DDRSS3_PI_84_DATA 0x00000000 -#define DDRSS3_PI_85_DATA 0x00000000 -#define DDRSS3_PI_86_DATA 0x00000000 -#define DDRSS3_PI_87_DATA 0x00000000 -#define DDRSS3_PI_88_DATA 0x00000000 -#define DDRSS3_PI_89_DATA 0x00000000 -#define DDRSS3_PI_90_DATA 0x00000000 -#define DDRSS3_PI_91_DATA 0x00000400 -#define DDRSS3_PI_92_DATA 0x02010000 -#define DDRSS3_PI_93_DATA 0x00080003 -#define DDRSS3_PI_94_DATA 0x00080000 -#define DDRSS3_PI_95_DATA 0x00000001 -#define DDRSS3_PI_96_DATA 0x00000000 -#define DDRSS3_PI_97_DATA 0x0000AA00 -#define DDRSS3_PI_98_DATA 0x00000000 -#define DDRSS3_PI_99_DATA 0x00000000 -#define DDRSS3_PI_100_DATA 0x00010000 -#define DDRSS3_PI_101_DATA 0x00000000 -#define DDRSS3_PI_102_DATA 0x00000000 -#define DDRSS3_PI_103_DATA 0x00000000 -#define DDRSS3_PI_104_DATA 0x00000000 -#define DDRSS3_PI_105_DATA 0x00000000 -#define DDRSS3_PI_106_DATA 0x00000000 -#define DDRSS3_PI_107_DATA 0x00000000 -#define DDRSS3_PI_108_DATA 0x00000000 -#define DDRSS3_PI_109_DATA 0x00000000 -#define DDRSS3_PI_110_DATA 0x00000000 -#define DDRSS3_PI_111_DATA 0x00000000 -#define DDRSS3_PI_112_DATA 0x00000000 -#define DDRSS3_PI_113_DATA 0x00000000 -#define DDRSS3_PI_114_DATA 0x00000000 -#define DDRSS3_PI_115_DATA 0x00000000 -#define DDRSS3_PI_116_DATA 0x00000000 -#define DDRSS3_PI_117_DATA 0x00000000 -#define DDRSS3_PI_118_DATA 0x00000000 -#define DDRSS3_PI_119_DATA 0x00000000 -#define DDRSS3_PI_120_DATA 0x00000000 -#define DDRSS3_PI_121_DATA 0x00000000 -#define DDRSS3_PI_122_DATA 0x00000000 -#define DDRSS3_PI_123_DATA 0x00000000 -#define DDRSS3_PI_124_DATA 0x00000000 -#define DDRSS3_PI_125_DATA 0x00000008 -#define DDRSS3_PI_126_DATA 0x00000000 -#define DDRSS3_PI_127_DATA 0x00000000 -#define DDRSS3_PI_128_DATA 0x00000000 -#define DDRSS3_PI_129_DATA 0x00000000 -#define DDRSS3_PI_130_DATA 0x00000000 -#define DDRSS3_PI_131_DATA 0x00000000 -#define DDRSS3_PI_132_DATA 0x00000000 -#define DDRSS3_PI_133_DATA 0x00000000 -#define DDRSS3_PI_134_DATA 0x00000002 -#define DDRSS3_PI_135_DATA 0x00000000 -#define DDRSS3_PI_136_DATA 0x00000000 -#define DDRSS3_PI_137_DATA 0x0000000A -#define DDRSS3_PI_138_DATA 0x00000019 -#define DDRSS3_PI_139_DATA 0x00000100 -#define DDRSS3_PI_140_DATA 0x00000000 -#define DDRSS3_PI_141_DATA 0x00000000 -#define DDRSS3_PI_142_DATA 0x00000000 -#define DDRSS3_PI_143_DATA 0x00000000 -#define DDRSS3_PI_144_DATA 0x01000000 -#define DDRSS3_PI_145_DATA 0x00010003 -#define DDRSS3_PI_146_DATA 0x02000101 -#define DDRSS3_PI_147_DATA 0x01030001 -#define DDRSS3_PI_148_DATA 0x00010400 -#define DDRSS3_PI_149_DATA 0x06000105 -#define DDRSS3_PI_150_DATA 0x01070001 -#define DDRSS3_PI_151_DATA 0x00000000 -#define DDRSS3_PI_152_DATA 0x00000000 -#define DDRSS3_PI_153_DATA 0x00000000 -#define DDRSS3_PI_154_DATA 0x00010001 -#define DDRSS3_PI_155_DATA 0x00000000 -#define DDRSS3_PI_156_DATA 0x00000000 -#define DDRSS3_PI_157_DATA 0x00000000 -#define DDRSS3_PI_158_DATA 0x00000000 -#define DDRSS3_PI_159_DATA 0x00000401 -#define DDRSS3_PI_160_DATA 0x00000000 -#define DDRSS3_PI_161_DATA 0x00010000 -#define DDRSS3_PI_162_DATA 0x00000000 -#define DDRSS3_PI_163_DATA 0x2B2B0200 -#define DDRSS3_PI_164_DATA 0x00000034 -#define DDRSS3_PI_165_DATA 0x00000064 -#define DDRSS3_PI_166_DATA 0x00020064 -#define DDRSS3_PI_167_DATA 0x02000200 -#define DDRSS3_PI_168_DATA 0x48120C04 -#define DDRSS3_PI_169_DATA 0x00154812 -#define DDRSS3_PI_170_DATA 0x000000CE -#define DDRSS3_PI_171_DATA 0x0000032B -#define DDRSS3_PI_172_DATA 0x00002073 -#define DDRSS3_PI_173_DATA 0x0000032B -#define DDRSS3_PI_174_DATA 0x04002073 -#define DDRSS3_PI_175_DATA 0x01010404 -#define DDRSS3_PI_176_DATA 0x00001501 -#define DDRSS3_PI_177_DATA 0x00150015 -#define DDRSS3_PI_178_DATA 0x01000100 -#define DDRSS3_PI_179_DATA 0x00000100 -#define DDRSS3_PI_180_DATA 0x00000000 -#define DDRSS3_PI_181_DATA 0x01010101 -#define DDRSS3_PI_182_DATA 0x00000101 -#define DDRSS3_PI_183_DATA 0x00000000 -#define DDRSS3_PI_184_DATA 0x00000000 -#define DDRSS3_PI_185_DATA 0x15040000 -#define DDRSS3_PI_186_DATA 0x0E0E0215 -#define DDRSS3_PI_187_DATA 0x00040402 -#define DDRSS3_PI_188_DATA 0x000D0035 -#define DDRSS3_PI_189_DATA 0x00218049 -#define DDRSS3_PI_190_DATA 0x00218049 -#define DDRSS3_PI_191_DATA 0x01010101 -#define DDRSS3_PI_192_DATA 0x0004000E -#define DDRSS3_PI_193_DATA 0x00040216 -#define DDRSS3_PI_194_DATA 0x01000216 -#define DDRSS3_PI_195_DATA 0x000F000F -#define DDRSS3_PI_196_DATA 0x02170100 -#define DDRSS3_PI_197_DATA 0x01000217 -#define DDRSS3_PI_198_DATA 0x02170217 -#define DDRSS3_PI_199_DATA 0x32103200 -#define DDRSS3_PI_200_DATA 0x01013210 -#define DDRSS3_PI_201_DATA 0x0A070601 -#define DDRSS3_PI_202_DATA 0x1F130A0D -#define DDRSS3_PI_203_DATA 0x1F130A14 -#define DDRSS3_PI_204_DATA 0x0000C014 -#define DDRSS3_PI_205_DATA 0x00C01000 -#define DDRSS3_PI_206_DATA 0x00C01000 -#define DDRSS3_PI_207_DATA 0x00021000 -#define DDRSS3_PI_208_DATA 0x0024000E -#define DDRSS3_PI_209_DATA 0x00240216 -#define DDRSS3_PI_210_DATA 0x00110216 -#define DDRSS3_PI_211_DATA 0x32000056 -#define DDRSS3_PI_212_DATA 0x00000301 -#define DDRSS3_PI_213_DATA 0x005B0036 -#define DDRSS3_PI_214_DATA 0x03013212 -#define DDRSS3_PI_215_DATA 0x00003600 -#define DDRSS3_PI_216_DATA 0x3212005B -#define DDRSS3_PI_217_DATA 0x09000301 -#define DDRSS3_PI_218_DATA 0x04010504 -#define DDRSS3_PI_219_DATA 0x040006C9 -#define DDRSS3_PI_220_DATA 0x0A032001 -#define DDRSS3_PI_221_DATA 0x2C31110A -#define DDRSS3_PI_222_DATA 0x00002918 -#define DDRSS3_PI_223_DATA 0x6001071C -#define DDRSS3_PI_224_DATA 0x1E202008 -#define DDRSS3_PI_225_DATA 0x2C311116 -#define DDRSS3_PI_226_DATA 0x00002918 -#define DDRSS3_PI_227_DATA 0x6001071C -#define DDRSS3_PI_228_DATA 0x1E202008 -#define DDRSS3_PI_229_DATA 0x00019C16 -#define DDRSS3_PI_230_DATA 0x00001018 -#define DDRSS3_PI_231_DATA 0x000040E6 -#define DDRSS3_PI_232_DATA 0x000288FC -#define DDRSS3_PI_233_DATA 0x000040E6 -#define DDRSS3_PI_234_DATA 0x000288FC -#define DDRSS3_PI_235_DATA 0x033B0016 -#define DDRSS3_PI_236_DATA 0x0303033B -#define DDRSS3_PI_237_DATA 0x002AF803 -#define DDRSS3_PI_238_DATA 0x0001ADAF -#define DDRSS3_PI_239_DATA 0x00000005 -#define DDRSS3_PI_240_DATA 0x0000006E -#define DDRSS3_PI_241_DATA 0x00000016 -#define DDRSS3_PI_242_DATA 0x000681C8 -#define DDRSS3_PI_243_DATA 0x0001ADAF -#define DDRSS3_PI_244_DATA 0x00000005 -#define DDRSS3_PI_245_DATA 0x000010A9 -#define DDRSS3_PI_246_DATA 0x0000033B -#define DDRSS3_PI_247_DATA 0x000681C8 -#define DDRSS3_PI_248_DATA 0x0001ADAF -#define DDRSS3_PI_249_DATA 0x00000005 -#define DDRSS3_PI_250_DATA 0x000010A9 -#define DDRSS3_PI_251_DATA 0x0100033B -#define DDRSS3_PI_252_DATA 0x00370040 -#define DDRSS3_PI_253_DATA 0x00010008 -#define DDRSS3_PI_254_DATA 0x08550040 -#define DDRSS3_PI_255_DATA 0x00010040 -#define DDRSS3_PI_256_DATA 0x08550040 -#define DDRSS3_PI_257_DATA 0x00000340 -#define DDRSS3_PI_258_DATA 0x006B006B -#define DDRSS3_PI_259_DATA 0x08040404 -#define DDRSS3_PI_260_DATA 0x00000055 -#define DDRSS3_PI_261_DATA 0x55083C5A -#define DDRSS3_PI_262_DATA 0x5A000000 -#define DDRSS3_PI_263_DATA 0x0055083C -#define DDRSS3_PI_264_DATA 0x3C5A0000 -#define DDRSS3_PI_265_DATA 0x00005508 -#define DDRSS3_PI_266_DATA 0x0C3C5A00 -#define DDRSS3_PI_267_DATA 0x080F0E0D -#define DDRSS3_PI_268_DATA 0x000B0A09 -#define DDRSS3_PI_269_DATA 0x00030201 -#define DDRSS3_PI_270_DATA 0x01000000 -#define DDRSS3_PI_271_DATA 0x04020201 -#define DDRSS3_PI_272_DATA 0x00080804 -#define DDRSS3_PI_273_DATA 0x00000000 -#define DDRSS3_PI_274_DATA 0x00000000 -#define DDRSS3_PI_275_DATA 0x00330084 -#define DDRSS3_PI_276_DATA 0x00160000 -#define DDRSS3_PI_277_DATA 0x35333FF4 -#define DDRSS3_PI_278_DATA 0x00160F27 -#define DDRSS3_PI_279_DATA 0x35333FF4 -#define DDRSS3_PI_280_DATA 0x00160F27 -#define DDRSS3_PI_281_DATA 0x00330084 -#define DDRSS3_PI_282_DATA 0x00160000 -#define DDRSS3_PI_283_DATA 0x35333FF4 -#define DDRSS3_PI_284_DATA 0x00160F27 -#define DDRSS3_PI_285_DATA 0x35333FF4 -#define DDRSS3_PI_286_DATA 0x00160F27 -#define DDRSS3_PI_287_DATA 0x00330084 -#define DDRSS3_PI_288_DATA 0x00160000 -#define DDRSS3_PI_289_DATA 0x35333FF4 -#define DDRSS3_PI_290_DATA 0x00160F27 -#define DDRSS3_PI_291_DATA 0x35333FF4 -#define DDRSS3_PI_292_DATA 0x00160F27 -#define DDRSS3_PI_293_DATA 0x00330084 -#define DDRSS3_PI_294_DATA 0x00160000 -#define DDRSS3_PI_295_DATA 0x35333FF4 -#define DDRSS3_PI_296_DATA 0x00160F27 -#define DDRSS3_PI_297_DATA 0x35333FF4 -#define DDRSS3_PI_298_DATA 0x00160F27 -#define DDRSS3_PI_299_DATA 0x00000000 -#define DDRSS3_PHY_00_DATA 0x000004F0 -#define DDRSS3_PHY_01_DATA 0x00000000 -#define DDRSS3_PHY_02_DATA 0x00030200 -#define DDRSS3_PHY_03_DATA 0x00000000 -#define DDRSS3_PHY_04_DATA 0x00000000 -#define DDRSS3_PHY_05_DATA 0x01030000 -#define DDRSS3_PHY_06_DATA 0x00010000 -#define DDRSS3_PHY_07_DATA 0x01030004 -#define DDRSS3_PHY_08_DATA 0x01000000 -#define DDRSS3_PHY_09_DATA 0x00000000 -#define DDRSS3_PHY_10_DATA 0x00000000 -#define DDRSS3_PHY_11_DATA 0x01000001 -#define DDRSS3_PHY_12_DATA 0x00000100 -#define DDRSS3_PHY_13_DATA 0x000800C0 -#define DDRSS3_PHY_14_DATA 0x060100CC -#define DDRSS3_PHY_15_DATA 0x00030066 -#define DDRSS3_PHY_16_DATA 0x00000000 -#define DDRSS3_PHY_17_DATA 0x00000301 -#define DDRSS3_PHY_18_DATA 0x0000AAAA -#define DDRSS3_PHY_19_DATA 0x00005555 -#define DDRSS3_PHY_20_DATA 0x0000B5B5 -#define DDRSS3_PHY_21_DATA 0x00004A4A -#define DDRSS3_PHY_22_DATA 0x00005656 -#define DDRSS3_PHY_23_DATA 0x0000A9A9 -#define DDRSS3_PHY_24_DATA 0x0000A9A9 -#define DDRSS3_PHY_25_DATA 0x0000B5B5 -#define DDRSS3_PHY_26_DATA 0x00000000 -#define DDRSS3_PHY_27_DATA 0x00000000 -#define DDRSS3_PHY_28_DATA 0x2A000000 -#define DDRSS3_PHY_29_DATA 0x00000808 -#define DDRSS3_PHY_30_DATA 0x0F000000 -#define DDRSS3_PHY_31_DATA 0x00000F0F -#define DDRSS3_PHY_32_DATA 0x10400000 -#define DDRSS3_PHY_33_DATA 0x0C002006 -#define DDRSS3_PHY_34_DATA 0x00000000 -#define DDRSS3_PHY_35_DATA 0x00000000 -#define DDRSS3_PHY_36_DATA 0x55555555 -#define DDRSS3_PHY_37_DATA 0xAAAAAAAA -#define DDRSS3_PHY_38_DATA 0x55555555 -#define DDRSS3_PHY_39_DATA 0xAAAAAAAA -#define DDRSS3_PHY_40_DATA 0x00005555 -#define DDRSS3_PHY_41_DATA 0x01000100 -#define DDRSS3_PHY_42_DATA 0x00800180 -#define DDRSS3_PHY_43_DATA 0x00000001 -#define DDRSS3_PHY_44_DATA 0x00000000 -#define DDRSS3_PHY_45_DATA 0x00000000 -#define DDRSS3_PHY_46_DATA 0x00000000 -#define DDRSS3_PHY_47_DATA 0x00000000 -#define DDRSS3_PHY_48_DATA 0x00000000 -#define DDRSS3_PHY_49_DATA 0x00000000 -#define DDRSS3_PHY_50_DATA 0x00000000 -#define DDRSS3_PHY_51_DATA 0x00000000 -#define DDRSS3_PHY_52_DATA 0x00000000 -#define DDRSS3_PHY_53_DATA 0x00000000 -#define DDRSS3_PHY_54_DATA 0x00000000 -#define DDRSS3_PHY_55_DATA 0x00000000 -#define DDRSS3_PHY_56_DATA 0x00000000 -#define DDRSS3_PHY_57_DATA 0x00000000 -#define DDRSS3_PHY_58_DATA 0x00000000 -#define DDRSS3_PHY_59_DATA 0x00000000 -#define DDRSS3_PHY_60_DATA 0x00000000 -#define DDRSS3_PHY_61_DATA 0x00000000 -#define DDRSS3_PHY_62_DATA 0x00000000 -#define DDRSS3_PHY_63_DATA 0x00000000 -#define DDRSS3_PHY_64_DATA 0x00000000 -#define DDRSS3_PHY_65_DATA 0x00000000 -#define DDRSS3_PHY_66_DATA 0x00000104 -#define DDRSS3_PHY_67_DATA 0x00000120 -#define DDRSS3_PHY_68_DATA 0x00000000 -#define DDRSS3_PHY_69_DATA 0x00000000 -#define DDRSS3_PHY_70_DATA 0x00000000 -#define DDRSS3_PHY_71_DATA 0x00000000 -#define DDRSS3_PHY_72_DATA 0x00000000 -#define DDRSS3_PHY_73_DATA 0x00000000 -#define DDRSS3_PHY_74_DATA 0x00000000 -#define DDRSS3_PHY_75_DATA 0x00000001 -#define DDRSS3_PHY_76_DATA 0x07FF0000 -#define DDRSS3_PHY_77_DATA 0x0080081F -#define DDRSS3_PHY_78_DATA 0x00081020 -#define DDRSS3_PHY_79_DATA 0x04010000 -#define DDRSS3_PHY_80_DATA 0x00000000 -#define DDRSS3_PHY_81_DATA 0x00000000 -#define DDRSS3_PHY_82_DATA 0x00000000 -#define DDRSS3_PHY_83_DATA 0x00000100 -#define DDRSS3_PHY_84_DATA 0x01CC0C01 -#define DDRSS3_PHY_85_DATA 0x1003CC0C -#define DDRSS3_PHY_86_DATA 0x20000140 -#define DDRSS3_PHY_87_DATA 0x07FF0200 -#define DDRSS3_PHY_88_DATA 0x0000DD01 -#define DDRSS3_PHY_89_DATA 0x10100303 -#define DDRSS3_PHY_90_DATA 0x10101010 -#define DDRSS3_PHY_91_DATA 0x10101010 -#define DDRSS3_PHY_92_DATA 0x00021010 -#define DDRSS3_PHY_93_DATA 0x00100010 -#define DDRSS3_PHY_94_DATA 0x00100010 -#define DDRSS3_PHY_95_DATA 0x00100010 -#define DDRSS3_PHY_96_DATA 0x00100010 -#define DDRSS3_PHY_97_DATA 0x00050010 -#define DDRSS3_PHY_98_DATA 0x51517041 -#define DDRSS3_PHY_99_DATA 0x31C06001 -#define DDRSS3_PHY_100_DATA 0x07AB0340 -#define DDRSS3_PHY_101_DATA 0x00C0C001 -#define DDRSS3_PHY_102_DATA 0x0E0D0001 -#define DDRSS3_PHY_103_DATA 0x10001000 -#define DDRSS3_PHY_104_DATA 0x0C083E42 -#define DDRSS3_PHY_105_DATA 0x0F0C3701 -#define DDRSS3_PHY_106_DATA 0x01000140 -#define DDRSS3_PHY_107_DATA 0x0C000420 -#define DDRSS3_PHY_108_DATA 0x00000198 -#define DDRSS3_PHY_109_DATA 0x0A0000D0 -#define DDRSS3_PHY_110_DATA 0x00030200 -#define DDRSS3_PHY_111_DATA 0x02800000 -#define DDRSS3_PHY_112_DATA 0x80800000 -#define DDRSS3_PHY_113_DATA 0x000E2010 -#define DDRSS3_PHY_114_DATA 0x76543210 -#define DDRSS3_PHY_115_DATA 0x00000008 -#define DDRSS3_PHY_116_DATA 0x02800280 -#define DDRSS3_PHY_117_DATA 0x02800280 -#define DDRSS3_PHY_118_DATA 0x02800280 -#define DDRSS3_PHY_119_DATA 0x02800280 -#define DDRSS3_PHY_120_DATA 0x00000280 -#define DDRSS3_PHY_121_DATA 0x0000A000 -#define DDRSS3_PHY_122_DATA 0x00A000A0 -#define DDRSS3_PHY_123_DATA 0x00A000A0 -#define DDRSS3_PHY_124_DATA 0x00A000A0 -#define DDRSS3_PHY_125_DATA 0x00A000A0 -#define DDRSS3_PHY_126_DATA 0x00A000A0 -#define DDRSS3_PHY_127_DATA 0x00A000A0 -#define DDRSS3_PHY_128_DATA 0x00A000A0 -#define DDRSS3_PHY_129_DATA 0x00A000A0 -#define DDRSS3_PHY_130_DATA 0x01C200A0 -#define DDRSS3_PHY_131_DATA 0x01A00005 -#define DDRSS3_PHY_132_DATA 0x00000000 -#define DDRSS3_PHY_133_DATA 0x00000000 -#define DDRSS3_PHY_134_DATA 0x00080200 -#define DDRSS3_PHY_135_DATA 0x00000000 -#define DDRSS3_PHY_136_DATA 0x20202000 -#define DDRSS3_PHY_137_DATA 0x20202020 -#define DDRSS3_PHY_138_DATA 0xF0F02020 -#define DDRSS3_PHY_139_DATA 0x00000000 -#define DDRSS3_PHY_140_DATA 0x00000000 -#define DDRSS3_PHY_141_DATA 0x00000000 -#define DDRSS3_PHY_142_DATA 0x00000000 -#define DDRSS3_PHY_143_DATA 0x00000000 -#define DDRSS3_PHY_144_DATA 0x00000000 -#define DDRSS3_PHY_145_DATA 0x00000000 -#define DDRSS3_PHY_146_DATA 0x00000000 -#define DDRSS3_PHY_147_DATA 0x00000000 -#define DDRSS3_PHY_148_DATA 0x00000000 -#define DDRSS3_PHY_149_DATA 0x00000000 -#define DDRSS3_PHY_150_DATA 0x00000000 -#define DDRSS3_PHY_151_DATA 0x00000000 -#define DDRSS3_PHY_152_DATA 0x00000000 -#define DDRSS3_PHY_153_DATA 0x00000000 -#define DDRSS3_PHY_154_DATA 0x00000000 -#define DDRSS3_PHY_155_DATA 0x00000000 -#define DDRSS3_PHY_156_DATA 0x00000000 -#define DDRSS3_PHY_157_DATA 0x00000000 -#define DDRSS3_PHY_158_DATA 0x00000000 -#define DDRSS3_PHY_159_DATA 0x00000000 -#define DDRSS3_PHY_160_DATA 0x00000000 -#define DDRSS3_PHY_161_DATA 0x00000000 -#define DDRSS3_PHY_162_DATA 0x00000000 -#define DDRSS3_PHY_163_DATA 0x00000000 -#define DDRSS3_PHY_164_DATA 0x00000000 -#define DDRSS3_PHY_165_DATA 0x00000000 -#define DDRSS3_PHY_166_DATA 0x00000000 -#define DDRSS3_PHY_167_DATA 0x00000000 -#define DDRSS3_PHY_168_DATA 0x00000000 -#define DDRSS3_PHY_169_DATA 0x00000000 -#define DDRSS3_PHY_170_DATA 0x00000000 -#define DDRSS3_PHY_171_DATA 0x00000000 -#define DDRSS3_PHY_172_DATA 0x00000000 -#define DDRSS3_PHY_173_DATA 0x00000000 -#define DDRSS3_PHY_174_DATA 0x00000000 -#define DDRSS3_PHY_175_DATA 0x00000000 -#define DDRSS3_PHY_176_DATA 0x00000000 -#define DDRSS3_PHY_177_DATA 0x00000000 -#define DDRSS3_PHY_178_DATA 0x00000000 -#define DDRSS3_PHY_179_DATA 0x00000000 -#define DDRSS3_PHY_180_DATA 0x00000000 -#define DDRSS3_PHY_181_DATA 0x00000000 -#define DDRSS3_PHY_182_DATA 0x00000000 -#define DDRSS3_PHY_183_DATA 0x00000000 -#define DDRSS3_PHY_184_DATA 0x00000000 -#define DDRSS3_PHY_185_DATA 0x00000000 -#define DDRSS3_PHY_186_DATA 0x00000000 -#define DDRSS3_PHY_187_DATA 0x00000000 -#define DDRSS3_PHY_188_DATA 0x00000000 -#define DDRSS3_PHY_189_DATA 0x00000000 -#define DDRSS3_PHY_190_DATA 0x00000000 -#define DDRSS3_PHY_191_DATA 0x00000000 -#define DDRSS3_PHY_192_DATA 0x00000000 -#define DDRSS3_PHY_193_DATA 0x00000000 -#define DDRSS3_PHY_194_DATA 0x00000000 -#define DDRSS3_PHY_195_DATA 0x00000000 -#define DDRSS3_PHY_196_DATA 0x00000000 -#define DDRSS3_PHY_197_DATA 0x00000000 -#define DDRSS3_PHY_198_DATA 0x00000000 -#define DDRSS3_PHY_199_DATA 0x00000000 -#define DDRSS3_PHY_200_DATA 0x00000000 -#define DDRSS3_PHY_201_DATA 0x00000000 -#define DDRSS3_PHY_202_DATA 0x00000000 -#define DDRSS3_PHY_203_DATA 0x00000000 -#define DDRSS3_PHY_204_DATA 0x00000000 -#define DDRSS3_PHY_205_DATA 0x00000000 -#define DDRSS3_PHY_206_DATA 0x00000000 -#define DDRSS3_PHY_207_DATA 0x00000000 -#define DDRSS3_PHY_208_DATA 0x00000000 -#define DDRSS3_PHY_209_DATA 0x00000000 -#define DDRSS3_PHY_210_DATA 0x00000000 -#define DDRSS3_PHY_211_DATA 0x00000000 -#define DDRSS3_PHY_212_DATA 0x00000000 -#define DDRSS3_PHY_213_DATA 0x00000000 -#define DDRSS3_PHY_214_DATA 0x00000000 -#define DDRSS3_PHY_215_DATA 0x00000000 -#define DDRSS3_PHY_216_DATA 0x00000000 -#define DDRSS3_PHY_217_DATA 0x00000000 -#define DDRSS3_PHY_218_DATA 0x00000000 -#define DDRSS3_PHY_219_DATA 0x00000000 -#define DDRSS3_PHY_220_DATA 0x00000000 -#define DDRSS3_PHY_221_DATA 0x00000000 -#define DDRSS3_PHY_222_DATA 0x00000000 -#define DDRSS3_PHY_223_DATA 0x00000000 -#define DDRSS3_PHY_224_DATA 0x00000000 -#define DDRSS3_PHY_225_DATA 0x00000000 -#define DDRSS3_PHY_226_DATA 0x00000000 -#define DDRSS3_PHY_227_DATA 0x00000000 -#define DDRSS3_PHY_228_DATA 0x00000000 -#define DDRSS3_PHY_229_DATA 0x00000000 -#define DDRSS3_PHY_230_DATA 0x00000000 -#define DDRSS3_PHY_231_DATA 0x00000000 -#define DDRSS3_PHY_232_DATA 0x00000000 -#define DDRSS3_PHY_233_DATA 0x00000000 -#define DDRSS3_PHY_234_DATA 0x00000000 -#define DDRSS3_PHY_235_DATA 0x00000000 -#define DDRSS3_PHY_236_DATA 0x00000000 -#define DDRSS3_PHY_237_DATA 0x00000000 -#define DDRSS3_PHY_238_DATA 0x00000000 -#define DDRSS3_PHY_239_DATA 0x00000000 -#define DDRSS3_PHY_240_DATA 0x00000000 -#define DDRSS3_PHY_241_DATA 0x00000000 -#define DDRSS3_PHY_242_DATA 0x00000000 -#define DDRSS3_PHY_243_DATA 0x00000000 -#define DDRSS3_PHY_244_DATA 0x00000000 -#define DDRSS3_PHY_245_DATA 0x00000000 -#define DDRSS3_PHY_246_DATA 0x00000000 -#define DDRSS3_PHY_247_DATA 0x00000000 -#define DDRSS3_PHY_248_DATA 0x00000000 -#define DDRSS3_PHY_249_DATA 0x00000000 -#define DDRSS3_PHY_250_DATA 0x00000000 -#define DDRSS3_PHY_251_DATA 0x00000000 -#define DDRSS3_PHY_252_DATA 0x00000000 -#define DDRSS3_PHY_253_DATA 0x00000000 -#define DDRSS3_PHY_254_DATA 0x00000000 -#define DDRSS3_PHY_255_DATA 0x00000000 -#define DDRSS3_PHY_256_DATA 0x000004F0 -#define DDRSS3_PHY_257_DATA 0x00000000 -#define DDRSS3_PHY_258_DATA 0x00030200 -#define DDRSS3_PHY_259_DATA 0x00000000 -#define DDRSS3_PHY_260_DATA 0x00000000 -#define DDRSS3_PHY_261_DATA 0x01030000 -#define DDRSS3_PHY_262_DATA 0x00010000 -#define DDRSS3_PHY_263_DATA 0x01030004 -#define DDRSS3_PHY_264_DATA 0x01000000 -#define DDRSS3_PHY_265_DATA 0x00000000 -#define DDRSS3_PHY_266_DATA 0x00000000 -#define DDRSS3_PHY_267_DATA 0x01000001 -#define DDRSS3_PHY_268_DATA 0x00000100 -#define DDRSS3_PHY_269_DATA 0x000800C0 -#define DDRSS3_PHY_270_DATA 0x060100CC -#define DDRSS3_PHY_271_DATA 0x00030066 -#define DDRSS3_PHY_272_DATA 0x00000000 -#define DDRSS3_PHY_273_DATA 0x00000301 -#define DDRSS3_PHY_274_DATA 0x0000AAAA -#define DDRSS3_PHY_275_DATA 0x00005555 -#define DDRSS3_PHY_276_DATA 0x0000B5B5 -#define DDRSS3_PHY_277_DATA 0x00004A4A -#define DDRSS3_PHY_278_DATA 0x00005656 -#define DDRSS3_PHY_279_DATA 0x0000A9A9 -#define DDRSS3_PHY_280_DATA 0x0000A9A9 -#define DDRSS3_PHY_281_DATA 0x0000B5B5 -#define DDRSS3_PHY_282_DATA 0x00000000 -#define DDRSS3_PHY_283_DATA 0x00000000 -#define DDRSS3_PHY_284_DATA 0x2A000000 -#define DDRSS3_PHY_285_DATA 0x00000808 -#define DDRSS3_PHY_286_DATA 0x0F000000 -#define DDRSS3_PHY_287_DATA 0x00000F0F -#define DDRSS3_PHY_288_DATA 0x10400000 -#define DDRSS3_PHY_289_DATA 0x0C002006 -#define DDRSS3_PHY_290_DATA 0x00000000 -#define DDRSS3_PHY_291_DATA 0x00000000 -#define DDRSS3_PHY_292_DATA 0x55555555 -#define DDRSS3_PHY_293_DATA 0xAAAAAAAA -#define DDRSS3_PHY_294_DATA 0x55555555 -#define DDRSS3_PHY_295_DATA 0xAAAAAAAA -#define DDRSS3_PHY_296_DATA 0x00005555 -#define DDRSS3_PHY_297_DATA 0x01000100 -#define DDRSS3_PHY_298_DATA 0x00800180 -#define DDRSS3_PHY_299_DATA 0x00000000 -#define DDRSS3_PHY_300_DATA 0x00000000 -#define DDRSS3_PHY_301_DATA 0x00000000 -#define DDRSS3_PHY_302_DATA 0x00000000 -#define DDRSS3_PHY_303_DATA 0x00000000 -#define DDRSS3_PHY_304_DATA 0x00000000 -#define DDRSS3_PHY_305_DATA 0x00000000 -#define DDRSS3_PHY_306_DATA 0x00000000 -#define DDRSS3_PHY_307_DATA 0x00000000 -#define DDRSS3_PHY_308_DATA 0x00000000 -#define DDRSS3_PHY_309_DATA 0x00000000 -#define DDRSS3_PHY_310_DATA 0x00000000 -#define DDRSS3_PHY_311_DATA 0x00000000 -#define DDRSS3_PHY_312_DATA 0x00000000 -#define DDRSS3_PHY_313_DATA 0x00000000 -#define DDRSS3_PHY_314_DATA 0x00000000 -#define DDRSS3_PHY_315_DATA 0x00000000 -#define DDRSS3_PHY_316_DATA 0x00000000 -#define DDRSS3_PHY_317_DATA 0x00000000 -#define DDRSS3_PHY_318_DATA 0x00000000 -#define DDRSS3_PHY_319_DATA 0x00000000 -#define DDRSS3_PHY_320_DATA 0x00000000 -#define DDRSS3_PHY_321_DATA 0x00000000 -#define DDRSS3_PHY_322_DATA 0x00000104 -#define DDRSS3_PHY_323_DATA 0x00000120 -#define DDRSS3_PHY_324_DATA 0x00000000 -#define DDRSS3_PHY_325_DATA 0x00000000 -#define DDRSS3_PHY_326_DATA 0x00000000 -#define DDRSS3_PHY_327_DATA 0x00000000 -#define DDRSS3_PHY_328_DATA 0x00000000 -#define DDRSS3_PHY_329_DATA 0x00000000 -#define DDRSS3_PHY_330_DATA 0x00000000 -#define DDRSS3_PHY_331_DATA 0x00000001 -#define DDRSS3_PHY_332_DATA 0x07FF0000 -#define DDRSS3_PHY_333_DATA 0x0080081F -#define DDRSS3_PHY_334_DATA 0x00081020 -#define DDRSS3_PHY_335_DATA 0x04010000 -#define DDRSS3_PHY_336_DATA 0x00000000 -#define DDRSS3_PHY_337_DATA 0x00000000 -#define DDRSS3_PHY_338_DATA 0x00000000 -#define DDRSS3_PHY_339_DATA 0x00000100 -#define DDRSS3_PHY_340_DATA 0x01CC0C01 -#define DDRSS3_PHY_341_DATA 0x1003CC0C -#define DDRSS3_PHY_342_DATA 0x20000140 -#define DDRSS3_PHY_343_DATA 0x07FF0200 -#define DDRSS3_PHY_344_DATA 0x0000DD01 -#define DDRSS3_PHY_345_DATA 0x10100303 -#define DDRSS3_PHY_346_DATA 0x10101010 -#define DDRSS3_PHY_347_DATA 0x10101010 -#define DDRSS3_PHY_348_DATA 0x00021010 -#define DDRSS3_PHY_349_DATA 0x00100010 -#define DDRSS3_PHY_350_DATA 0x00100010 -#define DDRSS3_PHY_351_DATA 0x00100010 -#define DDRSS3_PHY_352_DATA 0x00100010 -#define DDRSS3_PHY_353_DATA 0x00050010 -#define DDRSS3_PHY_354_DATA 0x51517041 -#define DDRSS3_PHY_355_DATA 0x31C06001 -#define DDRSS3_PHY_356_DATA 0x07AB0340 -#define DDRSS3_PHY_357_DATA 0x00C0C001 -#define DDRSS3_PHY_358_DATA 0x0E0D0001 -#define DDRSS3_PHY_359_DATA 0x10001000 -#define DDRSS3_PHY_360_DATA 0x0C083E42 -#define DDRSS3_PHY_361_DATA 0x0F0C3701 -#define DDRSS3_PHY_362_DATA 0x01000140 -#define DDRSS3_PHY_363_DATA 0x0C000420 -#define DDRSS3_PHY_364_DATA 0x00000198 -#define DDRSS3_PHY_365_DATA 0x0A0000D0 -#define DDRSS3_PHY_366_DATA 0x00030200 -#define DDRSS3_PHY_367_DATA 0x02800000 -#define DDRSS3_PHY_368_DATA 0x80800000 -#define DDRSS3_PHY_369_DATA 0x000E2010 -#define DDRSS3_PHY_370_DATA 0x76543210 -#define DDRSS3_PHY_371_DATA 0x00000008 -#define DDRSS3_PHY_372_DATA 0x02800280 -#define DDRSS3_PHY_373_DATA 0x02800280 -#define DDRSS3_PHY_374_DATA 0x02800280 -#define DDRSS3_PHY_375_DATA 0x02800280 -#define DDRSS3_PHY_376_DATA 0x00000280 -#define DDRSS3_PHY_377_DATA 0x0000A000 -#define DDRSS3_PHY_378_DATA 0x00A000A0 -#define DDRSS3_PHY_379_DATA 0x00A000A0 -#define DDRSS3_PHY_380_DATA 0x00A000A0 -#define DDRSS3_PHY_381_DATA 0x00A000A0 -#define DDRSS3_PHY_382_DATA 0x00A000A0 -#define DDRSS3_PHY_383_DATA 0x00A000A0 -#define DDRSS3_PHY_384_DATA 0x00A000A0 -#define DDRSS3_PHY_385_DATA 0x00A000A0 -#define DDRSS3_PHY_386_DATA 0x01C200A0 -#define DDRSS3_PHY_387_DATA 0x01A00005 -#define DDRSS3_PHY_388_DATA 0x00000000 -#define DDRSS3_PHY_389_DATA 0x00000000 -#define DDRSS3_PHY_390_DATA 0x00080200 -#define DDRSS3_PHY_391_DATA 0x00000000 -#define DDRSS3_PHY_392_DATA 0x20202000 -#define DDRSS3_PHY_393_DATA 0x20202020 -#define DDRSS3_PHY_394_DATA 0xF0F02020 -#define DDRSS3_PHY_395_DATA 0x00000000 -#define DDRSS3_PHY_396_DATA 0x00000000 -#define DDRSS3_PHY_397_DATA 0x00000000 -#define DDRSS3_PHY_398_DATA 0x00000000 -#define DDRSS3_PHY_399_DATA 0x00000000 -#define DDRSS3_PHY_400_DATA 0x00000000 -#define DDRSS3_PHY_401_DATA 0x00000000 -#define DDRSS3_PHY_402_DATA 0x00000000 -#define DDRSS3_PHY_403_DATA 0x00000000 -#define DDRSS3_PHY_404_DATA 0x00000000 -#define DDRSS3_PHY_405_DATA 0x00000000 -#define DDRSS3_PHY_406_DATA 0x00000000 -#define DDRSS3_PHY_407_DATA 0x00000000 -#define DDRSS3_PHY_408_DATA 0x00000000 -#define DDRSS3_PHY_409_DATA 0x00000000 -#define DDRSS3_PHY_410_DATA 0x00000000 -#define DDRSS3_PHY_411_DATA 0x00000000 -#define DDRSS3_PHY_412_DATA 0x00000000 -#define DDRSS3_PHY_413_DATA 0x00000000 -#define DDRSS3_PHY_414_DATA 0x00000000 -#define DDRSS3_PHY_415_DATA 0x00000000 -#define DDRSS3_PHY_416_DATA 0x00000000 -#define DDRSS3_PHY_417_DATA 0x00000000 -#define DDRSS3_PHY_418_DATA 0x00000000 -#define DDRSS3_PHY_419_DATA 0x00000000 -#define DDRSS3_PHY_420_DATA 0x00000000 -#define DDRSS3_PHY_421_DATA 0x00000000 -#define DDRSS3_PHY_422_DATA 0x00000000 -#define DDRSS3_PHY_423_DATA 0x00000000 -#define DDRSS3_PHY_424_DATA 0x00000000 -#define DDRSS3_PHY_425_DATA 0x00000000 -#define DDRSS3_PHY_426_DATA 0x00000000 -#define DDRSS3_PHY_427_DATA 0x00000000 -#define DDRSS3_PHY_428_DATA 0x00000000 -#define DDRSS3_PHY_429_DATA 0x00000000 -#define DDRSS3_PHY_430_DATA 0x00000000 -#define DDRSS3_PHY_431_DATA 0x00000000 -#define DDRSS3_PHY_432_DATA 0x00000000 -#define DDRSS3_PHY_433_DATA 0x00000000 -#define DDRSS3_PHY_434_DATA 0x00000000 -#define DDRSS3_PHY_435_DATA 0x00000000 -#define DDRSS3_PHY_436_DATA 0x00000000 -#define DDRSS3_PHY_437_DATA 0x00000000 -#define DDRSS3_PHY_438_DATA 0x00000000 -#define DDRSS3_PHY_439_DATA 0x00000000 -#define DDRSS3_PHY_440_DATA 0x00000000 -#define DDRSS3_PHY_441_DATA 0x00000000 -#define DDRSS3_PHY_442_DATA 0x00000000 -#define DDRSS3_PHY_443_DATA 0x00000000 -#define DDRSS3_PHY_444_DATA 0x00000000 -#define DDRSS3_PHY_445_DATA 0x00000000 -#define DDRSS3_PHY_446_DATA 0x00000000 -#define DDRSS3_PHY_447_DATA 0x00000000 -#define DDRSS3_PHY_448_DATA 0x00000000 -#define DDRSS3_PHY_449_DATA 0x00000000 -#define DDRSS3_PHY_450_DATA 0x00000000 -#define DDRSS3_PHY_451_DATA 0x00000000 -#define DDRSS3_PHY_452_DATA 0x00000000 -#define DDRSS3_PHY_453_DATA 0x00000000 -#define DDRSS3_PHY_454_DATA 0x00000000 -#define DDRSS3_PHY_455_DATA 0x00000000 -#define DDRSS3_PHY_456_DATA 0x00000000 -#define DDRSS3_PHY_457_DATA 0x00000000 -#define DDRSS3_PHY_458_DATA 0x00000000 -#define DDRSS3_PHY_459_DATA 0x00000000 -#define DDRSS3_PHY_460_DATA 0x00000000 -#define DDRSS3_PHY_461_DATA 0x00000000 -#define DDRSS3_PHY_462_DATA 0x00000000 -#define DDRSS3_PHY_463_DATA 0x00000000 -#define DDRSS3_PHY_464_DATA 0x00000000 -#define DDRSS3_PHY_465_DATA 0x00000000 -#define DDRSS3_PHY_466_DATA 0x00000000 -#define DDRSS3_PHY_467_DATA 0x00000000 -#define DDRSS3_PHY_468_DATA 0x00000000 -#define DDRSS3_PHY_469_DATA 0x00000000 -#define DDRSS3_PHY_470_DATA 0x00000000 -#define DDRSS3_PHY_471_DATA 0x00000000 -#define DDRSS3_PHY_472_DATA 0x00000000 -#define DDRSS3_PHY_473_DATA 0x00000000 -#define DDRSS3_PHY_474_DATA 0x00000000 -#define DDRSS3_PHY_475_DATA 0x00000000 -#define DDRSS3_PHY_476_DATA 0x00000000 -#define DDRSS3_PHY_477_DATA 0x00000000 -#define DDRSS3_PHY_478_DATA 0x00000000 -#define DDRSS3_PHY_479_DATA 0x00000000 -#define DDRSS3_PHY_480_DATA 0x00000000 -#define DDRSS3_PHY_481_DATA 0x00000000 -#define DDRSS3_PHY_482_DATA 0x00000000 -#define DDRSS3_PHY_483_DATA 0x00000000 -#define DDRSS3_PHY_484_DATA 0x00000000 -#define DDRSS3_PHY_485_DATA 0x00000000 -#define DDRSS3_PHY_486_DATA 0x00000000 -#define DDRSS3_PHY_487_DATA 0x00000000 -#define DDRSS3_PHY_488_DATA 0x00000000 -#define DDRSS3_PHY_489_DATA 0x00000000 -#define DDRSS3_PHY_490_DATA 0x00000000 -#define DDRSS3_PHY_491_DATA 0x00000000 -#define DDRSS3_PHY_492_DATA 0x00000000 -#define DDRSS3_PHY_493_DATA 0x00000000 -#define DDRSS3_PHY_494_DATA 0x00000000 -#define DDRSS3_PHY_495_DATA 0x00000000 -#define DDRSS3_PHY_496_DATA 0x00000000 -#define DDRSS3_PHY_497_DATA 0x00000000 -#define DDRSS3_PHY_498_DATA 0x00000000 -#define DDRSS3_PHY_499_DATA 0x00000000 -#define DDRSS3_PHY_500_DATA 0x00000000 -#define DDRSS3_PHY_501_DATA 0x00000000 -#define DDRSS3_PHY_502_DATA 0x00000000 -#define DDRSS3_PHY_503_DATA 0x00000000 -#define DDRSS3_PHY_504_DATA 0x00000000 -#define DDRSS3_PHY_505_DATA 0x00000000 -#define DDRSS3_PHY_506_DATA 0x00000000 -#define DDRSS3_PHY_507_DATA 0x00000000 -#define DDRSS3_PHY_508_DATA 0x00000000 -#define DDRSS3_PHY_509_DATA 0x00000000 -#define DDRSS3_PHY_510_DATA 0x00000000 -#define DDRSS3_PHY_511_DATA 0x00000000 -#define DDRSS3_PHY_512_DATA 0x000004F0 -#define DDRSS3_PHY_513_DATA 0x00000000 -#define DDRSS3_PHY_514_DATA 0x00030200 -#define DDRSS3_PHY_515_DATA 0x00000000 -#define DDRSS3_PHY_516_DATA 0x00000000 -#define DDRSS3_PHY_517_DATA 0x01030000 -#define DDRSS3_PHY_518_DATA 0x00010000 -#define DDRSS3_PHY_519_DATA 0x01030004 -#define DDRSS3_PHY_520_DATA 0x01000000 -#define DDRSS3_PHY_521_DATA 0x00000000 -#define DDRSS3_PHY_522_DATA 0x00000000 -#define DDRSS3_PHY_523_DATA 0x01000001 -#define DDRSS3_PHY_524_DATA 0x00000100 -#define DDRSS3_PHY_525_DATA 0x000800C0 -#define DDRSS3_PHY_526_DATA 0x060100CC -#define DDRSS3_PHY_527_DATA 0x00030066 -#define DDRSS3_PHY_528_DATA 0x00000000 -#define DDRSS3_PHY_529_DATA 0x00000301 -#define DDRSS3_PHY_530_DATA 0x0000AAAA -#define DDRSS3_PHY_531_DATA 0x00005555 -#define DDRSS3_PHY_532_DATA 0x0000B5B5 -#define DDRSS3_PHY_533_DATA 0x00004A4A -#define DDRSS3_PHY_534_DATA 0x00005656 -#define DDRSS3_PHY_535_DATA 0x0000A9A9 -#define DDRSS3_PHY_536_DATA 0x0000A9A9 -#define DDRSS3_PHY_537_DATA 0x0000B5B5 -#define DDRSS3_PHY_538_DATA 0x00000000 -#define DDRSS3_PHY_539_DATA 0x00000000 -#define DDRSS3_PHY_540_DATA 0x2A000000 -#define DDRSS3_PHY_541_DATA 0x00000808 -#define DDRSS3_PHY_542_DATA 0x0F000000 -#define DDRSS3_PHY_543_DATA 0x00000F0F -#define DDRSS3_PHY_544_DATA 0x10400000 -#define DDRSS3_PHY_545_DATA 0x0C002006 -#define DDRSS3_PHY_546_DATA 0x00000000 -#define DDRSS3_PHY_547_DATA 0x00000000 -#define DDRSS3_PHY_548_DATA 0x55555555 -#define DDRSS3_PHY_549_DATA 0xAAAAAAAA -#define DDRSS3_PHY_550_DATA 0x55555555 -#define DDRSS3_PHY_551_DATA 0xAAAAAAAA -#define DDRSS3_PHY_552_DATA 0x00005555 -#define DDRSS3_PHY_553_DATA 0x01000100 -#define DDRSS3_PHY_554_DATA 0x00800180 -#define DDRSS3_PHY_555_DATA 0x00000001 -#define DDRSS3_PHY_556_DATA 0x00000000 -#define DDRSS3_PHY_557_DATA 0x00000000 -#define DDRSS3_PHY_558_DATA 0x00000000 -#define DDRSS3_PHY_559_DATA 0x00000000 -#define DDRSS3_PHY_560_DATA 0x00000000 -#define DDRSS3_PHY_561_DATA 0x00000000 -#define DDRSS3_PHY_562_DATA 0x00000000 -#define DDRSS3_PHY_563_DATA 0x00000000 -#define DDRSS3_PHY_564_DATA 0x00000000 -#define DDRSS3_PHY_565_DATA 0x00000000 -#define DDRSS3_PHY_566_DATA 0x00000000 -#define DDRSS3_PHY_567_DATA 0x00000000 -#define DDRSS3_PHY_568_DATA 0x00000000 -#define DDRSS3_PHY_569_DATA 0x00000000 -#define DDRSS3_PHY_570_DATA 0x00000000 -#define DDRSS3_PHY_571_DATA 0x00000000 -#define DDRSS3_PHY_572_DATA 0x00000000 -#define DDRSS3_PHY_573_DATA 0x00000000 -#define DDRSS3_PHY_574_DATA 0x00000000 -#define DDRSS3_PHY_575_DATA 0x00000000 -#define DDRSS3_PHY_576_DATA 0x00000000 -#define DDRSS3_PHY_577_DATA 0x00000000 -#define DDRSS3_PHY_578_DATA 0x00000104 -#define DDRSS3_PHY_579_DATA 0x00000120 -#define DDRSS3_PHY_580_DATA 0x00000000 -#define DDRSS3_PHY_581_DATA 0x00000000 -#define DDRSS3_PHY_582_DATA 0x00000000 -#define DDRSS3_PHY_583_DATA 0x00000000 -#define DDRSS3_PHY_584_DATA 0x00000000 -#define DDRSS3_PHY_585_DATA 0x00000000 -#define DDRSS3_PHY_586_DATA 0x00000000 -#define DDRSS3_PHY_587_DATA 0x00000001 -#define DDRSS3_PHY_588_DATA 0x07FF0000 -#define DDRSS3_PHY_589_DATA 0x0080081F -#define DDRSS3_PHY_590_DATA 0x00081020 -#define DDRSS3_PHY_591_DATA 0x04010000 -#define DDRSS3_PHY_592_DATA 0x00000000 -#define DDRSS3_PHY_593_DATA 0x00000000 -#define DDRSS3_PHY_594_DATA 0x00000000 -#define DDRSS3_PHY_595_DATA 0x00000100 -#define DDRSS3_PHY_596_DATA 0x01CC0C01 -#define DDRSS3_PHY_597_DATA 0x1003CC0C -#define DDRSS3_PHY_598_DATA 0x20000140 -#define DDRSS3_PHY_599_DATA 0x07FF0200 -#define DDRSS3_PHY_600_DATA 0x0000DD01 -#define DDRSS3_PHY_601_DATA 0x10100303 -#define DDRSS3_PHY_602_DATA 0x10101010 -#define DDRSS3_PHY_603_DATA 0x10101010 -#define DDRSS3_PHY_604_DATA 0x00021010 -#define DDRSS3_PHY_605_DATA 0x00100010 -#define DDRSS3_PHY_606_DATA 0x00100010 -#define DDRSS3_PHY_607_DATA 0x00100010 -#define DDRSS3_PHY_608_DATA 0x00100010 -#define DDRSS3_PHY_609_DATA 0x00050010 -#define DDRSS3_PHY_610_DATA 0x51517041 -#define DDRSS3_PHY_611_DATA 0x31C06001 -#define DDRSS3_PHY_612_DATA 0x07AB0340 -#define DDRSS3_PHY_613_DATA 0x00C0C001 -#define DDRSS3_PHY_614_DATA 0x0E0D0001 -#define DDRSS3_PHY_615_DATA 0x10001000 -#define DDRSS3_PHY_616_DATA 0x0C083E42 -#define DDRSS3_PHY_617_DATA 0x0F0C3701 -#define DDRSS3_PHY_618_DATA 0x01000140 -#define DDRSS3_PHY_619_DATA 0x0C000420 -#define DDRSS3_PHY_620_DATA 0x00000198 -#define DDRSS3_PHY_621_DATA 0x0A0000D0 -#define DDRSS3_PHY_622_DATA 0x00030200 -#define DDRSS3_PHY_623_DATA 0x02800000 -#define DDRSS3_PHY_624_DATA 0x80800000 -#define DDRSS3_PHY_625_DATA 0x000E2010 -#define DDRSS3_PHY_626_DATA 0x76543210 -#define DDRSS3_PHY_627_DATA 0x00000008 -#define DDRSS3_PHY_628_DATA 0x02800280 -#define DDRSS3_PHY_629_DATA 0x02800280 -#define DDRSS3_PHY_630_DATA 0x02800280 -#define DDRSS3_PHY_631_DATA 0x02800280 -#define DDRSS3_PHY_632_DATA 0x00000280 -#define DDRSS3_PHY_633_DATA 0x0000A000 -#define DDRSS3_PHY_634_DATA 0x00A000A0 -#define DDRSS3_PHY_635_DATA 0x00A000A0 -#define DDRSS3_PHY_636_DATA 0x00A000A0 -#define DDRSS3_PHY_637_DATA 0x00A000A0 -#define DDRSS3_PHY_638_DATA 0x00A000A0 -#define DDRSS3_PHY_639_DATA 0x00A000A0 -#define DDRSS3_PHY_640_DATA 0x00A000A0 -#define DDRSS3_PHY_641_DATA 0x00A000A0 -#define DDRSS3_PHY_642_DATA 0x01C200A0 -#define DDRSS3_PHY_643_DATA 0x01A00005 -#define DDRSS3_PHY_644_DATA 0x00000000 -#define DDRSS3_PHY_645_DATA 0x00000000 -#define DDRSS3_PHY_646_DATA 0x00080200 -#define DDRSS3_PHY_647_DATA 0x00000000 -#define DDRSS3_PHY_648_DATA 0x20202000 -#define DDRSS3_PHY_649_DATA 0x20202020 -#define DDRSS3_PHY_650_DATA 0xF0F02020 -#define DDRSS3_PHY_651_DATA 0x00000000 -#define DDRSS3_PHY_652_DATA 0x00000000 -#define DDRSS3_PHY_653_DATA 0x00000000 -#define DDRSS3_PHY_654_DATA 0x00000000 -#define DDRSS3_PHY_655_DATA 0x00000000 -#define DDRSS3_PHY_656_DATA 0x00000000 -#define DDRSS3_PHY_657_DATA 0x00000000 -#define DDRSS3_PHY_658_DATA 0x00000000 -#define DDRSS3_PHY_659_DATA 0x00000000 -#define DDRSS3_PHY_660_DATA 0x00000000 -#define DDRSS3_PHY_661_DATA 0x00000000 -#define DDRSS3_PHY_662_DATA 0x00000000 -#define DDRSS3_PHY_663_DATA 0x00000000 -#define DDRSS3_PHY_664_DATA 0x00000000 -#define DDRSS3_PHY_665_DATA 0x00000000 -#define DDRSS3_PHY_666_DATA 0x00000000 -#define DDRSS3_PHY_667_DATA 0x00000000 -#define DDRSS3_PHY_668_DATA 0x00000000 -#define DDRSS3_PHY_669_DATA 0x00000000 -#define DDRSS3_PHY_670_DATA 0x00000000 -#define DDRSS3_PHY_671_DATA 0x00000000 -#define DDRSS3_PHY_672_DATA 0x00000000 -#define DDRSS3_PHY_673_DATA 0x00000000 -#define DDRSS3_PHY_674_DATA 0x00000000 -#define DDRSS3_PHY_675_DATA 0x00000000 -#define DDRSS3_PHY_676_DATA 0x00000000 -#define DDRSS3_PHY_677_DATA 0x00000000 -#define DDRSS3_PHY_678_DATA 0x00000000 -#define DDRSS3_PHY_679_DATA 0x00000000 -#define DDRSS3_PHY_680_DATA 0x00000000 -#define DDRSS3_PHY_681_DATA 0x00000000 -#define DDRSS3_PHY_682_DATA 0x00000000 -#define DDRSS3_PHY_683_DATA 0x00000000 -#define DDRSS3_PHY_684_DATA 0x00000000 -#define DDRSS3_PHY_685_DATA 0x00000000 -#define DDRSS3_PHY_686_DATA 0x00000000 -#define DDRSS3_PHY_687_DATA 0x00000000 -#define DDRSS3_PHY_688_DATA 0x00000000 -#define DDRSS3_PHY_689_DATA 0x00000000 -#define DDRSS3_PHY_690_DATA 0x00000000 -#define DDRSS3_PHY_691_DATA 0x00000000 -#define DDRSS3_PHY_692_DATA 0x00000000 -#define DDRSS3_PHY_693_DATA 0x00000000 -#define DDRSS3_PHY_694_DATA 0x00000000 -#define DDRSS3_PHY_695_DATA 0x00000000 -#define DDRSS3_PHY_696_DATA 0x00000000 -#define DDRSS3_PHY_697_DATA 0x00000000 -#define DDRSS3_PHY_698_DATA 0x00000000 -#define DDRSS3_PHY_699_DATA 0x00000000 -#define DDRSS3_PHY_700_DATA 0x00000000 -#define DDRSS3_PHY_701_DATA 0x00000000 -#define DDRSS3_PHY_702_DATA 0x00000000 -#define DDRSS3_PHY_703_DATA 0x00000000 -#define DDRSS3_PHY_704_DATA 0x00000000 -#define DDRSS3_PHY_705_DATA 0x00000000 -#define DDRSS3_PHY_706_DATA 0x00000000 -#define DDRSS3_PHY_707_DATA 0x00000000 -#define DDRSS3_PHY_708_DATA 0x00000000 -#define DDRSS3_PHY_709_DATA 0x00000000 -#define DDRSS3_PHY_710_DATA 0x00000000 -#define DDRSS3_PHY_711_DATA 0x00000000 -#define DDRSS3_PHY_712_DATA 0x00000000 -#define DDRSS3_PHY_713_DATA 0x00000000 -#define DDRSS3_PHY_714_DATA 0x00000000 -#define DDRSS3_PHY_715_DATA 0x00000000 -#define DDRSS3_PHY_716_DATA 0x00000000 -#define DDRSS3_PHY_717_DATA 0x00000000 -#define DDRSS3_PHY_718_DATA 0x00000000 -#define DDRSS3_PHY_719_DATA 0x00000000 -#define DDRSS3_PHY_720_DATA 0x00000000 -#define DDRSS3_PHY_721_DATA 0x00000000 -#define DDRSS3_PHY_722_DATA 0x00000000 -#define DDRSS3_PHY_723_DATA 0x00000000 -#define DDRSS3_PHY_724_DATA 0x00000000 -#define DDRSS3_PHY_725_DATA 0x00000000 -#define DDRSS3_PHY_726_DATA 0x00000000 -#define DDRSS3_PHY_727_DATA 0x00000000 -#define DDRSS3_PHY_728_DATA 0x00000000 -#define DDRSS3_PHY_729_DATA 0x00000000 -#define DDRSS3_PHY_730_DATA 0x00000000 -#define DDRSS3_PHY_731_DATA 0x00000000 -#define DDRSS3_PHY_732_DATA 0x00000000 -#define DDRSS3_PHY_733_DATA 0x00000000 -#define DDRSS3_PHY_734_DATA 0x00000000 -#define DDRSS3_PHY_735_DATA 0x00000000 -#define DDRSS3_PHY_736_DATA 0x00000000 -#define DDRSS3_PHY_737_DATA 0x00000000 -#define DDRSS3_PHY_738_DATA 0x00000000 -#define DDRSS3_PHY_739_DATA 0x00000000 -#define DDRSS3_PHY_740_DATA 0x00000000 -#define DDRSS3_PHY_741_DATA 0x00000000 -#define DDRSS3_PHY_742_DATA 0x00000000 -#define DDRSS3_PHY_743_DATA 0x00000000 -#define DDRSS3_PHY_744_DATA 0x00000000 -#define DDRSS3_PHY_745_DATA 0x00000000 -#define DDRSS3_PHY_746_DATA 0x00000000 -#define DDRSS3_PHY_747_DATA 0x00000000 -#define DDRSS3_PHY_748_DATA 0x00000000 -#define DDRSS3_PHY_749_DATA 0x00000000 -#define DDRSS3_PHY_750_DATA 0x00000000 -#define DDRSS3_PHY_751_DATA 0x00000000 -#define DDRSS3_PHY_752_DATA 0x00000000 -#define DDRSS3_PHY_753_DATA 0x00000000 -#define DDRSS3_PHY_754_DATA 0x00000000 -#define DDRSS3_PHY_755_DATA 0x00000000 -#define DDRSS3_PHY_756_DATA 0x00000000 -#define DDRSS3_PHY_757_DATA 0x00000000 -#define DDRSS3_PHY_758_DATA 0x00000000 -#define DDRSS3_PHY_759_DATA 0x00000000 -#define DDRSS3_PHY_760_DATA 0x00000000 -#define DDRSS3_PHY_761_DATA 0x00000000 -#define DDRSS3_PHY_762_DATA 0x00000000 -#define DDRSS3_PHY_763_DATA 0x00000000 -#define DDRSS3_PHY_764_DATA 0x00000000 -#define DDRSS3_PHY_765_DATA 0x00000000 -#define DDRSS3_PHY_766_DATA 0x00000000 -#define DDRSS3_PHY_767_DATA 0x00000000 -#define DDRSS3_PHY_768_DATA 0x000004F0 -#define DDRSS3_PHY_769_DATA 0x00000000 -#define DDRSS3_PHY_770_DATA 0x00030200 -#define DDRSS3_PHY_771_DATA 0x00000000 -#define DDRSS3_PHY_772_DATA 0x00000000 -#define DDRSS3_PHY_773_DATA 0x01030000 -#define DDRSS3_PHY_774_DATA 0x00010000 -#define DDRSS3_PHY_775_DATA 0x01030004 -#define DDRSS3_PHY_776_DATA 0x01000000 -#define DDRSS3_PHY_777_DATA 0x00000000 -#define DDRSS3_PHY_778_DATA 0x00000000 -#define DDRSS3_PHY_779_DATA 0x01000001 -#define DDRSS3_PHY_780_DATA 0x00000100 -#define DDRSS3_PHY_781_DATA 0x000800C0 -#define DDRSS3_PHY_782_DATA 0x060100CC -#define DDRSS3_PHY_783_DATA 0x00030066 -#define DDRSS3_PHY_784_DATA 0x00000000 -#define DDRSS3_PHY_785_DATA 0x00000301 -#define DDRSS3_PHY_786_DATA 0x0000AAAA -#define DDRSS3_PHY_787_DATA 0x00005555 -#define DDRSS3_PHY_788_DATA 0x0000B5B5 -#define DDRSS3_PHY_789_DATA 0x00004A4A -#define DDRSS3_PHY_790_DATA 0x00005656 -#define DDRSS3_PHY_791_DATA 0x0000A9A9 -#define DDRSS3_PHY_792_DATA 0x0000A9A9 -#define DDRSS3_PHY_793_DATA 0x0000B5B5 -#define DDRSS3_PHY_794_DATA 0x00000000 -#define DDRSS3_PHY_795_DATA 0x00000000 -#define DDRSS3_PHY_796_DATA 0x2A000000 -#define DDRSS3_PHY_797_DATA 0x00000808 -#define DDRSS3_PHY_798_DATA 0x0F000000 -#define DDRSS3_PHY_799_DATA 0x00000F0F -#define DDRSS3_PHY_800_DATA 0x10400000 -#define DDRSS3_PHY_801_DATA 0x0C002006 -#define DDRSS3_PHY_802_DATA 0x00000000 -#define DDRSS3_PHY_803_DATA 0x00000000 -#define DDRSS3_PHY_804_DATA 0x55555555 -#define DDRSS3_PHY_805_DATA 0xAAAAAAAA -#define DDRSS3_PHY_806_DATA 0x55555555 -#define DDRSS3_PHY_807_DATA 0xAAAAAAAA -#define DDRSS3_PHY_808_DATA 0x00005555 -#define DDRSS3_PHY_809_DATA 0x01000100 -#define DDRSS3_PHY_810_DATA 0x00800180 -#define DDRSS3_PHY_811_DATA 0x00000000 -#define DDRSS3_PHY_812_DATA 0x00000000 -#define DDRSS3_PHY_813_DATA 0x00000000 -#define DDRSS3_PHY_814_DATA 0x00000000 -#define DDRSS3_PHY_815_DATA 0x00000000 -#define DDRSS3_PHY_816_DATA 0x00000000 -#define DDRSS3_PHY_817_DATA 0x00000000 -#define DDRSS3_PHY_818_DATA 0x00000000 -#define DDRSS3_PHY_819_DATA 0x00000000 -#define DDRSS3_PHY_820_DATA 0x00000000 -#define DDRSS3_PHY_821_DATA 0x00000000 -#define DDRSS3_PHY_822_DATA 0x00000000 -#define DDRSS3_PHY_823_DATA 0x00000000 -#define DDRSS3_PHY_824_DATA 0x00000000 -#define DDRSS3_PHY_825_DATA 0x00000000 -#define DDRSS3_PHY_826_DATA 0x00000000 -#define DDRSS3_PHY_827_DATA 0x00000000 -#define DDRSS3_PHY_828_DATA 0x00000000 -#define DDRSS3_PHY_829_DATA 0x00000000 -#define DDRSS3_PHY_830_DATA 0x00000000 -#define DDRSS3_PHY_831_DATA 0x00000000 -#define DDRSS3_PHY_832_DATA 0x00000000 -#define DDRSS3_PHY_833_DATA 0x00000000 -#define DDRSS3_PHY_834_DATA 0x00000104 -#define DDRSS3_PHY_835_DATA 0x00000120 -#define DDRSS3_PHY_836_DATA 0x00000000 -#define DDRSS3_PHY_837_DATA 0x00000000 -#define DDRSS3_PHY_838_DATA 0x00000000 -#define DDRSS3_PHY_839_DATA 0x00000000 -#define DDRSS3_PHY_840_DATA 0x00000000 -#define DDRSS3_PHY_841_DATA 0x00000000 -#define DDRSS3_PHY_842_DATA 0x00000000 -#define DDRSS3_PHY_843_DATA 0x00000001 -#define DDRSS3_PHY_844_DATA 0x07FF0000 -#define DDRSS3_PHY_845_DATA 0x0080081F -#define DDRSS3_PHY_846_DATA 0x00081020 -#define DDRSS3_PHY_847_DATA 0x04010000 -#define DDRSS3_PHY_848_DATA 0x00000000 -#define DDRSS3_PHY_849_DATA 0x00000000 -#define DDRSS3_PHY_850_DATA 0x00000000 -#define DDRSS3_PHY_851_DATA 0x00000100 -#define DDRSS3_PHY_852_DATA 0x01CC0C01 -#define DDRSS3_PHY_853_DATA 0x1003CC0C -#define DDRSS3_PHY_854_DATA 0x20000140 -#define DDRSS3_PHY_855_DATA 0x07FF0200 -#define DDRSS3_PHY_856_DATA 0x0000DD01 -#define DDRSS3_PHY_857_DATA 0x10100303 -#define DDRSS3_PHY_858_DATA 0x10101010 -#define DDRSS3_PHY_859_DATA 0x10101010 -#define DDRSS3_PHY_860_DATA 0x00021010 -#define DDRSS3_PHY_861_DATA 0x00100010 -#define DDRSS3_PHY_862_DATA 0x00100010 -#define DDRSS3_PHY_863_DATA 0x00100010 -#define DDRSS3_PHY_864_DATA 0x00100010 -#define DDRSS3_PHY_865_DATA 0x00050010 -#define DDRSS3_PHY_866_DATA 0x51517041 -#define DDRSS3_PHY_867_DATA 0x31C06001 -#define DDRSS3_PHY_868_DATA 0x07AB0340 -#define DDRSS3_PHY_869_DATA 0x00C0C001 -#define DDRSS3_PHY_870_DATA 0x0E0D0001 -#define DDRSS3_PHY_871_DATA 0x10001000 -#define DDRSS3_PHY_872_DATA 0x0C083E42 -#define DDRSS3_PHY_873_DATA 0x0F0C3701 -#define DDRSS3_PHY_874_DATA 0x01000140 -#define DDRSS3_PHY_875_DATA 0x0C000420 -#define DDRSS3_PHY_876_DATA 0x00000198 -#define DDRSS3_PHY_877_DATA 0x0A0000D0 -#define DDRSS3_PHY_878_DATA 0x00030200 -#define DDRSS3_PHY_879_DATA 0x02800000 -#define DDRSS3_PHY_880_DATA 0x80800000 -#define DDRSS3_PHY_881_DATA 0x000E2010 -#define DDRSS3_PHY_882_DATA 0x76543210 -#define DDRSS3_PHY_883_DATA 0x00000008 -#define DDRSS3_PHY_884_DATA 0x02800280 -#define DDRSS3_PHY_885_DATA 0x02800280 -#define DDRSS3_PHY_886_DATA 0x02800280 -#define DDRSS3_PHY_887_DATA 0x02800280 -#define DDRSS3_PHY_888_DATA 0x00000280 -#define DDRSS3_PHY_889_DATA 0x0000A000 -#define DDRSS3_PHY_890_DATA 0x00A000A0 -#define DDRSS3_PHY_891_DATA 0x00A000A0 -#define DDRSS3_PHY_892_DATA 0x00A000A0 -#define DDRSS3_PHY_893_DATA 0x00A000A0 -#define DDRSS3_PHY_894_DATA 0x00A000A0 -#define DDRSS3_PHY_895_DATA 0x00A000A0 -#define DDRSS3_PHY_896_DATA 0x00A000A0 -#define DDRSS3_PHY_897_DATA 0x00A000A0 -#define DDRSS3_PHY_898_DATA 0x01C200A0 -#define DDRSS3_PHY_899_DATA 0x01A00005 -#define DDRSS3_PHY_900_DATA 0x00000000 -#define DDRSS3_PHY_901_DATA 0x00000000 -#define DDRSS3_PHY_902_DATA 0x00080200 -#define DDRSS3_PHY_903_DATA 0x00000000 -#define DDRSS3_PHY_904_DATA 0x20202000 -#define DDRSS3_PHY_905_DATA 0x20202020 -#define DDRSS3_PHY_906_DATA 0xF0F02020 -#define DDRSS3_PHY_907_DATA 0x00000000 -#define DDRSS3_PHY_908_DATA 0x00000000 -#define DDRSS3_PHY_909_DATA 0x00000000 -#define DDRSS3_PHY_910_DATA 0x00000000 -#define DDRSS3_PHY_911_DATA 0x00000000 -#define DDRSS3_PHY_912_DATA 0x00000000 -#define DDRSS3_PHY_913_DATA 0x00000000 -#define DDRSS3_PHY_914_DATA 0x00000000 -#define DDRSS3_PHY_915_DATA 0x00000000 -#define DDRSS3_PHY_916_DATA 0x00000000 -#define DDRSS3_PHY_917_DATA 0x00000000 -#define DDRSS3_PHY_918_DATA 0x00000000 -#define DDRSS3_PHY_919_DATA 0x00000000 -#define DDRSS3_PHY_920_DATA 0x00000000 -#define DDRSS3_PHY_921_DATA 0x00000000 -#define DDRSS3_PHY_922_DATA 0x00000000 -#define DDRSS3_PHY_923_DATA 0x00000000 -#define DDRSS3_PHY_924_DATA 0x00000000 -#define DDRSS3_PHY_925_DATA 0x00000000 -#define DDRSS3_PHY_926_DATA 0x00000000 -#define DDRSS3_PHY_927_DATA 0x00000000 -#define DDRSS3_PHY_928_DATA 0x00000000 -#define DDRSS3_PHY_929_DATA 0x00000000 -#define DDRSS3_PHY_930_DATA 0x00000000 -#define DDRSS3_PHY_931_DATA 0x00000000 -#define DDRSS3_PHY_932_DATA 0x00000000 -#define DDRSS3_PHY_933_DATA 0x00000000 -#define DDRSS3_PHY_934_DATA 0x00000000 -#define DDRSS3_PHY_935_DATA 0x00000000 -#define DDRSS3_PHY_936_DATA 0x00000000 -#define DDRSS3_PHY_937_DATA 0x00000000 -#define DDRSS3_PHY_938_DATA 0x00000000 -#define DDRSS3_PHY_939_DATA 0x00000000 -#define DDRSS3_PHY_940_DATA 0x00000000 -#define DDRSS3_PHY_941_DATA 0x00000000 -#define DDRSS3_PHY_942_DATA 0x00000000 -#define DDRSS3_PHY_943_DATA 0x00000000 -#define DDRSS3_PHY_944_DATA 0x00000000 -#define DDRSS3_PHY_945_DATA 0x00000000 -#define DDRSS3_PHY_946_DATA 0x00000000 -#define DDRSS3_PHY_947_DATA 0x00000000 -#define DDRSS3_PHY_948_DATA 0x00000000 -#define DDRSS3_PHY_949_DATA 0x00000000 -#define DDRSS3_PHY_950_DATA 0x00000000 -#define DDRSS3_PHY_951_DATA 0x00000000 -#define DDRSS3_PHY_952_DATA 0x00000000 -#define DDRSS3_PHY_953_DATA 0x00000000 -#define DDRSS3_PHY_954_DATA 0x00000000 -#define DDRSS3_PHY_955_DATA 0x00000000 -#define DDRSS3_PHY_956_DATA 0x00000000 -#define DDRSS3_PHY_957_DATA 0x00000000 -#define DDRSS3_PHY_958_DATA 0x00000000 -#define DDRSS3_PHY_959_DATA 0x00000000 -#define DDRSS3_PHY_960_DATA 0x00000000 -#define DDRSS3_PHY_961_DATA 0x00000000 -#define DDRSS3_PHY_962_DATA 0x00000000 -#define DDRSS3_PHY_963_DATA 0x00000000 -#define DDRSS3_PHY_964_DATA 0x00000000 -#define DDRSS3_PHY_965_DATA 0x00000000 -#define DDRSS3_PHY_966_DATA 0x00000000 -#define DDRSS3_PHY_967_DATA 0x00000000 -#define DDRSS3_PHY_968_DATA 0x00000000 -#define DDRSS3_PHY_969_DATA 0x00000000 -#define DDRSS3_PHY_970_DATA 0x00000000 -#define DDRSS3_PHY_971_DATA 0x00000000 -#define DDRSS3_PHY_972_DATA 0x00000000 -#define DDRSS3_PHY_973_DATA 0x00000000 -#define DDRSS3_PHY_974_DATA 0x00000000 -#define DDRSS3_PHY_975_DATA 0x00000000 -#define DDRSS3_PHY_976_DATA 0x00000000 -#define DDRSS3_PHY_977_DATA 0x00000000 -#define DDRSS3_PHY_978_DATA 0x00000000 -#define DDRSS3_PHY_979_DATA 0x00000000 -#define DDRSS3_PHY_980_DATA 0x00000000 -#define DDRSS3_PHY_981_DATA 0x00000000 -#define DDRSS3_PHY_982_DATA 0x00000000 -#define DDRSS3_PHY_983_DATA 0x00000000 -#define DDRSS3_PHY_984_DATA 0x00000000 -#define DDRSS3_PHY_985_DATA 0x00000000 -#define DDRSS3_PHY_986_DATA 0x00000000 -#define DDRSS3_PHY_987_DATA 0x00000000 -#define DDRSS3_PHY_988_DATA 0x00000000 -#define DDRSS3_PHY_989_DATA 0x00000000 -#define DDRSS3_PHY_990_DATA 0x00000000 -#define DDRSS3_PHY_991_DATA 0x00000000 -#define DDRSS3_PHY_992_DATA 0x00000000 -#define DDRSS3_PHY_993_DATA 0x00000000 -#define DDRSS3_PHY_994_DATA 0x00000000 -#define DDRSS3_PHY_995_DATA 0x00000000 -#define DDRSS3_PHY_996_DATA 0x00000000 -#define DDRSS3_PHY_997_DATA 0x00000000 -#define DDRSS3_PHY_998_DATA 0x00000000 -#define DDRSS3_PHY_999_DATA 0x00000000 -#define DDRSS3_PHY_1000_DATA 0x00000000 -#define DDRSS3_PHY_1001_DATA 0x00000000 -#define DDRSS3_PHY_1002_DATA 0x00000000 -#define DDRSS3_PHY_1003_DATA 0x00000000 -#define DDRSS3_PHY_1004_DATA 0x00000000 -#define DDRSS3_PHY_1005_DATA 0x00000000 -#define DDRSS3_PHY_1006_DATA 0x00000000 -#define DDRSS3_PHY_1007_DATA 0x00000000 -#define DDRSS3_PHY_1008_DATA 0x00000000 -#define DDRSS3_PHY_1009_DATA 0x00000000 -#define DDRSS3_PHY_1010_DATA 0x00000000 -#define DDRSS3_PHY_1011_DATA 0x00000000 -#define DDRSS3_PHY_1012_DATA 0x00000000 -#define DDRSS3_PHY_1013_DATA 0x00000000 -#define DDRSS3_PHY_1014_DATA 0x00000000 -#define DDRSS3_PHY_1015_DATA 0x00000000 -#define DDRSS3_PHY_1016_DATA 0x00000000 -#define DDRSS3_PHY_1017_DATA 0x00000000 -#define DDRSS3_PHY_1018_DATA 0x00000000 -#define DDRSS3_PHY_1019_DATA 0x00000000 -#define DDRSS3_PHY_1020_DATA 0x00000000 -#define DDRSS3_PHY_1021_DATA 0x00000000 -#define DDRSS3_PHY_1022_DATA 0x00000000 -#define DDRSS3_PHY_1023_DATA 0x00000000 -#define DDRSS3_PHY_1024_DATA 0x00000000 -#define DDRSS3_PHY_1025_DATA 0x00000000 -#define DDRSS3_PHY_1026_DATA 0x00000000 -#define DDRSS3_PHY_1027_DATA 0x00000000 -#define DDRSS3_PHY_1028_DATA 0x00000000 -#define DDRSS3_PHY_1029_DATA 0x00000100 -#define DDRSS3_PHY_1030_DATA 0x00000200 -#define DDRSS3_PHY_1031_DATA 0x00000000 -#define DDRSS3_PHY_1032_DATA 0x00000000 -#define DDRSS3_PHY_1033_DATA 0x00000000 -#define DDRSS3_PHY_1034_DATA 0x00000000 -#define DDRSS3_PHY_1035_DATA 0x00400000 -#define DDRSS3_PHY_1036_DATA 0x00000080 -#define DDRSS3_PHY_1037_DATA 0x00DCBA98 -#define DDRSS3_PHY_1038_DATA 0x03000000 -#define DDRSS3_PHY_1039_DATA 0x00200000 -#define DDRSS3_PHY_1040_DATA 0x00000000 -#define DDRSS3_PHY_1041_DATA 0x00000000 -#define DDRSS3_PHY_1042_DATA 0x00000000 -#define DDRSS3_PHY_1043_DATA 0x00000000 -#define DDRSS3_PHY_1044_DATA 0x00000000 -#define DDRSS3_PHY_1045_DATA 0x0000002A -#define DDRSS3_PHY_1046_DATA 0x00000015 -#define DDRSS3_PHY_1047_DATA 0x00000015 -#define DDRSS3_PHY_1048_DATA 0x0000002A -#define DDRSS3_PHY_1049_DATA 0x00000033 -#define DDRSS3_PHY_1050_DATA 0x0000000C -#define DDRSS3_PHY_1051_DATA 0x0000000C -#define DDRSS3_PHY_1052_DATA 0x00000033 -#define DDRSS3_PHY_1053_DATA 0x00543210 -#define DDRSS3_PHY_1054_DATA 0x003F0000 -#define DDRSS3_PHY_1055_DATA 0x000F013F -#define DDRSS3_PHY_1056_DATA 0x20202003 -#define DDRSS3_PHY_1057_DATA 0x00202020 -#define DDRSS3_PHY_1058_DATA 0x20008008 -#define DDRSS3_PHY_1059_DATA 0x00000810 -#define DDRSS3_PHY_1060_DATA 0x00000F00 -#define DDRSS3_PHY_1061_DATA 0x00000000 -#define DDRSS3_PHY_1062_DATA 0x00000000 -#define DDRSS3_PHY_1063_DATA 0x00000000 -#define DDRSS3_PHY_1064_DATA 0x000305CC -#define DDRSS3_PHY_1065_DATA 0x00030000 -#define DDRSS3_PHY_1066_DATA 0x00000300 -#define DDRSS3_PHY_1067_DATA 0x00000300 -#define DDRSS3_PHY_1068_DATA 0x00000300 -#define DDRSS3_PHY_1069_DATA 0x00000300 -#define DDRSS3_PHY_1070_DATA 0x00000300 -#define DDRSS3_PHY_1071_DATA 0x42080010 -#define DDRSS3_PHY_1072_DATA 0x0000803E -#define DDRSS3_PHY_1073_DATA 0x00000001 -#define DDRSS3_PHY_1074_DATA 0x01000102 -#define DDRSS3_PHY_1075_DATA 0x00008000 -#define DDRSS3_PHY_1076_DATA 0x00000000 -#define DDRSS3_PHY_1077_DATA 0x00000000 -#define DDRSS3_PHY_1078_DATA 0x00000000 -#define DDRSS3_PHY_1079_DATA 0x00000000 -#define DDRSS3_PHY_1080_DATA 0x00000000 -#define DDRSS3_PHY_1081_DATA 0x00000000 -#define DDRSS3_PHY_1082_DATA 0x00000000 -#define DDRSS3_PHY_1083_DATA 0x00000000 -#define DDRSS3_PHY_1084_DATA 0x00000000 -#define DDRSS3_PHY_1085_DATA 0x00000000 -#define DDRSS3_PHY_1086_DATA 0x00000000 -#define DDRSS3_PHY_1087_DATA 0x00000000 -#define DDRSS3_PHY_1088_DATA 0x00000000 -#define DDRSS3_PHY_1089_DATA 0x00000000 -#define DDRSS3_PHY_1090_DATA 0x00000000 -#define DDRSS3_PHY_1091_DATA 0x00000000 -#define DDRSS3_PHY_1092_DATA 0x00000000 -#define DDRSS3_PHY_1093_DATA 0x00000000 -#define DDRSS3_PHY_1094_DATA 0x00000000 -#define DDRSS3_PHY_1095_DATA 0x00000000 -#define DDRSS3_PHY_1096_DATA 0x00000000 -#define DDRSS3_PHY_1097_DATA 0x00000000 -#define DDRSS3_PHY_1098_DATA 0x00000000 -#define DDRSS3_PHY_1099_DATA 0x00000000 -#define DDRSS3_PHY_1100_DATA 0x00000000 -#define DDRSS3_PHY_1101_DATA 0x00000000 -#define DDRSS3_PHY_1102_DATA 0x00000000 -#define DDRSS3_PHY_1103_DATA 0x00000000 -#define DDRSS3_PHY_1104_DATA 0x00000000 -#define DDRSS3_PHY_1105_DATA 0x00000000 -#define DDRSS3_PHY_1106_DATA 0x00000000 -#define DDRSS3_PHY_1107_DATA 0x00000000 -#define DDRSS3_PHY_1108_DATA 0x00000000 -#define DDRSS3_PHY_1109_DATA 0x00000000 -#define DDRSS3_PHY_1110_DATA 0x00000000 -#define DDRSS3_PHY_1111_DATA 0x00000000 -#define DDRSS3_PHY_1112_DATA 0x00000000 -#define DDRSS3_PHY_1113_DATA 0x00000000 -#define DDRSS3_PHY_1114_DATA 0x00000000 -#define DDRSS3_PHY_1115_DATA 0x00000000 -#define DDRSS3_PHY_1116_DATA 0x00000000 -#define DDRSS3_PHY_1117_DATA 0x00000000 -#define DDRSS3_PHY_1118_DATA 0x00000000 -#define DDRSS3_PHY_1119_DATA 0x00000000 -#define DDRSS3_PHY_1120_DATA 0x00000000 -#define DDRSS3_PHY_1121_DATA 0x00000000 -#define DDRSS3_PHY_1122_DATA 0x00000000 -#define DDRSS3_PHY_1123_DATA 0x00000000 -#define DDRSS3_PHY_1124_DATA 0x00000000 -#define DDRSS3_PHY_1125_DATA 0x00000000 -#define DDRSS3_PHY_1126_DATA 0x00000000 -#define DDRSS3_PHY_1127_DATA 0x00000000 -#define DDRSS3_PHY_1128_DATA 0x00000000 -#define DDRSS3_PHY_1129_DATA 0x00000000 -#define DDRSS3_PHY_1130_DATA 0x00000000 -#define DDRSS3_PHY_1131_DATA 0x00000000 -#define DDRSS3_PHY_1132_DATA 0x00000000 -#define DDRSS3_PHY_1133_DATA 0x00000000 -#define DDRSS3_PHY_1134_DATA 0x00000000 -#define DDRSS3_PHY_1135_DATA 0x00000000 -#define DDRSS3_PHY_1136_DATA 0x00000000 -#define DDRSS3_PHY_1137_DATA 0x00000000 -#define DDRSS3_PHY_1138_DATA 0x00000000 -#define DDRSS3_PHY_1139_DATA 0x00000000 -#define DDRSS3_PHY_1140_DATA 0x00000000 -#define DDRSS3_PHY_1141_DATA 0x00000000 -#define DDRSS3_PHY_1142_DATA 0x00000000 -#define DDRSS3_PHY_1143_DATA 0x00000000 -#define DDRSS3_PHY_1144_DATA 0x00000000 -#define DDRSS3_PHY_1145_DATA 0x00000000 -#define DDRSS3_PHY_1146_DATA 0x00000000 -#define DDRSS3_PHY_1147_DATA 0x00000000 -#define DDRSS3_PHY_1148_DATA 0x00000000 -#define DDRSS3_PHY_1149_DATA 0x00000000 -#define DDRSS3_PHY_1150_DATA 0x00000000 -#define DDRSS3_PHY_1151_DATA 0x00000000 -#define DDRSS3_PHY_1152_DATA 0x00000000 -#define DDRSS3_PHY_1153_DATA 0x00000000 -#define DDRSS3_PHY_1154_DATA 0x00000000 -#define DDRSS3_PHY_1155_DATA 0x00000000 -#define DDRSS3_PHY_1156_DATA 0x00000000 -#define DDRSS3_PHY_1157_DATA 0x00000000 -#define DDRSS3_PHY_1158_DATA 0x00000000 -#define DDRSS3_PHY_1159_DATA 0x00000000 -#define DDRSS3_PHY_1160_DATA 0x00000000 -#define DDRSS3_PHY_1161_DATA 0x00000000 -#define DDRSS3_PHY_1162_DATA 0x00000000 -#define DDRSS3_PHY_1163_DATA 0x00000000 -#define DDRSS3_PHY_1164_DATA 0x00000000 -#define DDRSS3_PHY_1165_DATA 0x00000000 -#define DDRSS3_PHY_1166_DATA 0x00000000 -#define DDRSS3_PHY_1167_DATA 0x00000000 -#define DDRSS3_PHY_1168_DATA 0x00000000 -#define DDRSS3_PHY_1169_DATA 0x00000000 -#define DDRSS3_PHY_1170_DATA 0x00000000 -#define DDRSS3_PHY_1171_DATA 0x00000000 -#define DDRSS3_PHY_1172_DATA 0x00000000 -#define DDRSS3_PHY_1173_DATA 0x00000000 -#define DDRSS3_PHY_1174_DATA 0x00000000 -#define DDRSS3_PHY_1175_DATA 0x00000000 -#define DDRSS3_PHY_1176_DATA 0x00000000 -#define DDRSS3_PHY_1177_DATA 0x00000000 -#define DDRSS3_PHY_1178_DATA 0x00000000 -#define DDRSS3_PHY_1179_DATA 0x00000000 -#define DDRSS3_PHY_1180_DATA 0x00000000 -#define DDRSS3_PHY_1181_DATA 0x00000000 -#define DDRSS3_PHY_1182_DATA 0x00000000 -#define DDRSS3_PHY_1183_DATA 0x00000000 -#define DDRSS3_PHY_1184_DATA 0x00000000 -#define DDRSS3_PHY_1185_DATA 0x00000000 -#define DDRSS3_PHY_1186_DATA 0x00000000 -#define DDRSS3_PHY_1187_DATA 0x00000000 -#define DDRSS3_PHY_1188_DATA 0x00000000 -#define DDRSS3_PHY_1189_DATA 0x00000000 -#define DDRSS3_PHY_1190_DATA 0x00000000 -#define DDRSS3_PHY_1191_DATA 0x00000000 -#define DDRSS3_PHY_1192_DATA 0x00000000 -#define DDRSS3_PHY_1193_DATA 0x00000000 -#define DDRSS3_PHY_1194_DATA 0x00000000 -#define DDRSS3_PHY_1195_DATA 0x00000000 -#define DDRSS3_PHY_1196_DATA 0x00000000 -#define DDRSS3_PHY_1197_DATA 0x00000000 -#define DDRSS3_PHY_1198_DATA 0x00000000 -#define DDRSS3_PHY_1199_DATA 0x00000000 -#define DDRSS3_PHY_1200_DATA 0x00000000 -#define DDRSS3_PHY_1201_DATA 0x00000000 -#define DDRSS3_PHY_1202_DATA 0x00000000 -#define DDRSS3_PHY_1203_DATA 0x00000000 -#define DDRSS3_PHY_1204_DATA 0x00000000 -#define DDRSS3_PHY_1205_DATA 0x00000000 -#define DDRSS3_PHY_1206_DATA 0x00000000 -#define DDRSS3_PHY_1207_DATA 0x00000000 -#define DDRSS3_PHY_1208_DATA 0x00000000 -#define DDRSS3_PHY_1209_DATA 0x00000000 -#define DDRSS3_PHY_1210_DATA 0x00000000 -#define DDRSS3_PHY_1211_DATA 0x00000000 -#define DDRSS3_PHY_1212_DATA 0x00000000 -#define DDRSS3_PHY_1213_DATA 0x00000000 -#define DDRSS3_PHY_1214_DATA 0x00000000 -#define DDRSS3_PHY_1215_DATA 0x00000000 -#define DDRSS3_PHY_1216_DATA 0x00000000 -#define DDRSS3_PHY_1217_DATA 0x00000000 -#define DDRSS3_PHY_1218_DATA 0x00000000 -#define DDRSS3_PHY_1219_DATA 0x00000000 -#define DDRSS3_PHY_1220_DATA 0x00000000 -#define DDRSS3_PHY_1221_DATA 0x00000000 -#define DDRSS3_PHY_1222_DATA 0x00000000 -#define DDRSS3_PHY_1223_DATA 0x00000000 -#define DDRSS3_PHY_1224_DATA 0x00000000 -#define DDRSS3_PHY_1225_DATA 0x00000000 -#define DDRSS3_PHY_1226_DATA 0x00000000 -#define DDRSS3_PHY_1227_DATA 0x00000000 -#define DDRSS3_PHY_1228_DATA 0x00000000 -#define DDRSS3_PHY_1229_DATA 0x00000000 -#define DDRSS3_PHY_1230_DATA 0x00000000 -#define DDRSS3_PHY_1231_DATA 0x00000000 -#define DDRSS3_PHY_1232_DATA 0x00000000 -#define DDRSS3_PHY_1233_DATA 0x00000000 -#define DDRSS3_PHY_1234_DATA 0x00000000 -#define DDRSS3_PHY_1235_DATA 0x00000000 -#define DDRSS3_PHY_1236_DATA 0x00000000 -#define DDRSS3_PHY_1237_DATA 0x00000000 -#define DDRSS3_PHY_1238_DATA 0x00000000 -#define DDRSS3_PHY_1239_DATA 0x00000000 -#define DDRSS3_PHY_1240_DATA 0x00000000 -#define DDRSS3_PHY_1241_DATA 0x00000000 -#define DDRSS3_PHY_1242_DATA 0x00000000 -#define DDRSS3_PHY_1243_DATA 0x00000000 -#define DDRSS3_PHY_1244_DATA 0x00000000 -#define DDRSS3_PHY_1245_DATA 0x00000000 -#define DDRSS3_PHY_1246_DATA 0x00000000 -#define DDRSS3_PHY_1247_DATA 0x00000000 -#define DDRSS3_PHY_1248_DATA 0x00000000 -#define DDRSS3_PHY_1249_DATA 0x00000000 -#define DDRSS3_PHY_1250_DATA 0x00000000 -#define DDRSS3_PHY_1251_DATA 0x00000000 -#define DDRSS3_PHY_1252_DATA 0x00000000 -#define DDRSS3_PHY_1253_DATA 0x00000000 -#define DDRSS3_PHY_1254_DATA 0x00000000 -#define DDRSS3_PHY_1255_DATA 0x00000000 -#define DDRSS3_PHY_1256_DATA 0x00000000 -#define DDRSS3_PHY_1257_DATA 0x00000000 -#define DDRSS3_PHY_1258_DATA 0x00000000 -#define DDRSS3_PHY_1259_DATA 0x00000000 -#define DDRSS3_PHY_1260_DATA 0x00000000 -#define DDRSS3_PHY_1261_DATA 0x00000000 -#define DDRSS3_PHY_1262_DATA 0x00000000 -#define DDRSS3_PHY_1263_DATA 0x00000000 -#define DDRSS3_PHY_1264_DATA 0x00000000 -#define DDRSS3_PHY_1265_DATA 0x00000000 -#define DDRSS3_PHY_1266_DATA 0x00000000 -#define DDRSS3_PHY_1267_DATA 0x00000000 -#define DDRSS3_PHY_1268_DATA 0x00000000 -#define DDRSS3_PHY_1269_DATA 0x00000000 -#define DDRSS3_PHY_1270_DATA 0x00000000 -#define DDRSS3_PHY_1271_DATA 0x00000000 -#define DDRSS3_PHY_1272_DATA 0x00000000 -#define DDRSS3_PHY_1273_DATA 0x00000000 -#define DDRSS3_PHY_1274_DATA 0x00000000 -#define DDRSS3_PHY_1275_DATA 0x00000000 -#define DDRSS3_PHY_1276_DATA 0x00000000 -#define DDRSS3_PHY_1277_DATA 0x00000000 -#define DDRSS3_PHY_1278_DATA 0x00000000 -#define DDRSS3_PHY_1279_DATA 0x00000000 -#define DDRSS3_PHY_1280_DATA 0x00000000 -#define DDRSS3_PHY_1281_DATA 0x00010100 -#define DDRSS3_PHY_1282_DATA 0x00000000 -#define DDRSS3_PHY_1283_DATA 0x00000000 -#define DDRSS3_PHY_1284_DATA 0x00050000 -#define DDRSS3_PHY_1285_DATA 0x04000000 -#define DDRSS3_PHY_1286_DATA 0x00000055 -#define DDRSS3_PHY_1287_DATA 0x00000000 -#define DDRSS3_PHY_1288_DATA 0x00000000 -#define DDRSS3_PHY_1289_DATA 0x00000000 -#define DDRSS3_PHY_1290_DATA 0x00000000 -#define DDRSS3_PHY_1291_DATA 0x00002001 -#define DDRSS3_PHY_1292_DATA 0x0000400F -#define DDRSS3_PHY_1293_DATA 0x50020028 -#define DDRSS3_PHY_1294_DATA 0x01010000 -#define DDRSS3_PHY_1295_DATA 0x80080001 -#define DDRSS3_PHY_1296_DATA 0x10200000 -#define DDRSS3_PHY_1297_DATA 0x00000008 -#define DDRSS3_PHY_1298_DATA 0x00000000 -#define DDRSS3_PHY_1299_DATA 0x01090E00 -#define DDRSS3_PHY_1300_DATA 0x00040101 -#define DDRSS3_PHY_1301_DATA 0x0000010F -#define DDRSS3_PHY_1302_DATA 0x00000000 -#define DDRSS3_PHY_1303_DATA 0x0000FFFF -#define DDRSS3_PHY_1304_DATA 0x00000000 -#define DDRSS3_PHY_1305_DATA 0x01010000 -#define DDRSS3_PHY_1306_DATA 0x01080402 -#define DDRSS3_PHY_1307_DATA 0x01200F02 -#define DDRSS3_PHY_1308_DATA 0x00194280 -#define DDRSS3_PHY_1309_DATA 0x00000004 -#define DDRSS3_PHY_1310_DATA 0x00042000 -#define DDRSS3_PHY_1311_DATA 0x00000000 -#define DDRSS3_PHY_1312_DATA 0x00000000 -#define DDRSS3_PHY_1313_DATA 0x00000000 -#define DDRSS3_PHY_1314_DATA 0x00000000 -#define DDRSS3_PHY_1315_DATA 0x00000000 -#define DDRSS3_PHY_1316_DATA 0x00000000 -#define DDRSS3_PHY_1317_DATA 0x01000000 -#define DDRSS3_PHY_1318_DATA 0x00000705 -#define DDRSS3_PHY_1319_DATA 0x00000054 -#define DDRSS3_PHY_1320_DATA 0x00030820 -#define DDRSS3_PHY_1321_DATA 0x00010820 -#define DDRSS3_PHY_1322_DATA 0x00010820 -#define DDRSS3_PHY_1323_DATA 0x00010820 -#define DDRSS3_PHY_1324_DATA 0x00010820 -#define DDRSS3_PHY_1325_DATA 0x00010820 -#define DDRSS3_PHY_1326_DATA 0x00010820 -#define DDRSS3_PHY_1327_DATA 0x00010820 -#define DDRSS3_PHY_1328_DATA 0x00010820 -#define DDRSS3_PHY_1329_DATA 0x00000000 -#define DDRSS3_PHY_1330_DATA 0x00000074 -#define DDRSS3_PHY_1331_DATA 0x00000400 -#define DDRSS3_PHY_1332_DATA 0x00000108 -#define DDRSS3_PHY_1333_DATA 0x00000000 -#define DDRSS3_PHY_1334_DATA 0x00000000 -#define DDRSS3_PHY_1335_DATA 0x00000000 -#define DDRSS3_PHY_1336_DATA 0x00000000 -#define DDRSS3_PHY_1337_DATA 0x00000000 -#define DDRSS3_PHY_1338_DATA 0x03000000 -#define DDRSS3_PHY_1339_DATA 0x00000000 -#define DDRSS3_PHY_1340_DATA 0x00000000 -#define DDRSS3_PHY_1341_DATA 0x00000000 -#define DDRSS3_PHY_1342_DATA 0x04102006 -#define DDRSS3_PHY_1343_DATA 0x00041020 -#define DDRSS3_PHY_1344_DATA 0x01C98C98 -#define DDRSS3_PHY_1345_DATA 0x3F400000 -#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F -#define DDRSS3_PHY_1347_DATA 0x0000001F -#define DDRSS3_PHY_1348_DATA 0x00000000 -#define DDRSS3_PHY_1349_DATA 0x00000000 -#define DDRSS3_PHY_1350_DATA 0x00000000 -#define DDRSS3_PHY_1351_DATA 0x00010000 -#define DDRSS3_PHY_1352_DATA 0x00000000 -#define DDRSS3_PHY_1353_DATA 0x00000000 -#define DDRSS3_PHY_1354_DATA 0x00000000 -#define DDRSS3_PHY_1355_DATA 0x00000000 -#define DDRSS3_PHY_1356_DATA 0x76543210 -#define DDRSS3_PHY_1357_DATA 0x00010198 -#define DDRSS3_PHY_1358_DATA 0x00000000 -#define DDRSS3_PHY_1359_DATA 0x00000000 -#define DDRSS3_PHY_1360_DATA 0x00000000 -#define DDRSS3_PHY_1361_DATA 0x00040700 -#define DDRSS3_PHY_1362_DATA 0x00000000 -#define DDRSS3_PHY_1363_DATA 0x00000000 -#define DDRSS3_PHY_1364_DATA 0x00000000 -#define DDRSS3_PHY_1365_DATA 0x00000000 -#define DDRSS3_PHY_1366_DATA 0x00000000 -#define DDRSS3_PHY_1367_DATA 0x00000002 -#define DDRSS3_PHY_1368_DATA 0x00000000 -#define DDRSS3_PHY_1369_DATA 0x00000000 -#define DDRSS3_PHY_1370_DATA 0x00000000 -#define DDRSS3_PHY_1371_DATA 0x00000000 -#define DDRSS3_PHY_1372_DATA 0x00000000 -#define DDRSS3_PHY_1373_DATA 0x00000000 -#define DDRSS3_PHY_1374_DATA 0x00080000 -#define DDRSS3_PHY_1375_DATA 0x000007FF -#define DDRSS3_PHY_1376_DATA 0x00000000 -#define DDRSS3_PHY_1377_DATA 0x00000000 -#define DDRSS3_PHY_1378_DATA 0x00000000 -#define DDRSS3_PHY_1379_DATA 0x00000000 -#define DDRSS3_PHY_1380_DATA 0x00000000 -#define DDRSS3_PHY_1381_DATA 0x00000000 -#define DDRSS3_PHY_1382_DATA 0x000FFFFF -#define DDRSS3_PHY_1383_DATA 0x000FFFFF -#define DDRSS3_PHY_1384_DATA 0x0000FFFF -#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0 -#define DDRSS3_PHY_1386_DATA 0x030FFFFF -#define DDRSS3_PHY_1387_DATA 0x01FFFFFF -#define DDRSS3_PHY_1388_DATA 0x0000FFFF -#define DDRSS3_PHY_1389_DATA 0x00000000 -#define DDRSS3_PHY_1390_DATA 0x00000000 -#define DDRSS3_PHY_1391_DATA 0x00000000 -#define DDRSS3_PHY_1392_DATA 0x00000000 -#define DDRSS3_PHY_1393_DATA 0x0001F7C0 -#define DDRSS3_PHY_1394_DATA 0x00000003 -#define DDRSS3_PHY_1395_DATA 0x00000000 -#define DDRSS3_PHY_1396_DATA 0x00001142 -#define DDRSS3_PHY_1397_DATA 0x010207AB -#define DDRSS3_PHY_1398_DATA 0x01000080 -#define DDRSS3_PHY_1399_DATA 0x03900390 -#define DDRSS3_PHY_1400_DATA 0x03900390 -#define DDRSS3_PHY_1401_DATA 0x00000390 -#define DDRSS3_PHY_1402_DATA 0x00000390 -#define DDRSS3_PHY_1403_DATA 0x00000390 -#define DDRSS3_PHY_1404_DATA 0x00000390 -#define DDRSS3_PHY_1405_DATA 0x00000005 -#define DDRSS3_PHY_1406_DATA 0x01813FCC -#define DDRSS3_PHY_1407_DATA 0x000000CC -#define DDRSS3_PHY_1408_DATA 0x0C000DFF -#define DDRSS3_PHY_1409_DATA 0x30000DFF -#define DDRSS3_PHY_1410_DATA 0x3F0DFF11 -#define DDRSS3_PHY_1411_DATA 0x000100F0 -#define DDRSS3_PHY_1412_DATA 0x780DFFCC -#define DDRSS3_PHY_1413_DATA 0x00007E31 -#define DDRSS3_PHY_1414_DATA 0x000CBF11 -#define DDRSS3_PHY_1415_DATA 0x01990010 -#define DDRSS3_PHY_1416_DATA 0x000CBF11 -#define DDRSS3_PHY_1417_DATA 0x01990010 -#define DDRSS3_PHY_1418_DATA 0x3F0DFF11 -#define DDRSS3_PHY_1419_DATA 0x00EF00F0 -#define DDRSS3_PHY_1420_DATA 0x3F0DFF11 -#define DDRSS3_PHY_1421_DATA 0x01FF00F0 -#define DDRSS3_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi index 0e16d2f201d..521464e2264 100644 --- a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,29 @@ -// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0 - * This file was generated on 04/12/2023 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:55:08 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 2 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 3 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS2_PLL_FHS_CNT 5 +#define DDRSS3_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -16,6 +34,17 @@ #define MULTI_DDR_CFG_HYBRID_SELECT 24 #define MULTI_DDR_CFG_EMIFS_ACTIVE 15 +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay +#define DDR2_CTL_NODE_STAT okay +#define DDR3_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000007 +#define DDR_REG1_SIZE_LSB 0x80000000 + + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -36,7 +65,7 @@ #define DDRSS0_CTL_17_DATA 0x00000005 #define DDRSS0_CTL_18_DATA 0x000010A9 #define DDRSS0_CTL_19_DATA 0x01010000 -#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_20_DATA 0x01011001 #define DDRSS0_CTL_21_DATA 0x02010000 #define DDRSS0_CTL_22_DATA 0x00020100 #define DDRSS0_CTL_23_DATA 0x0000000B @@ -51,7 +80,7 @@ #define DDRSS0_CTL_32_DATA 0x00000000 #define DDRSS0_CTL_33_DATA 0x00000000 #define DDRSS0_CTL_34_DATA 0x040C0000 -#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_35_DATA 0x12501250 #define DDRSS0_CTL_36_DATA 0x00050804 #define DDRSS0_CTL_37_DATA 0x09040008 #define DDRSS0_CTL_38_DATA 0x15000204 @@ -66,27 +95,27 @@ #define DDRSS0_CTL_47_DATA 0x1E161110 #define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 -#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_50_DATA 0x2C060500 #define DDRSS0_CTL_51_DATA 0x08292C29 #define DDRSS0_CTL_52_DATA 0x14000E0A #define DDRSS0_CTL_53_DATA 0x04010A0A #define DDRSS0_CTL_54_DATA 0x01010004 -#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_55_DATA 0x0454540A #define DDRSS0_CTL_56_DATA 0x04313104 #define DDRSS0_CTL_57_DATA 0x00003131 #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x00000063 +#define DDRSS0_CTL_61_DATA 0x00000068 #define DDRSS0_CTL_62_DATA 0x0000032B #define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B #define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 -#define DDRSS0_CTL_68_DATA 0x00CB0012 -#define DDRSS0_CTL_69_DATA 0x00CB0408 -#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 #define DDRSS0_CTL_71_DATA 0x00120103 #define DDRSS0_CTL_72_DATA 0x00100005 #define DDRSS0_CTL_73_DATA 0x2F080010 @@ -192,22 +221,22 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 #define DDRSS0_CTL_178_DATA 0x35000000 #define DDRSS0_CTL_179_DATA 0x27270035 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 #define DDRSS0_CTL_185_DATA 0x00000000 #define DDRSS0_CTL_186_DATA 0x00353500 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 #define DDRSS0_CTL_190_DATA 0x00000020 -#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_191_DATA 0x01000000 #define DDRSS0_CTL_192_DATA 0x00000001 #define DDRSS0_CTL_193_DATA 0x00000000 #define DDRSS0_CTL_194_DATA 0x01000000 @@ -307,14 +336,14 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00010101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 #define DDRSS0_CTL_295_DATA 0x00000000 #define DDRSS0_CTL_296_DATA 0x00000000 -#define DDRSS0_CTL_297_DATA 0x00000000 -#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF #define DDRSS0_CTL_299_DATA 0x00000000 #define DDRSS0_CTL_300_DATA 0x00000000 #define DDRSS0_CTL_301_DATA 0x00000000 @@ -335,7 +364,7 @@ #define DDRSS0_CTL_316_DATA 0x01010001 #define DDRSS0_CTL_317_DATA 0x00010101 #define DDRSS0_CTL_318_DATA 0x050A0A03 -#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_319_DATA 0x10082323 #define DDRSS0_CTL_320_DATA 0x00090310 #define DDRSS0_CTL_321_DATA 0x0B0C030F #define DDRSS0_CTL_322_DATA 0x0B0C0306 @@ -410,7 +439,7 @@ #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x00000252 +#define DDRSS0_CTL_394_DATA 0x00000270 #define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 #define DDRSS0_CTL_397_DATA 0x0000206A @@ -420,7 +449,7 @@ #define DDRSS0_CTL_401_DATA 0x00000200 #define DDRSS0_CTL_402_DATA 0x0000613E #define DDRSS0_CTL_403_DATA 0x00014424 -#define DDRSS0_CTL_404_DATA 0x00000E15 +#define DDRSS0_CTL_404_DATA 0x00000E19 #define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 @@ -428,7 +457,7 @@ #define DDRSS0_CTL_409_DATA 0x00000200 #define DDRSS0_CTL_410_DATA 0x0000613E #define DDRSS0_CTL_411_DATA 0x00014424 -#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_412_DATA 0x02020E19 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 #define DDRSS0_CTL_415_DATA 0x00000000 @@ -445,7 +474,7 @@ #define DDRSS0_CTL_426_DATA 0x00000000 #define DDRSS0_CTL_427_DATA 0x02000000 #define DDRSS0_CTL_428_DATA 0x01000404 -#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_429_DATA 0x0B220B22 #define DDRSS0_CTL_430_DATA 0x00000105 #define DDRSS0_CTL_431_DATA 0x00010101 #define DDRSS0_CTL_432_DATA 0x00010101 @@ -488,8 +517,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -537,18 +566,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 #define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_67_DATA 0x0002020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -637,37 +666,37 @@ #define DDRSS0_PI_158_DATA 0x00000000 #define DDRSS0_PI_159_DATA 0x00000401 #define DDRSS0_PI_160_DATA 0x00000000 -#define DDRSS0_PI_161_DATA 0x00010000 -#define DDRSS0_PI_162_DATA 0x00000000 -#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 #define DDRSS0_PI_164_DATA 0x00000034 -#define DDRSS0_PI_165_DATA 0x00000064 -#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 #define DDRSS0_PI_167_DATA 0x02000200 -#define DDRSS0_PI_168_DATA 0x48120C04 -#define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x00000063 +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 #define DDRSS0_PI_171_DATA 0x0000032B #define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B #define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 -#define DDRSS0_PI_185_DATA 0x15040000 -#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 #define DDRSS0_PI_187_DATA 0x00040402 #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -675,8 +704,8 @@ #define DDRSS0_PI_196_DATA 0x02170100 #define DDRSS0_PI_197_DATA 0x01000217 #define DDRSS0_PI_198_DATA 0x02170217 -#define DDRSS0_PI_199_DATA 0x32103200 -#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B #define DDRSS0_PI_201_DATA 0x0A070601 #define DDRSS0_PI_202_DATA 0x1F130A0D #define DDRSS0_PI_203_DATA 0x1F130A14 @@ -688,13 +717,13 @@ #define DDRSS0_PI_209_DATA 0x00240216 #define DDRSS0_PI_210_DATA 0x00110216 #define DDRSS0_PI_211_DATA 0x32000056 -#define DDRSS0_PI_212_DATA 0x00000301 -#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 -#define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 -#define DDRSS0_PI_218_DATA 0x04010504 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 #define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A @@ -751,29 +780,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00F30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x35333FF4 +#define DDRSS0_PI_277_DATA 0x35F33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x35333FF4 +#define DDRSS0_PI_279_DATA 0x35F33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00F30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x35333FF4 +#define DDRSS0_PI_283_DATA 0x35F33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x35333FF4 +#define DDRSS0_PI_285_DATA 0x35F33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00F30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x35333FF4 +#define DDRSS0_PI_289_DATA 0x35F33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x35333FF4 +#define DDRSS0_PI_291_DATA 0x35F33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00F30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x35333FF4 +#define DDRSS0_PI_295_DATA 0x35F33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x35333FF4 +#define DDRSS0_PI_297_DATA 0x35F33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -789,7 +818,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -808,7 +837,7 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_31_DATA 0x00000F08 #define DDRSS0_PHY_32_DATA 0x10400000 #define DDRSS0_PHY_33_DATA 0x0C002006 #define DDRSS0_PHY_34_DATA 0x00000000 @@ -877,9 +906,9 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 -#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 #define DDRSS0_PHY_103_DATA 0x10001000 #define DDRSS0_PHY_104_DATA 0x0C083E42 #define DDRSS0_PHY_105_DATA 0x0F0C3701 @@ -1045,7 +1074,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1064,7 +1093,7 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_287_DATA 0x00000F08 #define DDRSS0_PHY_288_DATA 0x10400000 #define DDRSS0_PHY_289_DATA 0x0C002006 #define DDRSS0_PHY_290_DATA 0x00000000 @@ -1133,9 +1162,9 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 -#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 #define DDRSS0_PHY_359_DATA 0x10001000 #define DDRSS0_PHY_360_DATA 0x0C083E42 #define DDRSS0_PHY_361_DATA 0x0F0C3701 @@ -1301,7 +1330,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1320,7 +1349,7 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_543_DATA 0x00000F08 #define DDRSS0_PHY_544_DATA 0x10400000 #define DDRSS0_PHY_545_DATA 0x0C002006 #define DDRSS0_PHY_546_DATA 0x00000000 @@ -1389,9 +1418,9 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 -#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 #define DDRSS0_PHY_615_DATA 0x10001000 #define DDRSS0_PHY_616_DATA 0x0C083E42 #define DDRSS0_PHY_617_DATA 0x0F0C3701 @@ -1557,7 +1586,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1576,7 +1605,7 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_799_DATA 0x00000F08 #define DDRSS0_PHY_800_DATA 0x10400000 #define DDRSS0_PHY_801_DATA 0x0C002006 #define DDRSS0_PHY_802_DATA 0x00000000 @@ -1645,9 +1674,9 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 -#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 #define DDRSS0_PHY_871_DATA 0x10001000 #define DDRSS0_PHY_872_DATA 0x0C083E42 #define DDRSS0_PHY_873_DATA 0x0F0C3701 @@ -1832,7 +1861,7 @@ #define DDRSS0_PHY_1052_DATA 0x00000033 #define DDRSS0_PHY_1053_DATA 0x00543210 #define DDRSS0_PHY_1054_DATA 0x003F0000 -#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1055_DATA 0x000F3F3F #define DDRSS0_PHY_1056_DATA 0x20202003 #define DDRSS0_PHY_1057_DATA 0x00202020 #define DDRSS0_PHY_1058_DATA 0x20008008 @@ -2080,7 +2109,7 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 @@ -2174,7 +2203,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2221,7 +2250,7 @@ #define DDRSS1_CTL_17_DATA 0x00000005 #define DDRSS1_CTL_18_DATA 0x000010A9 #define DDRSS1_CTL_19_DATA 0x01010000 -#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_20_DATA 0x01011001 #define DDRSS1_CTL_21_DATA 0x02010000 #define DDRSS1_CTL_22_DATA 0x00020100 #define DDRSS1_CTL_23_DATA 0x0000000B @@ -2236,7 +2265,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2251,27 +2280,27 @@ #define DDRSS1_CTL_47_DATA 0x1E161110 #define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 -#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_50_DATA 0x2C060500 #define DDRSS1_CTL_51_DATA 0x08292C29 #define DDRSS1_CTL_52_DATA 0x14000E0A #define DDRSS1_CTL_53_DATA 0x04010A0A #define DDRSS1_CTL_54_DATA 0x01010004 -#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_55_DATA 0x0454540A #define DDRSS1_CTL_56_DATA 0x04313104 #define DDRSS1_CTL_57_DATA 0x00003131 #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x00000063 +#define DDRSS1_CTL_61_DATA 0x00000068 #define DDRSS1_CTL_62_DATA 0x0000032B #define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B #define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 -#define DDRSS1_CTL_68_DATA 0x00CB0012 -#define DDRSS1_CTL_69_DATA 0x00CB0408 -#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 #define DDRSS1_CTL_71_DATA 0x00120103 #define DDRSS1_CTL_72_DATA 0x00100005 #define DDRSS1_CTL_73_DATA 0x2F080010 @@ -2377,22 +2406,22 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 #define DDRSS1_CTL_178_DATA 0x35000000 #define DDRSS1_CTL_179_DATA 0x27270035 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 #define DDRSS1_CTL_186_DATA 0x00353500 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 #define DDRSS1_CTL_190_DATA 0x00000020 -#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_191_DATA 0x01000000 #define DDRSS1_CTL_192_DATA 0x00000001 #define DDRSS1_CTL_193_DATA 0x00000000 #define DDRSS1_CTL_194_DATA 0x01000000 @@ -2492,14 +2521,14 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 #define DDRSS1_CTL_295_DATA 0x00000000 #define DDRSS1_CTL_296_DATA 0x00000000 -#define DDRSS1_CTL_297_DATA 0x00000000 -#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF #define DDRSS1_CTL_299_DATA 0x00000000 #define DDRSS1_CTL_300_DATA 0x00000000 #define DDRSS1_CTL_301_DATA 0x00000000 @@ -2520,7 +2549,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2595,7 +2624,7 @@ #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x00000252 +#define DDRSS1_CTL_394_DATA 0x00000270 #define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 #define DDRSS1_CTL_397_DATA 0x0000206A @@ -2605,7 +2634,7 @@ #define DDRSS1_CTL_401_DATA 0x00000200 #define DDRSS1_CTL_402_DATA 0x0000613E #define DDRSS1_CTL_403_DATA 0x00014424 -#define DDRSS1_CTL_404_DATA 0x00000E15 +#define DDRSS1_CTL_404_DATA 0x00000E19 #define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 @@ -2613,7 +2642,7 @@ #define DDRSS1_CTL_409_DATA 0x00000200 #define DDRSS1_CTL_410_DATA 0x0000613E #define DDRSS1_CTL_411_DATA 0x00014424 -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2630,7 +2659,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2673,8 +2702,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2722,18 +2751,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2822,37 +2851,37 @@ #define DDRSS1_PI_158_DATA 0x00000000 #define DDRSS1_PI_159_DATA 0x00000401 #define DDRSS1_PI_160_DATA 0x00000000 -#define DDRSS1_PI_161_DATA 0x00010000 -#define DDRSS1_PI_162_DATA 0x00000000 -#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x00000063 +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 #define DDRSS1_PI_171_DATA 0x0000032B #define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B #define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2860,8 +2889,8 @@ #define DDRSS1_PI_196_DATA 0x02170100 #define DDRSS1_PI_197_DATA 0x01000217 #define DDRSS1_PI_198_DATA 0x02170217 -#define DDRSS1_PI_199_DATA 0x32103200 -#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B #define DDRSS1_PI_201_DATA 0x0A070601 #define DDRSS1_PI_202_DATA 0x1F130A0D #define DDRSS1_PI_203_DATA 0x1F130A14 @@ -2873,13 +2902,13 @@ #define DDRSS1_PI_209_DATA 0x00240216 #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 -#define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 -#define DDRSS1_PI_218_DATA 0x04010504 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 #define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A @@ -2936,29 +2965,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x35333FF4 +#define DDRSS1_PI_277_DATA 0x35F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x35333FF4 +#define DDRSS1_PI_279_DATA 0x35F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x35333FF4 +#define DDRSS1_PI_283_DATA 0x35F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x35333FF4 +#define DDRSS1_PI_285_DATA 0x35F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x35333FF4 +#define DDRSS1_PI_289_DATA 0x35F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x35333FF4 +#define DDRSS1_PI_291_DATA 0x35F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x35333FF4 +#define DDRSS1_PI_295_DATA 0x35F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x35333FF4 +#define DDRSS1_PI_297_DATA 0x35F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2974,7 +3003,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2993,7 +3022,7 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_31_DATA 0x00000F08 #define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 @@ -3062,9 +3091,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3230,7 +3259,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3249,7 +3278,7 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_287_DATA 0x00000F08 #define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 @@ -3318,9 +3347,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3486,7 +3515,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3505,7 +3534,7 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_543_DATA 0x00000F08 #define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 @@ -3574,9 +3603,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3742,7 +3771,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3761,7 +3790,7 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_799_DATA 0x00000F08 #define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 @@ -3830,9 +3859,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -4017,7 +4046,7 @@ #define DDRSS1_PHY_1052_DATA 0x00000033 #define DDRSS1_PHY_1053_DATA 0x00543210 #define DDRSS1_PHY_1054_DATA 0x003F0000 -#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1055_DATA 0x000F3F3F #define DDRSS1_PHY_1056_DATA 0x20202003 #define DDRSS1_PHY_1057_DATA 0x00202020 #define DDRSS1_PHY_1058_DATA 0x20008008 @@ -4265,7 +4294,7 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 @@ -4359,7 +4388,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4406,7 +4435,7 @@ #define DDRSS2_CTL_17_DATA 0x00000005 #define DDRSS2_CTL_18_DATA 0x000010A9 #define DDRSS2_CTL_19_DATA 0x01010000 -#define DDRSS2_CTL_20_DATA 0x02011001 +#define DDRSS2_CTL_20_DATA 0x01011001 #define DDRSS2_CTL_21_DATA 0x02010000 #define DDRSS2_CTL_22_DATA 0x00020100 #define DDRSS2_CTL_23_DATA 0x0000000B @@ -4421,7 +4450,7 @@ #define DDRSS2_CTL_32_DATA 0x00000000 #define DDRSS2_CTL_33_DATA 0x00000000 #define DDRSS2_CTL_34_DATA 0x040C0000 -#define DDRSS2_CTL_35_DATA 0x12481248 +#define DDRSS2_CTL_35_DATA 0x12501250 #define DDRSS2_CTL_36_DATA 0x00050804 #define DDRSS2_CTL_37_DATA 0x09040008 #define DDRSS2_CTL_38_DATA 0x15000204 @@ -4436,27 +4465,27 @@ #define DDRSS2_CTL_47_DATA 0x1E161110 #define DDRSS2_CTL_48_DATA 0x1000922C #define DDRSS2_CTL_49_DATA 0x02030410 -#define DDRSS2_CTL_50_DATA 0x2C040500 +#define DDRSS2_CTL_50_DATA 0x2C060500 #define DDRSS2_CTL_51_DATA 0x08292C29 #define DDRSS2_CTL_52_DATA 0x14000E0A #define DDRSS2_CTL_53_DATA 0x04010A0A #define DDRSS2_CTL_54_DATA 0x01010004 -#define DDRSS2_CTL_55_DATA 0x04545408 +#define DDRSS2_CTL_55_DATA 0x0454540A #define DDRSS2_CTL_56_DATA 0x04313104 #define DDRSS2_CTL_57_DATA 0x00003131 #define DDRSS2_CTL_58_DATA 0x00010100 #define DDRSS2_CTL_59_DATA 0x03010000 #define DDRSS2_CTL_60_DATA 0x00001508 -#define DDRSS2_CTL_61_DATA 0x00000063 +#define DDRSS2_CTL_61_DATA 0x00000068 #define DDRSS2_CTL_62_DATA 0x0000032B #define DDRSS2_CTL_63_DATA 0x00001035 #define DDRSS2_CTL_64_DATA 0x0000032B #define DDRSS2_CTL_65_DATA 0x00001035 #define DDRSS2_CTL_66_DATA 0x00000005 #define DDRSS2_CTL_67_DATA 0x00050000 -#define DDRSS2_CTL_68_DATA 0x00CB0012 -#define DDRSS2_CTL_69_DATA 0x00CB0408 -#define DDRSS2_CTL_70_DATA 0x00400408 +#define DDRSS2_CTL_68_DATA 0x00CB0005 +#define DDRSS2_CTL_69_DATA 0x00CB0200 +#define DDRSS2_CTL_70_DATA 0x00400200 #define DDRSS2_CTL_71_DATA 0x00120103 #define DDRSS2_CTL_72_DATA 0x00100005 #define DDRSS2_CTL_73_DATA 0x2F080010 @@ -4562,22 +4591,22 @@ #define DDRSS2_CTL_173_DATA 0x00000000 #define DDRSS2_CTL_174_DATA 0x00000000 #define DDRSS2_CTL_175_DATA 0x3FF40084 -#define DDRSS2_CTL_176_DATA 0x33003FF4 -#define DDRSS2_CTL_177_DATA 0x00003333 +#define DDRSS2_CTL_176_DATA 0xF3003FF4 +#define DDRSS2_CTL_177_DATA 0x0000F3F3 #define DDRSS2_CTL_178_DATA 0x35000000 #define DDRSS2_CTL_179_DATA 0x27270035 #define DDRSS2_CTL_180_DATA 0x0F0F0000 #define DDRSS2_CTL_181_DATA 0x16000000 #define DDRSS2_CTL_182_DATA 0x00841616 #define DDRSS2_CTL_183_DATA 0x3FF43FF4 -#define DDRSS2_CTL_184_DATA 0x33333300 +#define DDRSS2_CTL_184_DATA 0xF3F3F300 #define DDRSS2_CTL_185_DATA 0x00000000 #define DDRSS2_CTL_186_DATA 0x00353500 #define DDRSS2_CTL_187_DATA 0x00002727 #define DDRSS2_CTL_188_DATA 0x00000F0F #define DDRSS2_CTL_189_DATA 0x16161600 #define DDRSS2_CTL_190_DATA 0x00000020 -#define DDRSS2_CTL_191_DATA 0x00000000 +#define DDRSS2_CTL_191_DATA 0x01000000 #define DDRSS2_CTL_192_DATA 0x00000001 #define DDRSS2_CTL_193_DATA 0x00000000 #define DDRSS2_CTL_194_DATA 0x01000000 @@ -4677,14 +4706,14 @@ #define DDRSS2_CTL_288_DATA 0x00000000 #define DDRSS2_CTL_289_DATA 0x00000000 #define DDRSS2_CTL_290_DATA 0x03030300 -#define DDRSS2_CTL_291_DATA 0x00000001 +#define DDRSS2_CTL_291_DATA 0x00010101 #define DDRSS2_CTL_292_DATA 0x00000000 #define DDRSS2_CTL_293_DATA 0x00000000 #define DDRSS2_CTL_294_DATA 0x00000000 #define DDRSS2_CTL_295_DATA 0x00000000 #define DDRSS2_CTL_296_DATA 0x00000000 -#define DDRSS2_CTL_297_DATA 0x00000000 -#define DDRSS2_CTL_298_DATA 0x00000000 +#define DDRSS2_CTL_297_DATA 0xFFFFFFFF +#define DDRSS2_CTL_298_DATA 0x00000FFF #define DDRSS2_CTL_299_DATA 0x00000000 #define DDRSS2_CTL_300_DATA 0x00000000 #define DDRSS2_CTL_301_DATA 0x00000000 @@ -4705,7 +4734,7 @@ #define DDRSS2_CTL_316_DATA 0x01010001 #define DDRSS2_CTL_317_DATA 0x00010101 #define DDRSS2_CTL_318_DATA 0x050A0A03 -#define DDRSS2_CTL_319_DATA 0x10081F1F +#define DDRSS2_CTL_319_DATA 0x10082323 #define DDRSS2_CTL_320_DATA 0x00090310 #define DDRSS2_CTL_321_DATA 0x0B0C030F #define DDRSS2_CTL_322_DATA 0x0B0C0306 @@ -4780,7 +4809,7 @@ #define DDRSS2_CTL_391_DATA 0x00000200 #define DDRSS2_CTL_392_DATA 0x00000200 #define DDRSS2_CTL_393_DATA 0x00000200 -#define DDRSS2_CTL_394_DATA 0x00000252 +#define DDRSS2_CTL_394_DATA 0x00000270 #define DDRSS2_CTL_395_DATA 0x000007BC #define DDRSS2_CTL_396_DATA 0x00000204 #define DDRSS2_CTL_397_DATA 0x0000206A @@ -4790,7 +4819,7 @@ #define DDRSS2_CTL_401_DATA 0x00000200 #define DDRSS2_CTL_402_DATA 0x0000613E #define DDRSS2_CTL_403_DATA 0x00014424 -#define DDRSS2_CTL_404_DATA 0x00000E15 +#define DDRSS2_CTL_404_DATA 0x00000E19 #define DDRSS2_CTL_405_DATA 0x0000206A #define DDRSS2_CTL_406_DATA 0x00000200 #define DDRSS2_CTL_407_DATA 0x00000200 @@ -4798,7 +4827,7 @@ #define DDRSS2_CTL_409_DATA 0x00000200 #define DDRSS2_CTL_410_DATA 0x0000613E #define DDRSS2_CTL_411_DATA 0x00014424 -#define DDRSS2_CTL_412_DATA 0x02020E15 +#define DDRSS2_CTL_412_DATA 0x02020E19 #define DDRSS2_CTL_413_DATA 0x03030202 #define DDRSS2_CTL_414_DATA 0x00000022 #define DDRSS2_CTL_415_DATA 0x00000000 @@ -4815,7 +4844,7 @@ #define DDRSS2_CTL_426_DATA 0x00000000 #define DDRSS2_CTL_427_DATA 0x02000000 #define DDRSS2_CTL_428_DATA 0x01000404 -#define DDRSS2_CTL_429_DATA 0x0B1E0B1E +#define DDRSS2_CTL_429_DATA 0x0B220B22 #define DDRSS2_CTL_430_DATA 0x00000105 #define DDRSS2_CTL_431_DATA 0x00010101 #define DDRSS2_CTL_432_DATA 0x00010101 @@ -4858,8 +4887,8 @@ #define DDRSS2_PI_09_DATA 0x00000000 #define DDRSS2_PI_10_DATA 0x00000000 #define DDRSS2_PI_11_DATA 0x00000000 -#define DDRSS2_PI_12_DATA 0x00000007 -#define DDRSS2_PI_13_DATA 0x00010002 +#define DDRSS2_PI_12_DATA 0x00000003 +#define DDRSS2_PI_13_DATA 0x00010001 #define DDRSS2_PI_14_DATA 0x0800000F #define DDRSS2_PI_15_DATA 0x00000103 #define DDRSS2_PI_16_DATA 0x00000005 @@ -4907,18 +4936,18 @@ #define DDRSS2_PI_58_DATA 0x00000000 #define DDRSS2_PI_59_DATA 0x00000000 #define DDRSS2_PI_60_DATA 0x0A0A140A -#define DDRSS2_PI_61_DATA 0x10020101 +#define DDRSS2_PI_61_DATA 0x10020201 #define DDRSS2_PI_62_DATA 0x00020805 #define DDRSS2_PI_63_DATA 0x01000404 #define DDRSS2_PI_64_DATA 0x00000000 #define DDRSS2_PI_65_DATA 0x00000000 #define DDRSS2_PI_66_DATA 0x00000100 -#define DDRSS2_PI_67_DATA 0x0001010F +#define DDRSS2_PI_67_DATA 0x0002020F #define DDRSS2_PI_68_DATA 0x00340000 #define DDRSS2_PI_69_DATA 0x00000000 #define DDRSS2_PI_70_DATA 0x00000000 #define DDRSS2_PI_71_DATA 0x0000FFFF -#define DDRSS2_PI_72_DATA 0x00000000 +#define DDRSS2_PI_72_DATA 0x01000000 #define DDRSS2_PI_73_DATA 0x00080000 #define DDRSS2_PI_74_DATA 0x02000200 #define DDRSS2_PI_75_DATA 0x01000100 @@ -5007,37 +5036,37 @@ #define DDRSS2_PI_158_DATA 0x00000000 #define DDRSS2_PI_159_DATA 0x00000401 #define DDRSS2_PI_160_DATA 0x00000000 -#define DDRSS2_PI_161_DATA 0x00010000 -#define DDRSS2_PI_162_DATA 0x00000000 -#define DDRSS2_PI_163_DATA 0x2B2B0200 +#define DDRSS2_PI_161_DATA 0x05010000 +#define DDRSS2_PI_162_DATA 0x00000001 +#define DDRSS2_PI_163_DATA 0x2B2B0201 #define DDRSS2_PI_164_DATA 0x00000034 -#define DDRSS2_PI_165_DATA 0x00000064 -#define DDRSS2_PI_166_DATA 0x00020064 +#define DDRSS2_PI_165_DATA 0x00000068 +#define DDRSS2_PI_166_DATA 0x00020068 #define DDRSS2_PI_167_DATA 0x02000200 -#define DDRSS2_PI_168_DATA 0x48120C04 -#define DDRSS2_PI_169_DATA 0x00154812 -#define DDRSS2_PI_170_DATA 0x00000063 +#define DDRSS2_PI_168_DATA 0x50120C04 +#define DDRSS2_PI_169_DATA 0x00155012 +#define DDRSS2_PI_170_DATA 0x00000068 #define DDRSS2_PI_171_DATA 0x0000032B #define DDRSS2_PI_172_DATA 0x00001035 #define DDRSS2_PI_173_DATA 0x0000032B #define DDRSS2_PI_174_DATA 0x04001035 #define DDRSS2_PI_175_DATA 0x01010404 -#define DDRSS2_PI_176_DATA 0x00001501 +#define DDRSS2_PI_176_DATA 0x00001500 #define DDRSS2_PI_177_DATA 0x00150015 #define DDRSS2_PI_178_DATA 0x01000100 #define DDRSS2_PI_179_DATA 0x00000100 #define DDRSS2_PI_180_DATA 0x00000000 #define DDRSS2_PI_181_DATA 0x01010101 -#define DDRSS2_PI_182_DATA 0x00000101 +#define DDRSS2_PI_182_DATA 0x00000000 #define DDRSS2_PI_183_DATA 0x00000000 #define DDRSS2_PI_184_DATA 0x00000000 -#define DDRSS2_PI_185_DATA 0x15040000 -#define DDRSS2_PI_186_DATA 0x0E0E0215 +#define DDRSS2_PI_185_DATA 0x19040000 +#define DDRSS2_PI_186_DATA 0x0E0E0219 #define DDRSS2_PI_187_DATA 0x00040402 #define DDRSS2_PI_188_DATA 0x000D0035 #define DDRSS2_PI_189_DATA 0x00218049 #define DDRSS2_PI_190_DATA 0x00218049 -#define DDRSS2_PI_191_DATA 0x01010101 +#define DDRSS2_PI_191_DATA 0x01000101 #define DDRSS2_PI_192_DATA 0x0004000E #define DDRSS2_PI_193_DATA 0x00040216 #define DDRSS2_PI_194_DATA 0x01000216 @@ -5045,8 +5074,8 @@ #define DDRSS2_PI_196_DATA 0x02170100 #define DDRSS2_PI_197_DATA 0x01000217 #define DDRSS2_PI_198_DATA 0x02170217 -#define DDRSS2_PI_199_DATA 0x32103200 -#define DDRSS2_PI_200_DATA 0x01013210 +#define DDRSS2_PI_199_DATA 0x2F1B3200 +#define DDRSS2_PI_200_DATA 0x01012F1B #define DDRSS2_PI_201_DATA 0x0A070601 #define DDRSS2_PI_202_DATA 0x1F130A0D #define DDRSS2_PI_203_DATA 0x1F130A14 @@ -5058,13 +5087,13 @@ #define DDRSS2_PI_209_DATA 0x00240216 #define DDRSS2_PI_210_DATA 0x00110216 #define DDRSS2_PI_211_DATA 0x32000056 -#define DDRSS2_PI_212_DATA 0x00000301 -#define DDRSS2_PI_213_DATA 0x005B0036 +#define DDRSS2_PI_212_DATA 0x00000101 +#define DDRSS2_PI_213_DATA 0x005F0036 #define DDRSS2_PI_214_DATA 0x03013212 #define DDRSS2_PI_215_DATA 0x00003600 -#define DDRSS2_PI_216_DATA 0x3212005B -#define DDRSS2_PI_217_DATA 0x09000301 -#define DDRSS2_PI_218_DATA 0x04010504 +#define DDRSS2_PI_216_DATA 0x3212005F +#define DDRSS2_PI_217_DATA 0x09000001 +#define DDRSS2_PI_218_DATA 0x06010504 #define DDRSS2_PI_219_DATA 0x04000364 #define DDRSS2_PI_220_DATA 0x0A032001 #define DDRSS2_PI_221_DATA 0x2C31110A @@ -5121,29 +5150,29 @@ #define DDRSS2_PI_272_DATA 0x00080804 #define DDRSS2_PI_273_DATA 0x00000000 #define DDRSS2_PI_274_DATA 0x00000000 -#define DDRSS2_PI_275_DATA 0x00330084 +#define DDRSS2_PI_275_DATA 0x00F30084 #define DDRSS2_PI_276_DATA 0x00160000 -#define DDRSS2_PI_277_DATA 0x35333FF4 +#define DDRSS2_PI_277_DATA 0x35F33FF4 #define DDRSS2_PI_278_DATA 0x00160F27 -#define DDRSS2_PI_279_DATA 0x35333FF4 +#define DDRSS2_PI_279_DATA 0x35F33FF4 #define DDRSS2_PI_280_DATA 0x00160F27 -#define DDRSS2_PI_281_DATA 0x00330084 +#define DDRSS2_PI_281_DATA 0x00F30084 #define DDRSS2_PI_282_DATA 0x00160000 -#define DDRSS2_PI_283_DATA 0x35333FF4 +#define DDRSS2_PI_283_DATA 0x35F33FF4 #define DDRSS2_PI_284_DATA 0x00160F27 -#define DDRSS2_PI_285_DATA 0x35333FF4 +#define DDRSS2_PI_285_DATA 0x35F33FF4 #define DDRSS2_PI_286_DATA 0x00160F27 -#define DDRSS2_PI_287_DATA 0x00330084 +#define DDRSS2_PI_287_DATA 0x00F30084 #define DDRSS2_PI_288_DATA 0x00160000 -#define DDRSS2_PI_289_DATA 0x35333FF4 +#define DDRSS2_PI_289_DATA 0x35F33FF4 #define DDRSS2_PI_290_DATA 0x00160F27 -#define DDRSS2_PI_291_DATA 0x35333FF4 +#define DDRSS2_PI_291_DATA 0x35F33FF4 #define DDRSS2_PI_292_DATA 0x00160F27 -#define DDRSS2_PI_293_DATA 0x00330084 +#define DDRSS2_PI_293_DATA 0x00F30084 #define DDRSS2_PI_294_DATA 0x00160000 -#define DDRSS2_PI_295_DATA 0x35333FF4 +#define DDRSS2_PI_295_DATA 0x35F33FF4 #define DDRSS2_PI_296_DATA 0x00160F27 -#define DDRSS2_PI_297_DATA 0x35333FF4 +#define DDRSS2_PI_297_DATA 0x35F33FF4 #define DDRSS2_PI_298_DATA 0x00160F27 #define DDRSS2_PI_299_DATA 0x00000000 @@ -5159,7 +5188,7 @@ #define DDRSS2_PHY_09_DATA 0x00000000 #define DDRSS2_PHY_10_DATA 0x00000000 #define DDRSS2_PHY_11_DATA 0x01000001 -#define DDRSS2_PHY_12_DATA 0x00000100 +#define DDRSS2_PHY_12_DATA 0x00000200 #define DDRSS2_PHY_13_DATA 0x000800C0 #define DDRSS2_PHY_14_DATA 0x060100CC #define DDRSS2_PHY_15_DATA 0x00030066 @@ -5178,7 +5207,7 @@ #define DDRSS2_PHY_28_DATA 0x2A000000 #define DDRSS2_PHY_29_DATA 0x00000808 #define DDRSS2_PHY_30_DATA 0x0F000000 -#define DDRSS2_PHY_31_DATA 0x00000F0F +#define DDRSS2_PHY_31_DATA 0x00000F08 #define DDRSS2_PHY_32_DATA 0x10400000 #define DDRSS2_PHY_33_DATA 0x0C002006 #define DDRSS2_PHY_34_DATA 0x00000000 @@ -5247,9 +5276,9 @@ #define DDRSS2_PHY_97_DATA 0x00050010 #define DDRSS2_PHY_98_DATA 0x51517041 #define DDRSS2_PHY_99_DATA 0x31C06001 -#define DDRSS2_PHY_100_DATA 0x07AB0340 +#define DDRSS2_PHY_100_DATA 0x07AB01AB #define DDRSS2_PHY_101_DATA 0x00C0C001 -#define DDRSS2_PHY_102_DATA 0x0E0D0001 +#define DDRSS2_PHY_102_DATA 0x0E0D0101 #define DDRSS2_PHY_103_DATA 0x10001000 #define DDRSS2_PHY_104_DATA 0x0C083E42 #define DDRSS2_PHY_105_DATA 0x0F0C3701 @@ -5415,7 +5444,7 @@ #define DDRSS2_PHY_265_DATA 0x00000000 #define DDRSS2_PHY_266_DATA 0x00000000 #define DDRSS2_PHY_267_DATA 0x01000001 -#define DDRSS2_PHY_268_DATA 0x00000100 +#define DDRSS2_PHY_268_DATA 0x00000200 #define DDRSS2_PHY_269_DATA 0x000800C0 #define DDRSS2_PHY_270_DATA 0x060100CC #define DDRSS2_PHY_271_DATA 0x00030066 @@ -5434,7 +5463,7 @@ #define DDRSS2_PHY_284_DATA 0x2A000000 #define DDRSS2_PHY_285_DATA 0x00000808 #define DDRSS2_PHY_286_DATA 0x0F000000 -#define DDRSS2_PHY_287_DATA 0x00000F0F +#define DDRSS2_PHY_287_DATA 0x00000F08 #define DDRSS2_PHY_288_DATA 0x10400000 #define DDRSS2_PHY_289_DATA 0x0C002006 #define DDRSS2_PHY_290_DATA 0x00000000 @@ -5503,9 +5532,9 @@ #define DDRSS2_PHY_353_DATA 0x00050010 #define DDRSS2_PHY_354_DATA 0x51517041 #define DDRSS2_PHY_355_DATA 0x31C06001 -#define DDRSS2_PHY_356_DATA 0x07AB0340 +#define DDRSS2_PHY_356_DATA 0x07AB01AB #define DDRSS2_PHY_357_DATA 0x00C0C001 -#define DDRSS2_PHY_358_DATA 0x0E0D0001 +#define DDRSS2_PHY_358_DATA 0x0E0D0101 #define DDRSS2_PHY_359_DATA 0x10001000 #define DDRSS2_PHY_360_DATA 0x0C083E42 #define DDRSS2_PHY_361_DATA 0x0F0C3701 @@ -5671,7 +5700,7 @@ #define DDRSS2_PHY_521_DATA 0x00000000 #define DDRSS2_PHY_522_DATA 0x00000000 #define DDRSS2_PHY_523_DATA 0x01000001 -#define DDRSS2_PHY_524_DATA 0x00000100 +#define DDRSS2_PHY_524_DATA 0x00000200 #define DDRSS2_PHY_525_DATA 0x000800C0 #define DDRSS2_PHY_526_DATA 0x060100CC #define DDRSS2_PHY_527_DATA 0x00030066 @@ -5690,7 +5719,7 @@ #define DDRSS2_PHY_540_DATA 0x2A000000 #define DDRSS2_PHY_541_DATA 0x00000808 #define DDRSS2_PHY_542_DATA 0x0F000000 -#define DDRSS2_PHY_543_DATA 0x00000F0F +#define DDRSS2_PHY_543_DATA 0x00000F08 #define DDRSS2_PHY_544_DATA 0x10400000 #define DDRSS2_PHY_545_DATA 0x0C002006 #define DDRSS2_PHY_546_DATA 0x00000000 @@ -5759,9 +5788,9 @@ #define DDRSS2_PHY_609_DATA 0x00050010 #define DDRSS2_PHY_610_DATA 0x51517041 #define DDRSS2_PHY_611_DATA 0x31C06001 -#define DDRSS2_PHY_612_DATA 0x07AB0340 +#define DDRSS2_PHY_612_DATA 0x07AB01AB #define DDRSS2_PHY_613_DATA 0x00C0C001 -#define DDRSS2_PHY_614_DATA 0x0E0D0001 +#define DDRSS2_PHY_614_DATA 0x0E0D0101 #define DDRSS2_PHY_615_DATA 0x10001000 #define DDRSS2_PHY_616_DATA 0x0C083E42 #define DDRSS2_PHY_617_DATA 0x0F0C3701 @@ -5927,7 +5956,7 @@ #define DDRSS2_PHY_777_DATA 0x00000000 #define DDRSS2_PHY_778_DATA 0x00000000 #define DDRSS2_PHY_779_DATA 0x01000001 -#define DDRSS2_PHY_780_DATA 0x00000100 +#define DDRSS2_PHY_780_DATA 0x00000200 #define DDRSS2_PHY_781_DATA 0x000800C0 #define DDRSS2_PHY_782_DATA 0x060100CC #define DDRSS2_PHY_783_DATA 0x00030066 @@ -5946,7 +5975,7 @@ #define DDRSS2_PHY_796_DATA 0x2A000000 #define DDRSS2_PHY_797_DATA 0x00000808 #define DDRSS2_PHY_798_DATA 0x0F000000 -#define DDRSS2_PHY_799_DATA 0x00000F0F +#define DDRSS2_PHY_799_DATA 0x00000F08 #define DDRSS2_PHY_800_DATA 0x10400000 #define DDRSS2_PHY_801_DATA 0x0C002006 #define DDRSS2_PHY_802_DATA 0x00000000 @@ -6015,9 +6044,9 @@ #define DDRSS2_PHY_865_DATA 0x00050010 #define DDRSS2_PHY_866_DATA 0x51517041 #define DDRSS2_PHY_867_DATA 0x31C06001 -#define DDRSS2_PHY_868_DATA 0x07AB0340 +#define DDRSS2_PHY_868_DATA 0x07AB01AB #define DDRSS2_PHY_869_DATA 0x00C0C001 -#define DDRSS2_PHY_870_DATA 0x0E0D0001 +#define DDRSS2_PHY_870_DATA 0x0E0D0101 #define DDRSS2_PHY_871_DATA 0x10001000 #define DDRSS2_PHY_872_DATA 0x0C083E42 #define DDRSS2_PHY_873_DATA 0x0F0C3701 @@ -6202,7 +6231,7 @@ #define DDRSS2_PHY_1052_DATA 0x00000033 #define DDRSS2_PHY_1053_DATA 0x00543210 #define DDRSS2_PHY_1054_DATA 0x003F0000 -#define DDRSS2_PHY_1055_DATA 0x000F013F +#define DDRSS2_PHY_1055_DATA 0x000F3F3F #define DDRSS2_PHY_1056_DATA 0x20202003 #define DDRSS2_PHY_1057_DATA 0x00202020 #define DDRSS2_PHY_1058_DATA 0x20008008 @@ -6450,7 +6479,7 @@ #define DDRSS2_PHY_1300_DATA 0x00040101 #define DDRSS2_PHY_1301_DATA 0x0000010F #define DDRSS2_PHY_1302_DATA 0x00000000 -#define DDRSS2_PHY_1303_DATA 0x0000FFFF +#define DDRSS2_PHY_1303_DATA 0x00000064 #define DDRSS2_PHY_1304_DATA 0x00000000 #define DDRSS2_PHY_1305_DATA 0x01010000 #define DDRSS2_PHY_1306_DATA 0x01080402 @@ -6544,7 +6573,7 @@ #define DDRSS2_PHY_1394_DATA 0x00000003 #define DDRSS2_PHY_1395_DATA 0x00000000 #define DDRSS2_PHY_1396_DATA 0x00001142 -#define DDRSS2_PHY_1397_DATA 0x010207AB +#define DDRSS2_PHY_1397_DATA 0x040207AB #define DDRSS2_PHY_1398_DATA 0x01000080 #define DDRSS2_PHY_1399_DATA 0x03900390 #define DDRSS2_PHY_1400_DATA 0x03900390 @@ -6591,7 +6620,7 @@ #define DDRSS3_CTL_17_DATA 0x00000005 #define DDRSS3_CTL_18_DATA 0x000010A9 #define DDRSS3_CTL_19_DATA 0x01010000 -#define DDRSS3_CTL_20_DATA 0x02011001 +#define DDRSS3_CTL_20_DATA 0x01011001 #define DDRSS3_CTL_21_DATA 0x02010000 #define DDRSS3_CTL_22_DATA 0x00020100 #define DDRSS3_CTL_23_DATA 0x0000000B @@ -6606,7 +6635,7 @@ #define DDRSS3_CTL_32_DATA 0x00000000 #define DDRSS3_CTL_33_DATA 0x00000000 #define DDRSS3_CTL_34_DATA 0x040C0000 -#define DDRSS3_CTL_35_DATA 0x12481248 +#define DDRSS3_CTL_35_DATA 0x12501250 #define DDRSS3_CTL_36_DATA 0x00050804 #define DDRSS3_CTL_37_DATA 0x09040008 #define DDRSS3_CTL_38_DATA 0x15000204 @@ -6621,27 +6650,27 @@ #define DDRSS3_CTL_47_DATA 0x1E161110 #define DDRSS3_CTL_48_DATA 0x1000922C #define DDRSS3_CTL_49_DATA 0x02030410 -#define DDRSS3_CTL_50_DATA 0x2C040500 +#define DDRSS3_CTL_50_DATA 0x2C060500 #define DDRSS3_CTL_51_DATA 0x08292C29 #define DDRSS3_CTL_52_DATA 0x14000E0A #define DDRSS3_CTL_53_DATA 0x04010A0A #define DDRSS3_CTL_54_DATA 0x01010004 -#define DDRSS3_CTL_55_DATA 0x04545408 +#define DDRSS3_CTL_55_DATA 0x0454540A #define DDRSS3_CTL_56_DATA 0x04313104 #define DDRSS3_CTL_57_DATA 0x00003131 #define DDRSS3_CTL_58_DATA 0x00010100 #define DDRSS3_CTL_59_DATA 0x03010000 #define DDRSS3_CTL_60_DATA 0x00001508 -#define DDRSS3_CTL_61_DATA 0x00000063 +#define DDRSS3_CTL_61_DATA 0x00000068 #define DDRSS3_CTL_62_DATA 0x0000032B #define DDRSS3_CTL_63_DATA 0x00001035 #define DDRSS3_CTL_64_DATA 0x0000032B #define DDRSS3_CTL_65_DATA 0x00001035 #define DDRSS3_CTL_66_DATA 0x00000005 #define DDRSS3_CTL_67_DATA 0x00050000 -#define DDRSS3_CTL_68_DATA 0x00CB0012 -#define DDRSS3_CTL_69_DATA 0x00CB0408 -#define DDRSS3_CTL_70_DATA 0x00400408 +#define DDRSS3_CTL_68_DATA 0x00CB0005 +#define DDRSS3_CTL_69_DATA 0x00CB0200 +#define DDRSS3_CTL_70_DATA 0x00400200 #define DDRSS3_CTL_71_DATA 0x00120103 #define DDRSS3_CTL_72_DATA 0x00100005 #define DDRSS3_CTL_73_DATA 0x2F080010 @@ -6747,22 +6776,22 @@ #define DDRSS3_CTL_173_DATA 0x00000000 #define DDRSS3_CTL_174_DATA 0x00000000 #define DDRSS3_CTL_175_DATA 0x3FF40084 -#define DDRSS3_CTL_176_DATA 0x33003FF4 -#define DDRSS3_CTL_177_DATA 0x00003333 -#define DDRSS3_CTL_178_DATA 0x35000000 +#define DDRSS3_CTL_176_DATA 0xF3003FF4 +#define DDRSS3_CTL_177_DATA 0x0000F3F3 +#define DDRSS3_CTL_178_DATA 0x35350000 #define DDRSS3_CTL_179_DATA 0x27270035 #define DDRSS3_CTL_180_DATA 0x0F0F0000 #define DDRSS3_CTL_181_DATA 0x16000000 #define DDRSS3_CTL_182_DATA 0x00841616 #define DDRSS3_CTL_183_DATA 0x3FF43FF4 -#define DDRSS3_CTL_184_DATA 0x33333300 +#define DDRSS3_CTL_184_DATA 0xF3F3F300 #define DDRSS3_CTL_185_DATA 0x00000000 -#define DDRSS3_CTL_186_DATA 0x00353500 +#define DDRSS3_CTL_186_DATA 0x00353535 #define DDRSS3_CTL_187_DATA 0x00002727 #define DDRSS3_CTL_188_DATA 0x00000F0F #define DDRSS3_CTL_189_DATA 0x16161600 #define DDRSS3_CTL_190_DATA 0x00000020 -#define DDRSS3_CTL_191_DATA 0x00000000 +#define DDRSS3_CTL_191_DATA 0x01000000 #define DDRSS3_CTL_192_DATA 0x00000001 #define DDRSS3_CTL_193_DATA 0x00000000 #define DDRSS3_CTL_194_DATA 0x01000000 @@ -6862,14 +6891,14 @@ #define DDRSS3_CTL_288_DATA 0x00000000 #define DDRSS3_CTL_289_DATA 0x00000000 #define DDRSS3_CTL_290_DATA 0x03030300 -#define DDRSS3_CTL_291_DATA 0x00000001 +#define DDRSS3_CTL_291_DATA 0x00010101 #define DDRSS3_CTL_292_DATA 0x00000000 #define DDRSS3_CTL_293_DATA 0x00000000 #define DDRSS3_CTL_294_DATA 0x00000000 #define DDRSS3_CTL_295_DATA 0x00000000 #define DDRSS3_CTL_296_DATA 0x00000000 -#define DDRSS3_CTL_297_DATA 0x00000000 -#define DDRSS3_CTL_298_DATA 0x00000000 +#define DDRSS3_CTL_297_DATA 0xFFFFFFFF +#define DDRSS3_CTL_298_DATA 0x00000FFF #define DDRSS3_CTL_299_DATA 0x00000000 #define DDRSS3_CTL_300_DATA 0x00000000 #define DDRSS3_CTL_301_DATA 0x00000000 @@ -6890,7 +6919,7 @@ #define DDRSS3_CTL_316_DATA 0x01010001 #define DDRSS3_CTL_317_DATA 0x00010101 #define DDRSS3_CTL_318_DATA 0x050A0A03 -#define DDRSS3_CTL_319_DATA 0x10081F1F +#define DDRSS3_CTL_319_DATA 0x10082323 #define DDRSS3_CTL_320_DATA 0x00090310 #define DDRSS3_CTL_321_DATA 0x0B0C030F #define DDRSS3_CTL_322_DATA 0x0B0C0306 @@ -6965,7 +6994,7 @@ #define DDRSS3_CTL_391_DATA 0x00000200 #define DDRSS3_CTL_392_DATA 0x00000200 #define DDRSS3_CTL_393_DATA 0x00000200 -#define DDRSS3_CTL_394_DATA 0x00000252 +#define DDRSS3_CTL_394_DATA 0x00000270 #define DDRSS3_CTL_395_DATA 0x000007BC #define DDRSS3_CTL_396_DATA 0x00000204 #define DDRSS3_CTL_397_DATA 0x0000206A @@ -6975,7 +7004,7 @@ #define DDRSS3_CTL_401_DATA 0x00000200 #define DDRSS3_CTL_402_DATA 0x0000613E #define DDRSS3_CTL_403_DATA 0x00014424 -#define DDRSS3_CTL_404_DATA 0x00000E15 +#define DDRSS3_CTL_404_DATA 0x00000E19 #define DDRSS3_CTL_405_DATA 0x0000206A #define DDRSS3_CTL_406_DATA 0x00000200 #define DDRSS3_CTL_407_DATA 0x00000200 @@ -6983,7 +7012,7 @@ #define DDRSS3_CTL_409_DATA 0x00000200 #define DDRSS3_CTL_410_DATA 0x0000613E #define DDRSS3_CTL_411_DATA 0x00014424 -#define DDRSS3_CTL_412_DATA 0x02020E15 +#define DDRSS3_CTL_412_DATA 0x02020E19 #define DDRSS3_CTL_413_DATA 0x03030202 #define DDRSS3_CTL_414_DATA 0x00000022 #define DDRSS3_CTL_415_DATA 0x00000000 @@ -7000,7 +7029,7 @@ #define DDRSS3_CTL_426_DATA 0x00000000 #define DDRSS3_CTL_427_DATA 0x02000000 #define DDRSS3_CTL_428_DATA 0x01000404 -#define DDRSS3_CTL_429_DATA 0x0B1E0B1E +#define DDRSS3_CTL_429_DATA 0x0B220B22 #define DDRSS3_CTL_430_DATA 0x00000105 #define DDRSS3_CTL_431_DATA 0x00010101 #define DDRSS3_CTL_432_DATA 0x00010101 @@ -7043,8 +7072,8 @@ #define DDRSS3_PI_09_DATA 0x00000000 #define DDRSS3_PI_10_DATA 0x00000000 #define DDRSS3_PI_11_DATA 0x00000000 -#define DDRSS3_PI_12_DATA 0x00000007 -#define DDRSS3_PI_13_DATA 0x00010002 +#define DDRSS3_PI_12_DATA 0x00000003 +#define DDRSS3_PI_13_DATA 0x00010001 #define DDRSS3_PI_14_DATA 0x0800000F #define DDRSS3_PI_15_DATA 0x00000103 #define DDRSS3_PI_16_DATA 0x00000005 @@ -7092,18 +7121,18 @@ #define DDRSS3_PI_58_DATA 0x00000000 #define DDRSS3_PI_59_DATA 0x00000000 #define DDRSS3_PI_60_DATA 0x0A0A140A -#define DDRSS3_PI_61_DATA 0x10020101 +#define DDRSS3_PI_61_DATA 0x10020201 #define DDRSS3_PI_62_DATA 0x00020805 #define DDRSS3_PI_63_DATA 0x01000404 #define DDRSS3_PI_64_DATA 0x00000000 #define DDRSS3_PI_65_DATA 0x00000000 #define DDRSS3_PI_66_DATA 0x00000100 -#define DDRSS3_PI_67_DATA 0x0001010F +#define DDRSS3_PI_67_DATA 0x0002020F #define DDRSS3_PI_68_DATA 0x00340000 #define DDRSS3_PI_69_DATA 0x00000000 #define DDRSS3_PI_70_DATA 0x00000000 #define DDRSS3_PI_71_DATA 0x0000FFFF -#define DDRSS3_PI_72_DATA 0x00000000 +#define DDRSS3_PI_72_DATA 0x01000000 #define DDRSS3_PI_73_DATA 0x00080000 #define DDRSS3_PI_74_DATA 0x02000200 #define DDRSS3_PI_75_DATA 0x01000100 @@ -7192,37 +7221,37 @@ #define DDRSS3_PI_158_DATA 0x00000000 #define DDRSS3_PI_159_DATA 0x00000401 #define DDRSS3_PI_160_DATA 0x00000000 -#define DDRSS3_PI_161_DATA 0x00010000 -#define DDRSS3_PI_162_DATA 0x00000000 -#define DDRSS3_PI_163_DATA 0x2B2B0200 +#define DDRSS3_PI_161_DATA 0x05010000 +#define DDRSS3_PI_162_DATA 0x00000001 +#define DDRSS3_PI_163_DATA 0x2B2B0201 #define DDRSS3_PI_164_DATA 0x00000034 -#define DDRSS3_PI_165_DATA 0x00000064 -#define DDRSS3_PI_166_DATA 0x00020064 +#define DDRSS3_PI_165_DATA 0x00000068 +#define DDRSS3_PI_166_DATA 0x00020068 #define DDRSS3_PI_167_DATA 0x02000200 -#define DDRSS3_PI_168_DATA 0x48120C04 -#define DDRSS3_PI_169_DATA 0x00154812 -#define DDRSS3_PI_170_DATA 0x00000063 +#define DDRSS3_PI_168_DATA 0x50120C04 +#define DDRSS3_PI_169_DATA 0x00155012 +#define DDRSS3_PI_170_DATA 0x00000068 #define DDRSS3_PI_171_DATA 0x0000032B #define DDRSS3_PI_172_DATA 0x00001035 #define DDRSS3_PI_173_DATA 0x0000032B #define DDRSS3_PI_174_DATA 0x04001035 #define DDRSS3_PI_175_DATA 0x01010404 -#define DDRSS3_PI_176_DATA 0x00001501 +#define DDRSS3_PI_176_DATA 0x00001500 #define DDRSS3_PI_177_DATA 0x00150015 #define DDRSS3_PI_178_DATA 0x01000100 #define DDRSS3_PI_179_DATA 0x00000100 #define DDRSS3_PI_180_DATA 0x00000000 #define DDRSS3_PI_181_DATA 0x01010101 -#define DDRSS3_PI_182_DATA 0x00000101 +#define DDRSS3_PI_182_DATA 0x00000000 #define DDRSS3_PI_183_DATA 0x00000000 #define DDRSS3_PI_184_DATA 0x00000000 -#define DDRSS3_PI_185_DATA 0x15040000 -#define DDRSS3_PI_186_DATA 0x0E0E0215 +#define DDRSS3_PI_185_DATA 0x19040000 +#define DDRSS3_PI_186_DATA 0x0E0E0219 #define DDRSS3_PI_187_DATA 0x00040402 #define DDRSS3_PI_188_DATA 0x000D0035 #define DDRSS3_PI_189_DATA 0x00218049 #define DDRSS3_PI_190_DATA 0x00218049 -#define DDRSS3_PI_191_DATA 0x01010101 +#define DDRSS3_PI_191_DATA 0x01000101 #define DDRSS3_PI_192_DATA 0x0004000E #define DDRSS3_PI_193_DATA 0x00040216 #define DDRSS3_PI_194_DATA 0x01000216 @@ -7230,8 +7259,8 @@ #define DDRSS3_PI_196_DATA 0x02170100 #define DDRSS3_PI_197_DATA 0x01000217 #define DDRSS3_PI_198_DATA 0x02170217 -#define DDRSS3_PI_199_DATA 0x32103200 -#define DDRSS3_PI_200_DATA 0x01013210 +#define DDRSS3_PI_199_DATA 0x2F1B3200 +#define DDRSS3_PI_200_DATA 0x01012F1B #define DDRSS3_PI_201_DATA 0x0A070601 #define DDRSS3_PI_202_DATA 0x1F130A0D #define DDRSS3_PI_203_DATA 0x1F130A14 @@ -7243,13 +7272,13 @@ #define DDRSS3_PI_209_DATA 0x00240216 #define DDRSS3_PI_210_DATA 0x00110216 #define DDRSS3_PI_211_DATA 0x32000056 -#define DDRSS3_PI_212_DATA 0x00000301 -#define DDRSS3_PI_213_DATA 0x005B0036 +#define DDRSS3_PI_212_DATA 0x00000101 +#define DDRSS3_PI_213_DATA 0x005F0036 #define DDRSS3_PI_214_DATA 0x03013212 #define DDRSS3_PI_215_DATA 0x00003600 -#define DDRSS3_PI_216_DATA 0x3212005B -#define DDRSS3_PI_217_DATA 0x09000301 -#define DDRSS3_PI_218_DATA 0x04010504 +#define DDRSS3_PI_216_DATA 0x3212005F +#define DDRSS3_PI_217_DATA 0x09000001 +#define DDRSS3_PI_218_DATA 0x06010504 #define DDRSS3_PI_219_DATA 0x04000364 #define DDRSS3_PI_220_DATA 0x0A032001 #define DDRSS3_PI_221_DATA 0x2C31110A @@ -7306,29 +7335,29 @@ #define DDRSS3_PI_272_DATA 0x00080804 #define DDRSS3_PI_273_DATA 0x00000000 #define DDRSS3_PI_274_DATA 0x00000000 -#define DDRSS3_PI_275_DATA 0x00330084 +#define DDRSS3_PI_275_DATA 0x35F30084 #define DDRSS3_PI_276_DATA 0x00160000 -#define DDRSS3_PI_277_DATA 0x35333FF4 +#define DDRSS3_PI_277_DATA 0x35F33FF4 #define DDRSS3_PI_278_DATA 0x00160F27 -#define DDRSS3_PI_279_DATA 0x35333FF4 +#define DDRSS3_PI_279_DATA 0x35F33FF4 #define DDRSS3_PI_280_DATA 0x00160F27 -#define DDRSS3_PI_281_DATA 0x00330084 +#define DDRSS3_PI_281_DATA 0x35F30084 #define DDRSS3_PI_282_DATA 0x00160000 -#define DDRSS3_PI_283_DATA 0x35333FF4 +#define DDRSS3_PI_283_DATA 0x35F33FF4 #define DDRSS3_PI_284_DATA 0x00160F27 -#define DDRSS3_PI_285_DATA 0x35333FF4 +#define DDRSS3_PI_285_DATA 0x35F33FF4 #define DDRSS3_PI_286_DATA 0x00160F27 -#define DDRSS3_PI_287_DATA 0x00330084 +#define DDRSS3_PI_287_DATA 0x35F30084 #define DDRSS3_PI_288_DATA 0x00160000 -#define DDRSS3_PI_289_DATA 0x35333FF4 +#define DDRSS3_PI_289_DATA 0x35F33FF4 #define DDRSS3_PI_290_DATA 0x00160F27 -#define DDRSS3_PI_291_DATA 0x35333FF4 +#define DDRSS3_PI_291_DATA 0x35F33FF4 #define DDRSS3_PI_292_DATA 0x00160F27 -#define DDRSS3_PI_293_DATA 0x00330084 +#define DDRSS3_PI_293_DATA 0x35F30084 #define DDRSS3_PI_294_DATA 0x00160000 -#define DDRSS3_PI_295_DATA 0x35333FF4 +#define DDRSS3_PI_295_DATA 0x35F33FF4 #define DDRSS3_PI_296_DATA 0x00160F27 -#define DDRSS3_PI_297_DATA 0x35333FF4 +#define DDRSS3_PI_297_DATA 0x35F33FF4 #define DDRSS3_PI_298_DATA 0x00160F27 #define DDRSS3_PI_299_DATA 0x00000000 @@ -7344,7 +7373,7 @@ #define DDRSS3_PHY_09_DATA 0x00000000 #define DDRSS3_PHY_10_DATA 0x00000000 #define DDRSS3_PHY_11_DATA 0x01000001 -#define DDRSS3_PHY_12_DATA 0x00000100 +#define DDRSS3_PHY_12_DATA 0x00000200 #define DDRSS3_PHY_13_DATA 0x000800C0 #define DDRSS3_PHY_14_DATA 0x060100CC #define DDRSS3_PHY_15_DATA 0x00030066 @@ -7363,7 +7392,7 @@ #define DDRSS3_PHY_28_DATA 0x2A000000 #define DDRSS3_PHY_29_DATA 0x00000808 #define DDRSS3_PHY_30_DATA 0x0F000000 -#define DDRSS3_PHY_31_DATA 0x00000F0F +#define DDRSS3_PHY_31_DATA 0x00000F08 #define DDRSS3_PHY_32_DATA 0x10400000 #define DDRSS3_PHY_33_DATA 0x0C002006 #define DDRSS3_PHY_34_DATA 0x00000000 @@ -7432,9 +7461,9 @@ #define DDRSS3_PHY_97_DATA 0x00050010 #define DDRSS3_PHY_98_DATA 0x51517041 #define DDRSS3_PHY_99_DATA 0x31C06001 -#define DDRSS3_PHY_100_DATA 0x07AB0340 +#define DDRSS3_PHY_100_DATA 0x07AB01AB #define DDRSS3_PHY_101_DATA 0x00C0C001 -#define DDRSS3_PHY_102_DATA 0x0E0D0001 +#define DDRSS3_PHY_102_DATA 0x0E0D0101 #define DDRSS3_PHY_103_DATA 0x10001000 #define DDRSS3_PHY_104_DATA 0x0C083E42 #define DDRSS3_PHY_105_DATA 0x0F0C3701 @@ -7600,7 +7629,7 @@ #define DDRSS3_PHY_265_DATA 0x00000000 #define DDRSS3_PHY_266_DATA 0x00000000 #define DDRSS3_PHY_267_DATA 0x01000001 -#define DDRSS3_PHY_268_DATA 0x00000100 +#define DDRSS3_PHY_268_DATA 0x00000200 #define DDRSS3_PHY_269_DATA 0x000800C0 #define DDRSS3_PHY_270_DATA 0x060100CC #define DDRSS3_PHY_271_DATA 0x00030066 @@ -7619,7 +7648,7 @@ #define DDRSS3_PHY_284_DATA 0x2A000000 #define DDRSS3_PHY_285_DATA 0x00000808 #define DDRSS3_PHY_286_DATA 0x0F000000 -#define DDRSS3_PHY_287_DATA 0x00000F0F +#define DDRSS3_PHY_287_DATA 0x00000F08 #define DDRSS3_PHY_288_DATA 0x10400000 #define DDRSS3_PHY_289_DATA 0x0C002006 #define DDRSS3_PHY_290_DATA 0x00000000 @@ -7688,9 +7717,9 @@ #define DDRSS3_PHY_353_DATA 0x00050010 #define DDRSS3_PHY_354_DATA 0x51517041 #define DDRSS3_PHY_355_DATA 0x31C06001 -#define DDRSS3_PHY_356_DATA 0x07AB0340 +#define DDRSS3_PHY_356_DATA 0x07AB01AB #define DDRSS3_PHY_357_DATA 0x00C0C001 -#define DDRSS3_PHY_358_DATA 0x0E0D0001 +#define DDRSS3_PHY_358_DATA 0x0E0D0101 #define DDRSS3_PHY_359_DATA 0x10001000 #define DDRSS3_PHY_360_DATA 0x0C083E42 #define DDRSS3_PHY_361_DATA 0x0F0C3701 @@ -7856,7 +7885,7 @@ #define DDRSS3_PHY_521_DATA 0x00000000 #define DDRSS3_PHY_522_DATA 0x00000000 #define DDRSS3_PHY_523_DATA 0x01000001 -#define DDRSS3_PHY_524_DATA 0x00000100 +#define DDRSS3_PHY_524_DATA 0x00000200 #define DDRSS3_PHY_525_DATA 0x000800C0 #define DDRSS3_PHY_526_DATA 0x060100CC #define DDRSS3_PHY_527_DATA 0x00030066 @@ -7875,7 +7904,7 @@ #define DDRSS3_PHY_540_DATA 0x2A000000 #define DDRSS3_PHY_541_DATA 0x00000808 #define DDRSS3_PHY_542_DATA 0x0F000000 -#define DDRSS3_PHY_543_DATA 0x00000F0F +#define DDRSS3_PHY_543_DATA 0x00000F08 #define DDRSS3_PHY_544_DATA 0x10400000 #define DDRSS3_PHY_545_DATA 0x0C002006 #define DDRSS3_PHY_546_DATA 0x00000000 @@ -7944,9 +7973,9 @@ #define DDRSS3_PHY_609_DATA 0x00050010 #define DDRSS3_PHY_610_DATA 0x51517041 #define DDRSS3_PHY_611_DATA 0x31C06001 -#define DDRSS3_PHY_612_DATA 0x07AB0340 +#define DDRSS3_PHY_612_DATA 0x07AB01AB #define DDRSS3_PHY_613_DATA 0x00C0C001 -#define DDRSS3_PHY_614_DATA 0x0E0D0001 +#define DDRSS3_PHY_614_DATA 0x0E0D0101 #define DDRSS3_PHY_615_DATA 0x10001000 #define DDRSS3_PHY_616_DATA 0x0C083E42 #define DDRSS3_PHY_617_DATA 0x0F0C3701 @@ -8112,7 +8141,7 @@ #define DDRSS3_PHY_777_DATA 0x00000000 #define DDRSS3_PHY_778_DATA 0x00000000 #define DDRSS3_PHY_779_DATA 0x01000001 -#define DDRSS3_PHY_780_DATA 0x00000100 +#define DDRSS3_PHY_780_DATA 0x00000200 #define DDRSS3_PHY_781_DATA 0x000800C0 #define DDRSS3_PHY_782_DATA 0x060100CC #define DDRSS3_PHY_783_DATA 0x00030066 @@ -8131,7 +8160,7 @@ #define DDRSS3_PHY_796_DATA 0x2A000000 #define DDRSS3_PHY_797_DATA 0x00000808 #define DDRSS3_PHY_798_DATA 0x0F000000 -#define DDRSS3_PHY_799_DATA 0x00000F0F +#define DDRSS3_PHY_799_DATA 0x00000F08 #define DDRSS3_PHY_800_DATA 0x10400000 #define DDRSS3_PHY_801_DATA 0x0C002006 #define DDRSS3_PHY_802_DATA 0x00000000 @@ -8200,9 +8229,9 @@ #define DDRSS3_PHY_865_DATA 0x00050010 #define DDRSS3_PHY_866_DATA 0x51517041 #define DDRSS3_PHY_867_DATA 0x31C06001 -#define DDRSS3_PHY_868_DATA 0x07AB0340 +#define DDRSS3_PHY_868_DATA 0x07AB01AB #define DDRSS3_PHY_869_DATA 0x00C0C001 -#define DDRSS3_PHY_870_DATA 0x0E0D0001 +#define DDRSS3_PHY_870_DATA 0x0E0D0101 #define DDRSS3_PHY_871_DATA 0x10001000 #define DDRSS3_PHY_872_DATA 0x0C083E42 #define DDRSS3_PHY_873_DATA 0x0F0C3701 @@ -8387,7 +8416,7 @@ #define DDRSS3_PHY_1052_DATA 0x00000033 #define DDRSS3_PHY_1053_DATA 0x00543210 #define DDRSS3_PHY_1054_DATA 0x003F0000 -#define DDRSS3_PHY_1055_DATA 0x000F013F +#define DDRSS3_PHY_1055_DATA 0x000F3F3F #define DDRSS3_PHY_1056_DATA 0x20202003 #define DDRSS3_PHY_1057_DATA 0x00202020 #define DDRSS3_PHY_1058_DATA 0x20008008 @@ -8635,7 +8664,7 @@ #define DDRSS3_PHY_1300_DATA 0x00040101 #define DDRSS3_PHY_1301_DATA 0x0000010F #define DDRSS3_PHY_1302_DATA 0x00000000 -#define DDRSS3_PHY_1303_DATA 0x0000FFFF +#define DDRSS3_PHY_1303_DATA 0x00000064 #define DDRSS3_PHY_1304_DATA 0x00000000 #define DDRSS3_PHY_1305_DATA 0x01010000 #define DDRSS3_PHY_1306_DATA 0x01080402 @@ -8729,7 +8758,7 @@ #define DDRSS3_PHY_1394_DATA 0x00000003 #define DDRSS3_PHY_1395_DATA 0x00000000 #define DDRSS3_PHY_1396_DATA 0x00001142 -#define DDRSS3_PHY_1397_DATA 0x010207AB +#define DDRSS3_PHY_1397_DATA 0x040207AB #define DDRSS3_PHY_1398_DATA 0x01000080 #define DDRSS3_PHY_1399_DATA 0x03900390 #define DDRSS3_PHY_1400_DATA 0x03900390 diff --git a/arch/arm/dts/lemans-evk-u-boot.dtsi b/arch/arm/dts/lemans-evk-u-boot.dtsi new file mode 100644 index 00000000000..cdd3d32f61a --- /dev/null +++ b/arch/arm/dts/lemans-evk-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/ { + /* Will be removed when bootloader updates later */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x3ee00000>, + <0x0 0xc0000000 0x0 0x0fd00000>, + <0xD 0x00000000 0x2 0x54100000>, + <0xA 0x80000000 0x1 0x80000000>, + <0x9 0x00000000 0x1 0x80000000>, + <0x1 0x00000000 0x3 0x00000000>, + <0x0 0xd0000000 0x0 0x01900000>, + <0x0 0xd3500000 0x0 0x2cb00000>; + }; +}; diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts index e74d0956194..b5d9caa73e6 100644 --- a/arch/arm/dts/ls1021a-tsn.dts +++ b/arch/arm/dts/ls1021a-tsn.dts @@ -173,7 +173,7 @@ status = "okay"; flash@0 { - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; }; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 4f65ee765e3..005a40eff23 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -205,7 +205,7 @@ clocks = <&sysclk>; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -218,7 +218,7 @@ status = "disabled"; }; - dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -231,7 +231,7 @@ status = "disabled"; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi index d246be63293..891d3249ecd 100644 --- a/arch/arm/dts/mt8189.dtsi +++ b/arch/arm/dts/mt8189.dtsi @@ -7,6 +7,8 @@ #include <dt-bindings/clock/mediatek,mt8189-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/ti-syscon.h> / { compatible = "mediatek,mt8189"; @@ -179,6 +181,96 @@ status = "disabled"; }; + nor_flash: spi@11018000 { + compatible = "mediatek,mt8189-nor","mediatek,mt8186-nor"; + reg = <0 0x11018000 0 0x1000>; + clocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>, + <&pericfg_ao_clk CLK_PERAO_SFLASH>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_F>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_H>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_P>; + clock-names = "spi", "sf", "axi_f", "axi_h", "axi_p"; + assigned-clocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D8>; + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + xhci0: usb@11200000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 207 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB0_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_FRMCNT>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x214 110>; + status = "disabled"; + }; + + xhci1: usb@11210000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11210000 0 0x1000>, + <0 0x11213e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 203 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port1 PHY_TYPE_USB2>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB1_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_FRMCNT>; + clock-names = "sys_ck", "ref_ck","mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x21c 110>; + status = "disabled"; + }; + + xhci2: usb@11220000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11220000 0 0x1000>, + <0 0x11223e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 193 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port2 PHY_TYPE_USB2>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB2_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_FRMCNT>; + clock-names = "sys_ck", "ref_ck","mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x27c 110>; + status = "disabled"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8189-mmc"; reg = <0 0x11230000 0 0x10000>, @@ -203,6 +295,55 @@ status = "disabled"; }; + xhci3: usb@11260000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11260000 0 0x2e00>, + <0 0x11263e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 188 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port3 PHY_TYPE_USB2>, + <&u3port3 PHY_TYPE_USB3>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB3_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_FRMCNT>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x284 110>; + status = "disabled"; + }; + + xhci4: usb@11270000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11270000 0 0x1000>, + <0 0x11273e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port4 PHY_TYPE_USB2>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB4_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_FRMCNT>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x28c 110>; + status = "disabled"; + }; + clock-controller@1000c000 { compatible = "mediatek,mt8189-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; @@ -286,6 +427,207 @@ #interrupt-cells = <2>; }; + ufshci: ufshci@112b0000 { + compatible = "mediatek,mt8183-ufshci"; + reg = <0 0x112b0000 0 0x2300>; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&topckgen_clk CLK_TOP_U_SEL>, + <&clk26m>, + <&topckgen_clk CLK_TOP_MSDCPLL_D2>, + <&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>, + <&topckgen_clk CLK_TOP_U_MBIST_SEL>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_SYS>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_SAP_CFG>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_UFS>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_AES>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AHB>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AXI>; + + clock-names = "ufs_sel", + "ufs_sel_min_src", + "ufs_sel_max_src", + "ufs_fde", + "ufs_mbist", + "unipro_tx_sym", + "unipro_rx_sym0", + "unipro_rx_sym1", + "unipro_sys", + "unipro_phy_sap", + "phy_top_ahb_s_bus", + "ufshci_ufs", + "ufshci_aes", + "ufshci_ufs_ahb", + "ufshci_aes_axi"; + + freq-table-hz = <26000000 208000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + vcc-supply = <&mt6359_vemc_1_ldo_reg>; + vccq-supply = <&mt6359_vio18_ldo_reg>; + vccq2-supply = <&mt6359_vufs_ldo_reg>; + + resets = <&ufscfgpdn_rst 0>, + <&ufscfgpdn_rst 1>, + <&ufscfgpdn_rst 2>; + + reset-names = "unipro_rst", + "crypto_rst", + "hci_rst"; + + mediatek,ufs-disable-mcq; + mediatek,ufs-rtff-mtcmos; + mediatek,ufs-broken-vcc; + + status = "disabled"; + }; + + u3phy3: t-phy@11b00000 { + compatible = "mediatek,mt8189-tphy", + "mediatek,generic-tphy-v2"; + reg = <0 0x11b00000 0 0x700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port3: usb-phy@11b00000 { + reg = <0 0x11b00000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P3_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port3: usb-phy@11b00700 { + reg = <0 0x11b00700 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P3_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u2phy4: xs-phy@11b10000 { + compatible = "mediatek,mt8189-xsphy", "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port4: usb-phy@11b10000 { + reg = <0 0x11b10000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P4_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u3phy0: xs-phy@11e80000 { + compatible = "mediatek,mt8189-xsphy", "mediatek,xsphy"; + reg = <0 0x11e83000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port0: usb-phy@11e80000 { + reg = <0 0x11e80000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P0_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@11e83000 { + reg = <0 0x11e83400 0 0x500>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P0_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u2phy1: xs-phy@11e90000 { + compatible = "mediatek,mt8189-xsphy", "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port1: usb-phy@11e90000 { + reg = <0 0x11e90000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P1_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u2phy2: xs-phy@11ef0000 { + compatible = "mediatek,mt8189-xsphy", "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port2: usb-phy@11ef0000 { + reg = <0 0x11ef0000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P2_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + ufscfg_ao_reg_clk: syscon@112b8000 { + compatible = "mediatek,mt8189-ufscfg-ao", "syscon", "simple-mfd"; + reg = <0 0x112b8000 0 0x1000>; + #clock-cells = <1>; + + ufscfgao_rst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + /* ufs mphy reset */ + /* 8: mphy */ + 0x48 8 0x4c 8 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; + + ufscfg_pdn_reg_clk: syscon@112bb000 { + compatible = "mediatek,mt8189-ufscfg-pdn", "syscon", "simple-mfd"; + reg = <0 0x112bb000 0 0x1000>; + #clock-cells = <1>; + + ufscfgpdn_rst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + /* ufs ufschi/crypto/unipro reset */ + /* 0: unipro */ + 0x48 0 0x4c 0 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + /* 1: ufs-crypto */ + 0x48 1 0x4c 1 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + /* 2: ufshci */ + 0x48 2 0x4c 2 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; + pwrap: pwrap@1cc04000 { compatible = "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "syscon"; reg = <0 0x1cc04000 0 0x1000>; diff --git a/arch/arm/dts/mt8371-genio-common-ufs.dtso b/arch/arm/dts/mt8371-genio-common-ufs.dtso new file mode 100644 index 00000000000..b75fdafcf9b --- /dev/null +++ b/arch/arm/dts/mt8371-genio-common-ufs.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 MediaTek Inc. + * + * Adjusts for when boot DIP switches/jumpers on EVK are set for UFS boot + * instead of eMMC. + */ + +/dts-v1/; +/plugin/; + +&ufshci { + status = "okay"; +}; + +&mmc0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/mt8371-genio-common.dtsi b/arch/arm/dts/mt8371-genio-common.dtsi index 58322193aef..1d4728e3732 100644 --- a/arch/arm/dts/mt8371-genio-common.dtsi +++ b/arch/arm/dts/mt8371-genio-common.dtsi @@ -19,6 +19,51 @@ stdout-path = "serial0:921600n8"; }; + usb_p0_vbus: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "p0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 82 0>; + enable-active-high; + }; + + usb_p1_vbus: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "p1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 0>; + enable-active-high; + }; + + usb_p2_vbus: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "p2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 85 0>; + enable-active-high; + }; + + usb_p3_vbus: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "p3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 86 0>; + enable-active-high; + }; + + usb_p4_vbus: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "p4_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 87 0>; + enable-active-high; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -117,6 +162,21 @@ regulator-always-on; }; +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &pio { mmc0_default_pins: mmc0-default-pins { pins-clk { @@ -229,6 +289,22 @@ }; }; + nor_pins: nor-pins { + pins-ck-io { + pinmux = <PINMUX_GPIO150__FUNC_SPINOR_CK>, + <PINMUX_GPIO152__FUNC_SPINOR_IO0>, + <PINMUX_GPIO153__FUNC_SPINOR_IO1>; + drive-strength = <8>; + bias-pull-down; + }; + + pins-cs { + pinmux = <PINMUX_GPIO151__FUNC_SPINOR_CS>; + drive-strength = <8>; + bias-pull-up; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = <PINMUX_GPIO31__FUNC_UTXD0>, @@ -241,3 +317,28 @@ &pmic { interrupts-extended = <&pio 194 IRQ_TYPE_LEVEL_HIGH>; }; + +&xhci0{ + vbus-supply = <&usb_p0_vbus>; + status = "okay"; +}; + +&xhci1{ + vbus-supply = <&usb_p1_vbus>; + status = "okay"; +}; + +&xhci2{ + vbus-supply = <&usb_p2_vbus>; + status = "okay"; +}; + +&xhci3{ + vbus-supply = <&usb_p3_vbus>; + status = "okay"; +}; + +&xhci4{ + vbus-supply = <&usb_p4_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi index 8d4871135fa..c3ec4a317f7 100644 --- a/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi +++ b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi @@ -17,10 +17,6 @@ }; }; -&usb_1 { - dr_mode = "host"; -}; - // RAM Entry 0 : Base 0x0080000000 Size 0x003A800000 // RAM Entry 1 : Base 0x00C0000000 Size 0x0001800000 // RAM Entry 2 : Base 0x00C3400000 Size 0x003CC00000 diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi b/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi index 34fba29e859..9a30425bdad 100644 --- a/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi +++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi @@ -49,7 +49,6 @@ compatible = "renesas,r7s72100-rpc-if"; reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>; bank-width = <2>; - num-cs = <1>; status = "okay"; spi-max-frequency = <50000000>; #address-cells = <1>; diff --git a/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi b/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi index dcdddd9aed6..9a77e242af2 100644 --- a/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi +++ b/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi @@ -14,7 +14,6 @@ }; &rpc { - num-cs = <1>; status = "okay"; spi-max-frequency = <50000000>; #address-cells = <1>; diff --git a/arch/arm/dts/r8a774c0-u-boot.dtsi b/arch/arm/dts/r8a774c0-u-boot.dtsi index 17b863d23c9..d7b98783196 100644 --- a/arch/arm/dts/r8a774c0-u-boot.dtsi +++ b/arch/arm/dts/r8a774c0-u-boot.dtsi @@ -6,18 +6,6 @@ * */ -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a774c0-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; - /delete-node/ &can0; /delete-node/ &can1; /delete-node/ &canfd; diff --git a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi index d88e839a890..a162173b493 100644 --- a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi @@ -23,11 +23,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77951-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index 13760f3d5d4..e8a7fa27a76 100644 --- a/arch/arm/dts/r8a77951-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -5,18 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a7795-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; - /delete-node/ &ak4613; /delete-node/ &audma0; /delete-node/ &audma1; diff --git a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi index 8269d967af9..81bf715d300 100644 --- a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi @@ -32,11 +32,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi index 0a1602cdd23..3c90e2a87ad 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi @@ -23,11 +23,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index 9cc0d52f634..b437792a172 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -5,18 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a7796-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; - /delete-node/ &ak4613; /delete-node/ &audma0; /delete-node/ &audma1; diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi index d2a0406be17..2cc222d756a 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi @@ -32,11 +32,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi index 518466aca35..3ad407f022e 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi @@ -23,11 +23,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index 3cf32d84ca0..57382e34912 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -5,18 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77965-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; - /delete-node/ &ak4613; /delete-node/ &audma0; /delete-node/ &audma1; diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi index 3905bf4e4f7..ce715f61976 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi @@ -32,11 +32,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77970-eagle-u-boot.dtsi b/arch/arm/dts/r8a77970-eagle-u-boot.dtsi index c7971b9e9ce..27709ac8a71 100644 --- a/arch/arm/dts/r8a77970-eagle-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-eagle-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -#include "r8a77970-u-boot.dtsi" #include <dt-bindings/gpio/gpio.h> / { @@ -14,29 +13,8 @@ }; }; -&avb { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - -}; - -&phy0 { - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -}; - -&pfc { - avb0_pins: avb { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - }; -}; - &rpc { - num-cs = <1>; status = "okay"; - spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi deleted file mode 100644 index d00ef2f3105..00000000000 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A77970 SoC - * - * Copyright (C) 2018 Marek Vasut <[email protected]> - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77970-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi b/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi index c7b2e07793d..a94fe92c831 100644 --- a/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Cogent Embedded, Inc. */ -#include "r8a77970-u-boot.dtsi" #include <dt-bindings/gpio/gpio.h> / { @@ -25,29 +24,8 @@ }; }; -&avb { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - -}; - -&phy0 { - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -}; - -&pfc { - avb0_pins: avb { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - }; -}; - &rpc { - num-cs = <1>; status = "okay"; - spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dtsi b/arch/arm/dts/r8a77980-condor-u-boot.dtsi index 382bfe8cacd..34acdb1717c 100644 --- a/arch/arm/dts/r8a77980-condor-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-condor-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2019 Marek Vasut <[email protected]> */ -#include "r8a77980-u-boot.dtsi" - / { aliases { spi0 = &rpc; @@ -28,9 +26,7 @@ }; &rpc { - num-cs = <1>; status = "okay"; - spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi b/arch/arm/dts/r8a77980-u-boot.dtsi deleted file mode 100644 index df862978cba..00000000000 --- a/arch/arm/dts/r8a77980-u-boot.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A77980 SoC - * - * Copyright (C) 2019 Marek Vasut <[email protected]> - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77980-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi b/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi index 2901d0e7b57..2a4bd2e5fdf 100644 --- a/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2019 Cogent Embedded, Inc. */ -#include "r8a77980-u-boot.dtsi" - / { aliases { spi0 = &rpc; @@ -14,9 +12,7 @@ }; &rpc { - num-cs = <1>; status = "okay"; - spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi index a52c5de4ddf..91b9a20a042 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -#include "r8a77990-u-boot.dtsi" - / { sysinfo { compatible = "renesas,rcar-sysinfo"; @@ -33,11 +31,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi deleted file mode 100644 index d9dcce00e90..00000000000 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A77990 SoC - * - * Copyright (C) 2018 Marek Vasut <[email protected]> - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77990-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dtsi b/arch/arm/dts/r8a77995-draak-u-boot.dtsi index 19d19542efd..d0dd06f08bf 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-draak-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -#include "r8a77995-u-boot.dtsi" - / { sysinfo { compatible = "renesas,rcar-sysinfo"; @@ -22,8 +20,3 @@ bootph-all; }; }; - -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi deleted file mode 100644 index 85fccbabfb3..00000000000 --- a/arch/arm/dts/r8a77995-u-boot.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A77995 SoC - * - * Copyright (C) 2018 Marek Vasut <[email protected]> - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi b/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi index 3b8a017cb41..c1d92d2d9bb 100644 --- a/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi +++ b/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a779a0-u-boot.dtsi" - / { aliases { spi0 = &rpc; @@ -16,8 +14,6 @@ &rpc { #address-cells = <1>; #size-cells = <0>; - num-cs = <1>; - spi-max-frequency = <50000000>; status = "okay"; flash@0 { diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi deleted file mode 100644 index a4e75a67dc3..00000000000 --- a/arch/arm/dts/r8a779a0-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A779A0 SoC - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a779a0-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; - clocks = <&cpg CPG_MOD 629>; - bank-width = <2>; - num-cs = <1>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index bd6a3d0713f..5a2d1fe66ce 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -93,11 +93,6 @@ bootph-all; }; -&rpc { - bank-width = <2>; - num-cs = <1>; -}; - &soc { apmu@e6170000 { /* Remoteproc */ compatible = "renesas,r8a779g0-cr52"; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi index c04d2ae2be4..f9c419b11d7 100644 --- a/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi +++ b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi @@ -5,36 +5,16 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ -#include "r8a779h0-u-boot.dtsi" - / { aliases { spi0 = &rpc; }; }; -&pfc { - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; -}; - &rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <40000000>; status = "disabled"; flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi b/arch/arm/dts/r8a779h0-u-boot.dtsi deleted file mode 100644 index 40e070be9a8..00000000000 --- a/arch/arm/dts/r8a779h0-u-boot.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -&rpc { - bank-width = <2>; - num-cs = <1>; -}; diff --git a/arch/arm/dts/r8a779md-geist-u-boot.dtsi b/arch/arm/dts/r8a779md-geist-u-boot.dtsi new file mode 100644 index 00000000000..fbda218002a --- /dev/null +++ b/arch/arm/dts/r8a779md-geist-u-boot.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot for the Geist board with r8a779md + * + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&pfc { + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; +}; + +/* + * SPI access works only if TFA is built with RCAR_RPC_HYPERFLASH_LOCKED=0 + * and SPD=none , otherwise the RPC access is blocked either by TFA in case + * the former is set to 1, or by OPTEE-OS in case SPD=opteed . + */ +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <40000000>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; +}; + +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; diff --git a/arch/arm/dts/r8a779md-geist.dts b/arch/arm/dts/r8a779md-geist.dts new file mode 100644 index 00000000000..2921aba92a5 --- /dev/null +++ b/arch/arm/dts/r8a779md-geist.dts @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Geist board with R-Car M3Le + * + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "r8a779md.dtsi" + +/ { + model = "Renesas Geist board based on r8a779md"; + compatible = "renesas,geist", "renesas,r8a779md", "renesas,r8a77965"; + + aliases { + serial0 = &scif2; + serial1 = &hscif1; + ethernet0 = &avb; + mmc0 = &sdhi2; + mmc1 = &sdhi0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2500/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + + brightness-levels = <256 128 64 16 8 4 0>; + default-brightness-level = <6>; + + power-supply = <®_12v>; + enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + }; + + cvbs-in { + compatible = "composite-video-connector"; + label = "CVBS IN"; + + port { + cvbs_con: endpoint { + remote-endpoint = <&adv7482_ain7>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + label = "HDMI IN"; + type = "a"; + + port { + hdmi_in_con: endpoint { + remote-endpoint = <&adv7482_hdmi>; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + linux,code = <KEY_1>; + label = "SW4-1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + linux,code = <KEY_2>; + label = "SW4-2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + label = "SW4-3"; + wakeup-source; + debounce-interval = <20>; + }; + + key-4 { + gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_4>; + label = "SW4-4"; + wakeup-source; + debounce-interval = <20>; + }; + + key-a { + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_A>; + label = "TSW0"; + wakeup-source; + debounce-interval = <20>; + }; + + key-b { + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + linux,code = <KEY_B>; + label = "TSW1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-c { + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; + linux,code = <KEY_C>; + label = "TSW2"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "fixed-12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + sound_card: sound { + compatible = "audio-graph-card"; + + label = "rcar-sound"; + dais = <&rsnd_port0>; /* AK4619 Audio Codec */ + }; + + x12_clk: x12-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + /* External DU dot clocks */ + x21_clk: x21-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x22_clk: x22-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x23_clk: x23-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + x3013_clk: x3013-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7482_txa>; + }; + }; + }; +}; + +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + /* Please only enable hscif1 or scif1 */ + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + ak4619: codec@10 { + compatible = "asahi-kasei,ak4619"; + reg = <0x10>; + clocks = <&rcar_sound 3>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + ak4619_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + }; + }; + }; + + /* Pin-to-pin, register map, and control compatible with CS2000 and CS2200 */ + cs2500: clock-controller@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2500", "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2500>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + versaclock3: clock-controller@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x3013_clk>; + assigned-clocks = <&versaclock3 4>, <&versaclock3 5>; + assigned-clock-rates = <100000000>, <100000000>; + }; + + versaclock5: clock-controller@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x23_clk>; + clock-names = "xin"; + }; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70 0x71 0x72 0x73 0x74 0x75 + 0x60 0x61 0x62 0x63 0x64 0x65>; + reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", + "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; + + interrupts-extended = <&gpio6 30 IRQ_TYPE_LEVEL_LOW>, + <&gpio6 31 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "intrq1", "intrq2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; + }; + + port@a { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + + csa_vdd: adc@7c { + compatible = "maxim,max9611"; + reg = <0x7c>; + + shunt-resistor-micro-ohms = <5000>; + }; + + csa_dvfs: adc@7f { + compatible = "maxim,max9611"; + reg = <0x7f>; + + shunt-resistor-micro-ohms = <5000>; + }; +}; + +&i2c_dvfs { + status = "okay"; + + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; + status = "disabled"; +}; + +&pciec0 { + clocks = <&cpg CPG_MOD 319>, <&versaclock3 4>; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + + keys_pins: keys { + pins = "GP_5_17", "GP_5_20", "GP_5_22"; + bias-pull-up; + }; + + pwm1_pins: pwm1 { + groups = "pwm1_a"; + function = "pwm1"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_a", "scif1_ctrl"; + function = "scif1"; + }; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + function = "sdhi2"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + function = "audio_clk"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <12288000 11289600>; + + status = "okay"; + + /* update <audio_clk_b> to <cs2500> */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2500>, + <&audio_clk_c>, + <&cpg CPG_MOD 922>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + rsnd_port0: port@0 { + reg = <0>; + + rsnd_endpoint0: endpoint { + remote-endpoint = <&ak4619_endpoint>; + dai-format = "left_j"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + playback = <&ssi0>, <&src0>, <&dvc0>; + capture = <&ssi1>, <&src1>, <&dvc1>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + /* Please only enable hscif1 or scif1 */ + /* status = "okay"; */ +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + fixed-emmc-driver-type = <1>; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&usb_extal_clk { + clock-frequency = <50000000>; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; + +&vspb { + status = "okay"; +}; + +&vspi0 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a779md.dtsi b/arch/arm/dts/r8a779md.dtsi new file mode 100644 index 00000000000..f3065414134 --- /dev/null +++ b/arch/arm/dts/r8a779md.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car M3Le (R8A779MD) SoC + * + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +#include "r8a77965.dtsi" + +/ { + compatible = "renesas,r8a779md", "renesas,r8a77965"; +}; + +/delete-node/ &csi20; +/delete-node/ &drif00; +/delete-node/ &drif01; +/delete-node/ &drif10; +/delete-node/ &drif11; +/delete-node/ &drif20; +/delete-node/ &drif21; +/delete-node/ &drif30; +/delete-node/ &drif31; +/delete-node/ &du; +/delete-node/ &ehci1; +/delete-node/ &hdmi0; +/delete-node/ &lvds0; +/delete-node/ &mlp; +/delete-node/ &ohci1; +/delete-node/ &pciec1; +/delete-node/ &sata; +/delete-node/ &usb2_phy1; +/delete-node/ &usb3_peri0; +/delete-node/ &usb3_phy0; +/delete-node/ &vin0csi20; +/delete-node/ &vin1csi20; +/delete-node/ &vin2csi20; +/delete-node/ &vin3csi20; +/delete-node/ &vin4csi20; +/delete-node/ &vin5csi20; +/delete-node/ &vin6csi20; +/delete-node/ &vin7csi20; +/delete-node/ &xhci0; + +&sdhi0 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; +}; + +&sdhi1 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; +}; + +&sdhi2 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; +}; + +&sdhi3 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; + no-mmc; +}; diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi new file mode 100644 index 00000000000..2d4cdbac62a --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot for the Ironhide CM33 board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include "r8a78000-ironhide-u-boot.dtsi" + +/ { + model = "Renesas Ironhide board CM33 based on r8a78000"; + compatible = "renesas,ironhide-cm33", "renesas,r8a78000-cm33"; + + aliases { + serial1 = &hscif1; + }; + + chosen { + stdout-path = "serial1:1843200n8"; + }; + + /delete-node/ firmware; + /delete-node/ memory@40000000; + /delete-node/ memory@60600000; + /delete-node/ memory@1080000000; + /delete-node/ memory@1200000000; + /delete-node/ memory@1400000000; + /delete-node/ memory@1600000000; + /delete-node/ memory@1800000000; + /delete-node/ memory@1a00000000; + /delete-node/ memory@1c00000000; + /delete-node/ memory@1e00000000; + /delete-node/ reserved-memory; + + memory@b8400000 { + device_type = "memory"; + reg = <0x0 0xb8400000 0x0 0x00200000>; + }; + + dummy_clk_rclk: dummy-clk-rclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + dummy_clk_sasyncd4_rt: dummy-clk-sasyncd4-rt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16660000>; + }; + + ctl: syscon@5fffd000 { + compatible = "renesas,r8a78000-ctl", + "renesas,rcar-gen5-ctl", + "syscon"; + reg = <0 0x5fffd000 0 0xc4>; + }; + + watchdog@5fffd800 { + compatible = "renesas,r8a78000-wwdt", + "renesas,rcar-gen5-wwdt"; + clocks = <&dummy_clk_rclk>, <&dummy_clk_sasyncd4_rt>; + clock-names = "cnt", "bus"; + reg = <0 0x5fffd800 0 0x10>; + syscon = <&ctl>; + }; + + scp@c1340000 { + compatible = "renesas,r8a78000-rproc"; + reg = <0 0xc1340000 0 0x80000>; + }; +}; + +&cpg { + /delete-property/ firmware; +}; + +ð_pcs { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&mdlc_hscn { + /delete-property/ firmware; +}; + +&mdlc_pere { + /delete-property/ firmware; +}; + +&mmc0 { + status = "disabled"; +}; + +&mp_phy { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&pfc { + hscif1_pins: hscif1 { + groups = "hscif1_data", "hscif1_ctrl"; + function = "hscif1"; + }; +}; + +&rswitch3 { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&soc { + dma-ranges = <0 0x00000000 0 0xa0000000 0 0x20000000>; +}; + +&ufs0 { + /delete-property/ power-domains; +}; + +&ufs1 { + /delete-property/ power-domains; + status = "disabled"; +}; diff --git a/arch/arm/dts/r8a78000-ironhide-cm33.dts b/arch/arm/dts/r8a78000-ironhide-cm33.dts new file mode 100644 index 00000000000..79ad844165c --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-cm33.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Ironhide CM33 board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include "../../../dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts" diff --git a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi index 9c72f3e55f4..299716f96a4 100644 --- a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi @@ -5,4 +5,190 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include <dt-bindings/net/ti-dp83869.h> #include "r8a78000-u-boot.dtsi" + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &mmc0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&cpg { + firmware = <&scmi>; +}; + +ð_pcs { + phys = <&mp_phy 2 1>; + status = "okay"; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&mdlc_hscn { + firmware = <&scmi>; +}; + +&mdlc_pere { + firmware = <&scmi>; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-1 = <&mmc0_pins>; + pinctrl-names = "default", "state_uhs"; + + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + + status = "okay"; +}; + +&mp_phy { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + eth25g2_pins: eth25g2 { + groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; + function = "eth25g2"; + drive-strength = <24>; + }; + + ethes0_pins: ethes0 { + groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; + function = "ethes0"; + drive-strength = <24>; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + mmc0_pins: mmc0 { + groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; + function = "mmc0"; + drive-strength = <24>; + }; + + rsw3_pins: rsw3 { + groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; + function = "rsw3"; + drive-strength = <24>; + }; + + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rswitch3 { + pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * NOTE: Only port@4 is configured for R-Car X5H board. + * Other ports (0-3, 5-12) are currently unused or not + * connected. + */ + port@4 { + reg = <4>; + renesas,connect_to_xpcs; + phy-handle = <&dp83869_phy>; + phy-mode = "sgmii"; + phys = <ð_pcs 5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + dp83869_phy: ethernet-phy@2 { + reg = <2>; + ti,sgmii-interface; + ti,max-output-impedance; + ti,refclk-output-enable; + ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; + }; + }; + }; + }; +}; + +&ufs0 { + status = "okay"; +}; + +&ufs1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a78000-ironhide.dts b/arch/arm/dts/r8a78000-ironhide.dts deleted file mode 100644 index 601f2740b54..00000000000 --- a/arch/arm/dts/r8a78000-ironhide.dts +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the Ironhide board - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a78000.dtsi" -#include <dt-bindings/net/ti-dp83869.h> - -/ { - model = "Renesas Ironhide board based on r8a78000"; - compatible = "renesas,ironhide", "renesas,r8a78000"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - mmc0 = &mmc0; - serial0 = &hscif0; - }; - - chosen { - stdout-path = "serial0:1843200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x80000000>; - }; - - memory@1080000000 { - device_type = "memory"; - reg = <0x10 0x80000000 0x0 0x80000000>; - }; - - memory@1200000000 { - device_type = "memory"; - reg = <0x12 0x00000000 0x1 0x00000000>; - }; - - memory@1400000000 { - device_type = "memory"; - reg = <0x14 0x00000000 0x1 0x00000000>; - }; - - memory@1600000000 { - device_type = "memory"; - reg = <0x16 0x00000000 0x1 0x00000000>; - }; - - memory@1800000000 { - device_type = "memory"; - reg = <0x18 0x00000000 0x1 0x00000000>; - }; - - memory@1a00000000 { - device_type = "memory"; - reg = <0x1a 0x00000000 0x1 0x00000000>; - }; - - memory@1c00000000 { - device_type = "memory"; - reg = <0x1c 0x00000000 0x1 0x00000000>; - }; - - memory@1e00000000 { - device_type = "memory"; - reg = <0x1e 0x00000000 0x1 0x00000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&extal_clk { - clock-frequency = <16666600>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; -}; - -ð_pcs { - phys = <&mp_phy 2 1>; - status = "okay"; -}; - -&mmc0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-1 = <&mmc0_pins>; - pinctrl-names = "default", "state_uhs"; - - bus-width = <8>; - full-pwr-cycle-in-suspend; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - no-sd; - no-sdio; - non-removable; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - - status = "okay"; -}; - -&ufs0 { - status = "okay"; -}; - -&ufs1 { - status = "okay"; -}; - -&mp_phy { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - eth25g2_pins: eth25g2 { - groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; - function = "eth25g2"; - drive-strength = <24>; - }; - - ethes0_pins: ethes0 { - groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; - function = "ethes0"; - drive-strength = <24>; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; - function = "mmc0"; - drive-strength = <24>; - }; - - rsw3_pins: rsw3 { - groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; - function = "rsw3"; - drive-strength = <24>; - }; - - scif_clk_pins: scif-clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rswitch3 { - pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; - pinctrl-names = "default"; - status = "okay"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * NOTE: Only port@4 is configured for R-Car X5H board. - * Other ports (0-3, 5-12) are currently unused or not - * connected. - */ - port@4 { - reg = <4>; - renesas,connect_to_xpcs; - phy-handle = <&dp83869_phy>; - phy-mode = "sgmii"; - phys = <ð_pcs 5>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - dp83869_phy: ethernet-phy@2 { - reg = <2>; - ti,sgmii-interface; - ti,max-output-impedance; - ti,refclk-output-enable; - ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; - }; - }; - }; - }; -}; - -&scif_clk { - clock-frequency = <26000000>; -}; diff --git a/arch/arm/dts/r8a78000-u-boot.dtsi b/arch/arm/dts/r8a78000-u-boot.dtsi index 1bc73252430..df21a9e03a2 100644 --- a/arch/arm/dts/r8a78000-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-u-boot.dtsi @@ -5,9 +5,41 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include <dt-bindings/clock/r8a78000-clock-scmi.h> +#include <dt-bindings/power/r8a78000-power-scmi.h> +#include <dt-bindings/reset/r8a78000-reset-scmi.h> + / { - soc { - bootph-all; + firmware { + scmi: scmi { + compatible = "arm,scmi"; + arm,poll-transport; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 0>, <&mailbox 1>; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; + #address-cells = <1>; + #size-cells = <0>; + + protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; }; /* Placeholder clock until the clock provider is in place */ @@ -32,16 +64,12 @@ clk_stub_mmc: clk-stub-mmc { compatible = "renesas,compound-clock"; #clock-cells = <0>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>, - <&scmi_clk 1691>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_SDHI0>, + <&cpg SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN>; clock-names = "mdlc", "per"; }; }; -&cpg { - bootph-all; -}; - &extal_clk { bootph-all; }; @@ -50,90 +78,311 @@ bootph-all; }; -&gpio0 { - clocks = <&clk_stub_gpio>; +&prr { + bootph-all; }; -&gpio1 { - clocks = <&clk_stub_gpio>; -}; +&soc { + bootph-all; -&gpio2 { - clocks = <&clk_stub_gpio>; -}; + mailbox: mfis_mbox@18842000 { + compatible = "renesas,mfis-mbox"; + #mbox-cells = <1>; + reg = <0 0x18842004 0 0x8>; + interrupts = <GIC_SPI 4362 IRQ_TYPE_LEVEL_HIGH>; + }; -&gpio3 { - clocks = <&clk_stub_gpio>; -}; + pfc: pinctrl@c0400000 { + compatible = "renesas,pfc-r8a78000"; + reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, + <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, + <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, + <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, + <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, + <0 0xc9b00800 0 0x104>; + }; -&gpio4 { - clocks = <&clk_stub_gpio>; -}; + mmc0: mmc@c0880000 { + compatible = "renesas,rcar-gen5-sdhi"; + reg = <0 0xc0880000 0 0x2000>; + clock-names = "core"; + max-frequency = <200000000>; + clocks = <&clk_stub_mmc>; + status = "disabled"; + }; -&gpio5 { - clocks = <&clk_stub_gpio>; -}; + mdlc_pere: system-controller@c08f0000 { + compatible = "renesas,r8a78000-mdlc"; + reg = <0 0xc08f0000 0 0x1000>; + #power-domain-cells = <1>; + #reset-cells = <1>; + bootph-all; + }; -&gpio6 { - clocks = <&clk_stub_gpio>; -}; + ufs0: ufs@c0a80000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = <GIC_SPI 4284 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS0>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS0>; + resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS0>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; -&gpio7 { - clocks = <&clk_stub_gpio>; -}; + ufs1: ufs@c0a90000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = <GIC_SPI 4285 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS1>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS1>; + resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS1>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; -&gpio8 { - clocks = <&clk_stub_gpio>; -}; + scp: sram@c1000000 { + compatible = "arm,rcar-sram-ns", "mmio-sram"; + reg = <0x0 0xc1000000 0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc1000000 0x80000>; -&gpio9 { - clocks = <&clk_stub_gpio>; -}; + cpu_scp_lpri0: scp-shmem@60000 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61200 0x0100>; + }; -&gpio10 { - clocks = <&clk_stub_gpio>; -}; + cpu_scp_hpri0: scp-shmem@60300 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61300 0x100>; + }; + }; -&i2c0 { - clocks = <&clk_stub_i2c0>; -}; + cpg: clock-controller@c1320000 { + compatible = "renesas,r8a78000-cpg"; + reg = <0 0xc1320000 0 0x10000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <1>; + bootph-all; + }; -&i2c1 { - clocks = <&clk_stub_i2c1>; -}; + i2c0: i2c@c11d0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc11d0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_stub_i2c0>; + status = "disabled"; + }; -&i2c2 { - clocks = <&clk_stub_i2c1>; -}; + i2c1: i2c@c06c0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06c0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_stub_i2c1>; + status = "disabled"; + }; -&i2c3 { - clocks = <&clk_stub_i2c1>; -}; + gpio0: gpio@c1080110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 28>; + clocks = <&clk_stub_gpio>; + }; -&i2c4 { - clocks = <&clk_stub_i2c1>; -}; + gpio1: gpio@c1080910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 22>; + clocks = <&clk_stub_gpio>; + }; -&i2c5 { - clocks = <&clk_stub_i2c1>; -}; + gpio2: gpio@c1081110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1081110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 29>; + clocks = <&clk_stub_gpio>; + }; -&i2c6 { - clocks = <&clk_stub_i2c1>; -}; + gpio3: gpio@c0800110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 17>; + clocks = <&clk_stub_gpio>; + }; -&i2c7 { - clocks = <&clk_stub_i2c1>; -}; + gpio4: gpio@c0800910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 16>; + clocks = <&clk_stub_gpio>; + }; -&i2c8 { - clocks = <&clk_stub_i2c1>; -}; + gpio5: gpio@c0400110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 23>; + clocks = <&clk_stub_gpio>; + }; -&mmc0 { - clocks = <&clk_stub_mmc>; -}; + gpio6: gpio@c0400910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 31>; + clocks = <&clk_stub_gpio>; + }; -&prr { - bootph-all; + gpio7: gpio@c0401110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 31>; + clocks = <&clk_stub_gpio>; + }; + + gpio8: gpio@c0401910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 32>; + gpio-reserved-ranges = <16 10>; + clocks = <&clk_stub_gpio>; + }; + + gpio9: gpio@c9b00110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + clocks = <&clk_stub_gpio>; + }; + + gpio10: gpio@c9b00910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 14>; + clocks = <&clk_stub_gpio>; + }; + + mp_phy: mp_phy@c9a00000 { + compatible = "renesas,r8a78000-multi-protocol-phy"; + reg = <0 0xc9a00000 0 0x100000>; + #phy-cells = <2>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_MPPHY01>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY11>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY21>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY31>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY02>; + clock-names = "mpphy01", "mpphy11", "mpphy21", + "mpphy31", "mpphy02"; + power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP0>, + <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP1>, + <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP2>, + <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP3>; + resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY01>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY11>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY21>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY31>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY02>; + status = "disabled"; + }; + + rswitch3: ethernet@c9bc0000 { + compatible = "renesas,r8a78000-ether-switch3", + "renesas,etherswitch"; + reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; + reg-names = "base", "secure_base"; + power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_RSW>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_RSW3>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSN>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3AES>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3MFWD>; + clock-names = "rsw3", "rsw3tsn", "rsw3aes", + "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", + "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", + "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; + status = "disabled"; + }; + + eth_pcs: phy@c9c50000 { + compatible = "renesas,r8a78000-ether-pcs"; + reg = <0 0xc9c50000 0 0x4000>; + #phy-cells = <1>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_XPCS0>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS1>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS2>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS3>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS4>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS5>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS6>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS7>; + clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS0>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS1>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS2>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS3>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS4>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS5>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS6>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS7>; + reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + status = "disabled"; + }; + + mdlc_hscn: system-controller@c9c90000 { + compatible = "renesas,r8a78000-mdlc"; + reg = <0 0xc9c90000 0 0x1000>; + #power-domain-cells = <1>; + #reset-cells = <1>; + bootph-all; + }; }; diff --git a/arch/arm/dts/r8a78000.dtsi b/arch/arm/dts/r8a78000.dtsi deleted file mode 100644 index 89c2881fa94..00000000000 --- a/arch/arm/dts/r8a78000.dtsi +++ /dev/null @@ -1,1164 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car X5H (R8A78000) SoC - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -#include <dt-bindings/clock/r8a78000-clock-scmi.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/r8a78000-power-scmi.h> -#include <dt-bindings/reset/r8a78000-reset-scmi.h> - -/ { - compatible = "renesas,r8a78000"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a720_0>; - }; - core1 { - cpu = <&a720_1>; - }; - core2 { - cpu = <&a720_2>; - }; - core3 { - cpu = <&a720_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&a720_4>; - }; - core1 { - cpu = <&a720_5>; - }; - core2 { - cpu = <&a720_6>; - }; - core3 { - cpu = <&a720_7>; - }; - }; - - cluster2 { - core0 { - cpu = <&a720_8>; - }; - core1 { - cpu = <&a720_9>; - }; - core2 { - cpu = <&a720_10>; - }; - core3 { - cpu = <&a720_11>; - }; - }; - - cluster3 { - core0 { - cpu = <&a720_12>; - }; - core1 { - cpu = <&a720_13>; - }; - core2 { - cpu = <&a720_14>; - }; - core3 { - cpu = <&a720_15>; - }; - }; - - cluster4 { - core0 { - cpu = <&a720_16>; - }; - core1 { - cpu = <&a720_17>; - }; - core2 { - cpu = <&a720_18>; - }; - core3 { - cpu = <&a720_19>; - }; - }; - - cluster5 { - core0 { - cpu = <&a720_20>; - }; - core1 { - cpu = <&a720_21>; - }; - core2 { - cpu = <&a720_22>; - }; - core3 { - cpu = <&a720_23>; - }; - }; - - cluster6 { - core0 { - cpu = <&a720_24>; - }; - core1 { - cpu = <&a720_25>; - }; - core2 { - cpu = <&a720_26>; - }; - core3 { - cpu = <&a720_27>; - }; - }; - - cluster7 { - core0 { - cpu = <&a720_28>; - }; - core1 { - cpu = <&a720_29>; - }; - core2 { - cpu = <&a720_30>; - }; - core3 { - cpu = <&a720_31>; - }; - }; - }; - - a720_0: cpu@0 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x0>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_0>; - }; - - a720_1: cpu@100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_1>; - }; - - a720_2: cpu@200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_2>; - }; - - a720_3: cpu@300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_3>; - }; - - a720_4: cpu@10000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_4>; - }; - - a720_5: cpu@10100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_5>; - }; - - a720_6: cpu@10200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_6>; - }; - - a720_7: cpu@10300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_7>; - }; - - a720_8: cpu@20000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_8>; - }; - - a720_9: cpu@20100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_9>; - }; - - a720_10: cpu@20200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_10>; - }; - - a720_11: cpu@20300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_11>; - }; - - a720_12: cpu@30000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_12>; - }; - - a720_13: cpu@30100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_13>; - }; - - a720_14: cpu@30200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_14>; - }; - - a720_15: cpu@30300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_15>; - }; - - a720_16: cpu@40000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_16>; - }; - - a720_17: cpu@40100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_17>; - }; - - a720_18: cpu@40200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_18>; - }; - - a720_19: cpu@40300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_19>; - }; - - a720_20: cpu@50000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_20>; - }; - - a720_21: cpu@50100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_21>; - }; - - a720_22: cpu@50200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_22>; - }; - - a720_23: cpu@50300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_23>; - }; - - a720_24: cpu@60000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_24>; - }; - - a720_25: cpu@60100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_25>; - }; - - a720_26: cpu@60200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_26>; - }; - - a720_27: cpu@60300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_27>; - }; - - a720_28: cpu@70000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_28>; - }; - - a720_29: cpu@70100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_29>; - }; - - a720_30: cpu@70200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_30>; - }; - - a720_31: cpu@70300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_31>; - }; - - L2_CA720_0: cache-controller-200 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_1: cache-controller-201 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_2: cache-controller-202 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_3: cache-controller-203 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_4: cache-controller-204 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_5: cache-controller-205 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_6: cache-controller-206 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_7: cache-controller-207 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_8: cache-controller-208 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_9: cache-controller-209 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_10: cache-controller-210 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_11: cache-controller-211 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_12: cache-controller-212 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_13: cache-controller-213 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_14: cache-controller-214 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_15: cache-controller-215 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_16: cache-controller-216 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_17: cache-controller-217 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_18: cache-controller-218 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_19: cache-controller-219 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_20: cache-controller-220 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_21: cache-controller-221 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_22: cache-controller-222 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_23: cache-controller-223 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_24: cache-controller-224 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_25: cache-controller-225 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_26: cache-controller-226 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_27: cache-controller-227 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_28: cache-controller-228 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_29: cache-controller-229 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_30: cache-controller-230 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_31: cache-controller-231 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L3_CA720_0: cache-controller-30 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_1: cache-controller-31 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_2: cache-controller-32 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_3: cache-controller-33 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_4: cache-controller-34 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_5: cache-controller-35 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_6: cache-controller-36 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_7: cache-controller-37 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - }; - - /* - * In the early phase, there is no clock control support, - * so assume that the clocks are enabled by default. - * Therefore, dummy clocks are used. - */ - dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <66666000>; - }; - - dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <266660000>; - }; - - extal_clk: extal-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* clock-frequency must be set on board */ - }; - - extalr_clk: extalr-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* clock-frequency must be set on board */ - }; - - firmware { - scmi { - compatible = "arm,scmi"; - arm,poll-transport; - mbox-names = "tx", "rx"; - mboxes = <&mailbox 0>, <&mailbox 1>; - shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_devpd: protocol@11 { - reg = <0x11>; - #power-domain-cells = <1>; - }; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; /* optional */ - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mailbox: mfis_mbox@18842000 { - compatible = "renesas,mfis-mbox"; - #mbox-cells = <1>; - reg = <0 0x18842004 0 0x8>; - interrupts = <GIC_SPI 4362 IRQ_TYPE_LEVEL_HIGH>; - }; - - prr: chipid@189e0044 { - compatible = "renesas,prr"; - reg = <0 0x189e0044 0 4>; - }; - - /* Application Processors manage View-1 of a GIC-720AE */ - gic: interrupt-controller@39000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x39000000 0 0x10000>, - <0 0x39080000 0 0x800000>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - }; - - pfc: pinctrl@c0400000 { - compatible = "renesas,pfc-r8a78000"; - reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, - <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, - <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, - <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, - <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, - <0 0xc9b00800 0 0x104>; - }; - - scif0: serial@c0700000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0700000 0 0x40>; - interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif1: serial@c0704000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0704000 0 0x40>; - interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif3: serial@c0708000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0708000 0 0x40>; - interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif4: serial@c070c000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc070c000 0 0x40>; - interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - mmc0: mmc@c0880000 { - compatible = "renesas,rcar-gen5-sdhi"; - reg = <0 0xc0880000 0 0x2000>; - clock-names = "core"; - max-frequency = <200000000>; - status = "disabled"; - }; - - ufs0: ufs@c0a80000 { - compatible = "renesas,r8a78000-ufs"; - reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; - reg-names = "hcr", "phy"; - interrupts = <GIC_SPI 4284 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS0>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS0>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS0>; - freq-table-hz = <38400000 38400000>; - status = "disabled"; - }; - - ufs1: ufs@c0a90000 { - compatible = "renesas,r8a78000-ufs"; - reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; - reg-names = "hcr", "phy"; - interrupts = <GIC_SPI 4285 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS1>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS1>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS1>; - freq-table-hz = <38400000 38400000>; - status = "disabled"; - }; - - scp: sram@c1000000 { - compatible = "arm,rcar-sram-ns", "mmio-sram"; - reg = <0x0 0xc1000000 0x0 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xc1000000 0x80000>; - - cpu_scp_lpri0: scp-shmem@60000 { - compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; - reg = <0x61200 0x0100>; - }; - - cpu_scp_hpri0: scp-shmem@60300 { - compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; - reg = <0x61300 0x100>; - }; - }; - - cpg: clock-controller@c64f0000 { - compatible = "renesas,r8a78000-cpg-mssr"; - reg = <0 0xc64f0000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - hscif0: serial@c0710000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0710000 0 0x60>; - interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif1: serial@c0714000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0714000 0 0x60>; - interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif2: serial@c0718000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0718000 0 0x60>; - interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif3: serial@c071c000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc071c000 0 0x60>; - interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - i2c0: i2c@c11d0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc11d0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@c06c0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06c0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@c06c8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06c8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@c06d0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06d0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@c06d8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06d8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@c06e0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06e0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@c06e8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06e8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@c06f0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06f0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@c06f8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06f8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gpio0: gpio@c1080110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1080110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 28>; - }; - - gpio1: gpio@c1080910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1080910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 22>; - }; - - gpio2: gpio@c1081110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1081110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 29>; - }; - - gpio3: gpio@c0800110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0800110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - }; - - gpio4: gpio@c0800910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0800910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 16>; - }; - - gpio5: gpio@c0400110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0400110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 23>; - }; - - gpio6: gpio@c0400910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0400910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 31>; - }; - - gpio7: gpio@c0401110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0401110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 31>; - }; - - gpio8: gpio@c0401910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0401910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 256 32>; - gpio-reserved-ranges = <16 10>; - }; - - gpio9: gpio@c9b00110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc9b00110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 288 17>; - }; - - gpio10: gpio@c9b00910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc9b00910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 320 14>; - }; - - mp_phy: mp_phy@c9a00000 { - compatible = "renesas,r8a78000-multi-protocol-phy"; - reg = <0 0xc9a00000 0 0x100000>; - #phy-cells = <2>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY01>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY11>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY21>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY31>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY02>; - clock-names = "mpphy01", "mpphy11", "mpphy21", - "mpphy31", "mpphy02"; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP0>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP1>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP2>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP3>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY01>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY11>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY21>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY31>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY02>; - status = "disabled"; - }; - - rswitch3: ethernet@c9bc0000 { - compatible = "renesas,r8a78000-ether-switch3", - "renesas,etherswitch"; - reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; - reg-names = "base", "secure_base"; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_RSW>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSN>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3AES>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3MFWD>; - clock-names = "rsw3", "rsw3tsn", "rsw3aes", - "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", - "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", - "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; - status = "disabled"; - }; - - eth_pcs: phy@c9c50000 { - compatible = "renesas,r8a78000-ether-pcs"; - reg = <0 0xc9c50000 0 0x4000>; - #phy-cells = <1>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS0>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS1>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS2>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS4>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS5>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS6>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS7>; - clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", - "xpcs4", "xpcs5", "xpcs6", "xpcs7"; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS0>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS1>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS2>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS3>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS4>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS5>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS6>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS7>; - reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", - "xpcs4", "xpcs5", "xpcs6", "xpcs7"; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; - }; -}; diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts deleted file mode 100644 index 93291d78734..00000000000 --- a/arch/arm/dts/rk3128-evb.dts +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rk3128.dtsi" - -/ { - model = "Rockchip RK3128 Evaluation board"; - compatible = "rockchip,rk3128-evb", "rockchip,rk3128"; - - chosen { - stdout-path = &uart2; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_host: vcc5v0-host-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&emmc { - fifo-mode; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&pinctrl { - usb_otg { - otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi deleted file mode 100644 index 3253c640341..00000000000 --- a/arch/arm/dts/rk3128.dtsi +++ /dev/null @@ -1,780 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3128-cru.h> - -/ { - compatible = "rockchip,rk3128"; - rockchip,sram = <&sram>; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - spi0 = &spi0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3128-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - }; - - cpu_axi_bus: cpu_axi_bus { - compatible = "rockchip,cpu_axi_bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - qos { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - crypto { - reg = <0x10128080 0x20>; - }; - - core { - reg = <0x1012a000 0x20>; - }; - - peri { - reg = <0x1012c000 0x20>; - }; - - gpu { - reg = <0x1012d000 0x20>; - }; - - vpu { - reg = <0x1012e000 0x20>; - }; - - rga { - reg = <0x1012f000 0x20>; - }; - ebc { - reg = <0x1012f080 0x20>; - }; - - iep { - reg = <0x1012f100 0x20>; - }; - - lcdc { - reg = <0x1012f180 0x20>; - rockchip,priority = <3 3>; - }; - - vip { - reg = <0x1012f200 0x20>; - rockchip,priority = <3 3>; - }; - }; - - msch { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - msch@10128000 { - reg = <0x10128000 0x20>; - rockchip,read-latency = <0x3f>; - }; - }; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - migrate = <0x84000005>; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges; - - pdma: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - arm,pl330-broken-no-flushp;//2 - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin12m: xin12m { - compatible = "fixed-clock"; - clock-frequency = <12000000>; - clock-output-names = "xin12m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - timer@20044000 { - compatible = "arm,armv7-timer"; - reg = <0x20044000 0xb8>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - rockchip,broadcast = <1>; - }; - - watchdog: watchdog@2004c000 { - compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; - reg = <0x2004c000 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - rockchip,irq = <1>; - rockchip,timeout = <60>; - rockchip,atboot = <1>; - rockchip,debug = <0>; - }; - - reset: reset@20000110 { - compatible = "rockchip,reset"; - reg = <0x20000110 0x24>; - #reset-cells = <1>; - }; - - nandc: nand-controller@10500000 { - compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; - reg = <0x10500000 0x4000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; - clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; - clock-names = "ahb", "nfc"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3128-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - dmas = <&pdma 2>, <&pdma 3>; - #dma-cells = <2>; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - dmas = <&pdma 4>, <&pdma 5>; - #dma-cells = <2>; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - dmas = <&pdma 6>, <&pdma 7>; - #dma-cells = <2>; - }; - - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050000 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050010 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; - }; - - sram: sram@10080400 { - compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; - reg = <0x10080400 0x1C00>; - map-exec; - map-cacheable; - }; - - pmu: syscon@100a0000 { - compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; - reg = <0x100a0000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - reg = <0x10139000 0x1000>, - <0x1013a000 0x1000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = <GIC_PPI 9 0xf04>; - }; - - u2phy: usb2phy { - compatible = "rockchip,rk3128-usb2phy"; - reg = <0x017c 0x0c>; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "usb480m_phy"; - status = "disabled"; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - status = "disabled"; - }; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host_ehci: usb@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x20000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host_ohci: usb@101e0000 { - compatible = "generic-ohci"; - reg = <0x101e0000 0x20000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - sdmmc: mmc@10214000 { - compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - max-frequency = <150000000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - bus-width = <4>; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x1021c000 0x4000>; - max-frequency = <150000000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - default-sample-phase = <158>; - num-slots = <1>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - i2c0: i2c@20072000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <20072000 0x1000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - }; - - i2c2: i2c@2005a000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - }; - - i2c3: i2c@2005e000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005e000 0x1000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - }; - - spi0: spi@20074000 { - compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; - reg = <0x20074000 0x1000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; - rockchip,spi-src-clk = <0>; - num-cs = <2>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&pdma 8>, <&pdma 9>; - #dma-cells = <2>; - dma-names = "tx", "rx"; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3128-grf", "syscon"; - reg = <0x20008000 0x1000>; - }; - - pinctrl: pinctrl@20008000 { - compatible = "rockchip,rk3128-pinctrl"; - reg = <0x20008000 0xA8>, - <0x200080A8 0x4C>, - <0x20008118 0x20>, - <0x20008100 0x04>; - reg-names = "base", "mux", "pull", "drv"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20088000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20088000 0x100>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, - <1 RK_PD1 2 &pcfg_pull_none>, - <1 RK_PD2 2 &pcfg_pull_none>, - <1 RK_PD3 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>, - <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD6 2 &pcfg_pull_none>, - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - nandc{ - nandc_ale:nandc-ale { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_cle:nandc-cle { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_wrn:nandc-wrn { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_rdn:nandc-rdn { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_rdy:nandc-rdy { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_cs0:nandc-cs0 { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_data: nandc-data { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>, - <0 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>, - <2 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; - }; - - sdmmc_wp: sdmmc-wp { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; - }; - - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, - <1 RK_PC3 1 &pcfg_pull_up>, - <1 RK_PC4 1 &pcfg_pull_up>, - <1 RK_PC5 1 &pcfg_pull_up>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, - <2 RK_PC5 3 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_txd_mux0:spi0-txd-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_rxd_mux0:spi0-rxd-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_clk_mux0:spi0-clk-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_cs0_mux0:spi0-cs0-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_cs1_mux0:spi0-cs1-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - }; - - }; -}; diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts deleted file mode 100644 index 797476e8bef..00000000000 --- a/arch/arm/dts/rk3229-evb.dts +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include "rk3229.dtsi" - -/ { - model = "Rockchip RK3229 Evaluation board"; - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - - aliases { - mmc0 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - ext_gmac: ext_gmac { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vccio_1v8>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vccio_1v8: vccio-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vccio_3v3: vccio-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - gpio_keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power_key: power-key { - label = "GPIO Key Power"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - debounce-interval = <100>; - wakeup-source; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_3v3>; - vccio2-supply = <&vccio_1v8>; - vccio4-supply = <&vccio_3v3>; -}; - -&pinctrl { - keys { - pwr_key: pwr-key { - rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_ehci { - status = "okay"; -}; - -&usb_host2_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3229.dtsi b/arch/arm/dts/rk3229.dtsi deleted file mode 100644 index c340fb30e77..00000000000 --- a/arch/arm/dts/rk3229.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include "rk322x.dtsi" - -/ { - compatible = "rockchip,rk3229"; - - /delete-node/ opp-table0; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1325000>; - }; - opp-1392000000 { - opp-hz = /bits/ 64 <1392000000>; - opp-microvolt = <1375000>; - }; - opp-1464000000 { - opp-hz = /bits/ 64 <1464000000>; - opp-microvolt = <1400000>; - }; - }; -}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi deleted file mode 100644 index 8eed9e3a92e..00000000000 --- a/arch/arm/dts/rk322x.dtsi +++ /dev/null @@ -1,1293 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3228-cru.h> -#include <dt-bindings/thermal/thermal.h> -#include <dt-bindings/power/rk3228-power.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &spi0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - enable-method = "psci"; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - i2s1: i2s1@100b0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100b0000 0x4000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - dmas = <&pdma 14>, <&pdma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s0: i2s0@100c0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100c0000 0x4000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - dmas = <&pdma 11>, <&pdma 12>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spdif: spdif@100d0000 { - compatible = "rockchip,rk3228-spdif"; - reg = <0x100d0000 0x1000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; - clock-names = "mclk", "hclk"; - dmas = <&pdma 10>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - i2s2: i2s2@100e0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100e0000 0x4000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - grf: syscon@11000000 { - compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; - reg = <0x11000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rk3228-io-voltage-domain"; - status = "disabled"; - }; - - power: power-controller { - compatible = "rockchip,rk3228-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3228_PD_VIO { - reg = <RK3228_PD_VIO>; - clocks = <&cru ACLK_HDCP>, - <&cru SCLK_HDCP>, - <&cru ACLK_IEP>, - <&cru HCLK_IEP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>, - <&cru SCLK_RGA>; - pm_qos = <&qos_hdcp>, - <&qos_iep>, - <&qos_rga_r>, - <&qos_rga_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VOP { - reg = <RK3228_PD_VOP>; - clocks =<&cru ACLK_VOP>, - <&cru DCLK_VOP>, - <&cru HCLK_VOP>; - pm_qos = <&qos_vop>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VPU { - reg = <RK3228_PD_VPU>; - clocks = <&cru ACLK_VPU>, - <&cru HCLK_VPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_RKVDEC { - reg = <RK3228_PD_RKVDEC>; - clocks = <&cru ACLK_RKVDEC>, - <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - pm_qos = <&qos_rkvdec_r>, - <&qos_rkvdec_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_GPU { - reg = <RK3228_PD_GPU>; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; - - u2phy0: usb2phy@760 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0760 0x0c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - #clock-cells = <0>; - status = "disabled"; - - u2phy0_otg: otg-port { - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0_host: host-port { - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - u2phy1: usb2phy@800 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0800 0x0c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - #clock-cells = <0>; - status = "disabled"; - - u2phy1_otg: otg-port { - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy1_host: host-port { - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - efuse: efuse@11040000 { - compatible = "rockchip,rk3228-efuse"; - reg = <0x11040000 0x20>; - clocks = <&cru PCLK_EFUSE_256>; - clock-names = "pclk_efuse"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x7 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - spi0: spi@11090000 { - compatible = "rockchip,rk3228-spi"; - reg = <0x11090000 0x1000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; - status = "disabled"; - }; - - wdt: watchdog@110a0000 { - compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; - reg = <0x110a0000 0x100>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_CPU>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - <&cru PLL_GPLL>, <&cru ARMCLK>, - <&cru PLL_CPLL>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>; - assigned-clock-rates = - <594000000>, <816000000>, - <500000000>, <150000000>, - <150000000>, <75000000>, - <150000000>, <150000000>, - <75000000>; - }; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <32768>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - hdmi_phy: hdmi-phy@12030000 { - compatible = "rockchip,rk3228-hdmi-phy"; - reg = <0x12030000 0x10000>; - clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - #clock-cells = <0>; - clock-output-names = "hdmiphy_phy"; - #phy-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@20000000 { - compatible = "rockchip,rk3228-mali", "arm,mali-400"; - reg = <0x20000000 0x10000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - power-domains = <&power RK3228_PD_GPU>; - resets = <&cru SRST_GPU_A>; - status = "disabled"; - }; - - vpu: video-codec@20020000 { - compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; - reg = <0x20020000 0x800>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3228_PD_VPU>; - }; - - vpu_mmu: iommu@20020800 { - compatible = "rockchip,iommu"; - reg = <0x20020800 0x100>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VPU>; - #iommu-cells = <0>; - }; - - vdec: video-codec@20030000 { - compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; - reg = <0x20030000 0x480>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; - assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <300000000>, <300000000>; - iommus = <&vdec_mmu>; - power-domains = <&power RK3228_PD_RKVDEC>; - }; - - vdec_mmu: iommu@20030480 { - compatible = "rockchip,iommu"; - reg = <0x20030480 0x40>, <0x200304c0 0x40>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_RKVDEC>; - #iommu-cells = <0>; - }; - - vop: vop@20050000 { - compatible = "rockchip,rk3228-vop"; - reg = <0x20050000 0x1ffc>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - power-domains = <&power RK3228_PD_VOP>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@20053f00 { - compatible = "rockchip,iommu"; - reg = <0x20053f00 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VOP>; - #iommu-cells = <0>; - status = "disabled"; - }; - - rga: rga@20060000 { - compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; - reg = <0x20060000 0x1000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk", "hclk", "sclk"; - power-domains = <&power RK3228_PD_VIO>; - resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; - reset-names = "core", "axi", "ahb"; - }; - - iep_mmu: iommu@20070800 { - compatible = "rockchip,iommu"; - reg = <0x20070800 0x100>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@200a0000 { - compatible = "rockchip,rk3228-dw-hdmi"; - reg = <0x200a0000 0x20000>; - reg-io-width = <4>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - assigned-clocks = <&cru SCLK_HDMI_PHY>; - assigned-clock-parents = <&hdmi_phy>; - clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; - clock-names = "isfr", "iahb", "cec"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; - resets = <&cru SRST_HDMI_P>; - reset-names = "hdmi"; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - }; - - sdmmc: mmc@30000000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30000000 0x4000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "disabled"; - }; - - sdio: mmc@30010000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30010000 0x4000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; - status = "disabled"; - }; - - emmc: mmc@30020000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - rockchip,default-sample-phase = <158>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - usb_otg: usb@30040000 { - compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30040000 0x40000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ehci: usb@30080000 { - compatible = "generic-ehci"; - reg = <0x30080000 0x20000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@300a0000 { - compatible = "generic-ohci"; - reg = <0x300a0000 0x20000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@300c0000 { - compatible = "generic-ehci"; - reg = <0x300c0000 0x20000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@300e0000 { - compatible = "generic-ohci"; - reg = <0x300e0000 0x20000>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ehci: usb@30100000 { - compatible = "generic-ehci"; - reg = <0x30100000 0x20000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ohci: usb@30120000 { - compatible = "generic-ohci"; - reg = <0x30120000 0x20000>; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rk3228-gmac"; - reg = <0x30200000 0x10000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - qos_iep: qos@31030080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030080 0x20>; - }; - - qos_rga_w: qos@31030100 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030100 0x20>; - }; - - qos_hdcp: qos@31030180 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030180 0x20>; - }; - - qos_rga_r: qos@31030200 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030200 0x20>; - }; - - qos_vpu: qos@31040000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31040000 0x20>; - }; - - qos_gpu: qos@31050000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31050000 0x20>; - }; - - qos_vop: qos@31060000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31060000 0x20>; - }; - - qos_rkvdec_r: qos@31070000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070000 0x20>; - }; - - qos_rkvdec_w: qos@31070080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070080 0x20>; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, - <1 RK_PD1 2 &pcfg_pull_none>, - <1 RK_PD2 2 &pcfg_pull_none>, - <1 RK_PD3 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>, - <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD6 2 &pcfg_pull_none>, - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC5 2 &pcfg_pull_none>, - <2 RK_PC4 2 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - phy_pins: phy-pins { - rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, - <2 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, - <0 RK_PA7 2 &pcfg_pull_none>; - }; - - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, - <0 RK_PB1 1 &pcfg_pull_none>, - <0 RK_PB3 1 &pcfg_pull_none>, - <0 RK_PB4 1 &pcfg_pull_none>, - <0 RK_PB5 1 &pcfg_pull_none>, - <0 RK_PB6 1 &pcfg_pull_none>, - <1 RK_PA2 2 &pcfg_pull_none>, - <1 RK_PA4 2 &pcfg_pull_none>, - <1 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, - <2 RK_PD3 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - uart21_xfer: uart21-xfer { - rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index 018c9cc8d69..8db9495c6d4 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -12,7 +12,7 @@ }; chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci, &ufshc; }; dmc { @@ -81,6 +81,17 @@ bootph-some-ram; }; +#ifdef CONFIG_SPL_UFS_SUPPORT +&gpio4 { + /* This is specifically for GPIO4_D0, which is the only 1.2V capable + * pin on RK3576 available for use as the UFS device reset, thus + * &gpio4 is required for booting from UFS on RK3576. + */ + bootph-pre-ram; + bootph-some-ram; +}; +#endif + &ioc_grf { bootph-all; }; @@ -89,6 +100,11 @@ bootph-some-ram; }; +&pcfg_pull_down { + bootph-pre-ram; + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; @@ -172,6 +188,21 @@ bootph-pre-ram; }; +&ufshc { + bootph-pre-ram; + bootph-some-ram; +}; + +&ufs_refclk { + bootph-pre-ram; + bootph-some-ram; +}; + +&ufs_rstgpio { + bootph-pre-ram; + bootph-some-ram; +}; + &xin24m { bootph-all; }; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index e07b549c767..ddc177344eb 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -19,33 +19,6 @@ bootph-some-ram; }; -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m1_xfer>; - status = "okay"; - - usbc0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio3>; - interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - status = "okay"; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "sink"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>, - <PDO_VAR(5000, 20000, 5000)>; - }; - }; -}; - &saradc { bootph-pre-ram; vdd-microvolts = <1800000>; @@ -63,20 +36,6 @@ }; }; -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; +&usbc0 { status = "okay"; }; diff --git a/arch/arm/dts/rz-g2-beacon-u-boot.dtsi b/arch/arm/dts/rz-g2-beacon-u-boot.dtsi index 84416fceaff..97c4d4d292a 100644 --- a/arch/arm/dts/rz-g2-beacon-u-boot.dtsi +++ b/arch/arm/dts/rz-g2-beacon-u-boot.dtsi @@ -47,7 +47,6 @@ &rpc { pinctrl-0 = <&qspi_pins>; pinctrl-names = "default"; - num-cs = <1>; spi-max-frequency = <40000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi index 79494ecad90..600316205fc 100644 --- a/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi @@ -21,6 +21,13 @@ pinctrl1 = &pinctrl_z; }; + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + timeout-sec = <32>; + status = "okay"; + }; + binman: binman { multiple-images; }; @@ -103,7 +110,7 @@ }; &iwdg2 { - bootph-all; + status = "disabled"; }; /* pre-reloc probe = reserve video frame buffer in video_reserve() */ diff --git a/arch/arm/dts/t8103-j274-u-boot.dtsi b/arch/arm/dts/t8103-j274-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j274-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j274.dts b/arch/arm/dts/t8103-j274.dts deleted file mode 100644 index 9bc592bcdbf..00000000000 --- a/arch/arm/dts/t8103-j274.dts +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple Mac mini (M1, 2020) - * - * target-type: J274 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j274", "apple,t8103", "apple,arm-platform"; - model = "Apple Mac mini (M1, 2020)"; - - aliases { - ethernet0 = ðernet0; - }; -}; - -&wifi0 { - brcm,board-type = "apple,atlantisb"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Back-left"; -}; - -&typec1 { - label = "USB-C Back-right"; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ - -&port01 { - bus-range = <2 2>; -}; - -&port02 { - bus-range = <3 3>; - ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 10 18 00 00 00]; - }; -}; - -&i2c1 { - clock-frequency = <50000>; - - speaker_amp: codec@31 { - compatible = "ti,tas5770l", "ti,tas2770"; - reg = <0x31>; - reset-gpios = <&pinctrl_ap 181 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; -}; - -&i2c2 { - status = "okay"; - - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Mac mini integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - format = "left_j"; - tdm-slot-width = <32>; - mclk-fs = <64>; - - link0_cpu: cpu { - sound-dai = <&mca 0>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&speaker_amp>; - }; - }; - - simple-audio-card,dai-link@1 { - bitclock-inversion; - frame-inversion; - reg = <1>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link1_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link1_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j293-u-boot.dtsi b/arch/arm/dts/t8103-j293-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j293-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j293.dts b/arch/arm/dts/t8103-j293.dts deleted file mode 100644 index de1a21d97cd..00000000000 --- a/arch/arm/dts/t8103-j293.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple MacBook Pro (13-inch, M1, 2020) - * - * target-type: J293 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; - model = "Apple MacBook Pro (13-inch, M1, 2020)"; -}; - -&wifi0 { - brcm,board-type = "apple,honshu"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Left-back"; -}; - -&typec1 { - label = "USB-C Left-front"; -}; - -&spi3 { - status = "okay"; - - hid-transport@0 { - compatible = "apple,spi-hid-transport"; - reg = <0>; - spi-max-frequency = <8000000>; - /* - * cs-setup and cs-hold delays are derived from Apple's ADT - * Mac OS driver meta data secify 45 us for 'cs to clock' and - * 'clock to cs' delays. - */ - spi-cs-setup-delay-ns = <20000>; - spi-cs-hold-delay-ns = <20000>; - spi-cs-inactive-delay-ns = <250000>; - spien-gpios = <&pinctrl_ap 195 0>; - interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* - * Remove unused PCIe ports and disable the associated DARTs. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -&pcie0_dart_2 { - status = "disabled"; -}; - -/delete-node/ &port01; -/delete-node/ &port02; - -&i2c2 { - status = "okay"; - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "MacBook integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j313-u-boot.dtsi b/arch/arm/dts/t8103-j313-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j313-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j313.dts b/arch/arm/dts/t8103-j313.dts deleted file mode 100644 index 5efe8d7a63b..00000000000 --- a/arch/arm/dts/t8103-j313.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple MacBook Air (M1, 2020) - * - * target-type: J313 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j313", "apple,t8103", "apple,arm-platform"; - model = "Apple MacBook Air (M1, 2020)"; -}; - -&wifi0 { - brcm,board-type = "apple,shikoku"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Left-back"; -}; - -&typec1 { - label = "USB-C Left-front"; -}; - -&spi3 { - status = "okay"; - - hid-transport@0 { - compatible = "apple,spi-hid-transport"; - reg = <0>; - spi-max-frequency = <8000000>; - /* - * cs-setup and cs-hold delays are derived from Apple's ADT - * Mac OS driver meta data secify 45 us for 'cs to clock' and - * 'clock to cs' delays. - */ - spi-cs-setup-delay-ns = <20000>; - spi-cs-hold-delay-ns = <20000>; - spi-cs-inactive-delay-ns = <250000>; - spien-gpios = <&pinctrl_ap 195 0>; - interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* - * Remove unused PCIe ports and disable the associated DARTs. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -&pcie0_dart_2 { - status = "disabled"; -}; - -/delete-node/ &port01; -/delete-node/ &port02; - -&i2c3 { - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "MacBook integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j456-u-boot.dtsi b/arch/arm/dts/t8103-j456-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j456-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j456.dts b/arch/arm/dts/t8103-j456.dts deleted file mode 100644 index 8624168bdb7..00000000000 --- a/arch/arm/dts/t8103-j456.dts +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple iMac (24-inch, 4x USB-C, M1, 2020) - * - * target-type: J456 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j456", "apple,t8103", "apple,arm-platform"; - model = "Apple iMac (24-inch, 4x USB-C, M1, 2020)"; - - aliases { - ethernet0 = ðernet0; - }; -}; - -&wifi0 { - brcm,board-type = "apple,capri"; -}; - -&i2c0 { - hpm2: usb-pd@3b { - compatible = "apple,cd321x"; - reg = <0x3b>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - }; - - hpm3: usb-pd@3c { - compatible = "apple,cd321x"; - reg = <0x3c>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - }; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Back-right"; -}; - -&typec1 { - label = "USB-C Back-right-middle"; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ - -&port01 { - bus-range = <2 2>; -}; - -&port02 { - bus-range = <3 3>; - ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 10 18 00 00 00]; - }; -}; - -&i2c1 { - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "iMac integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j457-u-boot.dtsi b/arch/arm/dts/t8103-j457-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j457-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j457.dts b/arch/arm/dts/t8103-j457.dts deleted file mode 100644 index f3eec8d4729..00000000000 --- a/arch/arm/dts/t8103-j457.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple iMac (24-inch, 2x USB-C, M1, 2020) - * - * target-type: J457 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j457", "apple,t8103", "apple,arm-platform"; - model = "Apple iMac (24-inch, 2x USB-C, M1, 2020)"; - - aliases { - ethernet0 = ðernet0; - }; -}; - -&wifi0 { - brcm,board-type = "apple,santorini"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Back-right"; -}; - -&typec1 { - label = "USB-C Back-left"; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ - -&port02 { - bus-range = <3 3>; - ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 10 18 00 00 00]; - }; -}; - -/* - * Remove unused PCIe port and disable the associated DART. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -/delete-node/ &port01; - -&i2c1 { - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "iMac integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-jxxx.dtsi b/arch/arm/dts/t8103-jxxx.dtsi deleted file mode 100644 index b4bd8c4238a..00000000000 --- a/arch/arm/dts/t8103-jxxx.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple M1 Mac mini, MacBook Air/Pro, iMac 24" (M1, 2020/2021) - * - * This file contains parts common to all Apple M1 devices using the t8103. - * - * target-type: J274, J293, J313, J456, J457 - * - * Copyright The Asahi Linux Contributors - */ - -#include <dt-bindings/spmi/spmi.h> - -/ { - aliases { - serial0 = &serial0; - serial2 = &serial2; - wifi0 = &wifi0; - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - stdout-path = "serial0"; - - framebuffer0: framebuffer@0 { - compatible = "apple,simple-framebuffer", "simple-framebuffer"; - reg = <0 0 0 0>; /* To be filled by loader */ - /* Format properties will be added by loader */ - status = "disabled"; - }; - }; - - memory@800000000 { - device_type = "memory"; - reg = <0x8 0 0x2 0>; /* To be filled by loader */ - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - hpm0: usb-pd@38 { - compatible = "apple,cd321x"; - reg = <0x38>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - typec0: connector { - compatible = "usb-c-connector"; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - typec0_con_hs: endpoint { - remote-endpoint = <&typec0_usb_hs>; - }; - }; - }; - }; - }; - - hpm1: usb-pd@3f { - compatible = "apple,cd321x"; - reg = <0x3f>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - typec1: connector { - compatible = "usb-c-connector"; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - typec1_con_hs: endpoint { - remote-endpoint = <&typec1_usb_hs>; - }; - }; - }; - }; - }; -}; - -/* USB controllers */ -&dwc3_0 { - port { - typec0_usb_hs: endpoint { - remote-endpoint = <&typec0_con_hs>; - }; - }; -}; - -&dwc3_1 { - port { - typec1_usb_hs: endpoint { - remote-endpoint = <&typec1_con_hs>; - }; - }; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ -&port00 { - bus-range = <1 1>; - pwren-gpios = <&smc 13 0>; - wifi0: network@0,0 { - compatible = "pci14e4,4425"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 00 00 00 00 00]; - apple,antenna-sku = "XX"; - }; -}; - -&spmi { - status = "okay"; - - pmu@f { - compatible = "apple,sera-pmu"; - reg = <0xf SPMI_USID>; - }; -}; diff --git a/arch/arm/dts/t8103-pmgr.dtsi b/arch/arm/dts/t8103-pmgr.dtsi deleted file mode 100644 index 82ea4aa322e..00000000000 --- a/arch/arm/dts/t8103-pmgr.dtsi +++ /dev/null @@ -1,1138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * PMGR Power domains for the Apple T8103 "M1" SoC - * - * Copyright The Asahi Linux Contributors - */ - - -&pmgr { - ps_sbr: power-controller@100 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x100 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sbr"; - apple,always-on; /* Core device */ - }; - - ps_aic: power-controller@108 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x108 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "aic"; - apple,always-on; /* Core device */ - }; - - ps_dwi: power-controller@110 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x110 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dwi"; - apple,always-on; /* Core device */ - }; - - ps_soc_spmi0: power-controller@118 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x118 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_spmi0"; - }; - - ps_soc_spmi1: power-controller@120 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x120 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_spmi1"; - }; - - ps_soc_spmi2: power-controller@128 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x128 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_spmi2"; - }; - - ps_gpio: power-controller@130 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x130 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "gpio"; - }; - - ps_pms_busif: power-controller@138 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x138 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_busif"; - apple,always-on; /* Core device */ - }; - - ps_pms: power-controller@140 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x140 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms"; - apple,always-on; /* Core device */ - }; - - ps_pms_fpwm0: power-controller@148 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x148 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm0"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm1: power-controller@150 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x150 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm1"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm2: power-controller@158 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x158 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm2"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm3: power-controller@160 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x160 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm3"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm4: power-controller@168 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x168 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm4"; - power-domains = <&ps_pms>; - }; - - ps_soc_dpe: power-controller@170 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x170 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_dpe"; - apple,always-on; /* Core device */ - }; - - ps_pmgr_soc_ocla: power-controller@178 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x178 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pmgr_soc_ocla"; - }; - - ps_ispsens0: power-controller@180 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x180 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens0"; - }; - - ps_ispsens1: power-controller@188 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x188 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens1"; - }; - - ps_ispsens2: power-controller@190 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x190 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens2"; - }; - - ps_ispsens3: power-controller@198 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x198 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens3"; - }; - - ps_pcie_ref: power-controller@1a0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1a0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pcie_ref"; - }; - - ps_aft0: power-controller@1a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1a8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "aft0"; - }; - - ps_devc0_ivdmc: power-controller@1b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1b0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "devc0_ivdmc"; - }; - - ps_imx: power-controller@1b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1b8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "imx"; - apple,always-on; /* Apple fabric, critical block */ - }; - - ps_sio_busif: power-controller@1c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1c0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio_busif"; - }; - - ps_sio: power-controller@1c8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1c8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio"; - power-domains = <&ps_sio_busif>; - }; - - ps_sio_cpu: power-controller@1d0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1d0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio_cpu"; - power-domains = <&ps_sio>; - }; - - ps_fpwm0: power-controller@1d8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1d8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "fpwm0"; - }; - - ps_fpwm1: power-controller@1e0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1e0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "fpwm1"; - }; - - ps_fpwm2: power-controller@1e8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1e8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "fpwm2"; - }; - - ps_i2c0: power-controller@1f0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1f0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c0"; - power-domains = <&ps_sio>; - }; - - ps_i2c1: power-controller@1f8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1f8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c1"; - power-domains = <&ps_sio>; - }; - - ps_i2c2: power-controller@200 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x200 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c2"; - power-domains = <&ps_sio>; - }; - - ps_i2c3: power-controller@208 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x208 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c3"; - power-domains = <&ps_sio>; - }; - - ps_i2c4: power-controller@210 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x210 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c4"; - power-domains = <&ps_sio>; - }; - - ps_spi_p: power-controller@218 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x218 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi_p"; - power-domains = <&ps_sio>; - }; - - ps_uart_p: power-controller@220 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x220 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart_p"; - power-domains = <&ps_sio>; - }; - - ps_audio_p: power-controller@228 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x228 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "audio_p"; - power-domains = <&ps_sio>; - }; - - ps_sio_adma: power-controller@230 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x230 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio_adma"; - power-domains = <&ps_sio>, <&ps_pms>; - }; - - ps_aes: power-controller@238 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x238 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "aes"; - power-domains = <&ps_sio>; - }; - - ps_spi0: power-controller@240 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x240 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi0"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_spi1: power-controller@248 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x248 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi1"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_spi2: power-controller@250 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x250 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi2"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_spi3: power-controller@258 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x258 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi3"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_uart_n: power-controller@268 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x268 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart_n"; - power-domains = <&ps_uart_p>; - }; - - ps_uart0: power-controller@270 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x270 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart0"; - power-domains = <&ps_uart_p>; - }; - - ps_uart1: power-controller@278 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x278 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart1"; - power-domains = <&ps_uart_p>; - }; - - ps_uart2: power-controller@280 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x280 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart2"; - power-domains = <&ps_uart_p>; - }; - - ps_uart3: power-controller@288 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x288 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart3"; - power-domains = <&ps_uart_p>; - }; - - ps_uart4: power-controller@290 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x290 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart4"; - power-domains = <&ps_uart_p>; - }; - - ps_uart5: power-controller@298 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x298 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart5"; - power-domains = <&ps_uart_p>; - }; - - ps_uart6: power-controller@2a0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2a0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart6"; - power-domains = <&ps_uart_p>; - }; - - ps_uart7: power-controller@2a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2a8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart7"; - power-domains = <&ps_uart_p>; - }; - - ps_uart8: power-controller@2b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2b0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart8"; - power-domains = <&ps_uart_p>; - }; - - ps_mca0: power-controller@2b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2b8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca0"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; - }; - - ps_mca1: power-controller@2c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2c0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca1"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca2: power-controller@2c8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2c8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca2"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca3: power-controller@2d0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2d0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca3"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca4: power-controller@2d8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2d8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca4"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca5: power-controller@2e0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2e0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca5"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_dpa0: power-controller@2e8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2e8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dpa0"; - power-domains = <&ps_audio_p>; - }; - - ps_dpa1: power-controller@2f0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2f0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dpa1"; - power-domains = <&ps_audio_p>; - }; - - ps_mcc: power-controller@2f8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2f8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mcc"; - apple,always-on; /* Memory controller */ - }; - - ps_spi4: power-controller@260 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x260 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi4"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_dcs0: power-controller@300 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x300 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs0"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs1: power-controller@310 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x310 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs1"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs2: power-controller@308 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x308 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs2"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs3: power-controller@318 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x318 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs3"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_smx: power-controller@340 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x340 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "smx"; - apple,always-on; /* Apple fabric, critical block */ - }; - - ps_apcie: power-controller@348 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x348 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "apcie"; - power-domains = <&ps_imx>, <&ps_pcie_ref>; - }; - - ps_rmx: power-controller@350 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x350 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "rmx"; - /* Apple Fabric, display/image stuff: this can power down */ - }; - - ps_mmx: power-controller@358 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x358 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mmx"; - /* Apple Fabric, media stuff: this can power down */ - }; - - ps_disp0_fe: power-controller@360 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x360 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "disp0_fe"; - power-domains = <&ps_rmx>; - apple,always-on; /* TODO: figure out if we can enable PM here */ - }; - - ps_dispext_fe: power-controller@368 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x368 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispext_fe"; - power-domains = <&ps_rmx>; - }; - - ps_dispext_cpu0: power-controller@378 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x378 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispext_cpu0"; - power-domains = <&ps_dispext_fe>; - apple,min-state = <4>; - }; - - ps_jpg: power-controller@3c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3c0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "jpg"; - power-domains = <&ps_mmx>; - }; - - ps_msr: power-controller@3c8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3c8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "msr"; - power-domains = <&ps_mmx>; - }; - - ps_msr_ase_core: power-controller@3d0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3d0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "msr_ase_core"; - }; - - ps_pmp: power-controller@3d8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3d8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pmp"; - }; - - ps_pms_sram: power-controller@3e0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3e0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_sram"; - }; - - ps_apcie_gp: power-controller@3e8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3e8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "apcie_gp"; - power-domains = <&ps_apcie>; - }; - - ps_ans2: power-controller@3f0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3f0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ans2"; - /* - * The ADT makes ps_apcie_st depend on ps_ans2 instead, but this - * doesn't make much sense since ANS2 uses APCIE_ST. - */ - power-domains = <&ps_apcie_st>; - }; - - ps_gfx: power-controller@3f8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3f8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "gfx"; - }; - - ps_dcs4: power-controller@320 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x320 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs4"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs5: power-controller@330 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x330 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs5"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs6: power-controller@328 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x328 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs6"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs7: power-controller@338 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x338 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs7"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dispdfr_fe: power-controller@3a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3a8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispdfr_fe"; - power-domains = <&ps_rmx>; - }; - - ps_dispdfr_be: power-controller@3b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3b0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispdfr_be"; - power-domains = <&ps_dispdfr_fe>; - }; - - ps_mipi_dsi: power-controller@3b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3b8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mipi_dsi"; - power-domains = <&ps_dispdfr_be>; - }; - - ps_isp_sys: power-controller@400 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x400 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "isp_sys"; - power-domains = <&ps_rmx>; - }; - - ps_venc_sys: power-controller@408 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x408 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_sys"; - power-domains = <&ps_mmx>; - }; - - ps_avd_sys: power-controller@410 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x410 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "avd_sys"; - power-domains = <&ps_mmx>; - }; - - ps_apcie_st: power-controller@418 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x418 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "apcie_st"; - power-domains = <&ps_apcie>; - }; - - ps_ane_sys: power-controller@470 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x470 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ane_sys"; - }; - - ps_atc0_common: power-controller@420 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x420 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_common"; - }; - - ps_atc0_pcie: power-controller@428 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x428 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_pcie"; - power-domains = <&ps_atc0_common>; - }; - - ps_atc0_cio: power-controller@430 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x430 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_cio"; - power-domains = <&ps_atc0_common>; - }; - - ps_atc0_cio_pcie: power-controller@438 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x438 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_cio_pcie"; - power-domains = <&ps_atc0_cio>; - }; - - ps_atc0_cio_usb: power-controller@440 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x440 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_cio_usb"; - power-domains = <&ps_atc0_cio>; - }; - - ps_atc1_common: power-controller@448 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x448 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_common"; - }; - - ps_atc1_pcie: power-controller@450 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x450 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_pcie"; - power-domains = <&ps_atc1_common>; - }; - - ps_atc1_cio: power-controller@458 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x458 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_cio"; - power-domains = <&ps_atc1_common>; - }; - - ps_atc1_cio_pcie: power-controller@460 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x460 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_cio_pcie"; - power-domains = <&ps_atc1_cio>; - }; - - ps_atc1_cio_usb: power-controller@468 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x468 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_cio_usb"; - power-domains = <&ps_atc1_cio>; - }; - - ps_sep: power-controller@c00 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xc00 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sep"; - apple,always-on; /* Locked on */ - }; - - ps_venc_dma: power-controller@8000 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8000 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_dma"; - power-domains = <&ps_venc_sys>; - }; - - ps_venc_pipe4: power-controller@8008 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8008 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_pipe4"; - power-domains = <&ps_venc_dma>; - }; - - ps_venc_pipe5: power-controller@8010 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8010 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_pipe5"; - power-domains = <&ps_venc_dma>; - }; - - ps_venc_me0: power-controller@8018 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8018 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_me0"; - power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; - }; - - ps_venc_me1: power-controller@8020 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8020 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_me1"; - power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; - }; - - ps_ane_sys_cpu: power-controller@c000 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xc000 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ane_sys_cpu"; - power-domains = <&ps_ane_sys>; - }; - - ps_disp0_cpu0: power-controller@10018 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x10018 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "disp0_cpu0"; - power-domains = <&ps_disp0_fe>; - apple,always-on; /* TODO: figure out if we can enable PM here */ - apple,min-state = <4>; - }; -}; - -&pmgr_mini { - ps_debug: power-controller@58 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x58 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "debug"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_spmi0: power-controller@60 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x60 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_spmi0"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_aon: power-controller@70 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x70 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_aon"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_gpio: power-controller@80 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x80 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_gpio"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_fabric: power-controller@a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xa8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_fabric"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_sram: power-controller@b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xb0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_sram"; - apple,always-on; /* Core AON device */ - }; - - ps_debug_usb: power-controller@b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xb8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "debug_usb"; - apple,always-on; /* Core AON device */ - power-domains = <&ps_debug>; - }; - - ps_debug_auth: power-controller@c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xc0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "debug_auth"; - apple,always-on; /* Core AON device */ - power-domains = <&ps_debug>; - }; - - ps_nub_spmi1: power-controller@68 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x68 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_spmi1"; - apple,always-on; /* Core AON device */ - }; - - ps_msg: power-controller@78 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x78 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "msg"; - }; - - ps_atc0_usb_aon: power-controller@88 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x88 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_usb_aon"; - }; - - ps_atc1_usb_aon: power-controller@90 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x90 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_usb_aon"; - }; - - ps_atc0_usb: power-controller@98 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x98 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_usb"; - power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>; - }; - - ps_atc1_usb: power-controller@a0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xa0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_usb"; - power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>; - }; -}; diff --git a/arch/arm/dts/t8103-u-boot.dtsi b/arch/arm/dts/t8103-u-boot.dtsi deleted file mode 100644 index e9e593a00cf..00000000000 --- a/arch/arm/dts/t8103-u-boot.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT - -&serial0 { - bootph-all; -}; - -&pmgr { - bootph-all; -}; - -&ps_sio_busif { - bootph-all; -}; - -&ps_sio { - bootph-all; -}; - -&ps_uart_p { - bootph-all; -}; - -&ps_uart0 { - bootph-all; -}; diff --git a/arch/arm/dts/t8103.dtsi b/arch/arm/dts/t8103.dtsi deleted file mode 100644 index ed7840f94b6..00000000000 --- a/arch/arm/dts/t8103.dtsi +++ /dev/null @@ -1,696 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple T8103 "M1" SoC - * - * Other names: H13G, "Tonga" - * - * Copyright The Asahi Linux Contributors - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/apple-aic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/apple.h> - -/ { - compatible = "apple,t8103", "apple,arm-platform"; - - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu1: cpu@1 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu2: cpu@2 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu3: cpu@3 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu4: cpu@10100 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu5: cpu@10101 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu6: cpu@10102 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10102>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu7: cpu@10103 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10103>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&aic>; - interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; - interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, - <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, - <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, - <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; - }; - - clkref: clock-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "clkref"; - }; - - clk_120m: clock-120m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <120000000>; - clock-output-names = "clk_120m"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - - ranges; - nonposted-mmio; - - i2c0: i2c@235010000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35010000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c0>; - }; - - i2c1: i2c@235014000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35014000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c1>; - }; - - i2c2: i2c@235018000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35018000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c2>; - status = "disabled"; /* not used in all devices */ - }; - - i2c3: i2c@23501c000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x3501c000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c3>; - }; - - i2c4: i2c@235020000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35020000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c4>; - status = "disabled"; /* only used in J293 */ - }; - - spi3: spi@23510c000 { - compatible = "apple,t8103-spi", "apple,spi"; - reg = <0x2 0x3510c000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_120m>; - pinctrl-0 = <&spi3_pins>; - pinctrl-names = "default"; - power-domains = <&ps_spi3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; /* only used in J293/J313 */ - }; - - serial0: serial@235200000 { - compatible = "apple,s5l-uart"; - reg = <0x2 0x35200000 0x0 0x1000>; - reg-io-width = <4>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; - /* - * TODO: figure out the clocking properly, there may - * be a third selectable clock. - */ - clocks = <&clkref>, <&clkref>; - clock-names = "uart", "clk_uart_baud0"; - power-domains = <&ps_uart0>; - status = "disabled"; - }; - - serial2: serial@235208000 { - compatible = "apple,s5l-uart"; - reg = <0x2 0x35208000 0x0 0x1000>; - reg-io-width = <4>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkref>, <&clkref>; - clock-names = "uart", "clk_uart_baud0"; - power-domains = <&ps_uart2>; - status = "disabled"; - }; - - aic: interrupt-controller@23b100000 { - compatible = "apple,t8103-aic", "apple,aic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x2 0x3b100000 0x0 0x8000>; - power-domains = <&ps_aic>; - }; - - pmgr: power-management@23b700000 { - compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2 0x3b700000 0 0x14000>; - }; - - pinctrl_ap: pinctrl@23c100000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3c100000 0x0 0x100000>; - power-domains = <&ps_gpio>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_ap 0 0 212>; - apple,npins = <212>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; - - i2c0_pins: i2c0-pins { - pinmux = <APPLE_PINMUX(192, 1)>, - <APPLE_PINMUX(188, 1)>; - }; - - i2c1_pins: i2c1-pins { - pinmux = <APPLE_PINMUX(201, 1)>, - <APPLE_PINMUX(199, 1)>; - }; - - i2c2_pins: i2c2-pins { - pinmux = <APPLE_PINMUX(163, 1)>, - <APPLE_PINMUX(162, 1)>; - }; - - i2c3_pins: i2c3-pins { - pinmux = <APPLE_PINMUX(73, 1)>, - <APPLE_PINMUX(72, 1)>; - }; - - i2c4_pins: i2c4-pins { - pinmux = <APPLE_PINMUX(135, 1)>, - <APPLE_PINMUX(134, 1)>; - }; - - spi3_pins: spi3-pins { - pinmux = <APPLE_PINMUX(46, 1)>, - <APPLE_PINMUX(47, 1)>, - <APPLE_PINMUX(48, 1)>, - <APPLE_PINMUX(49, 1)>; - }; - - pcie_pins: pcie-pins { - pinmux = <APPLE_PINMUX(150, 1)>, - <APPLE_PINMUX(151, 1)>, - <APPLE_PINMUX(32, 1)>; - }; - }; - - spmi: spmi@23d0d9300 { - compatible = "apple,t8103-spmi", "apple,spmi"; - reg = <0x2 0x3d0d9300 0x0 0x100>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 343 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <0>; - status = "disabled"; - }; - - pinctrl_nub: pinctrl@23d1f0000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3d1f0000 0x0 0x4000>; - power-domains = <&ps_nub_gpio>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_nub 0 0 23>; - apple,npins = <23>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmgr_mini: power-management@23d280000 { - compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2 0x3d280000 0 0x4000>; - }; - - wdt: watchdog@23d2b0000 { - compatible = "apple,t8103-wdt", "apple,wdt"; - reg = <0x2 0x3d2b0000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; - }; - - pinctrl_smc: pinctrl@23e820000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3e820000 0x0 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_smc 0 0 16>; - apple,npins = <16>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; - }; - - smc_mbox: mbox@23e408000 { - compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; - reg = <0x2 0x3e408000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 400 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 401 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 402 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 403 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "send-empty", "send-not-empty", - "recv-empty", "recv-not-empty"; - #mbox-cells = <0>; - }; - - smc: smc@23e050000 { - compatible = "apple,smc"; - reg = <0x2 0x3e050000 0x0 0x4000>; - mboxes = <&smc_mbox>; - gpio-controller; - #gpio-cells = <2>; - gpio-13 = <0x00800000>; - }; - - pinctrl_aop: pinctrl@24a820000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x4a820000 0x0 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aop 0 0 42>; - apple,npins = <42>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; - }; - - ans_mbox: mbox@277408000 { - compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; - reg = <0x2 0x77408000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "send-empty", "send-not-empty", - "recv-empty", "recv-not-empty"; - #mbox-cells = <0>; - power-domains = <&ps_ans2>; - }; - - sart: sart@27bc50000 { - compatible = "apple,t8103-sart", "apple,sart2"; - reg = <0x2 0x7bc50000 0x0 0x10000>; - power-domains = <&ps_ans2>; - }; - - nvme@27bcc0000 { - compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2"; - reg = <0x2 0x7bcc0000 0x0 0x40000>, - <0x2 0x77400000 0x0 0x4000>; - reg-names = "nvme", "ans"; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>; - mboxes = <&ans_mbox>; - apple,sart = <&sart>; - power-domains = <&ps_ans2>; - resets = <&ps_ans2>; - }; - - dwc3_0: usb@382280000 { - compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3"; - reg = <0x3 0x82280000 0x0 0x100000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>; - usb-role-switch; - role-switch-default-mode = "host"; - iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; - power-domains = <&ps_atc0_usb>; - }; - - dwc3_0_dart_0: iommu@382f00000 { - compatible = "apple,t8103-dart"; - reg = <0x3 0x82f00000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_atc0_usb>; - }; - - dwc3_0_dart_1: iommu@382f80000 { - compatible = "apple,t8103-dart"; - reg = <0x3 0x82f80000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_atc0_usb>; - }; - - dwc3_1: usb@502280000 { - compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3"; - reg = <0x5 0x02280000 0x0 0x100000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>; - usb-role-switch; - role-switch-default-mode = "host"; - iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; - power-domains = <&ps_atc1_usb>; - }; - - dwc3_1_dart_0: iommu@502f00000 { - compatible = "apple,t8103-dart"; - reg = <0x5 0x02f00000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_atc1_usb>; - }; - - dwc3_1_dart_1: iommu@502f80000 { - compatible = "apple,t8103-dart"; - reg = <0x5 0x02f80000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_atc1_usb>; - }; - - pcie0_dart_0: dart@681008000 { - compatible = "apple,t8103-dart"; - reg = <0x6 0x81008000 0x0 0x4000>; - #iommu-cells = <1>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&ps_apcie_gp>; - }; - - pcie0_dart_1: dart@682008000 { - compatible = "apple,t8103-dart"; - reg = <0x6 0x82008000 0x0 0x4000>; - #iommu-cells = <1>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&ps_apcie_gp>; - }; - - pcie0_dart_2: dart@683008000 { - compatible = "apple,t8103-dart"; - reg = <0x6 0x83008000 0x0 0x4000>; - #iommu-cells = <1>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&ps_apcie_gp>; - }; - - pcie0: pcie@690000000 { - compatible = "apple,t8103-pcie", "apple,pcie"; - device_type = "pci"; - - reg = <0x6 0x90000000 0x0 0x1000000>, - <0x6 0x80000000 0x0 0x100000>, - <0x6 0x81000000 0x0 0x4000>, - <0x6 0x82000000 0x0 0x4000>, - <0x6 0x83000000 0x0 0x4000>; - reg-names = "config", "rc", "port0", "port1", "port2"; - - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; - - msi-controller; - msi-parent = <&pcie0>; - msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; - - - iommu-map = <0x100 &pcie0_dart_0 1 1>, - <0x200 &pcie0_dart_1 1 1>, - <0x300 &pcie0_dart_2 1 1>; - iommu-map-mask = <0xff00>; - - bus-range = <0 3>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, - <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; - - power-domains = <&ps_apcie_gp>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - - port00: pci@0,0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &port00 0 0 0 0>, - <0 0 0 2 &port00 0 0 0 1>, - <0 0 0 3 &port00 0 0 0 2>, - <0 0 0 4 &port00 0 0 0 3>; - }; - - port01: pci@1,0 { - device_type = "pci"; - reg = <0x800 0x0 0x0 0x0 0x0>; - reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &port01 0 0 0 0>, - <0 0 0 2 &port01 0 0 0 1>, - <0 0 0 3 &port01 0 0 0 2>, - <0 0 0 4 &port01 0 0 0 3>; - }; - - port02: pci@2,0 { - device_type = "pci"; - reg = <0x1000 0x0 0x0 0x0 0x0>; - reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &port02 0 0 0 0>, - <0 0 0 2 &port02 0 0 0 1>, - <0 0 0 3 &port02 0 0 0 2>, - <0 0 0 4 &port02 0 0 0 3>; - }; - }; - - dart_sio: iommu@235004000 { - compatible = "apple,t8103-dart", "apple,dart"; - reg = <0x2 0x35004000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_sio_cpu>; - }; - - nco_inp: clock-ref { - compatible = "fixed-factor-clock"; - clocks = <&clkref>; - #clock-cells = <0>; - clock-mult = <75>; - clock-div = <2>; // 24 MHz * (75/2) = 900 MHz - clock-output-names = "nco_inp"; - }; - - nco: nco@23b044000 { - compatible = "apple,t8103-nco", "apple,nco"; - reg = <0x2 0x3b044000 0x0 0x14000>; - clocks = <&nco_inp>; - #clock-cells = <1>; - apple,nchannels = <5>; - }; - - admac: dma-controller@238200000 { - compatible = "apple,t8103-admac", "apple,admac"; - reg = <0x2 0x38200000 0x0 0x34000>; - dma-channels = <12>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - iommus = <&dart_sio 2>; - power-domains = <&ps_sio_adma>; - }; - - mca: mca { - compatible = "apple,t8103-mca", "apple,mca"; - reg = <0x2 0x38400000 0x0 0x18000>, - <0x2 0x38300000 0x0 0x30000>; - reg-names = "clusters", "switch"; - clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>; - power-domains = <&ps_mca0>; //, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; - resets = <&ps_mca0>, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; - - #sound-dai-cells = <1>; - apple,nclusters = <6>; - apple,mclk-range = <2600000 25000000>; - - route { - dmas = <&admac 2>; - dma-names = "tx"; - apple,serdes = <1>; - sound-dai = <&mca 0>; - }; - - route2 { - dmas = <&admac 6>; - dma-names = "tx"; - apple,serdes = <3>; - sound-dai = <&mca 2>; - }; - }; - }; -}; - -#include "t8103-pmgr.dtsi" diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index b15938c021d..f9ecb6858f0 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -51,6 +51,7 @@ enum { BROM_BOOTSOURCE_SPINOR = 3, BROM_BOOTSOURCE_SPINAND = 4, BROM_BOOTSOURCE_SD = 5, + BROM_BOOTSOURCE_UFS = 7, BROM_BOOTSOURCE_I2C = 8, BROM_BOOTSOURCE_SPI = 9, BROM_BOOTSOURCE_USB = 10, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h index c51750beff2..fb77fbd7307 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h @@ -222,6 +222,20 @@ enum { REF_CLK0_OUT_PLL_DIV_SHIFT = 0, REF_CLK0_OUT_PLL_DIV_MASK = 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT, + /* CRU_CLK_SEL36_CON */ + CLK_REFCLKO25M_GMAC0_DIV_SHIFT = 0, + CLK_REFCLKO25M_GMAC0_DIV_MASK = 0x7f << CLK_REFCLKO25M_GMAC0_DIV_SHIFT, + CLK_REFCLKO25M_GMAC0_SEL_SHIFT = 7, + CLK_REFCLKO25M_GMAC0_SEL_MASK = 1 << CLK_REFCLKO25M_GMAC0_SEL_SHIFT, + CLK_REFCLKO25M_GMAC0_SEL_GPLL = 0, + CLK_REFCLKO25M_GMAC0_SEL_CPLL = 1, + CLK_REFCLKO25M_GMAC1_DIV_SHIFT = 8, + CLK_REFCLKO25M_GMAC1_DIV_MASK = 0x7f << CLK_REFCLKO25M_GMAC1_DIV_SHIFT, + CLK_REFCLKO25M_GMAC1_SEL_SHIFT = 15, + CLK_REFCLKO25M_GMAC1_SEL_MASK = 1 << CLK_REFCLKO25M_GMAC1_SEL_SHIFT, + CLK_REFCLKO25M_GMAC1_SEL_GPLL = 0, + CLK_REFCLKO25M_GMAC1_SEL_CPLL = 1, + /* CRU_CLK_SEL55_CON */ ACLK_BUS_ROOT_SEL_SHIFT = 9, ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT, diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 8aa5f9721c4..5359b2ad87b 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -222,6 +222,11 @@ u64 get_tcr(u64 *pips, u64 *pva_bits); * mmu_setup() - Sets up the mmu page tables as per mem_map */ void mmu_setup(void); + +/** + * mmu_enable() - Enable the MMU by setting 'M' bit in SCTLR register + */ +void mmu_enable(void); #endif #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 650783ae732..eba7bae9351 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,3 +1,5 @@ +#include <linux/types.h> + #ifdef CONFIG_GPIO_EXTRA_HEADER #include <asm/arch/gpio.h> #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9e3ad57073d..5ed6833c155 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -342,6 +342,7 @@ void smc_call(struct pt_regs *args); void __noreturn psci_system_reset(void); void __noreturn psci_system_reset2(u32 reset_level, u32 cookie); void __noreturn psci_system_off(void); +int psci_features(u32 psci_func_id); #ifdef CONFIG_ARMV8_PSCI extern char __secure_start[]; diff --git a/arch/arm/mach-apple/Kconfig b/arch/arm/mach-apple/Kconfig index 294690ec0e8..fdc8c32152f 100644 --- a/arch/arm/mach-apple/Kconfig +++ b/arch/arm/mach-apple/Kconfig @@ -3,12 +3,22 @@ if ARCH_APPLE config TEXT_BASE default 0x00000000 -config SYS_CONFIG_NAME +config SYS_SOC default "apple" -config SYS_SOC +config SYS_VENDOR default "apple" +config SYS_BOARD + string "Board name" + default "mac" + help + This option contains information about board name. + Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will + be used. + Apple silicon based devices are expected to use the generic board name + "mac". + config SYS_MALLOC_LEN default 0x4000000 diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 4cd8979bdc2..20054f54089 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -673,6 +673,83 @@ static struct mm_region t6022_mem_map[] = { } }; +/* Apple M3 */ + +static struct mm_region t8122_mem_map[] = { + { + /* I/O */ + .virt = 0x200000000, + .phys = 0x200000000, + .size = 4UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* NVMe */ + .virt = 0x300000000, + .phys = 0x300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x580000000, + .phys = 0x580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5a0000000, + .phys = 0x5a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5c0000000, + .phys = 0x5c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC0 */ + .virt = 0x700000000, + .phys = 0x700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC1 */ + .virt = 0xb00000000, + .phys = 0xb00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x10000000000, + .phys = 0x10000000000, + .size = 8UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + struct mm_region *mem_map; int board_init(void) @@ -720,6 +797,8 @@ void build_mem_map(void) mem_map = t6020_mem_map; else if (of_machine_is_compatible("apple,t6022")) mem_map = t6022_mem_map; + else if (of_machine_is_compatible("apple,t8122")) + mem_map = t8122_mem_map; else panic("Unsupported SoC\n"); diff --git a/arch/arm/mach-apple/rtkit_helper.c b/arch/arm/mach-apple/rtkit_helper.c index b7d60e15700..cbdc204f141 100644 --- a/arch/arm/mach-apple/rtkit_helper.c +++ b/arch/arm/mach-apple/rtkit_helper.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <asm/arch/rtkit.h> #include <linux/iopoll.h> +#include <linux/sizes.h> /* ASC registers */ #define REG_CPU_CTRL 0x0044 diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 7d00f1650b4..65e9d70f084 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -78,7 +78,6 @@ choice config TARGET_AT91SAM9260EK bool "Atmel at91sam9260 reference board" select AT91SAM9260 - select BOARD_EARLY_INIT_F config TARGET_GURNARD bool "Support gurnard" @@ -96,7 +95,6 @@ config TARGET_GURNARD config TARGET_AT91SAM9261EK bool "Atmel at91sam9261 reference board" select AT91SAM9261 - select BOARD_EARLY_INIT_F config TARGET_PM9261 bool "Ronetix pm9261 board" @@ -105,7 +103,6 @@ config TARGET_PM9261 config TARGET_AT91SAM9263EK bool "Atmel at91sam9263 reference board" select AT91SAM9263 - select BOARD_EARLY_INIT_F config TARGET_USB_A9263 bool "Caloa USB A9260 board" @@ -119,7 +116,6 @@ config TARGET_PM9263 config TARGET_AT91SAM9M10G45EK bool "Atmel AT91SAM9M10G45-EK board" select AT91SAM9M10G45 - select BOARD_EARLY_INIT_F select SUPPORT_SPL config TARGET_PM9G45 @@ -129,18 +125,15 @@ config TARGET_PM9G45 config TARGET_AT91SAM9N12EK bool "Atmel AT91SAM9N12-EK board" select AT91SAM9N12 - select BOARD_EARLY_INIT_F select SUPPORT_SPL config TARGET_AT91SAM9RLEK bool "Atmel at91sam9rl reference board" select AT91SAM9RL - select BOARD_EARLY_INIT_F config TARGET_AT91SAM9X5EK bool "Atmel AT91SAM9X5-EK board" select AT91SAM9X5 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SUPPORT_SPL @@ -154,31 +147,26 @@ config TARGET_GARDENA_SMART_GATEWAY_AT91SAM config TARGET_SAM9X60EK bool "SAM9X60-EK board" select SAM9X60 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT config TARGET_SAM9X60_CURIOSITY bool "SAM9X60 CURIOSITY board" select SAM9X60 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT config TARGET_SAM9X75_CURIOSITY bool "SAM9X75 CURIOSITY board" select SAM9X7 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT imply OF_UPSTREAM config TARGET_SAMA5D2_PTC_EK bool "SAMA5D2 PTC EK board" - select BOARD_EARLY_INIT_F select SAMA5D2 select BOARD_LATE_INIT config TARGET_SAMA5D2_XPLAINED bool "SAMA5D2 Xplained board" - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SAMA5D2 select SUPPORT_SPL @@ -186,7 +174,6 @@ config TARGET_SAMA5D2_XPLAINED config TARGET_SAMA5D27_SOM1_EK bool "SAMA5D27 SOM1 EK board" select SAMA5D2 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select CPU_V7A select SUPPORT_SPL @@ -201,7 +188,6 @@ config TARGET_SAMA5D27_SOM1_EK config TARGET_SAMA5D27_WLSOM1_EK bool "SAMA5D27 WLSOM1 EK board" select SAMA5D2 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select CPU_V7A select SUPPORT_SPL @@ -228,7 +214,6 @@ config TARGET_SAMA5D2_ICP bool "SAMA5D2 Industrial Connectivity Platform (ICP)" select SAMA5D2 select SUPPORT_SPL - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT help The SAMA5D2 ICP embeds SAMA5D27 rev. C SoC, together with @@ -248,28 +233,24 @@ config TARGET_SAMA5D29_CURIOSITY config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" - select BOARD_EARLY_INIT_F select SAMA5D3 select SUPPORT_SPL select BOARD_LATE_INIT config TARGET_SAMA5D3XEK bool "SAMA5D3X-EK board" - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SAMA5D3 select SUPPORT_SPL config TARGET_SAMA5D4_XPLAINED bool "SAMA5D4 Xplained board" - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SAMA5D4 select SUPPORT_SPL config TARGET_SAMA5D4EK bool "SAMA5D4 Evaluation Kit" - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SAMA5D4 select SUPPORT_SPL @@ -291,7 +272,6 @@ config TARGET_CORVUS config TARGET_SAMA7G5EK bool "SAMA7G5 EK board" select SAMA7G5 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT config TARGET_SAMA7G54_CURIOSITY @@ -307,7 +287,6 @@ config TARGET_SAMA7G54_CURIOSITY config TARGET_SAMA7D65_CURIOSITY bool "SAMA7D65 CURIOSITY board" select SAMA7D65 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT imply OF_UPSTREAM diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 7bfbadf0483..32cf78b3bf6 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -132,7 +132,8 @@ void board_init_f(ulong dummy) timer_init(); - board_early_init_f(); + if (IS_ENABLED(CONFIG_BOARD_EARLY_INIT_F)) + board_early_init_f(); at91_mem_init(); diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h index a86875b1833..c72b47e1b10 100644 --- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h @@ -54,6 +54,7 @@ #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 #define MISC_CTRL_MAX_BURST_SIZE_128 0x0 +#define MISC_CTRL_MAX_BURST_SIZE_128_2712 0x100000 #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c @@ -70,6 +71,7 @@ #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_PCIE_CTRL 0x4064 #define PCIE_MISC_PCIE_STATUS 0x4068 #define STATUS_PCIE_PORT_MASK 0x80 #define STATUS_PCIE_PORT_SHIFT 7 @@ -108,6 +110,10 @@ #define PCIE_RGR1_SW_INIT_1 0x9210 #define PCIE_EXT_CFG_INDEX 0x9000 +#define RGR1_SW_INIT_1_PERST_MASK 0x1 +#define RGR1_SW_INIT_1_PERSTB_MASK 0x4 +#define RGR1_SW_INIT_1_INIT_MASK 0x2 + /* A small window pointing at the ECAM of the device selected by CFG_INDEX */ #define PCIE_EXT_CFG_DATA 0x8000 diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 7a1de22e0ae..7a2faaa4de6 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -18,7 +18,7 @@ #ifdef CONFIG_ARM64 #include <asm/armv8/mmu.h> -#define MEM_MAP_MAX_ENTRIES (4) +#define MEM_MAP_MAX_ENTRIES (5) static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { { @@ -84,6 +84,14 @@ static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + /* Whole PCIe section */ + .virt = 0x1800000000UL, + .phys = 0x1800000000UL, + .size = 0x0800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* SoC bus */ .virt = 0x107c000000UL, .phys = 0x107c000000UL, diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 2308457df23..f072e6a9e3d 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -7,6 +7,7 @@ config AHAB_BOOT config IMX9 bool + select ARCH_MISC_INIT select BINMAN select CPU select CPU_IMX @@ -22,7 +23,6 @@ config IMX93 config IMX91 bool select IMX9 - select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS config IMX95_A0 @@ -30,7 +30,6 @@ config IMX95_A0 config IMX95 bool - select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS select IMX9 select DM_MAILBOX @@ -171,6 +170,10 @@ config TARGET_TORADEX_SMARC_IMX95 select IMX95 imply OF_UPSTREAM +config TARGET_VERDIN_IMX95 + bool "Support Toradex Verdin iMX95 module" + select IMX95 + config TARGET_IMX952_EVK bool "imx952_evk" select IMX_SM_CPU @@ -195,6 +198,7 @@ source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" source "board/toradex/smarc-imx95/Kconfig" +source "board/toradex/verdin-imx95/Kconfig" source "board/nxp/imx952_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index f576ee650f0..597eca142af 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -90,6 +90,21 @@ config TARGET_COLIBRI_IMX7 select MX7D imply CMD_DM +config TARGET_TQMA7 + bool "TQ-Systems TQMa7x SoM" + select BOARD_LATE_INIT + select SUPPORT_SPL + select SPL_SEPARATE_BSS if SPL + select DM + select DM_SERIAL + select MX7 + imply MX7D + imply CMD_DM + imply DM_THERMAL + help + TQMa7x is a TQ SoM with i.MX7 CPU + The SoM can be used on various baseboards. + endchoice config SYS_SOC @@ -102,6 +117,7 @@ source "board/novtech/meerkat96/Kconfig" source "board/storopack/smegw01/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" +source "board/tq/tqma7/Kconfig" source "board/warp7/Kconfig" endif diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index b0a75988714..19a6e24f38b 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -294,6 +294,7 @@ void enable_caches(void) __func__, ret); } + mmu_enable(); icache_enable(); dcache_enable(); } diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 81b5f1fa45e..b337a71956f 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -126,4 +126,14 @@ struct rom_extended_boot_data { u32 get_boot_device(void); const char *get_reset_reason(void); + +#define writel_verify(val, addr) \ +do { \ + u32 readback; \ + writel(val, addr); \ + readback = readl(addr); \ + if (readback != val) \ + printf("writel_verify failed: addr=0x%p, expected=0x%x, got=0x%x\n", \ + (void *)(addr), (val), readback); \ +} while (0) #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index b5453d8895d..780d853423f 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -40,6 +40,15 @@ #define NB_THREADMAP_BIT1 BIT(1) #define NB_THREADMAP_BIT2 BIT(2) +/* + * RAT mapping for errata ID: i2437 + */ +#define RAT_ERRATA_2437_BASE_REGION0 0x40f90000 +#define RAT_ERRATA_2437_IN_ADDR 0xc0000000 +#define RAT_ERRATA_2437_OUT_ADDR_U 0x0000004d +#define RAT_ERRATA_2437_OUT_ADDR_L 0x21000000 +#define RAT_ERRATA_2437_CTRL 0x80000010 + struct fwl_data cbass_hc_cfg0_fwls[] = { { "PCIE0_CFG", 2577, 7 }, { "EMMC8SS0_CFG", 2579, 4 }, @@ -346,6 +355,36 @@ void board_init_f(ulong dummy) if (ret) printf("AVS init failed: %d\n", ret); } + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * Errata ID i2437: SE Clock-Gating Turning Off Too Early + * + * A hardware bug is present in the C7120 Streaming Engine top level + * clock gating logic that can lead to the C7120 CPU hanging. + + * Workaround: The DSP_<COREID>_DEBUG_CLKEN_OVERRIDE fields of the + * COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register (where COREID is the + * name of the specific C7120 core) must be enabled before power-up + * of the C7120 core to override all clock-gating. + */ + + /* Setup RAT mapping */ + debug("Errata i2437: Use RAT for COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register\n"); + writel_verify(RAT_ERRATA_2437_IN_ADDR, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_L, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_U, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + writel_verify(RAT_ERRATA_2437_CTRL, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + + /* Enable DSP_X_DEBUG_CLKEN_OVERRIDE for C71x cores */ + writel_verify(0x300, RAT_ERRATA_2437_IN_ADDR + 0x200); + + /* Clear RAT mapping */ + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + } } #endif diff --git a/arch/arm/mach-k3/j784s4/Kconfig b/arch/arm/mach-k3/j784s4/Kconfig index fff44dbf7c9..f5447b0b836 100644 --- a/arch/arm/mach-k3/j784s4/Kconfig +++ b/arch/arm/mach-k3/j784s4/Kconfig @@ -14,6 +14,7 @@ config TARGET_AQUILA_AM69_A72 select ARM64 select SYS_DISABLE_DCACHE_OPS select BINMAN + imply OF_UPSTREAM config TARGET_AQUILA_AM69_R5 bool "Toradex Aquila AM69 running on R5" diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 53f152ccd9c..507b7ab685a 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -45,6 +45,15 @@ #define NB_THREADMAP_BIT1 BIT(1) #define NB_THREADMAP_BIT2 BIT(2) +/* + * RAT mapping for errata ID: i2437 + */ +#define RAT_ERRATA_2437_BASE_REGION0 0x40f90000 +#define RAT_ERRATA_2437_IN_ADDR 0xc0000000 +#define RAT_ERRATA_2437_OUT_ADDR_U 0x0000004d +#define RAT_ERRATA_2437_OUT_ADDR_L 0x21000000 +#define RAT_ERRATA_2437_CTRL 0x80000010 + struct fwl_data infra_cbass0_fwls[] = { { "PSC0", 5, 1 }, { "PLL_CTRL0", 6, 1 }, @@ -322,6 +331,36 @@ void board_init_f(ulong dummy) setup_navss_nb(); setup_qos(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * Errata ID i2437 SE Clock-Gating Turning Off Too Early + * + * A hardware bug is present in the C7120 Streaming Engine top level + * clock gating logic that can lead to the C7120 CPU hanging. + + * Workaround: The DSP_<COREID>_DEBUG_CLKEN_OVERRIDE fields of the + * COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register (where COREID is the + * name of the specific C7120 core) must be enabled before power-up + * of the C7120 core to override all clock-gating. + */ + + /* Setup RAT mapping */ + debug("Errata i2437: Use RAT for COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register\n"); + writel_verify(RAT_ERRATA_2437_IN_ADDR, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_L, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_U, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + writel_verify(RAT_ERRATA_2437_CTRL, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + + /* Enable DSP_X_DEBUG_CLKEN_OVERRIDE for C71x cores */ + writel_verify(0xF00, RAT_ERRATA_2437_IN_ADDR + 0x200); + + /* Clear RAT mapping */ + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + } } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index b5b06f4e5b2..80f7185e929 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -195,7 +195,6 @@ config SYS_BOARD be used. config SYS_CONFIG_NAME - default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 default "mt7981" if TARGET_MT7981 diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index ef86129b535..c687ef822a2 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -12,6 +12,8 @@ config MESON64_COMMON select MMC_PWRSEQ select BOARD_LATE_INIT select MESON_SM + imply SYSRESET + imply SYSRESET_PSCI imply CMD_DM config MESON_GX diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c index a5afc2d75c0..c34b81e5e78 100644 --- a/arch/arm/mach-meson/board-common.c +++ b/arch/arm/mach-meson/board-common.c @@ -155,16 +155,14 @@ int board_late_init(void) return meson_board_late_init(); } +#if defined(CONFIG_XPL) || !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { -#if CONFIG_SPL_BUILD /* * We do not have BL31 running yet, so no PSCI. * Instead, let the watchdog reset the board. */ for (;;) ; -#else - psci_system_reset(); -#endif } +#endif diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig index fa4e312a4dd..f86acc31039 100644 --- a/arch/arm/mach-renesas/Kconfig +++ b/arch/arm/mach-renesas/Kconfig @@ -1,15 +1,19 @@ if ARCH_RENESAS -# Renesas ARM SoCs R-Car Gen3/Gen4 (64bit) +config TMU_TIMER + bool + +# Renesas ARM SoCs R-Car Gen3/Gen4/Gen5 (64bit Cortex-A / 32bit Cortex-M/R) config RCAR_64 bool - select ARM64 + select CPU_V8M if RCAR_64_RSIP + select ARM64 if !RCAR_64_RSIP select CMD_CACHE - select OF_BOARD_SETUP + select OF_BOARD_SETUP if !RCAR_64_RSIP select PHY select PINCONF select PINCTRL - select POSITION_INDEPENDENT + select POSITION_INDEPENDENT if !RCAR_64_RSIP imply CMD_FS_UUID imply CMD_GPT imply CMD_MMC_SWRITE if MMC diff --git a/arch/arm/mach-renesas/Kconfig.32 b/arch/arm/mach-renesas/Kconfig.32 index bbc61ccf480..3ee52c40da7 100644 --- a/arch/arm/mach-renesas/Kconfig.32 +++ b/arch/arm/mach-renesas/Kconfig.32 @@ -134,17 +134,17 @@ choice config QOS_PRI_NORMAL bool "Non primary" help - Select normal mode for QoS setting. + Select normal mode for QoS setting. config QOS_PRI_MEDIA bool "Media primary" help - Select multimedia primary mode for QoS setting. + Select multimedia primary mode for QoS setting. config QOS_PRI_GFX bool "GFX primary" help - Select GFX(graphics) primary mode for QoS setting. + Select GFX(graphics) primary mode for QoS setting. endchoice diff --git a/arch/arm/mach-renesas/Kconfig.rcar3 b/arch/arm/mach-renesas/Kconfig.rcar3 index 0d5f7486218..6bed7684fb8 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar3 +++ b/arch/arm/mach-renesas/Kconfig.rcar3 @@ -96,35 +96,35 @@ config TARGET_CONDOR bool "Condor board" imply R8A77980 help - Support for Renesas R-Car Gen3 Condor platform + Support for Renesas R-Car Gen3 Condor platform config TARGET_V3HSK bool "V3HSK board" help - Support for Renesas R-Car Gen3 V3HSK platform + Support for Renesas R-Car Gen3 V3HSK platform config TARGET_DRAAK bool "Draak board" imply R8A77995 help - Support for Renesas R-Car Gen3 Draak platform + Support for Renesas R-Car Gen3 Draak platform config TARGET_EAGLE bool "Eagle board" imply R8A77970 help - Support for Renesas R-Car Gen3 Eagle platform + Support for Renesas R-Car Gen3 Eagle platform config TARGET_V3MSK bool "V3MSK board" help - Support for Renesas R-Car Gen3 V3MSK platform + Support for Renesas R-Car Gen3 V3MSK platform config TARGET_EBISU bool "Ebisu board" imply R8A77990 help - Support for Renesas R-Car Gen3 Ebisu platform + Support for Renesas R-Car Gen3 Ebisu platform config TARGET_HIHOPE_RZG2 bool "HiHope RZ/G2 board" @@ -135,14 +135,14 @@ config TARGET_HIHOPE_RZG2 imply RZ_G2 imply SYS_MALLOC_F help - Support for RZG2 HiHope platform + Support for RZG2 HiHope platform config TARGET_SILINUX_EK874 bool "Silicon Linux EK874 board" imply R8A774C0 imply RZ_G2 help - Support for Silicon Linux EK874 platform + Support for Silicon Linux EK874 platform config TARGET_SALVATOR_X bool "Salvator-X board" @@ -152,7 +152,7 @@ config TARGET_SALVATOR_X imply R8A77965 imply SYS_MALLOC_F help - Support for Renesas R-Car Gen3 platform + Support for Renesas R-Car Gen3 platform config TARGET_ULCB bool "ULCB board" @@ -162,7 +162,14 @@ config TARGET_ULCB imply R8A77965 imply SYS_MALLOC_F help - Support for Renesas R-Car Gen3 ULCB platform + Support for Renesas R-Car Gen3 ULCB platform + +config TARGET_GEIST + bool "Geist board" + imply R8A77965 + imply SYS_MALLOC_F + help + Support for Renesas R-Car Gen3 Geist platform endchoice @@ -170,6 +177,7 @@ source "board/renesas/condor/Kconfig" source "board/renesas/draak/Kconfig" source "board/renesas/eagle/Kconfig" source "board/renesas/ebisu/Kconfig" +source "board/renesas/geist/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" source "board/renesas/v3hsk/Kconfig" diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4 index 04418f7aa05..2439501d07e 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar4 +++ b/arch/arm/mach-renesas/Kconfig.rcar4 @@ -46,7 +46,7 @@ config TARGET_FALCON bool "Falcon board" imply R8A779A0 help - Support for Renesas R-Car Gen3 Falcon platform + Support for Renesas R-Car Gen3 Falcon platform config TARGET_SPIDER bool "Spider board" diff --git a/arch/arm/mach-renesas/Kconfig.rcar5 b/arch/arm/mach-renesas/Kconfig.rcar5 index 528fc5aecc9..fcca3811241 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar5 +++ b/arch/arm/mach-renesas/Kconfig.rcar5 @@ -1,11 +1,21 @@ if RCAR_GEN5 +config RCAR_64_RSIP + bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)" + select SKIP_RELOCATE_CODE + select TMU_TIMER + help + Build U-Boot for the Cortex-M33 RSIP core present on selected SoC. + The default is n, meaning U-Boot is built for the Cortex-A core. + menu "Select Target SoC" config R8A78000 bool "Renesas SoC R8A78000" select GICV3 + imply CLK_R8A78000 imply PINCTRL_PFC_R8A78000 + imply RENESAS_R8A78000_POWER_DOMAIN endmenu @@ -23,4 +33,7 @@ endchoice source "board/renesas/ironhide/Kconfig" +config SKIP_RELOCATE_CODE_DATA_OFFSET + default 0xa0000000 if RCAR_64_RSIP + endif diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 652a392ba6f..83c576d6007 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -40,6 +40,27 @@ else srec_cat_le_cmd := "-l-e-constant" endif +ifneq ($(CONFIG_RCAR_GEN5),) +quiet_cmd_srec_cat = SRECCAT $@ + cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ + -Output_Block_Size 16 \ + -generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \ + -generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4 + +quiet_cmd_srec_shdr_cat = SRECCAT $@ + cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \ + -Output_Block_Size 16 \ + -generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \ + -generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \ + -generate 0x18402004 0x18402008 $(srec_cat_le_cmd) 0x00010010 4 \ + -generate 0x18402008 0x1840200c $(srec_cat_le_cmd) 0x0 4 \ + -generate 0x1840200c 0x18402010 $(srec_cat_le_cmd) 0x34040000 4 \ + -generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \ + -generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4 \ + -generate 0x18402018 0x1840201c $(srec_cat_le_cmd) 0x0 4 \ + -generate 0x1840201c 0x18402020 $(srec_cat_le_cmd) 0x0 4 +else ifneq ($(CONFIG_RCAR_GEN4),) quiet_cmd_srec_cat = SRECCAT $@ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ @@ -106,10 +127,17 @@ quiet_cmd_srec_cat = SRECCAT $@ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 endif endif +endif spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin $(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}')) +u-boot-elf.scif: u-boot-elf.srec u-boot.bin + $(call cmd,srec_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}')) + +u-boot-elf.shdr: u-boot-elf.srec u-boot.bin + $(call cmd,srec_shdr_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}')) + # if srec_cat is present build u-boot-spl.scif by default has_srec_cat = $(call try-run,srec_cat -VERSion,y,n) INPUTS-$(has_srec_cat) += u-boot-spl.scif diff --git a/arch/arm/mach-renesas/cpu_info.c b/arch/arm/mach-renesas/cpu_info.c index f040d732a51..42183e2daa5 100644 --- a/arch/arm/mach-renesas/cpu_info.c +++ b/arch/arm/mach-renesas/cpu_info.c @@ -114,6 +114,8 @@ int arch_misc_init(void) int print_cpuinfo(void) { + const uintptr_t pfc_base = 0xe6060000; + void __iomem *rcar_m3nm3l_ident = (void __iomem *)pfc_base + 0x800; int i = renesas_cpuinfo_idx(); if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A7796 && @@ -123,6 +125,17 @@ int print_cpuinfo(void) return 0; } + /* + * M3Le PRR ID is the same as M3N , but PFC register 0x800 reads 0 + * on M3N and 1 on M3Le. Use this to discern M3Le from M3N . + */ + if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A77965 && + readl(rcar_m3nm3l_ident) == 1) { + printf("CPU: Renesas Electronics R8A779MD rev %d.%d\n", + renesas_get_cpu_rev_integer(), renesas_get_cpu_rev_fraction()); + return 0; + } + printf("CPU: Renesas Electronics %s rev %d.%d\n", get_cpu_name(i), renesas_get_cpu_rev_integer(), renesas_get_cpu_rev_fraction()); diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h index f9af3ef885a..35b0d00e45c 100644 --- a/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h @@ -9,7 +9,13 @@ /* * R-Car (R8A78000) I/O Addresses */ +#if defined(CONFIG_RCAR_64_RSIP) +/* Cortex-M33 address */ +#define TMU_BASE 0xC0680000 +#else +/* Cortex-A720AE address */ #define TMU_BASE 0x1C030000 +#endif /* Arm Generic Timer */ #define CNTCR_BASE 0x1C000FFF /* Region 0 */ diff --git a/arch/arm/mach-renesas/u-boot-rsip.lds b/arch/arm/mach-renesas/u-boot-rsip.lds new file mode 100644 index 00000000000..c5a74f8a608 --- /dev/null +++ b/arch/arm/mach-renesas/u-boot-rsip.lds @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <[email protected]> + */ + +#include <config.h> +#include <asm/psci.h> + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ +#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) + /* + * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not + * bundle with u-boot, and code offsets are fixed. Secure zone + * only needs to be copied from the loading address to + * CONFIG_ARMV7_SECURE_BASE, which is the linking and running + * address for secure code. + * + * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will + * be included in u-boot address space, and some absolute address + * were used in secure code. The absolute addresses of the secure + * code also needs to be relocated along with the accompanying u-boot + * code. + * + * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. + */ + /DISCARD/ : { *(.rel._secure*) } +#endif + . = 0x00000000; + + . = ALIGN(4); + __image_copy_start = ADDR(.text); + .text : + { + CPUDIR/start.o (.text*) + *(.vectors) + } + + /* This needs to come before *(.text*) */ + .efi_runtime : { + __efi_runtime_start = .; + *(.text.efi_runtime*) + *(.rodata.efi_runtime*) + *(.data.efi_runtime*) + __efi_runtime_stop = .; + } + + .text_rest : + { + *(.text*) + } + +#ifdef CONFIG_ARMV7_NONSEC + + /* Align the secure section only if we're going to use it in situ */ + .__secure_start +#ifndef CONFIG_ARMV7_SECURE_BASE + ALIGN(CONSTANT(COMMONPAGESIZE)) +#endif + : { + KEEP(*(.__secure_start)) + } + +#ifndef CONFIG_ARMV7_SECURE_BASE +#define __ARMV7_SECURE_BASE +#define __ARMV7_PSCI_STACK_IN_RAM +#else +#define __ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_BASE +#endif + + .secure_text __ARMV7_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + } + + .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) + { + *(._secure.data) + } + +#ifdef CONFIG_ARMV7_PSCI + .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data), + CONSTANT(COMMONPAGESIZE)) (NOLOAD) : +#ifdef __ARMV7_PSCI_STACK_IN_RAM + AT(ADDR(.secure_stack)) +#else + AT(LOADADDR(.secure_data) + SIZEOF(.secure_data)) +#endif + { + KEEP(*(.__secure_stack_start)) + + /* Skip addresses for stack */ + . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; + + /* Align end of stack section to page boundary */ + . = ALIGN(CONSTANT(COMMONPAGESIZE)); + + KEEP(*(.__secure_stack_end)) + +#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE + /* + * We are not checking (__secure_end - __secure_start) here, + * as these are the load addresses, and do not include the + * stack section. Instead, use the end of the stack section + * and the start of the text section. + */ + ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE, + "Error: secure section exceeds secure memory size"); +#endif + } + +#ifndef __ARMV7_PSCI_STACK_IN_RAM + /* Reset VMA but don't allocate space if we have secure SRAM */ + . = LOADADDR(.secure_stack); +#endif + +#endif + + .__secure_end : AT(ADDR(.__secure_end)) { + *(.__secure_end) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + __data_start = .; + *(.data*) + __data_end = .; + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); + } + + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.rel*.efi_runtime) + *(.rel*.efi_runtime.*) + __efi_runtime_rel_stop = .; + } + + . = ALIGN(8); + __image_copy_end = .; + + /* + * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start + * needs to be a multiple of 8 and we overlay .bss with .rel.dyn + */ + .rel.dyn ALIGN(8) : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + . = ALIGN(8); + } + + _end = .; + _image_binary_end = .; + +/* + * These sections occupy the same memory, but their lifetimes do + * not overlap: U-Boot initializes .bss only after applying dynamic + * relocations and therefore after it doesn't need .rel.dyn any more. + */ + + /* BSS goes to special read-write offset below U-Boot entry point */ + . = 0xb8400000; + .bss (OVERLAY): { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynbss) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu.hash) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } +} + +ASSERT(_image_binary_end % 8 == 0, \ + "_image_binary_end must be 8-byte aligned for device tree"); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 108713488af..d92fcae2bb5 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -65,6 +65,7 @@ config ROCKCHIP_RK3066 config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD help The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 @@ -108,6 +109,7 @@ config ROCKCHIP_RK322X select TPL_OF_LIBFDT select TPL_HAVE_INIT_STACK if TPL select SPL_DRIVERS_MISC + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS index 393edd3984c..79cf9e97f70 100644 --- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -10,6 +10,12 @@ S: Maintained F: arch/arm/dts/rk3576-nanopi-m5* F: configs/nanopi-m5-rk3576_defconfig +NANOPI-R76S-RK3576 +M: Jonas Karlman <[email protected]> +S: Maintained +F: arch/arm/dts/rk3576-nanopi-r76s* +F: configs/nanopi-r76s-rk3576_defconfig + OMNI3576-RK3576 M: Jonas Karlman <[email protected]> S: Maintained diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index c17ba418ced..1def4e87971 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -49,6 +49,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0", [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", + [BROM_BOOTSOURCE_UFS] = "/soc/ufshc@2a2d0000", }; static struct mm_region rk3576_mem_map[] = { diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 6572dde29f6..d2dd5e10935 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -76,6 +76,9 @@ static int spl_node_to_boot_device(int node) if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) return BOOT_DEVICE_SPI; + if (!uclass_find_device_by_of_offset(UCLASS_UFS, node, &parent)) + return BOOT_DEVICE_UFS; + return -1; } @@ -231,6 +234,17 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen) return -ENODEV; } + if (boot_device == BOOT_DEVICE_UFS) { + ret = uclass_find_device(UCLASS_UFS, 0, &dev); + if (ret) { + debug("%s: could not find device for UFS: %d\n", + __func__, ret); + return ret; + } + + return ofnode_get_path(dev_ofnode(dev), buf, buflen); + } + #if CONFIG_IS_ENABLED(BLK) dev_num = (boot_device == BOOT_DEVICE_MMC1) ? 0 : 1; diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 5fb3240acc5..829a0109ac7 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -555,6 +555,11 @@ int board_late_init(void) fdt_status |= !lmb_alloc(SZ_2M, &addr) ? env_set_hex("fdt_addr_r", addr) : 1; + if (IS_ENABLED(CONFIG_OF_LIBFDT_OVERLAY)) { + status |= !lmb_alloc(SZ_1M, &addr) ? + env_set_hex("fdtoverlay_addr_r", addr) : 1; + } + if (status || fdt_status) log_warning("%s: Failed to set run time variables\n", __func__); diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c index 5b6076ea8e5..374e6262db4 100644 --- a/arch/arm/mach-snapdragon/of_fixup.c +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -4,7 +4,7 @@ * * This file implements runtime fixups for Qualcomm DT to improve * compatibility with U-Boot. This includes adjusting the USB nodes - * to only use USB high-speed. + * to only use USB high-speed if SSPHY driver is not available. * * We use OF_LIVE for this rather than early FDT fixup for a couple * of reasons: it has a much nicer API, is most likely more efficient, @@ -21,26 +21,108 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dm/of_access.h> #include <dm/of.h> +#include <dm/device.h> +#include <dm/lists.h> #include <event.h> #include <fdt_support.h> #include <linux/errno.h> +#include <linker_lists.h> #include <stdlib.h> +#include <tee/optee.h> #include <time.h> -/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3 - * USB controllers. Rather than requiring source level DT changes, we fix up - * DT here. This improves compatibility with upstream DT and simplifies the - * porting process for new devices. +/** + * find_ssphy_node() - Find the super-speed PHY node referenced by DWC3 + * @dwc3: DWC3 device node + * + * Returns: Pointer to SS-PHY node if found, NULL otherwise */ +static struct device_node *find_ssphy_node(struct device_node *dwc3) +{ + const __be32 *phandles; + const char *phy_name; + int len, i, ret; + + phandles = of_get_property(dwc3, "phys", &len); + if (!phandles) + return NULL; + + len /= sizeof(*phandles); + + /* Iterate through PHY phandles to find the SS-PHY */ + for (i = 0; i < len; i++) { + ret = of_property_read_string_index(dwc3, "phy-names", i, &phy_name); + if (ret) + continue; + + /* Check if this is the super-speed PHY */ + if (!strncmp("usb3-phy", phy_name, strlen("usb3-phy")) || + !strncmp("usb3_phy", phy_name, strlen("usb3_phy"))) { + return of_find_node_by_phandle(NULL, be32_to_cpu(phandles[i])); + } + } + + return NULL; +} + +/** + * has_driver_for_node() - Check if any PHY driver can bind to this node + * @np: Device node to check + * + * Returns: true if a PHY driver with matching compatible string exists, false otherwise + */ +static bool has_driver_for_node(struct device_node *np) +{ + struct driver *driver = ll_entry_start(struct driver, driver); + const int n_ents = ll_entry_count(struct driver, driver); + const char *compat_list, *compat; + int compat_length, i; + struct driver *entry; + + if (!np) + return false; + + /* Get compatible strings from the node */ + compat_list = of_get_property(np, "compatible", &compat_length); + if (!compat_list) + return false; + + /* Check each compatible string against PHY drivers only */ + for (i = 0; i < compat_length; i += strlen(compat) + 1) { + compat = compat_list + i; + + /* Iterate through all registered drivers */ + for (entry = driver; entry != driver + n_ents; entry++) { + const struct udevice_id *of_match = entry->of_match; + + /* Skip non-PHY drivers to improve performance */ + if (entry->id != UCLASS_PHY) + continue; + + if (!of_match) + continue; + + while (of_match->compatible) { + if (!strcmp(of_match->compatible, compat)) { + debug("Found PHY driver '%s' for SS-PHY compatible '%s'\n", + entry->name, compat); + return true; + } + of_match++; + } + } + } + + return false; +} + static int fixup_qcom_dwc3(struct device_node *root, struct device_node *glue_np, bool flat) { - struct device_node *dwc3; + struct device_node *dwc3, *ssphy_np; int ret, len, hsphy_idx = 1; const __be32 *phandles; const char *second_phy_name; - debug("Fixing up %s\n", glue_np->name); - /* New DT flattens the glue and controller into a single node. */ if (flat) { dwc3 = glue_np; @@ -54,30 +136,43 @@ static int fixup_qcom_dwc3(struct device_node *root, struct device_node *glue_np } } - /* Tell the glue driver to configure the wrapper for high-speed only operation */ - ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL); - if (ret) { - log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': %d\n", ret); - return ret; - } + debug("Checking USB configuration for %s\n", dwc3->name); phandles = of_get_property(dwc3, "phys", &len); len /= sizeof(*phandles); if (len == 1) { - log_debug("Only one phy, not a superspeed controller\n"); + debug("Only one phy, not a superspeed controller\n"); return 0; } - /* Figure out if the superspeed phy is present and if so then which phy is it? */ + /* Figure out if the superspeed phy is present */ ret = of_property_read_string_index(dwc3, "phy-names", 1, &second_phy_name); if (ret == -ENODATA) { - log_debug("Only one phy, not a super-speed controller\n"); + debug("Only one phy, not a super-speed controller\n"); return 0; } else if (ret) { log_err("Failed to read second phy name: %d\n", ret); return ret; } + /* Find the super-speed PHY node and check if a driver is available */ + ssphy_np = find_ssphy_node(dwc3); + if (ssphy_np && has_driver_for_node(ssphy_np)) { + debug("Skipping USB fixup for %s (SS-PHY driver available)\n", + dwc3->name); + return 0; + } + + /* No driver available - apply the fixup */ + debug("Applying USB high-speed fixup to %s\n", dwc3->name); + + /* Tell the glue driver to configure the wrapper for high-speed only operation */ + ret = of_write_prop(dwc3, "qcom,select-utmi-as-pipe-clk", 0, NULL); + if (ret) { + log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': %d\n", ret); + return ret; + } + /* * Determine which phy is the superspeed phy by checking the name of the second phy * since it is typically the superspeed one. @@ -134,33 +229,34 @@ static void fixup_usb_nodes(struct device_node *root) } } -/* Remove all references to the rpmhpd device */ -static void fixup_power_domains(struct device_node *root) +static void add_optee_node(struct device_node *root) { - struct device_node *pd = NULL, *np = NULL; - struct property *prop; - const __be32 *val; + struct device_node *fw = NULL, *optee = NULL; + int ret; - /* All Qualcomm platforms name the rpm(h)pd "power-controller" */ - for_each_of_allnodes_from(root, pd) { - if (pd->name && !strcmp("power-controller", pd->name)) - break; + fw = of_find_node_by_path("/firmware"); + if (!fw) { + log_err("Failed to find /firmware node\n"); + return; } - /* Sanity check that this is indeed a power domain controller */ - if (!of_find_property(pd, "#power-domain-cells", NULL)) { - log_err("Found power-controller but it doesn't have #power-domain-cells\n"); + ret = of_add_subnode(fw, "optee", strlen("optee") + 1, &optee); + if (ret) { + log_err("Failed to add 'optee' subnode: %d\n", ret); return; } - /* Remove all references to the power domain controller */ - for_each_of_allnodes_from(root, np) { - if (!(prop = of_find_property(np, "power-domains", NULL))) - continue; + ret = of_write_prop(optee, "compatible", strlen("linaro,optee-tz") + 1, + "linaro,optee-tz"); + if (ret) { + log_err("Failed to add optee 'compatible' property: %d\n", ret); + return; + } - val = prop->value; - if (val[0] == cpu_to_fdt32(pd->phandle)) - of_remove_property(np, prop); + ret = of_write_prop(optee, "method", strlen("smc") + 1, "smc"); + if (ret) { + log_err("Failed to add optee 'method' property: %d\n", ret); + return; } } @@ -176,7 +272,9 @@ static int qcom_of_fixup_nodes(void * __maybe_unused ctx, struct event *event) struct device_node *root = event->data.of_live_built.root; time_call(fixup_usb_nodes, root); - time_call(fixup_power_domains, root); + + if (IS_ENABLED(CONFIG_OPTEE) && is_optee_smc_api()) + time_call(add_optee_node, root); return 0; } diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index de9d8547e61..1c6de559142 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -10,7 +10,6 @@ config STM32F4 select PINCTRL_STM32 select RAM select STM32_RCC - select STM32_RESET select STM32_SDRAM select STM32_SERIAL select STM32_TIMER @@ -27,7 +26,6 @@ config STM32F7 select PINCTRL_STM32 select RAM select STM32_RCC - select STM32_RESET select STM32_SDRAM select STM32_SERIAL select STM32_TIMER @@ -47,7 +45,6 @@ config STM32H7 select RAM select REGMAP select STM32_RCC - select STM32_RESET select STM32_SDRAM select STM32_SERIAL select STM32_TIMER diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 31b2746379d..39f25869c1d 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -50,7 +50,6 @@ config STM32MP13X select OF_BOARD_SETUP select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select SUPPORT_SPL if !TFABOOT select SYS_ARCH_TIMER @@ -72,7 +71,6 @@ config STM32MP15X select OF_BOARD_SETUP select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select SUPPORT_SPL select SYS_ARCH_TIMER @@ -91,7 +89,6 @@ config STM32MP21X select OF_BOARD select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select STM32MP_TAMP_NVMEM select SYS_ARCH_TIMER @@ -117,7 +114,6 @@ config STM32MP23X select OF_BOARD select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select STM32MP_TAMP_NVMEM select SYS_ARCH_TIMER @@ -143,7 +139,6 @@ config STM32MP25X select OF_BOARD select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select SYS_ARCH_TIMER select TFABOOT diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 7f349f3b68d..42e3735847a 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -135,6 +135,9 @@ enum forced_boot_mode { /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) +#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) +#define TAMP_FWU_BOOT_IDX_OFFSET 0 + #ifdef CONFIG_STM32MP15X #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) @@ -144,9 +147,6 @@ enum forced_boot_mode { #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) -#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) - -#define TAMP_FWU_BOOT_IDX_OFFSET 0 #define TAMP_COPRO_STATE_OFF 0 #define TAMP_COPRO_STATE_INIT 1 #define TAMP_COPRO_STATE_CRUN 2 @@ -196,8 +196,6 @@ enum forced_boot_mode { /* TAMP registers zone 3 RIF 1 (RW) at 96*/ #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) -#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) -#define TAMP_FWU_BOOT_IDX_OFFSET 0 #endif /* defined(CONFIG_STM32MP21X) || defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */ /* offset used for BSEC driver: misc_read and misc_write */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index a875907ac3e..05ce869c428 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -61,20 +61,20 @@ /* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ #define CPU_STM32MP257Cxx 0x00002000 #define CPU_STM32MP255Cxx 0x00082000 -#define CPU_STM32MP253Cxx 0x000B2004 -#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP253Cxx 0x000B300C +#define CPU_STM32MP251Cxx 0x000B306D #define CPU_STM32MP257Axx 0x40002E00 #define CPU_STM32MP255Axx 0x40082E00 -#define CPU_STM32MP253Axx 0x400B2E04 -#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP253Axx 0x400B3E0C +#define CPU_STM32MP251Axx 0x400B3E6D #define CPU_STM32MP257Fxx 0x80002000 #define CPU_STM32MP255Fxx 0x80082000 -#define CPU_STM32MP253Fxx 0x800B2004 -#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP253Fxx 0x800B300C +#define CPU_STM32MP251Fxx 0x800B306D #define CPU_STM32MP257Dxx 0xC0002E00 #define CPU_STM32MP255Dxx 0xC0082E00 -#define CPU_STM32MP253Dxx 0xC00B2E04 -#define CPU_STM32MP251Dxx 0xC00B3E65 +#define CPU_STM32MP253Dxx 0xC00B3E0C +#define CPU_STM32MP251Dxx 0xC00B3E6D /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); diff --git a/arch/arm/mach-stm32mp/soc.c b/arch/arm/mach-stm32mp/soc.c index fa56b0d2e0f..67be55e3381 100644 --- a/arch/arm/mach-stm32mp/soc.c +++ b/arch/arm/mach-stm32mp/soc.c @@ -64,7 +64,7 @@ __weak int setup_mac_address(void) struct udevice *dev; int nb_eth, nb_otp, index; - if (!IS_ENABLED(CONFIG_NET)) + if (!IS_ENABLED(CONFIG_NET_LEGACY)) return 0; nb_eth = get_eth_nb(); diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index e63bdaaf42f..d2e41b8e65f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -90,11 +90,6 @@ void spl_display_print(void) } #endif -__weak int board_early_init_f(void) -{ - return 0; -} - uint32_t stm32mp_get_dram_size(void) { struct ram_info ram; @@ -204,10 +199,12 @@ void board_init_f(ulong dummy) /* enable console uart printing */ preloader_console_init(); - ret = board_early_init_f(); - if (ret) { - log_debug("board_early_init_f() failed: %d\n", ret); - hang(); + if (IS_ENABLED(CONFIG_BOARD_EARLY_INIT_F)) { + ret = board_early_init_f(); + if (ret) { + log_debug("board_early_init_f() failed: %d\n", ret); + hang(); + } } ret = uclass_get_device(UCLASS_RAM, 0, &dev); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 89f0e77bcdb..ceba96b61a5 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -151,7 +151,6 @@ config DRAM_SUNXI_TPR3 config DRAM_SUNXI_TPR6 hex "DRAM TPR6 parameter" - default 0x3300c080 help TPR6 value from vendor DRAM settings. @@ -1245,15 +1244,17 @@ config SPL_SUNXI_LED_STATUS if SPL_SUNXI_LED_STATUS -config SPL_SUNXI_LED_STATUS_BIT +config SPL_SUNXI_LED_STATUS_GPIO int "GPIO number for GPIO status LED" help GPIO number for the GPIO controlling the GPIO status LED in SPL. -config SPL_SUNXI_LED_STATUS_STATE - bool "GPIO status LED initial state is on" +config SPL_SUNXI_LED_STATUS_ACTIVE_HIGH + bool "GPIO status LED is active high" + default y help - Whether the initial state of the status LED in SPL must be on or off. + Whether the GPIO of the status LED must be set high or low to turn + the LED on. endif # SPL_SUNXI_LED_STATUS diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 3345c9b8e82..42a0550e015 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -975,7 +975,7 @@ static bool mctl_phy_init(const struct dram_para *para, val = para->tpr6 & 0xff; break; case SUNXI_DRAM_TYPE_LPDDR3: - val = para->tpr6 >> 8 & 0xff; + val = para->tpr6 >> 16 & 0xff; break; case SUNXI_DRAM_TYPE_LPDDR4: val = para->tpr6 >> 24 & 0xff; diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index 9a02fe40733..a81609cdec7 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -18,7 +18,11 @@ DECLARE_GLOBAL_DATA_PTR; +#if CONFIG_IS_ENABLED(PCIE_DW_AMD) +#define VERSAL2_MEM_MAP_USED 6 +#else #define VERSAL2_MEM_MAP_USED 5 +#endif #define DRAM_BANKS CONFIG_NR_DRAM_BANKS @@ -60,6 +64,16 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN +#if CONFIG_IS_ENABLED(PCIE_DW_AMD) + }, { + /* PCIe DBI (1 MB) and config space (255 MB) are contiguous */ + .virt = 0x100000000000UL, + .phys = 0x100000000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN +#endif } }; @@ -69,7 +83,7 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { * @num_banks: Number of valid DRAM banks in bank_info array * * Copies DRAM bank information into the global versal2_mem_map[] array - * starting at index VERSAL2_MEM_MAP_USED (5), which is after the fixed + * starting at index VERSAL2_MEM_MAP_USED, which is after the fixed * device mappings. This must be called early in boot before MMU * initialization so that get_page_table_size() can calculate the * required page table size based on actual memory configuration. diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 6ce8f577e3a..00e89bd0a62 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -62,6 +62,7 @@ config MCF5441x select DM select DM_SERIAL select ARCH_COLDFIRE + select CREATE_ARCH_SYMLINK bool config M680x0 diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index f0264671d38..ae0e7c35d87 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -114,7 +114,7 @@ vector192_255: /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ asm_sbf_img_hdr: .long 0x00000000 /* checksum, not yet implemented */ - .long 0x00040000 /* image length */ + .long CONFIG_SYS_MONITOR_LEN /* image length */ .long CONFIG_TEXT_BASE /* image to be relocated at */ asm_dram_init: @@ -292,7 +292,6 @@ asm_dspi_rd_status: move.b (%a3), %d1 rts #endif /* CONFIG_CF_SBF */ - #ifdef CONFIG_SYS_NAND_BOOT /* copy 4 boot pages to dram as soon as possible */ /* each page is 996 bytes (1056 total with 60 ECC bytes */ diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi index dcca36312f5..7cd6072d4a5 100644 --- a/arch/m68k/dts/mcf5441x.dtsi +++ b/arch/m68k/dts/mcf5441x.dtsi @@ -163,5 +163,13 @@ clock-frequency = <100000>; status = "disabled"; }; + + esdhc: mmc@0xfc0cc000 { + compatible = "fsl,esdhc"; + reg = <0xfc0cc000 0x8000>; + non-removable; + bus-width = <4>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts index 3ba68b77d64..8e196fa65ff 100644 --- a/arch/m68k/dts/stmark2.dts +++ b/arch/m68k/dts/stmark2.dts @@ -45,3 +45,7 @@ &i2c0 { status = "okay"; }; + +&esdhc { + status = "okay"; +}; diff --git a/arch/m68k/include/asm/arch-mcf5445x/clock.h b/arch/m68k/include/asm/arch-mcf5445x/clock.h new file mode 100644 index 00000000000..10ceecafcea --- /dev/null +++ b/arch/m68k/include/asm/arch-mcf5445x/clock.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ColdFire clock support + * + * Copyright 2026 Kernelspace. + * Angelo Dureghello <[email protected]> + */ + +#ifndef __CLOCK_H +#define __CLOCK_H + +/* Stub to use fsl/nxp drivers. */ +enum mxc_clock { + MXC_ESDHC_CLK, +}; + +int mxc_get_clock(enum mxc_clock clk); + +#endif /* __CLOCK_H */ diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index cf93715637a..9ad67c4272c 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -9,3 +9,4 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o ashrdi3.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_ARCH_COLDFIRE) += cache.o interrupts.o time.o traps.o bdinfo.o fec.o +obj-$(CONFIG_MCF5441x) += clock.o diff --git a/arch/m68k/lib/clock.c b/arch/m68k/lib/clock.c new file mode 100644 index 00000000000..5d9aeed96c3 --- /dev/null +++ b/arch/m68k/lib/clock.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2026 Kernelspace + * Angelo Dureghello <[email protected]> + */ + +#include <config.h> +#include <asm/arch/clock.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; +/* + * Stub to use existing nxp/fsl drivers. + */ +int mxc_get_clock(enum mxc_clock clk) +{ + if (clk == MXC_ESDHC_CLK) + return gd->arch.sdhc_clk; + + printf("Unsupported MXC CLK: %d\n", clk); + + return 0; +} diff --git a/arch/mips/dts/mt7621-u-boot.dtsi b/arch/mips/dts/mt7621-u-boot.dtsi index fbac2ade25a..a6e585a0853 100644 --- a/arch/mips/dts/mt7621-u-boot.dtsi +++ b/arch/mips/dts/mt7621-u-boot.dtsi @@ -47,13 +47,13 @@ &binman { u-boot-spl-ddr { - align = <4>; - align-size = <4>; + align = <8>; + align-size = <8>; filename = "u-boot-spl-ddr.bin"; pad-byte = <0xff>; u-boot-spl { - align-end = <4>; + align-end = <8>; filename = "u-boot-spl.bin"; }; @@ -90,7 +90,7 @@ #ifndef CONFIG_MT7621_BOOT_FROM_NAND u-boot-tpl { - align-end = <4>; + align-end = <8>; filename = "u-boot-tpl.bin"; }; #endif diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 55152ab227e..cb564b32c07 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1375,7 +1375,7 @@ config SYS_L3_SIZE int default 262144 if SYS_L3_SIZE_256KB default 524288 if SYS_L3_SIZE_512KB - default 1048576 if SYS_L3_SIZE_512KB + default 1048576 if SYS_L3_SIZE_1024KB config SYS_PPC64 bool diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 739d14f8002..414782c835f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -41,10 +41,12 @@ #ifdef CONFIG_FSL_CAAM #include <fsl_sec.h> #endif -#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_FSL_CORENET) #include <asm/fsl_pamu.h> +#if defined(CONFIG_NXP_ESBC) #include <fsl_secboot_err.h> #endif +#endif #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include <nand.h> #include <errno.h> @@ -899,6 +901,8 @@ int cpu_init_r(void) #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) if (pamu_init() < 0) fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#elif defined(CONFIG_FSL_CORENET) + pamu_init(); #endif #ifdef CONFIG_FSL_CAAM diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 766b0c05951..4fd3478ac2f 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -14,7 +14,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb -dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi deleted file mode 100644 index ad09b138fc8..00000000000 --- a/arch/powerpc/dts/p2041.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P2041 Silicon/SoC Device Tree Source (pre include) - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/dts-v1/; - -/include/ "e500mc_power_isa.dtsi" - -/ { - compatible = "fsl,P2041"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: PowerPC,e500mc@0 { - device_type = "cpu"; - reg = <0>; - fsl,portid-mapping = <0x80000000>; - }; - cpu1: PowerPC,e500mc@1 { - device_type = "cpu"; - reg = <1>; - fsl,portid-mapping = <0x40000000>; - }; - cpu2: PowerPC,e500mc@2 { - device_type = "cpu"; - reg = <2>; - fsl,portid-mapping = <0x20000000>; - }; - cpu3: PowerPC,e500mc@3 { - device_type = "cpu"; - reg = <3>; - fsl,portid-mapping = <0x10000000>; - }; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "simple-bus"; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <4>; - reg = <0x40000 0x40000>; - compatible = "fsl,mpic", "chrp,open-pic"; - device_type = "open-pic"; - clock-frequency = <0x0>; - }; - - espi0: spi@110000 { - compatible = "fsl,mpc8536-espi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x110000 0x1000>; - fsl,espi-num-chipselects = <4>; - status = "disabled"; - }; - - usb0: usb@210000 { - compatible = "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - phy_type = "utmi"; - }; - - usb1: usb@211000 { - compatible = "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - phy_type = "utmi"; - }; - - sata: sata@220000 { - compatible = "fsl,pq-sata-v2"; - reg = <0x220000 0x1000>; - interrupts = <68 0x2 0 0>; - sata-offset = <0x1000>; - sata-number = <2>; - sata-fpdma = <0>; - }; - - esdhc: esdhc@114000 { - compatible = "fsl,esdhc"; - reg = <0x114000 0x1000>; - clock-frequency = <0>; - }; - - /include/ "qoriq-i2c-0.dtsi" - /include/ "qoriq-i2c-1.dtsi" - }; - - pcie@ffe200000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ - law_trgt_if = <0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe201000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ - law_trgt_if = <1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe202000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ - law_trgt_if = <2>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; -}; diff --git a/arch/powerpc/dts/p2041rdb-u-boot.dtsi b/arch/powerpc/dts/p2041rdb-u-boot.dtsi new file mode 100644 index 00000000000..1dc83cf846b --- /dev/null +++ b/arch/powerpc/dts/p2041rdb-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&serial0 { + bootph-all; +}; + +&soc { + i2c@118000 { + bootph-all; + }; + + spi@110000 { + flash@0 { + spi-max-frequency = <10000000>; + }; + }; +}; + +#include "u-boot.dtsi" diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts deleted file mode 100644 index 0fa1f098524..00000000000 --- a/arch/powerpc/dts/p2041rdb.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P2041RDB Device Tree Source - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/include/ "p2041.dtsi" - -/ { - model = "fsl,P2041RDB"; - compatible = "fsl,P2041RDB"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - aliases { - phy_rgmii_0 = &phy_rgmii_0; - phy_rgmii_1 = &phy_rgmii_1; - phy_sgmii_2 = &phy_sgmii_2; - phy_sgmii_3 = &phy_sgmii_3; - phy_sgmii_4 = &phy_sgmii_4; - phy_sgmii_1c = &phy_sgmii_1c; - phy_sgmii_1d = &phy_sgmii_1d; - phy_sgmii_1e = &phy_sgmii_1e; - phy_sgmii_1f = &phy_sgmii_1f; - phy_xgmii_2 = &phy_xgmii_2; - spi0 = &espi0; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - - fman@400000 { - ethernet@e0000 { - phy-handle = <&phy_sgmii_2>; - phy-connection-type = "sgmii"; - }; - - mdio@e1120 { - phy_rgmii_0: ethernet-phy@0 { - reg = <0x0>; - }; - - phy_rgmii_1: ethernet-phy@1 { - reg = <0x1>; - }; - - phy_sgmii_2: ethernet-phy@2 { - reg = <0x2>; - }; - - phy_sgmii_3: ethernet-phy@3 { - reg = <0x3>; - }; - - phy_sgmii_4: ethernet-phy@4 { - reg = <0x4>; - }; - - phy_sgmii_1c: ethernet-phy@1c { - reg = <0x1c>; - }; - - phy_sgmii_1d: ethernet-phy@1d { - reg = <0x1d>; - }; - - phy_sgmii_1e: ethernet-phy@1e { - reg = <0x1e>; - }; - - phy_sgmii_1f: ethernet-phy@1f { - reg = <0x1f>; - }; - }; - - ethernet@e2000 { - phy-handle = <&phy_sgmii_3>; - phy-connection-type = "sgmii"; - }; - - ethernet@e4000 { - phy-handle = <&phy_sgmii_4>; - phy-connection-type = "sgmii"; - }; - - ethernet@e6000 { - phy-handle = <&phy_rgmii_1>; - phy-connection-type = "rgmii"; - }; - - ethernet@e8000 { - phy-handle = <&phy_rgmii_0>; - phy-connection-type = "rgmii"; - }; - - ethernet@f0000 { - phy-handle = <&phy_xgmii_2>; - phy-connection-type = "xgmii"; - }; - - mdio@f1000 { - phy_xgmii_2: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0x0>; - }; - }; - }; - }; -}; - -&espi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - /* input clock */ - spi-max-frequency = <10000000>; - }; -}; - -/include/ "p2041si-post.dtsi" diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi deleted file mode 100644 index 8819199646f..00000000000 --- a/arch/powerpc/dts/p2041si-post.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * P2041/P2040 Silicon/SoC Device Tree Source (post include) - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2020 NXP - * - */ - -&soc { - -/include/ "qoriq-clockgen1.dtsi" -/include/ "qoriq-gpio-0.dtsi" -/include/ "qoriq-sec4.2-0.dtsi" - -/* include used FMan blocks */ -/include/ "qoriq-fman-0.dtsi" -/include/ "qoriq-fman-0-1g-0.dtsi" -/include/ "qoriq-fman-0-1g-1.dtsi" -/include/ "qoriq-fman-0-1g-2.dtsi" -/include/ "qoriq-fman-0-1g-3.dtsi" -/include/ "qoriq-fman-0-1g-4.dtsi" -/include/ "qoriq-fman-0-10g-0.dtsi" - fman@400000 { - enet0: ethernet@e0000 { - }; - - enet1: ethernet@e2000 { - }; - - enet2: ethernet@e4000 { - }; - - enet3: ethernet@e6000 { - }; - - enet4: ethernet@e8000 { - }; - - enet5: ethernet@f0000 { - }; - }; -}; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index ac92ebf1afd..0887de4333b 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -16,6 +16,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/sandbox-pinmux.h> #include <dt-bindings/mux/mux.h> +#include <dt-bindings/phy/phy.h> / { model = "sandbox"; @@ -502,6 +503,65 @@ phy-names = "phy1"; }; + /* PHY common props test nodes */ + phy_common_props_missing: phy-common-props-missing { + /* empty: no rx-polarity or tx-polarity properties */ + }; + + phy_common_props_more_values: phy-common-props-more-values { + /* 3 values but only 2 names => count mismatch */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT PHY_POL_NORMAL>; + rx-polarity-names = "sgmii", "2500base-x"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT PHY_POL_NORMAL>; + tx-polarity-names = "sgmii", "2500base-x"; + }; + + phy_common_props_single: phy-common-props-single { + /* 1 value, no names array => value applies to all modes */ + rx-polarity = <PHY_POL_INVERT>; + tx-polarity = <PHY_POL_INVERT>; + }; + + phy_common_props_more_names: phy-common-props-more-names { + /* 2 values but 3 names => count mismatch */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + rx-polarity-names = "sgmii", "2500base-x", "1000base-x"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + tx-polarity-names = "sgmii", "2500base-x", "1000base-x"; + }; + + phy_common_props_find_by_name: phy-common-props-find-by-name { + /* valid 3-element arrays, lookup by mode name */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT PHY_POL_AUTO>; + rx-polarity-names = "sgmii", "2500base-x", "usb-ss"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT PHY_POL_NORMAL>; + tx-polarity-names = "sgmii", "2500base-x", "1000base-x"; + }; + + phy_common_props_no_default: phy-common-props-no-default { + /* name not in array, no "default" entry => -EINVAL */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + rx-polarity-names = "2500base-x", "1000base-x"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + tx-polarity-names = "2500base-x", "1000base-x"; + }; + + phy_common_props_with_default: phy-common-props-with-default { + /* name not in array, but "default" entry exists */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + rx-polarity-names = "2500base-x", "default"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + tx-polarity-names = "2500base-x", "default"; + }; + + phy_common_props_unsupported: phy-common-props-unsupported { + /* PHY_POL_AUTO is not supported for manual-only modes */ + rx-polarity = <PHY_POL_AUTO>; + rx-polarity-names = "sgmii"; + tx-polarity = <PHY_POL_AUTO>; + tx-polarity-names = "sgmii"; + }; + some-bus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 0e8d19ce232..0438790028b 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -244,6 +244,14 @@ uint sandbox_spi_get_speed(struct udevice *dev); uint sandbox_spi_get_mode(struct udevice *dev); /** + * sandbox_spi_get_wordlen() - Get current wordlen setting of a sandbox spi slave + * + * @dev: Device to check + * Return: current wordlen + */ +uint sandbox_spi_get_wordlen(struct udevice *dev); + +/** * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status * * @dev: Device to check |