diff options
Diffstat (limited to 'arch')
569 files changed, 32595 insertions, 36092 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index e28e4c4bce7..8d63afeb138 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -11,14 +11,14 @@ config HAVE_ARCH_IOREMAP config HAVE_SETJMP bool help - The architecture supports setjmp() and longjmp(). + The architecture supports setjmp() and longjmp(). config HAVE_INITJMP bool depends on HAVE_SETJMP help - The architecture supports initjmp(), a non-standard companion to - setjmp() and longjmp(). + The architecture supports initjmp(), a non-standard companion to + setjmp() and longjmp(). config SUPPORT_BIG_ENDIAN bool @@ -457,11 +457,11 @@ config SYS_CONFIG_NAME config SYS_DISABLE_DCACHE_OPS bool help - This option disables dcache flush and dcache invalidation - operations. For example, on coherent systems where cache - operatios are not required, enable this option to avoid them. - Note that, its up to the individual architectures to implement - this functionality. + This option disables dcache flush and dcache invalidation + operations. For example, on coherent systems where cache + operatios are not required, enable this option to avoid them. + Note that, its up to the individual architectures to implement + this functionality. config SYS_IMMR hex "Address for the Internal Memory-Mapped Registers (IMMR) window" diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index ef9087d0197..152692e3230 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -242,24 +242,28 @@ config VOL_MONITOR_IR36021_SET config VOL_MONITOR_LTC3882_READ bool "Enable the LTC3882 voltage monitor read" + select PMBUS help This option enables LTC3882 voltage monitor read functionality. It is used by the common VID driver. config VOL_MONITOR_LTC3882_SET bool "Enable the LTC3882 voltage monitor set" + select PMBUS help This option enables LTC3882 voltage monitor set functionality. It is used by the common VID driver. config VOL_MONITOR_ISL68233_READ bool "Enable the ISL68233 voltage monitor read" + select PMBUS help This option enables ISL68233 voltage monitor read functionality. It is used by the common VID driver. config VOL_MONITOR_ISL68233_SET bool "Enable the ISL68233 voltage monitor set" + select PMBUS help This option enables ISL68233 voltage monitor set functionality. It is used by the common VID driver. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f624675eadf..1b474a346bf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -477,30 +477,30 @@ config SYS_THUMB_BUILD bool "Build U-Boot using the Thumb instruction set" depends on !ARM64 help - Use this flag to build U-Boot using the Thumb instruction set for - ARM architectures. Thumb instruction set provides better code - density. For ARM architectures that support Thumb2 this flag will - result in Thumb2 code generated by GCC. + Use this flag to build U-Boot using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. config SPL_SYS_THUMB_BUILD bool "Build SPL using the Thumb instruction set" default y if SYS_THUMB_BUILD depends on !ARM64 && SPL help - Use this flag to build SPL using the Thumb instruction set for - ARM architectures. Thumb instruction set provides better code - density. For ARM architectures that support Thumb2 this flag will - result in Thumb2 code generated by GCC. + Use this flag to build SPL using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. config TPL_SYS_THUMB_BUILD bool "Build TPL using the Thumb instruction set" default y if SYS_THUMB_BUILD depends on TPL && !ARM64 help - Use this flag to build TPL using the Thumb instruction set for - ARM architectures. Thumb instruction set provides better code - density. For ARM architectures that support Thumb2 this flag will - result in Thumb2 code generated by GCC. + Use this flag to build TPL using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. config SYS_L2_PL310 bool "ARM PL310 L2 cache controller" @@ -1082,6 +1082,7 @@ config ARCH_APPLE imply CMD_GPT imply BOOTSTD_FULL imply OF_HAS_PRIOR_STAGE + imply OF_UPSTREAM config ARCH_OWL bool "Actions Semi OWL SoCs" @@ -1582,7 +1583,7 @@ config TARGET_HIKEY select PL01X_SERIAL select SPECIFY_CONSOLE_INDEX imply CMD_DM - help + help Support for HiKey 96boards platform. It features a HI6220 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. @@ -1595,7 +1596,7 @@ config TARGET_HIKEY960 select OF_CONTROL select PL01X_SERIAL imply CMD_DM - help + help Support for HiKey960 96boards platform. It features a HI3660 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM. @@ -1608,7 +1609,7 @@ config TARGET_POPLAR select OF_CONTROL select PL01X_SERIAL imply CMD_DM - help + help Support for Poplar 96boards EE platform. It features a HI3798cv200 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU making it capable of running any commercial set-top solution based on @@ -1666,10 +1667,10 @@ config TARGET_LS1012AFRWY imply SCSI imply SCSI_AHCI help - Support for Freescale LS1012AFRWY platform. - The LS1012A FRWY board (FRWY) is a high-performance - development platform that supports the QorIQ LS1012A - Layerscape Architecture processor. + Support for Freescale LS1012AFRWY platform. + The LS1012A FRWY board (FRWY) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. config TARGET_LS1012AFRDM bool "Support ls1012afrdm" @@ -1777,9 +1778,9 @@ config TARGET_PG_WCOM_SELI8 select VENDOR_KM imply SCSI help - Support for Hitachi-Powergrids SELI8 service unit card. - SELI8 is a QorIQ LS1021a based service unit card used - in XMC20 and FOX615 product families. + Support for Hitachi-Powergrids SELI8 service unit card. + SELI8 is a QorIQ LS1021a based service unit card used + in XMC20 and FOX615 product families. config TARGET_PG_WCOM_EXPU1 bool "Support Hitachi-Powergrids EXPU1 service unit card" @@ -1795,9 +1796,9 @@ config TARGET_PG_WCOM_EXPU1 select VENDOR_KM imply SCSI help - Support for Hitachi-Powergrids EXPU1 service unit card. - EXPU1 is a QorIQ LS1021a based service unit card used - in XMC20 and FOX615 product families. + Support for Hitachi-Powergrids EXPU1 service unit card. + EXPU1 is a QorIQ LS1021a based service unit card used + in XMC20 and FOX615 product families. config TARGET_LS1021ATSN bool "Support ls1021atsn" @@ -2152,6 +2153,13 @@ config ARCH_ASPEED select OF_CONTROL imply CMD_DM +config ARCH_AXIADO + bool "Support Axiado SoCs" + select AXIADO_AX3005 + help + Support for Axiado AX-series SoCs such as the AX3005. + These ARM64 SoCs are used in BMC and security applications. + config TARGET_DURIAN bool "Support Phytium Durian Platform" select ARM64 @@ -2172,8 +2180,8 @@ config TARGET_POMELO select DM_SERIAL imply CMD_PCI help - Support for pomelo platform. - It has 8GB Sdram, uart and pcie. + Support for pomelo platform. + It has 8GB Sdram, uart and pcie. config TARGET_PE2201 bool "Support Phytium PE2201 Platform" @@ -2293,6 +2301,8 @@ source "arch/arm/mach-aspeed/Kconfig" source "arch/arm/mach-at91/Kconfig" +source "arch/arm/mach-axiado/Kconfig" + source "arch/arm/mach-bcm283x/Kconfig" source "arch/arm/mach-bcmbca/Kconfig" diff --git a/arch/arm/config.mk b/arch/arm/config.mk index a7eff84a267..bce9a31e966 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -112,6 +112,14 @@ endif # needed for relocation LDFLAGS_u-boot += -pie +ifeq ($(CONFIG_ARM64),y) +# U-Boot uses fixed 4K granules, so we force the linker to match. +# Otherwise, we're subject to toolchain preferences, (e.g Fedora's +# aarch64-linux-none toolchain selects 64K granules) and we end up wasting +# a lot of space in ELFs with MMU_PGPROT enabled. +LDFLAGS_u-boot += -z common-page-size=0x1000 -z max-page-size=0x1000 +endif + # # FIXME: binutils versions < 2.22 have a bug in the assembler where # branches to weak symbols can be incorrectly optimized in thumb mode diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 0df501e91db..6bd95a5185b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -26,7 +26,7 @@ MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg # quiet_cmd_mkivt_mxs = MXSIVT $@ cmd_mkivt_mxs = \ - sz=`expr \`stat -c "%s" $^\` + 64 + 3904 + 128` ; \ + sz=`expr \`stat -c "%s" $<\` + 64 + 3904 + 128` ; \ echo -n "0x402000d1 $2 0 0 0 $3 $4 0 $$sz 0 0 0 0 0 0 0" | \ tr -s " " | xargs -d " " -i printf "%08x\n" "{}" | rev | \ sed "s/\(.\)\(.\)/\\\\\\\\x\2\1\n/g" | xargs -i printf "{}" >$@ @@ -34,15 +34,15 @@ cmd_mkivt_mxs = \ # Align binary to 64B quiet_cmd_mkalign_mxs = MXSALGN $@ cmd_mkalign_mxs = \ - dd if=$^ of=$@ ibs=64 conv=sync 2>/dev/null && \ - mv $@ $^ + dd if=$< of=$@ ibs=64 conv=sync 2>/dev/null && \ + mv $@ $< # Assemble the CSF file quiet_cmd_mkcsfreq_mxs = MXSCSFR $@ cmd_mkcsfreq_mxs = \ - ivt=$(word 1,$^) ; \ - bin=$(word 2,$^) ; \ - csf=$(word 3,$^) ; \ + ivt=$(word 1,$(real-prereqs)) ; \ + bin=$(word 2,$(real-prereqs)) ; \ + csf=$(word 3,$(real-prereqs)) ; \ sed "s@VENDOR@$(VENDOR)@g;s@BOARD@$(BOARD)@g" "$$csf" | \ sed '/^\#\#Blocks/ d' > $@ ; \ echo " Blocks = $2 0x0 `stat -c '%s' $$bin` \"$$bin\" , \\" >> $@ ; \ @@ -50,7 +50,7 @@ cmd_mkcsfreq_mxs = \ # Sign files quiet_cmd_mkcst_mxs = MXSCST $@ -cmd_mkcst_mxs = cst -o $@ < $^ \ +cmd_mkcst_mxs = cst -o $@ < $< \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) spl/u-boot-spl.ivt: spl/u-boot-spl.bin FORCE diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 3a3c1784e18..18e7aed94d9 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -13,19 +13,19 @@ config ARMV7_NONSEC bool "Enable support for booting in non-secure mode" if EXPERT depends on CPU_V7_HAS_NONSEC default y - ---help--- - Say Y here to enable support for booting in non-secure / SVC mode. + help + Say Y here to enable support for booting in non-secure / SVC mode. config ARMV7_BOOT_SEC_DEFAULT bool "Boot in secure mode by default" if EXPERT depends on ARMV7_NONSEC default y if ARCH_TEGRA - ---help--- - Say Y here to boot in secure mode by default even if non-secure mode - is supported. This option is useful to boot kernels which do not - suppport booting in non-secure mode. Only set this if you need it. - This can be overridden at run-time by setting the bootm_boot_mode env. - variable to "sec" or "nonsec". + help + Say Y here to boot in secure mode by default even if non-secure mode + is supported. This option is useful to boot kernels which do not + support booting in non-secure mode. Only set this if you need it. + This can be overridden at run-time by setting the bootm_boot_mode env. + variable to "sec" or "nonsec". config HAS_ARMV7_SECURE_BASE bool "Enable support for a hardware secure memory area" @@ -74,8 +74,8 @@ config ARMV7_VIRT bool "Enable support for hardware virtualization" if EXPERT depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC default y - ---help--- - Say Y here to boot in hypervisor (HYP) mode when booting non-secure. + help + Say Y here to boot in hypervisor (HYP) mode when booting non-secure. config ARMV7_PSCI bool "Enable PSCI support" if EXPERT @@ -115,9 +115,9 @@ config ARMV7_LPAE bool "Use LPAE page table format" if EXPERT depends on CPU_V7A default y if ARMV7_VIRT - ---help--- - Say Y here to use the long descriptor page table format. This is - required if U-Boot runs in HYP mode. + help + Say Y here to use the long descriptor page table format. This is + required if U-Boot runs in HYP mode. config ARMV7_SET_CORTEX_SMPEN bool diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 5c8839583aa..9ce94555ed0 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -100,9 +100,9 @@ config SYS_FSL_ERRATUM_A008407 config SYS_FSL_QSPI_SKIP_CLKSEL bool "Skip setting QSPI clock during SoC init" help - To improve startup times when booting from QSPI flash, the QSPI - frequency can be set very early in the boot process. If this option - is enabled, the QSPI frequency will not be changed by U-Boot during - SoC initialization. + To improve startup times when booting from QSPI flash, the QSPI + frequency can be set very early in the boot process. If this option + is enabled, the QSPI frequency will not be changed by U-Boot during + SoC initialization. endmenu diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 34eea22eb92..09092ea7b7f 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -16,7 +16,6 @@ #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif -#include <tsec.h> #include <asm/arch/immap_ls102xa.h> #include <fsl_sec.h> #include <dm.h> @@ -26,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; void ft_fixup_enet_phy_connect_type(void *fdt) { struct udevice *dev; - struct tsec_private *priv; + struct eth_pdata *pdata; const char *enet_path, *phy_path; char enet[16]; char phy[16]; @@ -45,8 +44,8 @@ void ft_fixup_enet_phy_connect_type(void *fdt) continue; } - priv = dev_get_priv(dev); - if (priv->flags & TSEC_SGMII) + pdata = dev_get_plat(dev); + if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII) continue; enet_path = fdt_get_alias(fdt, enet); diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index dfc4ce851c3..7e4e3bdd66c 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -23,11 +23,11 @@ config ARMV8_SPL_EXCEPTION_VECTORS and want to save some space at the cost of less debugging info. config ARMV8_MULTIENTRY - bool "Enable multiple CPUs to enter into U-Boot" + bool "Enable multiple CPUs to enter into U-Boot" config ARMV8_SET_SMPEN - bool "Enable data coherency with other cores in cluster" - help + bool "Enable data coherency with other cores in cluster" + help Say Y here if there is not any trust firmware to set CPUECTLR_EL1.SMPEN bit before U-Boot. @@ -79,12 +79,12 @@ config ARMV8_SEC_FIRMWARE_SUPPORT process brief. Note: Only FIT format image is supported. You should prepare and provide the below information: - - Address of secure firmware. - - Address to hold the return address from secure firmware. - - Secure firmware FIT image related information. - Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME - - The target exception level that secure monitor firmware will - return to. + - Address of secure firmware. + - Address to hold the return address from secure firmware. + - Secure firmware FIT image related information. + Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME + - The target exception level that secure monitor firmware will + return to. config SPL_ARMV8_SEC_FIRMWARE_SUPPORT bool "Enable ARMv8 secure monitor firmware framework support for SPL" diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 39479df7b21..e59528e576e 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -69,9 +69,9 @@ int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs) } for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - mem_map[index].virt = gd->bd->bi_dram[i].start; - mem_map[index].phys = gd->bd->bi_dram[i].start; - mem_map[index].size = gd->bd->bi_dram[i].size; + mem_map[index].virt = gd->dram[i].start; + mem_map[index].phys = gd->dram[i].start; + mem_map[index].size = gd->dram[i].size; mem_map[index].attrs = attrs; index++; } @@ -163,7 +163,7 @@ u64 get_tcr(u64 *pips, u64 *pva_bits) static int pte_type(u64 *pte) { - return *pte & PTE_TYPE_MASK; + return *pte & PTE_TYPE_VALID ? *pte & PTE_TYPE_MASK : PTE_TYPE_FAULT; } /* Returns the LSB number for a PTE on level <level> */ @@ -534,7 +534,7 @@ static void __pagetable_walk(u64 addr, u64 tcr, int level, pte_walker_cb_t cb, v if (exit) return; - if (pte_type(&pte) == PTE_TYPE_FAULT) + if (!pte) continue; attrs = pte & ALL_ATTRS; @@ -573,7 +573,7 @@ static void __pagetable_walk(u64 addr, u64 tcr, int level, pte_walker_cb_t cb, v /* Go down a level */ __pagetable_walk(_addr, tcr, level + 1, cb, priv); state[level] = WALKER_STATE_START; - } else if (pte_type(&pte) == PTE_TYPE_BLOCK || pte_type(&pte) == PTE_TYPE_PAGE) { + } else { /* We foud a block or page, start walking */ entry_start = pte; state[level] = WALKER_STATE_REGION; @@ -734,6 +734,66 @@ void dump_pagetable(u64 ttbr, u64 tcr) walk_pagetable(ttbr, tcr, pagetable_print_entry, NULL); } +/* Do a software pagetable walk for the given address */ +void tlb_debug_lookup(u64 addr) +{ + u64 va_bits; + u64 ttbr = gd->arch.tlb_addr, *pte; + int lshift, level; + + get_tcr(NULL, &va_bits); + level = va_bits < 39 ? 1 : 0; + + printf("Performing software TLB lookup of address %#010llx va_bits: %lld\n", + addr, va_bits); + + addr = ALIGN_DOWN(addr, 0x1000); + pte = ((u64 *)ttbr); + for (int i = level; i < 4; i++) { + int indent = (i - level + 1) * 2; + u32 idx; + u64 _addr; + + lshift = level2shift(i); + idx = (addr >> lshift) & 0x1FF; + + printf("%*sPTE: %#010llx. addr[%d:%d]: %#05x (offset %#07x)\n", indent, "", (u64)pte, + lshift + 8, lshift, idx, idx * 8); + printf("%*sL%d: %#010llx -> ", indent, "", i, (u64)(&pte[idx])); + + pte = &pte[idx]; + _addr = *pte & GENMASK_ULL(va_bits, PAGE_SHIFT); + + /* + * Check the PTE and either descend if it's a table or print + * the mapping and return. + */ + switch (pte_type(pte)) { + case PTE_TYPE_FAULT: + printf("UNMAPPED!\n"); + return; + case PTE_TYPE_BLOCK: + printf("BLOCK (%#010llx)\n", _addr); + break; + case PTE_TYPE_TABLE: + if (i < 3) { + printf("TABLE (%#010llx)\n", _addr); + pte = (u64 *)_addr; + continue; + } else { /* PTE_TYPE_PAGE */ + printf("PAGE (%#010llx)\n", _addr); + } + break; + default: + printf("Unknown (%#010llx)\n", _addr); + break; + } + + printf("%*s[%#010llx - %#010llx]\n", indent + 2, "", _addr, _addr + (1 << lshift)); + return; + } +} + /* Returns the estimated required size of all page tables */ __weak u64 get_page_table_size(void) { @@ -810,8 +870,10 @@ __weak void mmu_setup(void) el = current_el(); set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL), MEMORY_ATTRIBUTES); +} - /* enable the mmu */ +void mmu_enable(void) +{ set_sctlr(get_sctlr() | CR_M); } @@ -881,6 +943,7 @@ void dcache_enable(void) if (!mmu_status()) { __asm_invalidate_tlb_all(); mmu_setup(); + mmu_enable(); } /* Set up page tables only once (it is done also by mmu_setup()) */ @@ -928,9 +991,10 @@ u64 *__weak arch_get_page_table(void) { return NULL; } +/* Checks if the current PTE is an aligned subset of the region */ static bool is_aligned(u64 addr, u64 size, u64 align) { - return !(addr & (align - 1)) && !(size & (align - 1)); + return !(addr & (align - 1)) && size >= align; } /* Use flag to indicate if attrs has more than d-cache attributes */ @@ -940,9 +1004,14 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level) u64 levelsize = 1ULL << levelshift; u64 *pte = find_pte(start, level); - /* Can we can just modify the current level block PTE? */ + /* Can we can just modify the current level block/page? */ if (is_aligned(start, size, levelsize)) { - if (flag) { + if (attrs == PTE_TYPE_FAULT) { + if (pte_type(pte) == PTE_TYPE_TABLE && level < 3) + *pte = 0; + else + *pte &= ~(PTE_TYPE_MASK); + } else if (flag) { *pte &= ~PMD_ATTRMASK; *pte |= attrs & PMD_ATTRMASK; } else { @@ -970,6 +1039,28 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level) return 0; } +static void set_regions(u64 start, u64 size, u64 attrs, bool flag) +{ + int level; + u64 r; + + /* + * Loop through the address range until we find a page granule that fits + * our alignment constraints, then set it to the new cache attributes + */ + while (size > 0) { + for (level = 1; level < 4; level++) { + r = set_one_region(start, size, attrs, flag, level); + if (r) { + /* PTE successfully replaced */ + size -= r; + start += r; + break; + } + } + } +} + void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { @@ -989,26 +1080,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, */ __asm_switch_ttbr(gd->arch.tlb_emerg); - /* - * Loop through the address range until we find a page granule that fits - * our alignment constraints, then set it to the new cache attributes - */ - while (size > 0) { - int level; - u64 r; - - for (level = 1; level < 4; level++) { - /* Set d-cache attributes only */ - r = set_one_region(start, size, attrs, false, level); - if (r) { - /* PTE successfully replaced */ - size -= r; - start += r; - break; - } - } - - } + set_regions(start, size, attrs, false); /* We're done modifying page tables, switch back to our primary ones */ __asm_switch_ttbr(gd->arch.tlb_addr); @@ -1020,29 +1092,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, flush_dcache_range(real_start, real_start + real_size); } -void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs) +void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t size, u64 attrs) { - int level; - u64 r, size, start; - - /* - * Loop through the address range until we find a page granule that fits - * our alignment constraints and set the new permissions - */ - start = addr; - size = siz; - while (size > 0) { - for (level = 1; level < 4; level++) { - /* Set PTE to new attributes */ - r = set_one_region(start, size, attrs, true, level); - if (r) { - /* PTE successfully updated */ - size -= r; - start += r; - break; - } - } - } + set_regions(addr, size, attrs, true); flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); __asm_invalidate_tlb_all(); @@ -1053,36 +1105,19 @@ void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs) * The procecess is break-before-make. The target region will be marked as * invalid during the process of changing. */ -void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +void mmu_change_region_attr(phys_addr_t addr, size_t size, u64 attrs) { - int level; - u64 r, size, start; - - start = addr; - size = siz; - /* - * Loop through the address range until we find a page granule that fits - * our alignment constraints, then set it to "invalid". - */ - while (size > 0) { - for (level = 1; level < 4; level++) { - /* Set PTE to fault */ - r = set_one_region(start, size, PTE_TYPE_FAULT, true, - level); - if (r) { - /* PTE successfully invalidated */ - size -= r; - start += r; - break; - } - } - } + set_regions(addr, size, PTE_TYPE_FAULT, true); flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); __asm_invalidate_tlb_all(); - mmu_change_region_attr_nobreak(addr, siz, attrs); + /* If we were unmapping a region then we have nothing to make and can return. */ + if (attrs == PTE_TYPE_FAULT) + return; + + mmu_change_region_attr_nobreak(addr, size, attrs); } int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 4c5b38e3b65..2335c776c2e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -440,8 +440,8 @@ config MAX_CPUS config EMC2305 bool "Fan controller" help - Enable the EMC2305 fan controller for configuration of fan - speed. + Enable the EMC2305 fan controller for configuration of fan + speed. config QSPI_AHB_INIT bool "Init the QSPI AHB bus" @@ -548,7 +548,7 @@ config SYS_FSL_PCLK_DIV help This is the divider that is used to derive Platform clock from Platform PLL, in another word: - Platform_clk = Platform_PLL_freq / this_divider + Platform_clk = Platform_PLL_freq / this_divider config SYS_FSL_DSPI_CLK_DIV int "DSPI clock divider" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cfbaa475701..88adcf35432 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,16 +538,16 @@ static inline void final_mmu_setup(void) */ switch (final_map[index].virt) { case CFG_SYS_FSL_DRAM_BASE1: - final_map[index].virt = gd->bd->bi_dram[0].start; - final_map[index].phys = gd->bd->bi_dram[0].start; - final_map[index].size = gd->bd->bi_dram[0].size; + final_map[index].virt = gd->dram[0].start; + final_map[index].phys = gd->dram[0].start; + final_map[index].size = gd->dram[0].size; break; #ifdef CFG_SYS_FSL_DRAM_BASE2 case CFG_SYS_FSL_DRAM_BASE2: #if (CONFIG_NR_DRAM_BANKS >= 2) - final_map[index].virt = gd->bd->bi_dram[1].start; - final_map[index].phys = gd->bd->bi_dram[1].start; - final_map[index].size = gd->bd->bi_dram[1].size; + final_map[index].virt = gd->dram[1].start; + final_map[index].phys = gd->dram[1].start; + final_map[index].size = gd->dram[1].size; #else final_map[index].size = 0; #endif @@ -556,9 +556,9 @@ static inline void final_mmu_setup(void) #ifdef CFG_SYS_FSL_DRAM_BASE3 case CFG_SYS_FSL_DRAM_BASE3: #if (CONFIG_NR_DRAM_BANKS >= 3) - final_map[index].virt = gd->bd->bi_dram[2].start; - final_map[index].phys = gd->bd->bi_dram[2].start; - final_map[index].size = gd->bd->bi_dram[2].size; + final_map[index].virt = gd->dram[2].start; + final_map[index].phys = gd->dram[2].start; + final_map[index].size = gd->dram[2].size; #else final_map[index].size = 0; #endif @@ -986,6 +986,27 @@ uint get_svr(void) } #endif +/* + * Layerscape mirror of the i.MX get_cpu_temp_grade(). i.MX reads the + * OCOTP "CPU temp grade" fuses; Layerscape has no such fuse, so the + * limits come from the data sheet instead. LX2160A Reference Manual + * Rev. 1 (10/2021) section 1.12.1 specifies the maximum operating + * junction temperature at 105 degC for commercial / embedded parts; + * the lower bound is the standard -40 degC commercial low. + * + * The TMU itself is documented as accurate within +/- 3 degC (RM + * section 28.1), which the thermal driver clears by setting its + * alert threshold 10 degC below critical. + */ +u32 get_cpu_temp_grade(int *minc, int *maxc) +{ + if (minc) + *minc = -40; + if (maxc) + *maxc = 105; + return 0; /* commercial */ +} + #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { @@ -1143,7 +1164,7 @@ int arch_early_init_r(void) #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif -#ifdef CONFIG_SYS_FSL_HAS_RGMII +#if defined(CONFIG_SYS_FSL_HAS_RGMII) && defined(CONFIG_FSL_MC_ENET) /* some dpmacs in armv8a based freescale layerscape SOCs can be * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via * EC*_PMUX(rgmii) bits in RCW. @@ -1158,6 +1179,10 @@ int arch_early_init_r(void) * function of SOC, the dpmac will be enabled as RGMII even if it was * also enabled before as SGMII. If ECx_PMUX is not configured for * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init(). + * + * fsl_rgmii_init() itself is only built under CONFIG_FSL_MC_ENET + * (drivers/net/ldpaa_eth/); gate the call the same way so builds + * without MC-ENET still link. */ fsl_rgmii_init(); #endif @@ -1371,10 +1396,10 @@ static int tfa_dram_init_banksize(void) } debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2); - gd->bd->bi_dram[i].start = res.a1; - gd->bd->bi_dram[i].size = res.a2; + gd->dram[i].start = res.a1; + gd->dram[i].size = res.a2; - dram_size -= gd->bd->bi_dram[i].size; + dram_size -= gd->dram[i].size; i++; } while (dram_size); @@ -1385,24 +1410,24 @@ static int tfa_dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1439,30 +1464,30 @@ int dram_init_banksize(void) } #endif - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - + gd->dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; + gd->dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; + gd->dram[1].size = gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; - gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - + if (gd->dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { + gd->dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; + gd->dram[2].size = gd->dram[1].size - CONFIG_SYS_DDR_BLOCK2_SIZE; - gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; + gd->dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; } #endif } else { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; } #ifdef CFG_SYS_MEM_RESERVE_SECURE - if (gd->bd->bi_dram[0].size > + if (gd->dram[0].size > CFG_SYS_MEM_RESERVE_SECURE) { - gd->bd->bi_dram[0].size -= + gd->dram[0].size -= CFG_SYS_MEM_RESERVE_SECURE; - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size; + gd->arch.secure_ram = gd->dram[0].start + + gd->dram[0].size; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE; } @@ -1471,24 +1496,24 @@ int dram_init_banksize(void) #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ #ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->bd->bi_dram[2].size >= - board_reserve_ram_top(gd->bd->bi_dram[2].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[2].start + - gd->bd->bi_dram[2].size - - board_reserve_ram_top(gd->bd->bi_dram[2].size); + if (gd->dram[2].size >= + board_reserve_ram_top(gd->dram[2].size)) { + gd->arch.resv_ram = gd->dram[2].start + + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->bd->bi_dram[1].size >= - board_reserve_ram_top(gd->bd->bi_dram[1].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[1].start + - gd->bd->bi_dram[1].size - - board_reserve_ram_top(gd->bd->bi_dram[1].size); - } else if (gd->bd->bi_dram[0].size > - board_reserve_ram_top(gd->bd->bi_dram[0].size)) { - gd->arch.resv_ram = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - - board_reserve_ram_top(gd->bd->bi_dram[0].size); + if (gd->dram[1].size >= + board_reserve_ram_top(gd->dram[1].size)) { + gd->arch.resv_ram = gd->dram[1].start + + gd->dram[1].size - + board_reserve_ram_top(gd->dram[1].size); + } else if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); } } #endif /* CONFIG_RESV_RAM */ @@ -1510,8 +1535,8 @@ int dram_init_banksize(void) CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; + gd->dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->dram[2].size = dp_ddr_size; } else { puts("Not detected"); } @@ -1542,14 +1567,15 @@ void lmb_arch_add_memory(void) if (i == 2) continue; /* skip DP-DDR */ #endif - ram_start = gd->bd->bi_dram[i].start; - ram_size = gd->bd->bi_dram[i].size; + ram_start = gd->dram[i].start; + ram_size = gd->dram[i].size; #ifdef CONFIG_RESV_RAM if (gd->arch.resv_ram >= ram_start && gd->arch.resv_ram < ram_start + ram_size) ram_size = gd->arch.resv_ram - ram_start; #endif - lmb_add(ram_start, ram_size); + if (ram_size > 0) + lmb_add(ram_start, ram_size); } } #endif diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 87de09979b1..f834d770dd6 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -129,3 +129,18 @@ void __noreturn psci_system_off(void) while (1) ; } + +int psci_features(u32 psci_func_id) +{ + struct pt_regs regs; + + regs.regs[0] = ARM_PSCI_1_0_FN_PSCI_FEATURES; + regs.regs[1] = psci_func_id; + + if (use_smc_for_psci) + smc_call(®s); + else + hvc_call(®s); + + return regs.regs[0]; +} diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 8e2266a90fe..98b0306f3b2 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -96,7 +96,7 @@ SECTIONS { KEEP(*(.__secure_stack_start)) - /* Skip addreses for stack */ + /* Skip addresses for stack */ . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; /* Align end of stack section to page boundary */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4085d4c2de1..25234697e6a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb +dtb-$(CONFIG_TARGET_SCM3005) += ax3005-scm3005.dtb dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb @@ -32,13 +33,6 @@ dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb -dtb-$(CONFIG_ARCH_APPLE) += \ - t8103-j274.dtb \ - t8103-j293.dtb \ - t8103-j313.dtb \ - t8103-j456.dtb \ - t8103-j457.dtb - dtb-$(CONFIG_ARCH_DAVINCI) += \ da850-lcdk.dtb \ da850-lego-ev3.dtb @@ -52,12 +46,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_RK3128) += \ - rk3128-evb.dtb - -dtb-$(CONFIG_ROCKCHIP_RK322X) += \ - rk3229-evb.dtb - dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ @@ -144,6 +132,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-388-gp.dtb \ armada-388-helios4.dtb \ armada-38x-controlcenterdc.dtb \ + armada-xp-atl-x220.dtb \ armada-xp-crs305-1g-4s.dtb \ armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \ @@ -169,6 +158,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-8040-clearfog-gt-8k.dtb \ armada-8040-db.dtb \ armada-8040-mcbin.dtb \ + armada-8040-nbx.dtb \ armada-8040-puzzle-m801.dtb \ cn9130-db-A.dtb \ cn9130-db-B.dtb \ @@ -403,26 +393,12 @@ dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb dtb-$(CONFIG_AM33XX) += \ am335x-baltos.dtb \ - am335x-bone.dtb \ - am335x-boneblack.dtb \ - am335x-boneblack-wireless.dtb \ - am335x-boneblue.dtb \ am335x-brppt1-mmc.dtb \ am335x-brxre1.dtb \ am335x-brsmarc1.dtb \ am335x-draco.dtb \ - am335x-evm.dtb \ - am335x-evmsk.dtb \ - am335x-bonegreen.dtb \ - am335x-bonegreen-eco.dtb \ - am335x-bonegreen-wireless.dtb \ - am335x-icev2.dtb \ - am335x-pocketbeagle.dtb \ am335x-pxm50.dtb \ am335x-rut.dtb \ - am335x-sancloud-bbe.dtb \ - am335x-sancloud-bbe-lite.dtb \ - am335x-sancloud-bbe-extended-wifi.dtb \ am335x-shc.dtb \ am335x-pdu001.dtb \ am335x-chiliboard.dtb \ @@ -874,13 +850,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-data-modul-edm-sbc.dtb \ - imx8mm-icore-mx8mm-ctouch2.dtb \ - imx8mm-icore-mx8mm-edimm2.2.dtb \ imx8mm-mx8menlo.dtb \ - imx8mm-phg.dtb \ imx8mq-cm.dtb \ - imx8mq-mnt-reform2.dtb \ - imx8mq-phanbell.dtb \ imx8mp-data-modul-edm-sbc.dtb \ imx8mp-dhcom-som-overlay-rev100.dtbo \ imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ @@ -888,16 +859,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ imx8mp-dhcom-drc02.dtb \ imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ - imx8mp-dhcom-picoitx.dtb \ - imx8mp-icore-mx8mp-edimm2.2.dtb \ - imx8mp-msc-sm2s.dtb \ - imx8mq-pico-pi.dtb \ - imx8mq-kontron-pitx-imx8m.dtb \ - imx8mq-librem5-r4.dtb - -dtb-$(CONFIG_ARCH_IMX9) += \ - imx93-11x11-frdm.dtb \ - imx93-var-som-symphony.dtb + imx8mp-dhcom-picoitx.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ @@ -906,12 +868,11 @@ dtb-$(CONFIG_RZA1) += \ r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb -dtb-$(CONFIG_RCAR_GEN5) += \ - r8a78000-ironhide.dtb +dtb-$(CONFIG_RCAR_GEN3) += \ + r8a779md-geist.dtb -ifdef CONFIG_RCAR_GEN5 -DTC_FLAGS += -R 4 -p 0x1000 -endif +dtb-$(CONFIG_RCAR_GEN5) += \ + r8a78000-ironhide-cm33.dtb dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb @@ -1063,6 +1024,8 @@ dtb-$(CONFIG_ASPEED_AST2600) += \ ast2600-evb.dtb \ ast2600-sbp1.dtb \ ast2600-x4tf.dtb +dtb-$(CONFIG_ASPEED_AST2700) += \ + ast2700-evb.dtb dtb-$(CONFIG_STM32MP15X) += \ stm32mp157c-odyssey.dtb @@ -1079,8 +1042,7 @@ dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\ k3-j721s2-r5-common-proc-board.dtb -dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-aquila-dev.dtb \ - k3-am69-r5-aquila-dev.dtb \ +dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-aquila-dev.dtb \ k3-am69-r5-sk.dtb \ k3-j784s4-r5-evm.dtb @@ -1105,6 +1067,9 @@ dtb-$(CONFIG_SOC_K3_AM62D2) += k3-am62d2-r5-evm.dtb dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \ k3-am62p5-verdin-r5.dtb +mt8371-genio-520-evk-ufs-dtbs := mt8371-genio-520-evk.dtb mt8371-genio-common-ufs.dtbo +mt8391-genio-720-evk-ufs-dtbs := mt8391-genio-720-evk.dtb mt8371-genio-common-ufs.dtbo + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ @@ -1125,7 +1090,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7988-sd-rfb.dtb \ mt8183-pumpkin.dtb \ mt8371-genio-520-evk.dtb \ + mt8371-genio-520-evk-ufs.dtb \ mt8391-genio-720-evk.dtb \ + mt8391-genio-720-evk-ufs.dtb \ mt8512-bm1-emmc.dtb \ mt8516-pumpkin.dtb \ mt8518-ap1-emmc.dtb @@ -1181,7 +1148,7 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \ imx8mm-cl-iot-gate-ied-tpm0.dtbo \ imx8mm-cl-iot-gate-ied-tpm1.dtbo -dtb-$(CONFIG_TARGET_SC573_EZKIT) += sc573-ezkit.dtb +dtb-$(CONFIG_TARGET_SC573_EZLITE) += sc573-ezlite.dtb dtb-$(CONFIG_TARGET_SC584_EZKIT) += sc584-ezkit.dtb dtb-$(CONFIG_TARGET_SC589_MINI) += sc589-mini.dtb dtb-$(CONFIG_TARGET_SC589_EZKIT) += sc589-ezkit.dtb diff --git a/arch/arm/dts/am335x-bone-common-u-boot.dtsi b/arch/arm/dts/am335x-bone-common-u-boot.dtsi new file mode 100644 index 00000000000..0fa2a311514 --- /dev/null +++ b/arch/arm/dts/am335x-bone-common-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-bone-common U-Boot Additions + * + * Common u-boot configuration for all BeagleBone variants + */ + +#include "am33xx-u-boot.dtsi" + +/ { + chosen { + tick-timer = &timer2; + }; +}; diff --git a/arch/arm/dts/am335x-bone-u-boot.dtsi b/arch/arm/dts/am335x-bone-u-boot.dtsi new file mode 100644 index 00000000000..11264707882 --- /dev/null +++ b/arch/arm/dts/am335x-bone-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-bone U-Boot Additions + */ + +#include "am335x-bone-common-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-bone.dts b/arch/arm/dts/am335x-bone.dts deleted file mode 100644 index b5d85ef51a0..00000000000 --- a/arch/arm/dts/am335x-bone.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" - -/ { - model = "TI AM335x BeagleBone"; - compatible = "ti,am335x-bone", "ti,am33xx"; -}; - -&ldo3_reg { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; -}; - -&mmc1 { - vmmc-supply = <&ldo3_reg>; -}; diff --git a/arch/arm/dts/am335x-boneblack-u-boot.dtsi b/arch/arm/dts/am335x-boneblack-u-boot.dtsi new file mode 100644 index 00000000000..366375bf446 --- /dev/null +++ b/arch/arm/dts/am335x-boneblack-u-boot.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-boneblack U-Boot Additions + */ + +#include "am335x-bone-common-u-boot.dtsi" + +&l4_per { + segment@300000 { + target-module@e000 { + bootph-all; + lcdc: lcdc@0 { + bootph-all; + }; + }; + }; +}; diff --git a/arch/arm/dts/am335x-boneblack-wireless-u-boot.dtsi b/arch/arm/dts/am335x-boneblack-wireless-u-boot.dtsi new file mode 100644 index 00000000000..c2cc9d93fd3 --- /dev/null +++ b/arch/arm/dts/am335x-boneblack-wireless-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-boneblack-wireless U-Boot Additions + */ + +#include "am335x-bone-common-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-boneblack-wireless.dts b/arch/arm/dts/am335x-boneblack-wireless.dts deleted file mode 100644 index afa4fdc5dd2..00000000000 --- a/arch/arm/dts/am335x-boneblack-wireless.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-boneblack-hdmi.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "TI AM335x BeagleBone Black Wireless"; - compatible = "ti,am335x-bone-black-wireless", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - /* WL_EN */ - gpio = <&gpio3 9 0>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - bt_pins: pinmux_bt_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_txd0.gpio0_28 - BT_EN */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ - >; - }; - - wl18xx_pins: pinmux_wl18xx_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gmii1_txclk.gpio3_9 WL_EN */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gmii1_rxclk.gpio3_10 LS_BUF_EN */ - >; - }; -}; - -&mac { - status = "disabled"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wl18xx_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <29 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &bt_pins>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio3 { - ls-buf-en-hog { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LS_BUF_EN"; - }; -}; diff --git a/arch/arm/dts/am335x-boneblack.dts b/arch/arm/dts/am335x-boneblack.dts deleted file mode 100644 index b956e2f60fe..00000000000 --- a/arch/arm/dts/am335x-boneblack.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-boneblack-hdmi.dtsi" - -/ { - model = "TI AM335x BeagleBone Black"; - compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&cpu0_opp_table { - /* - * All PG 2.0 silicon may not support 1GHz but some of the early - * BeagleBone Blacks have PG 2.0 silicon which is guaranteed - * to support 1GHz OPP so enable it for PG 2.0 on this board. - */ - oppnitro-1000000000 { - opp-supported-hw = <0x06 0x0100>; - }; -}; - -&gpio0 { - gpio-line-names = - "[mdio_data]", - "[mdio_clk]", - "P9_22 [spi0_sclk]", - "P9_21 [spi0_d0]", - "P9_18 [spi0_d1]", - "P9_17 [spi0_cs0]", - "[mmc0_cd]", - "P8_42A [ecappwm0]", - "P8_35 [lcd d12]", - "P8_33 [lcd d13]", - "P8_31 [lcd d14]", - "P8_32 [lcd d15]", - "P9_20 [i2c2_sda]", - "P9_19 [i2c2_scl]", - "P9_26 [uart1_rxd]", - "P9_24 [uart1_txd]", - "[rmii1_txd3]", - "[rmii1_txd2]", - "[usb0_drvvbus]", - "[hdmi cec]", - "P9_41B", - "[rmii1_txd1]", - "P8_19 [ehrpwm2a]", - "P8_13 [ehrpwm2b]", - "NC", - "NC", - "P8_14", - "P8_17", - "[rmii1_txd0]", - "[rmii1_refclk]", - "P9_11 [uart4_rxd]", - "P9_13 [uart4_txd]"; -}; - -&gpio1 { - gpio-line-names = - "P8_25 [mmc1_dat0]", - "[mmc1_dat1]", - "P8_5 [mmc1_dat2]", - "P8_6 [mmc1_dat3]", - "P8_23 [mmc1_dat4]", - "P8_22 [mmc1_dat5]", - "P8_3 [mmc1_dat6]", - "P8_4 [mmc1_dat7]", - "NC", - "NC", - "NC", - "NC", - "P8_12", - "P8_11", - "P8_16", - "P8_15", - "P9_15A", - "P9_23", - "P9_14 [ehrpwm1a]", - "P9_16 [ehrpwm1b]", - "[emmc rst]", - "[usr0 led]", - "[usr1 led]", - "[usr2 led]", - "[usr3 led]", - "[hdmi irq]", - "[usb vbus oc]", - "[hdmi audio]", - "P9_12", - "P8_26", - "P8_21 [emmc]", - "P8_20 [emmc]"; -}; - -&gpio2 { - gpio-line-names = - "P9_15B", - "P8_18", - "P8_7", - "P8_8", - "P8_10", - "P8_9", - "P8_45 [hdmi]", - "P8_46 [hdmi]", - "P8_43 [hdmi]", - "P8_44 [hdmi]", - "P8_41 [hdmi]", - "P8_42 [hdmi]", - "P8_39 [hdmi]", - "P8_40 [hdmi]", - "P8_37 [hdmi]", - "P8_38 [hdmi]", - "P8_36 [hdmi]", - "P8_34 [hdmi]", - "[rmii1_rxd3]", - "[rmii1_rxd2]", - "[rmii1_rxd1]", - "[rmii1_rxd0]", - "P8_27 [hdmi]", - "P8_29 [hdmi]", - "P8_28 [hdmi]", - "P8_30 [hdmi]", - "[mmc0_dat3]", - "[mmc0_dat2]", - "[mmc0_dat1]", - "[mmc0_dat0]", - "[mmc0_clk]", - "[mmc0_cmd]"; -}; - -&gpio3 { - gpio-line-names = - "[mii col]", - "[mii crs]", - "[mii rx err]", - "[mii tx en]", - "[mii rx dv]", - "[i2c0 sda]", - "[i2c0 scl]", - "[jtag emu0]", - "[jtag emu1]", - "[mii tx clk]", - "[mii rx clk]", - "NC", - "NC", - "[usb vbus en]", - "P9_31 [spi1_sclk]", - "P9_29 [spi1_d0]", - "P9_30 [spi1_d1]", - "P9_28 [spi1_cs0]", - "P9_42B [ecappwm0]", - "P9_27", - "P9_41A", - "P9_25", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC"; -}; - -&baseboard_eeprom { - vcc-supply = <&ldo4_reg>; -}; diff --git a/arch/arm/dts/am335x-boneblue-u-boot.dtsi b/arch/arm/dts/am335x-boneblue-u-boot.dtsi new file mode 100644 index 00000000000..aae211eef5c --- /dev/null +++ b/arch/arm/dts/am335x-boneblue-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-boneblue U-Boot Additions + */ + +#include "am335x-bone-common-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-boneblue.dts b/arch/arm/dts/am335x-boneblue.dts deleted file mode 100644 index f04f46d6e5e..00000000000 --- a/arch/arm/dts/am335x-boneblue.dts +++ /dev/null @@ -1,617 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-osd335x-common.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "TI AM335x BeagleBone Blue"; - compatible = "ti,am335x-bone-blue", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - tick-timer = &timer2; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - usr_0_led { - label = "beaglebone:green:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - usr_1_led { - label = "beaglebone:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - usr_2_led { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - usr_3_led { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - wifi_led { - label = "wifi"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "phy0assoc"; - }; - - red_led { - label = "red"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - green_led { - label = "green"; - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_1_led { - label = "bat25"; - gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_2_led { - label = "bat50"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_3_led { - label = "bat75"; - gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - batt_4_led { - label = "bat100"; - gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - /* WL_EN */ - gpio = <&gpio3 9 0>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] - WIFI_LED */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7) /* (R7) gpmc_advn_ale.gpio2[2] - P8.7, LED_RED, GP1_PIN_5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE7) /* (T7) gpmc_oen_ren.gpio2[3] - P8.8, LED_GREEN, GP1_PIN_6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* (U12) gpmc_ad11.gpio0[27] - P8.17, BATT_LED_1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7) /* (T5) lcd_data15.gpio0[11] - P8.32, BATT_LED_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE7) /* (V6) gpmc_csn0.gpio1[29] - P8.26, BATT_LED_3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7) /* (T11) gpmc_ad10.gpio0[26] - P8.14, BATT_LED_4 */ - - >; - }; - - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ - >; - }; - - /* UT0 */ - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - /* UT1 */ - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - /* GPS */ - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (B17) spi0_d0.uart2_txd */ - >; - }; - - /* DSM2 */ - uart4_pins: pinmux_uart4_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ - >; - }; - - /* UT5 */ - uart5_pins: pinmux_uart5_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* (U2) lcd_data9.uart5_rxd */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* (U1) lcd_data8.uart5_txd */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* (U9) gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* (V9) gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* (U7) gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* (V7) gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* (R8) gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (T8) gpmc_ad3.mmc1_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* (U8) gpmc_ad4.mmc1_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* (V8) gpmc_ad5.mmc1_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* (R9) gpmc_ad6.mmc1_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* (T9) gpmc_ad7.mmc1_dat7 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6) /* (L15) gmii1_rxd1.mmc2_clk */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6) /* (J16) gmii1_txen.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5) /* (J17) gmii1_rxdv.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5) /* (J18) gmii1_txd3.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5) /* (K15) gmii1_txd2.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5) /* (H16) gmii1_col.mmc2_dat3 */ - >; - }; - - bt_pins: pinmux_bt_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* (M17) mdio_data.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* (M18) mdio_clk.uart3_rtsn */ - >; - }; - - wl18xx_pins: pinmux_wl18xx_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* (K16) gmii1_txd1.gpio0[21] - WL_IRQ */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* (L18) gmii1_rxclk.gpio3[10] - LS_BUF_EN */ - >; - }; - - /* DCAN */ - dcan1_pins: pinmux_dcan1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ - >; - }; - - /* E1 */ - eqep0_pins: pinmux_eqep0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */ - >; - }; - - /* E2 */ - eqep1_pins: pinmux_eqep1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */ - >; - }; - - /* E3 */ - eqep2_pins: pinmux_eqep2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&uart5_pins>; - - status = "okay"; -}; - -&usb0 { - dr_mode = "peripheral"; - interrupts-extended = <&intc 18 &tps 0>; - interrupt-names = "mc", "vbus"; -}; - -&usb1 { - dr_mode = "host"; -}; - -&i2c0 { - baseboard_eeprom: baseboard_eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - - #address-cells = <1>; - #size-cells = <1>; - baseboard_data: baseboard_data@0 { - reg = <0 0x100>; - }; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <400000>; - - mpu9250@68 { - compatible = "invensense,mpu9250"; - reg = <0x68>; - interrupt-parent = <&gpio3>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - ax8975@c { - compatible = "asahi-kasei,ak8975"; - reg = <0x0c>; - }; - }; - }; - - pressure@76 { - compatible = "bosch,bmp280"; - reg = <0x76>; - }; -}; - -/include/ "tps65217.dtsi" - -&tps { - /delete-property/ ti,pmic-shutdown-controller; - - charger { - interrupts = <0>, <1>; - interrupt-names = "USB", "AC"; - status = "okay"; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wl18xx_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <21 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&tscadc { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &bt_pins>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&rtc { - system-power-controller; - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; - -&dcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins>; - status = "okay"; -}; - -&gpio0 { - gpio-line-names = - "UART3_CTS", /* M17 */ - "UART3_RTS", /* M18 */ - "UART2_RX", /* A17 */ - "UART2_TX", /* B17 */ - "I2C1_SDA", /* B16 */ - "I2C1_SCL", /* A16 */ - "MMC0_CD", /* C15 */ - "SPI1_SS2", /* C18 */ - "EQEP_1A", /* V2 */ - "EQEP_1B", /* V3 */ - "MDIR_2B", /* V4 */ - "BATT_LED_2", /* T5 */ - "I2C2_SDA", /* D18 */ - "I2C2_SCL", /* D17 */ - "UART1_RX", /* D16 */ - "UART1_TX", /* D15 */ - "MMC2_DAT1", /* J18 */ - "MMC2_DAT2", /* K15 */ - "NC", /* F16 */ - "WIFI_LED", /* A15 */ - "MOT_STBY", /* D14 */ - "WLAN_IRQ", /* K16 */ - "PWM_2A", /* U10 */ - "PWM_2B", /* T10 */ - "", - "", - "BATT_LED_4", /* T11 */ - "BATT_LED_1", /* U12 */ - "BT_EN", /* K17 */ - "SPI1_SS1", /* H18 */ - "UART4_RX", /* T17 */ - "MDIR_1B"; /* U17 */ -}; - -&gpio1 { - gpio-line-names = - "MMC1_DAT0", /* U7 */ - "MMC1_DAT1", /* V7 */ - "MMC1_DAT2", /* R8 */ - "MMC1_DAT3", /* T8 */ - "MMC1_DAT4", /* U8 */ - "MMC1_DAT5", /* V8 */ - "MMC1_DAT6", /* R9 */ - "MMC1_DAT7", /* T9 */ - "DCAN1_TX", /* E18 */ - "DCAN1_RX", /* E17 */ - "UART0_RX", /* E15 */ - "UART0_TX", /* E16 */ - "EQEP_2A", /* T12 */ - "EQEP_2B", /* R12 */ - "PRU_E_A", /* V13 */ - "PRU_E_B", /* U13 */ - "MDIR_2A", /* R13 */ - "GPIO1_17", /* V14 */ - "PWM_1A", /* U14 */ - "PWM_1B", /* T14 */ - "EMMC_RST", /* R14 */ - "USR_LED_0", /* V15 */ - "USR_LED_1", /* U15 */ - "USR_LED_2", /* T15 */ - "USR_LED_3", /* V16 */ - "GPIO1_25", /* U16 */ - "MCASP0_AXR0", /* T16 */ - "MCASP0_AXR1", /* V17 */ - "MCASP0_ACLKR", /* U18 */ - "BATT_LED_3", /* V6 */ - "MMC1_CLK", /* U9 */ - "MMC1_CMD"; /* V9 */ -}; - -&gpio2 { - gpio-line-names = - "MDIR_1A", /* T13 */ - "MCASP0_FSR", /* V12 */ - "LED_RED", /* R7 */ - "LED_GREEN", /* T7 */ - "MODE_BTN", /* U6 */ - "PAUSE_BTN", /* T6 */ - "MDIR_4A", /* R1 */ - "MDIR_4B", /* R2 */ - "MDIR_3B", /* R3 */ - "MDIR_3A", /* R4 */ - "SVO7", /* T1 */ - "SVO8", /* T2 */ - "SVO5", /* T3 */ - "SVO6", /* T4 */ - "UART5_TX", /* U1 */ - "UART5_RX", /* U2 */ - "SERVO_EN", /* U3 */ - "NC", /* U4 */ - "UART3_RX", /* L17 */ - "UART3_TX", /* L16 */ - "MMC2_CLK", /* L15 */ - "DCAN1_SILENT", /* M16 */ - "SVO1", /* U5 */ - "SVO3", /* R5 */ - "SVO2", /* V5 */ - "SVO4", /* R6 */ - "MMC0_DAT3", /* F17 */ - "MMC0_DAT2", /* F18 */ - "MMC0_DAT1", /* G15 */ - "MMC0_DAT0", /* G16 */ - "MMC0_CLK", /* G17 */ - "MMC0_CMD"; /* G18 */ -}; - -&gpio3 { - gpio-line-names = - "MMC2_DAT3", /* H16 */ - "GPIO3_1", /* H17 */ - "GPIO3_2", /* J15 */ - "MMC2_CMD", /* J16 */ - "MMC2_DAT0", /* J17 */ - "I2C0_SDA", /* C17 */ - "I2C0_SCL", /* C16 */ - "EMU1", /* C14 */ - "EMU0", /* B14 */ - "WL_EN", /* K18 */ - "WL_BT_OE", /* L18 */ - "", - "", - "NC", /* F15 */ - "SPI1_SCK", /* A13 */ - "SPI1_MISO", /* B13 */ - "SPI1_MOSI", /* D12 */ - "GPIO3_17", /* C12 */ - "EQEP_0A", /* B12 */ - "EQEP_0B", /* C13 */ - "GPIO3_20", /* D13 */ - "IMU_INT", /* A14 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - ""; - - ls-buf-en-hog { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&eqep0 { - pinctrl-names = "default"; - pinctrl-0 = <&eqep0_pins>; - status = "okay"; -}; - -&epwmss1 { - status = "okay"; -}; - -&eqep1 { - pinctrl-names = "default"; - pinctrl-0 = <&eqep1_pins>; - status = "okay"; -}; - -&epwmss2 { - status = "okay"; -}; - -&eqep2 { - pinctrl-names = "default"; - pinctrl-0 = <&eqep2_pins>; - status = "okay"; -}; diff --git a/arch/arm/dts/am335x-bonegreen-eco-u-boot.dtsi b/arch/arm/dts/am335x-bonegreen-eco-u-boot.dtsi new file mode 100644 index 00000000000..e348f84d9be --- /dev/null +++ b/arch/arm/dts/am335x-bonegreen-eco-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-bonegreen-eco U-Boot Additions + */ + +#include "am335x-bone-common-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-bonegreen-eco.dts b/arch/arm/dts/am335x-bonegreen-eco.dts deleted file mode 100644 index 1e9d7fed3fd..00000000000 --- a/arch/arm/dts/am335x-bonegreen-eco.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2025 Bootlin - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-bonegreen-common.dtsi" -#include <dt-bindings/net/ti-dp83867.h> - -/ { - model = "TI AM335x BeagleBone Green Eco"; - compatible = "ti,am335x-bone-green-eco", "ti,am335x-bone-green", - "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; - - cpus { - cpu@0 { - /delete-property/ cpu0-supply; - }; - }; -}; - -&usb0 { - interrupts-extended = <&intc 18>; - interrupt-names = "mc"; -}; - -&cpsw_emac0 { - phy-mode = "rgmii-id"; - phy-handle = <&dp83867_0>; -}; - -&davinci_mdio { - /delete-node/ ethernet-phy@0; - - dp83867_0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&baseboard_eeprom { - /delete-property/ vcc-supply; -}; - -&i2c0 { - /delete-node/ tps@24; -}; diff --git a/arch/arm/dts/am335x-bonegreen-u-boot.dtsi b/arch/arm/dts/am335x-bonegreen-u-boot.dtsi new file mode 100644 index 00000000000..47e371a816f --- /dev/null +++ b/arch/arm/dts/am335x-bonegreen-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-bonegreen U-Boot Additions + */ + +#include "am335x-bone-common-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-bonegreen-wireless-u-boot.dtsi b/arch/arm/dts/am335x-bonegreen-wireless-u-boot.dtsi new file mode 100644 index 00000000000..b03e679ece4 --- /dev/null +++ b/arch/arm/dts/am335x-bonegreen-wireless-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-bonegreen-wireless U-Boot Additions + */ + +#include "am335x-bone-common-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-bonegreen-wireless.dts b/arch/arm/dts/am335x-bonegreen-wireless.dts deleted file mode 100644 index b363d032441..00000000000 --- a/arch/arm/dts/am335x-bonegreen-wireless.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-bonegreen-common.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "TI AM335x BeagleBone Green Wireless"; - compatible = "ti,am335x-bone-green-wireless", "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <70000>; - - /* WL_EN */ - gpio = <&gpio0 26 0>; - enable-active-high; - }; -}; - -&am33xx_pinmux { - bt_pins: pinmux_bt_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* gmii1_rxd2.uart3_txd */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3) /* mdio_data.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* mdio_clk.uart3_rtsn */ - >; - }; - - wl18xx_pins: pinmux_wl18xx_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 LS_BUF_EN */ - >; - }; -}; - -&mac { - status = "disabled"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wl18xx_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins &bt_pins>; - status = "okay"; - - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio1 { - ls-buf-en-hog { - gpio-hog; - gpios = <29 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "LS_BUF_EN"; - }; -}; - -/* BT_AUD_OUT from wl1835 has to be pulled low when WL_EN is activated.*/ -/* in case it isn't, wilink8 ends up in one of the test modes that */ -/* intruces various issues (elp wkaeup timeouts etc.) */ -/* On the BBGW this pin is routed through the level shifter (U21) that */ -/* introduces a pullup on the line and wilink8 ends up in a bad state. */ -/* use a gpio hog to force this pin low. An alternative may be adding */ -/* an external pulldown on U21 pin 4. */ - -&gpio3 { - bt-aud-in-hog { - gpio-hog; - gpios = <16 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "MCASP0_AHCLKR"; - }; -}; diff --git a/arch/arm/dts/am335x-bonegreen.dts b/arch/arm/dts/am335x-bonegreen.dts deleted file mode 100644 index 18cc0f49e99..00000000000 --- a/arch/arm/dts/am335x-bonegreen.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-bonegreen-common.dtsi" - -/ { - model = "TI AM335x BeagleBone Green"; - compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi b/arch/arm/dts/am335x-evm-u-boot.dtsi index 72402c82928..2ebf60bf7d6 100644 --- a/arch/arm/dts/am335x-evm-u-boot.dtsi +++ b/arch/arm/dts/am335x-evm-u-boot.dtsi @@ -5,6 +5,12 @@ #include "am33xx-u-boot.dtsi" +/ { + chosen { + tick-timer = &timer2; + }; +}; + &l4_per { bootph-all; segment@300000 { diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts deleted file mode 100644 index 1b5b6270068..00000000000 --- a/arch/arm/dts/am335x-evm.dts +++ /dev/null @@ -1,766 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "TI AM335x EVM"; - compatible = "ti,am335x-evm", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - tick-timer = &timer2; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - wlan_en_reg: fixedregulator2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - /* WLAN_EN GPIO for this board - Bank1, pin16 */ - gpio = <&gpio1 16 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; - - matrix_keypad: matrix_keypad@0 { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ - &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ - &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ - - col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ - &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ - - linux,keymap = <0x0000008b /* MENU */ - 0x0100009e /* BACK */ - 0x02000069 /* LEFT */ - 0x0001006a /* RIGHT */ - 0x0101001c /* ENTER */ - 0x0201006c>; /* DOWN */ - }; - - gpio_keys: volume-keys { - compatible = "gpio-keys"; - autorepeat; - - switch-9 { - label = "volume-up"; - linux,code = <115>; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - gpio-key,wakeup; - }; - - switch-10 { - label = "volume-down"; - linux,code = <114>; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - gpio-key,wakeup; - }; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&ecap0 0 50000 0>; - brightness-levels = <0 51 53 56 62 75 101 152 255>; - default-brightness-level = <8>; - }; - - panel { - compatible = "ti,tilcdc,panel"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins_s0>; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - - display-timings { - 800x480p62 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <39>; - hback-porch = <39>; - hsync-len = <47>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <2>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - }; - - sound { - compatible = "ti,da830-evm-audio"; - ti,model = "AM335x-EVM"; - ti,audio-codec = <&tlv320aic3106>; - ti,mcasp-controller = <&mcasp1>; - ti,codec-clock-rate = <12000000>; - ti,audio-routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; - - matrix_keypad_s0: matrix_keypad_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ - >; - }; - - volume_keys_s0: volume_keys_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ - >; - }; - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - nandflash_pins_s0: nandflash_pins_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) - >; - }; - - ecap0_pins: backlight_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ - >; - }; - - wlan_pins: pinmux_wlan_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ - >; - }; - - lcd_pins_s0: lcd_pins_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tsl2550: tsl2550@39 { - compatible = "taos,tsl2550"; - reg = <0x39>; - }; - - tmp275: tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tlv320aic3106: tlv320aic3106@1b { - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&vaux2_reg>; - IOVDD-supply = <&vaux2_reg>; - DRVDD-supply = <&vaux2_reg>; - DVDD-supply = <&vbat>; - }; -}; - -&lcdc { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -&epwmss0 { - status = "okay"; - - ecap0: pwm@100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap0_pins>; - }; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ - nand@0,0 { - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <8>; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x00020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000C0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001C0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001E0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00A00000 0x0F600000>; - }; - }; -}; - -#include "tps65910.dtsi" - -&mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcasp1_pins>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; - slaves = <1>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - ti,charge-delay = <0x400>; - }; - - adc { - ti,adc-channels = <4 5 6 7>; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&mmc3 { - /* these are on the crossbar and are outlined in the - xbar-event-map element */ - dmas = <&edma 12 0 - &edma 13 0>; - dma-names = "tx", "rx"; - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wlan_pins>; - ti,non-removable; - ti,needs-special-hs-handling; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio3>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&edma { - ti,edma-xbar-event-map = /bits/ 16 <1 12 - 2 13>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&dcan1 { - status = "disabled"; /* Enable only if Profile 1 is selected */ - pinctrl-names = "default"; - pinctrl-0 = <&dcan1_pins_default>; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; diff --git a/arch/arm/dts/am335x-evmsk-u-boot.dtsi b/arch/arm/dts/am335x-evmsk-u-boot.dtsi index 669cb6bf165..06ee1eb7c3e 100644 --- a/arch/arm/dts/am335x-evmsk-u-boot.dtsi +++ b/arch/arm/dts/am335x-evmsk-u-boot.dtsi @@ -7,6 +7,12 @@ #include "am33xx-u-boot.dtsi" +/ { + chosen { + tick-timer = &timer2; + }; +}; + &l4_per { segment@300000 { diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts deleted file mode 100644 index e0267657f90..00000000000 --- a/arch/arm/dts/am335x-evmsk.dts +++ /dev/null @@ -1,730 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * AM335x Starter Kit - * https://www.ti.com/tool/tmdssk3358 - */ - -/dts-v1/; - -#include "am33xx.dtsi" -#include <dt-bindings/pwm/pwm.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "TI AM335x EVM-SK"; - compatible = "ti,am335x-evmsk", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - tick-timer = &timer2; - }; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - lis3_reg: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "lis3_reg"; - regulator-boot-on; - }; - - wl12xx_vmmc: fixedregulator2 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 29 0>; - startup-delay-us = <70000>; - enable-active-high; - }; - - vtt_fixed: fixedregulator3 { - compatible = "regulator-fixed"; - regulator-name = "vtt"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds_s0>; - - compatible = "gpio-leds"; - - led1 { - label = "evmsk:green:usr0"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "evmsk:green:usr1"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "evmsk:green:mmc0"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led4 { - label = "evmsk:green:heartbeat"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - - gpio_buttons: gpio_buttons0 { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - switch1 { - label = "button0"; - linux,code = <0x100>; - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - }; - - switch2 { - label = "button1"; - linux,code = <0x101>; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - }; - - switch3 { - label = "button2"; - linux,code = <0x102>; - gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; - wakeup-source; - }; - - switch4 { - label = "button3"; - linux,code = <0x103>; - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; - }; - }; - - lcd_bl: backlight { - compatible = "pwm-backlight"; - pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 58 61 66 75 90 125 170 255>; - default-brightness-level = <8>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "AM335x-EVMSK"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound_master>; - simple-audio-card,frame-master = <&sound_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp1>; - }; - - sound_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - system-clock-frequency = <24000000>; - }; - }; - - panel { - compatible = "ti,tilcdc,panel"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_pins_default>; - pinctrl-1 = <&lcd_pins_sleep>; - status = "okay"; - panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; - }; - display-timings { - 480x272 { - hactive = <480>; - vactive = <272>; - hback-porch = <43>; - hfront-porch = <8>; - hsync-len = <4>; - vback-porch = <12>; - vfront-porch = <4>; - vsync-len = <10>; - clock-frequency = <9000000>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; - - lcd_pins_default: lcd_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - - lcd_pins_sleep: lcd_pins_sleep { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad8.lcd_data23 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad9.lcd_data22 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad10.lcd_data21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad11.lcd_data20 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.lcd_data19 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.lcd_data18 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.lcd_data17 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.lcd_data16 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - - user_leds_s0: user_leds_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad4.gpio1_4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad5.gpio1_5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad6.gpio1_6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad7.gpio1_7 */ - >; - }; - - gpio_keys_s0: gpio_keys_s0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_wait0.gpio0_30 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ - >; - }; - - ecap2_pins: backlight_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - - /* Slave 2 reset value*/ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ - >; - }; - - mcasp1_pins: mcasp1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ - >; - }; - - mcasp1_pins_sleep: mcasp1_pins_sleep { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */ - >; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - }; - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - - tlv320aic3106: tlv320aic3106@1b { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x1b>; - status = "okay"; - - /* Regulators */ - AVDD-supply = <&vaux2_reg>; - IOVDD-supply = <&vaux2_reg>; - DRVDD-supply = <&vaux2_reg>; - DVDD-supply = <&vbat>; - }; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; - -&epwmss2 { - status = "okay"; - - ecap2: pwm@100 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ecap2_pins>; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; - bus-width = <4>; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1271"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */ - ref-clock-frequency = <38400000>; - }; -}; - -&mcasp1 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp1_pins>; - pinctrl-1 = <&mcasp1_pins_sleep>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 0 1 2 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&tscadc { - status = "okay"; - tsc { - ti,wires = <4>; - ti,x-plate-resistance = <200>; - ti,coordinate-readouts = <5>; - ti,wire-config = <0x00 0x11 0x22 0x33>; - }; -}; - -&lcdc { - status = "okay"; -}; - -&rtc { - clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; - clock-names = "ext-clk", "int-clk"; -}; diff --git a/arch/arm/dts/am335x-icev2-u-boot.dtsi b/arch/arm/dts/am335x-icev2-u-boot.dtsi index ac1feaa9d9f..4ae100a3a7f 100644 --- a/arch/arm/dts/am335x-icev2-u-boot.dtsi +++ b/arch/arm/dts/am335x-icev2-u-boot.dtsi @@ -6,6 +6,10 @@ #include "am33xx-u-boot.dtsi" / { + chosen { + tick-timer = &timer2; + }; + xtal25mhz: xtal25mhz { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts deleted file mode 100644 index bcfdbb772c1..00000000000 --- a/arch/arm/dts/am335x-icev2.dts +++ /dev/null @@ -1,486 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/* - * AM335x ICE V2 board - * https://www.ti.com/tool/tmdsice3359 - */ - -/dts-v1/; - -#include "am33xx.dtsi" - -/ { - model = "TI AM3359 ICE-V2"; - compatible = "ti,am3359-icev2", "ti,am33xx"; - - chosen { - stdout-path = &uart3; - tick-timer = &timer2; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - vtt_fixed: fixedregulator1 { - compatible = "regulator-fixed"; - regulator-name = "vtt"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - }; - - leds-iio { - compatible = "gpio-leds"; - led-out0 { - label = "out0"; - gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out1 { - label = "out1"; - gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out2 { - label = "out2"; - gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out3 { - label = "out3"; - gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out4 { - label = "out4"; - gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out5 { - label = "out5"; - gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out6 { - label = "out6"; - gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-out7 { - label = "out7"; - gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - /* Tricolor status LEDs */ - leds1 { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>; - - led0 { - label = "status0:red:cpu0"; - gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "cpu0"; - }; - - led1 { - label = "status0:green:usr"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "status0:yellow:usr"; - gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - label = "status1:red:mmc0"; - gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "mmc0"; - }; - - led4 { - label = "status1:green:usr"; - gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led5 { - label = "status1:yellow:usr"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - user_leds: user_leds { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ - >; - }; - - mmc0_pins_default: mmc0_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */ - >; - }; - - i2c0_pins_default: i2c0_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) - >; - }; - - spi0_pins_default: spi0_pins_default { - pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ - AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ - AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ - >; - }; - - uart3_pins_default: uart3_pins_default { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1, RMII mode */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ - /* Slave 2, RMII mode */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wait0.rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_col.rmii2_refclk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a11.rmii2_rxd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a10.rmii2_rxd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_wpn.rmii2_rxerr */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a5.rmii2_txd0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a4.rmii2_txd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* gpmc_a0.rmii2_txen */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - - /* Slave 2 reset value */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_default>; - - status = "okay"; - clock-frequency = <400000>; - - tps: power-controller@2d { - reg = <0x2d>; - }; - - tpic2810: gpio@60 { - compatible = "ti,tpic2810"; - reg = <0x60>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins_default>; - - sn65hvs882@1 { - compatible = "pisosr-gpio"; - gpio-controller; - #gpio-cells = <2>; - - load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; - - reg = <1>; - spi-max-frequency = <1000000>; - spi-cpol; - }; - - spi_nor: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q64", "jedec,spi-nor"; - spi-max-frequency = <80000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "u-boot"; - reg = <0x80000 0x100000>; - read-only; - }; - - partition@2 { - label = "u-boot-env"; - reg = <0x180000 0x20000>; - read-only; - }; - - partition@3 { - label = "misc"; - reg = <0x1A0000 0x660000>; - }; - }; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1326000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1144000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmc_reg>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_default>; -}; - -&gpio0 { - /* Do not idle the GPIO used for holding the VTT regulator */ - ti,no-reset-on-init; - ti,no-idle-on-init; - - p7 { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "FET_SWITCH_CTRL"; - }; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; - status = "okay"; -}; - -&gpio3 { - pr1-mii-ctl-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "PR1_MII_CTRL"; - }; - - mux-mii-hog { - gpio-hog; - gpios = <10 GPIO_ACTIVE_HIGH>; - /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ - output-high; - line-name = "MUX_MII_CTRL"; - }; -}; - -&cpsw_emac0 { - phy-handle = <ðphy0>; - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy-handle = <ðphy1>; - phy-mode = "rmii"; - dual_emac_res_vlan = <2>; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; - dual_emac; -}; - -&phy_sel { - rmii-clock-ext; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; /* PHY datasheet states 1uS min */ - - ethphy0: ethernet-phy@1 { - reg = <1>; - }; - - ethphy1: ethernet-phy@3 { - reg = <3>; - }; -}; - diff --git a/arch/arm/dts/am335x-pocketbeagle-u-boot.dtsi b/arch/arm/dts/am335x-pocketbeagle-u-boot.dtsi new file mode 100644 index 00000000000..52c4bc26e12 --- /dev/null +++ b/arch/arm/dts/am335x-pocketbeagle-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-pocketbeagle U-Boot Additions + */ + +#include "am335x-bone-common-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-pocketbeagle.dts b/arch/arm/dts/am335x-pocketbeagle.dts deleted file mode 100644 index b379e3a5570..00000000000 --- a/arch/arm/dts/am335x-pocketbeagle.dts +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * Author: Robert Nelson <[email protected]> - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-osd335x-common.dtsi" - -/ { - model = "TI AM335x PocketBeagle"; - compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; - - chosen { - stdout-path = &uart0; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&usr_leds_pins>; - - compatible = "gpio-leds"; - - led-usr0 { - label = "beaglebone:green:usr0"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led-usr1 { - label = "beaglebone:green:usr1"; - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led-usr2 { - label = "beaglebone:green:usr2"; - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led-usr3 { - label = "beaglebone:green:usr3"; - gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&am33xx_pinmux { - i2c2_pins: pinmux-i2c2-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ - >; - }; - - ehrpwm0_pins: pinmux-ehrpwm0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ - >; - }; - - ehrpwm1_pins: pinmux-ehrpwm1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ - >; - }; - - mmc0_pins: pinmux-mmc0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ - >; - }; - - spi0_pins: pinmux-spi0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - spi1_pins: pinmux-spi1-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ - >; - }; - - usr_leds_pins: pinmux-usr-leds-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ - >; - }; - - uart0_pins: pinmux-uart0-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart4_pins: pinmux-uart4-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ - >; - }; -}; - -&epwmss0 { - status = "okay"; -}; - -&ehrpwm0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm0_pins>; -}; - -&epwmss1 { - status = "okay"; -}; - -&ehrpwm1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ehrpwm1_pins>; -}; - -&i2c0 { - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - - status = "okay"; - clock-frequency = <400000>; -}; - -&mmc1 { - status = "okay"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; -}; - -&rtc { - system-power-controller; -}; - -&tscadc { - status = "okay"; - adc { - ti,adc-channels = <0 1 2 3 4 5 6 7>; - ti,chan-step-avg = <16 16 16 16 16 16 16 16>; - ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; - ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins>; - - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "otg"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; - dr_mode = "host"; -}; - -&cppi41dma { - status = "okay"; -}; diff --git a/arch/arm/dts/am335x-sancloud-bbe-common.dtsi b/arch/arm/dts/am335x-sancloud-bbe-common.dtsi deleted file mode 100644 index 21b601fa4c1..00000000000 --- a/arch/arm/dts/am335x-sancloud-bbe-common.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ - -&am33xx_pinmux { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) - >; - }; - - usb_hub_ctrl: usb_hub_ctrl { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ - >; - }; -}; - -&mac { - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; -}; - -&cpsw_emac0 { - phy-mode = "rgmii-id"; -}; - -&i2c0 { - usb2512b: usb-hub@2c { - pinctrl-names = "default"; - pinctrl-0 = <&usb_hub_ctrl>; - compatible = "microchip,usb2512b"; - reg = <0x2c>; - reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; -}; diff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi-u-boot.dtsi b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi-u-boot.dtsi new file mode 100644 index 00000000000..17b86bdba3e --- /dev/null +++ b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * am335x-sancloud-bbe-extended-wifi U-Boot Additions + */ + +#include "am335x-sancloud-bbe-u-boot.dtsi" diff --git a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts deleted file mode 100644 index 271d1ab356c..00000000000 --- a/arch/arm/dts/am335x-sancloud-bbe-extended-wifi.dts +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2021 Sancloud Ltd - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-sancloud-bbe-common.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "SanCloud BeagleBone Enhanced Extended WiFi"; - compatible = "sancloud,am335x-boneenhanced", - "ti,am335x-bone-black", - "ti,am335x-bone", - "ti,am33xx"; - - wlan_en_reg: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - }; -}; - -&am33xx_pinmux { - mmc3_pins: pinmux_mmc3_pins { - pinctrl-single,pins = < - /* gpmc_a9.gpio1_25: RADIO_EN */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7) - - /* gpmc_ad12.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_ad13.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_ad14.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_ad15.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) - - /* gpmc_clk.mmc2_clk */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) - >; - }; - - bluetooth_pins: pinmux_bluetooth_pins { - pinctrl-single,pins = < - /* event_intr0.gpio0_19 */ - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - /* uart1_rxd */ - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) - - /* uart1_txd */ - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) - - /* uart1_ctsn */ - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) - - /* uart1_rtsn */ - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; -}; - -&i2c2 { - status = "disabled"; -}; - -&mmc3 { - status = "okay"; - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - non-removable; - cap-power-off-card; - ti,needs-special-hs-handling; - keep-power-in-suspend; - pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins>; - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - clock-frequency = <50000000>; - max-frequency = <50000000>; -}; - -&uart1 { - status = "okay"; - - bluetooth { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins &bluetooth_pins>; - compatible = "qcom,qca6174-bt"; - enable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; - interrupt-parent = <&gpio0>; - interrupts = <19 IRQ_TYPE_EDGE_RISING>; - }; -}; diff --git a/arch/arm/dts/am335x-sancloud-bbe-lite.dts b/arch/arm/dts/am335x-sancloud-bbe-lite.dts deleted file mode 100644 index daa90f64a8a..00000000000 --- a/arch/arm/dts/am335x-sancloud-bbe-lite.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * Copyright (C) 2021 SanCloud Ltd - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-sancloud-bbe-common.dtsi" - -/ { - model = "SanCloud BeagleBone Enhanced Lite"; - compatible = "sancloud,am335x-boneenhanced", - "ti,am335x-bone-black", - "ti,am335x-bone", - "ti,am33xx"; -}; - -&am33xx_pinmux { - bb_spi0_pins: pinmux_bb_spi0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0) - >; - }; -}; - -&spi0 { - #address-cells = <1>; - #size-cells = <0>; - - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&bb_spi0_pins>; - - channel@0 { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "micron,spi-authenta", "jedec,spi-nor"; - - reg = <0>; - spi-max-frequency = <16000000>; - spi-cpha; - }; -}; diff --git a/arch/arm/dts/am335x-sancloud-bbe.dts b/arch/arm/dts/am335x-sancloud-bbe.dts deleted file mode 100644 index efbe93135db..00000000000 --- a/arch/arm/dts/am335x-sancloud-bbe.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "am33xx.dtsi" -#include "am335x-bone-common.dtsi" -#include "am335x-boneblack-common.dtsi" -#include "am335x-boneblack-hdmi.dtsi" -#include "am335x-sancloud-bbe-common.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "SanCloud BeagleBone Enhanced"; - compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; -}; - -&am33xx_pinmux { - mpu6050_pins: pinmux_mpu6050_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ - >; - }; - - lps3331ap_pins: pinmux_lps3331ap_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ - >; - }; -}; - -&i2c0 { - lps331ap: barometer@5c { - pinctrl-names = "default"; - pinctrl-0 = <&lps3331ap_pins>; - compatible = "st,lps331ap-press"; - st,drdy-int-pin = <1>; - reg = <0x5c>; - interrupt-parent = <&gpio1>; - interrupts = <26 IRQ_TYPE_EDGE_RISING>; - }; - - mpu6050: accelerometer@68 { - pinctrl-names = "default"; - pinctrl-0 = <&mpu6050_pins>; - compatible = "invensense,mpu6050"; - reg = <0x68>; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - orientation = <0xff 0 0 0 1 0 0 0 0xff>; - }; -}; diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 595b4b5abba..1123a81a1a4 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -147,12 +147,12 @@ * for IO and the rest 112 MB (64+32+16) for MEM. Controller supports 32-bit IO mapping. * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): - * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 - * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf - * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 + * https://git.u-boot-project.org/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 + * https://git.u-boot-project.org/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf + * https://git.u-boot-project.org/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 * Bug related to requirement of same child and parent addresses for first range is fixed * in U-Boot version 2022.04 by following commit: - * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 + * https://git.u-boot-project.org/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 */ #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/dts/armada-8040-nbx-u-boot.dtsi b/arch/arm/dts/armada-8040-nbx-u-boot.dtsi new file mode 100644 index 00000000000..dec473b7156 --- /dev/null +++ b/arch/arm/dts/armada-8040-nbx-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Free Mobile, Vincent Jardin + */ + +#ifdef CONFIG_OPTEE +/ { + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; +#endif diff --git a/arch/arm/dts/armada-8040-nbx.dts b/arch/arm/dts/armada-8040-nbx.dts new file mode 100644 index 00000000000..b8b7298b4f5 --- /dev/null +++ b/arch/arm/dts/armada-8040-nbx.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for NBX board (Freebox Nodebox10G) + * Based on Marvell Armada 8040 SoC + * + * Copyright (C) 2024 + */ + +#include "armada-8040.dtsi" + +/ { + model = "NBX Armada 8040"; + compatible = "nbx,armada8040", "marvell,armada8040"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + gpio0 = &ap_gpio0; + gpio1 = &cp0_gpio0; + gpio2 = &cp0_gpio1; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* 2GB */ + }; +}; + +/* AP806 UART - active */ +&uart0 { + status = "okay"; +}; + +/* AP806 pinctrl */ +&ap_pinctl { + /* + * MPP Bus: + * eMMC [0-10] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 1 1 1 1 1 1 1 1 + 1 3 0 0 0 0 0 0 0 3 >; +}; + +/* AP806 on-board eMMC */ +&ap_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&ap_emmc_pins>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* CP0 pinctrl */ +&cp0_pinctl { + /* + * MPP Bus: + * [0-31] = 0xff: Keep default CP0_shared_pins + * [32,34] GE_MDIO/MDC + * [35-36] I2C1 + * [37-38] I2C0 + * [57-58] MSS I2C + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 7 0 7 2 2 2 2 0 + 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 2 2 0 + 0 0 0 >; + + cp0_smi_pins: cp0-smi-pins { + marvell,pins = <32 34>; + marvell,function = <7>; + }; +}; + +/* CP0 I2C0 */ +&cp0_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +/* CP0 I2C1 */ +&cp0_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; + status = "okay"; + clock-frequency = <100000>; +}; + +/* CP0 MSS I2C0 - Management SubSystem I2C (pins 57-58, func 2) */ +&cp0_mss_i2c0 { + status = "okay"; +}; + +/* CP0 MDIO for PHY */ +&cp0_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_smi_pins>; + + nbx_phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +/* CP0 ComPhy - SerDes configuration */ +&cp0_comphy { + /* + * CP0 Serdes Configuration: + * Lane 0-3: Unconnected + * Lane 4: SFI (10G Ethernet) + * Lane 5: SGMII2 (1G Ethernet) + */ + phy0 { + phy-type = <COMPHY_TYPE_UNCONNECTED>; + }; + phy1 { + phy-type = <COMPHY_TYPE_UNCONNECTED>; + }; + phy2 { + phy-type = <COMPHY_TYPE_UNCONNECTED>; + }; + phy3 { + phy-type = <COMPHY_TYPE_UNCONNECTED>; + }; + phy4 { + phy-type = <COMPHY_TYPE_SFI0>; + phy-speed = <COMPHY_SPEED_10_3125G>; + }; + phy5 { + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; +}; + +/* CP0 Ethernet - only eth2 (MAC3) is active via SGMII */ +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth2 { + status = "okay"; + phy = <&nbx_phy0>; + phy-mode = "sgmii"; +}; + +/* CP0 UTMI PHY for USB */ +&cp0_utmi { + status = "okay"; +}; + +&cp0_utmi0 { + status = "okay"; +}; + +&cp0_utmi1 { + status = "okay"; +}; + +/* CP0 USB3 Host controllers */ +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; + +/* CP1 pinctrl */ +&cp1_pinctl { + /* + * MPP Bus: + * [0-26] = Unconfigured + * [27-28] GE_MDIO/MDC + * [29-30] MSS I2C + * [31] = Unconfigured + * [32-62] = 0xff: Keep default CP1_shared_pins + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8 0x8 0x8 + 0x8 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff 0xff>; + + cp1_mss_i2c_pins: cp1-mss-i2c-pins { + marvell,pins = <29 30>; + marvell,function = <8>; + }; +}; + +/* CP1 MSS I2C0 - Management SubSystem I2C (pins 29-30, func 8) */ +&cp1_mss_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp1_mss_i2c_pins>; +}; + +/* CP1 ComPhy - SerDes configuration */ +&cp1_comphy { + /* + * CP1 Serdes Configuration: + * Lane 0: PCIe x1 + * Lane 1: USB3 Host + * Lane 2-3: Unconnected + * Lane 4: SFI (10G Ethernet) + * Lane 5: Unconnected + */ + phy0 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + phy1 { + phy-type = <COMPHY_TYPE_USB3_HOST0>; + }; + phy2 { + phy-type = <COMPHY_TYPE_UNCONNECTED>; + }; + phy3 { + phy-type = <COMPHY_TYPE_UNCONNECTED>; + }; + phy4 { + phy-type = <COMPHY_TYPE_SFI0>; + phy-speed = <COMPHY_SPEED_10_3125G>; + }; + phy5 { + phy-type = <COMPHY_TYPE_UNCONNECTED>; + }; +}; + +/* CP1 PCIe x1 on lane 0 */ +&cp1_pcie0 { + status = "okay"; +}; + +/* CP1 USB3 Host on lane 1 */ +&cp1_usb3_0 { + status = "okay"; +}; + +/* CP1 UTMI PHY for USB */ +&cp1_utmi { + status = "okay"; +}; + +&cp1_utmi0 { + status = "okay"; +}; diff --git a/arch/arm/dts/armada-xp-atl-x220.dts b/arch/arm/dts/armada-xp-atl-x220.dts new file mode 100644 index 00000000000..5b3307ed288 --- /dev/null +++ b/arch/arm/dts/armada-xp-atl-x220.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for x220 board + * + * Copyright (C) 2025 Allied Telesis Labs + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-98dx3236.dtsi" +#include "mvebu-u-boot.dtsi" + +/ { + model = "x220"; + compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200"; + }; + + aliases { + i2c0 = &i2c0; + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1340"; + reg = <0x68>; + }; + + adt7476a@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; + + sfpgpio: gpio@27 { + #address-cells = <2>; + #size-cells = <0>; + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + }; + + systemgpio: gpio@25 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9555"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + + nand-protect { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "nand-protect"; + }; + + usb-enable { + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-enable"; + }; + + phy-reset { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-high; + line-name = "phy-reset"; + }; + + led-enable { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "led-enable"; + }; + }; +}; + +&watchdog { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + }; +}; + +&nand_controller { + compatible = "marvell,armada370-nand-controller"; + label = "pxa3xx_nand-0"; + status = "okay"; + nand-rb = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; +}; + +&{/} { + boot-board { + compatible = "atl,boot-board"; + present-gpio = <&systemgpio 12 GPIO_ACTIVE_HIGH>; + override-gpio = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; +}; + diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi b/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi index dc20643bfa3..ad64813e770 100644 --- a/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi +++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi @@ -5,7 +5,6 @@ status = "okay"; label = "pxa3xx_nand-0"; nand-rb = <0>; - marvell,nand-keep-config; nand-on-flash-bbt; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; diff --git a/arch/arm/dts/ast2700-evb.dts b/arch/arm/dts/ast2700-evb.dts new file mode 100644 index 00000000000..e7222d9691f --- /dev/null +++ b/arch/arm/dts/ast2700-evb.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "ast2700.dtsi" +#include "ast2700-u-boot.dtsi" + +/ { + model = "AST2700 EVB"; + compatible = "aspeed,ast2700-evb", "aspeed,ast2700"; + + memory@400000000 { + device_type = "memory"; + reg = <0x4 0x00000000 0x0 0x20000000>; + }; + + chosen { + stdout-path = &uart12; + }; + +}; + +&uart12 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mdio1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ethphy1: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mac0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; +}; + +&mac1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@1 { + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@2 { + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&wdt0 { + status = "okay"; +}; diff --git a/arch/arm/dts/ast2700-u-boot.dtsi b/arch/arm/dts/ast2700-u-boot.dtsi new file mode 100644 index 00000000000..8830eca3a43 --- /dev/null +++ b/arch/arm/dts/ast2700-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&soc0 { + bootph-all; +}; + +&sdrammc { + bootph-all; +}; + +&syscon0 { + bootph-all; +}; + +&uart12 { + bootph-all; +}; + +&soc1 { + bootph-all; +}; + +&syscon1 { + bootph-all; +}; diff --git a/arch/arm/dts/ast2700.dtsi b/arch/arm/dts/ast2700.dtsi new file mode 100644 index 00000000000..3dd6826fd0c --- /dev/null +++ b/arch/arm/dts/ast2700.dtsi @@ -0,0 +1,693 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <dt-bindings/clock/aspeed,ast2700-scu.h> +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/aspeed,ast2700-scu.h> + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2700"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + serial10 = &uart10; + serial11 = &uart11; + serial12 = &uart12; + mmc0 = &emmc; + mmc1 = &sdhci; + ethernet0 = &mac0; + ethernet1 = &mac1; + ethernet2 = &mac2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + gic: interrupt-controller@12200000 { + compatible = "arm,gic-v3"; + reg = <0 0x12200000 0 0x10000>, /* GICD */ + <0 0x12280000 0 0x80000>, /* GICR */ + <0 0x40440000 0 0x1000>; /* GICC */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf: trusted-firmware-a@430000000 { + reg = <0x4 0x30000000 0x0 0x80000>; + no-map; + }; + + optee_core: optee-core@430080000 { + reg = <0x4 0x30080000 0x0 0x1000000>; + no-map; + }; + }; + + soc0: soc@10000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x4000000>; + + uhci0: usb@12040000 { + compatible = "aspeed,ast2700-uhci", "generic-uhci"; + reg = <0x0 0x12040000 0x0 0x100>; + #ports = <2>; + clocks = <&syscon0 SCU0_CLK_GATE_UHCICLK>; + resets = <&syscon0 SCU0_RESET_UHCI>; + status = "disabled"; + }; + + ehci0: usb@12061000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x12061000 0x0 0x100>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTA_VHUB_EHCI>; + status = "disabled"; + }; + + vhuba0: usb-vhub@12060000 { + compatible = "aspeed,ast2700-usb-vhuba0"; + reg = <0 0x12060000 0 0x350>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTA_VHUB_EHCI>; + status = "disabled"; + }; + + vhubb0: usb-vhub@12062000 { + compatible = "aspeed,ast2700-usb-vhubb0"; + reg = <0x0 0x12062000 0x0 0x350>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTBUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTB_VHUB_EHCI>; + status = "disabled"; + }; + + ehci1: usb@12063000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x12063000 0x0 0x100>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTBUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTB_VHUB_EHCI>; + status = "disabled"; + }; + + emmc_controller: sdc@12090000 { + compatible = "aspeed,ast2700-sd-controller"; + reg = <0 0x12090000 0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x12090000 0x10000>; + clocks = <&syscon0 SCU0_CLK_GATE_EMMCCLK>; + resets = <&syscon0 SCU0_RESET_EMMC>; + status = "disable"; + + emmc: sdhci@100 { + compatible = "aspeed,ast2700-sdhci"; + reg = <0x100 0x100>; + sdhci,auto-cmd12; + clocks = <&syscon0 SCU0_CLK_GATE_EMMCCLK>; + status = "disable"; + }; + }; + + intc0: interrupt-controller@12100000 { + compatible = "aspeed,ast2700-intc0"; + reg = <0x0 0x12100000 0x0 0x3c00>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + }; + + sdrammc: sdrammc@12c00000 { + compatible = "aspeed,ast2700-sdrammc"; + reg = <0 0x12c00000 0 0x3000 0 0x13000000 0 0x300 >; + clocks = <&syscon0 SCU0_CLK_MPLL>; + resets = <&syscon0 SCU0_RESET_SDRAM>; + aspeed,scu0 = <&syscon0>; + aspeed,scu1 = <&syscon1>; + }; + + syscon0: syscon@12c02000 { + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg = <0x0 0x12c02000 0x0 0x1000>; + ranges = <0x0 0x0 0x12c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + pinctrl0: pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + }; + }; + + gpio0: gpio@12c11000 { + compatible = "aspeed,ast2700-gpio"; + reg = <0x0 0x12c11000 0x0 0x1000>; + gpio-ranges = <&pinctrl0 0 0 12>; + ngpios = <12>; + clocks = <&syscon0 SCU0_CLK_APB>; + }; + + uart4: serial@12c1a000 { + compatible = "ns16550a"; + reg = <0x0 0x12c1a000 0x0 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>; + no-loopback-test; + status = "disabled"; + }; + + mbox0: mbox@12c1c200 { + compatible = "aspeed,ast2700-mailbox"; + reg = <0x0 0x12c1c200 0x0 0x100>, <0x0 0x12c1c300 0x0 0x100>; + reg-names = "tx", "rx"; + #mbox-cells = <1>; + }; + + mbox1: mbox@12c1c600 { + compatible = "aspeed,ast2700-mailbox"; + reg = <0x0 0x12c1c600 0x0 0x100>, <0x0 0x12c1c700 0x0 0x100>; + reg-names = "tx", "rx"; + #mbox-cells = <1>; + }; + }; + + soc1: soc@14000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x14000000 0x0 0x14000000 0x2 0xec000000>; + + fmc: spi@14000000 { + reg = <0x0 0x14000000 0x0 0xc4>, <0x1 0x00000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-fmc"; + status = "disabled"; + clocks = <&syscon1 SCU1_CLK_AHB>; + num-cs = <3>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@2 { + reg = <2>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi0: spi@14010000 { + reg = <0x0 0x14010000 0x0 0xc4>, <0x1 0x80000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-spi"; + status = "disabled"; + clocks = <&syscon1 SCU1_CLK_AHB>; + num-cs = <2>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi1: spi@14020000 { + reg = <0x0 0x14020000 0x0 0xc4>, <0x2 0x00000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-spi"; + status = "disabled"; + clocks = <&syscon1 SCU1_CLK_AHB>; + num-cs = <2>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi2: spi@14030000 { + reg = <0x0 0x14030000 0x0 0xc4>, <0x2 0x80000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-spi"; + status = "disabled"; + clocks = <&syscon1 SCU1_CLK_AHB>; + resets = <&syscon1 SCU1_RESET_SPI2>; + num-cs = <2>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + mdio0: mdio@14040000 { + compatible = "aspeed,ast2700-mdio"; + reg = <0 0x14040000 0 0x8>; + resets = <&syscon1 SCU1_RESET_MII>; + status = "disabled"; + }; + + mdio1: mdio@14040008 { + compatible = "aspeed,ast2700-mdio"; + reg = <0 0x14040008 0 0x8>; + resets = <&syscon1 SCU1_RESET_MII>; + status = "disabled"; + }; + + mdio2: mdio@14040010 { + compatible = "aspeed,ast2700-mdio"; + reg = <0 0x14040010 0 0x8>; + resets = <&syscon1 SCU1_RESET_MII>; + status = "disabled"; + }; + + mac0: ftgmac@14050000 { + compatible = "aspeed,ast2700-mac", "faraday,ftgmac100"; + reg = <0x0 0x14050000 0x0 0x200>; + clocks = <&syscon1 SCU1_CLK_GATE_MAC0CLK>; + resets = <&syscon1 SCU1_RESET_MAC0>; + status = "disabled"; + }; + + mac1: ftgmac@14060000 { + compatible = "aspeed,ast2700-mac", "faraday,ftgmac100"; + reg = <0x0 0x14060000 0x0 0x200>; + clocks = <&syscon1 SCU1_CLK_GATE_MAC1CLK>; + resets = <&syscon1 SCU1_RESET_MAC1>; + status = "disabled"; + }; + + mac2: ftgmac@14070000 { + compatible = "aspeed,ast2700-mac", "faraday,ftgmac100"; + reg = <0x0 0x14070000 0x0 0x200>; + clocks = <&syscon1 SCU1_CLK_GATE_MAC2CLK>; + resets = <&syscon1 SCU1_RESET_MAC2>; + status = "disabled"; + }; + + sdio_controller: sdc@14080000 { + compatible = "aspeed,ast2700-sd-controller"; + reg = <0 0x14080000 0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&syscon1 SCU1_CLK_GATE_SDCLK>; + resets = <&syscon1 SCU1_RESET_SD>; + ranges = <0 0 0x14080000 0x10000>; + status = "disable"; + + sdhci: sdhci@100 { + compatible = "aspeed,ast2700-sdhci"; + reg = <0x100 0x100>; + sdhci,auto-cmd12; + clocks = <&syscon1 SCU1_CLK_GATE_SDCLK>; + }; + }; + + uhci1: usb@14110000 { + compatible = "aspeed,ast2700-uhci", "generic-uhci"; + reg = <0x0 0x14110000 0x0 0x100>; + #ports = <2>; + clocks = <&syscon1 SCU1_CLK_GATE_UHCICLK>; + resets = <&syscon1 SCU1_RESET_UHCI>; + status = "disabled"; + }; + + vhubc: usb-vhub@14120000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x14120000 0x0 0x820>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTCUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTC_VHUB_EHCI>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + status = "disabled"; + }; + + ehci2: usb@14121000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x14121000 0x0 0x100>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTCUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTC_VHUB_EHCI>; + status = "disabled"; + }; + + vhubd: usb-vhub@14122000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x14122000 0x0 0x820>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTDUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTD_VHUB_EHCI>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + status = "disabled"; + }; + + ehci3: usb@14123000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x14123000 0x0 0x100>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTDUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTD_VHUB_EHCI>; + status = "disabled"; + }; + + syscon1: syscon@14c02000 { + compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg = <0x0 0x14c02000 0x0 0x1000>; + ranges = <0x0 0x0 0x14c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + pinctrl1: pinctrl@400 { + compatible = "aspeed,ast2700-soc1-pinctrl"; + reg = <0x400 0x2a0>; + }; + }; + + gpio1: gpio@14c0b000 { + compatible = "aspeed,ast2700-gpio"; + reg = <0x0 0x14c0b000 0x0 0x1000>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pinctrl1 0 0 216>; + ngpios = <216>; + clocks = <&syscon1 SCU1_CLK_AHB>; + }; + + intc1: interrupt-controller@14c18000 { + compatible = "aspeed,ast2700-intc1"; + reg = <0 0x14c18000 0 0x400>; + interrupt-controller; + interrupt-parent = <&intc0>; + #interrupt-cells = <1>; + }; + + uart0: serial@14c33000 { + compatible = "ns16550a"; + reg = <0x0 0x14c33000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART0CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart1: serial@14c33100 { + compatible = "ns16550a"; + reg = <0x0 0x14c33100 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART1CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@14c33200 { + compatible = "ns16550a"; + reg = <0x0 0x14c33200 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART2CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@14c33300 { + compatible = "ns16550a"; + reg = <0x0 0x14c33300 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART3CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@14c33400 { + compatible = "ns16550a"; + reg = <0x0 0x14c33400 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART5CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart6: serial@14c33500 { + compatible = "ns16550a"; + reg = <0x0 0x14c33500 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART6CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart7: serial@14c33600 { + compatible = "ns16550a"; + reg = <0x0 0x14c33600 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART7CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart8: serial@14c33700 { + compatible = "ns16550a"; + reg = <0x0 0x14c33700 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART8CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart9: serial@14c33800 { + compatible = "ns16550a"; + reg = <0x0 0x14c33800 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART9CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart10: serial@14c33900 { + compatible = "ns16550a"; + reg = <0x0 0x14c33900 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART10CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart11: serial@14c33a00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33a00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART11CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart12: serial@14c33b00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33b00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>; + clock-frequency = <1846154>; + no-loopback-test; + status = "disabled"; + }; + + uart13: serial@14c33c00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33c00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_UART13>; + no-loopback-test; + status = "disabled"; + }; + + uart14: serial@14c33d00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33d00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_UART14>; + no-loopback-test; + status = "disabled"; + }; + + wdt0: watchdog@14c37000 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37000 0x0 0x80>; + status = "disabled"; + }; + + wdt1: watchdog@14c37080 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37080 0x0 0x80>; + status = "disabled"; + }; + + wdt2: watchdog@14c37100 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37100 0x0 0x80>; + status = "disabled"; + }; + + wdt3: watchdog@14c37180 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37180 0x0 0x80>; + status = "disabled"; + }; + + wdt4: watchdog@14c37200 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37200 0x0 0x80>; + status = "disabled"; + }; + + wdt5: watchdog@14c37280 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37280 0x0 0x80>; + status = "disabled"; + }; + + wdt6: watchdog@14c37300 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37300 0x0 0x80>; + status = "disabled"; + }; + + wdt7: watchdog@14c37380 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37380 0x0 0x80>; + status = "disabled"; + }; + + wdt_abr: watchdog@14c37400 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37400 0x0 0x80>; + status = "disabled"; + }; + + mbox2: mbox@14c39200 { + compatible = "aspeed,ast2700-mailbox"; + reg = <0x0 0x14c39200 0x0 0x100>, <0x0 0x14c39300 0x0 0x100>; + reg-names = "tx", "rx"; + #mbox-cells = <1>; + }; + + }; +}; diff --git a/arch/arm/dts/ax3005-scm3005.dts b/arch/arm/dts/ax3005-scm3005.dts new file mode 100644 index 00000000000..b684602176c --- /dev/null +++ b/arch/arm/dts/ax3005-scm3005.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + */ + +/dts-v1/; + +#include "ax3005.dtsi" + +/ { + model = "Axiado AX3005 SCM3005"; + compatible = "axiado,ax3005-scm3005", "axiado,ax3005"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "serial3:115200"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0x80000000>; + }; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/dts/ax3005.dtsi b/arch/arm/dts/ax3005.dtsi new file mode 100644 index 00000000000..6df2e4a821c --- /dev/null +++ b/arch/arm/dts/ax3005.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/memreserve/ 0x80002fa0 0x00000008; + +/ { + aliases { + serial3 = &uart3; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80002fa0>; + }; + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80002fa0>; + }; + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80002fa0>; + }; + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x80002fa0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic500>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <1000000000>; + }; + + clocks { + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + bootph-pre-reloc; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic500>; + ranges; + + gic500: interrupt-controller@40400000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + reg = <0x00 0x40400000 0x00 0x10000>, + <0x00 0x40500000 0x00 0xc0000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart3: serial@33020800 { + compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x00 0x33020800 0x00 0x100>; + clock-names = "uart_clk", "pclk"; + clocks = <&refclk &refclk>; + bootph-pre-reloc; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/en7523-u-boot.dtsi b/arch/arm/dts/en7523-u-boot.dtsi index 62d1a724678..7866a3552e6 100644 --- a/arch/arm/dts/en7523-u-boot.dtsi +++ b/arch/arm/dts/en7523-u-boot.dtsi @@ -2,6 +2,9 @@ #include <dt-bindings/reset/airoha,en7523-reset.h> +/delete-node/ &gpio0; +/delete-node/ &gpio1; + / { reserved-memory { #address-cells = <1>; @@ -22,6 +25,26 @@ #reset-cells = <1>; }; + system-controller@1fbf0200 { + compatible = "syscon", "simple-mfd"; + reg = <0x1fbf0200 0xc0>; + + en7523_pinctrl: pinctrl { + compatible = "airoha,en7523-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&en7523_pinctrl 0 12 30>; + }; + }; + eth: ethernet@1fb50000 { compatible = "airoha,en7523-eth"; reg = <0x1fb50000 0x2600>, diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi index 910d2a5c778..194ab344350 100644 --- a/arch/arm/dts/fsl-ls1012a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi @@ -17,7 +17,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -25,7 +25,7 @@ spi-max-frequency = <1000000>; /* input clock */ }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -33,7 +33,7 @@ reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 796d72fc9ed..b0f3fd79094 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -48,7 +48,7 @@ clocks = <&sysclk>; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -178,7 +178,7 @@ clocks = <&clockgen 4 0>; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 3b063d0257d..ac5b2d9dde9 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -26,29 +26,29 @@ bus-num = <0>; status = "okay"; - dflash0: sst25wf040b { + dflash0: sst25wf040b@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash1: en25s64 { + dflash1: en25s64@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash2: n25q128a { + dflash2: n25q128a@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -60,29 +60,29 @@ bus-num = <0>; status = "okay"; - dflash3: sst25wf040b { + dflash3: sst25wf040b@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash4: en25s64 { + dflash4: en25s64@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash5: n25q128a { + dflash5: n25q128a@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -94,10 +94,10 @@ bus-num = <0>; status = "okay"; - dflash8: en25s64 { + dflash8: en25s64@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 5e02cd91d75..fa1bda51108 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -21,7 +21,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -31,7 +31,7 @@ reg = <0>; }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -41,7 +41,7 @@ reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts index f5b3bb68b3d..80787907df6 100644 --- a/arch/arm/dts/fsl-ls1043a-rdb.dts +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -28,7 +28,7 @@ bus-num = <0>; status = "okay"; - dspiflash: n25q12a { + dspiflash: n25q12a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 21643a1d951..7337d3cecb6 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -54,7 +54,7 @@ clocks = <&sysclk>; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -67,7 +67,7 @@ status = "disabled"; }; - dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -306,7 +306,7 @@ clock-names = "ipg"; status = "disabled"; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index d66824975c5..706405ba805 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -21,7 +21,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -31,7 +31,7 @@ reg = <0>; }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -41,7 +41,7 @@ reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 44ee4c5808d..ceb5d6b3356 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -54,7 +54,7 @@ clocks = <&sysclk>; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -67,7 +67,7 @@ status = "disabled"; }; - dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -311,7 +311,7 @@ status = "disabled"; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/fsl-ls1088a-qds-21-x-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-qds-21-x-u-boot.dtsi new file mode 100644 index 00000000000..1d58f1c593b --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-21-x-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * + */ + +#include <config.h> + +#include "fsl-ls1088a-qds-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1088a-qds-29-x-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-qds-29-x-u-boot.dtsi new file mode 100644 index 00000000000..1d58f1c593b --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-29-x-u-boot.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * + */ + +#include <config.h> + +#include "fsl-ls1088a-qds-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi index 4d21d4fbd5e..83635a2e40d 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi @@ -144,7 +144,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -152,7 +152,7 @@ spi-max-frequency = <1000000>; /* input clock */ }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -160,7 +160,7 @@ reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi index 4e6700d586e..0d64795bf44 100644 --- a/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi @@ -18,11 +18,3 @@ ethernet9 = &dpmac1; }; }; - -&i2c0 { - uc: board-controller@7e { - compatible = "traverse,ten64-controller"; - reg = <0x7e>; - }; -}; - diff --git a/arch/arm/dts/fsl-ls1088a-ten64.dts b/arch/arm/dts/fsl-ls1088a-ten64.dts deleted file mode 100644 index 0d11440d88d..00000000000 --- a/arch/arm/dts/fsl-ls1088a-ten64.dts +++ /dev/null @@ -1,388 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree file for Traverse Technologies Ten64 - * (LS1088A) board - * Based on fsl-ls1088a-rdb.dts - * Copyright 2017-2020 NXP - * Copyright 2019-2023 Traverse Technologies - * - * Author: Mathew McBride <[email protected]> - */ - -/dts-v1/; - -#include "fsl-ls1088a.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Traverse Ten64"; - compatible = "traverse,ten64", "fsl,ls1088a"; - - aliases { - serial0 = &duart0; - serial1 = &duart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - buttons { - compatible = "gpio-keys"; - - /* Fired by system controller when - * external power off (e.g ATX Power Button) - * asserted - */ - button-powerdn { - label = "External Power Down"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - }; - - /* Rear Panel 'ADMIN' button (GPIO_H) */ - button-admin { - label = "ADMIN button"; - gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; - linux,code = <KEY_WPS_BUTTON>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "ten64:green:sfp1:down"; - gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "ten64:green:sfp2:up"; - gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - label = "ten64:admin"; - gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>; - }; - }; - - sfp_xg0: dpmac2-sfp { - compatible = "sff,sfp"; - i2c-bus = <&sfplower_i2c>; - tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>; - los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <2000>; - }; - - sfp_xg1: dpmac1-sfp { - compatible = "sff,sfp"; - i2c-bus = <&sfpupper_i2c>; - tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>; - tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>; - mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>; - los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>; - maximum-power-milliwatt = <2000>; - }; -}; - -/* XG1 - Upper SFP */ -&dpmac1 { - sfp = <&sfp_xg1>; - pcs-handle = <&pcs1>; - phy-connection-type = "10gbase-r"; - managed = "in-band-status"; -}; - -/* XG0 - Lower SFP */ -&dpmac2 { - sfp = <&sfp_xg0>; - pcs-handle = <&pcs2>; - phy-connection-type = "10gbase-r"; - managed = "in-band-status"; -}; - -/* DPMAC3..6 is GE4 to GE8 */ -&dpmac3 { - phy-handle = <&mdio1_phy5>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs3_0>; -}; - -&dpmac4 { - phy-handle = <&mdio1_phy6>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs3_1>; -}; - -&dpmac5 { - phy-handle = <&mdio1_phy7>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs3_2>; -}; - -&dpmac6 { - phy-handle = <&mdio1_phy8>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs3_3>; -}; - -/* DPMAC7..10 is GE0 to GE3 */ -&dpmac7 { - phy-handle = <&mdio1_phy1>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs7_0>; -}; - -&dpmac8 { - phy-handle = <&mdio1_phy2>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs7_1>; -}; - -&dpmac9 { - phy-handle = <&mdio1_phy3>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs7_2>; -}; - -&dpmac10 { - phy-handle = <&mdio1_phy4>; - phy-connection-type = "qsgmii"; - managed = "in-band-status"; - pcs-handle = <&pcs7_3>; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&emdio1 { - status = "okay"; - - mdio1_phy5: ethernet-phy@c { - reg = <0xc>; - }; - - mdio1_phy6: ethernet-phy@d { - reg = <0xd>; - }; - - mdio1_phy7: ethernet-phy@e { - reg = <0xe>; - }; - - mdio1_phy8: ethernet-phy@f { - reg = <0xf>; - }; - - mdio1_phy1: ethernet-phy@1c { - reg = <0x1c>; - }; - - mdio1_phy2: ethernet-phy@1d { - reg = <0x1d>; - }; - - mdio1_phy3: ethernet-phy@1e { - reg = <0x1e>; - }; - - mdio1_phy4: ethernet-phy@1f { - reg = <0x1f>; - }; -}; - -&esdhc { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - sfpgpio: gpio@76 { - compatible = "ti,tca9539"; - reg = <0x76>; - #gpio-cells = <2>; - gpio-controller; - - admin_led_lower { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-low; - }; - }; - - at97sc: tpm@29 { - compatible = "atmel,at97sc3204t"; - reg = <0x29>; - }; -}; - -&i2c2 { - status = "okay"; - - rx8035: rtc@32 { - compatible = "epson,rx8035"; - reg = <0x32>; - }; -}; - -&i2c3 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9540"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - sfpupper_i2c: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - sfplower_i2c: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; -}; - -&pcs_mdio1 { - status = "okay"; -}; - -&pcs_mdio2 { - status = "okay"; -}; - -&pcs_mdio3 { - status = "okay"; -}; - -&pcs_mdio7 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - en25s64: flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0 0x100000>; - }; - - partition@100000 { - label = "bl3"; - reg = <0x100000 0x200000>; - }; - - partition@300000 { - label = "mcfirmware"; - reg = <0x300000 0x200000>; - }; - - partition@500000 { - label = "ubootenv"; - reg = <0x500000 0x80000>; - }; - - partition@580000 { - label = "dpl"; - reg = <0x580000 0x40000>; - }; - - partition@5C0000 { - label = "dpc"; - reg = <0x5C0000 0x40000>; - }; - - partition@600000 { - label = "devicetree"; - reg = <0x600000 0x40000>; - }; - }; - }; - - nand: flash@1 { - compatible = "spi-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* reserved for future boot direct from NAND flash - * (this would use the same layout as the 8MiB NOR flash) - */ - partition@0 { - label = "nand-boot-reserved"; - reg = <0 0x800000>; - }; - - /* recovery / install environment */ - partition@800000 { - label = "recovery"; - reg = <0x800000 0x2000000>; - }; - - /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */ - partition@2800000 { - label = "ubia"; - reg = <0x2800000 0x6C00000>; - }; - - /* ubib (second OpenWrt) */ - partition@9400000 { - label = "ubib"; - reg = <0x9400000 0x6C00000>; - }; - }; - }; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi index efcfdd96aef..8ae45f6a638 100644 --- a/arch/arm/dts/fsl-ls1088a-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1088a-u-boot.dtsi @@ -55,9 +55,14 @@ &usb0 { compatible = "fsl,layerscape-dwc3", "snps,dwc3"; + status = "okay"; }; &usb1 { compatible = "fsl,layerscape-dwc3", "snps,dwc3"; + status = "okay"; }; +&esdhc { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index e5fb137ac02..9a62f148d8e 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -978,51 +978,61 @@ dpmac1: ethernet@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <1>; + status = "disabled"; }; dpmac2: ethernet@2 { compatible = "fsl,qoriq-mc-dpmac"; reg = <2>; + status = "disabled"; }; dpmac3: ethernet@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <3>; + status = "disabled"; }; dpmac4: ethernet@4 { compatible = "fsl,qoriq-mc-dpmac"; reg = <4>; + status = "disabled"; }; dpmac5: ethernet@5 { compatible = "fsl,qoriq-mc-dpmac"; reg = <5>; + status = "disabled"; }; dpmac6: ethernet@6 { compatible = "fsl,qoriq-mc-dpmac"; reg = <6>; + status = "disabled"; }; dpmac7: ethernet@7 { compatible = "fsl,qoriq-mc-dpmac"; reg = <7>; + status = "disabled"; }; dpmac8: ethernet@8 { compatible = "fsl,qoriq-mc-dpmac"; reg = <8>; + status = "disabled"; }; dpmac9: ethernet@9 { compatible = "fsl,qoriq-mc-dpmac"; reg = <9>; + status = "disabled"; }; dpmac10: ethernet@a { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xa>; + status = "disabled"; }; }; }; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dtsi b/arch/arm/dts/fsl-ls2080a-qds.dtsi index cb7851f2cc0..f442baa8bfe 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dtsi +++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi @@ -31,7 +31,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -40,7 +40,7 @@ spi-cpha; reg = <0>; }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -49,7 +49,7 @@ spi-cpha; reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts b/arch/arm/dts/fsl-ls2080a-rdb.dts index 0a87caeba96..5a9b5c06e23 100644 --- a/arch/arm/dts/fsl-ls2080a-rdb.dts +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts @@ -22,7 +22,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q512a { + dflash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index d754eb4d5cc..c1173a95f24 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -118,7 +118,7 @@ interrupts = <0 35 0x4>; /* Level high type */ }; - dspi: dspi@2100000 { + dspi: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -127,7 +127,7 @@ spi-num-chipselects = <6>; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls2080a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/fsl-ls2081a-rdb.dts b/arch/arm/dts/fsl-ls2081a-rdb.dts index b0b7ef08a02..61f0ed9b821 100644 --- a/arch/arm/dts/fsl-ls2081a-rdb.dts +++ b/arch/arm/dts/fsl-ls2081a-rdb.dts @@ -25,7 +25,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q512a { + dflash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index a609290000f..1884946cc7a 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -113,7 +113,7 @@ bus-num = <0>; status = "okay"; - dflash0: n25q512a { + dflash0: n25q512a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index e96605b1b4f..6fa36de0622 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -31,28 +31,28 @@ bus-num = <0>; status = "okay"; - dflash0: n25q128a { + dflash0: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash1: sst25wf040b { + dflash1: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash2: en25s64 { + dflash2: en25s64@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -64,28 +64,28 @@ bus-num = <0>; status = "okay"; - dflash3: n25q128a { + dflash3: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash4: sst25wf040b { + dflash4: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash5: en25s64 { + dflash5: en25s64@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; @@ -97,28 +97,28 @@ bus-num = <0>; status = "okay"; - dflash6: n25q128a { + dflash6: n25q128a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <0>; }; - dflash7: sst25wf040b { + dflash7: sst25wf040b@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; reg = <1>; }; - dflash8: en25s64 { + dflash8: en25s64@2 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <3000000>; spi-cpol; spi-cpha; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 680c69c7b73..61d78b74f19 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -134,7 +134,7 @@ <1 10 0x8>; /* Hypervisor PPI, active-low */ }; - fspi: flexspi@20c0000 { + fspi: spi@20c0000 { compatible = "nxp,lx2160a-fspi"; #address-cells = <1>; #size-cells = <0>; @@ -221,7 +221,7 @@ status = "disabled"; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -230,7 +230,7 @@ spi-num-chipselects = <6>; }; - dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -239,7 +239,7 @@ spi-num-chipselects = <6>; }; - dspi2: dspi@2120000 { + dspi2: spi@2120000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -292,7 +292,7 @@ #interrupt-cells = <2>; }; - watchdog@23a0000 { + wdt0: watchdog@23a0000 { compatible = "arm,sbsa-gwdt"; reg = <0x0 0x23a0000 0 0x1000>, <0x0 0x2390000 0 0x1000>; @@ -594,6 +594,64 @@ }; }; + /* LX2160ARM Chapter 28 ("Thermal Monitoring Unit") */ + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + fsl,tmu-range = <0x800000e6 0x8001017d>; + fsl,tmu-calibration = <0x00000000 0x00000035 + 0x00000001 0x00000154>; + little-endian; + #thermal-sensor-cells = <1>; + label = "lx2160a-tmu"; /* explicit naming */ + }; + + /* explicit thermal-zones names per LX2160ARM Table 323 */ + thermal-zones { + cluster67-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>; + }; + + ddr1-cluster5-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + }; + + wriop-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 2>; + }; + + dce-qbman-hsio2-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 3>; + }; + + ccn-dpaa-tbu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 4>; + }; + + cluster4-hsio3-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 5>; + }; + + cluster23-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 6>; + }; + }; + /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ emdio1: mdio@8b96000 { compatible = "fsl,ls-mdio"; diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts index 0ca30df8620..35d80639958 100644 --- a/arch/arm/dts/fsl-lx2162a-qds.dts +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -37,105 +37,6 @@ status = "disabled"; }; -&dspi0 { - bus-num = <0>; - status = "okay"; - - dflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; - dflash1: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <1>; - }; - dflash2: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <2>; - }; -}; - -&dspi1 { - bus-num = <0>; - status = "okay"; - - dflash3: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; - dflash4: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <1>; - }; - dflash5: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <2>; - }; -}; - -&dspi2 { - bus-num = <0>; - status = "okay"; - - dflash6: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; - dflash7: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <1>; - }; - dflash8: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <2>; - }; -}; - &esdhc1 { mmc-hs200-1_8v; mmc-hs400-1_8v; diff --git a/arch/arm/dts/imx6ul-tqma6ul-common-u-boot.dtsi b/arch/arm/dts/imx6ul-tqma6ul-common-u-boot.dtsi new file mode 100644 index 00000000000..09f94f23074 --- /dev/null +++ b/arch/arm/dts/imx6ul-tqma6ul-common-u-boot.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +/ { + aliases { + spi0 = &qspi; + }; + + config { + u-boot,mmc-env-offset = <0x100000>; + u-boot,mmc-env-offset-redundant = <0x110000>; + }; +}; + +&clks { + bootph-pre-ram; +}; + +&flash0 { + bootph-pre-ram; +}; + +&osc { + bootph-pre-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; +}; + +&pinctrl_qspi { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&qspi { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx6ul-tqma6ul1-mba6ulx-u-boot.dtsi b/arch/arm/dts/imx6ul-tqma6ul1-mba6ulx-u-boot.dtsi new file mode 100644 index 00000000000..0917ecfd82a --- /dev/null +++ b/arch/arm/dts/imx6ul-tqma6ul1-mba6ulx-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include "imx6ul-u-boot.dtsi" +#include "imx6ul-tqma6ul-common-u-boot.dtsi" +#include "mba6ulx-u-boot.dtsi" diff --git a/arch/arm/dts/imx6ul-tqma6ul2-mba6ulx-u-boot.dtsi b/arch/arm/dts/imx6ul-tqma6ul2-mba6ulx-u-boot.dtsi new file mode 100644 index 00000000000..0917ecfd82a --- /dev/null +++ b/arch/arm/dts/imx6ul-tqma6ul2-mba6ulx-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include "imx6ul-u-boot.dtsi" +#include "imx6ul-tqma6ul-common-u-boot.dtsi" +#include "mba6ulx-u-boot.dtsi" diff --git a/arch/arm/dts/imx6ul-tqma6ul2l-mba6ulx-u-boot.dtsi b/arch/arm/dts/imx6ul-tqma6ul2l-mba6ulx-u-boot.dtsi new file mode 100644 index 00000000000..0917ecfd82a --- /dev/null +++ b/arch/arm/dts/imx6ul-tqma6ul2l-mba6ulx-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include "imx6ul-u-boot.dtsi" +#include "imx6ul-tqma6ul-common-u-boot.dtsi" +#include "mba6ulx-u-boot.dtsi" diff --git a/arch/arm/dts/imx6ull-tqma6ull2-mba6ulx-u-boot.dtsi b/arch/arm/dts/imx6ull-tqma6ull2-mba6ulx-u-boot.dtsi new file mode 100644 index 00000000000..21fb2ab4ae9 --- /dev/null +++ b/arch/arm/dts/imx6ull-tqma6ull2-mba6ulx-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include "imx6ull-u-boot.dtsi" +#include "imx6ul-tqma6ul-common-u-boot.dtsi" +#include "mba6ulx-u-boot.dtsi" diff --git a/arch/arm/dts/imx6ull-tqma6ull2l-mba6ulx-u-boot.dtsi b/arch/arm/dts/imx6ull-tqma6ull2l-mba6ulx-u-boot.dtsi new file mode 100644 index 00000000000..21fb2ab4ae9 --- /dev/null +++ b/arch/arm/dts/imx6ull-tqma6ull2l-mba6ulx-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include "imx6ull-u-boot.dtsi" +#include "imx6ul-tqma6ul-common-u-boot.dtsi" +#include "mba6ulx-u-boot.dtsi" diff --git a/arch/arm/dts/imx7d-mba7-u-boot.dtsi b/arch/arm/dts/imx7d-mba7-u-boot.dtsi new file mode 100644 index 00000000000..3ccc95a7ac6 --- /dev/null +++ b/arch/arm/dts/imx7d-mba7-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for TQ-Systems TQMa7D board on MBa7x carrier board. + * + * Copyright (C) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany + * Author: Steffen Doster + */ + +#include "imx7s-mba7-u-boot.dtsi" diff --git a/arch/arm/dts/imx7s-mba7-u-boot.dtsi b/arch/arm/dts/imx7s-mba7-u-boot.dtsi new file mode 100644 index 00000000000..bb560f4d85b --- /dev/null +++ b/arch/arm/dts/imx7s-mba7-u-boot.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for TQ-Systems TQMa7S board on MBa7x carrier board. + * + * Copyright (C) 2025-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany + * Author: Steffen Doster + */ + +#include "imx7s-tqma7-u-boot.dtsi" + +/ { + config { + u-boot,mmc-env-offset = <0x100000>; + u-boot,mmc-env-offset-redundant = <0x110000>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&gpio4 { + /* Deassert BOOT_EN after boot to separate BOOT_CFG circuits from LCD signals */ + boot-en-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + }; +}; + +&wdog1 { + u-boot,noautostart; + timeout-sec = <60>; +}; + +&iomuxc { + bootph-pre-ram; +}; + +&pinctrl_uart6 { + bootph-pre-ram; +}; + +&uart6 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx7s-tqma7-u-boot.dtsi b/arch/arm/dts/imx7s-tqma7-u-boot.dtsi new file mode 100644 index 00000000000..2b6bbcc0276 --- /dev/null +++ b/arch/arm/dts/imx7s-tqma7-u-boot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for TQ-Systems TQMa7S module. + * + * Copyright (C) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany + * Author: Steffen Doster + */ + +#include "imx7s-u-boot.dtsi" + +/ { + sysinfo: sysinfo { + compatible = "tq,eeprom-sysinfo"; + nvmem-cells = <&module_info>; + nvmem-cell-names = "device_info"; + }; +}; + +&m24c64 { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + module_info: module-info@20 { + reg = <0x20 0x60>; + }; + }; +}; + +&soc { + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; +}; + +&aips3 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx7ulp-com-u-boot.dtsi b/arch/arm/dts/imx7ulp-com-u-boot.dtsi index f6d34e1b635..e13bcfe45f4 100644 --- a/arch/arm/dts/imx7ulp-com-u-boot.dtsi +++ b/arch/arm/dts/imx7ulp-com-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2019 Foundries.io */ +#include "imx7ulp-u-boot.dtsi" + &iomuxc1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx7ulp-com.dts b/arch/arm/dts/imx7ulp-com.dts deleted file mode 100644 index d76fea3b35c..00000000000 --- a/arch/arm/dts/imx7ulp-com.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2019 NXP - -/dts-v1/; - -#include "imx7ulp.dtsi" -#include <dt-bindings/input/input.h> - -/ { - model = "Embedded Artists i.MX7ULP COM"; - compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; - - chosen { - stdout-path = &lpuart4; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x4000000>; - }; -}; - -&lpuart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart4>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usdhc0 { - assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0>; - non-removable; - bus-width = <8>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc1 { - pinctrl_lpuart4: lpuart4grp { - fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 - >; - }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 - IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 - IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 - IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 - IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 - IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 - >; - }; -}; diff --git a/arch/arm/dts/imx7ulp-evk-u-boot.dtsi b/arch/arm/dts/imx7ulp-evk-u-boot.dtsi new file mode 100644 index 00000000000..1944a024ecc --- /dev/null +++ b/arch/arm/dts/imx7ulp-evk-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "imx7ulp-u-boot.dtsi" diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts deleted file mode 100644 index eff51e113db..00000000000 --- a/arch/arm/dts/imx7ulp-evk.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - * Dong Aisheng <[email protected]> - */ - -/dts-v1/; - -#include "imx7ulp.dtsi" - -/ { - model = "NXP i.MX7ULP EVK"; - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp"; - - chosen { - stdout-path = &lpuart4; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&tpm4 1 50000 0>; - brightness-levels = <0 20 25 30 35 40 100>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vsd_3v3: regulator-vsd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0_rst>; - gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&lpuart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart4>; - status = "okay"; -}; - -&tpm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0>; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_id>; - srp-disable; - hnp-disable; - adp-disable; - disable-over-current; - status = "okay"; -}; - -&usdhc0 { - assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc0>; - cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_vsd_3v3>; - status = "okay"; -}; - -&iomuxc1 { - pinctrl_lpuart4: lpuart4grp { - fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 - >; - bias-pull-up; - }; - - pinctrl_pwm0: pwm0grp { - fsl,pins = < - IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 - >; - }; - - pinctrl_usbotg1_vbus: otg1vbusgrp { - fsl,pins = < - IMX7ULP_PAD_PTC0__PTC0 0x20000 - >; - }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 - IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */ - >; - }; - - pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { - fsl,pins = < - IMX7ULP_PAD_PTD0__PTD0 0x3 - >; - }; -}; diff --git a/arch/arm/dts/imx7ulp-u-boot.dtsi b/arch/arm/dts/imx7ulp-u-boot.dtsi new file mode 100644 index 00000000000..88cb5716a29 --- /dev/null +++ b/arch/arm/dts/imx7ulp-u-boot.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +&ahbbridge0 { + wdog2: watchdog@40430000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x40430000 0x10000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + timeout-sec = <40>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi deleted file mode 100644 index bcec98b9641..00000000000 --- a/arch/arm/dts/imx7ulp.dtsi +++ /dev/null @@ -1,461 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP - * Dong Aisheng <[email protected]> - */ - -#include <dt-bindings/clock/imx7ulp-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> - -#include "imx7ulp-pinfunc.h" - -/ { - interrupt-parent = <&intc>; - - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio_ptc; - gpio1 = &gpio_ptd; - gpio2 = &gpio_pte; - gpio3 = &gpio_ptf; - i2c0 = &lpi2c6; - i2c1 = &lpi2c7; - mmc0 = &usdhc0; - mmc1 = &usdhc1; - serial0 = &lpuart4; - serial1 = &lpuart5; - serial2 = &lpuart6; - serial3 = &lpuart7; - usbphy0 = &usbphy1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; - }; - }; - - intc: interrupt-controller@40021000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x40021000 0x1000>, - <0x40022000 0x1000>; - }; - - rosc: clock-rosc { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "rosc"; - #clock-cells = <0>; - }; - - sosc: clock-sosc { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "sosc"; - #clock-cells = <0>; - }; - - sirc: clock-sirc { - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-output-names = "sirc"; - #clock-cells = <0>; - }; - - firc: clock-firc { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - clock-output-names = "firc"; - #clock-cells = <0>; - }; - - upll: clock-upll { - compatible = "fixed-clock"; - clock-frequency = <480000000>; - clock-output-names = "upll"; - #clock-cells = <0>; - }; - - ahbbridge0: bus@40000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40000000 0x800000>; - ranges; - - edma1: dma-controller@40080000 { - #dma-cells = <2>; - compatible = "fsl,imx7ulp-edma"; - reg = <0x40080000 0x2000>, - <0x40210000 0x1000>; - dma-channels = <32>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dma", "dmamux0"; - clocks = <&pcc2 IMX7ULP_CLK_DMA1>, - <&pcc2 IMX7ULP_CLK_DMA_MUX1>; - }; - - crypto: crypto@40240000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40240000 0x10000>; - ranges = <0 0x40240000 0x10000>; - clocks = <&pcc2 IMX7ULP_CLK_CAAM>, - <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - lpuart4: serial@402d0000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x402d0000 0x1000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; - clock-names = "ipg"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - assigned-clock-rates = <24000000>; - status = "disabled"; - }; - - lpuart5: serial@402e0000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x402e0000 0x1000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; - clock-names = "ipg"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - tpm4: pwm@40250000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x40250000 0x1000>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm5: tpm@40260000 { - compatible = "fsl,imx7ulp-tpm"; - reg = <0x40260000 0x1000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&pcc2 IMX7ULP_CLK_LPTPM5>; - clock-names = "ipg", "per"; - }; - - usbotg1: usb@40330000 { - compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; - reg = <0x40330000 0x200>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc2 IMX7ULP_CLK_USB0>; - phys = <&usbphy1>; - fsl,usbmisc = <&usbmisc1 0>; - ahb-burst-config = <0x0>; - tx-burst-size-dword = <0x8>; - rx-burst-size-dword = <0x8>; - status = "disabled"; - }; - - usbmisc1: usbmisc@40330200 { - compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x40330200 0x200>; - }; - - usbphy1: usb-phy@40350000 { - compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; - reg = <0x40350000 0x1000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; - #phy-cells = <0>; - }; - - usdhc0: mmc@40370000 { - compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x40370000 0x10000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&pcc2 IMX7ULP_CLK_USDHC0>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - usdhc1: mmc@40380000 { - compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; - reg = <0x40380000 0x10000>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&pcc2 IMX7ULP_CLK_USDHC1>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - scg1: clock-controller@403e0000 { - compatible = "fsl,imx7ulp-scg1"; - reg = <0x403e0000 0x10000>; - clocks = <&rosc>, <&sosc>, <&sirc>, - <&firc>, <&upll>; - clock-names = "rosc", "sosc", "sirc", - "firc", "upll"; - #clock-cells = <1>; - }; - - wdog1: watchdog@403d0000 { - compatible = "fsl,imx7ulp-wdt"; - reg = <0x403d0000 0x10000>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; - timeout-sec = <40>; - }; - - pcc2: clock-controller@403f0000 { - compatible = "fsl,imx7ulp-pcc2"; - reg = <0x403f0000 0x10000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&scg1 IMX7ULP_CLK_DDR_DIV>, - <&scg1 IMX7ULP_CLK_APLL_PFD2>, - <&scg1 IMX7ULP_CLK_APLL_PFD1>, - <&scg1 IMX7ULP_CLK_APLL_PFD0>, - <&scg1 IMX7ULP_CLK_UPLL>, - <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_ROSC>, - <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; - clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", - "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", - "firc_bus_clk", "rosc", "spll_bus_clk"; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - }; - - smc1: clock-controller@40410000 { - compatible = "fsl,imx7ulp-smc1"; - reg = <0x40410000 0x1000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, - <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; - clock-names = "divcore", "hsrun_divcore"; - }; - - pcc3: clock-controller@40b30000 { - compatible = "fsl,imx7ulp-pcc3"; - reg = <0x40b30000 0x10000>; - #clock-cells = <1>; - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, - <&scg1 IMX7ULP_CLK_NIC1_DIV>, - <&scg1 IMX7ULP_CLK_DDR_DIV>, - <&scg1 IMX7ULP_CLK_APLL_PFD2>, - <&scg1 IMX7ULP_CLK_APLL_PFD1>, - <&scg1 IMX7ULP_CLK_APLL_PFD0>, - <&scg1 IMX7ULP_CLK_UPLL>, - <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_ROSC>, - <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; - clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", - "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", - "firc_bus_clk", "rosc", "spll_bus_clk"; - }; - }; - - ahbbridge1: bus@40800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40800000 0x800000>; - ranges; - - lpi2c6: i2c@40a40000 { - compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x40a40000 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpi2c7: i2c@40a50000 { - compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x40a50000 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpuart6: serial@40a60000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x40a60000 0x1000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpuart7: serial@40a70000 { - compatible = "fsl,imx7ulp-lpuart"; - reg = <0x40a70000 0x1000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; - clock-names = "ipg"; - assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - memory-controller@40ab0000 { - compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; - reg = <0x40ab0000 0x1000>; - clocks = <&pcc3 IMX7ULP_CLK_MMDC>; - }; - - iomuxc1: pinctrl@40ac0000 { - compatible = "fsl,imx7ulp-iomuxc1"; - reg = <0x40ac0000 0x1000>; - }; - - gpio_ptc: gpio@40ae0000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40ae0000 0x1000 0x400f0000 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLC>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 0 20>; - }; - - gpio_ptd: gpio@40af0000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40af0000 0x1000 0x400f0040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLD>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 32 12>; - }; - - gpio_pte: gpio@40b00000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40b00000 0x1000 0x400f0080 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 64 16>; - }; - - gpio_ptf: gpio@40b10000 { - compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; - reg = <0x40b10000 0x1000 0x400f00c0 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, - <&pcc3 IMX7ULP_CLK_PCTLF>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc1 0 96 20>; - }; - }; - - m4aips1: bus@41080000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x41080000 0x80000>; - ranges; - - sim: sim@410a3000 { - compatible = "fsl,imx7ulp-sim", "syscon"; - reg = <0x410a3000 0x1000>; - }; - - ocotp: efuse@410a6000 { - compatible = "fsl,imx7ulp-ocotp", "syscon"; - reg = <0x410a6000 0x4000>; - clocks = <&scg1 IMX7ULP_CLK_DUMMY>; - }; - }; -}; diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi deleted file mode 100644 index 03266bd90a0..00000000000 --- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi +++ /dev/null @@ -1,437 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -#include <dt-bindings/phy/phy-imx8-pcie.h> - -/ { - leds { - compatible = "gpio-leds"; - - led0 { - label = "gen_led0"; - gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led1 { - label = "gen_led1"; - gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led2 { - label = "gen_led2"; - gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led3>; - label = "heartbeat"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - pcie0_refclk: pcie0-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie0_refclk_gated: pcie0-refclk-gated { - compatible = "gpio-gate-clock"; - clocks = <&pcie0_refclk>; - #clock-cells = <0>; - enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "3v3_aud"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usbotg1: regulator-usbotg1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_otg1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_camera: regulator-camera { - compatible = "regulator-fixed"; - regulator-name = "mipi_pwr"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100000>; - }; - - reg_pcie0: regulator-pcie { - compatible = "regulator-fixed"; - regulator-name = "pci_pwr_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - }; -}; - -&csi { - status = "okay"; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - eeprom@0 { - compatible = "microchip,at25160bn", "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - pagesize = <32>; - size = <2048>; - address-width = <16>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clk IMX8MM_CLK_CLKO1>; - clock-names = "xclk"; - assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; - assigned-clock-parents = <&clk IMX8MM_CLK_24M>; - assigned-clock-rates = <24000000>; - AVDD-supply = <®_camera>; /* 2.8v */ - powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&imx8mm_mipi_csi_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; - - pca6416_0: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6414>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - pca6416_1: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&mipi_csi { - status = "okay"; - ports { - port@0 { - imx8mm_mipi_csi_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,tx-deemph-gen1 = <0x2d>; - fsl,tx-deemph-gen2 = <0xf>; - fsl,clkreq-unsupported; - clocks = <&pcie0_refclk_gated>; - clock-names = "ref"; - status = "okay"; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&pcie0_refclk_gated>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_PCIE1_CTRL>; - assigned-clock-rates = <10000000>, <250000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, - <&clk IMX8MM_SYS_PLL2_250M>; - vpcie-supply = <®_pcie0>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MM_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usbotg1>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usbotg2 { - pinctrl-names = "default"; - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - -&usbphynop2 { - reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_espi2: espi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_led3: led3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 - >; - }; - - pinctrl_ov5640: ov5640grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 - >; - }; - - pinctrl_pcal6414: pcal6414-gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 - >; - }; - - pinctrl_reg_usb_otg1: usbotg1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 - MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 - MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 - MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts deleted file mode 100644 index 50274540284..00000000000 --- a/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 NXP - * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "imx8mm.dtsi" -#include "imx8mm-icore-mx8mm.dtsi" - -/ { - model = "Engicam i.Core MX8M Mini C.TOUCH 2.0"; - compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm", - "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; - -&fec1 { - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* SD */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - max-frequency = <50000000>; - bus-width = <4>; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts deleted file mode 100644 index ddac8bc7ae6..00000000000 --- a/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 NXP - * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; -#include "imx8mm.dtsi" -#include "imx8mm-icore-mx8mm.dtsi" - -/ { - model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit"; - compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm", - "fsl,imx8mm"; - - chosen { - stdout-path = &uart2; - }; -}; - -&fec1 { - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -/* SD */ -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - max-frequency = <50000000>; - bus-width = <4>; - no-1-8-v; - keep-power-in-suspend; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi deleted file mode 100644 index def7bb5d37c..00000000000 --- a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 NXP - * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/ { - compatible = "engicam,icore-mx8mm", "fsl,imx8mm"; -}; - -&A53_0 { - cpu-supply = <®_buck4>; -}; - -&A53_1 { - cpu-supply = <®_buck4>; -}; - -&A53_2 { - cpu-supply = <®_buck4>; -}; - -&A53_3 { - cpu-supply = <®_buck4>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "nxp,pf8121a"; - reg = <0x08>; - - regulators { - reg_ldo1: ldo1 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_ldo2: ldo2 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_ldo3: ldo3 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_ldo4: ldo4 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_buck1: buck1 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_buck2: buck2 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_buck3: buck3 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_buck4: buck4 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_buck5: buck5 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_buck6: buck6 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_buck7: buck7 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_vsnvs: vsnvs { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mm-phg.dts b/arch/arm/dts/imx8mm-phg.dts deleted file mode 100644 index e9447738b10..00000000000 --- a/arch/arm/dts/imx8mm-phg.dts +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Fabio Estevam <[email protected]> - */ - -/dts-v1/; - -#include "imx8mm-tqma8mqml.dtsi" - -/ { - model = "Cloos i.MX8MM PHG board"; - compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; - - aliases { - mmc0 = &usdhc3; - mmc1 = &usdhc2; - }; - - chosen { - stdout-path = &uart2; - }; - - beeper { - compatible = "gpio-beeper"; - pinctrl-0 = <&pinctrl_beeper>; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - led-0 { - label = "status1"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - led-1 { - label = "status2"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - led-2 { - label = "status3"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - }; - - led-3 { - label = "run"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - - led-4 { - label = "powerled"; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg_vbus_ctrl>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usbphynop1 { - power-domains = <&pgc_otg1>; -}; - -&usbphynop2 { - power-domains = <&pgc_otg2>; -}; - -&usbotg1 { - dr_mode = "host"; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; - assigned-clock-rates = <400000000>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - disable-wp; - no-mmc; - no-sdio; - sd-uhs-sdr104; - sd-uhs-ddr50; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_beeper: beepergrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14 - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14 - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14 - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14 - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14 - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14 - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_otg_vbus_ctrl: otgvbusctrlgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-tqma8mqml.dtsi b/arch/arm/dts/imx8mm-tqma8mqml.dtsi deleted file mode 100644 index f649dfacb4b..00000000000 --- a/arch/arm/dts/imx8mm-tqma8mqml.dtsi +++ /dev/null @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -/* - * Copyright 2020-2021 TQ-Systems GmbH - */ - -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mm.dtsi" - -/ { - model = "TQ-Systems GmbH i.MX8MM TQMa8MxML"; - compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; - - memory@40000000 { - device_type = "memory"; - /* our minimum RAM config will be 1024 MiB */ - reg = <0x00000000 0x40000000 0 0x40000000>; - }; - - /* e-MMC IO, needed for HS modes */ - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - /* identical to buck4_reg, but should never change */ - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - /* 640 MiB */ - size = <0 0x28000000>; - /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ - alloc-ranges = <0 0x40000000 0 0x78000000>; - linux,cma-default; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <84000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - }; -}; - -&gpu_2d { - status = "okay"; -}; - -&gpu_3d { - status = "okay"; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - sensor0: temperature-sensor-eeprom@1b { - compatible = "nxp,se97", "jedec,jc-42.4-temp"; - reg = <0x1b>; - }; - - pca9450: pmic@25 { - compatible = "nxp,pca9450a"; - reg = <0x25>; - - /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ - pinctrl-0 = <&pinctrl_pmic>; - pinctrl-names = "default"; - interrupt-parent = <&gpio1>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; - - regulators { - /* V_0V85_SOC: 0.85 */ - buck1_reg: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - /* VDD_ARM */ - buck2_reg: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - regulator-ramp-delay = <3125>; - }; - - /* V_0V85_GPU / DRAM / VPU */ - buck3_reg: BUCK3 { - regulator-name = "BUCK3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - /* VCC3V3 -> VMMC, ... must not be changed */ - buck4_reg: BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ - buck5_reg: BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_1V1 -> RAM, ... must not be changed */ - buck6_reg: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_1V8_SNVS */ - ldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_0V8_SNVS */ - ldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_1V8_ANA */ - ldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* V_0V9_MIPI */ - ldo4_reg: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VCC SD IO - switched using SD2 VSELECT */ - ldo5_reg: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - - pcf85063: rtc@51 { - compatible = "nxp,pcf85063a"; - reg = <0x51>; - quartz-load-femtofarads = <7000>; - }; - - eeprom1: eeprom@53 { - compatible = "nxp,se97b", "atmel,24c02"; - read-only; - reg = <0x53>; - pagesize = <16>; - }; - - eeprom0: eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - pagesize = <32>; - }; -}; - -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - fsl,clkreq-unsupported; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc1v8>; - status = "okay"; -}; - -/* - * Attention: - * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR - * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. - */ -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_flexspi: flexspigrp { - fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>, - <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, - <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, - <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, - <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, - <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>, - <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>; - }; - - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>, - <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, - <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, - <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, - <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, - <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, - <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, - /* option USDHC3_RESET_B not defined, only in RM */ - <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, - <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, - <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, - <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, - <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, - <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, - /* option USDHC3_RESET_B not defined, only in RM */ - <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, - <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, - <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, - <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, - <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, - <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, - <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, - <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, - <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, - /* option USDHC3_RESET_B not defined, only in RM */ - <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; - }; -}; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index d891e8062fe..50ecb6cad39 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -50,14 +50,6 @@ section { pad-byte = <0x00>; -#ifdef CONFIG_FSPI_CONF_HEADER - fspi_conf_block { - filename = CONFIG_FSPI_CONF_FILE; - type = "blob-ext"; - size = <0x1000>; - }; -#endif - #ifdef CONFIG_IMX_HAB nxp-imx8mcst@0 { filename = "u-boot-spl-mkimage.signed.bin"; @@ -68,7 +60,12 @@ binman_imx_spl: nxp-imx8mimage { filename = "u-boot-spl-mkimage.bin"; +#ifdef CONFIG_FSPI_CONF_HEADER + nxp,boot-from = "fspi"; + nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE; +#else nxp,boot-from = "sd"; +#endif nxp,rom-version = <1>; nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; args; /* Needed by mkimage etype superclass */ @@ -85,25 +82,25 @@ }; ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; diff --git a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi b/arch/arm/dts/imx8mn-beacon-baseboard.dtsi deleted file mode 100644 index 9e82069c941..00000000000 --- a/arch/arm/dts/imx8mn-beacon-baseboard.dtsi +++ /dev/null @@ -1,309 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2020 Compass Electronics Group, LLC - */ - -/ { - leds { - compatible = "gpio-leds"; - - led-0 { - label = "gen_led0"; - gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-1 { - label = "gen_led1"; - gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-2 { - label = "gen_led2"; - gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - led-3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led3>; - label = "heartbeat"; - gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "3v3_aud"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - regulator-name = "vsd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb_otg_vbus: regulator-usb { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb_otg>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_espi2>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - eeprom@0 { - compatible = "microchip,at25160bn", "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - pagesize = <32>; - size = <2048>; - address-width = <16>; - }; -}; - -&i2c4 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - pca6416_0: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6414>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - pca6416_1: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - wm8962: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - DCVDD-supply = <®_audio>; - DBVDD-supply = <®_audio>; - AVDD-supply = <®_audio>; - CPVDD-supply = <®_audio>; - MICVDD-supply = <®_audio>; - PLLVDD-supply = <®_audio>; - SPKVDD1-supply = <®_audio>; - SPKVDD2-supply = <®_audio>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; -}; - -&easrc { - fsl,asrc-rate = <48000>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MN_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MN_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - vbus-supply = <®_usb_otg_vbus>; - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_espi2: espi2grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_led3: led3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 - >; - }; - - pinctrl_pcal6414: pcal6414-gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 - >; - }; - - pinctrl_reg_usb_otg: reg-otggrp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 - MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 - MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 - MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi deleted file mode 100644 index 261c3654007..00000000000 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ /dev/null @@ -1,533 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 NXP - */ - -#include <dt-bindings/usb/pd.h> -#include "imx8mn.dtsi" - -/ { - chosen { - stdout-path = &uart2; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - status { - label = "yellow:status"; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ir>; - linux,autosuspend-period = <125>; - }; - - audio_codec_bt_sco: audio-codec-bt-sco { - compatible = "linux,bt-sco"; - #sound-dai-cells = <1>; - }; - - wm8524: audio-codec { - #sound-dai-cells = <0>; - compatible = "wlf,wm8524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_wlf>; - wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - clock-names = "mclk"; - }; - - sound-bt-sco { - compatible = "simple-audio-card"; - simple-audio-card,name = "bt-sco-audio"; - simple-audio-card,format = "dsp_a"; - simple-audio-card,bitclock-inversion; - simple-audio-card,frame-master = <&btcpu>; - simple-audio-card,bitclock-master = <&btcpu>; - - btcpu: simple-audio-card,cpu { - sound-dai = <&sai2>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - - simple-audio-card,codec { - sound-dai = <&audio_codec_bt_sco 1>; - }; - }; - - sound-wm8524 { - compatible = "fsl,imx-audio-wm8524"; - model = "wm8524-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8524>; - audio-asrc = <&easrc>; - audio-routing = - "Line Out Jack", "LINEVOUTL", - "Line Out Jack", "LINEVOUTR"; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif1>; - spdif-out; - spdif-in; - }; -}; - -&easrc { - fsl,asrc-rate = <48000>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - qca,disable-smarteee; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi>; - status = "okay"; - - flash0: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <166000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec1>; - reg = <0x50>; - interrupt-parent = <&gpio2>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - status = "okay"; - - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 20000, 3000)>; - op-sink-microwatt = <15000000>; - self-powered; - }; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - pca6416: gpio@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&sai2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MN_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MN_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&spdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif1>; - assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; - assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - assigned-clocks = <&clk IMX8MN_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - >; - }; - - pinctrl_gpio_wlf: gpiowlfgrp { - fsl,pins = < - MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 - >; - }; - - pinctrl_ir: irgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 - MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - >; - }; - - pinctrl_spdif1: spdif1grp { - fsl,pins = < - MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 - MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 - >; - }; - - pinctrl_typec1: typec1grp { - fsl,pins = < - MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 - MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 - MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 - MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 - >; - }; -}; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 29eecd6d70d..690f56e65bb 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -104,14 +104,6 @@ section { pad-byte = <0x00>; -#ifdef CONFIG_FSPI_CONF_HEADER - fspi_conf_block { - filename = CONFIG_FSPI_CONF_FILE; - type = "blob-ext"; - offset = <0x400>; - }; -#endif - #ifdef CONFIG_IMX_HAB nxp-imx8mcst@0 { filename = "u-boot-spl-mkimage.signed.bin"; @@ -122,7 +114,12 @@ binman_imx_spl: nxp-imx8mimage { filename = "u-boot-spl-mkimage.bin"; +#ifdef CONFIG_FSPI_CONF_HEADER + nxp,boot-from = "fspi"; + nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE; +#else nxp,boot-from = "sd"; +#endif nxp,rom-version = <2>; nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; args; /* Needed by mkimage etype superclass */ @@ -140,7 +137,7 @@ ddr-1d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; #elif CONFIG_IMX8M_DDR4 filename = "ddr4_imem_1d_201810.bin"; #else @@ -152,7 +149,7 @@ ddr-1d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; #elif CONFIG_IMX8M_DDR4 filename = "ddr4_dmem_1d_201810.bin"; #else @@ -165,7 +162,7 @@ #if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4) ddr-2d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; #else filename = "ddr4_imem_2d_201810.bin"; #endif @@ -175,7 +172,7 @@ ddr-2d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; #else filename = "ddr4_dmem_2d_201810.bin"; #endif diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts deleted file mode 100644 index a02b31c42db..00000000000 --- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 NXP - * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include "imx8mp-icore-mx8mp.dtsi" -#include <dt-bindings/usb/pd.h> - -/ { - model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit"; - compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp", - "fsl,imx8mp"; - - chosen { - stdout-path = &uart2; - }; - - reg_usb1_vbus: regulator-usb1 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb1_host_vbus"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - }; -}; - -/* Ethernet */ -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - micrel,led-mode = <0>; - reg = <7>; - }; - }; -}; - -/* console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -/* SDCARD */ -&usdhc2 { - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - pinctrl-names = "default" ; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x10 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 - >; - }; - - pinctrl_reg_usb1: regusb1grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-icore-mx8mp.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp.dtsi deleted file mode 100644 index a6319824ea2..00000000000 --- a/arch/arm/dts/imx8mp-icore-mx8mp.dtsi +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 NXP - * Copyright (c) 2019 Engicam srl - * Copyright (c) 2020 Amarula Solutions(India) - */ - -/ { - compatible = "engicam,icore-mx8mp", "fsl,imx8mp"; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pca9450: pmic@25 { - compatible = "nxp,pca9450c"; - interrupt-parent = <&gpio3>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - reg = <0x25>; - - regulators { - buck1: BUCK1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1000000>; - regulator-name = "BUCK1"; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1025000>; - regulator-min-microvolt = <720000>; - regulator-name = "BUCK2"; - regulator-ramp-delay = <3125>; - }; - - buck4: BUCK4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3600000>; - regulator-min-microvolt = <3000000>; - regulator-name = "BUCK4"; - }; - - buck5: BUCK5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1950000>; - regulator-min-microvolt = <1650000>; - regulator-name = "BUCK5"; - }; - - buck6: BUCK6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1155000>; - regulator-min-microvolt = <1045000>; - regulator-name = "BUCK6"; - }; - - ldo1: LDO1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1950000>; - regulator-min-microvolt = <1650000>; - regulator-name = "LDO1"; - }; - - ldo3: LDO3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1890000>; - regulator-min-microvolt = <1710000>; - regulator-name = "LDO3"; - }; - - ldo5: LDO5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "LDO5"; - }; - }; - }; -}; - -/* EMMC */ -&usdhc3 { - bus-width = <8>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - status = "okay"; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 - >; - }; -}; diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi b/arch/arm/dts/imx8mp-msc-sm2s-ep1-u-boot.dtsi index ce61ca6671e..ce61ca6671e 100644 --- a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-msc-sm2s-ep1-u-boot.dtsi diff --git a/arch/arm/dts/imx8mp-msc-sm2s.dts b/arch/arm/dts/imx8mp-msc-sm2s.dts deleted file mode 100644 index 5dbec71747c..00000000000 --- a/arch/arm/dts/imx8mp-msc-sm2s.dts +++ /dev/null @@ -1,820 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022 Avnet Embedded GmbH - */ - -/dts-v1/; - -#include "imx8mp.dtsi" -#include <dt-bindings/net/ti-dp83867.h> - -/ { - aliases { - rtc0 = &sys_rtc; - rtc1 = &snvs_rtc; - }; - - chosen { - stdout-path = &uart2; - }; - - reg_usb0_host_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb0_host_vbus"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_vbus>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usb1_host_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1_host_vbus"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_vbus>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; - - reg_flexcan1_xceiver: regulator-flexcan1 { - compatible = "regulator-fixed"; - regulator-name = "flexcan1-xceiver"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_flexcan2_xceiver: regulator-flexcan2 { - compatible = "regulator-fixed"; - regulator-name = "flexcan2-xceiver"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lcd0_backlight: backlight-0 { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_backlight>; - pwms = <&pwm1 0 100000 0>; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <255>; - enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - lcd1_backlight: backlight-1 { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_backlight>; - pwms = <&pwm2 0 100000 0>; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <255>; - enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - status = "okay"; - - led-sw { - label = "sw-led"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - }; - - extcon_usb0: extcon-usb0 { - compatible = "linux,extcon-usb-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_extcon>; - id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; -}; - -&A53_0 { - cpu-supply = <&vcc_arm>; -}; - -&A53_1 { - cpu-supply = <&vcc_arm>; -}; - -&A53_2 { - cpu-supply = <&vcc_arm>; -}; - -&A53_3 { - cpu-supply = <&vcc_arm>; -}; - -&ecspi1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -&ecspi2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; - reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - eee-broken-1000t; - reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clock-frequency = <400000>; - status = "okay"; - - id_eeprom: eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <400000>; - status = "disabled"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <400000>; - status = "disabled"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <400000>; - status = "disabled"; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c5>; - clock-frequency = <400000>; - status = "disabled"; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c6>; - clock-frequency = <400000>; - status = "okay"; - - tca6424: gpio@22 { - compatible = "ti,tca6424"; - reg = <0x22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tca6424>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#", - "gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int", - "PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#", - "wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#", - "gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#", - "CHARGER_PRSNT#"; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_RISING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - dsi_lvds_bridge: bridge@2d { - compatible = "ti,sn65dsi83"; - reg = <0x2d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds_bridge>; - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - pmic: pmic@30 { - compatible = "ricoh,rn5t567"; - reg = <0x30>; - interrupt-parent = <&tca6424>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - - regulators { - DCDC1 { - regulator-name = "VCC_SOC"; - regulator-always-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - }; - - DCDC2 { - regulator-name = "VCC_DRAM"; - regulator-always-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - vcc_arm: DCDC3 { - regulator-name = "VCC_ARM"; - regulator-always-on; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - }; - - DCDC4 { - regulator-name = "VCC_1V8"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - LDO1 { - regulator-name = "VCC_LDO1_2V5"; - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - LDO2 { - regulator-name = "VCC_LDO2_1V8"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - LDO3 { - regulator-name = "VCC_ETH_2V5"; - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - LDO4 { - regulator-name = "VCC_DDR4_2V5"; - regulator-always-on; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - LDO5 { - regulator-name = "VCC_LDO5_1V8"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - LDORTC1 { - regulator-name = "VCC_SNVS_1V8"; - regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - LDORTC2 { - regulator-name = "VCC_SNVS_3V3"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - sys_rtc: rtc@32 { - compatible = "ricoh,r2221tl"; - reg = <0x32>; - interrupt-parent = <&tca6424>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - }; - - tmp_sensor: temperature-sensor@71 { - compatible = "ti,tmp103"; - reg = <0x71>; - }; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_flexcan1_xceiver>; - status = "disabled"; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_flexcan2_xceiver>; - status = "disabled"; -}; - -&flexspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexspi0>; - status = "okay"; - - qspi_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <80000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "disabled"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "disabled"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "disabled"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; -}; - -&usb3_phy0 { - vbus-supply = <®_usb0_host_vbus>; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_usb1_host_vbus>; - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - extcon = <&extcon_usb0>; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = - <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82>, - <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82>, - <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82>, - <MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x40000>, - <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x40000>; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = - <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82>, - <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82>, - <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82>, - <MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x40000>, - <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x40000>; - }; - - pinctrl_eqos: eqosgrp { - fsl,pins = - <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, - <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, - <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, - <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, - <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, - <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, - <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, - <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, - <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, - <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, - <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, - <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, - <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, - <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; - }; - - pinctrl_fec: fecgrp { - fsl,pins = - <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, - <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, - <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, - <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, - <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, - <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, - <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, - <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, - <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, - <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, - <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, - <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, - <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, - <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = - <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154>, - <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154>; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = - <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154>, - <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154>; - }; - - pinctrl_flexspi0: flexspi0grp { - fsl,pins = - <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, - <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, - <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, - <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, - <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, - <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, - <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x19>; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = - <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3>, - <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = - <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>, - <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3>; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = - <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3>, - <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3>; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = - <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3>, - <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3>; - }; - - pinctrl_i2c5: i2c5grp { - fsl,pins = - <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3>, - <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3>; - }; - - pinctrl_i2c6: i2c6grp { - fsl,pins = - <MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3>, - <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>; - }; - - pinctrl_lcd0_backlight: lcd0-backlightgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41>; - }; - - pinctrl_lcd1_backlight: lcd1-backlightgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x41>; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19>; - }; - - pinctrl_lvds_bridge: lvds-bridgegrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x41>; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = - <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116>; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = - <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116>; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x116>; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = - <MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116>; - }; - - pinctrl_tca6424: tca6424grp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x41>; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = - <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49>, - <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49>; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = - <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x1c4>, - <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x1c4>, - <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49>, - <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49>; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = - <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>, - <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4>, - <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49>, - <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49>; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = - <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49>, - <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49>; - }; - - pinctrl_usb0_extcon: usb0-extcongrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x19>; - }; - - pinctrl_usb0_vbus: usb0-vbusgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19>; - }; - - pinctrl_usb1_vbus: usb1-vbusgrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19>; - }; - - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>, - <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4>; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>, - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>; - }; - - pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41>; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>, - <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, - <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, - <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>, - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6>, - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6>, - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6>, - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6>, - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6>, - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6>, - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6>, - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6>, - <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; - }; -}; diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index d987f68b6ba..ca80dc994b1 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -2,19 +2,105 @@ #include "imx8mq-u-boot.dtsi" +&aips1 { + bootph-all; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&pinctrl_i2c1 { + bootph-all; +}; + +&i2c1 { + bootph-all; +}; + +&soc { + bootph-all; + bootph-pre-ram; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} { + bootph-all; +}; + &pinctrl_uart1 { bootph-pre-ram; }; +&uart1 { + bootph-pre-ram; +}; + &usdhc1 { + bootph-pre-ram; mmc-hs400-1_8v; + /delete-property/ vqmmc-supply; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; }; &usdhc2 { + bootph-pre-ram; sd-uhs-sdr104; sd-uhs-ddr50; }; -&uart1 { +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2 { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +#ifdef CONFIG_FSL_CAAM +&crypto { + bootph-pre-ram; +}; + +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { bootph-pre-ram; }; +#endif diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi index d361f3f5592..7ab7706d7a7 100644 --- a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi @@ -2,26 +2,90 @@ #include "imx8mq-u-boot.dtsi" +&aips1 { + bootph-all; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&pinctrl_i2c1 { + bootph-all; +}; + +&i2c1 { + bootph-all; +}; + +&soc { + bootph-all; + bootph-pre-ram; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@8} { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@8/regulators} { + bootph-all; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&uart1 { + bootph-pre-ram; +}; + &usdhc1 { + bootph-pre-ram; mmc-hs400-1_8v; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; }; &usdhc2 { + bootph-pre-ram; sd-uhs-sdr104; sd-uhs-ddr50; }; +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2 { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + &uart1 { + bootph-pre-ram; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; }; &uart2 { + bootph-pre-ram; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; }; &uart3 { + bootph-pre-ram; /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; }; diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts deleted file mode 100644 index a91c136797f..00000000000 --- a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts +++ /dev/null @@ -1,613 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree File for the Kontron pitx-imx8m board. - * - * Copyright (C) 2021 Heiko Thiery <[email protected]> - */ - -/dts-v1/; - -#include "imx8mq.dtsi" -#include <dt-bindings/net/ti-dp83867.h> - -/ { - model = "Kontron pITX-imx8m"; - compatible = "kontron,pitx-imx8m", "fsl,imx8mq"; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - spi0 = &qspi0; - spi1 = &ecspi2; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - pcie0_refclk: pcie0-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie1_refclk: pcie1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2>; - regulator-name = "V_3V3_SD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <20000>; - enable-active-high; - }; -}; - -&ecspi2 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@0 { - compatible = "infineon,slb9670"; - reg = <0>; - spi-max-frequency = <43000000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - reset-assert-us = <10>; - reset-deassert-us = <280>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@8 { - compatible = "fsl,pfuze100"; - fsl,pfuze-support-disable-sw; - reg = <0x8>; - - regulators { - sw1a_reg: sw1ab { - regulator-name = "V_0V9_GPU"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw1c_reg: sw1c { - regulator-name = "V_0V9_VPU"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - }; - - sw2_reg: sw2 { - regulator-name = "V_1V1_NVCC_DRAM"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw3a_reg: sw3ab { - regulator-name = "V_1V0_DRAM"; - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-name = "V_1V8_S0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-name = "NC"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-name = "V_0V9_SNVS"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-name = "V_0V55_VREF_DDR"; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-name = "V_1V5_CSI"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen2_reg: vgen2 { - regulator-name = "V_0V9_PHY"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <975000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-name = "V_1V8_PHY"; - regulator-min-microvolt = <1675000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-name = "V_1V8_VDDA"; - regulator-min-microvolt = <1625000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-name = "V_3V3_PHY"; - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3625000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-name = "V_2V8_CAM"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - fan-controller@1b { - compatible = "maxim,max6650"; - reg = <0x1b>; - maxim,fan-microvolt = <5000000>; - }; - - rtc@32 { - compatible = "microcrystal,rv8803"; - reg = <0x32>; - }; - - sensor@4b { - compatible = "national,lm75b"; - reg = <0x4b>; - }; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; -}; - -/* M.2 B-key slot */ -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, - <&clk IMX8MQ_CLK_PCIE1_AUX>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -/* Intel Ethernet Controller I210/I211 */ -&pcie1 { - clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - fsl,max-link-speed = <1>; - status = "okay"; -}; - -&pgc_gpu { - power-supply = <&sw1a_reg>; -}; - -&pgc_vpu { - power-supply = <&sw1c_reg>; -}; - -&qspi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - m25p,fast-read; - spi-max-frequency = <50000000>; - }; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MQ_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - assigned-clocks = <&clk IMX8MQ_CLK_UART2>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - assigned-clocks = <&clk IMX8MQ_CLK_UART3>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - maximum-speed = "high-speed"; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <&sw4_reg>; - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */ - MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */ - MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */ - MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */ - MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */ - MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */ - MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */ - MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */ - MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */ - >; - }; - - pinctrl_pcie0: pcie0grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */ - MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */ - >; - }; - - pinctrl_reg_usdhc2: regusdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 - MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 - MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 - MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 - MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 - >; - }; - - pinctrl_ecspi2_cs: ecspi2csgrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 - MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usb0: usb0grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19 - MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-librem5-r3.dtsi b/arch/arm/dts/imx8mq-librem5-r3.dtsi deleted file mode 100644 index e4f8b47cce4..00000000000 --- a/arch/arm/dts/imx8mq-librem5-r3.dtsi +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2021 Purism SPC <[email protected]> - -/dts-v1/; - -/* - * This file describes hardware that is shared among r3 ("Dogwood") and - * later revisions of the Librem 5 so it has to be included in dts there. - */ - -#include "imx8mq-librem5.dtsi" - -/ { - model = "Purism Librem 5r3"; - compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq"; -}; - -&accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; -}; - -&bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ - ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ -}; - -&camera_front { - pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>; - shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; -}; - -&iomuxc { - pinctrl_r3_camera_pwr: r3camerapwrgrp { - fsl,pins = < - MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83 - >; - }; -}; - -&proximity { - proximity-near-level = <25>; -}; diff --git a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi index 98da015a444..4d326040c0a 100644 --- a/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi @@ -10,7 +10,7 @@ bootph-pre-ram; }; -&binman_imx_spl { +&binman { section { signed-hdmi-imx8m { filename = "signed_dp_imx8m.bin"; diff --git a/arch/arm/dts/imx8mq-librem5-r4.dts b/arch/arm/dts/imx8mq-librem5-r4.dts deleted file mode 100644 index 1056b7981bd..00000000000 --- a/arch/arm/dts/imx8mq-librem5-r4.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2021 Purism SPC <[email protected]> - -/dts-v1/; - -#include "imx8mq-librem5-r3.dtsi" - -/ { - model = "Purism Librem 5r4"; - compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq"; -}; - -&bat { - maxim,rsns-microohm = <1667>; -}; - -&led_backlight { - led-max-microamp = <25000>; -}; - -&lcd_panel { - compatible = "ys,ys57pss36bh5gq"; -}; - -&proximity { - proximity-near-level = <10>; -}; diff --git a/arch/arm/dts/imx8mq-librem5.dtsi b/arch/arm/dts/imx8mq-librem5.dtsi deleted file mode 100644 index ae08556b2ef..00000000000 --- a/arch/arm/dts/imx8mq-librem5.dtsi +++ /dev/null @@ -1,1382 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018-2020 Purism SPC - */ - -/dts-v1/; - -#include "dt-bindings/input/input.h" -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/leds/common.h> -#include "dt-bindings/pwm/pwm.h" -#include "dt-bindings/usb/pd.h" -#include "imx8mq.dtsi" - -/ { - model = "Purism Librem 5"; - compatible = "purism,librem5", "fsl,imx8mq"; - chassis-type = "handset"; - - backlight_dsi: backlight-dsi { - compatible = "led-backlight"; - leds = <&led_backlight>; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - chosen { - stdout-path = &uart1; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_keys>; - - key-vol-down { - label = "VOL_DOWN"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <50>; - wakeup-source; - }; - - key-vol-up { - label = "VOL_UP"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <50>; - wakeup-source; - }; - }; - - led-controller { - compatible = "pwm-leds"; - - led-0 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_BLUE>; - max-brightness = <248>; - pwms = <&pwm2 0 50000 0>; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - max-brightness = <248>; - pwms = <&pwm4 0 50000 0>; - }; - - led-2 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_RED>; - max-brightness = <248>; - pwms = <&pwm3 0 50000 0>; - }; - }; - - reg_aud_1v8: regulator-audio-1v8 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audiopwr>; - regulator-name = "AUDIO_PWR_EN"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* - * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC - * since we can't have it twice in the 2 different regulator nodes. - */ - reg_csi_1v8: regulator-csi-1v8 { - compatible = "regulator-fixed"; - regulator-name = "CAMERA_VDDIO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_vdd_3v3>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - /* controlled by the CAMERA_POWER_KEY HKS */ - reg_vcam_1v2: regulator-vcam-1v2 { - compatible = "regulator-fixed"; - regulator-name = "CAMERA_VDDD_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <®_vdd_1v8>; - enable-active-high; - }; - - reg_vcam_2v8: regulator-vcam-2v8 { - compatible = "regulator-fixed"; - regulator-name = "CAMERA_VDDA_2V8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - vin-supply = <®_vdd_3v3>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_gnss: regulator-gnss { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gnsspwr>; - regulator-name = "GNSS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_hub: regulator-hub { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hub_pwr>; - regulator-name = "HUB"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_lcd_1v8: regulator-lcd-1v8 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dsien>; - regulator-name = "LCD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_vdd_1v8>; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* Otherwise i2c3 is not functional */ - regulator-always-on; - }; - - reg_lcd_3v4: regulator-lcd-3v4 { - compatible = "regulator-fixed"; - regulator-name = "LCD_3V4"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dsibiasen>; - vin-supply = <®_vsys_3v4>; - gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vdd_sen: regulator-vdd-sen { - compatible = "regulator-fixed"; - regulator-name = "VDD_SEN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vdd_1v8: regulator-vdd-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&buck7_reg>; - }; - - reg_vdd_3v3: regulator-vdd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_vsys_3v4: regulator-vsys-3v4 { - compatible = "regulator-fixed"; - regulator-name = "VSYS_3V4"; - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - regulator-always-on; - }; - - reg_wifi_3v3: regulator-wifi-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pwr>; - regulator-name = "3V3_WIFI"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vdd_3v3>; - }; - - sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hp>; - simple-audio-card,name = "Librem 5"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Headphone", "Headphones", - "Microphone", "Headset Mic", - "Microphone", "Digital Mic", - "Speaker", "Speaker"; - simple-audio-card,routing = - "Headphones", "HPOUTL", - "Headphones", "HPOUTR", - "Speaker", "SPKOUTL", - "Speaker", "SPKOUTR", - "Headset Mic", "MICBIAS", - "IN3R", "Headset Mic", - "DMICDAT", "Digital Mic"; - simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; - - simple-audio-card,cpu { - sound-dai = <&sai2>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - frame-master; - bitclock-master; - }; - }; - - sound-wwan { - compatible = "simple-audio-card"; - simple-audio-card,name = "Modem"; - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&sai6>; - frame-inversion; - }; - - simple-audio-card,codec { - sound-dai = <&bm818_codec>; - frame-master; - bitclock-master; - }; - }; - - usdhc2_pwrseq: pwrseq { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt>, <&pinctrl_wifi_disable>; - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>, - <&gpio4 29 GPIO_ACTIVE_HIGH>; - }; - - bm818_codec: sound-wwan-codec { - compatible = "broadmobi,bm818", "option,gtm601"; - #sound-dai-cells = <0>; - }; - - vibrator { - compatible = "pwm-vibrator"; - pwms = <&pwm1 0 1000000000 0>; - pwm-names = "enable"; - vcc-supply = <®_vdd_3v3>; - }; -}; - -&A53_0 { - cpu-supply = <&buck2_reg>; -}; - -&A53_1 { - cpu-supply = <&buck2_reg>; -}; - -&A53_2 { - cpu-supply = <&buck2_reg>; -}; - -&A53_3 { - cpu-supply = <&buck2_reg>; -}; - -&csi1 { - status = "okay"; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - status = "okay"; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; -}; - -&dphy { - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - nor_flash: flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "protected0"; - reg = <0x0 0x30000>; - read-only; - }; - - partition@30000 { - label = "firmware"; - reg = <0x30000 0x1d0000>; - read-only; - }; - }; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic_5v>; - - pmic-5v-hog { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - input; - lane-mapping = "pmic-5v"; - }; -}; - -&iomuxc { - pinctrl_audiopwr: audiopwrgrp { - fsl,pins = < - /* AUDIO_POWER_EN_3V3 */ - MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x83 - >; - }; - - pinctrl_bl: blgrp { - fsl,pins = < - /* BACKLINGE_EN */ - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83 - >; - }; - - pinctrl_bt: btgrp { - fsl,pins = < - /* BT_REG_ON */ - MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x83 - >; - }; - - pinctrl_camera_pwr: camerapwrgrp { - fsl,pins = < - /* CAMERA_PWR_EN_3V3 */ - MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83 - >; - }; - - pinctrl_csi1: csi1grp { - fsl,pins = < - /* CSI1_NRST */ - MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83 - >; - }; - - pinctrl_charger_in: chargeringrp { - fsl,pins = < - /* CHRG_INT */ - MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 - >; - }; - - pinctrl_dsibiasen: dsibiasengrp { - fsl,pins = < - /* DSI_BIAS_EN */ - MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x83 - >; - }; - - pinctrl_dsien: dsiengrp { - fsl,pins = < - /* DSI_EN_3V3 */ - MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x83 - >; - }; - - pinctrl_dsirst: dsirstgrp { - fsl,pins = < - /* DSI_RST */ - MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x83 - /* DSI_TE */ - MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x83 - /* TP_RST */ - MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x83 - >; - }; - - pinctrl_ecspi1: ecspigrp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x83 - MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x83 - MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 - MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x83 - >; - }; - - pinctrl_gauge: gaugegrp { - fsl,pins = < - /* BAT_LOW */ - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x80 - >; - }; - - pinctrl_gnsspwr: gnsspwrgrp { - fsl,pins = < - /* GPS3V3_EN */ - MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x83 - >; - }; - - pinctrl_haptic: hapticgrp { - fsl,pins = < - /* MOTO */ - MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x83 - >; - }; - - pinctrl_hp: hpgrp { - fsl,pins = < - /* HEADPHONE_DET_1V8 */ - MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x180 - >; - }; - - pinctrl_hub_pwr: hubpwrgrp { - fsl,pins = < - /* HUB_PWR_3V3_EN */ - MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x83 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000026 - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000026 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000026 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000026 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000026 - >; - }; - - pinctrl_keys: keysgrp { - fsl,pins = < - /* VOL- */ - MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 - /* VOL+ */ - MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 - >; - }; - - pinctrl_led_b: ledbgrp { - fsl,pins = < - /* LED_B */ - MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x06 - >; - }; - - pinctrl_led_g: ledggrp { - fsl,pins = < - /* LED_G */ - MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x06 - >; - }; - - pinctrl_led_r: ledrgrp { - fsl,pins = < - /* LED_R */ - MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x06 - >; - }; - - pinctrl_mag: maggrp { - fsl,pins = < - /* INT_MAG */ - MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x80 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - /* PMIC_NINT */ - MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 - >; - }; - - pinctrl_pmic_5v: pmic5vgrp { - fsl,pins = < - /* PMIC_5V */ - MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x80 - >; - }; - - pinctrl_prox: proxgrp { - fsl,pins = < - /* INT_LIGHT */ - MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x80 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - /* RTC_INT */ - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - >; - }; - - pinctrl_sai6: sai6grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 - >; - }; - - pinctrl_tcpc: tcpcgrp { - fsl,pins = < - /* TCPC_INT */ - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - /* TP_INT */ - MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x80 - >; - }; - - pinctrl_typec: typecgrp { - fsl,pins = < - /* TYPEC_MUX_EN */ - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x83 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 - MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 - MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 - MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd - MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf - MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1 - >; - }; - - pinctrl_wifi_disable: wifidisablegrp { - fsl,pins = < - /* WIFI_REG_ON */ - MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x83 - >; - }; - - pinctrl_wifi_pwr: wifipwrgrp { - fsl,pins = < - /* WIFI3V3_EN */ - MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x83 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - /* nWDOG */ - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x1f - >; - }; -}; - -&i2c1 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - typec_pd: usb-pd@3f { - compatible = "ti,tps6598x"; - reg = <0x3f>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_typec>, <&pinctrl_tcpc>; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_con_hs: endpoint { - remote-endpoint = <&typec_hs>; - }; - }; - - port@1 { - reg = <1>; - - usb_con_ss: endpoint { - remote-endpoint = <&typec_ss>; - }; - }; - }; - }; - }; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>; - clocks = <&pmic_osc>; - clock-names = "osc"; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - regulator-always-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - regulator-always-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck4_reg: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - rohm,dvs-run-voltage = <1000000>; - }; - - buck5_reg: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - /* leave on for snvs power button */ - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: LDO5 { - /* VDD_PHY_0V9 - MIPI and HDMI domains */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo6_reg: LDO6 { - /* VDD_PHY_0V9 - MIPI, HDMI and USB domains */ - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - /* VDD_PHY_3V3 - USB domain */ - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - rtc@68 { - compatible = "microcrystal,rv4162"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c2 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - magnetometer@1e { - compatible = "st,lsm9ds1-magn"; - reg = <0x1e>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mag>; - interrupt-parent = <&gpio3>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - vdd-supply = <®_vdd_sen>; - vddio-supply = <®_vdd_1v8>; - }; - - regulator@3e { - compatible = "tps65132"; - reg = <0x3e>; - - reg_lcd_avdd: outp { - regulator-name = "LCD_AVDD"; - vin-supply = <®_lcd_3v4>; - }; - - reg_lcd_avee: outn { - regulator-name = "LCD_AVEE"; - vin-supply = <®_lcd_3v4>; - }; - }; - - proximity: prox@60 { - compatible = "vishay,vcnl4040"; - reg = <0x60>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_prox>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - }; - - accel_gyro: accel-gyro@6a { - compatible = "st,lsm9ds1-imu"; - reg = <0x6a>; - vdd-supply = <®_vdd_sen>; - vddio-supply = <®_vdd_1v8>; - }; -}; - -&i2c3 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - codec: audio-codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - #sound-dai-cells = <0>; - mic-cfg = <0x200>; - DCVDD-supply = <®_aud_1v8>; - DBVDD-supply = <®_aud_1v8>; - AVDD-supply = <®_aud_1v8>; - CPVDD-supply = <®_aud_1v8>; - MICVDD-supply = <®_aud_1v8>; - PLLVDD-supply = <®_aud_1v8>; - SPKVDD1-supply = <®_vsys_3v4>; - SPKVDD2-supply = <®_vsys_3v4>; - gpio-cfg = < - 0x0000 /* n/c */ - 0x0001 /* gpio2, 1: default */ - 0x0013 /* gpio3, 2: dmicclk */ - 0x0000 /* n/c, 3: default */ - 0x8014 /* gpio5, 4: dmic_dat */ - 0x0000 /* gpio6, 5: default */ - >; - }; - - camera_front: camera@20 { - compatible = "hynix,hi846"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csi1>; - clocks = <&clk IMX8MQ_CLK_CLKO2>; - assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; - assigned-clock-rates = <25000000>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - vdda-supply = <®_vcam_2v8>; - vddd-supply = <®_vcam_1v2>; - vddio-supply = <®_csi_1v8>; - rotation = <90>; - orientation = <0>; - - port { - camera1_ep: endpoint { - data-lanes = <1 2>; - link-frequencies = /bits/ 64 - <80000000 200000000 300000000>; - remote-endpoint = <&mipi1_sensor_ep>; - }; - }; - }; - - backlight@36 { - compatible = "ti,lm36922"; - reg = <0x36>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bl>; - #address-cells = <1>; - #size-cells = <0>; - enable-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - vled-supply = <®_vsys_3v4>; - ti,ovp-microvolt = <25000000>; - - led_backlight: led@0 { - reg = <0>; - label = ":backlight"; - linux,default-trigger = "backlight"; - led-max-microamp = <20000>; - }; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5506"; - reg = <0x38>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - interrupt-parent = <&gpio1>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1440>; - vcc-supply = <®_lcd_1v8>; - }; -}; - -&i2c4 { - clock-frequency = <387000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - vcm@c { - compatible = "dongwoon,dw9714"; - reg = <0x0c>; - vcc-supply = <®_csi_1v8>; - }; - - bat: fuel-gauge@36 { - compatible = "maxim,max17055"; - reg = <0x36>; - interrupt-parent = <&gpio3>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gauge>; - power-supplies = <&bq25895>; - maxim,over-heat-temp = <700>; - maxim,over-volt = <4500>; - maxim,rsns-microohm = <5000>; - }; - - bq25895: charger@6a { - compatible = "ti,bq25895", "ti,bq25890"; - reg = <0x6a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_in>; - interrupt-parent = <&gpio3>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - phys = <&usb3_phy0>; - ti,precharge-current = <130000>; /* uA */ - ti,minimum-sys-voltage = <3700000>; /* uV */ - ti,boost-voltage = <5000000>; /* uV */ - ti,boost-max-current = <1500000>; /* uA */ - ti,use-vinmin-threshold = <1>; /* enable VINDPM */ - ti,vinmin-threshold = <3900000>; /* uV */ - monitored-battery = <&bat>; - power-supplies = <&typec_pd>; - }; -}; - -&lcdif { - status = "okay"; -}; - -&mipi_csi1 { - status = "okay"; - - ports { - port@0 { - reg = <0>; - - mipi1_sensor_ep: endpoint { - remote-endpoint = <&camera1_ep>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&mipi_dsi { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - lcd_panel: panel@0 { - compatible = "mantix,mlaf057we51-x"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dsirst>; - avdd-supply = <®_lcd_avdd>; - avee-supply = <®_lcd_avee>; - vddi-supply = <®_lcd_1v8>; - backlight = <&backlight_dsi>; - reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - mantix,tp-rstn-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; - - port { - panel_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - - mipi_dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pgc_gpu { - power-supply = <&buck3_reg>; -}; - -&pgc_mipi { - power-supply = <&ldo5_reg>; -}; - -&pgc_vpu { - power-supply = <&buck4_reg>; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_haptic>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_b>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_r>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_g>; - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; -}; - -&sai6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai6>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; - assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-synchronous-rx; - status = "okay"; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { /* TPS - GPS - DEBUG */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; - - gnss { - compatible = "globaltop,pa6h"; - vcc-supply = <®_gnss>; - current-speed = <9600>; - }; -}; - -&uart3 { /* SMC */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_hub>; - status = "okay"; -}; - -&usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; - dr_mode = "otg"; - snps,dis_u3_susphy_quirk; - usb-role-switch; - status = "okay"; - - port@0 { - reg = <0>; - - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; - }; - }; - - port@1 { - reg = <1>; - - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; - }; - }; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip USB2642 */ - hub@1 { - compatible = "usb424,2640"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - mass-storage@1 { - compatible = "usb424,4041"; - reg = <1>; - }; - }; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - vmmc-supply = <®_vdd_3v3>; - power-supply = <®_vdd_1v8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <4>; - vmmc-supply = <®_wifi_3v3>; - mmc-pwrseq = <&usdhc2_pwrseq>; - post-power-on-delay-ms = <1000>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - max-frequency = <50000000>; - disable-wp; - cap-sdio-irq; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi index 46a4dfe4e8a..71ce1b5b3ca 100644 --- a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi @@ -9,3 +9,7 @@ &uart1 { /* console */ bootph-pre-ram; }; + +&{/panel} { + compatible = "innolux,n125hce-gn1", "simple-panel"; +}; diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts deleted file mode 100644 index 055031bba8c..00000000000 --- a/arch/arm/dts/imx8mq-mnt-reform2.dts +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/* - * Copyright 2019-2021 MNT Research GmbH - * Copyright 2021 Lucas Stach <[email protected]> - */ - -/dts-v1/; - -#include "imx8mq-nitrogen-som.dtsi" - -/ { - model = "MNT Reform 2"; - compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; - chassis-type = "laptop"; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm2 0 10000 0>; - power-supply = <®_main_usb>; - enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - brightness-levels = <0 32 64 128 160 200 255>; - default-brightness-level = <6>; - }; - - panel { - compatible = "innolux,n125hce-gn1", "simple-panel"; - power-supply = <®_main_3v3>; - backlight = <&backlight>; - no-hpd; - - port { - panel_in: endpoint { - remote-endpoint = <&edp_bridge_out>; - }; - }; - }; - - pcie1_refclk: clock-pcie1-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - reg_main_5v: regulator-main-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_main_3v3: regulator-main-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_main_usb: regulator-main-usb { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_main_5v>; - }; - - reg_main_1v8: regulator-main-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_main_3v3>; - }; - - reg_main_1v2: regulator-main-1v2 { - compatible = "regulator-fixed"; - regulator-name = "1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <®_main_5v>; - }; - - sound { - compatible = "fsl,imx-audio-wm8960"; - audio-cpu = <&sai2>; - audio-codec = <&wm8960>; - audio-routing = - "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN", - "LINPUT1", "Mic Jack", - "Mic Jack", "MICB", - "LINPUT2", "Line In Jack", - "RINPUT2", "Line In Jack"; - model = "wm8960-audio"; - }; -}; - -&dphy { - assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; - assigned-clock-rates = <25000000>; - status = "okay"; -}; - -&fec1 { - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - wm8960: codec@1a { - compatible = "wlf,wm8960"; - reg = <0x1a>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; - clock-names = "mclk"; - #sound-dai-cells = <0>; - }; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <400000>; - status = "okay"; - - edp_bridge: bridge@2c { - compatible = "ti,sn65dsi86"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edp_bridge>; - reg = <0x2c>; - enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - vccio-supply = <®_main_1v8>; - vpll-supply = <®_main_1v8>; - vcca-supply = <®_main_1v2>; - vcc-supply = <®_main_1v2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - edp_bridge_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - - port@1 { - reg = <1>; - - edp_bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; -}; - -&lcdif { - assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; - /delete-property/assigned-clock-rates; - status = "okay"; -}; - -&mipi_dsi { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - mipi_dsi_out: endpoint { - remote-endpoint = <&edp_bridge_in>; - }; - }; - }; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1>; - reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, - <&clk IMX8MQ_CLK_PCIE2_AUX>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&pcie1_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -®_1p8v { - vin-supply = <®_main_5v>; -}; - -®_snvs { - vin-supply = <®_main_5v>; -}; - -®_arm_dram { - vin-supply = <®_main_5v>; -}; - -®_dram_1p1v { - vin-supply = <®_main_5v>; -}; - -®_soc_gpu_vpu { - vin-supply = <®_main_5v>; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; - assigned-clock-rates = <25000000>; - fsl,sai-mclk-direction-output; - fsl,sai-asynchronous; - status = "okay"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usb3_phy0 { - vbus-supply = <®_main_usb>; - status = "okay"; -}; - -&usb3_phy1 { - vbus-supply = <®_main_usb>; - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "host"; - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_main_3v3>; - vmmc-supply = <®_main_3v3>; - bus-width = <4>; - status = "okay"; -}; - -&iomuxc { - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3 - >; - }; - - pinctrl_edp_bridge: edpbridgegrp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022 - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022 - MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022 - >; - }; - - pinctrl_pcie1: pcie1grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3 - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 - MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 - MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 - MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-nitrogen-som.dtsi b/arch/arm/dts/imx8mq-nitrogen-som.dtsi deleted file mode 100644 index 395f77b5aca..00000000000 --- a/arch/arm/dts/imx8mq-nitrogen-som.dtsi +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2018 Boundary Devices - * Copyright 2021 Lucas Stach <[email protected]> - */ - -#include "imx8mq.dtsi" - -/ { - model = "Boundary Devices i.MX8MQ Nitrogen8M"; - compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - reg_1p8v: regulator-fixed-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_snvs: regulator-fixed-snvs { - compatible = "regulator-fixed"; - regulator-name = "VDD_SNVS"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&{/opp-table/opp-800000000} { - opp-microvolt = <1000000>; -}; - -&{/opp-table/opp-1000000000} { - opp-microvolt = <1000000>; -}; - -&A53_0 { - cpu-supply = <®_arm_dram>; -}; - -&A53_1 { - cpu-supply = <®_arm_dram>; -}; - -&A53_2 { - cpu-supply = <®_arm_dram>; -}; - -&A53_3 { - cpu-supply = <®_arm_dram>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <4>; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9546"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_pca9546>; - reg = <0x70>; - reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - - i2c1a: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - reg_arm_dram: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - regulator-name = "VDD_ARM_DRAM_1V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - }; - - i2c1b: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - reg_dram_1p1v: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - regulator-name = "NVCC_DRAM_1P1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - }; - - i2c1c: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - reg_soc_gpu_vpu: regulator@60 { - compatible = "fcs,fan53555"; - reg = <0x60>; - regulator-name = "VDD_SOC_GPU_VPU"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-always-on; - }; - }; - - i2c1d: i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&pgc_gpu { - power-supply = <®_soc_gpu_vpu>; -}; - -&pgc_vpu { - power-supply = <®_soc_gpu_vpu>; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vqmmc-supply = <®_1p8v>; - vmmc-supply = <®_snvs>; - bus-width = <8>; - non-removable; - no-mmc-hs400; - no-sdio; - no-sd; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1 - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1 - MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022 - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022 - >; - }; - - pinctrl_i2c1_pca9546: i2c1-pca9546grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi index 05f809c035d..11b81f0bbb9 100644 --- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi @@ -2,7 +2,12 @@ #include "imx8mq-u-boot.dtsi" +&gpio2 { + bootph-pre-ram; +}; + ®_usdhc2_vmmc { + bootph-pre-ram; u-boot,off-on-delay-us = <20000>; }; @@ -13,3 +18,39 @@ &pinctrl_uart1 { bootph-pre-ram; }; + +&usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mq-phanbell.dts b/arch/arm/dts/imx8mq-phanbell.dts deleted file mode 100644 index a3b9d615a3b..00000000000 --- a/arch/arm/dts/imx8mq-phanbell.dts +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2017-2019 NXP - */ - -/dts-v1/; - -#include "imx8mq.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "Google i.MX8MQ Phanbell"; - compatible = "google,imx8mq-phanbell", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x00000000 0x40000000 0 0x40000000>; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - fan: gpio-fan { - compatible = "gpio-fan"; - gpio-fan,speed-map = <0 0 8600 1>; - gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; - #cooling-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_fan>; - status = "okay"; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; -}; - -&cpu_thermal { - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_alert1: trip1 { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit0: trip3 { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - - fan_toggle0: trip4 { - temperature = <65000>; - hysteresis = <10000>; - type = "active"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A53_0 0 1>; /* Exclude highest OPP */ - }; - - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&A53_0 0 2>; /* Exclude two highest OPPs */ - }; - - map4 { - trip = <&fan_toggle0>; - cooling-device = <&fan 0 1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - compatible = "rohm,bd71837"; - reg = <0x4b>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - #clock-cells = <0>; - clocks = <&pmic_osc>; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <900000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-always-on; - rohm,dvs-run-voltage = <900000>; - }; - - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - regulator-always-on; - }; - - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo7: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - }; - }; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb_dwc3_0 { - dr_mode = "otg"; - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_gpio_fan: gpiofangrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 - MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-pico-pi.dts b/arch/arm/dts/imx8mq-pico-pi.dts deleted file mode 100644 index 89cbec5c41b..00000000000 --- a/arch/arm/dts/imx8mq-pico-pi.dts +++ /dev/null @@ -1,418 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 Wandboard, Org. - * Copyright 2017 NXP - * - * Author: Richard Hu <[email protected]> - */ - -/dts-v1/; - -#include "imx8mq.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "TechNexion PICO-PI-8M"; - compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq"; - - chosen { - stdout-path = &uart1; - }; - - pmic_osc: clock-pmic { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "pmic_osc"; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_otg_vbus>; - compatible = "regulator-fixed"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 14 GPIO_ACTIVE_LOW>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pmic@4b { - reg = <0x4b>; - compatible = "rohm,bd71837"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - clocks = <&pmic_osc>; - clock-names = "osc"; - clock-output-names = "pmic_clk"; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - regulators { - buck1: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; - rohm,dvs-suspend-voltage = <800000>; - }; - - buck2: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; - }; - - buck3: BUCK3 { - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - - buck4: BUCK4 { - regulator-name = "buck4"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; - regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; - }; - - buck5: BUCK5 { - regulator-name = "buck5"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - }; - - buck6: BUCK6 { - regulator-name = "buck6"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - buck7: BUCK7 { - regulator-name = "buck7"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; - regulator-boot-on; - }; - - buck8: BUCK8 { - regulator-name = "buck8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - - ldo1: LDO1 { - regulator-name = "ldo1"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "ldo2"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo4: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo5: LDO5 { - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo6: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - ldo7: LDO7 { - regulator-name = "ldo7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&uart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; - assigned-clock-rates = <400000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - bus-width = <4>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usb3_phy0 { - status = "okay"; -}; - -&usb3_phy1 { - status = "okay"; -}; - -&usb_dwc3_1 { - dr_mode = "host"; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_enet_3v3: enet3v3grp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 - >; - }; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 - MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f - MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f - MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f - >; - }; - - pinctrl_otg_vbus: otgvbusgrp { - fsl,pins = < - MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */ - >; - }; - - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 - MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 - MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 - MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 - MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 - MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 - MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 - MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 - MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 - MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 - MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 - MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 - MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 - MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 - MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 - MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 - MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 - MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 - MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 - MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 - MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 0687fcdbd68..b4deaa92160 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -41,6 +41,33 @@ filename = "flash.bin"; section { pad-byte = <0x00>; + /* + * signed_hdmi_imx8m.bin contains a 1KB zero-filled padding at + * its beginning. This padding has no functional purpose, but + * the firmware is provided and signed by NXP, so the head + * must be preserved and should not be removed. + * + * When the signed HDMI firmware is placed at the beginning of + * flash.bin, the IVT header of u-boot-spl must still reside at + * a 4KB-aligned address. Since flash.bin starts with the HDMI + * firmware (including its 1KB padding), there is already a 1KB + * empty region at the head of flash.bin. + * + * The required 4KB alignment is therefore calculated relative + * to the location after this 1KB padding. To achieve this, we + * explicitly set align and align-size to 0x1000, and add an + * additional 0x400 (1KB) fill to account for the padding. + */ + signed-hdmi-imx8m { + filename = "signed_hdmi_imx8m.bin"; + type = "blob-ext"; + align = <0x1000>; + align-size = <0x1000>; + }; + + fill { + size = <0x400>; + }; #ifdef CONFIG_IMX_HAB nxp-imx8mcst@0 { @@ -51,145 +78,142 @@ #endif binman_imx_spl: nxp-imx8mimage { - filename = "u-boot-spl-mkimage.bin"; - nxp,boot-from = "sd"; - nxp,rom-version = <1>; - nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; - args; /* Needed by mkimage etype superclass */ - - section { - align = <4>; - align-size = <4>; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; + filename = "u-boot-spl-mkimage.bin"; + nxp,boot-from = "sd"; + nxp,rom-version = <1>; + nxp,loader-address = <CONFIG_SPL_TEXT_BASE>; + args; /* Needed by mkimage etype superclass */ - u-boot-spl { - align-end = <4>; - filename = "u-boot-spl.bin"; - }; + section { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; - ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; - ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-imem-fw { + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-1d-dmem-fw { + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; + align-end = <4>; + type = "blob-ext"; + }; - ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; - align-end = <4>; - type = "blob-ext"; - }; + ddr-2d-imem-fw { + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; + align-end = <4>; + type = "blob-ext"; + }; - signed-hdmi-imx8m { - filename = "signed_hdmi_imx8m.bin"; - type = "blob-ext"; - }; + ddr-2d-dmem-fw { + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; + align-end = <4>; + type = "blob-ext"; }; }; + }; #ifdef CONFIG_IMX_HAB }; +#endif + }; - nxp-imx8mcst@1 { - filename = "u-boot-fit.signed.bin"; - nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>; - offset = <0x58000>; - args; /* Needed by mkimage etype superclass */ +#ifdef CONFIG_IMX_HAB + nxp-imx8mcst@1 { + filename = "u-boot-fit.signed.bin"; + nxp,loader-address = <CONFIG_SPL_LOAD_FIT_ADDRESS>; + offset = <0x58400>; + args; /* Needed by mkimage etype superclass */ #endif - binman_imx_fit: fit { - description = "Configuration to load ATF before U-Boot"; - filename = "u-boot.itb"; + binman_imx_fit: fit { + description = "Configuration to load ATF before U-Boot"; + filename = "u-boot.itb"; #ifndef CONFIG_IMX_HAB - fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; #endif - #address-cells = <1>; + #address-cells = <1>; - offset = <0x57c00>; + offset = <0x58000>; - images { - uboot { - arch = "arm64"; - compression = "none"; - description = "U-Boot (64-bit)"; - load = <CONFIG_TEXT_BASE>; - type = "standalone"; + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = <CONFIG_TEXT_BASE>; + type = "standalone"; - uboot-blob { - filename = "u-boot-nodtb.bin"; - type = "blob-ext"; - }; + uboot-blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; }; + }; #ifndef CONFIG_ARMV8_PSCI - atf { - arch = "arm64"; - compression = "none"; - description = "ARM Trusted Firmware"; - entry = <0x910000>; - load = <0x910000>; - type = "firmware"; + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x910000>; + load = <0x910000>; + type = "firmware"; - atf-blob { - filename = "bl31.bin"; - type = "blob-ext"; - }; + atf-blob { + filename = "bl31.bin"; + type = "blob-ext"; }; + }; #endif - tee: tee { - description = "OP-TEE"; - type = "tee"; - arch = "arm64"; - compression = "none"; - os = "tee"; - load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>; - entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>; + tee: tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>; + entry = <CONFIG_IMX8M_OPTEE_LOAD_ADDR>; - tee-os { - filename = "tee.bin"; - optional; - }; + tee-os { + filename = "tee.bin"; + optional; }; + }; - fdt { - compression = "none"; - description = "NAME"; - type = "flat_dt"; + fdt { + compression = "none"; + description = "NAME"; + type = "flat_dt"; - uboot-fdt-blob { - filename = "u-boot.dtb"; - type = "blob-ext"; - }; + uboot-fdt-blob { + filename = "u-boot.dtb"; + type = "blob-ext"; }; }; + }; - configurations { - default = "conf"; + configurations { + default = "conf"; - conf { - description = "NAME"; - fdt = "fdt"; - firmware = "uboot"; + conf { + description = "NAME"; + fdt = "fdt"; + firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI - loadables = "atf", "tee"; + loadables = "atf", "tee"; #endif - }; }; }; -#ifdef CONFIG_IMX_HAB }; -#endif +#ifdef CONFIG_IMX_HAB }; +#endif }; diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi deleted file mode 100644 index 19eaa523564..00000000000 --- a/arch/arm/dts/imx8mq.dtsi +++ /dev/null @@ -1,1615 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2017 NXP - * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <[email protected]> - */ - -#include <dt-bindings/clock/imx8mq-clock.h> -#include <dt-bindings/power/imx8mq-power.h> -#include <dt-bindings/reset/imx8mq-reset.h> -#include <dt-bindings/gpio/gpio.h> -#include "dt-bindings/input/input.h" -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/thermal/thermal.h> -#include <dt-bindings/interconnect/imx8mq.h> -#include "imx8mq-pinfunc.h" - -/ { - interrupt-parent = <&gpc>; - - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &fec1; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - }; - - ckil: clock-ckil { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc_25m: clock-osc-25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "osc_25m"; - }; - - osc_27m: clock-osc-27m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "osc_27m"; - }; - - hdmi_phy_27m: clock-hdmi-phy-27m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - clock-output-names = "hdmi_phy_27m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - clk_ext2: clock-ext2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext2"; - }; - - clk_ext3: clock-ext3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext3"; - }; - - clk_ext4: clock-ext4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext4"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A53_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - nvmem-cells = <&cpu_speed_grade>; - nvmem-cell-names = "speed_grade"; - }; - - A53_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x1>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x2>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x3>; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clk IMX8MQ_CLK_ARM>; - enable-method = "psci"; - i-cache-size = <0x8000>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <0x8000>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&A53_L2>; - operating-points-v2 = <&a53_opp_table>; - #cooling-cells = <2>; - }; - - A53_L2: l2-cache0 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x100000>; - cache-line-size = <64>; - cache-sets = <1024>; - }; - }; - - a53_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <900000>; - /* Industrial only */ - opp-supported-hw = <0xf>, <0x4>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <900000>; - /* Consumer only */ - opp-supported-hw = <0xe>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0xc>, <0x4>; - clock-latency-ns = <150000>; - opp-suspend; - }; - - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1000000>; - opp-supported-hw = <0x8>, <0x3>; - clock-latency-ns = <150000>; - opp-suspend; - }; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 1>; - - trips { - gpu_alert: gpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - gpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - vpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 2>; - - trips { - vpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ - interrupt-parent = <&gic>; - arm,no-tick-in-suspend; - }; - - soc: soc@0 { - compatible = "fsl,imx8mq-soc", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x3e000000>; - dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; - nvmem-cells = <&imx8mq_uid>; - nvmem-cell-names = "soc_unique_id"; - - aips1: bus@30000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30000000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30000000 0x30000000 0x400000>; - - sai1: sai@30010000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30010000 0x10000>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, - <&clk IMX8MQ_CLK_SAI1_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai6: sai@30030000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30030000 0x10000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, - <&clk IMX8MQ_CLK_SAI6_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai5: sai@30040000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30040000 0x10000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, - <&clk IMX8MQ_CLK_SAI5_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai4: sai@30050000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x30050000 0x10000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, - <&clk IMX8MQ_CLK_SAI4_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - gpio1: gpio@30200000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 10 30>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 40 21>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 61 26>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 87 32>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 119 30>; - }; - - tmu: tmu@30260000 { - compatible = "fsl,imx8mq-tmu"; - reg = <0x30260000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; - little-endian; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000023>, - <0x00000001 0x00000029>, - <0x00000002 0x0000002f>, - <0x00000003 0x00000035>, - <0x00000004 0x0000003d>, - <0x00000005 0x00000043>, - <0x00000006 0x0000004b>, - <0x00000007 0x00000051>, - <0x00000008 0x00000057>, - <0x00000009 0x0000005f>, - <0x0000000a 0x00000067>, - <0x0000000b 0x0000006f>, - - <0x00010000 0x0000001b>, - <0x00010001 0x00000023>, - <0x00010002 0x0000002b>, - <0x00010003 0x00000033>, - <0x00010004 0x0000003b>, - <0x00010005 0x00000043>, - <0x00010006 0x0000004b>, - <0x00010007 0x00000055>, - <0x00010008 0x0000005d>, - <0x00010009 0x00000067>, - <0x0001000a 0x00000070>, - - <0x00020000 0x00000017>, - <0x00020001 0x00000023>, - <0x00020002 0x0000002d>, - <0x00020003 0x00000037>, - <0x00020004 0x00000041>, - <0x00020005 0x0000004b>, - <0x00020006 0x00000057>, - <0x00020007 0x00000063>, - <0x00020008 0x0000006f>, - - <0x00030000 0x00000015>, - <0x00030001 0x00000021>, - <0x00030002 0x0000002d>, - <0x00030003 0x00000039>, - <0x00030004 0x00000045>, - <0x00030005 0x00000053>, - <0x00030006 0x0000005f>, - <0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; - }; - - wdog1: watchdog@30280000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; - status = "disabled"; - }; - - wdog2: watchdog@30290000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; - status = "disabled"; - }; - - wdog3: watchdog@302a0000 { - compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; - status = "disabled"; - }; - - sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x302c0000 0x10000>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, - <&clk IMX8MQ_CLK_SDMA2_ROOT>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - lcdif: lcd-controller@30320000 { - compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; - reg = <0x30320000 0x10000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "pix"; - assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, - <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, - <&clk IMX8MQ_CLK_LCDIF_PIXEL>, - <&clk IMX8MQ_VIDEO_PLL1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, - <&clk IMX8MQ_VIDEO_PLL1>, - <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <0>, <0>, <0>, <594000000>; - status = "disabled"; - - port { - lcdif_mipi_dsi: endpoint { - remote-endpoint = <&mipi_dsi_lcdif_in>; - }; - }; - }; - - iomuxc: pinctrl@30330000 { - compatible = "fsl,imx8mq-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - iomuxc_gpr: syscon@30340000 { - compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", - "syscon", "simple-mfd"; - reg = <0x30340000 0x10000>; - - mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ - }; - }; - - ocotp: efuse@30350000 { - compatible = "fsl,imx8mq-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; - #address-cells = <1>; - #size-cells = <1>; - - imx8mq_uid: soc-uid@410 { - reg = <0x4 0x8>; - }; - - cpu_speed_grade: speed-grade@10 { - reg = <0x10 4>; - }; - - fec_mac_address: mac-address@90 { - reg = <0x90 6>; - }; - }; - - anatop: syscon@30360000 { - compatible = "fsl,imx8mq-anatop", "syscon"; - reg = <0x30360000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp{ - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; - offset = <0x34>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; - clock-names = "snvs-rtc"; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; - clock-names = "snvs-pwrkey"; - linux,keycode = <KEY_POWER>; - wakeup-source; - status = "disabled"; - }; - }; - - clk: clock-controller@30380000 { - compatible = "fsl,imx8mq-ccm"; - reg = <0x30380000 0x10000>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - clocks = <&ckil>, <&osc_25m>, <&osc_27m>, - <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; - clock-names = "ckil", "osc_25m", "osc_27m", - "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, - <&clk IMX8MQ_CLK_A53_CORE>, - <&clk IMX8MQ_CLK_NOC>, - <&clk IMX8MQ_CLK_AUDIO_AHB>, - <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, - <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, - <&clk IMX8MQ_AUDIO_PLL1>, - <&clk IMX8MQ_AUDIO_PLL2>; - assigned-clock-rates = <0>, <0>, - <800000000>, - <0>, - <0>, - <0>, - <786432000>, - <722534400>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_ARM_PLL_OUT>, - <0>, - <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_AUDIO_PLL1>, - <&clk IMX8MQ_AUDIO_PLL2>; - }; - - src: reset-controller@30390000 { - compatible = "fsl,imx8mq-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - - gpc: gpc@303a0000 { - compatible = "fsl,imx8mq-gpc"; - reg = <0x303a0000 0x10000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - interrupt-controller; - #interrupt-cells = <3>; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - pgc_mipi: power-domain@0 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_MIPI>; - }; - - /* - * As per comment in ATF source code: - * - * PCIE1 and PCIE2 share the - * same reset signal, if we - * power down PCIE2, PCIE1 - * will be held in reset too. - * - * So instead of creating two - * separate power domains for - * PCIE1 and PCIE2 we create a - * link between both and use - * it as a shared PCIE power - * domain. - */ - pgc_pcie: power-domain@1 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_PCIE1>; - power-domains = <&pgc_pcie2>; - }; - - pgc_otg1: power-domain@2 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; - }; - - pgc_otg2: power-domain@3 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; - }; - - pgc_ddr1: power-domain@4 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_DDR1>; - }; - - pgc_gpu: power-domain@5 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_GPU>; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; - }; - - pgc_vpu: power-domain@6 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_VPU>; - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, - <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>; - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, - <&clk IMX8MQ_CLK_VPU_G2>, - <&clk IMX8MQ_CLK_VPU_BUS>, - <&clk IMX8MQ_VPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VPU_PLL>; - assigned-clock-rates = <600000000>, - <600000000>, - <800000000>, - <0>; - }; - - pgc_disp: power-domain@7 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_DISP>; - }; - - pgc_mipi_csi1: power-domain@8 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; - }; - - pgc_mipi_csi2: power-domain@9 { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; - }; - - pgc_pcie2: power-domain@a { - #power-domain-cells = <0>; - reg = <IMX8M_POWER_DOMAIN_PCIE2>; - }; - }; - }; - }; - - aips2: bus@30400000 { /* AIPS2 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30400000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30400000 0x30400000 0x400000>; - - pwm1: pwm@30660000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, - <&clk IMX8MQ_CLK_PWM1_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, - <&clk IMX8MQ_CLK_PWM2_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, - <&clk IMX8MQ_CLK_PWM3_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, - <&clk IMX8MQ_CLK_PWM4_ROOT>; - clock-names = "ipg", "per"; - #pwm-cells = <3>; - status = "disabled"; - }; - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc_25m>; - clock-names = "per"; - }; - }; - - aips3: bus@30800000 { /* AIPS3 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x30800000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x30800000 0x30800000 0x400000>, - <0x08000000 0x08000000 0x10000000>; - - spdif1: spdif@30810000 { - compatible = "fsl,imx35-spdif"; - reg = <0x30810000 0x10000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ - <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ - <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ - <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ - <&clk IMX8MQ_CLK_DUMMY>; /* spba */ - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi1: spi@30820000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, - <&clk IMX8MQ_CLK_ECSPI1_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi2: spi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, - <&clk IMX8MQ_CLK_ECSPI2_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - ecspi3: spi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, - <&clk IMX8MQ_CLK_ECSPI3_ROOT>; - clock-names = "ipg", "per"; - dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@30860000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, - <&clk IMX8MQ_CLK_UART1_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, - <&clk IMX8MQ_CLK_UART3_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, - <&clk IMX8MQ_CLK_UART2_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - spdif2: spdif@308a0000 { - compatible = "fsl,imx35-spdif"; - reg = <0x308a0000 0x10000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ - <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ - <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ - <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ - <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ - <&clk IMX8MQ_CLK_DUMMY>; /* spba */ - clock-names = "core", "rxtx0", - "rxtx1", "rxtx2", - "rxtx3", "rxtx4", - "rxtx5", "rxtx6", - "rxtx7", "spba"; - dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x308b0000 0x10000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, - <&clk IMX8MQ_CLK_SAI2_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx8mq-sai"; - reg = <0x308c0000 0x10000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, - <&clk IMX8MQ_CLK_SAI3_ROOT>, - <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - crypto: crypto@30900000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_AHB>, - <&clk IMX8MQ_CLK_IPG_ROOT>; - clock-names = "aclk", "ipg"; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - mipi_dsi: mipi-dsi@30a00000 { - compatible = "fsl,imx8mq-nwl-dsi"; - reg = <0x30a00000 0x300>; - clocks = <&clk IMX8MQ_CLK_DSI_CORE>, - <&clk IMX8MQ_CLK_DSI_AHB>, - <&clk IMX8MQ_CLK_DSI_IPG_DIV>, - <&clk IMX8MQ_CLK_DSI_PHY_REF>, - <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, - <&clk IMX8MQ_CLK_DSI_CORE>, - <&clk IMX8MQ_CLK_DSI_IPG_DIV>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, - <&clk IMX8MQ_SYS1_PLL_266M>; - assigned-clock-rates = <80000000>, <266000000>, <20000000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - mux-controls = <&mux 0>; - power-domains = <&pgc_mipi>; - phys = <&dphy>; - phy-names = "dphy"; - resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, - <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, - <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, - <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; - reset-names = "byte", "dpi", "esc", "pclk"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - mipi_dsi_lcdif_in: endpoint@0 { - reg = <0>; - remote-endpoint = <&lcdif_mipi_dsi>; - }; - }; - }; - }; - - dphy: dphy@30a00300 { - compatible = "fsl,imx8mq-mipi-dphy"; - reg = <0x30a00300 0x100>; - clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; - clock-names = "phy_ref"; - assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, - <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, - <&clk IMX8MQ_CLK_DSI_PHY_REF>, - <&clk IMX8MQ_VIDEO_PLL1>; - assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, - <&clk IMX8MQ_VIDEO_PLL1>, - <&clk IMX8MQ_VIDEO_PLL1_OUT>; - assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; - #phy-cells = <0>; - power-domains = <&pgc_mipi>; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx8mq-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, - <&clk IMX8MQ_CLK_UART4_ROOT>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - mipi_csi1: csi@30a70000 { - compatible = "fsl,imx8mq-mipi-csi2"; - reg = <0x30a70000 0x1000>; - clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, - <&clk IMX8MQ_CLK_CSI1_ESC>, - <&clk IMX8MQ_CLK_CSI1_PHY_REF>; - clock-names = "core", "esc", "ui"; - assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, - <&clk IMX8MQ_CLK_CSI1_PHY_REF>, - <&clk IMX8MQ_CLK_CSI1_ESC>; - assigned-clock-rates = <266000000>, <333000000>, <66000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, - <&clk IMX8MQ_SYS2_PLL_1000M>, - <&clk IMX8MQ_SYS1_PLL_800M>; - power-domains = <&pgc_mipi_csi1>; - resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; - fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; - interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; - interconnect-names = "dram"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - csi1_mipi_ep: endpoint { - remote-endpoint = <&csi1_ep>; - }; - }; - }; - }; - - csi1: csi@30a90000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; - reg = <0x30a90000 0x10000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; - clock-names = "mclk"; - status = "disabled"; - - port { - csi1_ep: endpoint { - remote-endpoint = <&csi1_mipi_ep>; - }; - }; - }; - - mipi_csi2: csi@30b60000 { - compatible = "fsl,imx8mq-mipi-csi2"; - reg = <0x30b60000 0x1000>; - clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, - <&clk IMX8MQ_CLK_CSI2_ESC>, - <&clk IMX8MQ_CLK_CSI2_PHY_REF>; - clock-names = "core", "esc", "ui"; - assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, - <&clk IMX8MQ_CLK_CSI2_PHY_REF>, - <&clk IMX8MQ_CLK_CSI2_ESC>; - assigned-clock-rates = <266000000>, <333000000>, <66000000>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, - <&clk IMX8MQ_SYS2_PLL_1000M>, - <&clk IMX8MQ_SYS1_PLL_800M>; - power-domains = <&pgc_mipi_csi2>; - resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, - <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; - fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; - interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; - interconnect-names = "dram"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - csi2_mipi_ep: endpoint { - remote-endpoint = <&csi2_ep>; - }; - }; - }; - }; - - csi2: csi@30b80000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; - reg = <0x30b80000 0x10000>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; - clock-names = "mclk"; - status = "disabled"; - - port { - csi2_ep: endpoint { - remote-endpoint = <&csi2_mipi_ep>; - }; - }; - }; - - mu: mailbox@30aa0000 { - compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; - reg = <0x30aa0000 0x10000>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_MU_ROOT>; - #mbox-cells = <2>; - }; - - usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, - <&clk IMX8MQ_CLK_USDHC1_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mq-usdhc", - "fsl,imx7d-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, - <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, - <&clk IMX8MQ_CLK_USDHC2_ROOT>; - clock-names = "ipg", "ahb", "per"; - fsl,tuning-start-tap = <20>; - fsl,tuning-step = <2>; - bus-width = <4>; - status = "disabled"; - }; - - qspi0: spi@30bb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; - reg = <0x30bb0000 0x10000>, - <0x08000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, - <&clk IMX8MQ_CLK_QSPI_ROOT>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; - reg = <0x30bd0000 0x10000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, - <&clk IMX8MQ_CLK_AHB>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; - }; - - fec1: ethernet@30be0000 { - compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET1_ROOT>, - <&clk IMX8MQ_CLK_ENET_TIMER>, - <&clk IMX8MQ_CLK_ENET_REF>, - <&clk IMX8MQ_CLK_ENET_PHY_REF>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, - <&clk IMX8MQ_CLK_ENET_TIMER>, - <&clk IMX8MQ_CLK_ENET_REF>, - <&clk IMX8MQ_CLK_ENET_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, - <&clk IMX8MQ_SYS2_PLL_100M>, - <&clk IMX8MQ_SYS2_PLL_125M>, - <&clk IMX8MQ_SYS2_PLL_50M>; - assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - nvmem-cells = <&fec_mac_address>; - nvmem-cell-names = "mac-address"; - fsl,stop-mode = <&iomuxc_gpr 0x10 3>; - status = "disabled"; - }; - }; - - noc: interconnect@32700000 { - compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; - reg = <0x32700000 0x100000>; - clocks = <&clk IMX8MQ_CLK_NOC>; - fsl,ddrc = <&ddrc>; - #interconnect-cells = <1>; - operating-points-v2 = <&noc_opp_table>; - - noc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-133M { - opp-hz = /bits/ 64 <133333333>; - }; - - opp-400M { - opp-hz = /bits/ 64 <400000000>; - }; - - opp-800M { - opp-hz = /bits/ 64 <800000000>; - }; - }; - }; - - aips4: bus@32c00000 { /* AIPS4 */ - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x32c00000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x32c00000 0x32c00000 0x400000>; - - irqsteer: interrupt-controller@32e2d000 { - compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; - reg = <0x32e2d000 0x1000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; - clock-names = "ipg"; - fsl,channel = <0>; - fsl,num-irqs = <64>; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - gpu: gpu@38000000 { - compatible = "vivante,gc"; - reg = <0x38000000 0x40000>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, - <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; - clock-names = "core", "shader", "bus", "reg"; - #cooling-cells = <2>; - assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, - <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, - <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>, - <&clk IMX8MQ_GPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL>; - assigned-clock-rates = <800000000>, <800000000>, - <800000000>, <800000000>, <0>; - power-domains = <&pgc_gpu>; - }; - - usb_dwc3_0: usb@38100000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38100000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb3_phy0>, <&usb3_phy0>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg1>; - usb3-resume-missing-cas; - status = "disabled"; - }; - - usb3_phy0: usb-phy@381f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x381f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; - }; - - usb_dwc3_1: usb@38200000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; - reg = <0x38200000 0x10000>; - clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, - <&clk IMX8MQ_CLK_USB_CORE_REF>, - <&clk IMX8MQ_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, - <&clk IMX8MQ_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <500000000>, <100000000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb3_phy1>, <&usb3_phy1>; - phy-names = "usb2-phy", "usb3-phy"; - power-domains = <&pgc_otg2>; - usb3-resume-missing-cas; - status = "disabled"; - }; - - usb3_phy1: usb-phy@382f0040 { - compatible = "fsl,imx8mq-usb-phy"; - reg = <0x382f0040 0x40>; - clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; - clock-names = "phy"; - assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; - assigned-clock-rates = <100000000>; - #phy-cells = <0>; - status = "disabled"; - }; - - vpu_g1: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu-g1"; - reg = <0x38300000 0x10000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; - }; - - vpu_g2: video-codec@38310000 { - compatible = "nxp,imx8mq-vpu-g2"; - reg = <0x38310000 0x10000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; - power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; - }; - - vpu_blk_ctrl: blk-ctrl@38320000 { - compatible = "fsl,imx8mq-vpu-blk-ctrl"; - reg = <0x38320000 0x100>; - power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; - power-domain-names = "bus", "g1", "g2"; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>; - clock-names = "g1", "g2"; - #power-domain-cells = <1>; - }; - - pcie0: pcie@33800000 { - compatible = "fsl,imx8mq-pcie"; - reg = <0x33800000 0x400000>, - <0x1ff00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ - <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <2>; - linux,pci-domain = <0>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, - <&clk IMX8MQ_CLK_PCIE1_PHY>, - <&clk IMX8MQ_CLK_PCIE1_AUX>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, - <&clk IMX8MQ_SYS2_PLL_100M>, - <&clk IMX8MQ_SYS1_PLL_80M>; - assigned-clock-rates = <250000000>, <100000000>, - <10000000>; - status = "disabled"; - }; - - pcie1: pcie@33c00000 { - compatible = "fsl,imx8mq-pcie"; - reg = <0x33c00000 0x400000>, - <0x27f00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ - <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - fsl,max-link-speed = <2>; - linux,pci-domain = <1>; - power-domains = <&pgc_pcie>; - resets = <&src IMX8MQ_RESET_PCIEPHY2>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, - <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, - <&clk IMX8MQ_CLK_PCIE2_PHY>, - <&clk IMX8MQ_CLK_PCIE2_AUX>; - assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, - <&clk IMX8MQ_SYS2_PLL_100M>, - <&clk IMX8MQ_SYS1_PLL_80M>; - assigned-clock-rates = <250000000>, <100000000>, - <10000000>; - status = "disabled"; - }; - - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>, /* GICR */ - <0x31000000 0x2000>, /* GICC */ - <0x31010000 0x2000>, /* GICV */ - <0x31020000 0x2000>; /* GICH */ - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - }; - - ddrc: memory-controller@3d400000 { - compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; - reg = <0x3d400000 0x400000>; - clock-names = "core", "pll", "alt", "apb"; - clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, - <&clk IMX8MQ_DRAM_PLL_OUT>, - <&clk IMX8MQ_CLK_DRAM_ALT>, - <&clk IMX8MQ_CLK_DRAM_APB>; - status = "disabled"; - }; - - ddr-pmu@3d800000 { - compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; - reg = <0x3d800000 0x400000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - }; - }; -}; diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index 860994129ae..ac130b54738 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -26,10 +26,6 @@ status = "disabled"; }; -&wdog3 { - status = "disabled"; -}; - &per_bridge4 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8ulp-u-boot.dtsi b/arch/arm/dts/imx8ulp-u-boot.dtsi index 30baaeff8ef..54ecbcf1795 100644 --- a/arch/arm/dts/imx8ulp-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-u-boot.dtsi @@ -61,3 +61,7 @@ }; }; #endif + +&wdog3 { + bootph-all; +}; diff --git a/arch/arm/dts/imx91-11x11-evk.dts b/arch/arm/dts/imx91-11x11-evk.dts deleted file mode 100644 index ca9070a4c76..00000000000 --- a/arch/arm/dts/imx91-11x11-evk.dts +++ /dev/null @@ -1,875 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2024 NXP - */ - -/dts-v1/; - -#include <dt-bindings/usb/pd.h> -#include "imx91.dtsi" - -/ { - compatible = "fsl,imx91-11x11-evk", "fsl,imx91"; - model = "NXP i.MX91 11X11 EVK board"; - - aliases { - ethernet0 = &fec; - ethernet1 = &eqos; - rtc0 = &bbnsm_rtc; - }; - - chosen { - stdout-path = &lpuart1; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "vref_1v8"; - }; - - reg_audio_pwr: regulator-audio-pwr { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "audio-pwr"; - gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - off-on-delay-us = <12000>; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - pinctrl-names = "default"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc3_vmmc: regulator-usdhc3 { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "WLAN_EN"; - gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * IW612 wifi chip needs more delay than other wifi chips to complete - * the host interface initialization after power up, otherwise the - * internal state of IW612 may be unstable, resulting in the failure of - * the SDIO3.0 switch voltage. - */ - startup-delay-us = <20000>; - }; - - reg_vdd_12v: regulator-vdd-12v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <12000000>; - regulator-min-microvolt = <12000000>; - regulator-name = "reg_vdd_12v"; - gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vrpi_3v3: regulator-vrpi-3v3 { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VRPI_3V3"; - vin-supply = <&buck4>; - gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vrpi_5v: regulator-vrpi-5v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "VRPI_5V"; - gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x80000000 0 0x40000000>; - reusable; - size = <0 0x10000000>; - linux,cma-default; - }; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&eqos { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; - pinctrl-0 = <&pinctrl_eqos>; - pinctrl-1 = <&pinctrl_eqos_sleep>; - pinctrl-names = "default", "sleep"; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - eee-broken-1000t; - }; - }; -}; - -&fec { - phy-handle = <ðphy2>; - phy-mode = "rgmii-id"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - pinctrl-names = "default", "sleep"; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy2: ethernet-phy@2 { - reg = <2>; - eee-broken-1000t; - }; - }; -}; - -/* - * When add, delete or change any target device setting in &lpi2c1, - * please synchronize the changes to the &i3c1 bus in imx91-11x11-evk-i3c.dts. - */ -&lpi2c1 { - clock-frequency = <400000>; - pinctrl-0 = <&pinctrl_lpi2c1>; - pinctrl-names = "default"; - status = "okay"; - - codec: wm8962@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX93_CLK_SAI3_GATE>; - AVDD-supply = <®_audio_pwr>; - CPVDD-supply = <®_audio_pwr>; - DBVDD-supply = <®_audio_pwr>; - DCVDD-supply = <®_audio_pwr>; - MICVDD-supply = <®_audio_pwr>; - PLLVDD-supply = <®_audio_pwr>; - SPKVDD1-supply = <®_audio_pwr>; - SPKVDD2-supply = <®_audio_pwr>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; - - lsm6dsm@6a { - compatible = "st,lsm6dso"; - reg = <0x6a>; - }; -}; - -&lpi2c2 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - pinctrl-0 = <&pinctrl_lpi2c2>; - pinctrl-names = "default"; - status = "okay"; - - pcal6524: gpio@22 { - compatible = "nxp,pcal6524"; - reg = <0x22>; - #interrupt-cells = <2>; - interrupt-controller; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - interrupt-parent = <&gpio3>; - pinctrl-0 = <&pinctrl_pcal6524>; - pinctrl-names = "default"; - }; - - pmic@25 { - compatible = "nxp,pca9451a"; - reg = <0x25>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&pcal6524>; - - regulators { - - buck1: BUCK1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2237500>; - regulator-min-microvolt = <650000>; - regulator-name = "BUCK1"; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2187500>; - regulator-min-microvolt = <600000>; - regulator-name = "BUCK2"; - regulator-ramp-delay = <3125>; - }; - - buck4: BUCK4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3400000>; - regulator-min-microvolt = <600000>; - regulator-name = "BUCK4"; - }; - - buck5: BUCK5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3400000>; - regulator-min-microvolt = <600000>; - regulator-name = "BUCK5"; - }; - - buck6: BUCK6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3400000>; - regulator-min-microvolt = <600000>; - regulator-name = "BUCK6"; - }; - - ldo1: LDO1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1600000>; - regulator-name = "LDO1"; - }; - - ldo4: LDO4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <800000>; - regulator-name = "LDO4"; - }; - - ldo5: LDO5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "LDO5"; - }; - }; - }; - - adp5585: io-expander@34 { - compatible = "adi,adp5585-00", "adi,adp5585"; - reg = <0x34>; - #gpio-cells = <2>; - gpio-controller; - #pwm-cells = <3>; - gpio-reserved-ranges = <5 1>; - - exp-sel-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-low; - }; - }; -}; - -&lpi2c3 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - pinctrl-0 = <&pinctrl_lpi2c3>; - pinctrl-names = "default"; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x50>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio3>; - status = "okay"; - - typec1_con: connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <15000000>; - power-role = "dual"; - self-powered; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 20000, 3000)>; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - try-power-role = "sink"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - }; - }; - }; - - ptn5110_2: tcpc@51 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x51>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio3>; - status = "okay"; - - typec2_con: connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <15000000>; - power-role = "dual"; - self-powered; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 20000, 3000)>; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - try-power-role = "sink"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - typec2_dr_sw: endpoint { - remote-endpoint = <&usb2_drd_sw>; - }; - }; - }; - }; - }; - - pcf2131: rtc@53 { - compatible = "nxp,pcf2131"; - reg = <0x53>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&pcal6524>; - status = "okay"; - }; -}; - -&lpuart1 { - pinctrl-0 = <&pinctrl_uart1>; - pinctrl-names = "default"; - status = "okay"; -}; - -&lpuart5 { - pinctrl-0 = <&pinctrl_uart5>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg1 { - adp-disable; - disable-over-current; - dr_mode = "otg"; - hnp-disable; - srp-disable; - usb-role-switch; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usbotg2 { - adp-disable; - disable-over-current; - dr_mode = "otg"; - hnp-disable; - srp-disable; - usb-role-switch; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - status = "okay"; - - port { - usb2_drd_sw: endpoint { - remote-endpoint = <&typec2_dr_sw>; - }; - }; -}; - -&usdhc1 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - status = "okay"; -}; - -&usdhc2 { - bus-width = <4>; - cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; - no-mmc; - no-sdio; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog3 { - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e - MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e - MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e - MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e - MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e - MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e - MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe - MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e - MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e - MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e - MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e - MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e - MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe - MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_eqos_sleep: eqossleepgrp { - fsl,pins = < - MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e - MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e - MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e - MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e - MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e - MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e - MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e - MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e - MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e - MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e - MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e - MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e - MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e - MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e - MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e - MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e - MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e - MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e - MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e - MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe - MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e - MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e - MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e - MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e - MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e - MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe - MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_fec_sleep: fecsleepgrp { - fsl,pins = < - MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e - MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e - MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e - MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e - MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e - MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e - MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e - MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e - MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e - MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e - MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e - MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e - MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e - MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX91_PAD_GPIO_IO25__CAN2_TX 0x139e - MX91_PAD_GPIO_IO27__CAN2_RX 0x139e - >; - }; - - pinctrl_flexcan2_sleep: flexcan2sleepgrp { - fsl,pins = < - MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e - MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e - >; - }; - - pinctrl_lcdif_gpio: lcdifgpiogrp { - fsl,pins = < - MX91_PAD_GPIO_IO00__GPIO2_IO0 0x51e - MX91_PAD_GPIO_IO01__GPIO2_IO1 0x51e - MX91_PAD_GPIO_IO02__GPIO2_IO2 0x51e - MX91_PAD_GPIO_IO03__GPIO2_IO3 0x51e - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e - MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e - MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e - MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e - MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e - MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e - MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e - MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e - MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e - MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e - MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e - MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e - MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e - MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e - MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e - MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e - MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e - MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e - MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e - MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e - MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e - MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e - MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e - MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = < - MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e - MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c3: lpi2c3grp { - fsl,pins = < - MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e - MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e - >; - }; - - pinctrl_pcal6524: pcal6524grp { - fsl,pins = < - MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e - >; - }; - - pinctrl_pdm: pdmgrp { - fsl,pins = < - MX91_PAD_PDM_CLK__PDM_CLK 0x31e - MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e - MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e - >; - }; - - pinctrl_pdm_sleep: pdmsleepgrp { - fsl,pins = < - MX91_PAD_PDM_CLK__GPIO1_IO8 0x31e - MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x31e - MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e - >; - }; - - pinctrl_sai1: sai1grp { - fsl,pins = < - MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e - MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e - MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e - MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e - >; - }; - - pinctrl_sai1_sleep: sai1sleepgrp { - fsl,pins = < - MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e - MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e - MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e - MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e - MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e - MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e - MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e - MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e - >; - }; - - pinctrl_sai3_sleep: sai3sleepgrp { - fsl,pins = < - MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e - MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e - MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e - MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e - MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e - MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e - >; - }; - - pinctrl_spdif_sleep: spdifsleepgrp { - fsl,pins = < - MX91_PAD_GPIO_IO22__GPIO2_IO22 0x31e - MX91_PAD_GPIO_IO23__GPIO2_IO23 0x31e - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX91_PAD_UART1_RXD__LPUART1_RX 0x31e - MX91_PAD_UART1_TXD__LPUART1_TX 0x31e - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e - MX91_PAD_DAP_TDI__LPUART5_RX 0x31e - MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e - MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e - MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e - MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e - MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e - MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e - MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e - MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e - MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e - MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e - MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e - MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe - MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe - MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe - MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe - MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe - MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe - MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe - MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe - MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 - MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 - MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 - MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 - MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 - MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 - MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 - MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 - MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 - MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 - MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e - MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e - MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e - MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e - MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe - MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { - fsl,pins = < - MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 - MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 - MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 - MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 - MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 - MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 - MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_sleep: usdhc2sleepgrp { - fsl,pins = < - MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e - MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e - MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e - MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e - MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e - MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e - MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e - MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e - MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e - MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e - MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e - MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe - MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe - MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe - MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe - MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe - MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 - MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 - MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 - MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 - MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 - MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3sleepgrp { - fsl,pins = < - MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e - MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e - MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e - MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e - MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e - MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e - >; - }; - - pinctrl_usdhc3_wlan: usdhc3wlangrp { - fsl,pins = < - MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e - >; - }; -}; diff --git a/arch/arm/dts/imx91-11x11-frdm.dts b/arch/arm/dts/imx91-11x11-frdm.dts deleted file mode 100644 index fc9d6729c58..00000000000 --- a/arch/arm/dts/imx91-11x11-frdm.dts +++ /dev/null @@ -1,773 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2025 NXP - */ - -/dts-v1/; - -#include <dt-bindings/usb/pd.h> -#include "imx91.dtsi" - -/ { - compatible = "fsl,imx91-11x11-frdm", "fsl,imx91"; - model = "NXP i.MX91 11X11 FRDM Board"; - - aliases { - ethernet0 = &fec; - ethernet1 = &eqos; - rtc0 = &pcf2131; - }; - - chosen { - stdout-path = &lpuart1; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "vref_1v8"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - off-on-delay-us = <12000>; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - pinctrl-names = "default"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - bootph-pre-ram; - bootph-some-ram; - }; - - reg_vdd_12v: regulator-vdd-12v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <12000000>; - regulator-min-microvolt = <12000000>; - regulator-name = "reg_vdd_12v"; - gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vexp_3v3: regulator-vexp-3v3 { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "VEXP_3V3"; - vin-supply = <&buck4>; - gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vexp_5v: regulator-vexp-5v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "VEXP_5V"; - gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x80000000 0 0x40000000>; - reusable; - size = <0 0x10000000>; - linux,cma-default; - }; - }; - - soc@0 { - bootph-all; - bootph-pre-ram; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&aips1 { - bootph-pre-ram; - bootph-all; -}; - -&aips2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&aips3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&clk { - bootph-all; - bootph-pre-ram; -}; - -&clk_ext1 { - bootph-all; - bootph-pre-ram; -}; - -&eqos { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; - pinctrl-0 = <&pinctrl_eqos>; - pinctrl-1 = <&pinctrl_eqos_sleep>; - pinctrl-names = "default", "sleep"; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - eee-broken-1000t; - reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; - reset-assert-us = <15000>; - reset-deassert-us = <100000>; - }; - }; -}; - -&fec { - phy-handle = <ðphy2>; - phy-mode = "rgmii-id"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - pinctrl-names = "default", "sleep"; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy2: ethernet-phy@2 { - reg = <2>; - eee-broken-1000t; - reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; - reset-assert-us = <15000>; - reset-deassert-us = <100000>; - }; - }; -}; - -&gpio1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio4 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c2 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - pinctrl-0 = <&pinctrl_lpi2c2>; - pinctrl-names = "default"; - status = "okay"; - bootph-pre-ram; - bootph-some-ram; - - pcal6524: gpio@22 { - compatible = "nxp,pcal6524"; - reg = <0x22>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - pinctrl-0 = <&pinctrl_pcal6524>; - pinctrl-names = "default"; - }; - - pmic@25 { - compatible = "nxp,pca9451a"; - reg = <0x25>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&pcal6524>; - bootph-pre-ram; - bootph-some-ram; - - regulators { - bootph-pre-ram; - bootph-some-ram; - - buck1: BUCK1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2237500>; - regulator-min-microvolt = <650000>; - regulator-name = "BUCK1"; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2187500>; - regulator-min-microvolt = <600000>; - regulator-name = "BUCK2"; - regulator-ramp-delay = <3125>; - }; - - buck4: BUCK4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3400000>; - regulator-min-microvolt = <600000>; - regulator-name = "BUCK4"; - }; - - buck5: BUCK5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3400000>; - regulator-min-microvolt = <600000>; - regulator-name = "BUCK5"; - }; - - buck6: BUCK6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3400000>; - regulator-min-microvolt = <600000>; - regulator-name = "BUCK6"; - }; - - ldo1: LDO1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1600000>; - regulator-name = "LDO1"; - }; - - ldo4: LDO4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <800000>; - regulator-name = "LDO4"; - }; - - ldo5: LDO5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "LDO5"; - }; - }; - }; - - eeprom: at24c256@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -&lpi2c3 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - pinctrl-0 = <&pinctrl_lpi2c3>; - pinctrl-names = "default"; - status = "okay"; - bootph-pre-ram; - bootph-some-ram; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x50>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio3>; - status = "okay"; - - typec1_con: connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <15000000>; - power-role = "dual"; - self-powered; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 20000, 3000)>; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - try-power-role = "sink"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - }; - }; - }; - - pcf2131: rtc@53 { - compatible = "nxp,pcf2131"; - reg = <0x53>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&pcal6524>; - status = "okay"; - }; -}; - -&lpuart1 { - pinctrl-0 = <&pinctrl_uart1>; - pinctrl-names = "default"; - status = "okay"; - bootph-pre-ram; - bootph-some-ram; -}; - -&lpuart5 { - pinctrl-0 = <&pinctrl_uart5>; - pinctrl-names = "default"; - status = "okay"; -}; - -&osc_32k { - bootph-all; - bootph-pre-ram; -}; - -&osc_24m { - bootph-all; - bootph-pre-ram; -}; - -&usbotg1 { - adp-disable; - disable-over-current; - dr_mode = "otg"; - hnp-disable; - srp-disable; - usb-role-switch; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - status = "okay"; -}; - -&usdhc1 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - status = "okay"; - bootph-pre-ram; - bootph-some-ram; -}; - -&usdhc2 { - bus-width = <4>; - cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; - no-mmc; - no-sdio; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog3 { - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - bootph-pre-ram; - bootph-some-ram; - - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e - MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e - MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e - MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e - MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e - MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e - MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe - MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e - MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e - MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e - MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e - MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e - MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe - MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_eqos_sleep: eqossleepgrp { - fsl,pins = < - MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e - MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e - MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e - MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e - MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e - MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e - MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e - MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e - MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e - MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e - MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e - MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e - MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e - MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e - MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e - MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e - MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e - MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e - MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e - MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe - MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e - MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e - MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e - MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e - MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e - MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe - MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_fec_sleep: fecsleepgrp { - fsl,pins = < - MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e - MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e - MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e - MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e - MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e - MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e - MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e - MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e - MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e - MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e - MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e - MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e - MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e - MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e - >; - }; - - pinctrl_lcdif_gpio: lcdifgpiogrp { - fsl,pins = < - MX91_PAD_GPIO_IO00__GPIO2_IO0 0x51e - MX91_PAD_GPIO_IO01__GPIO2_IO1 0x51e - MX91_PAD_GPIO_IO02__GPIO2_IO2 0x51e - MX91_PAD_GPIO_IO03__GPIO2_IO3 0x51e - >; - }; - - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e - MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e - MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e - MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e - MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e - MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e - MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e - MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e - MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e - MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e - MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e - MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e - MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e - MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e - MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e - MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e - MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e - MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e - MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e - MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e - MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e - MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e - MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e - MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e - >; - bootph-pre-ram; - bootph-some-ram; - }; - - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = < - MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e - MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e - >; - bootph-pre-ram; - bootph-some-ram; - }; - - pinctrl_lpi2c3: lpi2c3grp { - fsl,pins = < - MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e - MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e - >; - bootph-pre-ram; - bootph-some-ram; - }; - - pinctrl_pcal6524: pcal6524grp { - fsl,pins = < - MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e - >; - bootph-pre-ram; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX91_PAD_UART1_RXD__LPUART1_RX 0x31e - MX91_PAD_UART1_TXD__LPUART1_TX 0x31e - >; - bootph-pre-ram; - bootph-some-ram; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e - MX91_PAD_DAP_TDI__LPUART5_RX 0x31e - MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e - MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e - MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e - MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e - MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e - MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e - MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e - MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e - MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e - MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e - MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e - MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe - MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe - MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe - MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe - MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe - MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe - MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe - MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe - MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 - MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 - MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 - MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 - MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 - MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 - MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 - MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 - MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 - MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 - MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 - >; - bootph-pre-ram; - bootph-some-ram; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e - MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e - MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e - MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e - MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e - MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e - MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe - MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e - >; - bootph-pre-ram; - bootph-some-ram; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { - fsl,pins = < - MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 - MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 - MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 - MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 - MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 - MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 - MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - bootph-pre-ram; - bootph-some-ram; - }; - - pinctrl_usdhc2_sleep: usdhc2sleepgrp { - fsl,pins = < - MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e - MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e - MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e - MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e - MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e - MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e - MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e - MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e - MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e - MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e - MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e - MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe - MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe - MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe - MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe - MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe - MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 - MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 - MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 - MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 - MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 - MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 - >; - }; - - pinctrl_usdhc3_sleep: usdhc3sleepgrp { - fsl,pins = < - MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e - MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e - MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e - MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e - MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e - MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e - >; - }; -}; diff --git a/arch/arm/dts/imx91-pinfunc.h b/arch/arm/dts/imx91-pinfunc.h deleted file mode 100644 index 5677928ab7c..00000000000 --- a/arch/arm/dts/imx91-pinfunc.h +++ /dev/null @@ -1,770 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright 2024 NXP - */ - -#ifndef __DTS_IMX91_PINFUNC_H -#define __DTS_IMX91_PINFUNC_H - -/* - * The pin function ID is a tuple of - * <mux_reg conf_reg input_reg mux_mode input_val> - */ -#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01b0 0x03d8 0x00 0x00 -#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01b0 0x0000 0x01 0x00 -#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01b0 0x0000 0x03 0x00 -#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01b0 0x0000 0x04 0x00 -#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01b0 0x0000 0x05 0x00 -#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01b0 0x0488 0x06 0x00 - -#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01b4 0x03dc 0x00 0x00 -#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01b4 0x0000 0x04 0x00 -#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01b4 0x0000 0x05 0x00 -#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01b4 0x0000 0x06 0x00 - -#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01b8 0x03d4 0x00 0x00 -#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01b8 0x0000 0x04 0x00 -#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01b8 0x0000 0x05 0x00 -#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01b8 0x0484 0x06 0x00 - -#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x01bc 0x0000 0x00 0x00 -#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x01bc 0x0000 0x01 0x00 -#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x01bc 0x0364 0x03 0x00 -#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000c 0x01bc 0x0000 0x04 0x00 -#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000c 0x01bc 0x0000 0x05 0x00 -#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x01bc 0x048c 0x06 0x00 - -#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01c0 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01c0 0x03f4 0x01 0x00 -#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01c0 0x04bc 0x02 0x00 -#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01c0 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01c0 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01c0 0x048c 0x05 0x01 -#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01c0 0x0404 0x06 0x00 -#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01c0 0x036c 0x07 0x00 - -#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01c4 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01c4 0x03f0 0x01 0x00 -#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01c4 0x0490 0x02 0x00 -#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01c4 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01c4 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01c4 0x0488 0x05 0x01 -#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01c4 0x0400 0x06 0x00 -#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01c4 0x0370 0x07 0x00 - -#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01c8 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01c8 0x03fc 0x01 0x00 -#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01c8 0x04c0 0x02 0x00 -#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01c8 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01c8 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01c8 0x0484 0x05 0x01 -#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01c8 0x040c 0x06 0x00 -#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01c8 0x0374 0x07 0x00 - -#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x01cc 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001c 0x01cc 0x03f8 0x01 0x00 -#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001c 0x01cc 0x04b8 0x02 0x00 -#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001c 0x01cc 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x01cc 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x01cc 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x01cc 0x0408 0x06 0x00 -#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x01cc 0x0378 0x07 0x00 - -#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01d0 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01d0 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01d0 0x0000 0x02 0x00 -#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01d0 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01d0 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01d0 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01d0 0x040c 0x06 0x01 -#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01d0 0x037c 0x07 0x00 - -#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01d4 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01d4 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01d4 0x04c4 0x02 0x00 -#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01d4 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01d4 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01d4 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01d4 0x0408 0x06 0x01 -#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01d4 0x0380 0x07 0x00 - -#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01d8 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01d8 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01d8 0x04c8 0x02 0x00 -#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01d8 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01d8 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01d8 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01d8 0x0414 0x06 0x00 -#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01d8 0x0384 0x07 0x00 - -#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x01dc 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x01dc 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002c 0x01dc 0x0494 0x02 0x00 -#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002c 0x01dc 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x01dc 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x01dc 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x01dc 0x0410 0x06 0x00 -#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x01dc 0x0388 0x07 0x00 - -#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01e0 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01e0 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01e0 0x0498 0x02 0x00 -#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01e0 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01e0 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01e0 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01e0 0x0414 0x06 0x01 -#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01e0 0x038c 0x07 0x00 - -#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01e4 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01e4 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01e4 0x049c 0x02 0x00 -#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01e4 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01e4 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01e4 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01e4 0x0410 0x06 0x01 -#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01e4 0x0390 0x07 0x00 - -#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01e8 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01e8 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01e8 0x04a0 0x02 0x00 -#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01e8 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01e8 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01e8 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01e8 0x041c 0x06 0x00 -#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01e8 0x0394 0x07 0x00 - -#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x01ec 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x01ec 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003c 0x01ec 0x04a4 0x02 0x00 -#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003c 0x01ec 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x01ec 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x01ec 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x01ec 0x0418 0x06 0x00 -#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x01ec 0x0398 0x07 0x00 - -#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01f0 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01f0 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01f0 0x04cc 0x02 0x00 -#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01f0 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01f0 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01f0 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01f0 0x041c 0x06 0x01 -#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01f0 0x04dc 0x07 0x00 - -#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01f4 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01f4 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01f4 0x04d0 0x02 0x00 -#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01f4 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01f4 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01f4 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01f4 0x0418 0x06 0x01 -#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01f4 0x039c 0x07 0x00 - -#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01f8 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01f8 0x0474 0x01 0x00 -#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01f8 0x04a8 0x02 0x00 -#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01f8 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01f8 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01f8 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01f8 0x0480 0x06 0x00 -#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01f8 0x03a0 0x07 0x00 - -#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x01fc 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004c 0x01fc 0x0470 0x01 0x00 -#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004c 0x01fc 0x04ac 0x02 0x00 -#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004c 0x01fc 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x01fc 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x01fc 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x01fc 0x047c 0x06 0x00 -#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x01fc 0x03a4 0x07 0x00 - -#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04cc 0x02 0x01 -#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046c 0x04 0x00 -#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00 -#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03a8 0x07 0x00 - -#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04b0 0x02 0x00 -#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00 -#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03ac 0x07 0x00 - -#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04d8 0x01 0x00 -#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04b4 0x02 0x00 -#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00 -#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03b0 0x07 0x00 - -#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x020c 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005c 0x020c 0x04dc 0x01 0x01 -#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005c 0x020c 0x04d0 0x02 0x01 -#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005c 0x020c 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005c 0x020c 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005c 0x020c 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005c 0x020c 0x0000 0x06 0x00 -#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005c 0x020c 0x0000 0x07 0x00 - -#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04c4 0x02 0x01 -#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00 -#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03b4 0x07 0x00 - -#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00 -#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00 -#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00 -#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04d8 0x07 0x01 - -#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04e8 0x01 0x00 -#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04e4 0x02 0x00 -#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01 -#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03b8 0x07 0x00 - -#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x021c 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006c 0x021c 0x04ec 0x01 0x00 -#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006c 0x021c 0x0000 0x02 0x00 -#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006c 0x021c 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006c 0x021c 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006c 0x021c 0x0400 0x06 0x01 -#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006c 0x021c 0x03bc 0x07 0x00 - -#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04f0 0x01 0x00 -#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00 -#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00 -#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03c0 0x07 0x00 - -#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04f4 0x01 0x00 -#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00 -#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03d4 0x05 0x01 -#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00 -#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03c4 0x07 0x00 - -#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04f8 0x01 0x00 -#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04c8 0x02 0x01 -#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03d8 0x05 0x01 -#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00 -#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04e0 0x07 0x00 - -#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x022c 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007c 0x022c 0x04fc 0x01 0x00 -#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007c 0x022c 0x0364 0x02 0x01 -#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007c 0x022c 0x0000 0x03 0x00 -#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007c 0x022c 0x0000 0x04 0x00 -#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007c 0x022c 0x03dc 0x05 0x01 -#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007c 0x022c 0x0000 0x06 0x00 -#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007c 0x022c 0x03c8 0x07 0x00 - -#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03f4 0x01 0x01 -#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00 -#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00 - -#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00 -#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03f0 0x01 0x01 -#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00 -#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00 - -#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00 -#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00 -#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00 - -#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008c 0x023c 0x0000 0x05 0x00 -#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008c 0x023c 0x0000 0x00 0x00 -#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008c 0x023c 0x03c8 0x04 0x01 - -#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00 -#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00 -#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00 - -#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00 -#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00 -#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00 - -#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00 -#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03cc 0x02 0x00 -#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00 -#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00 -#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03e0 0x06 0x00 - -#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009c 0x024c 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009c 0x024c 0x0000 0x01 0x00 -#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009c 0x024c 0x03d0 0x02 0x00 -#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009c 0x024c 0x0000 0x03 0x00 -#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009c 0x024c 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009c 0x024c 0x0000 0x05 0x00 -#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009c 0x024c 0x03e4 0x06 0x00 - -#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00a0 0x0250 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00 -#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00 -#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_TD3__GPIO4_IO2 0x00a0 0x0250 0x0000 0x05 0x00 -#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00 - -#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00a4 0x0254 0x0000 0x01 0x00 -#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00a4 0x0254 0x0364 0x02 0x02 -#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00a4 0x0254 0x0000 0x03 0x00 -#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00a4 0x0254 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00a4 0x0254 0x0000 0x05 0x00 -#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00a4 0x0254 0x03ec 0x06 0x00 - -#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00a8 0x0258 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00a8 0x0258 0x0000 0x01 0x00 -#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00a8 0x0258 0x0000 0x02 0x00 -#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00a8 0x0258 0x0000 0x03 0x00 -#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00a8 0x0258 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00a8 0x0258 0x0000 0x05 0x00 -#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00a8 0x0258 0x0000 0x06 0x00 - -#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00ac 0x025c 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00ac 0x025c 0x0474 0x01 0x01 -#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00ac 0x025c 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00ac 0x025c 0x0000 0x05 0x00 - -#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00b0 0x0260 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00b0 0x0260 0x0000 0x01 0x00 -#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00b0 0x0260 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00b0 0x0260 0x0000 0x05 0x00 -#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00b0 0x0260 0x043c 0x02 0x00 - -#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00b4 0x0264 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00b4 0x0264 0x0000 0x01 0x00 -#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00b4 0x0264 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00b4 0x0264 0x0000 0x05 0x00 -#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00b4 0x0264 0x0440 0x02 0x00 - -#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00b8 0x0268 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00b8 0x0268 0x0000 0x01 0x00 -#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00b8 0x0268 0x0000 0x03 0x00 -#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00b8 0x0268 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00b8 0x0268 0x0000 0x05 0x00 -#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00b8 0x0268 0x0434 0x02 0x00 - -#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00bc 0x026c 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00bc 0x026c 0x0000 0x01 0x00 -#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00bc 0x026c 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00bc 0x026c 0x0000 0x05 0x00 -#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00bc 0x026c 0x0444 0x02 0x00 - -#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00c0 0x0270 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00c0 0x0270 0x0470 0x01 0x01 -#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00c0 0x0270 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00c0 0x0270 0x0000 0x05 0x00 - -#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00c4 0x0274 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00c4 0x0274 0x046c 0x01 0x01 -#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00c4 0x0274 0x0448 0x03 0x00 -#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00c4 0x0274 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00c4 0x0274 0x0000 0x05 0x00 - -#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00c8 0x0278 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00c8 0x0278 0x044c 0x03 0x00 -#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00c8 0x0278 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00c8 0x0278 0x0000 0x05 0x00 - -#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00cc 0x027c 0x0000 0x00 0x00 -#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00cc 0x027c 0x0000 0x02 0x00 -#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00cc 0x027c 0x0450 0x03 0x00 -#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00cc 0x027c 0x0000 0x04 0x00 -#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00cc 0x027c 0x0000 0x05 0x00 - -#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00d0 0x0280 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00d0 0x0280 0x0000 0x01 0x00 -#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00d0 0x0280 0x0000 0x02 0x00 -#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00d0 0x0280 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00d0 0x0280 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00d0 0x0280 0x04bc 0x06 0x01 - -#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00d4 0x0284 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00d4 0x0284 0x0000 0x01 0x00 -#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00d4 0x0284 0x0000 0x02 0x00 -#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00d4 0x0284 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00d4 0x0284 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00d4 0x0284 0x0490 0x06 0x01 - -#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00d8 0x0288 0x0000 0x02 0x00 -#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00d8 0x0288 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00d8 0x0288 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00d8 0x0288 0x04c0 0x06 0x01 -#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00d8 0x0288 0x0000 0x00 0x00 - -#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00dc 0x028c 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00dc 0x028c 0x0000 0x01 0x00 -#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00dc 0x028c 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00dc 0x028c 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00dc 0x028c 0x04b8 0x06 0x01 - -#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00e0 0x0290 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00e0 0x0290 0x0000 0x01 0x00 -#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00e0 0x0290 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00e0 0x0290 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00e0 0x0290 0x0494 0x06 0x01 - -#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00e4 0x0294 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00e4 0x0294 0x0480 0x01 0x01 -#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00e4 0x0294 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00e4 0x0294 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00e4 0x0294 0x0498 0x06 0x01 - -#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00e8 0x0298 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00e8 0x0298 0x0000 0x01 0x00 -#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00e8 0x0298 0x0000 0x02 0x00 -#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00e8 0x0298 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00e8 0x0298 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00e8 0x0298 0x049c 0x06 0x01 - -#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00ec 0x029c 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00ec 0x029c 0x0000 0x01 0x00 -#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00ec 0x029c 0x0000 0x02 0x00 -#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00ec 0x029c 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00ec 0x029c 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00ec 0x029c 0x04a0 0x06 0x01 - -#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00f0 0x02a0 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00f0 0x02a0 0x0000 0x01 0x00 -#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00f0 0x02a0 0x0000 0x02 0x00 -#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00f0 0x02a0 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00f0 0x02a0 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00f0 0x02a0 0x04a4 0x06 0x01 - -#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00f4 0x02a4 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00f4 0x02a4 0x0000 0x01 0x00 -#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00f4 0x02a4 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00f4 0x02a4 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00f4 0x02a4 0x04a8 0x06 0x01 - -#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00f8 0x02a8 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00f8 0x02a8 0x047c 0x01 0x01 -#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00f8 0x02a8 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00f8 0x02a8 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00f8 0x02a8 0x04ac 0x06 0x01 - -#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00fc 0x02ac 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00fc 0x02ac 0x04e4 0x01 0x01 -#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00fc 0x02ac 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00fc 0x02ac 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00fc 0x02ac 0x04b0 0x06 0x01 - -#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02b0 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02b0 0x0478 0x01 0x01 -#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02b0 0x0000 0x02 0x00 -#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02b0 0x0000 0x03 0x00 -#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02b0 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02b0 0x0000 0x05 0x00 -#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02b0 0x04b4 0x06 0x01 - -#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02b4 0x0000 0x00 0x00 -#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02b4 0x0000 0x01 0x00 -#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02b4 0x04e4 0x02 0x02 -#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02b4 0x0000 0x03 0x00 -#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02b4 0x0000 0x04 0x00 -#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02b4 0x0000 0x05 0x00 - -#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02b8 0x038c 0x04 0x01 -#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02b8 0x0000 0x05 0x00 -#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02b8 0x0000 0x00 0x00 -#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02b8 0x043c 0x03 0x01 - -#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010c 0x02bc 0x0000 0x00 0x00 -#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010c 0x02bc 0x0390 0x04 0x01 -#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010c 0x02bc 0x0000 0x05 0x00 -#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010c 0x02bc 0x0440 0x03 0x01 - -#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02c0 0x0000 0x00 0x00 -#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02c0 0x0394 0x04 0x01 -#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02c0 0x0000 0x05 0x00 -#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02c0 0x0434 0x03 0x01 - -#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02c4 0x0000 0x00 0x00 -#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02c4 0x0398 0x04 0x01 -#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02c4 0x0000 0x05 0x00 -#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02c4 0x0000 0x06 0x00 -#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02c4 0x0444 0x03 0x01 - -#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02c8 0x0000 0x00 0x00 -#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02c8 0x0000 0x04 0x00 -#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02c8 0x0000 0x05 0x00 -#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02c8 0x0000 0x06 0x00 -#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02c8 0x0438 0x03 0x00 - -#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011c 0x02cc 0x0000 0x00 0x00 -#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011c 0x02cc 0x0000 0x01 0x00 -#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011c 0x02cc 0x039c 0x04 0x01 -#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011c 0x02cc 0x0000 0x05 0x00 -#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011c 0x02cc 0x0424 0x03 0x00 - -#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02d0 0x0000 0x00 0x00 -#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02d0 0x0000 0x01 0x00 -#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02d0 0x03a0 0x04 0x01 -#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02d0 0x0000 0x05 0x00 -#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02d0 0x0420 0x03 0x00 - -#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02d4 0x0000 0x00 0x00 -#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02d4 0x0000 0x01 0x00 -#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02d4 0x0000 0x02 0x00 -#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02d4 0x03a4 0x04 0x01 -#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02d4 0x0000 0x05 0x00 -#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02d4 0x042c 0x03 0x00 - -#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02d8 0x0000 0x00 0x00 -#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02d8 0x0000 0x01 0x00 -#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02d8 0x0000 0x02 0x00 -#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02d8 0x03a8 0x04 0x01 -#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02d8 0x0000 0x05 0x00 -#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02d8 0x0428 0x03 0x00 - -#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012c 0x02dc 0x0000 0x00 0x00 -#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012c 0x02dc 0x0000 0x01 0x00 -#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012c 0x02dc 0x0000 0x02 0x00 -#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012c 0x02dc 0x03ac 0x04 0x01 -#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012c 0x02dc 0x0000 0x05 0x00 -#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012c 0x02dc 0x0430 0x03 0x00 - -#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02e0 0x0000 0x00 0x00 -#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02e0 0x0000 0x01 0x00 -#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02e0 0x03b0 0x04 0x01 -#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02e0 0x0000 0x05 0x00 - -#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02e4 0x0000 0x00 0x00 -#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02e4 0x0000 0x01 0x00 -#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02e4 0x0450 0x02 0x01 -#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02e4 0x0000 0x04 0x00 -#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02e4 0x0000 0x05 0x00 -#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02e4 0x0368 0x06 0x00 - -#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02e8 0x04e8 0x00 0x01 -#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02e8 0x0000 0x01 0x00 -#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02e8 0x0454 0x02 0x00 -#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02e8 0x03b4 0x04 0x01 -#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02e8 0x0000 0x05 0x00 - -#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013c 0x02ec 0x04ec 0x00 0x01 -#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013c 0x02ec 0x0000 0x01 0x00 -#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013c 0x02ec 0x0000 0x02 0x00 -#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013c 0x02ec 0x0000 0x04 0x00 -#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013c 0x02ec 0x0000 0x05 0x00 - -#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02f0 0x04f0 0x00 0x01 -#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02f0 0x0000 0x01 0x00 -#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02f0 0x0460 0x02 0x00 -#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02f0 0x03b8 0x04 0x01 -#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02f0 0x0000 0x05 0x00 - -#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02f4 0x04f4 0x00 0x01 -#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02f4 0x0000 0x01 0x00 -#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02f4 0x0000 0x02 0x00 -#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02f4 0x03bc 0x04 0x01 -#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02f4 0x0000 0x05 0x00 - -#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02f8 0x04f8 0x00 0x01 -#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02f8 0x03fc 0x02 0x01 -#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02f8 0x0000 0x01 0x00 -#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02f8 0x03c0 0x04 0x01 -#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02f8 0x0000 0x05 0x00 - -#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014c 0x02fc 0x04fc 0x00 0x01 -#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014c 0x02fc 0x0000 0x01 0x00 -#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014c 0x02fc 0x03f8 0x02 0x01 -#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014c 0x02fc 0x03c4 0x04 0x01 -#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014c 0x02fc 0x0000 0x05 0x00 - -#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00 -#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00 -#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03cc 0x02 0x01 -#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036c 0x04 0x01 -#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00 -#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03e0 0x03 0x01 - -#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00 -#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00 -#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00 -#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03d0 0x02 0x01 -#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01 -#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00 -#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00 -#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03e4 0x03 0x01 - -#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00 -#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00 -#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00 -#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00 -#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01 -#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00 -#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00 - -#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015c 0x030c 0x0000 0x00 0x00 -#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015c 0x030c 0x0000 0x01 0x00 -#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015c 0x030c 0x0000 0x02 0x00 -#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015c 0x030c 0x0378 0x04 0x01 -#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015c 0x030c 0x0000 0x05 0x00 -#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015c 0x030c 0x045c 0x03 0x00 -#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015c 0x030c 0x0000 0x06 0x00 - -#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00 -#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00 -#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03 -#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037c 0x04 0x01 -#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00 -#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00 -#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00 - -#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00 -#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00 -#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00 -#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01 -#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00 -#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00 -#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00 - -#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00 -#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01 -#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00 -#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01 -#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00 -#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00 -#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00 - -#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016c 0x031c 0x0000 0x00 0x00 -#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016c 0x031c 0x044c 0x01 0x01 -#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016c 0x031c 0x0388 0x04 0x01 -#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016c 0x031c 0x0000 0x05 0x00 -#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016c 0x031c 0x0000 0x06 0x00 - -#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03e0 0x00 0x02 -#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00 -#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00 -#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00 -#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00 - -#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03e4 0x00 0x02 -#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00 -#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00 -#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00 -#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00 - -#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03e8 0x00 0x01 -#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00 -#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00 -#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00 -#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00 -#define MX91_PAD_I2C2_SCL__GPIO1_IO2 0x0178 0x0328 0x0000 0x05 0x00 -#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00 - -#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01 -#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017c 0x032c 0x0000 0x02 0x00 -#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017c 0x032c 0x0000 0x03 0x00 -#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017c 0x032c 0x0000 0x04 0x00 -#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017c 0x032c 0x0000 0x05 0x00 - -#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01 -#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00 -#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02 -#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00 -#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00 - -#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045c 0x00 0x01 -#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00 -#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02 -#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00 -#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00 - -#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01 -#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01 -#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02 -#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00 -#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04d4 0x04 0x00 -#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00 - -#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018c 0x033c 0x0468 0x00 0x01 -#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018c 0x033c 0x0000 0x01 0x00 -#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018c 0x033c 0x043c 0x02 0x02 -#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018c 0x033c 0x0000 0x03 0x00 -#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018c 0x033c 0x0000 0x05 0x00 -#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018c 0x033c 0x04e0 0x07 0x02 - -#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00 -#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00 -#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00 -#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00 -#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00 - -#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04c4 0x00 0x02 -#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00 -#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01 -#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00 -#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00 -#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00 -#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01 - -#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04c8 0x00 0x02 -#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01 -#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00 -#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00 -#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00 -#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01 - -#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019c 0x034c 0x0000 0x00 0x00 -#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019c 0x034c 0x0000 0x01 0x00 -#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019c 0x034c 0x0420 0x02 0x01 -#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019c 0x034c 0x0000 0x03 0x00 -#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019c 0x034c 0x0000 0x04 0x00 -#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019c 0x034c 0x0000 0x05 0x00 - -#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01a0 0x0350 0x0000 0x00 0x00 -#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01a0 0x0350 0x0460 0x01 0x01 -#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01a0 0x0350 0x042c 0x02 0x01 -#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01a0 0x0350 0x0000 0x03 0x00 -#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01a0 0x0350 0x0360 0x04 0x02 -#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01a0 0x0350 0x0000 0x05 0x00 - -#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01a4 0x0354 0x0000 0x00 0x00 -#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01a4 0x0354 0x0000 0x01 0x00 -#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01a4 0x0354 0x0428 0x02 0x01 -#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01a4 0x0354 0x0000 0x03 0x00 -#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01a4 0x0354 0x0000 0x04 0x00 -#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01a4 0x0354 0x0000 0x05 0x00 -#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01a4 0x0354 0x04d4 0x06 0x01 - -#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01a8 0x0358 0x0000 0x00 0x00 -#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01a8 0x0358 0x04d4 0x01 0x02 -#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01a8 0x0358 0x0430 0x02 0x01 -#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01a8 0x0358 0x0000 0x03 0x00 -#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01a8 0x0358 0x0000 0x04 0x00 -#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01a8 0x0358 0x0000 0x05 0x00 - -#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01ac 0x035c 0x0000 0x00 0x00 -#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01ac 0x035c 0x0000 0x05 0x00 -#endif /* __DTS_IMX91_PINFUNC_H */ diff --git a/arch/arm/dts/imx91-u-boot.dtsi b/arch/arm/dts/imx91-u-boot.dtsi index 5b639c965d6..149f7bc685a 100644 --- a/arch/arm/dts/imx91-u-boot.dtsi +++ b/arch/arm/dts/imx91-u-boot.dtsi @@ -90,3 +90,15 @@ }; }; }; + +&wdog3 { + bootph-all; +}; + +&wdog4 { + bootph-all; +}; + +&wdog5 { + bootph-all; +}; diff --git a/arch/arm/dts/imx91.dtsi b/arch/arm/dts/imx91.dtsi deleted file mode 100644 index 9963f0bb5ce..00000000000 --- a/arch/arm/dts/imx91.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2024 NXP - */ - -#include "imx91-pinfunc.h" -#include "imx93.dtsi" - -/delete-node/ &A55_1; -/delete-node/ &mlmix; -/delete-node/ &mu1; -/delete-node/ &mu2; - -&clk { - compatible = "fsl,imx91-ccm"; -}; - -&eqos { - clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, - <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, - <&clk IMX91_CLK_ENET_TIMER>, - <&clk IMX91_CLK_ENET1_QOS_TSN>, - <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; - assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, - <&clk IMX91_CLK_ENET1_QOS_TSN>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; -}; - -&fec { - clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>, - <&clk IMX91_CLK_ENET2_REGULAR_GATE>, - <&clk IMX91_CLK_ENET_TIMER>, - <&clk IMX91_CLK_ENET2_REGULAR>, - <&clk IMX93_CLK_DUMMY>; - assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, - <&clk IMX91_CLK_ENET2_REGULAR>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; - assigned-clock-rates = <100000000>, <250000000>; -}; - -&iomuxc { - compatible = "fsl,imx91-iomuxc"; -}; - -&tmu { - status = "disabled"; -}; - -&{/thermal-zones/cpu-thermal/cooling-maps/map0} { - cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -}; diff --git a/arch/arm/dts/imx93-11x11-frdm.dts b/arch/arm/dts/imx93-11x11-frdm.dts deleted file mode 100644 index 993567e767d..00000000000 --- a/arch/arm/dts/imx93-11x11-frdm.dts +++ /dev/null @@ -1,603 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/dts-v1/; - -#include <dt-bindings/usb/pd.h> -#include "imx93.dtsi" - -/ { - compatible = "fsl,imx93-11x11-frdm", "fsl,imx93"; - model = "NXP i.MX93 11X11 FRDM board"; - - aliases { - mmc0 = &usdhc1; /* EMMC */ - mmc1 = &usdhc2; /* uSD */ - rtc0 = &pcf2131; - serial0 = &lpuart1; - }; - - chosen { - stdout-path = &lpuart1; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vref_1v8"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - off-on-delay-us = <12000>; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - pinctrl-names = "default"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "VSD_3V3"; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_usdhc3_vmmc: regulator-usdhc3 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "WLAN_EN"; - gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * IW612 wifi chip needs more delay than other wifi chips to complete - * the host interface initialization after power up, otherwise the - * internal state of IW612 may be unstable, resulting in the failure of - * the SDIO3.0 switch voltage. - */ - startup-delay-us = <20000>; - }; - - reserved-memory { - ranges; - #address-cells = <2>; - #size-cells = <2>; - - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x80000000 0 0x30000000>; - reusable; - size = <0 0x10000000>; - linux,cma-default; - }; - - rsc_table: rsc-table@2021e000 { - reg = <0 0x2021e000 0 0x1000>; - no-map; - }; - - vdev0vring0: vdev0vring0@a4000000 { - reg = <0 0xa4000000 0 0x8000>; - no-map; - }; - - vdev0vring1: vdev0vring1@a4008000 { - reg = <0 0xa4008000 0 0x8000>; - no-map; - }; - - vdev1vring0: vdev1vring0@a4010000 { - reg = <0 0xa4010000 0 0x8000>; - no-map; - }; - - vdev1vring1: vdev1vring1@a4018000 { - reg = <0 0xa4018000 0 0x8000>; - no-map; - }; - - vdevbuffer: vdevbuffer@a4020000 { - compatible = "shared-dma-pool"; - reg = <0 0xa4020000 0 0x100000>; - no-map; - }; - }; - - usdhc3_pwrseq: usdhc3_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&eqos { - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; - pinctrl-0 = <&pinctrl_eqos>; - pinctrl-1 = <&pinctrl_eqos_sleep>; - pinctrl-names = "default", "sleep"; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&fec { - phy-handle = <ðphy2>; - phy-mode = "rgmii-id"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - pinctrl-names = "default", "sleep"; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy2: ethernet-phy@2 { - reg = <2>; - eee-broken-1000t; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&lpi2c2 { - clock-frequency = <400000>; - pinctrl-0 = <&pinctrl_lpi2c2>; - pinctrl-names = "default"; - status = "okay"; - - pcal6524: gpio@22 { - compatible = "nxp,pcal6524"; - reg = <0x22>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - pinctrl-0 = <&pinctrl_pcal6524>; - pinctrl-names = "default"; - }; - - pmic@25 { - compatible = "nxp,pca9451a"; - reg = <0x25>; - interrupt-parent = <&pcal6524>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - - regulators { - - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2237500>; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-ramp-delay = <3125>; - }; - - buck4: BUCK4 { - regulator-name = "BUCK4"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - }; - - buck5: BUCK5 { - regulator-name = "BUCK5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - pagesize = <64>; - }; -}; - -&lpi2c3 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - pinctrl-0 = <&pinctrl_lpi2c3>; - pinctrl-names = "default"; - status = "okay"; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x50>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - typec1_con: connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <15000000>; - power-role = "dual"; - self-powered; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 20000, 3000)>; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - try-power-role = "sink"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - }; - }; - }; - - pcf2131: rtc@53 { - compatible = "nxp,pcf2131"; - reg = <0x53>; - interrupt-parent = <&pcal6524>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&lpuart1 { /* console */ - pinctrl-0 = <&pinctrl_uart1>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usbotg1 { - adp-disable; - disable-over-current; - dr_mode = "otg"; - hnp-disable; - srp-disable; - usb-role-switch; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - status = "okay"; - - port { - - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - samsung,picophy-dc-vol-level-adjust = <7>; - samsung,picophy-pre-emp-curr-control = <3>; - status = "okay"; -}; - -&usdhc1 { - bus-width = <8>; - non-removable; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - status = "okay"; -}; - -&usdhc2 { - bus-width = <4>; - cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; - no-mmc; - no-sdio; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&wdog3 { - status = "okay"; -}; - -&iomuxc { - - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e - MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e - MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e - MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e - MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e - MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e - MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e - MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e - MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e - MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e - MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e - MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e - MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_eqos_sleep: eqossleepgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e - MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e - MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e - MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e - MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e - MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e - MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e - MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e - MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e - MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e - MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e - MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e - MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e - MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e - MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e - MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e - MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e - MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e - MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_fec_sleep: fecsleepgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e - MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e - MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e - MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e - MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e - MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e - MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e - MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e - MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e - MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e - MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e - MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e - MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e - MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX93_PAD_GPIO_IO25__CAN2_TX 0x139e - MX93_PAD_GPIO_IO27__CAN2_RX 0x139e - >; - }; - - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = < - MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e - MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c3: lpi2c3grp { - fsl,pins = < - MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e - MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e - >; - }; - - pinctrl_pcal6524: pcal6524grp { - fsl,pins = < - MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x31e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 - MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e - MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 - MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_sleep: usdhc2-sleepgrp { - fsl,pins = < - MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e - MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e - MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e - MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e - MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e - MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e - MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e - >; - }; -}; diff --git a/arch/arm/dts/imx93-u-boot.dtsi b/arch/arm/dts/imx93-u-boot.dtsi index dc86746ac90..bd970c955cf 100644 --- a/arch/arm/dts/imx93-u-boot.dtsi +++ b/arch/arm/dts/imx93-u-boot.dtsi @@ -69,6 +69,9 @@ container; image0 = "a55", "bl31.bin", "0x204E0000"; image1 = "a55", "u-boot.bin", "0x80200000"; +#if defined(CONFIG_OPTEE) + image2 = "a55", "tee.bin", "0x96000000"; +#endif }; }; }; @@ -96,3 +99,15 @@ 0x000001b2 0x800001b6>; #thermal-sensor-cells = <1>; }; + +&wdog3 { + bootph-all; +}; + +&wdog4 { + bootph-all; +}; + +&wdog5 { + bootph-all; +}; diff --git a/arch/arm/dts/imx93-var-som-symphony.dts b/arch/arm/dts/imx93-var-som-symphony.dts deleted file mode 100644 index 1bc61942716..00000000000 --- a/arch/arm/dts/imx93-var-som-symphony.dts +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 NXP - * Copyright 2023 Variscite Ltd. - */ - -/dts-v1/; - -#include "imx93-var-som.dtsi" - -/{ - model = "Variscite VAR-SOM-MX93 on Symphony evaluation board"; - compatible = "variscite,var-som-mx93-symphony", - "variscite,var-som-mx93", "fsl,imx93"; - - aliases { - ethernet0 = &eqos; - ethernet1 = &fec; - }; - - chosen { - stdout-path = &lpuart1; - }; - - /* - * Needed only for Symphony <= v1.5 - */ - reg_fec_phy: regulator-fec-phy { - compatible = "regulator-fixed"; - regulator-name = "fec-phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <20000>; - gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <20000>; - enable-active-high; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed"; - regulator-name = "vref_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ethosu_mem: ethosu-region@88000000 { - compatible = "shared-dma-pool"; - reusable; - reg = <0x0 0x88000000 0x0 0x8000000>; - }; - - vdev0vring0: vdev0vring0@87ee0000 { - reg = <0 0x87ee0000 0 0x8000>; - no-map; - }; - - vdev0vring1: vdev0vring1@87ee8000 { - reg = <0 0x87ee8000 0 0x8000>; - no-map; - }; - - vdev1vring0: vdev1vring0@87ef0000 { - reg = <0 0x87ef0000 0 0x8000>; - no-map; - }; - - vdev1vring1: vdev1vring1@87ef8000 { - reg = <0 0x87ef8000 0 0x8000>; - no-map; - }; - - rsc_table: rsc-table@2021f000 { - reg = <0 0x2021f000 0 0x1000>; - no-map; - }; - - vdevbuffer: vdevbuffer@87f00000 { - compatible = "shared-dma-pool"; - reg = <0 0x87f00000 0 0x100000>; - no-map; - }; - - ele_reserved: ele-reserved@87de0000 { - compatible = "shared-dma-pool"; - reg = <0 0x87de0000 0 0x100000>; - no-map; - }; - }; -}; - -/* Use external instead of internal RTC*/ -&bbnsm_rtc { - status = "disabled"; -}; - -&eqos { - mdio { - ethphy1: ethernet-phy@5 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <5>; - qca,disable-smarteee; - eee-broken-1000t; - reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <20000>; - vddio-supply = <&vddio1>; - - vddio1: vddio-regulator { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - phy-supply = <®_fec_phy>; - status = "okay"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e - MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e - MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e - MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e - MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e - MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX93_PAD_PDM_CLK__CAN1_TX 0x139e - MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e - MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { - fsl,pins = < - MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e - MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e - >; - }; - - pinctrl_lpi2c5: lpi2c5grp { - fsl,pins = < - MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e - MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { - fsl,pins = < - MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e - MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e - >; - }; - - pinctrl_pca9534: pca9534grp { - fsl,pins = < - MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x31e - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; -}; - -&lpi2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "sleep", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c1>; - pinctrl-1 = <&pinctrl_lpi2c1_gpio>; - pinctrl-2 = <&pinctrl_lpi2c1_gpio>; - scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; - - /* DS1337 RTC module */ - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; -}; - -&lpi2c5 { - clock-frequency = <400000>; - pinctrl-names = "default", "sleep", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c5>; - pinctrl-1 = <&pinctrl_lpi2c5_gpio>; - pinctrl-2 = <&pinctrl_lpi2c5_gpio>; - scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pca9534: gpio@20 { - compatible = "nxp,pca9534"; - reg = <0x20>; - gpio-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9534>; - interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - #gpio-cells = <2>; - wakeup-source; - }; -}; - -/* Console */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; - clock-names = "ipg", "per"; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - hnp-disable; - srp-disable; - adp-disable; - disable-over-current; - status = "okay"; -}; - -/* SD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; - no-sdio; - no-mmc; -}; - -/* Watchdog */ -&wdog3 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx93-var-som.dtsi b/arch/arm/dts/imx93-var-som.dtsi deleted file mode 100644 index 6c77b886666..00000000000 --- a/arch/arm/dts/imx93-var-som.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 NXP - * Copyright 2023 Variscite Ltd. - */ - -/dts-v1/; - -#include "imx93.dtsi" - -/{ - model = "Variscite VAR-SOM-MX93 module"; - compatible = "variscite,var-som-mx93", "fsl,imx93"; - - mmc_pwrseq: mmc-pwrseq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <100>; - power-off-delay-us = <10000>; - reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ - <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ - }; - - reg_eqos_phy: regulator-eqos-phy { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_eqos_phy>; - regulator-name = "eth_phy_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100000>; - regulator-always-on; - }; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - phy-supply = <®_eqos_phy>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <1000000>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - eee-broken-1000t; - }; - }; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e - MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e - MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e - MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e - MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e - MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe - MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e - MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e - MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e - MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e - MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e - MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe - MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_reg_eqos_phy: regeqosgrp { - fsl,pins = < - MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe - >; - }; -}; - -/* eMMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1>; - pinctrl-2 = <&pinctrl_usdhc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi deleted file mode 100644 index d6964714ea0..00000000000 --- a/arch/arm/dts/imx93.dtsi +++ /dev/null @@ -1,906 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 NXP - */ - -#include <dt-bindings/clock/imx93-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/fsl,imx93-power.h> -#include <dt-bindings/thermal/thermal.h> - -#include "imx93-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &lpi2c1; - i2c1 = &lpi2c2; - i2c2 = &lpi2c3; - i2c3 = &lpi2c4; - i2c4 = &lpi2c5; - i2c5 = &lpi2c6; - i2c6 = &lpi2c7; - i2c7 = &lpi2c8; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &lpuart1; - serial1 = &lpuart2; - serial2 = &lpuart3; - serial3 = &lpuart4; - serial4 = &lpuart5; - serial5 = &lpuart6; - serial6 = &lpuart7; - serial7 = &lpuart8; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A55_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - #cooling-cells = <2>; - }; - - A55_1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - }; - - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <24000000>; - arm,no-tick-in-suspend; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@48000000 { - compatible = "arm,gic-v3"; - reg = <0 0x48000000 0 0x10000>, - <0 0x48040000 0 0xc0000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x80000000>, - <0x28000000 0x0 0x28000000 0x10000000>; - - aips1: bus@44000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x44000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - anomix_ns_gpr: syscon@44210000 { - compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; - reg = <0x44210000 0x1000>; - }; - - mu1: mailbox@44230000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x44230000 0x10000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU1_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@44290000 { - compatible = "nxp,sysctr-timer"; - reg = <0x44290000 0x30000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc_24m>; - clock-names = "per"; - nxp,no-divider; - }; - - tpm1: pwm@44310000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44310000 0x1000>; - clocks = <&clk IMX93_CLK_TPM1_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm2: pwm@44320000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44320000 0x10000>; - clocks = <&clk IMX93_CLK_TPM2_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lpi2c1: i2c@44340000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44340000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c2: i2c@44350000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44350000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi1: spi@44360000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44360000 0x10000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi2: spi@44370000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44370000 0x10000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpuart1: serial@44380000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44380000 0x1000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - lpuart2: serial@44390000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44390000 0x1000>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART2_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - flexcan1: can@443a0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x443a0000 0x10000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_AON>, - <&clk IMX93_CLK_CAN1_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - status = "disabled"; - }; - - iomuxc: pinctrl@443c0000 { - compatible = "fsl,imx93-iomuxc"; - reg = <0x443c0000 0x10000>; - status = "okay"; - }; - - bbnsm: bbnsm@44440000 { - compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; - reg = <0x44440000 0x10000>; - - bbnsm_rtc: rtc { - compatible = "nxp,imx93-bbnsm-rtc"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - }; - - bbnsm_pwrkey: pwrkey { - compatible = "nxp,imx93-bbnsm-pwrkey"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - linux,code = <KEY_POWER>; - }; - }; - - clk: clock-controller@44450000 { - compatible = "fsl,imx93-ccm"; - reg = <0x44450000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; - clock-names = "osc_32k", "osc_24m", "clk_ext1"; - status = "okay"; - }; - - src: system-controller@44460000 { - compatible = "fsl,imx93-src", "syscon"; - reg = <0x44460000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mediamix: power-domain@44462400 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44462400 0x400>, <0x44465800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_MEDIA_AXI>, - <&clk IMX93_CLK_MEDIA_APB>; - }; - - mlmix: power-domain@44461800 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44461800 0x400>, <0x44464800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_ML_APB>, - <&clk IMX93_CLK_ML>; - }; - }; - - anatop: anatop@44480000 { - compatible = "fsl,imx93-anatop", "syscon"; - reg = <0x44480000 0x10000>; - }; - - tmu: tmu@44482000 { - compatible = "fsl,imx93-tmu"; - reg = <0x44482000 0x1000>; - clocks = <&clk IMX93_CLK_TMC_GATE>; - little-endian; - fsl,tmu-calibration = <0x0000000e 0x800000da - 0x00000029 0x800000e9 - 0x00000056 0x80000102 - 0x000000a2 0x8000012a - 0x00000116 0x80000166 - 0x00000195 0x800001a7 - 0x000001b2 0x800001b6>; - #thermal-sensor-cells = <1>; - }; - - adc1: adc@44530000 { - compatible = "nxp,imx93-adc"; - reg = <0x44530000 0x10000>; - interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_ADC1_GATE>; - clock-names = "ipg"; - #io-channel-cells = <1>; - status = "disabled"; - }; - }; - - aips2: bus@42000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - wakeupmix_gpr: syscon@42420000 { - compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; - reg = <0x42420000 0x1000>; - }; - - mu2: mailbox@42440000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x42440000 0x10000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU2_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - wdog3: wdog@42490000 { - compatible = "fsl,imx93-wdt"; - reg = <0x42490000 0x10000>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG3_GATE>; - timeout-sec = <40>; - }; - - tpm3: pwm@424e0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424e0000 0x1000>; - clocks = <&clk IMX93_CLK_TPM3_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm4: pwm@424f0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424f0000 0x10000>; - clocks = <&clk IMX93_CLK_TPM4_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm5: pwm@42500000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42500000 0x10000>; - clocks = <&clk IMX93_CLK_TPM5_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm6: pwm@42510000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42510000 0x10000>; - clocks = <&clk IMX93_CLK_TPM6_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lpi2c3: i2c@42530000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42530000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c4: i2c@42540000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42540000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi3: spi@42550000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42550000 0x10000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi4: spi@42560000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42560000 0x10000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpuart3: serial@42570000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42570000 0x1000>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART3_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart4: serial@42580000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42580000 0x1000>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART4_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart5: serial@42590000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42590000 0x1000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART5_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart6: serial@425a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x425a0000 0x1000>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART6_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - flexcan2: can@425b0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x425b0000 0x10000>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_CAN2_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN2>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - status = "disabled"; - }; - - flexspi1: spi@425e0000 { - compatible = "nxp,imx8mm-fspi"; - reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, - <&clk IMX93_CLK_FLEXSPI1_GATE>; - clock-names = "fspi_en", "fspi"; - assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - status = "disabled"; - }; - - lpuart7: serial@42690000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42690000 0x1000>; - interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART7_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart8: serial@426a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x426a0000 0x1000>; - interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART8_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpi2c5: i2c@426b0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c6: i2c@426c0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426c0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c7: i2c@426d0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426d0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c8: i2c@426e0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426e0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi5: spi@426f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x426f0000 0x10000>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi6: spi@42700000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42700000 0x10000>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi7: spi@42710000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42710000 0x10000>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi8: spi@42720000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42720000 0x10000>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - }; - - aips3: bus@42800000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42800000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usdhc1: mmc@42850000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42850000 0x10000>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC1_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <8>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc2: mmc@42860000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42860000 0x10000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC2_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - eqos: ethernet@428a0000 { - compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; - reg = <0x428a0000 0x10000>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>, - <&clk IMX93_CLK_ENET_QOS_GATE>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; - assigned-clock-rates = <100000000>, <250000000>; - intf_mode = <&wakeupmix_gpr 0x28>; - snps,clk-csr = <0>; - status = "disabled"; - }; - - fec: ethernet@42890000 { - compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x42890000 0x10000>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <100000000>, <250000000>, <50000000>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - - usdhc3: mmc@428b0000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x428b0000 0x10000>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC3_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - }; - - gpio2: gpio@43810080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43810080 0x1000>, <0x43810040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO2_GATE>, - <&clk IMX93_CLK_GPIO2_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 4 30>; - }; - - gpio3: gpio@43820080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43820080 0x1000>, <0x43820040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO3_GATE>, - <&clk IMX93_CLK_GPIO3_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, - <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; - }; - - gpio4: gpio@43830080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43830080 0x1000>, <0x43830040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO4_GATE>, - <&clk IMX93_CLK_GPIO4_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; - }; - - gpio1: gpio@47400080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x47400080 0x1000>, <0x47400040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO1_GATE>, - <&clk IMX93_CLK_GPIO1_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 92 16>; - }; - - s4muap: mailbox@47520000 { - compatible = "fsl,imx93-mu-s4"; - reg = <0x47520000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - #mbox-cells = <2>; - }; - - media_blk_ctrl: system-controller@4ac10000 { - compatible = "fsl,imx93-media-blk-ctrl", "syscon"; - reg = <0x4ac10000 0x10000>; - power-domains = <&mediamix>; - clocks = <&clk IMX93_CLK_MEDIA_APB>, - <&clk IMX93_CLK_MEDIA_AXI>, - <&clk IMX93_CLK_NIC_MEDIA_GATE>, - <&clk IMX93_CLK_MEDIA_DISP_PIX>, - <&clk IMX93_CLK_CAM_PIX>, - <&clk IMX93_CLK_PXP_GATE>, - <&clk IMX93_CLK_LCDIF_GATE>, - <&clk IMX93_CLK_ISI_GATE>, - <&clk IMX93_CLK_MIPI_CSI_GATE>, - <&clk IMX93_CLK_MIPI_DSI_GATE>; - clock-names = "apb", "axi", "nic", "disp", "cam", - "pxp", "lcdif", "isi", "csi", "dsi"; - #power-domain-cells = <1>; - status = "disabled"; - }; - - usbotg1: usb@4c100000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c100000 0x200>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root_clk", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@4c100200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c100200 0x200>; - #index-cells = <1>; - }; - - usbotg2: usb@4c200000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c200000 0x200>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root_clk", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@4c200200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c200200 0x200>; - #index-cells = <1>; - }; - }; -}; diff --git a/arch/arm/dts/imx943-evk-u-boot.dtsi b/arch/arm/dts/imx943-evk-u-boot.dtsi index 247a7ed6838..3b3619d2232 100644 --- a/arch/arm/dts/imx943-evk-u-boot.dtsi +++ b/arch/arm/dts/imx943-evk-u-boot.dtsi @@ -153,10 +153,6 @@ bootph-pre-ram; }; -&wdog3 { - status = "disabled"; -}; - &xspi1 { bootph-pre-ram; pinctrl-names = "default"; diff --git a/arch/arm/dts/imx943-u-boot.dtsi b/arch/arm/dts/imx943-u-boot.dtsi index 3457442a3b0..74481aeefb5 100644 --- a/arch/arm/dts/imx943-u-boot.dtsi +++ b/arch/arm/dts/imx943-u-boot.dtsi @@ -159,6 +159,21 @@ }; }; +&aips4 { + bootph-all; + + wdog4: watchdog@49230000 { + compatible = "fsl,imx94-wdt", "fsl,imx93-wdt"; + reg = <0x49230000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; + timeout-sec = <40>; + fsl,ext-reset-output; + status = "disabled"; + bootph-all; + }; +}; + &clk_ext1 { bootph-all; }; @@ -339,12 +354,6 @@ }; }; - netc_timer0: ethernet@0,1 { - compatible = "pci1131,ee02"; - reg = <0x100 0 0 0 0>; - status = "disabled"; - }; - netc_switch: ethernet-switch@0,2 { compatible = "pci1131,eef2", "nxp,imx943-netc-switch"; reg = <0x200 0 0 0 0>; @@ -408,12 +417,6 @@ status = "disabled"; }; - netc_timer1: ethernet@0,1 { - compatible = "pci1131,ee02"; - reg = <0x10100 0 0 0 0>; - status = "disabled"; - }; - enetc1: ethernet@8,0 { compatible = "pci1131,e101"; reg = <0x14000 0 0 0 0>; @@ -426,12 +429,6 @@ status = "disabled"; }; - netc_timer2: ethernet@10,1 { - compatible = "pci1131,ee02"; - reg = <0x18100 0 0 0 0>; - status = "disabled"; - }; - netc_emdio: mdio@18,0 { compatible = "pci1131,ee00"; reg = <0x1c000 0 0 0 0>; @@ -460,3 +457,7 @@ &sram0 { bootph-all; }; + +&wdog3 { + bootph-all; +}; diff --git a/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi b/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi index 514dd729be9..34b4073ff35 100644 --- a/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi +++ b/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi @@ -44,10 +44,6 @@ bootph-pre-ram; }; -&wdog3 { - status = "disabled"; -}; - &pinctrl_uart1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi index 8b59831b7ca..1083d863c4d 100644 --- a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi +++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi @@ -28,10 +28,6 @@ bootph-pre-ram; }; -&wdog3 { - status = "disabled"; -}; - &pinctrl_uart1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi new file mode 100644 index 00000000000..92ec0d3efa3 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) Toradex */ + +#include "imx95-u-boot.dtsi" + +/ { + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&usb3 { + bootph-pre-ram; +}; + +&usb3_dwc3 { + bootph-pre-ram; + compatible = "fsl,imx95a-dwc3", "fsl,imx8mq-dwc3", "snps,dwc3"; +}; + +&usdhc1 { + bootph-pre-ram; +}; + diff --git a/arch/arm/dts/imx95-aquila-dev.dts b/arch/arm/dts/imx95-aquila-dev.dts new file mode 100644 index 00000000000..3df17700b63 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/aquila-development-board-kit + */ + +/dts-v1/; + +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "imx95-aquila.dtsi" + +/ { + model = "Aquila iMX95 on Aquila Development Board"; + compatible = "toradex,aquila-imx95-dev", + "toradex,aquila-imx95", + "fsl,imx95"; + + aliases { + eeprom1 = &carrier_eeprom; + }; + + dp_1_connector: dp0-connector { + compatible = "dp-connector"; + dp-pwr-supply = <®_dp_3p3v>; + type = "full-size"; + + port { + dp_1_connector_in: endpoint { + remote-endpoint = <&dsi2dp_out>; + }; + }; + }; + + reg_carrier_1p8v: regulator-carrier-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier 1V8"; + }; + + reg_dp_3p3v: regulator-dp-3p3v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_21_dp>; + /* Aquila GPIO_21_DP */ + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "DP_3V3"; + startup-delay-us = <10000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "aquila-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Digital Mic"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Digital Mic", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + status = "okay"; +}; + +/* Aquila CTRL_WAKE1_MICO# */ +&aquila_key_wake { + status = "okay"; +}; + +&dsi2dp_out { + remote-endpoint = <&dp_1_connector_in>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + status = "okay"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + status = "okay"; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + status = "okay"; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-0 = <&pinctrl_flexspi1_4bit>, + <&pinctrl_qspi_cs1>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_8>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + cooling-levels = <255>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_mclk>; + clocks = <&scmi_clk IMX95_CLK_SAI2>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_carrier_1p8v>; + CPVDD-supply = <®_carrier_1p8v>; + DBVDD-supply = <®_carrier_1p8v>; + DCVDD-supply = <®_carrier_1p8v>; + MICVDD-supply = <®_carrier_1p8v>; + wlf,drc-cfg-names = "default", "peaklimiter"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + wlf,in1r-as-dmicdat2; + }; + + /* Current measurement into module VCC */ + hwmon@41 { + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* USB-C OTG (TCPC USB PD PHY) */ + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb1_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb1_con_ss>; + }; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_2 */ +&i3c2 { + status = "okay"; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + status = "okay"; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + status = "okay"; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pin #4 and #6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pin #52 and #54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + status = "okay"; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + status = "okay"; +}; + +/* Aquila UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Aquila UART_1 */ +&lpuart3 { + status = "okay"; +}; + +/* Aquila UART_2 as RS485 */ +&lpuart7 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Aquila PWM_1 */ +&tpm3 { + status = "okay"; +}; + +/* Aquila PWM_2 */ +&tpm6 { + status = "okay"; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + status = "okay"; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + status = "okay"; +}; + +/* Aquila USB_1 */ +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + + port { + usb1_con_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + + status = "okay"; + + port { + usb1_con_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +/* Aquila SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx95-aquila.dtsi b/arch/arm/dts/imx95-aquila.dtsi new file mode 100644 index 00000000000..69dc962a24a --- /dev/null +++ b/arch/arm/dts/imx95-aquila.dtsi @@ -0,0 +1,1160 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + */ + +#include <dt-bindings/net/ti-dp83867.h> +#include "imx95.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + can3 = &flexcan4; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + i2c0 = &lpi2c3; + i2c1 = &lpi2c2; + i2c2 = &i3c2; + i2c3 = &lpi2c8; + i2c4 = &lpi2c4; + i2c6 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart3; + serial1 = &lpuart7; + serial2 = &lpuart1; + serial3 = &lpuart2; + usb0 = &usb3; + usb1 = &usb2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aquila_key_wake: gpio-key-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + key-wakeup { + /* Aquila CTRL_WAKE1_MICO# */ + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + label = "Wake Up"; + wakeup-source; + linux,code = <KEY_WAKEUP>; + }; + }; + + clk_dsi2dp_refclk: clock-dsi2dp-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_dsi2dp_refclk_en: clock-dsi2dp-refclk-en { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_dp_clk_en>; + clocks = <&clk_dsi2dp_refclk>; + #clock-cells = <0>; + /* CTRL_DP_CLK_EN */ + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + clk_serdes_eth_ref: clock-serdes-eth-ref { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + /* CTRL_ETH_REF_CLK_STBY */ + enable-gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_LOW>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + reg_dp_1p2v: regulator-dp-1p2v { + compatible = "regulator-fixed"; + /* CTRL_DP_BRIDGE_EN */ + gpios = <&som_gpio_expander_0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DP"; + vin-supply = <®_1p8v>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_1_EN */ + gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_2_EN */ + gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_H_EN"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Aquila SD_1_PWR_EN */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + /* PMIC_SD_1_VSEL */ + gpios = <&som_gpio_expander_1 9 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PMIC_SD_1_VSEL"; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan4>; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1_8bit>, + <&pinctrl_qspi_cs1>; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_C24", /* 10 */ + "", + "AQUILA_B17", + "CTRL_GPIO_EXP_INT#", + "AQUILA_B18"; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "AQUILA_B42", + "", + "AQUILA_B43"; +}; + +&gpio3 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_A11", + "", /* 20 */ + "AQUILA_B57", + "AQUILA_B19"; +}; + +&gpio4 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "AQUILA_C22", + "AQUILA_C21", + "AQUILA_C20", + "", /* 20 */ + "", + "", + "AQUILA_C23", + "AQUILA_D23", + "AQUILA_D24", + "", + "AQUILA_D25"; +}; + +&gpio5 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "AQUILA_B44", + "AQUILA_B45"; +}; + +/* Aquila I2C_2 */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <100000>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* On-module I2C - I2C_SOM */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>, <&pinctrl_ctrl_gpio_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>, <&pinctrl_ctrl_gpio_exp_int>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + status = "okay"; + + som_gpio_expander_0: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C38", /* 0 */ + "PCIE_2_RESET#", + "AQUILA_B77", + "USB_2_H_EN", + "BT_DISABLE#", + "WIFI_DISABLE#", + "CTRL_ETH_REF_CLK_STBY", + "CTRL_DP_BRIDGE_EN"; + }; + + som_gpio_expander_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C1", /* 0 */ + "AQUILA_C2", + "AQUILA_C3", + "AQUILA_C4", + "AQUILA_C36", + "AQUILA_B74", + "AQUILA_B75", + "USB_2_H_OC#", + "AQUILA_B81", + "PMIC_SD_1_VSEL", + "ETH_1_INT#", /* 10 */ + "CTRL_TPM_INT#", + "SPI_2_CS2_TPM", + "PCIE_WAKE_WIFI#", + "WIFI_WAKE_BT", + "WIFI_WAKEUP_HOST"; + }; + + som_dsi2dp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clocks = <&clk_dsi2dp_refclk_en>; + clock-names = "refclk"; + vcc-supply = <®_dp_1p2v>; + vcca-supply = <®_dp_1p2v>; + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_out: endpoint { + data-lanes = <3 2 1 0>; + }; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila SPI_2 */ +&lpspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi4>; + cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, + <&som_gpio_expander_1 12 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi4's per-clock (2x the max speed) is 24 MHz. + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Aquila UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Aquila UART_1 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; +}; + +/* Aquila UART_2 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +/* Aquila ETH_2_XGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_timer { + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpios = <&som_gpio_expander_0 0 GPIO_ACTIVE_LOW>; +}; + +/* On-module Wi-Fi or Aquila PCIE_2 */ +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI2>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = <KEY_POWER>; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Aquila PWM_1 */ +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +/* Aquila PWM_2 */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_dsi>, <&pinctrl_pwm4_dp>; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; +}; + +/* Aquila USB_1 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; +}; + +&usb3_phy { + vbus-supply = <®_usb1_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Aquila SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_sd1_cd_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_sd1_cd_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* Aquila CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e>; /* Aquila D6 */ + }; + + pinctrl_ctrl_dp_clk_en: dpclkengrp { + fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x11e>; /* CTRL_DP_CLK_EN */ + }; + + /* Aquila ETH_2_XGMII_MDIO */ + pinctrl_emdio: emdiogrp { + fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e>, /* Aquila B90 */ + <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e>; /* Aquila B89 */ + }; + + /* Aquila ETH_1 */ + pinctrl_enetc0: enetc0grp { + fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ + <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ + <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ + <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ + <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ + <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ + <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ + <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ + <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ + <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ + <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ + <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ + }; + + /* Aquila CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* Aquila B48 */ + <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* Aquila B49 */ + }; + + /* Aquila CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* Aquila B50 */ + <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* Aquila B51 */ + }; + + /* Aquila CAN_3 */ + pinctrl_flexcan3: flexcan3grp { + fsl,pins = <IMX95_PAD_CCM_CLKO3__CAN3_TX 0x39e>, /* Aquila B53 */ + <IMX95_PAD_CCM_CLKO4__CAN3_RX 0x39e>; /* Aquila B54 */ + }; + + /* Aquila CAN_4 */ + pinctrl_flexcan4: flexcan4grp { + fsl,pins = <IMX95_PAD_GPIO_IO04__CAN4_TX 0x39e>, /* Aquila B55 */ + <IMX95_PAD_GPIO_IO05__CAN4_RX 0x39e>; /* Aquila B56 */ + }; + + /* Aquila QSPI_1 (4 bit) */ + pinctrl_flexspi1_4bit: flexspi14bitgrp { + fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */ + <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */ + <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */ + <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */ + <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */ + <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */ + }; + + /* Aquila QSPI_1 (8 bit) */ + pinctrl_flexspi1_8bit: flexspi18bitgrp { + fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */ + <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */ + <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */ + <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */ + <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */ + <IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe>, /* Aquila B70 */ + <IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe>, /* Aquila B71 */ + <IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe>, /* Aquila B72 */ + <IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe>, /* Aquila B73 */ + <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */ + }; + + /* Aquila GPIO_01 */ + pinctrl_gpio_1: gpio1grp { + fsl,pins = <IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x31e>; /* Aquila D23 */ + }; + + /* Aquila GPIO_02 */ + pinctrl_gpio_2: gpio2grp { + fsl,pins = <IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x31e>; /* Aquila D24 */ + }; + + /* Aquila GPIO_03 */ + pinctrl_gpio_3: gpio3grp { + fsl,pins = <IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x31e>; /* Aquila D25 */ + }; + + /* Aquila GPIO_04 */ + pinctrl_gpio_4: gpio4grp { + fsl,pins = <IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x31e>; /* Aquila C20 */ + }; + + /* Aquila GPIO_05 */ + pinctrl_gpio_5: gpio5grp { + fsl,pins = <IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x31e>; /* Aquila C21 */ + }; + + /* Aquila GPIO_06 */ + pinctrl_gpio_6: gpio6grp { + fsl,pins = <IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x31e>; /* Aquila C22 */ + }; + + /* Aquila GPIO_07 */ + pinctrl_gpio_7: gpio7grp { + fsl,pins = <IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x31e>; /* Aquila C23 */ + }; + + /* Aquila GPIO_08 */ + pinctrl_gpio_8: gpio8grp { + fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* Aquila C24 */ + }; + + /* Aquila GPIO_09_CSI_1 */ + pinctrl_gpio_9_csi_1: gpio9csi1grp { + fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* Aquila B17 */ + }; + + /* Aquila GPIO_10_CSI_1 */ + pinctrl_gpio_10_csi_1: gpio10csi1grp { + fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* Aquila B18 */ + }; + + /* Aquila GPIO_11_CSI_1 */ + pinctrl_gpio_11_csi_1: gpio11csi1grp { + fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x31e>; /* Aquila A11*/ + }; + + /* Aquila GPIO_12_CSI_1 */ + pinctrl_gpio_12_csi_1: gpio12csi1grp { + fsl,pins = <IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x31e>; /* Aquila B19 */ + }; + + /* Aquila GPIO_17_DSI_1 */ + pinctrl_gpio_17_dsi_1: gpio17dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x31e>; /* Aquila B42 */ + }; + + /* Aquila GPIO_18_DSI_1 */ + pinctrl_gpio_18_dsi_1: gpio18dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x31e>; /* Aquila B43 */ + }; + + /* Aquila GPIO_19_DSI_1 */ + pinctrl_gpio_19_dsi_1: gpio19dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e>; /* Aquila B44 */ + }; + + /* Aquila GPIO_20_DSI_1 */ + pinctrl_gpio_20_dsi_1: gpio20dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e>; /* Aquila B45 */ + }; + + /* Aquila GPIO_21_DP */ + pinctrl_gpio_21_dp: gpio21dpgrp { + fsl,pins = <IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x31e>; /* Aquila B57 */ + }; + + pinctrl_ctrl_gpio_exp_int: gpioexpintgrp { + fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* CTRL_GPIO_EXP_INT# */ + }; + + /* Aquila I2C_2 */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* Aquila C17 */ + <IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* Aquila C16 */ + }; + + /* Aquila I2C_1 as GPIOs */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* Aquila D8 */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* Aquila D7 */ + }; + + /* Aquila I2C_1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* Aquila D8 */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* Aquila D7 */ + }; + + /* On-module I2C as GPIOs */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* I2C_SOM_SDA */ + <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* I2C_SOM_SCL */ + }; + + /* On-module I2C */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* I2C_SOM_SDA */ + <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* I2C_SOM_SCL */ + }; + + /* Aquila I2C_4_CSI1 as GPIO */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>, /* Aquila A12 */ + <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>; /* Aquila A13 */ + }; + + /* Aquila I2C_4_CSI1 */ + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>, /* Aquila A12 */ + <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>; /* Aquila A13 */ + }; + + /* Aquila I2C_6 as GPIO */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* Aquila C18 */ + <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* Aquila C19 */ + }; + + /* Aquila I2C_6 */ + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* Aquila C18 */ + <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* Aquila C19 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 as GPIO */ + pinctrl_lpi2c8_gpio: lpi2c8gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x40001b9e>, /* Aquila C5/B40 */ + <IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x40001b9e>; /* Aquila C6/B41 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 */ + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = <IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x40001b9e>, /* Aquila C5/B40 */ + <IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x40001b9e>; /* Aquila C6/B41 */ + }; + + /* Aquila SPI_2 */ + pinctrl_lpspi4: lpspi4grp { + fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* Aquila D16 */ + <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* Aquila D15 */ + <IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x3fe>, /* Aquila D17 */ + <IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x3fe>; /* Aquila D14 */ + }; + + /* Aquila SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* Aquila D9 */ + <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* Aquila D10 */ + <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* Aquila D11 */ + <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* Aquila D12 */ + }; + + /* Aquila PCIE_1 */ + pinctrl_pcie0: pcie0grp { + fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* Aquila C37 */ + }; + + /* Aquila PCIE_2 */ + pinctrl_pcie1: pcie1grp { + fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* Aquila C34 */ + }; + + /* Aquila QSPI_1_CS1# */ + pinctrl_qspi_cs1: qspics1grp { + fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>; /* Aquila B66 */ + }; + + /* Aquila QSPI_1_CS2# as GPIO */ + pinctrl_qspi_cs2_gpio: qspics2gpiogrp { + fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x3fe>; /* Aquila B62 */ + }; + + /* Aquila I2S_1 */ + pinctrl_sai2: sai2grp { + fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x11e>, /* Aquila B21 */ + <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x11e>, /* Aquila B20 */ + <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x11e>, /* Aquila B23 */ + <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x11e>; /* Aquila B22 */ + }; + + pinctrl_sai2_mclk: sai2mclkgrp { + fsl,pins = <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e>; /* Aquila B24 */ + }; + + /* Aquila SD_1_CD# as GPIO */ + pinctrl_sd1_cd_gpio: sd1cdgpiogrp { + fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* Aquila A1 */ + }; + + /* Aquila SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: sd1pwrengpiogrp { + fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* Aquila A6 */ + }; + + /* Aquila PWM_1 */ + pinctrl_pwm1: tpm3ch3grp { + fsl,pins = <IMX95_PAD_GPIO_IO24__TPM3_CH3 0x11e>; /* Aquila C25 */ + }; + + /* Aquila PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: tpm5ch0gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x11e>; /* Aquila B46 */ + }; + + /* Aquila PWM_3_DSI */ + pinctrl_pwm3_dsi: tpm5ch0grp { + fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* Aquila B46 */ + }; + + /* Aquila PWM_4_DP */ + pinctrl_pwm4_dp: tpm5ch3grp { + fsl,pins = <IMX95_PAD_GPIO_IO26__TPM5_CH3 0x11e>; /* Aquila B58 */ + }; + + /* Aquila PWM_2 */ + pinctrl_pwm2: tpm6ch0grp { + fsl,pins = <IMX95_PAD_GPIO_IO08__TPM6_CH0 0x11e>; /* Aquila C26 */ + }; + + /* Aquila UART_3 */ + pinctrl_uart1: uart1grp { + fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* Aquila D20 */ + <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* Aquila D19 */ + }; + + /* Aquila UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>, /* Aquila D22 */ + <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>; /* Aquila D21 */ + }; + + /* Aquila UART_1 */ + pinctrl_uart3: uart3grp { + fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* Aquila B37 */ + <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>, /* Aquila B35 */ + <IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x31e>, /* Aquila B36 */ + <IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x31e>; /* Aquila B38 */ + }; + + /* Aquila UART_2 */ + pinctrl_uart7: uart7grp { + fsl,pins = <IMX95_PAD_GPIO_IO36__LPUART7_TX 0x31e>, /* Aquila B33 */ + <IMX95_PAD_GPIO_IO37__LPUART7_RX 0x31e>, /* Aquila B31 */ + <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* Aquila B32 */ + <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* Aquila B34 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* eMMC_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* eMMC_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* eMMC_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* eMMC_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* eMMC_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* eMMC_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* eMMC_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* eMMC_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* eMMC_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* eMMC_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* eMMC_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* eMMC_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* eMMC_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* eMMC_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* eMMC_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* eMMC_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* eMMC_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* eMMC_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* eMMC_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* eMMC_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* eMMC_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* eMMC_STROBE */ + }; + + /* Aquila SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* Aquila A5 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* Aquila A7 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* Aquila A3 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* Aquila A2 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* Aquila A10 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* Aquila A8 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* Aquila A5 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* Aquila A7 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* Aquila A3 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* Aquila A2 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* Aquila A10 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* Aquila A8 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* Aquila A5 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* Aquila A7 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* Aquila A3 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* Aquila A2 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* Aquila A10 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* Aquila A8 */ + }; +}; diff --git a/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi index 97ce7402e50..e4eda61e5c4 100644 --- a/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi +++ b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi @@ -10,7 +10,6 @@ }; &gpio1 { - reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>; bootph-pre-ram; }; @@ -104,7 +103,3 @@ &usdhc2 { bootph-pre-ram; }; - -&wdog3 { - status = "disabled"; -}; diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi index 6dec159752b..cc67f09ed97 100644 --- a/arch/arm/dts/imx95-u-boot.dtsi +++ b/arch/arm/dts/imx95-u-boot.dtsi @@ -138,6 +138,16 @@ &aips2 { bootph-all; + + wdog4: watchdog@424a0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424a0000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + bootph-all; + }; }; &aips3 { @@ -238,3 +248,7 @@ &scmi_buf1 { bootph-all; }; + +&wdog3 { + bootph-all; +}; diff --git a/arch/arm/dts/imx95-verdin-dev.dtsi b/arch/arm/dts/imx95-verdin-dev.dtsi new file mode 100644 index 00000000000..803480eef47 --- /dev/null +++ b/arch/arm/dts/imx95-verdin-dev.dtsi @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + clocks = <&scmi_clk IMX95_CLK_SAI3>; + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3_mclk>; + #sound-dai-cells = <0>; + }; + + carrier_gpio_expander: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&lpuart7 { + rs485-rts-active-low; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +&netc_emdio { + ethphy2: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin I2S_1 */ +&sai3 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; diff --git a/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi new file mode 100644 index 00000000000..8ab70cf7399 --- /dev/null +++ b/arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) Toradex */ + +#include "imx95-u-boot.dtsi" + +/ { + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-imem} { + filename = "lpddr4x_imem_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-dmem} { + filename = "lpddr4x_dmem_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-imem-qb} { + filename = "lpddr4x_imem_qb_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-dmem-qb} { + filename = "lpddr4x_dmem_qb_v202409.bin"; +}; + +&gpio1 { + bootph-pre-ram; + + ctrl-sleep-moci-hog { + bootph-pre-ram; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <14 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + }; +}; + +&som_gpio_expander { + bootph-pre-ram; +}; + +&lpi2c2 { + bootph-pre-ram; +}; + +&lpuart1 { + clocks = <&scmi_clk IMX95_CLK_LPUART1>, <&scmi_clk IMX95_CLK_LPUART1>; + clock-names = "ipg", "per"; + bootph-pre-ram; +}; + +&pinctrl_ctrl_sleep_moci { + bootph-pre-ram; +}; + +&pinctrl_io_exp_int { + bootph-pre-ram; +}; + +&pinctrl_lpi2c2 { + bootph-pre-ram; +}; + +&pinctrl_lpi2c2_gpio { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&som_gpio_expander { + bootph-pre-ram; +}; + +&usb2 { + /delete-property/power-domains; +}; + +&usb3 { + status = "disabled"; +}; + +&usb3_dwc3 { + status = "disabled"; +}; + +&usb_recov_ctrl { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx95-verdin-wifi-dev.dts b/arch/arm/dts/imx95-verdin-wifi-dev.dts new file mode 100644 index 00000000000..345d3724702 --- /dev/null +++ b/arch/arm/dts/imx95-verdin-wifi-dev.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Verdin Development Board"; + compatible = "toradex,verdin-imx95-wifi-dev", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm/dts/imx95-verdin-wifi.dtsi b/arch/arm/dts/imx95-verdin-wifi.dtsi new file mode 100644 index 00000000000..256c9ed0460 --- /dev/null +++ b/arch/arm/dts/imx95-verdin-wifi.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + /* PMIC_EN_WIFI */ + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PDn_MAYA-W260"; + startup-delay-us = <2000>; + }; +}; + +/* On-module Bluetooth */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + uart-has-rtscts; + + status = "okay"; + + som_bt: bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_wifi_en>; + + status = "okay"; +}; diff --git a/arch/arm/dts/imx95-verdin.dtsi b/arch/arm/dts/imx95-verdin.dtsi new file mode 100644 index 00000000000..29cd4b91a16 --- /dev/null +++ b/arch/arm/dts/imx95-verdin.dtsi @@ -0,0 +1,1172 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include "imx95.dtsi" +#include "imx95-u-boot.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + i2c0 = &lpi2c2; + i2c1 = &lpi2c4; + i2c2 = &lpi2c3; + i2c3 = &i3c2; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart7; + serial1 = &lpuart8; + serial2 = &lpuart1; + serial3 = &lpuart2; + serial4 = &lpuart6; + usb0 = &usb2; + usb1 = &usb3; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + /* Verdin USB_1_ID (SODIMM 161) */ + id-gpios = <&som_gpio_expander 5 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb1_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_id>; + }; + }; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + verdin_key_wakeup: key-wakeup { + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Verdin USB_1_EN (SODIMM 155) */ + gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Verdin USB_2_EN (SODIMM 185) */ + gpios = <&som_gpio_expander 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_EN"; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vsel>; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + states = <1800000 0x1>, + <3300000 0x0>; + regulator-name = "PMIC_SD2_VSEL"; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + cm7: remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu7 0 1 + &mu7 1 1 + &mu7 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; +}; + +&gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153", + "SODIMM_20", + "SODIMM_22", + "SODIMM_252", /* 10 */ + "", + "SODIMM_189", + "IO_EXP_INT", + "SODIMM_256", + ""; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = + "SODIMM_206", /* 0 */ + "SODIMM_198", + "SODIMM_200", + "SODIMM_196", + "", + "SODIMM_15", + "SODIMM_16", + "", + "SODIMM_131", + "SODIMM_129", + "SODIMM_135", /* 10 */ + "SODIMM_133", + "SODIMM_139", + "SODIMM_137", + "SODIMM_143", + "SODIMM_141", + "SODIMM_30", + "SODIMM_38", + "SODIMM_208", + "SODIMM_19", + "SODIMM_36", /* 20 */ + "SODIMM_34", + "SODIMM_93", + "SODIMM_95", + "SODIMM_210", + "SODIMM_24", + "SODIMM_32", + "SODIMM_26", + "SODIMM_53", + "SODIMM_55", + "SODIMM_12", /* 30 */ + "SODIMM_14"; +}; + +&gpio3 { + gpio-line-names = + "SODIMM_84", /* 0 */ + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72", + "SODIMM_76", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "PMIC_SD2_VSEL", + "", /* 20 */ + "", + "", + "", + "", + "", + "SODIMM_91", + "SODIMM_218", + "", + "", + "", /* 30 */ + ""; +}; + +&gpio4 { + gpio-line-names = + "SODIMM_59", /* 0 */ + "SODIMM_57", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "SODIMM_193", + "SODIMM_191", + "SODIMM_215", + "SODIMM_217", + "SODIMM_219", + "SODIMM_221", + "SODIMM_211", /* 20 */ + "SODIMM_213", + "SODIMM_199", + "SODIMM_197", + "SODIMM_201", + "SODIMM_203", + "SODIMM_205", + "SODIMM_207", + "SODIMM_216", + "SODIMM_202"; +}; + +&gpio5 { + gpio-line-names = + "SODIMM_56", /* 0 */ + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "SODIMM_46", + "SODIMM_44", + "SODIMM_42", + "SODIMM_48", + "SODIMM_66", + "SODIMM_52", + "SODIMM_54", /* 10 */ + "SODIMM_64", + "SODIMM_212", + "", + "", + "", + "", + ""; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <400000>; +}; + +/* CTRL_I2C (On-module I2C) */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>, <&pinctrl_io_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>, <&pinctrl_io_exp_int>; + clock-frequency = <400000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; + + status = "okay"; + + som_gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "SODIMM_220", /* 0 */ + "SODIMM_222", + "SODIMM_17", + "SODIMM_21", + "SODIMM_244", + "SODIMM_161", + "SODIMM_157", + "SODIMM_155", + "SODIMM_185", + "SODIMM_187", + "USB_RECOV_CTRL#", /* 10 */ + "ENET1_INT#", + "TPM_INT#", + "TPM_CS#", + "", + ""; + + /* + * Switch USB to default position: + * - SoC USB2 -> Verdin USB_1 + * - SoC USB1 -> Verdin USB_2 + * Reset configuration: + * - SoC USB1 -> Verdin USB_1 (USB recovery) + * - SoC USB2 not connected + */ + usb_recov_ctrl: usb-recov-ctrl-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "USB_RECOV_CTRL#"; + output-high; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_spi1_cs>; + cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, + <&som_gpio_expander 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi6's per-clock (twice the max speed) is 24 MHz + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Verdin UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Verdin UART_1 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>, <&pinctrl_uart8_cts>, <&pinctrl_uart8_rts>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_bus0 { + msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; //NETC Timer + iommu-map = <0x0 &smmu 0x20 0x1>, + <0x10 &smmu 0x21 0x1>, + <0x20 &smmu 0x22 0x1>, + <0x40 &smmu 0x23 0x1>, + <0x50 &smmu 0x25 0x1>, + <0x60 &smmu 0x26 0x1>, + <0x80 &smmu 0x24 0x1>, + <0xc0 &smmu 0x27 0x1>; +}; + +/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_LOW>; +}; + +/* Verdin I2S_1 */ +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = <KEY_POWER>; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Verdin PWM_1 */ +&tpm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm4>; +}; + +/* Verdin PWM_2 */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; +}; + +/* Verdin USB_1 */ +&usb2 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; + vbus-supply = <®_usb1_vbus>; + + port { + usb1_id: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "host"; +}; + +&usb3_phy { + vbus-supply = <®_usb2_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* On-module Bluetooth on WB SKUs, module-specific UART otherwise */ + pinctrl_bt_uart: btuartgrp { + fsl,pins = <IMX95_PAD_GPIO_IO04__LPUART6_TX 0x31e>, /* WiFi_UART_SoC_TXD */ + <IMX95_PAD_GPIO_IO33__LPUART6_RX 0x31e>, /* WiFi_UART_SoC_RXD */ + <IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x31e>, /* WiFi_UART_SoC_CTS */ + <IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e>; /* WiFi_UART_SoC_RTS */ + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_csi1_mclk: csi1mclkgrp { + fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SODIMM 91 */ + }; + + /* Verdin CTRL_SLEEP_MOCI# */ + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x51e>; /* SODIMM 256 */ + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* SODIMM 252 */ + }; + + /* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ + pinctrl_emdio: emdiogrp { + fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* ENET2_MDC, SODIMM 193 */ + <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* ENET2_MDIO, SODIMM 191 */ + }; + + /* Verdin ETH_1 (On-module PHY) */ + pinctrl_enetc0: enetc0grp { + fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ + <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ + <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ + <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ + <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ + <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ + <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ + <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ + <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ + <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ + <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ + <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ + }; + + /* Verdin ETH_2_RGMII */ + pinctrl_enetc1: enetc1grp { + fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */ + <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */ + <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */ + <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */ + <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */ + <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */ + <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */ + <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */ + <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */ + <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */ + <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */ + <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */ + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: eth2rgmiiintgrp { + fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* SODIMM 189 */ + }; + + /* Verdin CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SODIMM 20 */ + <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SODIMM 22 */ + }; + + /* Verdin CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SODIMM 24 */ + <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SODIMM 26 */ + }; + + /* Verdin QSPI_1 */ + pinctrl_flexspi1: flexspi1grp { + fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>, /* SODIMM 54 */ + <IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x3fe>, /* SODIMM 64 */ + <IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x3fe>, /* SODIMM 52 */ + <IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x3fe>, /* SODIMM 56 */ + <IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x3fe>, /* SODIMM 58 */ + <IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x3fe>, /* SODIMM 60 */ + <IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x3fe>, /* SODIMM 62 */ + <IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x3fe>; /* SODIMM 66 */ + }; + + /* Verdin GPIO_1 */ + pinctrl_gpio1: gpio1grp { + fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x51e>; /* SODIMM 206 */ + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio2: gpio2grp { + fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x51e>; /* SODIMM 208 */ + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio3: gpio3grp { + fsl,pins = <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x51e>; /* SODIMM 210 */ + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = <IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x51e>; /* SODIMM 212 */ + }; + + /* Verdin GPIO_5_CSI */ + pinctrl_gpio5: gpio5grp { + fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x51e>; /* SODIMM 216 */ + }; + + /* Verdin GPIO_6_CSI */ + pinctrl_gpio6: gpio6grp { + fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e>; /* SODIMM 218 */ + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_bclk_gpio: i2s2bclkgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x51e>; /* SODIMM 42 */ + }; + + /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_d_in_gpio: i2s2dingpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x31e>; /* SODIMM 48 */ + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_d_out_gpio: i2s2doutgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x51e>; /* SODIMM 46 */ + }; + + /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_sync_gpio: i2s2syncgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x51e>; /* SODIMM 44 */ + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* SODIMM 59 */ + <IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* SODIMM 57 */ + }; + + pinctrl_io_exp_int: ioexpintgrp { + fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* IO_EXP_INT */ + }; + + /* CTRL_I2C (On-module I2C) */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* CTRL_I2C_SCL */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* CTRL_I2C_SDA */ + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* CTRL_I2C_SCL */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* CTRL_I2C_SDA */ + }; + + /* Verdin I2C_2_DSI */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SODIMM 53 */ + <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SODIMM 55 */ + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SODIMM 53 */ + <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SODIMM 55 */ + }; + + /* Verdin I2C_1 */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* SODIMM 14 */ + <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* SODIMM 12 */ + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* SODIMM 14 */ + <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* SODIMM 12 */ + }; + + /* Verdin I2C_4_CSI */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SODIMM 93 */ + <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SODIMM 95 */ + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SODIMM 93 */ + <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SODIMM 95 */ + }; + + /* Verdin SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SODIMM 198 */ + <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SODIMM 200 */ + <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SODIMM 196 */ + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: qspi1clkgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x11e>; /* SODIMM 52 */ + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: qspi1cs2gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x11e>; /* SODIMM 64 */ + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: qspi1csgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x11e>; /* SODIMM 54 */ + }; + + /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_dqs_gpio: qspi1dqsgpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x11e>; /* SODIMM 66 */ + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: qspi1io0gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x119e>; /* SODIMM 56 */ + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: qspi1io1gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x119e>; /* SODIMM 58 */ + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: qspi1io2gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x11e>; /* SODIMM 60 */ + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: qspi1io3gpiogrp { + fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x11e>; /* SODIMM 62 */ + }; + + /* Verdin I2S_1 */ + pinctrl_sai3: sai3grp { + fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SODIMM 30 */ + <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SODIMM 36 */ + <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SODIMM 34 */ + <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SODIMM 32 */ + }; + + /* Verdin I2S_1_MCLK */ + pinctrl_sai3_mclk: sai3mclkgrp { + fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SODIMM 38 */ + }; + + /* Verdin I2S_2 */ + pinctrl_sai5: sai5grp { + fsl,pins = <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SODIMM 46 */ + <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>, /* SODIMM 44 */ + <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SODIMM 42 */ + <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>; /* SODIMM 48 */ + }; + + /* Verdin SPI_1_CS */ + pinctrl_spi1_cs: spi1csgrp { + fsl,pins = <IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x3fe>; /* SODIMM 202 */ + }; + + /* Verdin PWM_1 */ + pinctrl_tpm4: tpm4grp { + fsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0 0x11e>; /* SODIMM 15 */ + }; + + /* Verdin PWM_2 */ + pinctrl_tpm5: tpm5grp { + fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SODIMM 16 */ + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_tpm6_gpio: tpm6gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x51e>; /* SODIMM 19 */ + }; + + /* Verdin PWM_3_DSI */ + pinctrl_tpm6: tpm6grp { + fsl,pins = <IMX95_PAD_GPIO_IO19__TPM6_CH2 0x11e>; /* SODIMM 19 */ + }; + + /* Verdin UART_3, used as the Linux Console */ + pinctrl_uart1: uart1grp { + fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>, /* SODIMM 147 */ + <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>; /* SODIMM 149 */ + }; + + /* Verdin UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SODIMM 151 */ + <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SODIMM 153 */ + }; + + /* Verdin UART_1 */ + pinctrl_uart7: uart7grp { + fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX 0x31e>, /* SODIMM 131 */ + <IMX95_PAD_GPIO_IO09__LPUART7_RX 0x31e>, /* SODIMM 129 */ + <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* SODIMM 135 */ + <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* SODIMM 133 */ + }; + + /* Verdin UART_2 CTS */ + pinctrl_uart8_cts: uart8ctsgrp { + fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x31e>; /* SODIMM 143 */ + }; + + /* Verdin UART_2 RTS */ + pinctrl_uart8_rts: uart8rtsgrp { + fsl,pins = <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x31e>; /* SODIMM 141 */ + }; + + /* Verdin UART_2 RX/TX */ + pinctrl_uart8: uart8grp { + fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>, /* SODIMM 139 */ + <IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e>; /* SODIMM 137 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */ + }; + + /* Verdin SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SODIMM 78 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SODIMM 74 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SODIMM 80 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SODIMM 82 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SODIMM 70 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SODIMM 78 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SODIMM 74 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SODIMM 80 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SODIMM 82 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SODIMM 70 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SODIMM 78 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SODIMM 74 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SODIMM 80 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SODIMM 82 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SODIMM 70 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SODIMM 72 */ + }; + + /* Verdin SD_1_CD# */ + pinctrl_usdhc2_cd: usdhc2-cdgrp { + fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SODIMM 84 */ + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { + fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SODIMM 76 */ + }; + + pinctrl_usdhc2_vsel: usdhc2-vselgrp { + fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */ + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */ + <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */ + <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */ + <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */ + <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */ + <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */ + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */ + <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */ + <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */ + <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */ + <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */ + <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */ + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x51e>; /* PMIC_EN_WIFI */ + }; +}; diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi index e977014992e..80399e6ff2a 100644 --- a/arch/arm/dts/imx952-u-boot.dtsi +++ b/arch/arm/dts/imx952-u-boot.dtsi @@ -115,6 +115,16 @@ &aips2 { bootph-all; + + wdog4: watchdog@420c0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x420c0000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + bootph-all; + }; }; &aips3 { @@ -171,12 +181,7 @@ bootph-all; }; -&gpio1 { - reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>; -}; - &gpio2 { - reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>; bootph-pre-ram; /* * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2 @@ -186,17 +191,14 @@ }; &gpio3 { - reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>; bootph-pre-ram; }; &gpio4 { - reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>; bootph-pre-ram; }; &gpio5 { - reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>; bootph-pre-ram; }; @@ -237,6 +239,10 @@ bootph-pre-ram; }; +&wdog3 { + bootph-all; +}; + &scmi_iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; diff --git a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi index 9e4af4d9f72..36640f31d61 100644 --- a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi +++ b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi @@ -12,6 +12,9 @@ reg = <0x0 0x80000000 0x0 0x20000000>; }; + chosen { + stdout-path = "serial0:115200n8"; + }; }; &sdhc { diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi index 5e777a1f305..6d57a5d9ffa 100644 --- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi @@ -9,6 +9,11 @@ #include "k3-binman.dtsi" #ifdef CONFIG_TARGET_PHYCORE_AM62X_R5 + +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + &binman { tiboot3-am62x-hs-phycore-som.bin { filename = "tiboot3-am62x-hs-phycore-som.bin"; @@ -309,13 +314,24 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - conf-0 { - description = "k3-am625-phyboard-lyra-rdk"; + conf-hs-fs { + description = "k3-am625-phyboard-lyra-rdk-hs-fs"; firmware = "atf"; - loadables = "tee", "tifsstub-hs", "tifsstub-fs", - "tifsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-fs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am625-phyboard-lyra-rdk-hs-se"; + firmware = "atf"; + loadables = "tee", "tifsstub-hs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-gp { + description = "k3-am625-phyboard-lyra-rdk-gp"; + firmware = "atf"; + loadables = "tee", "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -547,13 +563,24 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - conf-0 { - description = "k3-am625-phyboard-lyra-rdk"; + conf-hs-fs { + description = "k3-am625-phyboard-lyra-rdk-hs-fs"; + firmware = "atf"; + loadables = "tee", "tifsstub-fs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am625-phyboard-lyra-rdk-hs-se"; + firmware = "atf"; + loadables = "tee", "tifsstub-hs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-gp { + description = "k3-am625-phyboard-lyra-rdk-gp"; firmware = "atf"; - loadables = "tee", "tifsstub-hs", "tifsstub-fs", - "tifsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index ba29a047406..1717621a850 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -263,12 +263,21 @@ }; configurations { - default = "conf-0"; - conf-0 { - description = "k3-am625-sk-falcon"; + default = "conf-hs-fs"; + conf-hs-fs { + description = "k3-am625-sk-falcon-hs-fs"; + firmware = "atf"; + loadables = "tee", "tifsstub-fs", "dm"; + }; + conf-hs-se { + description = "k3-am625-sk-falcon-hs-se"; + firmware = "atf"; + loadables = "tee", "tifsstub-hs", "dm"; + }; + conf-gp { + description = "k3-am625-sk-falcon-gp"; firmware = "atf"; - loadables = "tee", "tifsstub-hs", "tifsstub-fs", - "tifsstub-gp", "dm"; + loadables = "tee", "tifsstub-gp", "dm"; }; }; }; @@ -376,13 +385,24 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - conf-0 { - description = "k3-am625-sk"; + conf-hs-fs { + description = "k3-am625-sk-hs-fs"; + firmware = "atf"; + loadables = "tee", "tifsstub-fs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am625-sk-hs-se"; firmware = "atf"; - loadables = "tee", "tifsstub-hs", "tifsstub-fs", - "tifsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-gp { + description = "k3-am625-sk-gp"; + firmware = "atf"; + loadables = "tee", "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -497,13 +517,24 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - conf-0 { - description = "k3-am625-sk"; + conf-hs-fs { + description = "k3-am625-sk-hs-fs"; + firmware = "atf"; + loadables = "tee", "tifsstub-fs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am625-sk-hs-se"; + firmware = "atf"; + loadables = "tee", "tifsstub-hs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-gp { + description = "k3-am625-sk-gp"; firmware = "atf"; - loadables = "tee", "tifsstub-hs", "tifsstub-fs", - "tifsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index 7b646629587..35b7f8b256e 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -7,6 +7,10 @@ #ifdef CONFIG_TARGET_VERDIN_AM62_R5 +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + &binman { tiboot3-am62x-hs-verdin.bin { filename = "tiboot3-am62x-hs-verdin.bin"; @@ -295,13 +299,24 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - conf-0 { - description = "k3-am625-verdin-wifi-dev"; + conf-hs-fs { + description = "k3-am625-verdin-wifi-dev-hs-fs"; + firmware = "atf"; + loadables = "tee", "tifsstub-fs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am625-verdin-wifi-dev-hs-se"; + firmware = "atf"; + loadables = "tee", "tifsstub-hs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-gp { + description = "k3-am625-verdin-wifi-dev-gp"; firmware = "atf"; - loadables = "tee", "tifsstub-hs", "tifsstub-fs", - "tifsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -414,13 +429,24 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - conf-0 { - description = "k3-am625-verdin-wifi-dev"; + conf-hs-fs { + description = "k3-am625-verdin-wifi-dev-hs-fs"; + firmware = "atf"; + loadables = "tee", "tifsstub-fs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am625-verdin-wifi-dev-hs-se"; + firmware = "atf"; + loadables = "tee", "tifsstub-hs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-gp { + description = "k3-am625-verdin-wifi-dev-gp"; firmware = "atf"; - loadables = "tee", "tifsstub-hs", "tifsstub-fs", - "tifsstub-gp", "dm", "spl"; + loadables = "tee", "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi index 6f82a40908f..cdc9a100a04 100644 --- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -247,13 +247,18 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - conf-0 { - description = "k3-am62a7-phyboard-lyra-rdk"; + conf-hs-fs { + description = "k3-am62a7-phyboard-lyra-rdk-hs-fs"; + firmware = "atf"; + loadables = "tee", "dm", "spl", "tifsstub-fs"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am62a7-phyboard-lyra-rdk-hs-se"; firmware = "atf"; - loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs"; + loadables = "tee", "dm", "spl", "tifsstub-hs"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 49c90f5855c..6e7deb218e9 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -185,11 +185,16 @@ }; configurations { - default = "conf-0"; - conf-0 { - description = "k3-am62a7-sk-falcon"; + default = "conf-hs-fs"; + conf-hs-fs { + description = "k3-am62a7-sk-falcon-hs-fs"; + firmware = "atf"; + loadables = "tee", "dm", "tifsstub-fs"; + }; + conf-hs-se { + description = "k3-am62a7-sk-falcon-hs-se"; firmware = "atf"; - loadables = "tee", "dm", "tifsstub-hs", "tifsstub-fs"; + loadables = "tee", "dm", "tifsstub-hs"; }; }; }; @@ -284,13 +289,18 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - ti_spl_conf_0: conf-0 { - description = "k3-am62a7-sk"; + ti_spl_conf_0: conf-hs-fs { + description = "k3-am62a7-sk-hs-fs"; + firmware = "atf"; + loadables = "tee", "dm", "spl", "tifsstub-fs"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am62a7-sk-hs-se"; firmware = "atf"; - loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs"; + loadables = "tee", "dm", "spl", "tifsstub-hs"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index cca56b76d69..c56ecad85a6 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -206,11 +206,16 @@ }; configurations { - default = "conf-0"; - conf-0 { - description = "k3-am62p5-sk-falcon"; + default = "conf-hs-fs"; + conf-hs-fs { + description = "k3-am62p5-sk-falcon-hs-fs"; firmware = "atf"; - loadables = "tee", "dm", "tifsstub-hs", "tifsstub-fs"; + loadables = "tee", "dm", "tifsstub-fs"; + }; + conf-hs-se { + description = "k3-am62p5-sk-falcon-hs-se"; + firmware = "atf"; + loadables = "tee", "dm", "tifsstub-hs"; }; }; }; @@ -309,13 +314,18 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - conf-0 { - description = "k3-am62px-sk"; + conf-hs-fs { + description = "k3-am62px-sk-hs-fs"; + firmware = "atf"; + loadables = "tee", "dm", "spl", "tifsstub-fs"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am62px-sk-hs-se"; firmware = "atf"; - loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs"; + loadables = "tee", "dm", "spl", "tifsstub-hs"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi index b46e871ef8a..307cac5ebc7 100644 --- a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi @@ -7,6 +7,10 @@ #if IS_ENABLED(CONFIG_TARGET_VERDIN_AM62P_R5) +&rcfg_yaml_tifs { + config = "tifs-rm-cfg.yaml"; +}; + &binman { tiboot3-am62px-hs-fs-verdin.bin { filename = "tiboot3-am62px-hs-fs-verdin.bin"; @@ -248,13 +252,18 @@ }; configurations { - default = "conf-0"; + default = "conf-hs-fs"; - conf-0 { - description = "k3-am62p5-verdin-wifi-dev"; + conf-hs-fs { + description = "k3-am62p5-verdin-wifi-dev-hs-fs"; + firmware = "atf"; + loadables = "tee", "tifsstub-fs", "dm", "spl"; + fdt = "fdt-0"; + }; + conf-hs-se { + description = "k3-am62p5-verdin-wifi-dev-hs-se"; firmware = "atf"; - loadables = "tee", "tifsstub-hs", "tifsstub-fs", - "dm", "spl"; + loadables = "tee", "tifsstub-hs", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index e3d363a8e39..d1fe7efd006 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -23,3 +23,13 @@ clocks = <&clk_200mhz>; clock-names = "clk_xin"; }; + +&main_uart1_pins_default { + bootph-pre-ram; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + bootph-pre-ram; + status="okay"; +}; diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 27f3e87fb90..19435cd1f5c 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -18,3 +18,13 @@ &serdes_wiz0 { status = "okay"; }; + +&main_uart1_pins_default { + bootph-pre-ram; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + bootph-pre-ram; + status="okay"; +}; diff --git a/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi new file mode 100644 index 00000000000..ea773a2ca4f --- /dev/null +++ b/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi @@ -0,0 +1,4410 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:50:37 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_0 27500000 +#define DDRSS_PLL_FREQUENCY_1 1066500000 +#define DDRSS_PLL_FREQUENCY_2 1066500000 + +#define MULTI_DDR_CFG_INTRLV_GRAN 0 +#define MULTI_DDR_CFG_INTRLV_SIZE 11 +#define MULTI_DDR_CFG_ECC_ENABLE 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 0 +#define MULTI_DDR_CFG_EMIFS_ACTIVE 3 + +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000003 +#define DDR_REG1_SIZE_LSB 0x80000000 + + +#define DDRSS0_CTL_00_DATA 0x00000B00 +#define DDRSS0_CTL_01_DATA 0x00000000 +#define DDRSS0_CTL_02_DATA 0x00000000 +#define DDRSS0_CTL_03_DATA 0x00000000 +#define DDRSS0_CTL_04_DATA 0x00000000 +#define DDRSS0_CTL_05_DATA 0x00000000 +#define DDRSS0_CTL_06_DATA 0x00000000 +#define DDRSS0_CTL_07_DATA 0x00002AF8 +#define DDRSS0_CTL_08_DATA 0x0001ADAF +#define DDRSS0_CTL_09_DATA 0x00000005 +#define DDRSS0_CTL_10_DATA 0x0000006E +#define DDRSS0_CTL_11_DATA 0x000681C8 +#define DDRSS0_CTL_12_DATA 0x004111C9 +#define DDRSS0_CTL_13_DATA 0x00000005 +#define DDRSS0_CTL_14_DATA 0x000010A9 +#define DDRSS0_CTL_15_DATA 0x000681C8 +#define DDRSS0_CTL_16_DATA 0x004111C9 +#define DDRSS0_CTL_17_DATA 0x00000005 +#define DDRSS0_CTL_18_DATA 0x000010A9 +#define DDRSS0_CTL_19_DATA 0x01010000 +#define DDRSS0_CTL_20_DATA 0x01011001 +#define DDRSS0_CTL_21_DATA 0x02010000 +#define DDRSS0_CTL_22_DATA 0x00020100 +#define DDRSS0_CTL_23_DATA 0x0000000B +#define DDRSS0_CTL_24_DATA 0x0000001C +#define DDRSS0_CTL_25_DATA 0x00000000 +#define DDRSS0_CTL_26_DATA 0x00000000 +#define DDRSS0_CTL_27_DATA 0x03020200 +#define DDRSS0_CTL_28_DATA 0x00005656 +#define DDRSS0_CTL_29_DATA 0x00100000 +#define DDRSS0_CTL_30_DATA 0x00000000 +#define DDRSS0_CTL_31_DATA 0x00000000 +#define DDRSS0_CTL_32_DATA 0x00000000 +#define DDRSS0_CTL_33_DATA 0x00000000 +#define DDRSS0_CTL_34_DATA 0x040C0000 +#define DDRSS0_CTL_35_DATA 0x12501250 +#define DDRSS0_CTL_36_DATA 0x00050804 +#define DDRSS0_CTL_37_DATA 0x09040008 +#define DDRSS0_CTL_38_DATA 0x15000204 +#define DDRSS0_CTL_39_DATA 0x1760008B +#define DDRSS0_CTL_40_DATA 0x1500422B +#define DDRSS0_CTL_41_DATA 0x1760008B +#define DDRSS0_CTL_42_DATA 0x2000422B +#define DDRSS0_CTL_43_DATA 0x000A0A09 +#define DDRSS0_CTL_44_DATA 0x040003C5 +#define DDRSS0_CTL_45_DATA 0x1E161104 +#define DDRSS0_CTL_46_DATA 0x1000922C +#define DDRSS0_CTL_47_DATA 0x1E161110 +#define DDRSS0_CTL_48_DATA 0x1000922C +#define DDRSS0_CTL_49_DATA 0x02030410 +#define DDRSS0_CTL_50_DATA 0x2C060500 +#define DDRSS0_CTL_51_DATA 0x08292C29 +#define DDRSS0_CTL_52_DATA 0x14000E0A +#define DDRSS0_CTL_53_DATA 0x04010A0A +#define DDRSS0_CTL_54_DATA 0x01010004 +#define DDRSS0_CTL_55_DATA 0x0454540A +#define DDRSS0_CTL_56_DATA 0x04313104 +#define DDRSS0_CTL_57_DATA 0x00003131 +#define DDRSS0_CTL_58_DATA 0x00010100 +#define DDRSS0_CTL_59_DATA 0x03010000 +#define DDRSS0_CTL_60_DATA 0x00001508 +#define DDRSS0_CTL_61_DATA 0x00000068 +#define DDRSS0_CTL_62_DATA 0x0000032B +#define DDRSS0_CTL_63_DATA 0x00001035 +#define DDRSS0_CTL_64_DATA 0x0000032B +#define DDRSS0_CTL_65_DATA 0x00001035 +#define DDRSS0_CTL_66_DATA 0x00000005 +#define DDRSS0_CTL_67_DATA 0x00050000 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 +#define DDRSS0_CTL_71_DATA 0x00120103 +#define DDRSS0_CTL_72_DATA 0x00100005 +#define DDRSS0_CTL_73_DATA 0x2F080010 +#define DDRSS0_CTL_74_DATA 0x0505012F +#define DDRSS0_CTL_75_DATA 0x0401030A +#define DDRSS0_CTL_76_DATA 0x041E100B +#define DDRSS0_CTL_77_DATA 0x100B0401 +#define DDRSS0_CTL_78_DATA 0x0001041E +#define DDRSS0_CTL_79_DATA 0x00160016 +#define DDRSS0_CTL_80_DATA 0x033B033B +#define DDRSS0_CTL_81_DATA 0x033B033B +#define DDRSS0_CTL_82_DATA 0x03050505 +#define DDRSS0_CTL_83_DATA 0x03010303 +#define DDRSS0_CTL_84_DATA 0x200B100B +#define DDRSS0_CTL_85_DATA 0x04041004 +#define DDRSS0_CTL_86_DATA 0x200B100B +#define DDRSS0_CTL_87_DATA 0x04041004 +#define DDRSS0_CTL_88_DATA 0x03010000 +#define DDRSS0_CTL_89_DATA 0x00010000 +#define DDRSS0_CTL_90_DATA 0x00000000 +#define DDRSS0_CTL_91_DATA 0x00000000 +#define DDRSS0_CTL_92_DATA 0x01000000 +#define DDRSS0_CTL_93_DATA 0x80104002 +#define DDRSS0_CTL_94_DATA 0x00000000 +#define DDRSS0_CTL_95_DATA 0x00040005 +#define DDRSS0_CTL_96_DATA 0x00000000 +#define DDRSS0_CTL_97_DATA 0x00050000 +#define DDRSS0_CTL_98_DATA 0x00000004 +#define DDRSS0_CTL_99_DATA 0x00000000 +#define DDRSS0_CTL_100_DATA 0x00040005 +#define DDRSS0_CTL_101_DATA 0x00000000 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 +#define DDRSS0_CTL_107_DATA 0x00000000 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 +#define DDRSS0_CTL_114_DATA 0x00000000 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 +#define DDRSS0_CTL_121_DATA 0x00000000 +#define DDRSS0_CTL_122_DATA 0x00007173 +#define DDRSS0_CTL_123_DATA 0x00000000 +#define DDRSS0_CTL_124_DATA 0x00000000 +#define DDRSS0_CTL_125_DATA 0x00000000 +#define DDRSS0_CTL_126_DATA 0x00000000 +#define DDRSS0_CTL_127_DATA 0x00000000 +#define DDRSS0_CTL_128_DATA 0x00000000 +#define DDRSS0_CTL_129_DATA 0x00000000 +#define DDRSS0_CTL_130_DATA 0x00000000 +#define DDRSS0_CTL_131_DATA 0x0B030500 +#define DDRSS0_CTL_132_DATA 0x00040B04 +#define DDRSS0_CTL_133_DATA 0x0A090000 +#define DDRSS0_CTL_134_DATA 0x0A090701 +#define DDRSS0_CTL_135_DATA 0x0900000E +#define DDRSS0_CTL_136_DATA 0x0907010A +#define DDRSS0_CTL_137_DATA 0x00000E0A +#define DDRSS0_CTL_138_DATA 0x07010A09 +#define DDRSS0_CTL_139_DATA 0x000E0A09 +#define DDRSS0_CTL_140_DATA 0x07000401 +#define DDRSS0_CTL_141_DATA 0x00000000 +#define DDRSS0_CTL_142_DATA 0x00000000 +#define DDRSS0_CTL_143_DATA 0x00000000 +#define DDRSS0_CTL_144_DATA 0x00000000 +#define DDRSS0_CTL_145_DATA 0x00000000 +#define DDRSS0_CTL_146_DATA 0x00000000 +#define DDRSS0_CTL_147_DATA 0x00000000 +#define DDRSS0_CTL_148_DATA 0x08080000 +#define DDRSS0_CTL_149_DATA 0x01000000 +#define DDRSS0_CTL_150_DATA 0x800000C0 +#define DDRSS0_CTL_151_DATA 0x800000C0 +#define DDRSS0_CTL_152_DATA 0x800000C0 +#define DDRSS0_CTL_153_DATA 0x00000000 +#define DDRSS0_CTL_154_DATA 0x00001500 +#define DDRSS0_CTL_155_DATA 0x00000000 +#define DDRSS0_CTL_156_DATA 0x00000001 +#define DDRSS0_CTL_157_DATA 0x00000002 +#define DDRSS0_CTL_158_DATA 0x0000100E +#define DDRSS0_CTL_159_DATA 0x00000000 +#define DDRSS0_CTL_160_DATA 0x00000000 +#define DDRSS0_CTL_161_DATA 0x00000000 +#define DDRSS0_CTL_162_DATA 0x00000000 +#define DDRSS0_CTL_163_DATA 0x00000000 +#define DDRSS0_CTL_164_DATA 0x000B0000 +#define DDRSS0_CTL_165_DATA 0x000E0006 +#define DDRSS0_CTL_166_DATA 0x000E0404 +#define DDRSS0_CTL_167_DATA 0x00D601AB +#define DDRSS0_CTL_168_DATA 0x10100216 +#define DDRSS0_CTL_169_DATA 0x01AB0216 +#define DDRSS0_CTL_170_DATA 0x021600D6 +#define DDRSS0_CTL_171_DATA 0x02161010 +#define DDRSS0_CTL_172_DATA 0x00000000 +#define DDRSS0_CTL_173_DATA 0x00000000 +#define DDRSS0_CTL_174_DATA 0x00000000 +#define DDRSS0_CTL_175_DATA 0x3FF40084 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 +#define DDRSS0_CTL_178_DATA 0x36000000 +#define DDRSS0_CTL_179_DATA 0x27270036 +#define DDRSS0_CTL_180_DATA 0x0F0F0000 +#define DDRSS0_CTL_181_DATA 0x16000000 +#define DDRSS0_CTL_182_DATA 0x00841616 +#define DDRSS0_CTL_183_DATA 0x3FF43FF4 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 +#define DDRSS0_CTL_185_DATA 0x00000000 +#define DDRSS0_CTL_186_DATA 0x00363600 +#define DDRSS0_CTL_187_DATA 0x00002727 +#define DDRSS0_CTL_188_DATA 0x00000F0F +#define DDRSS0_CTL_189_DATA 0x16161600 +#define DDRSS0_CTL_190_DATA 0x00000020 +#define DDRSS0_CTL_191_DATA 0x01000000 +#define DDRSS0_CTL_192_DATA 0x00000001 +#define DDRSS0_CTL_193_DATA 0x00000000 +#define DDRSS0_CTL_194_DATA 0x01000000 +#define DDRSS0_CTL_195_DATA 0x00000001 +#define DDRSS0_CTL_196_DATA 0x00000000 +#define DDRSS0_CTL_197_DATA 0x00000000 +#define DDRSS0_CTL_198_DATA 0x00000000 +#define DDRSS0_CTL_199_DATA 0x00000000 +#define DDRSS0_CTL_200_DATA 0x00000000 +#define DDRSS0_CTL_201_DATA 0x00000000 +#define DDRSS0_CTL_202_DATA 0x00000000 +#define DDRSS0_CTL_203_DATA 0x00000000 +#define DDRSS0_CTL_204_DATA 0x00000000 +#define DDRSS0_CTL_205_DATA 0x00000000 +#define DDRSS0_CTL_206_DATA 0x02000000 +#define DDRSS0_CTL_207_DATA 0x01080101 +#define DDRSS0_CTL_208_DATA 0x00000000 +#define DDRSS0_CTL_209_DATA 0x00000000 +#define DDRSS0_CTL_210_DATA 0x00000000 +#define DDRSS0_CTL_211_DATA 0x00000000 +#define DDRSS0_CTL_212_DATA 0x00000000 +#define DDRSS0_CTL_213_DATA 0x00000000 +#define DDRSS0_CTL_214_DATA 0x00000000 +#define DDRSS0_CTL_215_DATA 0x00000000 +#define DDRSS0_CTL_216_DATA 0x00000000 +#define DDRSS0_CTL_217_DATA 0x00000000 +#define DDRSS0_CTL_218_DATA 0x00000000 +#define DDRSS0_CTL_219_DATA 0x00000000 +#define DDRSS0_CTL_220_DATA 0x00000000 +#define DDRSS0_CTL_221_DATA 0x00000000 +#define DDRSS0_CTL_222_DATA 0x00001000 +#define DDRSS0_CTL_223_DATA 0x006403E8 +#define DDRSS0_CTL_224_DATA 0x00000000 +#define DDRSS0_CTL_225_DATA 0x00000000 +#define DDRSS0_CTL_226_DATA 0x00000000 +#define DDRSS0_CTL_227_DATA 0x15110000 +#define DDRSS0_CTL_228_DATA 0x00040C18 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 +#define DDRSS0_CTL_231_DATA 0x00000000 +#define DDRSS0_CTL_232_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 +#define DDRSS0_CTL_235_DATA 0x00000000 +#define DDRSS0_CTL_236_DATA 0x00000000 +#define DDRSS0_CTL_237_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 +#define DDRSS0_CTL_240_DATA 0x00000000 +#define DDRSS0_CTL_241_DATA 0x00000000 +#define DDRSS0_CTL_242_DATA 0x00030000 +#define DDRSS0_CTL_243_DATA 0x00000000 +#define DDRSS0_CTL_244_DATA 0x00000000 +#define DDRSS0_CTL_245_DATA 0x00000000 +#define DDRSS0_CTL_246_DATA 0x00000000 +#define DDRSS0_CTL_247_DATA 0x00000000 +#define DDRSS0_CTL_248_DATA 0x00000000 +#define DDRSS0_CTL_249_DATA 0x00000000 +#define DDRSS0_CTL_250_DATA 0x00000000 +#define DDRSS0_CTL_251_DATA 0x00000000 +#define DDRSS0_CTL_252_DATA 0x00000000 +#define DDRSS0_CTL_253_DATA 0x00000000 +#define DDRSS0_CTL_254_DATA 0x00000000 +#define DDRSS0_CTL_255_DATA 0x00000000 +#define DDRSS0_CTL_256_DATA 0x00000000 +#define DDRSS0_CTL_257_DATA 0x01000200 +#define DDRSS0_CTL_258_DATA 0x00370040 +#define DDRSS0_CTL_259_DATA 0x00020008 +#define DDRSS0_CTL_260_DATA 0x00400100 +#define DDRSS0_CTL_261_DATA 0x00400855 +#define DDRSS0_CTL_262_DATA 0x01000200 +#define DDRSS0_CTL_263_DATA 0x08550040 +#define DDRSS0_CTL_264_DATA 0x00000040 +#define DDRSS0_CTL_265_DATA 0x006B0003 +#define DDRSS0_CTL_266_DATA 0x0100006B +#define DDRSS0_CTL_267_DATA 0x03030303 +#define DDRSS0_CTL_268_DATA 0x00000000 +#define DDRSS0_CTL_269_DATA 0x00000202 +#define DDRSS0_CTL_270_DATA 0x00001FFF +#define DDRSS0_CTL_271_DATA 0x3FFF2000 +#define DDRSS0_CTL_272_DATA 0x03FF0000 +#define DDRSS0_CTL_273_DATA 0x000103FF +#define DDRSS0_CTL_274_DATA 0x0FFF0B00 +#define DDRSS0_CTL_275_DATA 0x01010001 +#define DDRSS0_CTL_276_DATA 0x01010101 +#define DDRSS0_CTL_277_DATA 0x01180101 +#define DDRSS0_CTL_278_DATA 0x00030000 +#define DDRSS0_CTL_279_DATA 0x00000000 +#define DDRSS0_CTL_280_DATA 0x00000000 +#define DDRSS0_CTL_281_DATA 0x00000000 +#define DDRSS0_CTL_282_DATA 0x00000000 +#define DDRSS0_CTL_283_DATA 0x00000000 +#define DDRSS0_CTL_284_DATA 0x00000000 +#define DDRSS0_CTL_285_DATA 0x00000000 +#define DDRSS0_CTL_286_DATA 0x00040101 +#define DDRSS0_CTL_287_DATA 0x04010100 +#define DDRSS0_CTL_288_DATA 0x00000000 +#define DDRSS0_CTL_289_DATA 0x00000000 +#define DDRSS0_CTL_290_DATA 0x03030300 +#define DDRSS0_CTL_291_DATA 0x00010101 +#define DDRSS0_CTL_292_DATA 0x00000000 +#define DDRSS0_CTL_293_DATA 0x00000000 +#define DDRSS0_CTL_294_DATA 0x00000000 +#define DDRSS0_CTL_295_DATA 0x00000000 +#define DDRSS0_CTL_296_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF +#define DDRSS0_CTL_299_DATA 0x00000000 +#define DDRSS0_CTL_300_DATA 0x00000000 +#define DDRSS0_CTL_301_DATA 0x00000000 +#define DDRSS0_CTL_302_DATA 0x00000000 +#define DDRSS0_CTL_303_DATA 0x00000000 +#define DDRSS0_CTL_304_DATA 0x00000000 +#define DDRSS0_CTL_305_DATA 0x00000000 +#define DDRSS0_CTL_306_DATA 0x00000000 +#define DDRSS0_CTL_307_DATA 0x00000000 +#define DDRSS0_CTL_308_DATA 0x00000000 +#define DDRSS0_CTL_309_DATA 0x00000000 +#define DDRSS0_CTL_310_DATA 0x00000000 +#define DDRSS0_CTL_311_DATA 0x00000000 +#define DDRSS0_CTL_312_DATA 0x00000000 +#define DDRSS0_CTL_313_DATA 0x01000000 +#define DDRSS0_CTL_314_DATA 0x00020201 +#define DDRSS0_CTL_315_DATA 0x01000101 +#define DDRSS0_CTL_316_DATA 0x01010001 +#define DDRSS0_CTL_317_DATA 0x00010101 +#define DDRSS0_CTL_318_DATA 0x050A0A03 +#define DDRSS0_CTL_319_DATA 0x10082323 +#define DDRSS0_CTL_320_DATA 0x00090310 +#define DDRSS0_CTL_321_DATA 0x0B0C030F +#define DDRSS0_CTL_322_DATA 0x0B0C0306 +#define DDRSS0_CTL_323_DATA 0x0C090006 +#define DDRSS0_CTL_324_DATA 0x0100000C +#define DDRSS0_CTL_325_DATA 0x08040801 +#define DDRSS0_CTL_326_DATA 0x00000004 +#define DDRSS0_CTL_327_DATA 0x00000000 +#define DDRSS0_CTL_328_DATA 0x00010000 +#define DDRSS0_CTL_329_DATA 0x00280D00 +#define DDRSS0_CTL_330_DATA 0x00000001 +#define DDRSS0_CTL_331_DATA 0x00030001 +#define DDRSS0_CTL_332_DATA 0x00000000 +#define DDRSS0_CTL_333_DATA 0x00000000 +#define DDRSS0_CTL_334_DATA 0x00000000 +#define DDRSS0_CTL_335_DATA 0x00000000 +#define DDRSS0_CTL_336_DATA 0x00000000 +#define DDRSS0_CTL_337_DATA 0x00000000 +#define DDRSS0_CTL_338_DATA 0x00000000 +#define DDRSS0_CTL_339_DATA 0x00000000 +#define DDRSS0_CTL_340_DATA 0x01000000 +#define DDRSS0_CTL_341_DATA 0x00000001 +#define DDRSS0_CTL_342_DATA 0x00010100 +#define DDRSS0_CTL_343_DATA 0x03030000 +#define DDRSS0_CTL_344_DATA 0x00000000 +#define DDRSS0_CTL_345_DATA 0x00000000 +#define DDRSS0_CTL_346_DATA 0x00000000 +#define DDRSS0_CTL_347_DATA 0x00000000 +#define DDRSS0_CTL_348_DATA 0x00000000 +#define DDRSS0_CTL_349_DATA 0x00000000 +#define DDRSS0_CTL_350_DATA 0x00000000 +#define DDRSS0_CTL_351_DATA 0x00000000 +#define DDRSS0_CTL_352_DATA 0x00000000 +#define DDRSS0_CTL_353_DATA 0x00000000 +#define DDRSS0_CTL_354_DATA 0x00000000 +#define DDRSS0_CTL_355_DATA 0x00000000 +#define DDRSS0_CTL_356_DATA 0x00000000 +#define DDRSS0_CTL_357_DATA 0x00000000 +#define DDRSS0_CTL_358_DATA 0x00000000 +#define DDRSS0_CTL_359_DATA 0x00000000 +#define DDRSS0_CTL_360_DATA 0x000556AA +#define DDRSS0_CTL_361_DATA 0x000AAAAA +#define DDRSS0_CTL_362_DATA 0x000AA955 +#define DDRSS0_CTL_363_DATA 0x00055555 +#define DDRSS0_CTL_364_DATA 0x000B3133 +#define DDRSS0_CTL_365_DATA 0x0004CD33 +#define DDRSS0_CTL_366_DATA 0x0004CECC +#define DDRSS0_CTL_367_DATA 0x000B32CC +#define DDRSS0_CTL_368_DATA 0x00010300 +#define DDRSS0_CTL_369_DATA 0x03000100 +#define DDRSS0_CTL_370_DATA 0x00000000 +#define DDRSS0_CTL_371_DATA 0x00000000 +#define DDRSS0_CTL_372_DATA 0x00000000 +#define DDRSS0_CTL_373_DATA 0x00000000 +#define DDRSS0_CTL_374_DATA 0x00000000 +#define DDRSS0_CTL_375_DATA 0x00000000 +#define DDRSS0_CTL_376_DATA 0x00000000 +#define DDRSS0_CTL_377_DATA 0x00010000 +#define DDRSS0_CTL_378_DATA 0x00000404 +#define DDRSS0_CTL_379_DATA 0x00000000 +#define DDRSS0_CTL_380_DATA 0x00000000 +#define DDRSS0_CTL_381_DATA 0x00000000 +#define DDRSS0_CTL_382_DATA 0x00000000 +#define DDRSS0_CTL_383_DATA 0x00000000 +#define DDRSS0_CTL_384_DATA 0x00000000 +#define DDRSS0_CTL_385_DATA 0x00000000 +#define DDRSS0_CTL_386_DATA 0x00000000 +#define DDRSS0_CTL_387_DATA 0x3A3A1B00 +#define DDRSS0_CTL_388_DATA 0x000A0000 +#define DDRSS0_CTL_389_DATA 0x000000C6 +#define DDRSS0_CTL_390_DATA 0x00000200 +#define DDRSS0_CTL_391_DATA 0x00000200 +#define DDRSS0_CTL_392_DATA 0x00000200 +#define DDRSS0_CTL_393_DATA 0x00000200 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC +#define DDRSS0_CTL_396_DATA 0x00000204 +#define DDRSS0_CTL_397_DATA 0x0000206A +#define DDRSS0_CTL_398_DATA 0x00000200 +#define DDRSS0_CTL_399_DATA 0x00000200 +#define DDRSS0_CTL_400_DATA 0x00000200 +#define DDRSS0_CTL_401_DATA 0x00000200 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A +#define DDRSS0_CTL_406_DATA 0x00000200 +#define DDRSS0_CTL_407_DATA 0x00000200 +#define DDRSS0_CTL_408_DATA 0x00000200 +#define DDRSS0_CTL_409_DATA 0x00000200 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 +#define DDRSS0_CTL_413_DATA 0x03030202 +#define DDRSS0_CTL_414_DATA 0x00000022 +#define DDRSS0_CTL_415_DATA 0x00000000 +#define DDRSS0_CTL_416_DATA 0x00000000 +#define DDRSS0_CTL_417_DATA 0x00001403 +#define DDRSS0_CTL_418_DATA 0x000007D0 +#define DDRSS0_CTL_419_DATA 0x00000000 +#define DDRSS0_CTL_420_DATA 0x00000000 +#define DDRSS0_CTL_421_DATA 0x00030000 +#define DDRSS0_CTL_422_DATA 0x0007001F +#define DDRSS0_CTL_423_DATA 0x001B0033 +#define DDRSS0_CTL_424_DATA 0x001B0033 +#define DDRSS0_CTL_425_DATA 0x00000000 +#define DDRSS0_CTL_426_DATA 0x00000000 +#define DDRSS0_CTL_427_DATA 0x02000000 +#define DDRSS0_CTL_428_DATA 0x01000404 +#define DDRSS0_CTL_429_DATA 0x0B220B22 +#define DDRSS0_CTL_430_DATA 0x00000105 +#define DDRSS0_CTL_431_DATA 0x00010101 +#define DDRSS0_CTL_432_DATA 0x00010101 +#define DDRSS0_CTL_433_DATA 0x00010001 +#define DDRSS0_CTL_434_DATA 0x00000101 +#define DDRSS0_CTL_435_DATA 0x02000201 +#define DDRSS0_CTL_436_DATA 0x02010000 +#define DDRSS0_CTL_437_DATA 0x00000200 +#define DDRSS0_CTL_438_DATA 0x28060000 +#define DDRSS0_CTL_439_DATA 0x00000128 +#define DDRSS0_CTL_440_DATA 0xFFFFFFFF +#define DDRSS0_CTL_441_DATA 0xFFFFFFFF +#define DDRSS0_CTL_442_DATA 0x00000000 +#define DDRSS0_CTL_443_DATA 0x00000000 +#define DDRSS0_CTL_444_DATA 0x00000000 +#define DDRSS0_CTL_445_DATA 0x00000000 +#define DDRSS0_CTL_446_DATA 0x00000000 +#define DDRSS0_CTL_447_DATA 0x00000000 +#define DDRSS0_CTL_448_DATA 0x00000000 +#define DDRSS0_CTL_449_DATA 0x00000000 +#define DDRSS0_CTL_450_DATA 0x00000000 +#define DDRSS0_CTL_451_DATA 0x00000000 +#define DDRSS0_CTL_452_DATA 0x00000000 +#define DDRSS0_CTL_453_DATA 0x00000000 +#define DDRSS0_CTL_454_DATA 0x00000000 +#define DDRSS0_CTL_455_DATA 0x00000000 +#define DDRSS0_CTL_456_DATA 0x00000000 +#define DDRSS0_CTL_457_DATA 0x00000000 +#define DDRSS0_CTL_458_DATA 0x00000000 + +#define DDRSS0_PI_00_DATA 0x00000B00 +#define DDRSS0_PI_01_DATA 0x00000000 +#define DDRSS0_PI_02_DATA 0x00000000 +#define DDRSS0_PI_03_DATA 0x00000000 +#define DDRSS0_PI_04_DATA 0x00000000 +#define DDRSS0_PI_05_DATA 0x00000101 +#define DDRSS0_PI_06_DATA 0x00640000 +#define DDRSS0_PI_07_DATA 0x00000001 +#define DDRSS0_PI_08_DATA 0x00000000 +#define DDRSS0_PI_09_DATA 0x00000000 +#define DDRSS0_PI_10_DATA 0x00000000 +#define DDRSS0_PI_11_DATA 0x00000000 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 +#define DDRSS0_PI_14_DATA 0x0800000F +#define DDRSS0_PI_15_DATA 0x00000103 +#define DDRSS0_PI_16_DATA 0x00000005 +#define DDRSS0_PI_17_DATA 0x00000000 +#define DDRSS0_PI_18_DATA 0x00000000 +#define DDRSS0_PI_19_DATA 0x00000000 +#define DDRSS0_PI_20_DATA 0x00000000 +#define DDRSS0_PI_21_DATA 0x00000000 +#define DDRSS0_PI_22_DATA 0x00000000 +#define DDRSS0_PI_23_DATA 0x00000000 +#define DDRSS0_PI_24_DATA 0x00000000 +#define DDRSS0_PI_25_DATA 0x00000000 +#define DDRSS0_PI_26_DATA 0x00010100 +#define DDRSS0_PI_27_DATA 0x00280A00 +#define DDRSS0_PI_28_DATA 0x00000000 +#define DDRSS0_PI_29_DATA 0x0F000000 +#define DDRSS0_PI_30_DATA 0x00003200 +#define DDRSS0_PI_31_DATA 0x00000000 +#define DDRSS0_PI_32_DATA 0x00000000 +#define DDRSS0_PI_33_DATA 0x01010102 +#define DDRSS0_PI_34_DATA 0x00000000 +#define DDRSS0_PI_35_DATA 0x000000AA +#define DDRSS0_PI_36_DATA 0x00000055 +#define DDRSS0_PI_37_DATA 0x000000B5 +#define DDRSS0_PI_38_DATA 0x0000004A +#define DDRSS0_PI_39_DATA 0x00000056 +#define DDRSS0_PI_40_DATA 0x000000A9 +#define DDRSS0_PI_41_DATA 0x000000A9 +#define DDRSS0_PI_42_DATA 0x000000B5 +#define DDRSS0_PI_43_DATA 0x00000000 +#define DDRSS0_PI_44_DATA 0x00000000 +#define DDRSS0_PI_45_DATA 0x000F0F00 +#define DDRSS0_PI_46_DATA 0x0000001B +#define DDRSS0_PI_47_DATA 0x000007D0 +#define DDRSS0_PI_48_DATA 0x00000300 +#define DDRSS0_PI_49_DATA 0x00000000 +#define DDRSS0_PI_50_DATA 0x00000000 +#define DDRSS0_PI_51_DATA 0x01000000 +#define DDRSS0_PI_52_DATA 0x00010101 +#define DDRSS0_PI_53_DATA 0x00000000 +#define DDRSS0_PI_54_DATA 0x00030000 +#define DDRSS0_PI_55_DATA 0x0F000000 +#define DDRSS0_PI_56_DATA 0x00000017 +#define DDRSS0_PI_57_DATA 0x00000000 +#define DDRSS0_PI_58_DATA 0x00000000 +#define DDRSS0_PI_59_DATA 0x00000000 +#define DDRSS0_PI_60_DATA 0x0A0A140A +#define DDRSS0_PI_61_DATA 0x10020201 +#define DDRSS0_PI_62_DATA 0x00020805 +#define DDRSS0_PI_63_DATA 0x01000404 +#define DDRSS0_PI_64_DATA 0x00000000 +#define DDRSS0_PI_65_DATA 0x00000000 +#define DDRSS0_PI_66_DATA 0x01000100 +#define DDRSS0_PI_67_DATA 0x0102020F +#define DDRSS0_PI_68_DATA 0x00340000 +#define DDRSS0_PI_69_DATA 0x00000000 +#define DDRSS0_PI_70_DATA 0x00000000 +#define DDRSS0_PI_71_DATA 0x0000FFFF +#define DDRSS0_PI_72_DATA 0x01000000 +#define DDRSS0_PI_73_DATA 0x00080000 +#define DDRSS0_PI_74_DATA 0x02000200 +#define DDRSS0_PI_75_DATA 0x01000100 +#define DDRSS0_PI_76_DATA 0x01000000 +#define DDRSS0_PI_77_DATA 0x02000200 +#define DDRSS0_PI_78_DATA 0x00000200 +#define DDRSS0_PI_79_DATA 0x00000000 +#define DDRSS0_PI_80_DATA 0x00000000 +#define DDRSS0_PI_81_DATA 0x00000000 +#define DDRSS0_PI_82_DATA 0x00000000 +#define DDRSS0_PI_83_DATA 0x00000000 +#define DDRSS0_PI_84_DATA 0x00000000 +#define DDRSS0_PI_85_DATA 0x00000000 +#define DDRSS0_PI_86_DATA 0x00000000 +#define DDRSS0_PI_87_DATA 0x00000000 +#define DDRSS0_PI_88_DATA 0x00000000 +#define DDRSS0_PI_89_DATA 0x00000000 +#define DDRSS0_PI_90_DATA 0x00000000 +#define DDRSS0_PI_91_DATA 0x00000400 +#define DDRSS0_PI_92_DATA 0x02010000 +#define DDRSS0_PI_93_DATA 0x00080003 +#define DDRSS0_PI_94_DATA 0x00080000 +#define DDRSS0_PI_95_DATA 0x00000001 +#define DDRSS0_PI_96_DATA 0x00000000 +#define DDRSS0_PI_97_DATA 0x0000AA00 +#define DDRSS0_PI_98_DATA 0x00000000 +#define DDRSS0_PI_99_DATA 0x00000000 +#define DDRSS0_PI_100_DATA 0x00010000 +#define DDRSS0_PI_101_DATA 0x00000000 +#define DDRSS0_PI_102_DATA 0x00000000 +#define DDRSS0_PI_103_DATA 0x00000000 +#define DDRSS0_PI_104_DATA 0x00000000 +#define DDRSS0_PI_105_DATA 0x00000000 +#define DDRSS0_PI_106_DATA 0x00000000 +#define DDRSS0_PI_107_DATA 0x00000000 +#define DDRSS0_PI_108_DATA 0x00000000 +#define DDRSS0_PI_109_DATA 0x00000000 +#define DDRSS0_PI_110_DATA 0x00000000 +#define DDRSS0_PI_111_DATA 0x00000000 +#define DDRSS0_PI_112_DATA 0x00000000 +#define DDRSS0_PI_113_DATA 0x00000000 +#define DDRSS0_PI_114_DATA 0x00000000 +#define DDRSS0_PI_115_DATA 0x00000000 +#define DDRSS0_PI_116_DATA 0x00000000 +#define DDRSS0_PI_117_DATA 0x00000000 +#define DDRSS0_PI_118_DATA 0x00000000 +#define DDRSS0_PI_119_DATA 0x00000000 +#define DDRSS0_PI_120_DATA 0x00000000 +#define DDRSS0_PI_121_DATA 0x00000000 +#define DDRSS0_PI_122_DATA 0x00000000 +#define DDRSS0_PI_123_DATA 0x00000000 +#define DDRSS0_PI_124_DATA 0x00000000 +#define DDRSS0_PI_125_DATA 0x00000008 +#define DDRSS0_PI_126_DATA 0x00000000 +#define DDRSS0_PI_127_DATA 0x00000000 +#define DDRSS0_PI_128_DATA 0x00000000 +#define DDRSS0_PI_129_DATA 0x00000000 +#define DDRSS0_PI_130_DATA 0x00000000 +#define DDRSS0_PI_131_DATA 0x00000000 +#define DDRSS0_PI_132_DATA 0x00000000 +#define DDRSS0_PI_133_DATA 0x00000000 +#define DDRSS0_PI_134_DATA 0x00000002 +#define DDRSS0_PI_135_DATA 0x00000000 +#define DDRSS0_PI_136_DATA 0x00000000 +#define DDRSS0_PI_137_DATA 0x0000000A +#define DDRSS0_PI_138_DATA 0x00000019 +#define DDRSS0_PI_139_DATA 0x00000100 +#define DDRSS0_PI_140_DATA 0x00000000 +#define DDRSS0_PI_141_DATA 0x00000000 +#define DDRSS0_PI_142_DATA 0x00000000 +#define DDRSS0_PI_143_DATA 0x00000000 +#define DDRSS0_PI_144_DATA 0x01000000 +#define DDRSS0_PI_145_DATA 0x00010003 +#define DDRSS0_PI_146_DATA 0x02000101 +#define DDRSS0_PI_147_DATA 0x01030001 +#define DDRSS0_PI_148_DATA 0x00010400 +#define DDRSS0_PI_149_DATA 0x06000105 +#define DDRSS0_PI_150_DATA 0x01070001 +#define DDRSS0_PI_151_DATA 0x00000000 +#define DDRSS0_PI_152_DATA 0x00000000 +#define DDRSS0_PI_153_DATA 0x00000000 +#define DDRSS0_PI_154_DATA 0x00010001 +#define DDRSS0_PI_155_DATA 0x00000000 +#define DDRSS0_PI_156_DATA 0x00000000 +#define DDRSS0_PI_157_DATA 0x00000000 +#define DDRSS0_PI_158_DATA 0x00000000 +#define DDRSS0_PI_159_DATA 0x00000401 +#define DDRSS0_PI_160_DATA 0x00000000 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 +#define DDRSS0_PI_164_DATA 0x00000034 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 +#define DDRSS0_PI_167_DATA 0x02000200 +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 +#define DDRSS0_PI_171_DATA 0x0000032B +#define DDRSS0_PI_172_DATA 0x00001035 +#define DDRSS0_PI_173_DATA 0x0000032B +#define DDRSS0_PI_174_DATA 0x04001035 +#define DDRSS0_PI_175_DATA 0x01010404 +#define DDRSS0_PI_176_DATA 0x00001500 +#define DDRSS0_PI_177_DATA 0x00150015 +#define DDRSS0_PI_178_DATA 0x01000100 +#define DDRSS0_PI_179_DATA 0x00000100 +#define DDRSS0_PI_180_DATA 0x00000000 +#define DDRSS0_PI_181_DATA 0x01010101 +#define DDRSS0_PI_182_DATA 0x00000000 +#define DDRSS0_PI_183_DATA 0x00000000 +#define DDRSS0_PI_184_DATA 0x00000000 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 +#define DDRSS0_PI_187_DATA 0x00040402 +#define DDRSS0_PI_188_DATA 0x000D0035 +#define DDRSS0_PI_189_DATA 0x00218049 +#define DDRSS0_PI_190_DATA 0x00218049 +#define DDRSS0_PI_191_DATA 0x01000101 +#define DDRSS0_PI_192_DATA 0x0004000E +#define DDRSS0_PI_193_DATA 0x00040216 +#define DDRSS0_PI_194_DATA 0x01000216 +#define DDRSS0_PI_195_DATA 0x000F000F +#define DDRSS0_PI_196_DATA 0x02170100 +#define DDRSS0_PI_197_DATA 0x01000217 +#define DDRSS0_PI_198_DATA 0x02170217 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B +#define DDRSS0_PI_201_DATA 0x0A070601 +#define DDRSS0_PI_202_DATA 0x1F130A0D +#define DDRSS0_PI_203_DATA 0x1F130A14 +#define DDRSS0_PI_204_DATA 0x0000C014 +#define DDRSS0_PI_205_DATA 0x00C01000 +#define DDRSS0_PI_206_DATA 0x00C01000 +#define DDRSS0_PI_207_DATA 0x00021000 +#define DDRSS0_PI_208_DATA 0x0024000E +#define DDRSS0_PI_209_DATA 0x00240216 +#define DDRSS0_PI_210_DATA 0x00110216 +#define DDRSS0_PI_211_DATA 0x32000056 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 +#define DDRSS0_PI_214_DATA 0x03013212 +#define DDRSS0_PI_215_DATA 0x00003600 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 +#define DDRSS0_PI_220_DATA 0x0A032001 +#define DDRSS0_PI_221_DATA 0x2C31110A +#define DDRSS0_PI_222_DATA 0x00002918 +#define DDRSS0_PI_223_DATA 0x6000838E +#define DDRSS0_PI_224_DATA 0x1E202008 +#define DDRSS0_PI_225_DATA 0x2C311116 +#define DDRSS0_PI_226_DATA 0x00002918 +#define DDRSS0_PI_227_DATA 0x6000838E +#define DDRSS0_PI_228_DATA 0x1E202008 +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 +#define DDRSS0_PI_235_DATA 0x033B0016 +#define DDRSS0_PI_236_DATA 0x0303033B +#define DDRSS0_PI_237_DATA 0x002AF803 +#define DDRSS0_PI_238_DATA 0x0001ADAF +#define DDRSS0_PI_239_DATA 0x00000005 +#define DDRSS0_PI_240_DATA 0x0000006E +#define DDRSS0_PI_241_DATA 0x00000016 +#define DDRSS0_PI_242_DATA 0x000681C8 +#define DDRSS0_PI_243_DATA 0x0001ADAF +#define DDRSS0_PI_244_DATA 0x00000005 +#define DDRSS0_PI_245_DATA 0x000010A9 +#define DDRSS0_PI_246_DATA 0x0000033B +#define DDRSS0_PI_247_DATA 0x000681C8 +#define DDRSS0_PI_248_DATA 0x0001ADAF +#define DDRSS0_PI_249_DATA 0x00000005 +#define DDRSS0_PI_250_DATA 0x000010A9 +#define DDRSS0_PI_251_DATA 0x0100033B +#define DDRSS0_PI_252_DATA 0x00370040 +#define DDRSS0_PI_253_DATA 0x00010008 +#define DDRSS0_PI_254_DATA 0x08550040 +#define DDRSS0_PI_255_DATA 0x00010040 +#define DDRSS0_PI_256_DATA 0x08550040 +#define DDRSS0_PI_257_DATA 0x00000340 +#define DDRSS0_PI_258_DATA 0x006B006B +#define DDRSS0_PI_259_DATA 0x08040404 +#define DDRSS0_PI_260_DATA 0x00000055 +#define DDRSS0_PI_261_DATA 0x55083C5A +#define DDRSS0_PI_262_DATA 0x5A000000 +#define DDRSS0_PI_263_DATA 0x0055083C +#define DDRSS0_PI_264_DATA 0x3C5A0000 +#define DDRSS0_PI_265_DATA 0x00005508 +#define DDRSS0_PI_266_DATA 0x0C3C5A00 +#define DDRSS0_PI_267_DATA 0x080F0E0D +#define DDRSS0_PI_268_DATA 0x000B0A09 +#define DDRSS0_PI_269_DATA 0x00030201 +#define DDRSS0_PI_270_DATA 0x01000000 +#define DDRSS0_PI_271_DATA 0x04020201 +#define DDRSS0_PI_272_DATA 0x00080804 +#define DDRSS0_PI_273_DATA 0x00000000 +#define DDRSS0_PI_274_DATA 0x00000000 +#define DDRSS0_PI_275_DATA 0x00F30084 +#define DDRSS0_PI_276_DATA 0x00160000 +#define DDRSS0_PI_277_DATA 0x36F33FF4 +#define DDRSS0_PI_278_DATA 0x00160F27 +#define DDRSS0_PI_279_DATA 0x36F33FF4 +#define DDRSS0_PI_280_DATA 0x00160F27 +#define DDRSS0_PI_281_DATA 0x00F30084 +#define DDRSS0_PI_282_DATA 0x00160000 +#define DDRSS0_PI_283_DATA 0x36F33FF4 +#define DDRSS0_PI_284_DATA 0x00160F27 +#define DDRSS0_PI_285_DATA 0x36F33FF4 +#define DDRSS0_PI_286_DATA 0x00160F27 +#define DDRSS0_PI_287_DATA 0x00F30084 +#define DDRSS0_PI_288_DATA 0x00160000 +#define DDRSS0_PI_289_DATA 0x36F33FF4 +#define DDRSS0_PI_290_DATA 0x00160F27 +#define DDRSS0_PI_291_DATA 0x36F33FF4 +#define DDRSS0_PI_292_DATA 0x00160F27 +#define DDRSS0_PI_293_DATA 0x00F30084 +#define DDRSS0_PI_294_DATA 0x00160000 +#define DDRSS0_PI_295_DATA 0x36F33FF4 +#define DDRSS0_PI_296_DATA 0x00160F27 +#define DDRSS0_PI_297_DATA 0x36F33FF4 +#define DDRSS0_PI_298_DATA 0x00160F27 +#define DDRSS0_PI_299_DATA 0x00000000 + +#define DDRSS0_PHY_00_DATA 0x000004F0 +#define DDRSS0_PHY_01_DATA 0x00000000 +#define DDRSS0_PHY_02_DATA 0x00030200 +#define DDRSS0_PHY_03_DATA 0x00000000 +#define DDRSS0_PHY_04_DATA 0x00000000 +#define DDRSS0_PHY_05_DATA 0x01030000 +#define DDRSS0_PHY_06_DATA 0x00010000 +#define DDRSS0_PHY_07_DATA 0x01030004 +#define DDRSS0_PHY_08_DATA 0x01000000 +#define DDRSS0_PHY_09_DATA 0x00000000 +#define DDRSS0_PHY_10_DATA 0x00000000 +#define DDRSS0_PHY_11_DATA 0x01000001 +#define DDRSS0_PHY_12_DATA 0x00000200 +#define DDRSS0_PHY_13_DATA 0x000800C0 +#define DDRSS0_PHY_14_DATA 0x060100CC +#define DDRSS0_PHY_15_DATA 0x00030066 +#define DDRSS0_PHY_16_DATA 0x00000000 +#define DDRSS0_PHY_17_DATA 0x00000301 +#define DDRSS0_PHY_18_DATA 0x0000AAAA +#define DDRSS0_PHY_19_DATA 0x00005555 +#define DDRSS0_PHY_20_DATA 0x0000B5B5 +#define DDRSS0_PHY_21_DATA 0x00004A4A +#define DDRSS0_PHY_22_DATA 0x00005656 +#define DDRSS0_PHY_23_DATA 0x0000A9A9 +#define DDRSS0_PHY_24_DATA 0x0000A9A9 +#define DDRSS0_PHY_25_DATA 0x0000B5B5 +#define DDRSS0_PHY_26_DATA 0x00000000 +#define DDRSS0_PHY_27_DATA 0x00000000 +#define DDRSS0_PHY_28_DATA 0x2A000000 +#define DDRSS0_PHY_29_DATA 0x00000808 +#define DDRSS0_PHY_30_DATA 0x0F000000 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002002 +#define DDRSS0_PHY_34_DATA 0x00000000 +#define DDRSS0_PHY_35_DATA 0x00000000 +#define DDRSS0_PHY_36_DATA 0x55555555 +#define DDRSS0_PHY_37_DATA 0xAAAAAAAA +#define DDRSS0_PHY_38_DATA 0x55555555 +#define DDRSS0_PHY_39_DATA 0xAAAAAAAA +#define DDRSS0_PHY_40_DATA 0x00005555 +#define DDRSS0_PHY_41_DATA 0x01000100 +#define DDRSS0_PHY_42_DATA 0x00800180 +#define DDRSS0_PHY_43_DATA 0x00000001 +#define DDRSS0_PHY_44_DATA 0x00000000 +#define DDRSS0_PHY_45_DATA 0x00000000 +#define DDRSS0_PHY_46_DATA 0x00000000 +#define DDRSS0_PHY_47_DATA 0x00000000 +#define DDRSS0_PHY_48_DATA 0x00000000 +#define DDRSS0_PHY_49_DATA 0x00000000 +#define DDRSS0_PHY_50_DATA 0x00000000 +#define DDRSS0_PHY_51_DATA 0x00000000 +#define DDRSS0_PHY_52_DATA 0x00000000 +#define DDRSS0_PHY_53_DATA 0x00000000 +#define DDRSS0_PHY_54_DATA 0x00000000 +#define DDRSS0_PHY_55_DATA 0x00000000 +#define DDRSS0_PHY_56_DATA 0x00000000 +#define DDRSS0_PHY_57_DATA 0x00000000 +#define DDRSS0_PHY_58_DATA 0x00000000 +#define DDRSS0_PHY_59_DATA 0x00000000 +#define DDRSS0_PHY_60_DATA 0x00000000 +#define DDRSS0_PHY_61_DATA 0x00000000 +#define DDRSS0_PHY_62_DATA 0x00000000 +#define DDRSS0_PHY_63_DATA 0x00000000 +#define DDRSS0_PHY_64_DATA 0x00000000 +#define DDRSS0_PHY_65_DATA 0x00000000 +#define DDRSS0_PHY_66_DATA 0x00000104 +#define DDRSS0_PHY_67_DATA 0x00000120 +#define DDRSS0_PHY_68_DATA 0x00000000 +#define DDRSS0_PHY_69_DATA 0x00000000 +#define DDRSS0_PHY_70_DATA 0x00000000 +#define DDRSS0_PHY_71_DATA 0x00000000 +#define DDRSS0_PHY_72_DATA 0x00000000 +#define DDRSS0_PHY_73_DATA 0x00000000 +#define DDRSS0_PHY_74_DATA 0x00000000 +#define DDRSS0_PHY_75_DATA 0x00000001 +#define DDRSS0_PHY_76_DATA 0x07FF0000 +#define DDRSS0_PHY_77_DATA 0x0080081F +#define DDRSS0_PHY_78_DATA 0x00081020 +#define DDRSS0_PHY_79_DATA 0x04010000 +#define DDRSS0_PHY_80_DATA 0x00000000 +#define DDRSS0_PHY_81_DATA 0x00000000 +#define DDRSS0_PHY_82_DATA 0x00000000 +#define DDRSS0_PHY_83_DATA 0x00000100 +#define DDRSS0_PHY_84_DATA 0x01CC0C01 +#define DDRSS0_PHY_85_DATA 0x1003CC0C +#define DDRSS0_PHY_86_DATA 0x20000140 +#define DDRSS0_PHY_87_DATA 0x07FF0200 +#define DDRSS0_PHY_88_DATA 0x0000DD01 +#define DDRSS0_PHY_89_DATA 0x10100303 +#define DDRSS0_PHY_90_DATA 0x10101010 +#define DDRSS0_PHY_91_DATA 0x10101010 +#define DDRSS0_PHY_92_DATA 0x00021010 +#define DDRSS0_PHY_93_DATA 0x00100010 +#define DDRSS0_PHY_94_DATA 0x00100010 +#define DDRSS0_PHY_95_DATA 0x00100010 +#define DDRSS0_PHY_96_DATA 0x00100010 +#define DDRSS0_PHY_97_DATA 0x00050010 +#define DDRSS0_PHY_98_DATA 0x51517041 +#define DDRSS0_PHY_99_DATA 0x31C06001 +#define DDRSS0_PHY_100_DATA 0x07AB01AB +#define DDRSS0_PHY_101_DATA 0x00C0C001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 +#define DDRSS0_PHY_103_DATA 0x10001000 +#define DDRSS0_PHY_104_DATA 0x0C083E42 +#define DDRSS0_PHY_105_DATA 0x0F0C3701 +#define DDRSS0_PHY_106_DATA 0x01000140 +#define DDRSS0_PHY_107_DATA 0x0C000420 +#define DDRSS0_PHY_108_DATA 0x00000198 +#define DDRSS0_PHY_109_DATA 0x0A0000D0 +#define DDRSS0_PHY_110_DATA 0x00030200 +#define DDRSS0_PHY_111_DATA 0x02800000 +#define DDRSS0_PHY_112_DATA 0x80800000 +#define DDRSS0_PHY_113_DATA 0x000E2010 +#define DDRSS0_PHY_114_DATA 0x76543210 +#define DDRSS0_PHY_115_DATA 0x00000008 +#define DDRSS0_PHY_116_DATA 0x02800280 +#define DDRSS0_PHY_117_DATA 0x02800280 +#define DDRSS0_PHY_118_DATA 0x02800280 +#define DDRSS0_PHY_119_DATA 0x02800280 +#define DDRSS0_PHY_120_DATA 0x00000280 +#define DDRSS0_PHY_121_DATA 0x0000A000 +#define DDRSS0_PHY_122_DATA 0x00A000A0 +#define DDRSS0_PHY_123_DATA 0x00A000A0 +#define DDRSS0_PHY_124_DATA 0x00A000A0 +#define DDRSS0_PHY_125_DATA 0x00A000A0 +#define DDRSS0_PHY_126_DATA 0x00A000A0 +#define DDRSS0_PHY_127_DATA 0x00A000A0 +#define DDRSS0_PHY_128_DATA 0x00A000A0 +#define DDRSS0_PHY_129_DATA 0x00A000A0 +#define DDRSS0_PHY_130_DATA 0x01C200A0 +#define DDRSS0_PHY_131_DATA 0x01A00005 +#define DDRSS0_PHY_132_DATA 0x00000000 +#define DDRSS0_PHY_133_DATA 0x00000000 +#define DDRSS0_PHY_134_DATA 0x00080200 +#define DDRSS0_PHY_135_DATA 0x00000000 +#define DDRSS0_PHY_136_DATA 0x20202020 +#define DDRSS0_PHY_137_DATA 0x20202020 +#define DDRSS0_PHY_138_DATA 0xF0F02020 +#define DDRSS0_PHY_139_DATA 0x00000000 +#define DDRSS0_PHY_140_DATA 0x00000000 +#define DDRSS0_PHY_141_DATA 0x00000000 +#define DDRSS0_PHY_142_DATA 0x00000000 +#define DDRSS0_PHY_143_DATA 0x00000000 +#define DDRSS0_PHY_144_DATA 0x00000000 +#define DDRSS0_PHY_145_DATA 0x00000000 +#define DDRSS0_PHY_146_DATA 0x00000000 +#define DDRSS0_PHY_147_DATA 0x00000000 +#define DDRSS0_PHY_148_DATA 0x00000000 +#define DDRSS0_PHY_149_DATA 0x00000000 +#define DDRSS0_PHY_150_DATA 0x00000000 +#define DDRSS0_PHY_151_DATA 0x00000000 +#define DDRSS0_PHY_152_DATA 0x00000000 +#define DDRSS0_PHY_153_DATA 0x00000000 +#define DDRSS0_PHY_154_DATA 0x00000000 +#define DDRSS0_PHY_155_DATA 0x00000000 +#define DDRSS0_PHY_156_DATA 0x00000000 +#define DDRSS0_PHY_157_DATA 0x00000000 +#define DDRSS0_PHY_158_DATA 0x00000000 +#define DDRSS0_PHY_159_DATA 0x00000000 +#define DDRSS0_PHY_160_DATA 0x00000000 +#define DDRSS0_PHY_161_DATA 0x00000000 +#define DDRSS0_PHY_162_DATA 0x00000000 +#define DDRSS0_PHY_163_DATA 0x00000000 +#define DDRSS0_PHY_164_DATA 0x00000000 +#define DDRSS0_PHY_165_DATA 0x00000000 +#define DDRSS0_PHY_166_DATA 0x00000000 +#define DDRSS0_PHY_167_DATA 0x00000000 +#define DDRSS0_PHY_168_DATA 0x00000000 +#define DDRSS0_PHY_169_DATA 0x00000000 +#define DDRSS0_PHY_170_DATA 0x00000000 +#define DDRSS0_PHY_171_DATA 0x00000000 +#define DDRSS0_PHY_172_DATA 0x00000000 +#define DDRSS0_PHY_173_DATA 0x00000000 +#define DDRSS0_PHY_174_DATA 0x00000000 +#define DDRSS0_PHY_175_DATA 0x00000000 +#define DDRSS0_PHY_176_DATA 0x00000000 +#define DDRSS0_PHY_177_DATA 0x00000000 +#define DDRSS0_PHY_178_DATA 0x00000000 +#define DDRSS0_PHY_179_DATA 0x00000000 +#define DDRSS0_PHY_180_DATA 0x00000000 +#define DDRSS0_PHY_181_DATA 0x00000000 +#define DDRSS0_PHY_182_DATA 0x00000000 +#define DDRSS0_PHY_183_DATA 0x00000000 +#define DDRSS0_PHY_184_DATA 0x00000000 +#define DDRSS0_PHY_185_DATA 0x00000000 +#define DDRSS0_PHY_186_DATA 0x00000000 +#define DDRSS0_PHY_187_DATA 0x00000000 +#define DDRSS0_PHY_188_DATA 0x00000000 +#define DDRSS0_PHY_189_DATA 0x00000000 +#define DDRSS0_PHY_190_DATA 0x00000000 +#define DDRSS0_PHY_191_DATA 0x00000000 +#define DDRSS0_PHY_192_DATA 0x00000000 +#define DDRSS0_PHY_193_DATA 0x00000000 +#define DDRSS0_PHY_194_DATA 0x00000000 +#define DDRSS0_PHY_195_DATA 0x00000000 +#define DDRSS0_PHY_196_DATA 0x00000000 +#define DDRSS0_PHY_197_DATA 0x00000000 +#define DDRSS0_PHY_198_DATA 0x00000000 +#define DDRSS0_PHY_199_DATA 0x00000000 +#define DDRSS0_PHY_200_DATA 0x00000000 +#define DDRSS0_PHY_201_DATA 0x00000000 +#define DDRSS0_PHY_202_DATA 0x00000000 +#define DDRSS0_PHY_203_DATA 0x00000000 +#define DDRSS0_PHY_204_DATA 0x00000000 +#define DDRSS0_PHY_205_DATA 0x00000000 +#define DDRSS0_PHY_206_DATA 0x00000000 +#define DDRSS0_PHY_207_DATA 0x00000000 +#define DDRSS0_PHY_208_DATA 0x00000000 +#define DDRSS0_PHY_209_DATA 0x00000000 +#define DDRSS0_PHY_210_DATA 0x00000000 +#define DDRSS0_PHY_211_DATA 0x00000000 +#define DDRSS0_PHY_212_DATA 0x00000000 +#define DDRSS0_PHY_213_DATA 0x00000000 +#define DDRSS0_PHY_214_DATA 0x00000000 +#define DDRSS0_PHY_215_DATA 0x00000000 +#define DDRSS0_PHY_216_DATA 0x00000000 +#define DDRSS0_PHY_217_DATA 0x00000000 +#define DDRSS0_PHY_218_DATA 0x00000000 +#define DDRSS0_PHY_219_DATA 0x00000000 +#define DDRSS0_PHY_220_DATA 0x00000000 +#define DDRSS0_PHY_221_DATA 0x00000000 +#define DDRSS0_PHY_222_DATA 0x00000000 +#define DDRSS0_PHY_223_DATA 0x00000000 +#define DDRSS0_PHY_224_DATA 0x00000000 +#define DDRSS0_PHY_225_DATA 0x00000000 +#define DDRSS0_PHY_226_DATA 0x00000000 +#define DDRSS0_PHY_227_DATA 0x00000000 +#define DDRSS0_PHY_228_DATA 0x00000000 +#define DDRSS0_PHY_229_DATA 0x00000000 +#define DDRSS0_PHY_230_DATA 0x00000000 +#define DDRSS0_PHY_231_DATA 0x00000000 +#define DDRSS0_PHY_232_DATA 0x00000000 +#define DDRSS0_PHY_233_DATA 0x00000000 +#define DDRSS0_PHY_234_DATA 0x00000000 +#define DDRSS0_PHY_235_DATA 0x00000000 +#define DDRSS0_PHY_236_DATA 0x00000000 +#define DDRSS0_PHY_237_DATA 0x00000000 +#define DDRSS0_PHY_238_DATA 0x00000000 +#define DDRSS0_PHY_239_DATA 0x00000000 +#define DDRSS0_PHY_240_DATA 0x00000000 +#define DDRSS0_PHY_241_DATA 0x00000000 +#define DDRSS0_PHY_242_DATA 0x00000000 +#define DDRSS0_PHY_243_DATA 0x00000000 +#define DDRSS0_PHY_244_DATA 0x00000000 +#define DDRSS0_PHY_245_DATA 0x00000000 +#define DDRSS0_PHY_246_DATA 0x00000000 +#define DDRSS0_PHY_247_DATA 0x00000000 +#define DDRSS0_PHY_248_DATA 0x00000000 +#define DDRSS0_PHY_249_DATA 0x00000000 +#define DDRSS0_PHY_250_DATA 0x00000000 +#define DDRSS0_PHY_251_DATA 0x00000000 +#define DDRSS0_PHY_252_DATA 0x00000000 +#define DDRSS0_PHY_253_DATA 0x00000000 +#define DDRSS0_PHY_254_DATA 0x00000000 +#define DDRSS0_PHY_255_DATA 0x00000000 +#define DDRSS0_PHY_256_DATA 0x000004F0 +#define DDRSS0_PHY_257_DATA 0x00000000 +#define DDRSS0_PHY_258_DATA 0x00030200 +#define DDRSS0_PHY_259_DATA 0x00000000 +#define DDRSS0_PHY_260_DATA 0x00000000 +#define DDRSS0_PHY_261_DATA 0x01030000 +#define DDRSS0_PHY_262_DATA 0x00010000 +#define DDRSS0_PHY_263_DATA 0x01030004 +#define DDRSS0_PHY_264_DATA 0x01000000 +#define DDRSS0_PHY_265_DATA 0x00000000 +#define DDRSS0_PHY_266_DATA 0x00000000 +#define DDRSS0_PHY_267_DATA 0x01000001 +#define DDRSS0_PHY_268_DATA 0x00000200 +#define DDRSS0_PHY_269_DATA 0x000800C0 +#define DDRSS0_PHY_270_DATA 0x060100CC +#define DDRSS0_PHY_271_DATA 0x00030066 +#define DDRSS0_PHY_272_DATA 0x00000000 +#define DDRSS0_PHY_273_DATA 0x00000301 +#define DDRSS0_PHY_274_DATA 0x0000AAAA +#define DDRSS0_PHY_275_DATA 0x00005555 +#define DDRSS0_PHY_276_DATA 0x0000B5B5 +#define DDRSS0_PHY_277_DATA 0x00004A4A +#define DDRSS0_PHY_278_DATA 0x00005656 +#define DDRSS0_PHY_279_DATA 0x0000A9A9 +#define DDRSS0_PHY_280_DATA 0x0000A9A9 +#define DDRSS0_PHY_281_DATA 0x0000B5B5 +#define DDRSS0_PHY_282_DATA 0x00000000 +#define DDRSS0_PHY_283_DATA 0x00000000 +#define DDRSS0_PHY_284_DATA 0x2A000000 +#define DDRSS0_PHY_285_DATA 0x00000808 +#define DDRSS0_PHY_286_DATA 0x0F000000 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002002 +#define DDRSS0_PHY_290_DATA 0x00000000 +#define DDRSS0_PHY_291_DATA 0x00000000 +#define DDRSS0_PHY_292_DATA 0x55555555 +#define DDRSS0_PHY_293_DATA 0xAAAAAAAA +#define DDRSS0_PHY_294_DATA 0x55555555 +#define DDRSS0_PHY_295_DATA 0xAAAAAAAA +#define DDRSS0_PHY_296_DATA 0x00005555 +#define DDRSS0_PHY_297_DATA 0x01000100 +#define DDRSS0_PHY_298_DATA 0x00800180 +#define DDRSS0_PHY_299_DATA 0x00000000 +#define DDRSS0_PHY_300_DATA 0x00000000 +#define DDRSS0_PHY_301_DATA 0x00000000 +#define DDRSS0_PHY_302_DATA 0x00000000 +#define DDRSS0_PHY_303_DATA 0x00000000 +#define DDRSS0_PHY_304_DATA 0x00000000 +#define DDRSS0_PHY_305_DATA 0x00000000 +#define DDRSS0_PHY_306_DATA 0x00000000 +#define DDRSS0_PHY_307_DATA 0x00000000 +#define DDRSS0_PHY_308_DATA 0x00000000 +#define DDRSS0_PHY_309_DATA 0x00000000 +#define DDRSS0_PHY_310_DATA 0x00000000 +#define DDRSS0_PHY_311_DATA 0x00000000 +#define DDRSS0_PHY_312_DATA 0x00000000 +#define DDRSS0_PHY_313_DATA 0x00000000 +#define DDRSS0_PHY_314_DATA 0x00000000 +#define DDRSS0_PHY_315_DATA 0x00000000 +#define DDRSS0_PHY_316_DATA 0x00000000 +#define DDRSS0_PHY_317_DATA 0x00000000 +#define DDRSS0_PHY_318_DATA 0x00000000 +#define DDRSS0_PHY_319_DATA 0x00000000 +#define DDRSS0_PHY_320_DATA 0x00000000 +#define DDRSS0_PHY_321_DATA 0x00000000 +#define DDRSS0_PHY_322_DATA 0x00000104 +#define DDRSS0_PHY_323_DATA 0x00000120 +#define DDRSS0_PHY_324_DATA 0x00000000 +#define DDRSS0_PHY_325_DATA 0x00000000 +#define DDRSS0_PHY_326_DATA 0x00000000 +#define DDRSS0_PHY_327_DATA 0x00000000 +#define DDRSS0_PHY_328_DATA 0x00000000 +#define DDRSS0_PHY_329_DATA 0x00000000 +#define DDRSS0_PHY_330_DATA 0x00000000 +#define DDRSS0_PHY_331_DATA 0x00000001 +#define DDRSS0_PHY_332_DATA 0x07FF0000 +#define DDRSS0_PHY_333_DATA 0x0080081F +#define DDRSS0_PHY_334_DATA 0x00081020 +#define DDRSS0_PHY_335_DATA 0x04010000 +#define DDRSS0_PHY_336_DATA 0x00000000 +#define DDRSS0_PHY_337_DATA 0x00000000 +#define DDRSS0_PHY_338_DATA 0x00000000 +#define DDRSS0_PHY_339_DATA 0x00000100 +#define DDRSS0_PHY_340_DATA 0x01CC0C01 +#define DDRSS0_PHY_341_DATA 0x1003CC0C +#define DDRSS0_PHY_342_DATA 0x20000140 +#define DDRSS0_PHY_343_DATA 0x07FF0200 +#define DDRSS0_PHY_344_DATA 0x0000DD01 +#define DDRSS0_PHY_345_DATA 0x10100303 +#define DDRSS0_PHY_346_DATA 0x10101010 +#define DDRSS0_PHY_347_DATA 0x10101010 +#define DDRSS0_PHY_348_DATA 0x00021010 +#define DDRSS0_PHY_349_DATA 0x00100010 +#define DDRSS0_PHY_350_DATA 0x00100010 +#define DDRSS0_PHY_351_DATA 0x00100010 +#define DDRSS0_PHY_352_DATA 0x00100010 +#define DDRSS0_PHY_353_DATA 0x00050010 +#define DDRSS0_PHY_354_DATA 0x51517041 +#define DDRSS0_PHY_355_DATA 0x31C06001 +#define DDRSS0_PHY_356_DATA 0x07AB01AB +#define DDRSS0_PHY_357_DATA 0x00C0C001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 +#define DDRSS0_PHY_359_DATA 0x10001000 +#define DDRSS0_PHY_360_DATA 0x0C083E42 +#define DDRSS0_PHY_361_DATA 0x0F0C3701 +#define DDRSS0_PHY_362_DATA 0x01000140 +#define DDRSS0_PHY_363_DATA 0x0C000420 +#define DDRSS0_PHY_364_DATA 0x00000198 +#define DDRSS0_PHY_365_DATA 0x0A0000D0 +#define DDRSS0_PHY_366_DATA 0x00030200 +#define DDRSS0_PHY_367_DATA 0x02800000 +#define DDRSS0_PHY_368_DATA 0x80800000 +#define DDRSS0_PHY_369_DATA 0x000E2010 +#define DDRSS0_PHY_370_DATA 0x76543210 +#define DDRSS0_PHY_371_DATA 0x00000008 +#define DDRSS0_PHY_372_DATA 0x02800280 +#define DDRSS0_PHY_373_DATA 0x02800280 +#define DDRSS0_PHY_374_DATA 0x02800280 +#define DDRSS0_PHY_375_DATA 0x02800280 +#define DDRSS0_PHY_376_DATA 0x00000280 +#define DDRSS0_PHY_377_DATA 0x0000A000 +#define DDRSS0_PHY_378_DATA 0x00A000A0 +#define DDRSS0_PHY_379_DATA 0x00A000A0 +#define DDRSS0_PHY_380_DATA 0x00A000A0 +#define DDRSS0_PHY_381_DATA 0x00A000A0 +#define DDRSS0_PHY_382_DATA 0x00A000A0 +#define DDRSS0_PHY_383_DATA 0x00A000A0 +#define DDRSS0_PHY_384_DATA 0x00A000A0 +#define DDRSS0_PHY_385_DATA 0x00A000A0 +#define DDRSS0_PHY_386_DATA 0x01C200A0 +#define DDRSS0_PHY_387_DATA 0x01A00005 +#define DDRSS0_PHY_388_DATA 0x00000000 +#define DDRSS0_PHY_389_DATA 0x00000000 +#define DDRSS0_PHY_390_DATA 0x00080200 +#define DDRSS0_PHY_391_DATA 0x00000000 +#define DDRSS0_PHY_392_DATA 0x20202020 +#define DDRSS0_PHY_393_DATA 0x20202020 +#define DDRSS0_PHY_394_DATA 0xF0F02020 +#define DDRSS0_PHY_395_DATA 0x00000000 +#define DDRSS0_PHY_396_DATA 0x00000000 +#define DDRSS0_PHY_397_DATA 0x00000000 +#define DDRSS0_PHY_398_DATA 0x00000000 +#define DDRSS0_PHY_399_DATA 0x00000000 +#define DDRSS0_PHY_400_DATA 0x00000000 +#define DDRSS0_PHY_401_DATA 0x00000000 +#define DDRSS0_PHY_402_DATA 0x00000000 +#define DDRSS0_PHY_403_DATA 0x00000000 +#define DDRSS0_PHY_404_DATA 0x00000000 +#define DDRSS0_PHY_405_DATA 0x00000000 +#define DDRSS0_PHY_406_DATA 0x00000000 +#define DDRSS0_PHY_407_DATA 0x00000000 +#define DDRSS0_PHY_408_DATA 0x00000000 +#define DDRSS0_PHY_409_DATA 0x00000000 +#define DDRSS0_PHY_410_DATA 0x00000000 +#define DDRSS0_PHY_411_DATA 0x00000000 +#define DDRSS0_PHY_412_DATA 0x00000000 +#define DDRSS0_PHY_413_DATA 0x00000000 +#define DDRSS0_PHY_414_DATA 0x00000000 +#define DDRSS0_PHY_415_DATA 0x00000000 +#define DDRSS0_PHY_416_DATA 0x00000000 +#define DDRSS0_PHY_417_DATA 0x00000000 +#define DDRSS0_PHY_418_DATA 0x00000000 +#define DDRSS0_PHY_419_DATA 0x00000000 +#define DDRSS0_PHY_420_DATA 0x00000000 +#define DDRSS0_PHY_421_DATA 0x00000000 +#define DDRSS0_PHY_422_DATA 0x00000000 +#define DDRSS0_PHY_423_DATA 0x00000000 +#define DDRSS0_PHY_424_DATA 0x00000000 +#define DDRSS0_PHY_425_DATA 0x00000000 +#define DDRSS0_PHY_426_DATA 0x00000000 +#define DDRSS0_PHY_427_DATA 0x00000000 +#define DDRSS0_PHY_428_DATA 0x00000000 +#define DDRSS0_PHY_429_DATA 0x00000000 +#define DDRSS0_PHY_430_DATA 0x00000000 +#define DDRSS0_PHY_431_DATA 0x00000000 +#define DDRSS0_PHY_432_DATA 0x00000000 +#define DDRSS0_PHY_433_DATA 0x00000000 +#define DDRSS0_PHY_434_DATA 0x00000000 +#define DDRSS0_PHY_435_DATA 0x00000000 +#define DDRSS0_PHY_436_DATA 0x00000000 +#define DDRSS0_PHY_437_DATA 0x00000000 +#define DDRSS0_PHY_438_DATA 0x00000000 +#define DDRSS0_PHY_439_DATA 0x00000000 +#define DDRSS0_PHY_440_DATA 0x00000000 +#define DDRSS0_PHY_441_DATA 0x00000000 +#define DDRSS0_PHY_442_DATA 0x00000000 +#define DDRSS0_PHY_443_DATA 0x00000000 +#define DDRSS0_PHY_444_DATA 0x00000000 +#define DDRSS0_PHY_445_DATA 0x00000000 +#define DDRSS0_PHY_446_DATA 0x00000000 +#define DDRSS0_PHY_447_DATA 0x00000000 +#define DDRSS0_PHY_448_DATA 0x00000000 +#define DDRSS0_PHY_449_DATA 0x00000000 +#define DDRSS0_PHY_450_DATA 0x00000000 +#define DDRSS0_PHY_451_DATA 0x00000000 +#define DDRSS0_PHY_452_DATA 0x00000000 +#define DDRSS0_PHY_453_DATA 0x00000000 +#define DDRSS0_PHY_454_DATA 0x00000000 +#define DDRSS0_PHY_455_DATA 0x00000000 +#define DDRSS0_PHY_456_DATA 0x00000000 +#define DDRSS0_PHY_457_DATA 0x00000000 +#define DDRSS0_PHY_458_DATA 0x00000000 +#define DDRSS0_PHY_459_DATA 0x00000000 +#define DDRSS0_PHY_460_DATA 0x00000000 +#define DDRSS0_PHY_461_DATA 0x00000000 +#define DDRSS0_PHY_462_DATA 0x00000000 +#define DDRSS0_PHY_463_DATA 0x00000000 +#define DDRSS0_PHY_464_DATA 0x00000000 +#define DDRSS0_PHY_465_DATA 0x00000000 +#define DDRSS0_PHY_466_DATA 0x00000000 +#define DDRSS0_PHY_467_DATA 0x00000000 +#define DDRSS0_PHY_468_DATA 0x00000000 +#define DDRSS0_PHY_469_DATA 0x00000000 +#define DDRSS0_PHY_470_DATA 0x00000000 +#define DDRSS0_PHY_471_DATA 0x00000000 +#define DDRSS0_PHY_472_DATA 0x00000000 +#define DDRSS0_PHY_473_DATA 0x00000000 +#define DDRSS0_PHY_474_DATA 0x00000000 +#define DDRSS0_PHY_475_DATA 0x00000000 +#define DDRSS0_PHY_476_DATA 0x00000000 +#define DDRSS0_PHY_477_DATA 0x00000000 +#define DDRSS0_PHY_478_DATA 0x00000000 +#define DDRSS0_PHY_479_DATA 0x00000000 +#define DDRSS0_PHY_480_DATA 0x00000000 +#define DDRSS0_PHY_481_DATA 0x00000000 +#define DDRSS0_PHY_482_DATA 0x00000000 +#define DDRSS0_PHY_483_DATA 0x00000000 +#define DDRSS0_PHY_484_DATA 0x00000000 +#define DDRSS0_PHY_485_DATA 0x00000000 +#define DDRSS0_PHY_486_DATA 0x00000000 +#define DDRSS0_PHY_487_DATA 0x00000000 +#define DDRSS0_PHY_488_DATA 0x00000000 +#define DDRSS0_PHY_489_DATA 0x00000000 +#define DDRSS0_PHY_490_DATA 0x00000000 +#define DDRSS0_PHY_491_DATA 0x00000000 +#define DDRSS0_PHY_492_DATA 0x00000000 +#define DDRSS0_PHY_493_DATA 0x00000000 +#define DDRSS0_PHY_494_DATA 0x00000000 +#define DDRSS0_PHY_495_DATA 0x00000000 +#define DDRSS0_PHY_496_DATA 0x00000000 +#define DDRSS0_PHY_497_DATA 0x00000000 +#define DDRSS0_PHY_498_DATA 0x00000000 +#define DDRSS0_PHY_499_DATA 0x00000000 +#define DDRSS0_PHY_500_DATA 0x00000000 +#define DDRSS0_PHY_501_DATA 0x00000000 +#define DDRSS0_PHY_502_DATA 0x00000000 +#define DDRSS0_PHY_503_DATA 0x00000000 +#define DDRSS0_PHY_504_DATA 0x00000000 +#define DDRSS0_PHY_505_DATA 0x00000000 +#define DDRSS0_PHY_506_DATA 0x00000000 +#define DDRSS0_PHY_507_DATA 0x00000000 +#define DDRSS0_PHY_508_DATA 0x00000000 +#define DDRSS0_PHY_509_DATA 0x00000000 +#define DDRSS0_PHY_510_DATA 0x00000000 +#define DDRSS0_PHY_511_DATA 0x00000000 +#define DDRSS0_PHY_512_DATA 0x000004F0 +#define DDRSS0_PHY_513_DATA 0x00000000 +#define DDRSS0_PHY_514_DATA 0x00030200 +#define DDRSS0_PHY_515_DATA 0x00000000 +#define DDRSS0_PHY_516_DATA 0x00000000 +#define DDRSS0_PHY_517_DATA 0x01030000 +#define DDRSS0_PHY_518_DATA 0x00010000 +#define DDRSS0_PHY_519_DATA 0x01030004 +#define DDRSS0_PHY_520_DATA 0x01000000 +#define DDRSS0_PHY_521_DATA 0x00000000 +#define DDRSS0_PHY_522_DATA 0x00000000 +#define DDRSS0_PHY_523_DATA 0x01000001 +#define DDRSS0_PHY_524_DATA 0x00000200 +#define DDRSS0_PHY_525_DATA 0x000800C0 +#define DDRSS0_PHY_526_DATA 0x060100CC +#define DDRSS0_PHY_527_DATA 0x00030066 +#define DDRSS0_PHY_528_DATA 0x00000000 +#define DDRSS0_PHY_529_DATA 0x00000301 +#define DDRSS0_PHY_530_DATA 0x0000AAAA +#define DDRSS0_PHY_531_DATA 0x00005555 +#define DDRSS0_PHY_532_DATA 0x0000B5B5 +#define DDRSS0_PHY_533_DATA 0x00004A4A +#define DDRSS0_PHY_534_DATA 0x00005656 +#define DDRSS0_PHY_535_DATA 0x0000A9A9 +#define DDRSS0_PHY_536_DATA 0x0000A9A9 +#define DDRSS0_PHY_537_DATA 0x0000B5B5 +#define DDRSS0_PHY_538_DATA 0x00000000 +#define DDRSS0_PHY_539_DATA 0x00000000 +#define DDRSS0_PHY_540_DATA 0x2A000000 +#define DDRSS0_PHY_541_DATA 0x00000808 +#define DDRSS0_PHY_542_DATA 0x0F000000 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002002 +#define DDRSS0_PHY_546_DATA 0x00000000 +#define DDRSS0_PHY_547_DATA 0x00000000 +#define DDRSS0_PHY_548_DATA 0x55555555 +#define DDRSS0_PHY_549_DATA 0xAAAAAAAA +#define DDRSS0_PHY_550_DATA 0x55555555 +#define DDRSS0_PHY_551_DATA 0xAAAAAAAA +#define DDRSS0_PHY_552_DATA 0x00005555 +#define DDRSS0_PHY_553_DATA 0x01000100 +#define DDRSS0_PHY_554_DATA 0x00800180 +#define DDRSS0_PHY_555_DATA 0x00000001 +#define DDRSS0_PHY_556_DATA 0x00000000 +#define DDRSS0_PHY_557_DATA 0x00000000 +#define DDRSS0_PHY_558_DATA 0x00000000 +#define DDRSS0_PHY_559_DATA 0x00000000 +#define DDRSS0_PHY_560_DATA 0x00000000 +#define DDRSS0_PHY_561_DATA 0x00000000 +#define DDRSS0_PHY_562_DATA 0x00000000 +#define DDRSS0_PHY_563_DATA 0x00000000 +#define DDRSS0_PHY_564_DATA 0x00000000 +#define DDRSS0_PHY_565_DATA 0x00000000 +#define DDRSS0_PHY_566_DATA 0x00000000 +#define DDRSS0_PHY_567_DATA 0x00000000 +#define DDRSS0_PHY_568_DATA 0x00000000 +#define DDRSS0_PHY_569_DATA 0x00000000 +#define DDRSS0_PHY_570_DATA 0x00000000 +#define DDRSS0_PHY_571_DATA 0x00000000 +#define DDRSS0_PHY_572_DATA 0x00000000 +#define DDRSS0_PHY_573_DATA 0x00000000 +#define DDRSS0_PHY_574_DATA 0x00000000 +#define DDRSS0_PHY_575_DATA 0x00000000 +#define DDRSS0_PHY_576_DATA 0x00000000 +#define DDRSS0_PHY_577_DATA 0x00000000 +#define DDRSS0_PHY_578_DATA 0x00000104 +#define DDRSS0_PHY_579_DATA 0x00000120 +#define DDRSS0_PHY_580_DATA 0x00000000 +#define DDRSS0_PHY_581_DATA 0x00000000 +#define DDRSS0_PHY_582_DATA 0x00000000 +#define DDRSS0_PHY_583_DATA 0x00000000 +#define DDRSS0_PHY_584_DATA 0x00000000 +#define DDRSS0_PHY_585_DATA 0x00000000 +#define DDRSS0_PHY_586_DATA 0x00000000 +#define DDRSS0_PHY_587_DATA 0x00000001 +#define DDRSS0_PHY_588_DATA 0x07FF0000 +#define DDRSS0_PHY_589_DATA 0x0080081F +#define DDRSS0_PHY_590_DATA 0x00081020 +#define DDRSS0_PHY_591_DATA 0x04010000 +#define DDRSS0_PHY_592_DATA 0x00000000 +#define DDRSS0_PHY_593_DATA 0x00000000 +#define DDRSS0_PHY_594_DATA 0x00000000 +#define DDRSS0_PHY_595_DATA 0x00000100 +#define DDRSS0_PHY_596_DATA 0x01CC0C01 +#define DDRSS0_PHY_597_DATA 0x1003CC0C +#define DDRSS0_PHY_598_DATA 0x20000140 +#define DDRSS0_PHY_599_DATA 0x07FF0200 +#define DDRSS0_PHY_600_DATA 0x0000DD01 +#define DDRSS0_PHY_601_DATA 0x10100303 +#define DDRSS0_PHY_602_DATA 0x10101010 +#define DDRSS0_PHY_603_DATA 0x10101010 +#define DDRSS0_PHY_604_DATA 0x00021010 +#define DDRSS0_PHY_605_DATA 0x00100010 +#define DDRSS0_PHY_606_DATA 0x00100010 +#define DDRSS0_PHY_607_DATA 0x00100010 +#define DDRSS0_PHY_608_DATA 0x00100010 +#define DDRSS0_PHY_609_DATA 0x00050010 +#define DDRSS0_PHY_610_DATA 0x51517041 +#define DDRSS0_PHY_611_DATA 0x31C06001 +#define DDRSS0_PHY_612_DATA 0x07AB01AB +#define DDRSS0_PHY_613_DATA 0x00C0C001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 +#define DDRSS0_PHY_615_DATA 0x10001000 +#define DDRSS0_PHY_616_DATA 0x0C083E42 +#define DDRSS0_PHY_617_DATA 0x0F0C3701 +#define DDRSS0_PHY_618_DATA 0x01000140 +#define DDRSS0_PHY_619_DATA 0x0C000420 +#define DDRSS0_PHY_620_DATA 0x00000198 +#define DDRSS0_PHY_621_DATA 0x0A0000D0 +#define DDRSS0_PHY_622_DATA 0x00030200 +#define DDRSS0_PHY_623_DATA 0x02800000 +#define DDRSS0_PHY_624_DATA 0x80800000 +#define DDRSS0_PHY_625_DATA 0x000E2010 +#define DDRSS0_PHY_626_DATA 0x76543210 +#define DDRSS0_PHY_627_DATA 0x00000008 +#define DDRSS0_PHY_628_DATA 0x02800280 +#define DDRSS0_PHY_629_DATA 0x02800280 +#define DDRSS0_PHY_630_DATA 0x02800280 +#define DDRSS0_PHY_631_DATA 0x02800280 +#define DDRSS0_PHY_632_DATA 0x00000280 +#define DDRSS0_PHY_633_DATA 0x0000A000 +#define DDRSS0_PHY_634_DATA 0x00A000A0 +#define DDRSS0_PHY_635_DATA 0x00A000A0 +#define DDRSS0_PHY_636_DATA 0x00A000A0 +#define DDRSS0_PHY_637_DATA 0x00A000A0 +#define DDRSS0_PHY_638_DATA 0x00A000A0 +#define DDRSS0_PHY_639_DATA 0x00A000A0 +#define DDRSS0_PHY_640_DATA 0x00A000A0 +#define DDRSS0_PHY_641_DATA 0x00A000A0 +#define DDRSS0_PHY_642_DATA 0x01C200A0 +#define DDRSS0_PHY_643_DATA 0x01A00005 +#define DDRSS0_PHY_644_DATA 0x00000000 +#define DDRSS0_PHY_645_DATA 0x00000000 +#define DDRSS0_PHY_646_DATA 0x00080200 +#define DDRSS0_PHY_647_DATA 0x00000000 +#define DDRSS0_PHY_648_DATA 0x20202020 +#define DDRSS0_PHY_649_DATA 0x20202020 +#define DDRSS0_PHY_650_DATA 0xF0F02020 +#define DDRSS0_PHY_651_DATA 0x00000000 +#define DDRSS0_PHY_652_DATA 0x00000000 +#define DDRSS0_PHY_653_DATA 0x00000000 +#define DDRSS0_PHY_654_DATA 0x00000000 +#define DDRSS0_PHY_655_DATA 0x00000000 +#define DDRSS0_PHY_656_DATA 0x00000000 +#define DDRSS0_PHY_657_DATA 0x00000000 +#define DDRSS0_PHY_658_DATA 0x00000000 +#define DDRSS0_PHY_659_DATA 0x00000000 +#define DDRSS0_PHY_660_DATA 0x00000000 +#define DDRSS0_PHY_661_DATA 0x00000000 +#define DDRSS0_PHY_662_DATA 0x00000000 +#define DDRSS0_PHY_663_DATA 0x00000000 +#define DDRSS0_PHY_664_DATA 0x00000000 +#define DDRSS0_PHY_665_DATA 0x00000000 +#define DDRSS0_PHY_666_DATA 0x00000000 +#define DDRSS0_PHY_667_DATA 0x00000000 +#define DDRSS0_PHY_668_DATA 0x00000000 +#define DDRSS0_PHY_669_DATA 0x00000000 +#define DDRSS0_PHY_670_DATA 0x00000000 +#define DDRSS0_PHY_671_DATA 0x00000000 +#define DDRSS0_PHY_672_DATA 0x00000000 +#define DDRSS0_PHY_673_DATA 0x00000000 +#define DDRSS0_PHY_674_DATA 0x00000000 +#define DDRSS0_PHY_675_DATA 0x00000000 +#define DDRSS0_PHY_676_DATA 0x00000000 +#define DDRSS0_PHY_677_DATA 0x00000000 +#define DDRSS0_PHY_678_DATA 0x00000000 +#define DDRSS0_PHY_679_DATA 0x00000000 +#define DDRSS0_PHY_680_DATA 0x00000000 +#define DDRSS0_PHY_681_DATA 0x00000000 +#define DDRSS0_PHY_682_DATA 0x00000000 +#define DDRSS0_PHY_683_DATA 0x00000000 +#define DDRSS0_PHY_684_DATA 0x00000000 +#define DDRSS0_PHY_685_DATA 0x00000000 +#define DDRSS0_PHY_686_DATA 0x00000000 +#define DDRSS0_PHY_687_DATA 0x00000000 +#define DDRSS0_PHY_688_DATA 0x00000000 +#define DDRSS0_PHY_689_DATA 0x00000000 +#define DDRSS0_PHY_690_DATA 0x00000000 +#define DDRSS0_PHY_691_DATA 0x00000000 +#define DDRSS0_PHY_692_DATA 0x00000000 +#define DDRSS0_PHY_693_DATA 0x00000000 +#define DDRSS0_PHY_694_DATA 0x00000000 +#define DDRSS0_PHY_695_DATA 0x00000000 +#define DDRSS0_PHY_696_DATA 0x00000000 +#define DDRSS0_PHY_697_DATA 0x00000000 +#define DDRSS0_PHY_698_DATA 0x00000000 +#define DDRSS0_PHY_699_DATA 0x00000000 +#define DDRSS0_PHY_700_DATA 0x00000000 +#define DDRSS0_PHY_701_DATA 0x00000000 +#define DDRSS0_PHY_702_DATA 0x00000000 +#define DDRSS0_PHY_703_DATA 0x00000000 +#define DDRSS0_PHY_704_DATA 0x00000000 +#define DDRSS0_PHY_705_DATA 0x00000000 +#define DDRSS0_PHY_706_DATA 0x00000000 +#define DDRSS0_PHY_707_DATA 0x00000000 +#define DDRSS0_PHY_708_DATA 0x00000000 +#define DDRSS0_PHY_709_DATA 0x00000000 +#define DDRSS0_PHY_710_DATA 0x00000000 +#define DDRSS0_PHY_711_DATA 0x00000000 +#define DDRSS0_PHY_712_DATA 0x00000000 +#define DDRSS0_PHY_713_DATA 0x00000000 +#define DDRSS0_PHY_714_DATA 0x00000000 +#define DDRSS0_PHY_715_DATA 0x00000000 +#define DDRSS0_PHY_716_DATA 0x00000000 +#define DDRSS0_PHY_717_DATA 0x00000000 +#define DDRSS0_PHY_718_DATA 0x00000000 +#define DDRSS0_PHY_719_DATA 0x00000000 +#define DDRSS0_PHY_720_DATA 0x00000000 +#define DDRSS0_PHY_721_DATA 0x00000000 +#define DDRSS0_PHY_722_DATA 0x00000000 +#define DDRSS0_PHY_723_DATA 0x00000000 +#define DDRSS0_PHY_724_DATA 0x00000000 +#define DDRSS0_PHY_725_DATA 0x00000000 +#define DDRSS0_PHY_726_DATA 0x00000000 +#define DDRSS0_PHY_727_DATA 0x00000000 +#define DDRSS0_PHY_728_DATA 0x00000000 +#define DDRSS0_PHY_729_DATA 0x00000000 +#define DDRSS0_PHY_730_DATA 0x00000000 +#define DDRSS0_PHY_731_DATA 0x00000000 +#define DDRSS0_PHY_732_DATA 0x00000000 +#define DDRSS0_PHY_733_DATA 0x00000000 +#define DDRSS0_PHY_734_DATA 0x00000000 +#define DDRSS0_PHY_735_DATA 0x00000000 +#define DDRSS0_PHY_736_DATA 0x00000000 +#define DDRSS0_PHY_737_DATA 0x00000000 +#define DDRSS0_PHY_738_DATA 0x00000000 +#define DDRSS0_PHY_739_DATA 0x00000000 +#define DDRSS0_PHY_740_DATA 0x00000000 +#define DDRSS0_PHY_741_DATA 0x00000000 +#define DDRSS0_PHY_742_DATA 0x00000000 +#define DDRSS0_PHY_743_DATA 0x00000000 +#define DDRSS0_PHY_744_DATA 0x00000000 +#define DDRSS0_PHY_745_DATA 0x00000000 +#define DDRSS0_PHY_746_DATA 0x00000000 +#define DDRSS0_PHY_747_DATA 0x00000000 +#define DDRSS0_PHY_748_DATA 0x00000000 +#define DDRSS0_PHY_749_DATA 0x00000000 +#define DDRSS0_PHY_750_DATA 0x00000000 +#define DDRSS0_PHY_751_DATA 0x00000000 +#define DDRSS0_PHY_752_DATA 0x00000000 +#define DDRSS0_PHY_753_DATA 0x00000000 +#define DDRSS0_PHY_754_DATA 0x00000000 +#define DDRSS0_PHY_755_DATA 0x00000000 +#define DDRSS0_PHY_756_DATA 0x00000000 +#define DDRSS0_PHY_757_DATA 0x00000000 +#define DDRSS0_PHY_758_DATA 0x00000000 +#define DDRSS0_PHY_759_DATA 0x00000000 +#define DDRSS0_PHY_760_DATA 0x00000000 +#define DDRSS0_PHY_761_DATA 0x00000000 +#define DDRSS0_PHY_762_DATA 0x00000000 +#define DDRSS0_PHY_763_DATA 0x00000000 +#define DDRSS0_PHY_764_DATA 0x00000000 +#define DDRSS0_PHY_765_DATA 0x00000000 +#define DDRSS0_PHY_766_DATA 0x00000000 +#define DDRSS0_PHY_767_DATA 0x00000000 +#define DDRSS0_PHY_768_DATA 0x000004F0 +#define DDRSS0_PHY_769_DATA 0x00000000 +#define DDRSS0_PHY_770_DATA 0x00030200 +#define DDRSS0_PHY_771_DATA 0x00000000 +#define DDRSS0_PHY_772_DATA 0x00000000 +#define DDRSS0_PHY_773_DATA 0x01030000 +#define DDRSS0_PHY_774_DATA 0x00010000 +#define DDRSS0_PHY_775_DATA 0x01030004 +#define DDRSS0_PHY_776_DATA 0x01000000 +#define DDRSS0_PHY_777_DATA 0x00000000 +#define DDRSS0_PHY_778_DATA 0x00000000 +#define DDRSS0_PHY_779_DATA 0x01000001 +#define DDRSS0_PHY_780_DATA 0x00000200 +#define DDRSS0_PHY_781_DATA 0x000800C0 +#define DDRSS0_PHY_782_DATA 0x060100CC +#define DDRSS0_PHY_783_DATA 0x00030066 +#define DDRSS0_PHY_784_DATA 0x00000000 +#define DDRSS0_PHY_785_DATA 0x00000301 +#define DDRSS0_PHY_786_DATA 0x0000AAAA +#define DDRSS0_PHY_787_DATA 0x00005555 +#define DDRSS0_PHY_788_DATA 0x0000B5B5 +#define DDRSS0_PHY_789_DATA 0x00004A4A +#define DDRSS0_PHY_790_DATA 0x00005656 +#define DDRSS0_PHY_791_DATA 0x0000A9A9 +#define DDRSS0_PHY_792_DATA 0x0000A9A9 +#define DDRSS0_PHY_793_DATA 0x0000B5B5 +#define DDRSS0_PHY_794_DATA 0x00000000 +#define DDRSS0_PHY_795_DATA 0x00000000 +#define DDRSS0_PHY_796_DATA 0x2A000000 +#define DDRSS0_PHY_797_DATA 0x00000808 +#define DDRSS0_PHY_798_DATA 0x0F000000 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002002 +#define DDRSS0_PHY_802_DATA 0x00000000 +#define DDRSS0_PHY_803_DATA 0x00000000 +#define DDRSS0_PHY_804_DATA 0x55555555 +#define DDRSS0_PHY_805_DATA 0xAAAAAAAA +#define DDRSS0_PHY_806_DATA 0x55555555 +#define DDRSS0_PHY_807_DATA 0xAAAAAAAA +#define DDRSS0_PHY_808_DATA 0x00005555 +#define DDRSS0_PHY_809_DATA 0x01000100 +#define DDRSS0_PHY_810_DATA 0x00800180 +#define DDRSS0_PHY_811_DATA 0x00000000 +#define DDRSS0_PHY_812_DATA 0x00000000 +#define DDRSS0_PHY_813_DATA 0x00000000 +#define DDRSS0_PHY_814_DATA 0x00000000 +#define DDRSS0_PHY_815_DATA 0x00000000 +#define DDRSS0_PHY_816_DATA 0x00000000 +#define DDRSS0_PHY_817_DATA 0x00000000 +#define DDRSS0_PHY_818_DATA 0x00000000 +#define DDRSS0_PHY_819_DATA 0x00000000 +#define DDRSS0_PHY_820_DATA 0x00000000 +#define DDRSS0_PHY_821_DATA 0x00000000 +#define DDRSS0_PHY_822_DATA 0x00000000 +#define DDRSS0_PHY_823_DATA 0x00000000 +#define DDRSS0_PHY_824_DATA 0x00000000 +#define DDRSS0_PHY_825_DATA 0x00000000 +#define DDRSS0_PHY_826_DATA 0x00000000 +#define DDRSS0_PHY_827_DATA 0x00000000 +#define DDRSS0_PHY_828_DATA 0x00000000 +#define DDRSS0_PHY_829_DATA 0x00000000 +#define DDRSS0_PHY_830_DATA 0x00000000 +#define DDRSS0_PHY_831_DATA 0x00000000 +#define DDRSS0_PHY_832_DATA 0x00000000 +#define DDRSS0_PHY_833_DATA 0x00000000 +#define DDRSS0_PHY_834_DATA 0x00000104 +#define DDRSS0_PHY_835_DATA 0x00000120 +#define DDRSS0_PHY_836_DATA 0x00000000 +#define DDRSS0_PHY_837_DATA 0x00000000 +#define DDRSS0_PHY_838_DATA 0x00000000 +#define DDRSS0_PHY_839_DATA 0x00000000 +#define DDRSS0_PHY_840_DATA 0x00000000 +#define DDRSS0_PHY_841_DATA 0x00000000 +#define DDRSS0_PHY_842_DATA 0x00000000 +#define DDRSS0_PHY_843_DATA 0x00000001 +#define DDRSS0_PHY_844_DATA 0x07FF0000 +#define DDRSS0_PHY_845_DATA 0x0080081F +#define DDRSS0_PHY_846_DATA 0x00081020 +#define DDRSS0_PHY_847_DATA 0x04010000 +#define DDRSS0_PHY_848_DATA 0x00000000 +#define DDRSS0_PHY_849_DATA 0x00000000 +#define DDRSS0_PHY_850_DATA 0x00000000 +#define DDRSS0_PHY_851_DATA 0x00000100 +#define DDRSS0_PHY_852_DATA 0x01CC0C01 +#define DDRSS0_PHY_853_DATA 0x1003CC0C +#define DDRSS0_PHY_854_DATA 0x20000140 +#define DDRSS0_PHY_855_DATA 0x07FF0200 +#define DDRSS0_PHY_856_DATA 0x0000DD01 +#define DDRSS0_PHY_857_DATA 0x10100303 +#define DDRSS0_PHY_858_DATA 0x10101010 +#define DDRSS0_PHY_859_DATA 0x10101010 +#define DDRSS0_PHY_860_DATA 0x00021010 +#define DDRSS0_PHY_861_DATA 0x00100010 +#define DDRSS0_PHY_862_DATA 0x00100010 +#define DDRSS0_PHY_863_DATA 0x00100010 +#define DDRSS0_PHY_864_DATA 0x00100010 +#define DDRSS0_PHY_865_DATA 0x00050010 +#define DDRSS0_PHY_866_DATA 0x51517041 +#define DDRSS0_PHY_867_DATA 0x31C06001 +#define DDRSS0_PHY_868_DATA 0x07AB01AB +#define DDRSS0_PHY_869_DATA 0x00C0C001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 +#define DDRSS0_PHY_871_DATA 0x10001000 +#define DDRSS0_PHY_872_DATA 0x0C083E42 +#define DDRSS0_PHY_873_DATA 0x0F0C3701 +#define DDRSS0_PHY_874_DATA 0x01000140 +#define DDRSS0_PHY_875_DATA 0x0C000420 +#define DDRSS0_PHY_876_DATA 0x00000198 +#define DDRSS0_PHY_877_DATA 0x0A0000D0 +#define DDRSS0_PHY_878_DATA 0x00030200 +#define DDRSS0_PHY_879_DATA 0x02800000 +#define DDRSS0_PHY_880_DATA 0x80800000 +#define DDRSS0_PHY_881_DATA 0x000E2010 +#define DDRSS0_PHY_882_DATA 0x76543210 +#define DDRSS0_PHY_883_DATA 0x00000008 +#define DDRSS0_PHY_884_DATA 0x02800280 +#define DDRSS0_PHY_885_DATA 0x02800280 +#define DDRSS0_PHY_886_DATA 0x02800280 +#define DDRSS0_PHY_887_DATA 0x02800280 +#define DDRSS0_PHY_888_DATA 0x00000280 +#define DDRSS0_PHY_889_DATA 0x0000A000 +#define DDRSS0_PHY_890_DATA 0x00A000A0 +#define DDRSS0_PHY_891_DATA 0x00A000A0 +#define DDRSS0_PHY_892_DATA 0x00A000A0 +#define DDRSS0_PHY_893_DATA 0x00A000A0 +#define DDRSS0_PHY_894_DATA 0x00A000A0 +#define DDRSS0_PHY_895_DATA 0x00A000A0 +#define DDRSS0_PHY_896_DATA 0x00A000A0 +#define DDRSS0_PHY_897_DATA 0x00A000A0 +#define DDRSS0_PHY_898_DATA 0x01C200A0 +#define DDRSS0_PHY_899_DATA 0x01A00005 +#define DDRSS0_PHY_900_DATA 0x00000000 +#define DDRSS0_PHY_901_DATA 0x00000000 +#define DDRSS0_PHY_902_DATA 0x00080200 +#define DDRSS0_PHY_903_DATA 0x00000000 +#define DDRSS0_PHY_904_DATA 0x20202020 +#define DDRSS0_PHY_905_DATA 0x20202020 +#define DDRSS0_PHY_906_DATA 0xF0F02020 +#define DDRSS0_PHY_907_DATA 0x00000000 +#define DDRSS0_PHY_908_DATA 0x00000000 +#define DDRSS0_PHY_909_DATA 0x00000000 +#define DDRSS0_PHY_910_DATA 0x00000000 +#define DDRSS0_PHY_911_DATA 0x00000000 +#define DDRSS0_PHY_912_DATA 0x00000000 +#define DDRSS0_PHY_913_DATA 0x00000000 +#define DDRSS0_PHY_914_DATA 0x00000000 +#define DDRSS0_PHY_915_DATA 0x00000000 +#define DDRSS0_PHY_916_DATA 0x00000000 +#define DDRSS0_PHY_917_DATA 0x00000000 +#define DDRSS0_PHY_918_DATA 0x00000000 +#define DDRSS0_PHY_919_DATA 0x00000000 +#define DDRSS0_PHY_920_DATA 0x00000000 +#define DDRSS0_PHY_921_DATA 0x00000000 +#define DDRSS0_PHY_922_DATA 0x00000000 +#define DDRSS0_PHY_923_DATA 0x00000000 +#define DDRSS0_PHY_924_DATA 0x00000000 +#define DDRSS0_PHY_925_DATA 0x00000000 +#define DDRSS0_PHY_926_DATA 0x00000000 +#define DDRSS0_PHY_927_DATA 0x00000000 +#define DDRSS0_PHY_928_DATA 0x00000000 +#define DDRSS0_PHY_929_DATA 0x00000000 +#define DDRSS0_PHY_930_DATA 0x00000000 +#define DDRSS0_PHY_931_DATA 0x00000000 +#define DDRSS0_PHY_932_DATA 0x00000000 +#define DDRSS0_PHY_933_DATA 0x00000000 +#define DDRSS0_PHY_934_DATA 0x00000000 +#define DDRSS0_PHY_935_DATA 0x00000000 +#define DDRSS0_PHY_936_DATA 0x00000000 +#define DDRSS0_PHY_937_DATA 0x00000000 +#define DDRSS0_PHY_938_DATA 0x00000000 +#define DDRSS0_PHY_939_DATA 0x00000000 +#define DDRSS0_PHY_940_DATA 0x00000000 +#define DDRSS0_PHY_941_DATA 0x00000000 +#define DDRSS0_PHY_942_DATA 0x00000000 +#define DDRSS0_PHY_943_DATA 0x00000000 +#define DDRSS0_PHY_944_DATA 0x00000000 +#define DDRSS0_PHY_945_DATA 0x00000000 +#define DDRSS0_PHY_946_DATA 0x00000000 +#define DDRSS0_PHY_947_DATA 0x00000000 +#define DDRSS0_PHY_948_DATA 0x00000000 +#define DDRSS0_PHY_949_DATA 0x00000000 +#define DDRSS0_PHY_950_DATA 0x00000000 +#define DDRSS0_PHY_951_DATA 0x00000000 +#define DDRSS0_PHY_952_DATA 0x00000000 +#define DDRSS0_PHY_953_DATA 0x00000000 +#define DDRSS0_PHY_954_DATA 0x00000000 +#define DDRSS0_PHY_955_DATA 0x00000000 +#define DDRSS0_PHY_956_DATA 0x00000000 +#define DDRSS0_PHY_957_DATA 0x00000000 +#define DDRSS0_PHY_958_DATA 0x00000000 +#define DDRSS0_PHY_959_DATA 0x00000000 +#define DDRSS0_PHY_960_DATA 0x00000000 +#define DDRSS0_PHY_961_DATA 0x00000000 +#define DDRSS0_PHY_962_DATA 0x00000000 +#define DDRSS0_PHY_963_DATA 0x00000000 +#define DDRSS0_PHY_964_DATA 0x00000000 +#define DDRSS0_PHY_965_DATA 0x00000000 +#define DDRSS0_PHY_966_DATA 0x00000000 +#define DDRSS0_PHY_967_DATA 0x00000000 +#define DDRSS0_PHY_968_DATA 0x00000000 +#define DDRSS0_PHY_969_DATA 0x00000000 +#define DDRSS0_PHY_970_DATA 0x00000000 +#define DDRSS0_PHY_971_DATA 0x00000000 +#define DDRSS0_PHY_972_DATA 0x00000000 +#define DDRSS0_PHY_973_DATA 0x00000000 +#define DDRSS0_PHY_974_DATA 0x00000000 +#define DDRSS0_PHY_975_DATA 0x00000000 +#define DDRSS0_PHY_976_DATA 0x00000000 +#define DDRSS0_PHY_977_DATA 0x00000000 +#define DDRSS0_PHY_978_DATA 0x00000000 +#define DDRSS0_PHY_979_DATA 0x00000000 +#define DDRSS0_PHY_980_DATA 0x00000000 +#define DDRSS0_PHY_981_DATA 0x00000000 +#define DDRSS0_PHY_982_DATA 0x00000000 +#define DDRSS0_PHY_983_DATA 0x00000000 +#define DDRSS0_PHY_984_DATA 0x00000000 +#define DDRSS0_PHY_985_DATA 0x00000000 +#define DDRSS0_PHY_986_DATA 0x00000000 +#define DDRSS0_PHY_987_DATA 0x00000000 +#define DDRSS0_PHY_988_DATA 0x00000000 +#define DDRSS0_PHY_989_DATA 0x00000000 +#define DDRSS0_PHY_990_DATA 0x00000000 +#define DDRSS0_PHY_991_DATA 0x00000000 +#define DDRSS0_PHY_992_DATA 0x00000000 +#define DDRSS0_PHY_993_DATA 0x00000000 +#define DDRSS0_PHY_994_DATA 0x00000000 +#define DDRSS0_PHY_995_DATA 0x00000000 +#define DDRSS0_PHY_996_DATA 0x00000000 +#define DDRSS0_PHY_997_DATA 0x00000000 +#define DDRSS0_PHY_998_DATA 0x00000000 +#define DDRSS0_PHY_999_DATA 0x00000000 +#define DDRSS0_PHY_1000_DATA 0x00000000 +#define DDRSS0_PHY_1001_DATA 0x00000000 +#define DDRSS0_PHY_1002_DATA 0x00000000 +#define DDRSS0_PHY_1003_DATA 0x00000000 +#define DDRSS0_PHY_1004_DATA 0x00000000 +#define DDRSS0_PHY_1005_DATA 0x00000000 +#define DDRSS0_PHY_1006_DATA 0x00000000 +#define DDRSS0_PHY_1007_DATA 0x00000000 +#define DDRSS0_PHY_1008_DATA 0x00000000 +#define DDRSS0_PHY_1009_DATA 0x00000000 +#define DDRSS0_PHY_1010_DATA 0x00000000 +#define DDRSS0_PHY_1011_DATA 0x00000000 +#define DDRSS0_PHY_1012_DATA 0x00000000 +#define DDRSS0_PHY_1013_DATA 0x00000000 +#define DDRSS0_PHY_1014_DATA 0x00000000 +#define DDRSS0_PHY_1015_DATA 0x00000000 +#define DDRSS0_PHY_1016_DATA 0x00000000 +#define DDRSS0_PHY_1017_DATA 0x00000000 +#define DDRSS0_PHY_1018_DATA 0x00000000 +#define DDRSS0_PHY_1019_DATA 0x00000000 +#define DDRSS0_PHY_1020_DATA 0x00000000 +#define DDRSS0_PHY_1021_DATA 0x00000000 +#define DDRSS0_PHY_1022_DATA 0x00000000 +#define DDRSS0_PHY_1023_DATA 0x00000000 +#define DDRSS0_PHY_1024_DATA 0x00000000 +#define DDRSS0_PHY_1025_DATA 0x00000000 +#define DDRSS0_PHY_1026_DATA 0x00000000 +#define DDRSS0_PHY_1027_DATA 0x00000000 +#define DDRSS0_PHY_1028_DATA 0x00000000 +#define DDRSS0_PHY_1029_DATA 0x00000100 +#define DDRSS0_PHY_1030_DATA 0x00000200 +#define DDRSS0_PHY_1031_DATA 0x00000000 +#define DDRSS0_PHY_1032_DATA 0x00000000 +#define DDRSS0_PHY_1033_DATA 0x00000000 +#define DDRSS0_PHY_1034_DATA 0x00000000 +#define DDRSS0_PHY_1035_DATA 0x00400000 +#define DDRSS0_PHY_1036_DATA 0x00000080 +#define DDRSS0_PHY_1037_DATA 0x00DCBA98 +#define DDRSS0_PHY_1038_DATA 0x03000000 +#define DDRSS0_PHY_1039_DATA 0x00200000 +#define DDRSS0_PHY_1040_DATA 0x00000000 +#define DDRSS0_PHY_1041_DATA 0x00000000 +#define DDRSS0_PHY_1042_DATA 0x00000000 +#define DDRSS0_PHY_1043_DATA 0x00000000 +#define DDRSS0_PHY_1044_DATA 0x00000000 +#define DDRSS0_PHY_1045_DATA 0x0000002A +#define DDRSS0_PHY_1046_DATA 0x00000015 +#define DDRSS0_PHY_1047_DATA 0x00000015 +#define DDRSS0_PHY_1048_DATA 0x0000002A +#define DDRSS0_PHY_1049_DATA 0x00000033 +#define DDRSS0_PHY_1050_DATA 0x0000000C +#define DDRSS0_PHY_1051_DATA 0x0000000C +#define DDRSS0_PHY_1052_DATA 0x00000033 +#define DDRSS0_PHY_1053_DATA 0x00543210 +#define DDRSS0_PHY_1054_DATA 0x003F0000 +#define DDRSS0_PHY_1055_DATA 0x000F3F3F +#define DDRSS0_PHY_1056_DATA 0x20202003 +#define DDRSS0_PHY_1057_DATA 0x00202020 +#define DDRSS0_PHY_1058_DATA 0x20008008 +#define DDRSS0_PHY_1059_DATA 0x00000810 +#define DDRSS0_PHY_1060_DATA 0x00000F00 +#define DDRSS0_PHY_1061_DATA 0x00000000 +#define DDRSS0_PHY_1062_DATA 0x00000000 +#define DDRSS0_PHY_1063_DATA 0x00000000 +#define DDRSS0_PHY_1064_DATA 0x000305CC +#define DDRSS0_PHY_1065_DATA 0x00030000 +#define DDRSS0_PHY_1066_DATA 0x00000300 +#define DDRSS0_PHY_1067_DATA 0x00000300 +#define DDRSS0_PHY_1068_DATA 0x00000300 +#define DDRSS0_PHY_1069_DATA 0x00000300 +#define DDRSS0_PHY_1070_DATA 0x00000300 +#define DDRSS0_PHY_1071_DATA 0x42080010 +#define DDRSS0_PHY_1072_DATA 0x0000803E +#define DDRSS0_PHY_1073_DATA 0x00000001 +#define DDRSS0_PHY_1074_DATA 0x01000102 +#define DDRSS0_PHY_1075_DATA 0x00008000 +#define DDRSS0_PHY_1076_DATA 0x00000000 +#define DDRSS0_PHY_1077_DATA 0x00000000 +#define DDRSS0_PHY_1078_DATA 0x00000000 +#define DDRSS0_PHY_1079_DATA 0x00000000 +#define DDRSS0_PHY_1080_DATA 0x00000000 +#define DDRSS0_PHY_1081_DATA 0x00000000 +#define DDRSS0_PHY_1082_DATA 0x00000000 +#define DDRSS0_PHY_1083_DATA 0x00000000 +#define DDRSS0_PHY_1084_DATA 0x00000000 +#define DDRSS0_PHY_1085_DATA 0x00000000 +#define DDRSS0_PHY_1086_DATA 0x00000000 +#define DDRSS0_PHY_1087_DATA 0x00000000 +#define DDRSS0_PHY_1088_DATA 0x00000000 +#define DDRSS0_PHY_1089_DATA 0x00000000 +#define DDRSS0_PHY_1090_DATA 0x00000000 +#define DDRSS0_PHY_1091_DATA 0x00000000 +#define DDRSS0_PHY_1092_DATA 0x00000000 +#define DDRSS0_PHY_1093_DATA 0x00000000 +#define DDRSS0_PHY_1094_DATA 0x00000000 +#define DDRSS0_PHY_1095_DATA 0x00000000 +#define DDRSS0_PHY_1096_DATA 0x00000000 +#define DDRSS0_PHY_1097_DATA 0x00000000 +#define DDRSS0_PHY_1098_DATA 0x00000000 +#define DDRSS0_PHY_1099_DATA 0x00000000 +#define DDRSS0_PHY_1100_DATA 0x00000000 +#define DDRSS0_PHY_1101_DATA 0x00000000 +#define DDRSS0_PHY_1102_DATA 0x00000000 +#define DDRSS0_PHY_1103_DATA 0x00000000 +#define DDRSS0_PHY_1104_DATA 0x00000000 +#define DDRSS0_PHY_1105_DATA 0x00000000 +#define DDRSS0_PHY_1106_DATA 0x00000000 +#define DDRSS0_PHY_1107_DATA 0x00000000 +#define DDRSS0_PHY_1108_DATA 0x00000000 +#define DDRSS0_PHY_1109_DATA 0x00000000 +#define DDRSS0_PHY_1110_DATA 0x00000000 +#define DDRSS0_PHY_1111_DATA 0x00000000 +#define DDRSS0_PHY_1112_DATA 0x00000000 +#define DDRSS0_PHY_1113_DATA 0x00000000 +#define DDRSS0_PHY_1114_DATA 0x00000000 +#define DDRSS0_PHY_1115_DATA 0x00000000 +#define DDRSS0_PHY_1116_DATA 0x00000000 +#define DDRSS0_PHY_1117_DATA 0x00000000 +#define DDRSS0_PHY_1118_DATA 0x00000000 +#define DDRSS0_PHY_1119_DATA 0x00000000 +#define DDRSS0_PHY_1120_DATA 0x00000000 +#define DDRSS0_PHY_1121_DATA 0x00000000 +#define DDRSS0_PHY_1122_DATA 0x00000000 +#define DDRSS0_PHY_1123_DATA 0x00000000 +#define DDRSS0_PHY_1124_DATA 0x00000000 +#define DDRSS0_PHY_1125_DATA 0x00000000 +#define DDRSS0_PHY_1126_DATA 0x00000000 +#define DDRSS0_PHY_1127_DATA 0x00000000 +#define DDRSS0_PHY_1128_DATA 0x00000000 +#define DDRSS0_PHY_1129_DATA 0x00000000 +#define DDRSS0_PHY_1130_DATA 0x00000000 +#define DDRSS0_PHY_1131_DATA 0x00000000 +#define DDRSS0_PHY_1132_DATA 0x00000000 +#define DDRSS0_PHY_1133_DATA 0x00000000 +#define DDRSS0_PHY_1134_DATA 0x00000000 +#define DDRSS0_PHY_1135_DATA 0x00000000 +#define DDRSS0_PHY_1136_DATA 0x00000000 +#define DDRSS0_PHY_1137_DATA 0x00000000 +#define DDRSS0_PHY_1138_DATA 0x00000000 +#define DDRSS0_PHY_1139_DATA 0x00000000 +#define DDRSS0_PHY_1140_DATA 0x00000000 +#define DDRSS0_PHY_1141_DATA 0x00000000 +#define DDRSS0_PHY_1142_DATA 0x00000000 +#define DDRSS0_PHY_1143_DATA 0x00000000 +#define DDRSS0_PHY_1144_DATA 0x00000000 +#define DDRSS0_PHY_1145_DATA 0x00000000 +#define DDRSS0_PHY_1146_DATA 0x00000000 +#define DDRSS0_PHY_1147_DATA 0x00000000 +#define DDRSS0_PHY_1148_DATA 0x00000000 +#define DDRSS0_PHY_1149_DATA 0x00000000 +#define DDRSS0_PHY_1150_DATA 0x00000000 +#define DDRSS0_PHY_1151_DATA 0x00000000 +#define DDRSS0_PHY_1152_DATA 0x00000000 +#define DDRSS0_PHY_1153_DATA 0x00000000 +#define DDRSS0_PHY_1154_DATA 0x00000000 +#define DDRSS0_PHY_1155_DATA 0x00000000 +#define DDRSS0_PHY_1156_DATA 0x00000000 +#define DDRSS0_PHY_1157_DATA 0x00000000 +#define DDRSS0_PHY_1158_DATA 0x00000000 +#define DDRSS0_PHY_1159_DATA 0x00000000 +#define DDRSS0_PHY_1160_DATA 0x00000000 +#define DDRSS0_PHY_1161_DATA 0x00000000 +#define DDRSS0_PHY_1162_DATA 0x00000000 +#define DDRSS0_PHY_1163_DATA 0x00000000 +#define DDRSS0_PHY_1164_DATA 0x00000000 +#define DDRSS0_PHY_1165_DATA 0x00000000 +#define DDRSS0_PHY_1166_DATA 0x00000000 +#define DDRSS0_PHY_1167_DATA 0x00000000 +#define DDRSS0_PHY_1168_DATA 0x00000000 +#define DDRSS0_PHY_1169_DATA 0x00000000 +#define DDRSS0_PHY_1170_DATA 0x00000000 +#define DDRSS0_PHY_1171_DATA 0x00000000 +#define DDRSS0_PHY_1172_DATA 0x00000000 +#define DDRSS0_PHY_1173_DATA 0x00000000 +#define DDRSS0_PHY_1174_DATA 0x00000000 +#define DDRSS0_PHY_1175_DATA 0x00000000 +#define DDRSS0_PHY_1176_DATA 0x00000000 +#define DDRSS0_PHY_1177_DATA 0x00000000 +#define DDRSS0_PHY_1178_DATA 0x00000000 +#define DDRSS0_PHY_1179_DATA 0x00000000 +#define DDRSS0_PHY_1180_DATA 0x00000000 +#define DDRSS0_PHY_1181_DATA 0x00000000 +#define DDRSS0_PHY_1182_DATA 0x00000000 +#define DDRSS0_PHY_1183_DATA 0x00000000 +#define DDRSS0_PHY_1184_DATA 0x00000000 +#define DDRSS0_PHY_1185_DATA 0x00000000 +#define DDRSS0_PHY_1186_DATA 0x00000000 +#define DDRSS0_PHY_1187_DATA 0x00000000 +#define DDRSS0_PHY_1188_DATA 0x00000000 +#define DDRSS0_PHY_1189_DATA 0x00000000 +#define DDRSS0_PHY_1190_DATA 0x00000000 +#define DDRSS0_PHY_1191_DATA 0x00000000 +#define DDRSS0_PHY_1192_DATA 0x00000000 +#define DDRSS0_PHY_1193_DATA 0x00000000 +#define DDRSS0_PHY_1194_DATA 0x00000000 +#define DDRSS0_PHY_1195_DATA 0x00000000 +#define DDRSS0_PHY_1196_DATA 0x00000000 +#define DDRSS0_PHY_1197_DATA 0x00000000 +#define DDRSS0_PHY_1198_DATA 0x00000000 +#define DDRSS0_PHY_1199_DATA 0x00000000 +#define DDRSS0_PHY_1200_DATA 0x00000000 +#define DDRSS0_PHY_1201_DATA 0x00000000 +#define DDRSS0_PHY_1202_DATA 0x00000000 +#define DDRSS0_PHY_1203_DATA 0x00000000 +#define DDRSS0_PHY_1204_DATA 0x00000000 +#define DDRSS0_PHY_1205_DATA 0x00000000 +#define DDRSS0_PHY_1206_DATA 0x00000000 +#define DDRSS0_PHY_1207_DATA 0x00000000 +#define DDRSS0_PHY_1208_DATA 0x00000000 +#define DDRSS0_PHY_1209_DATA 0x00000000 +#define DDRSS0_PHY_1210_DATA 0x00000000 +#define DDRSS0_PHY_1211_DATA 0x00000000 +#define DDRSS0_PHY_1212_DATA 0x00000000 +#define DDRSS0_PHY_1213_DATA 0x00000000 +#define DDRSS0_PHY_1214_DATA 0x00000000 +#define DDRSS0_PHY_1215_DATA 0x00000000 +#define DDRSS0_PHY_1216_DATA 0x00000000 +#define DDRSS0_PHY_1217_DATA 0x00000000 +#define DDRSS0_PHY_1218_DATA 0x00000000 +#define DDRSS0_PHY_1219_DATA 0x00000000 +#define DDRSS0_PHY_1220_DATA 0x00000000 +#define DDRSS0_PHY_1221_DATA 0x00000000 +#define DDRSS0_PHY_1222_DATA 0x00000000 +#define DDRSS0_PHY_1223_DATA 0x00000000 +#define DDRSS0_PHY_1224_DATA 0x00000000 +#define DDRSS0_PHY_1225_DATA 0x00000000 +#define DDRSS0_PHY_1226_DATA 0x00000000 +#define DDRSS0_PHY_1227_DATA 0x00000000 +#define DDRSS0_PHY_1228_DATA 0x00000000 +#define DDRSS0_PHY_1229_DATA 0x00000000 +#define DDRSS0_PHY_1230_DATA 0x00000000 +#define DDRSS0_PHY_1231_DATA 0x00000000 +#define DDRSS0_PHY_1232_DATA 0x00000000 +#define DDRSS0_PHY_1233_DATA 0x00000000 +#define DDRSS0_PHY_1234_DATA 0x00000000 +#define DDRSS0_PHY_1235_DATA 0x00000000 +#define DDRSS0_PHY_1236_DATA 0x00000000 +#define DDRSS0_PHY_1237_DATA 0x00000000 +#define DDRSS0_PHY_1238_DATA 0x00000000 +#define DDRSS0_PHY_1239_DATA 0x00000000 +#define DDRSS0_PHY_1240_DATA 0x00000000 +#define DDRSS0_PHY_1241_DATA 0x00000000 +#define DDRSS0_PHY_1242_DATA 0x00000000 +#define DDRSS0_PHY_1243_DATA 0x00000000 +#define DDRSS0_PHY_1244_DATA 0x00000000 +#define DDRSS0_PHY_1245_DATA 0x00000000 +#define DDRSS0_PHY_1246_DATA 0x00000000 +#define DDRSS0_PHY_1247_DATA 0x00000000 +#define DDRSS0_PHY_1248_DATA 0x00000000 +#define DDRSS0_PHY_1249_DATA 0x00000000 +#define DDRSS0_PHY_1250_DATA 0x00000000 +#define DDRSS0_PHY_1251_DATA 0x00000000 +#define DDRSS0_PHY_1252_DATA 0x00000000 +#define DDRSS0_PHY_1253_DATA 0x00000000 +#define DDRSS0_PHY_1254_DATA 0x00000000 +#define DDRSS0_PHY_1255_DATA 0x00000000 +#define DDRSS0_PHY_1256_DATA 0x00000000 +#define DDRSS0_PHY_1257_DATA 0x00000000 +#define DDRSS0_PHY_1258_DATA 0x00000000 +#define DDRSS0_PHY_1259_DATA 0x00000000 +#define DDRSS0_PHY_1260_DATA 0x00000000 +#define DDRSS0_PHY_1261_DATA 0x00000000 +#define DDRSS0_PHY_1262_DATA 0x00000000 +#define DDRSS0_PHY_1263_DATA 0x00000000 +#define DDRSS0_PHY_1264_DATA 0x00000000 +#define DDRSS0_PHY_1265_DATA 0x00000000 +#define DDRSS0_PHY_1266_DATA 0x00000000 +#define DDRSS0_PHY_1267_DATA 0x00000000 +#define DDRSS0_PHY_1268_DATA 0x00000000 +#define DDRSS0_PHY_1269_DATA 0x00000000 +#define DDRSS0_PHY_1270_DATA 0x00000000 +#define DDRSS0_PHY_1271_DATA 0x00000000 +#define DDRSS0_PHY_1272_DATA 0x00000000 +#define DDRSS0_PHY_1273_DATA 0x00000000 +#define DDRSS0_PHY_1274_DATA 0x00000000 +#define DDRSS0_PHY_1275_DATA 0x00000000 +#define DDRSS0_PHY_1276_DATA 0x00000000 +#define DDRSS0_PHY_1277_DATA 0x00000000 +#define DDRSS0_PHY_1278_DATA 0x00000000 +#define DDRSS0_PHY_1279_DATA 0x00000000 +#define DDRSS0_PHY_1280_DATA 0x00000000 +#define DDRSS0_PHY_1281_DATA 0x00010100 +#define DDRSS0_PHY_1282_DATA 0x00000000 +#define DDRSS0_PHY_1283_DATA 0x00000000 +#define DDRSS0_PHY_1284_DATA 0x00050000 +#define DDRSS0_PHY_1285_DATA 0x04000000 +#define DDRSS0_PHY_1286_DATA 0x00000055 +#define DDRSS0_PHY_1287_DATA 0x00000000 +#define DDRSS0_PHY_1288_DATA 0x00000000 +#define DDRSS0_PHY_1289_DATA 0x00000000 +#define DDRSS0_PHY_1290_DATA 0x00000000 +#define DDRSS0_PHY_1291_DATA 0x00002001 +#define DDRSS0_PHY_1292_DATA 0x0000400F +#define DDRSS0_PHY_1293_DATA 0x50020028 +#define DDRSS0_PHY_1294_DATA 0x01010000 +#define DDRSS0_PHY_1295_DATA 0x80080001 +#define DDRSS0_PHY_1296_DATA 0x10200000 +#define DDRSS0_PHY_1297_DATA 0x00000008 +#define DDRSS0_PHY_1298_DATA 0x00000000 +#define DDRSS0_PHY_1299_DATA 0x01090E00 +#define DDRSS0_PHY_1300_DATA 0x00040101 +#define DDRSS0_PHY_1301_DATA 0x0000010F +#define DDRSS0_PHY_1302_DATA 0x00000000 +#define DDRSS0_PHY_1303_DATA 0x00000064 +#define DDRSS0_PHY_1304_DATA 0x00000000 +#define DDRSS0_PHY_1305_DATA 0x01010000 +#define DDRSS0_PHY_1306_DATA 0x01080402 +#define DDRSS0_PHY_1307_DATA 0x01200F02 +#define DDRSS0_PHY_1308_DATA 0x00194280 +#define DDRSS0_PHY_1309_DATA 0x00000004 +#define DDRSS0_PHY_1310_DATA 0x00042000 +#define DDRSS0_PHY_1311_DATA 0x00000000 +#define DDRSS0_PHY_1312_DATA 0x00000000 +#define DDRSS0_PHY_1313_DATA 0x00000000 +#define DDRSS0_PHY_1314_DATA 0x00000000 +#define DDRSS0_PHY_1315_DATA 0x00000000 +#define DDRSS0_PHY_1316_DATA 0x00000000 +#define DDRSS0_PHY_1317_DATA 0x01000000 +#define DDRSS0_PHY_1318_DATA 0x00000705 +#define DDRSS0_PHY_1319_DATA 0x00000054 +#define DDRSS0_PHY_1320_DATA 0x00030820 +#define DDRSS0_PHY_1321_DATA 0x00010820 +#define DDRSS0_PHY_1322_DATA 0x00010820 +#define DDRSS0_PHY_1323_DATA 0x00010820 +#define DDRSS0_PHY_1324_DATA 0x00010820 +#define DDRSS0_PHY_1325_DATA 0x00010820 +#define DDRSS0_PHY_1326_DATA 0x00010820 +#define DDRSS0_PHY_1327_DATA 0x00010820 +#define DDRSS0_PHY_1328_DATA 0x00010820 +#define DDRSS0_PHY_1329_DATA 0x00000000 +#define DDRSS0_PHY_1330_DATA 0x00000074 +#define DDRSS0_PHY_1331_DATA 0x00000400 +#define DDRSS0_PHY_1332_DATA 0x00000108 +#define DDRSS0_PHY_1333_DATA 0x00000000 +#define DDRSS0_PHY_1334_DATA 0x00000000 +#define DDRSS0_PHY_1335_DATA 0x00000000 +#define DDRSS0_PHY_1336_DATA 0x00000000 +#define DDRSS0_PHY_1337_DATA 0x00000000 +#define DDRSS0_PHY_1338_DATA 0x03000000 +#define DDRSS0_PHY_1339_DATA 0x00000000 +#define DDRSS0_PHY_1340_DATA 0x00000000 +#define DDRSS0_PHY_1341_DATA 0x00000000 +#define DDRSS0_PHY_1342_DATA 0x04102006 +#define DDRSS0_PHY_1343_DATA 0x00041020 +#define DDRSS0_PHY_1344_DATA 0x01C98C98 +#define DDRSS0_PHY_1345_DATA 0x3F400000 +#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS0_PHY_1347_DATA 0x0000001F +#define DDRSS0_PHY_1348_DATA 0x00000000 +#define DDRSS0_PHY_1349_DATA 0x00000000 +#define DDRSS0_PHY_1350_DATA 0x00000000 +#define DDRSS0_PHY_1351_DATA 0x00010000 +#define DDRSS0_PHY_1352_DATA 0x00000000 +#define DDRSS0_PHY_1353_DATA 0x00000000 +#define DDRSS0_PHY_1354_DATA 0x00000000 +#define DDRSS0_PHY_1355_DATA 0x00000000 +#define DDRSS0_PHY_1356_DATA 0x76543210 +#define DDRSS0_PHY_1357_DATA 0x00010198 +#define DDRSS0_PHY_1358_DATA 0x00000000 +#define DDRSS0_PHY_1359_DATA 0x00000000 +#define DDRSS0_PHY_1360_DATA 0x00000000 +#define DDRSS0_PHY_1361_DATA 0x00040700 +#define DDRSS0_PHY_1362_DATA 0x00000000 +#define DDRSS0_PHY_1363_DATA 0x00000000 +#define DDRSS0_PHY_1364_DATA 0x00000000 +#define DDRSS0_PHY_1365_DATA 0x00000000 +#define DDRSS0_PHY_1366_DATA 0x00000000 +#define DDRSS0_PHY_1367_DATA 0x00000002 +#define DDRSS0_PHY_1368_DATA 0x00000000 +#define DDRSS0_PHY_1369_DATA 0x00000000 +#define DDRSS0_PHY_1370_DATA 0x00000000 +#define DDRSS0_PHY_1371_DATA 0x00000000 +#define DDRSS0_PHY_1372_DATA 0x00000000 +#define DDRSS0_PHY_1373_DATA 0x00000000 +#define DDRSS0_PHY_1374_DATA 0x00080000 +#define DDRSS0_PHY_1375_DATA 0x000007FF +#define DDRSS0_PHY_1376_DATA 0x00000000 +#define DDRSS0_PHY_1377_DATA 0x00000000 +#define DDRSS0_PHY_1378_DATA 0x00000000 +#define DDRSS0_PHY_1379_DATA 0x00000000 +#define DDRSS0_PHY_1380_DATA 0x00000000 +#define DDRSS0_PHY_1381_DATA 0x00000000 +#define DDRSS0_PHY_1382_DATA 0x000FFFFF +#define DDRSS0_PHY_1383_DATA 0x000FFFFF +#define DDRSS0_PHY_1384_DATA 0x0000FFFF +#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS0_PHY_1386_DATA 0x030FFFFF +#define DDRSS0_PHY_1387_DATA 0x01FFFFFF +#define DDRSS0_PHY_1388_DATA 0x0000FFFF +#define DDRSS0_PHY_1389_DATA 0x00000000 +#define DDRSS0_PHY_1390_DATA 0x00000000 +#define DDRSS0_PHY_1391_DATA 0x00000000 +#define DDRSS0_PHY_1392_DATA 0x00000000 +#define DDRSS0_PHY_1393_DATA 0x0001F7C0 +#define DDRSS0_PHY_1394_DATA 0x00000003 +#define DDRSS0_PHY_1395_DATA 0x00000000 +#define DDRSS0_PHY_1396_DATA 0x00001142 +#define DDRSS0_PHY_1397_DATA 0x040207AB +#define DDRSS0_PHY_1398_DATA 0x01000080 +#define DDRSS0_PHY_1399_DATA 0x03900390 +#define DDRSS0_PHY_1400_DATA 0x03900390 +#define DDRSS0_PHY_1401_DATA 0x00000390 +#define DDRSS0_PHY_1402_DATA 0x00000390 +#define DDRSS0_PHY_1403_DATA 0x00000390 +#define DDRSS0_PHY_1404_DATA 0x00000390 +#define DDRSS0_PHY_1405_DATA 0x00000005 +#define DDRSS0_PHY_1406_DATA 0x01813FCC +#define DDRSS0_PHY_1407_DATA 0x000000CC +#define DDRSS0_PHY_1408_DATA 0x0C000DFF +#define DDRSS0_PHY_1409_DATA 0x30000DFF +#define DDRSS0_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1411_DATA 0x000100F0 +#define DDRSS0_PHY_1412_DATA 0x780DFFCC +#define DDRSS0_PHY_1413_DATA 0x00007E31 +#define DDRSS0_PHY_1414_DATA 0x000CBF11 +#define DDRSS0_PHY_1415_DATA 0x01990010 +#define DDRSS0_PHY_1416_DATA 0x000CBF11 +#define DDRSS0_PHY_1417_DATA 0x01990010 +#define DDRSS0_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1419_DATA 0x00EF00F0 +#define DDRSS0_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1421_DATA 0x01FF00F0 +#define DDRSS0_PHY_1422_DATA 0x20040006 + +#define DDRSS1_CTL_00_DATA 0x00000B00 +#define DDRSS1_CTL_01_DATA 0x00000000 +#define DDRSS1_CTL_02_DATA 0x00000000 +#define DDRSS1_CTL_03_DATA 0x00000000 +#define DDRSS1_CTL_04_DATA 0x00000000 +#define DDRSS1_CTL_05_DATA 0x00000000 +#define DDRSS1_CTL_06_DATA 0x00000000 +#define DDRSS1_CTL_07_DATA 0x00002AF8 +#define DDRSS1_CTL_08_DATA 0x0001ADAF +#define DDRSS1_CTL_09_DATA 0x00000005 +#define DDRSS1_CTL_10_DATA 0x0000006E +#define DDRSS1_CTL_11_DATA 0x000681C8 +#define DDRSS1_CTL_12_DATA 0x004111C9 +#define DDRSS1_CTL_13_DATA 0x00000005 +#define DDRSS1_CTL_14_DATA 0x000010A9 +#define DDRSS1_CTL_15_DATA 0x000681C8 +#define DDRSS1_CTL_16_DATA 0x004111C9 +#define DDRSS1_CTL_17_DATA 0x00000005 +#define DDRSS1_CTL_18_DATA 0x000010A9 +#define DDRSS1_CTL_19_DATA 0x01010000 +#define DDRSS1_CTL_20_DATA 0x01011001 +#define DDRSS1_CTL_21_DATA 0x02010000 +#define DDRSS1_CTL_22_DATA 0x00020100 +#define DDRSS1_CTL_23_DATA 0x0000000B +#define DDRSS1_CTL_24_DATA 0x0000001C +#define DDRSS1_CTL_25_DATA 0x00000000 +#define DDRSS1_CTL_26_DATA 0x00000000 +#define DDRSS1_CTL_27_DATA 0x03020200 +#define DDRSS1_CTL_28_DATA 0x00005656 +#define DDRSS1_CTL_29_DATA 0x00100000 +#define DDRSS1_CTL_30_DATA 0x00000000 +#define DDRSS1_CTL_31_DATA 0x00000000 +#define DDRSS1_CTL_32_DATA 0x00000000 +#define DDRSS1_CTL_33_DATA 0x00000000 +#define DDRSS1_CTL_34_DATA 0x040C0000 +#define DDRSS1_CTL_35_DATA 0x12501250 +#define DDRSS1_CTL_36_DATA 0x00050804 +#define DDRSS1_CTL_37_DATA 0x09040008 +#define DDRSS1_CTL_38_DATA 0x15000204 +#define DDRSS1_CTL_39_DATA 0x1760008B +#define DDRSS1_CTL_40_DATA 0x1500422B +#define DDRSS1_CTL_41_DATA 0x1760008B +#define DDRSS1_CTL_42_DATA 0x2000422B +#define DDRSS1_CTL_43_DATA 0x000A0A09 +#define DDRSS1_CTL_44_DATA 0x040003C5 +#define DDRSS1_CTL_45_DATA 0x1E161104 +#define DDRSS1_CTL_46_DATA 0x1000922C +#define DDRSS1_CTL_47_DATA 0x1E161110 +#define DDRSS1_CTL_48_DATA 0x1000922C +#define DDRSS1_CTL_49_DATA 0x02030410 +#define DDRSS1_CTL_50_DATA 0x2C060500 +#define DDRSS1_CTL_51_DATA 0x08292C29 +#define DDRSS1_CTL_52_DATA 0x14000E0A +#define DDRSS1_CTL_53_DATA 0x04010A0A +#define DDRSS1_CTL_54_DATA 0x01010004 +#define DDRSS1_CTL_55_DATA 0x0454540A +#define DDRSS1_CTL_56_DATA 0x04313104 +#define DDRSS1_CTL_57_DATA 0x00003131 +#define DDRSS1_CTL_58_DATA 0x00010100 +#define DDRSS1_CTL_59_DATA 0x03010000 +#define DDRSS1_CTL_60_DATA 0x00001508 +#define DDRSS1_CTL_61_DATA 0x00000068 +#define DDRSS1_CTL_62_DATA 0x0000032B +#define DDRSS1_CTL_63_DATA 0x00001035 +#define DDRSS1_CTL_64_DATA 0x0000032B +#define DDRSS1_CTL_65_DATA 0x00001035 +#define DDRSS1_CTL_66_DATA 0x00000005 +#define DDRSS1_CTL_67_DATA 0x00050000 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 +#define DDRSS1_CTL_71_DATA 0x00120103 +#define DDRSS1_CTL_72_DATA 0x00100005 +#define DDRSS1_CTL_73_DATA 0x2F080010 +#define DDRSS1_CTL_74_DATA 0x0505012F +#define DDRSS1_CTL_75_DATA 0x0401030A +#define DDRSS1_CTL_76_DATA 0x041E100B +#define DDRSS1_CTL_77_DATA 0x100B0401 +#define DDRSS1_CTL_78_DATA 0x0001041E +#define DDRSS1_CTL_79_DATA 0x00160016 +#define DDRSS1_CTL_80_DATA 0x033B033B +#define DDRSS1_CTL_81_DATA 0x033B033B +#define DDRSS1_CTL_82_DATA 0x03050505 +#define DDRSS1_CTL_83_DATA 0x03010303 +#define DDRSS1_CTL_84_DATA 0x200B100B +#define DDRSS1_CTL_85_DATA 0x04041004 +#define DDRSS1_CTL_86_DATA 0x200B100B +#define DDRSS1_CTL_87_DATA 0x04041004 +#define DDRSS1_CTL_88_DATA 0x03010000 +#define DDRSS1_CTL_89_DATA 0x00010000 +#define DDRSS1_CTL_90_DATA 0x00000000 +#define DDRSS1_CTL_91_DATA 0x00000000 +#define DDRSS1_CTL_92_DATA 0x01000000 +#define DDRSS1_CTL_93_DATA 0x80104002 +#define DDRSS1_CTL_94_DATA 0x00000000 +#define DDRSS1_CTL_95_DATA 0x00040005 +#define DDRSS1_CTL_96_DATA 0x00000000 +#define DDRSS1_CTL_97_DATA 0x00050000 +#define DDRSS1_CTL_98_DATA 0x00000004 +#define DDRSS1_CTL_99_DATA 0x00000000 +#define DDRSS1_CTL_100_DATA 0x00040005 +#define DDRSS1_CTL_101_DATA 0x00000000 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 +#define DDRSS1_CTL_107_DATA 0x00000000 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 +#define DDRSS1_CTL_114_DATA 0x00000000 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 +#define DDRSS1_CTL_121_DATA 0x00000000 +#define DDRSS1_CTL_122_DATA 0x00007173 +#define DDRSS1_CTL_123_DATA 0x00000000 +#define DDRSS1_CTL_124_DATA 0x00000000 +#define DDRSS1_CTL_125_DATA 0x00000000 +#define DDRSS1_CTL_126_DATA 0x00000000 +#define DDRSS1_CTL_127_DATA 0x00000000 +#define DDRSS1_CTL_128_DATA 0x00000000 +#define DDRSS1_CTL_129_DATA 0x00000000 +#define DDRSS1_CTL_130_DATA 0x00000000 +#define DDRSS1_CTL_131_DATA 0x0B030500 +#define DDRSS1_CTL_132_DATA 0x00040B04 +#define DDRSS1_CTL_133_DATA 0x0A090000 +#define DDRSS1_CTL_134_DATA 0x0A090701 +#define DDRSS1_CTL_135_DATA 0x0900000E +#define DDRSS1_CTL_136_DATA 0x0907010A +#define DDRSS1_CTL_137_DATA 0x00000E0A +#define DDRSS1_CTL_138_DATA 0x07010A09 +#define DDRSS1_CTL_139_DATA 0x000E0A09 +#define DDRSS1_CTL_140_DATA 0x07000401 +#define DDRSS1_CTL_141_DATA 0x00000000 +#define DDRSS1_CTL_142_DATA 0x00000000 +#define DDRSS1_CTL_143_DATA 0x00000000 +#define DDRSS1_CTL_144_DATA 0x00000000 +#define DDRSS1_CTL_145_DATA 0x00000000 +#define DDRSS1_CTL_146_DATA 0x00000000 +#define DDRSS1_CTL_147_DATA 0x00000000 +#define DDRSS1_CTL_148_DATA 0x08080000 +#define DDRSS1_CTL_149_DATA 0x01000000 +#define DDRSS1_CTL_150_DATA 0x800000C0 +#define DDRSS1_CTL_151_DATA 0x800000C0 +#define DDRSS1_CTL_152_DATA 0x800000C0 +#define DDRSS1_CTL_153_DATA 0x00000000 +#define DDRSS1_CTL_154_DATA 0x00001500 +#define DDRSS1_CTL_155_DATA 0x00000000 +#define DDRSS1_CTL_156_DATA 0x00000001 +#define DDRSS1_CTL_157_DATA 0x00000002 +#define DDRSS1_CTL_158_DATA 0x0000100E +#define DDRSS1_CTL_159_DATA 0x00000000 +#define DDRSS1_CTL_160_DATA 0x00000000 +#define DDRSS1_CTL_161_DATA 0x00000000 +#define DDRSS1_CTL_162_DATA 0x00000000 +#define DDRSS1_CTL_163_DATA 0x00000000 +#define DDRSS1_CTL_164_DATA 0x000B0000 +#define DDRSS1_CTL_165_DATA 0x000E0006 +#define DDRSS1_CTL_166_DATA 0x000E0404 +#define DDRSS1_CTL_167_DATA 0x00D601AB +#define DDRSS1_CTL_168_DATA 0x10100216 +#define DDRSS1_CTL_169_DATA 0x01AB0216 +#define DDRSS1_CTL_170_DATA 0x021600D6 +#define DDRSS1_CTL_171_DATA 0x02161010 +#define DDRSS1_CTL_172_DATA 0x00000000 +#define DDRSS1_CTL_173_DATA 0x00000000 +#define DDRSS1_CTL_174_DATA 0x00000000 +#define DDRSS1_CTL_175_DATA 0x3FF40084 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x36000000 +#define DDRSS1_CTL_179_DATA 0x27270036 +#define DDRSS1_CTL_180_DATA 0x0F0F0000 +#define DDRSS1_CTL_181_DATA 0x16000000 +#define DDRSS1_CTL_182_DATA 0x00841616 +#define DDRSS1_CTL_183_DATA 0x3FF43FF4 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 +#define DDRSS1_CTL_185_DATA 0x00000000 +#define DDRSS1_CTL_186_DATA 0x00363600 +#define DDRSS1_CTL_187_DATA 0x00002727 +#define DDRSS1_CTL_188_DATA 0x00000F0F +#define DDRSS1_CTL_189_DATA 0x16161600 +#define DDRSS1_CTL_190_DATA 0x00000020 +#define DDRSS1_CTL_191_DATA 0x01000000 +#define DDRSS1_CTL_192_DATA 0x00000001 +#define DDRSS1_CTL_193_DATA 0x00000000 +#define DDRSS1_CTL_194_DATA 0x01000000 +#define DDRSS1_CTL_195_DATA 0x00000001 +#define DDRSS1_CTL_196_DATA 0x00000000 +#define DDRSS1_CTL_197_DATA 0x00000000 +#define DDRSS1_CTL_198_DATA 0x00000000 +#define DDRSS1_CTL_199_DATA 0x00000000 +#define DDRSS1_CTL_200_DATA 0x00000000 +#define DDRSS1_CTL_201_DATA 0x00000000 +#define DDRSS1_CTL_202_DATA 0x00000000 +#define DDRSS1_CTL_203_DATA 0x00000000 +#define DDRSS1_CTL_204_DATA 0x00000000 +#define DDRSS1_CTL_205_DATA 0x00000000 +#define DDRSS1_CTL_206_DATA 0x02000000 +#define DDRSS1_CTL_207_DATA 0x01080101 +#define DDRSS1_CTL_208_DATA 0x00000000 +#define DDRSS1_CTL_209_DATA 0x00000000 +#define DDRSS1_CTL_210_DATA 0x00000000 +#define DDRSS1_CTL_211_DATA 0x00000000 +#define DDRSS1_CTL_212_DATA 0x00000000 +#define DDRSS1_CTL_213_DATA 0x00000000 +#define DDRSS1_CTL_214_DATA 0x00000000 +#define DDRSS1_CTL_215_DATA 0x00000000 +#define DDRSS1_CTL_216_DATA 0x00000000 +#define DDRSS1_CTL_217_DATA 0x00000000 +#define DDRSS1_CTL_218_DATA 0x00000000 +#define DDRSS1_CTL_219_DATA 0x00000000 +#define DDRSS1_CTL_220_DATA 0x00000000 +#define DDRSS1_CTL_221_DATA 0x00000000 +#define DDRSS1_CTL_222_DATA 0x00001000 +#define DDRSS1_CTL_223_DATA 0x006403E8 +#define DDRSS1_CTL_224_DATA 0x00000000 +#define DDRSS1_CTL_225_DATA 0x00000000 +#define DDRSS1_CTL_226_DATA 0x00000000 +#define DDRSS1_CTL_227_DATA 0x15110000 +#define DDRSS1_CTL_228_DATA 0x00040C18 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 +#define DDRSS1_CTL_231_DATA 0x00000000 +#define DDRSS1_CTL_232_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 +#define DDRSS1_CTL_235_DATA 0x00000000 +#define DDRSS1_CTL_236_DATA 0x00000000 +#define DDRSS1_CTL_237_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 +#define DDRSS1_CTL_240_DATA 0x00000000 +#define DDRSS1_CTL_241_DATA 0x00000000 +#define DDRSS1_CTL_242_DATA 0x00030000 +#define DDRSS1_CTL_243_DATA 0x00000000 +#define DDRSS1_CTL_244_DATA 0x00000000 +#define DDRSS1_CTL_245_DATA 0x00000000 +#define DDRSS1_CTL_246_DATA 0x00000000 +#define DDRSS1_CTL_247_DATA 0x00000000 +#define DDRSS1_CTL_248_DATA 0x00000000 +#define DDRSS1_CTL_249_DATA 0x00000000 +#define DDRSS1_CTL_250_DATA 0x00000000 +#define DDRSS1_CTL_251_DATA 0x00000000 +#define DDRSS1_CTL_252_DATA 0x00000000 +#define DDRSS1_CTL_253_DATA 0x00000000 +#define DDRSS1_CTL_254_DATA 0x00000000 +#define DDRSS1_CTL_255_DATA 0x00000000 +#define DDRSS1_CTL_256_DATA 0x00000000 +#define DDRSS1_CTL_257_DATA 0x01000200 +#define DDRSS1_CTL_258_DATA 0x00370040 +#define DDRSS1_CTL_259_DATA 0x00020008 +#define DDRSS1_CTL_260_DATA 0x00400100 +#define DDRSS1_CTL_261_DATA 0x00400855 +#define DDRSS1_CTL_262_DATA 0x01000200 +#define DDRSS1_CTL_263_DATA 0x08550040 +#define DDRSS1_CTL_264_DATA 0x00000040 +#define DDRSS1_CTL_265_DATA 0x006B0003 +#define DDRSS1_CTL_266_DATA 0x0100006B +#define DDRSS1_CTL_267_DATA 0x03030303 +#define DDRSS1_CTL_268_DATA 0x00000000 +#define DDRSS1_CTL_269_DATA 0x00000202 +#define DDRSS1_CTL_270_DATA 0x00001FFF +#define DDRSS1_CTL_271_DATA 0x3FFF2000 +#define DDRSS1_CTL_272_DATA 0x03FF0000 +#define DDRSS1_CTL_273_DATA 0x000103FF +#define DDRSS1_CTL_274_DATA 0x0FFF0B00 +#define DDRSS1_CTL_275_DATA 0x01010001 +#define DDRSS1_CTL_276_DATA 0x01010101 +#define DDRSS1_CTL_277_DATA 0x01180101 +#define DDRSS1_CTL_278_DATA 0x00030000 +#define DDRSS1_CTL_279_DATA 0x00000000 +#define DDRSS1_CTL_280_DATA 0x00000000 +#define DDRSS1_CTL_281_DATA 0x00000000 +#define DDRSS1_CTL_282_DATA 0x00000000 +#define DDRSS1_CTL_283_DATA 0x00000000 +#define DDRSS1_CTL_284_DATA 0x00000000 +#define DDRSS1_CTL_285_DATA 0x00000000 +#define DDRSS1_CTL_286_DATA 0x00040101 +#define DDRSS1_CTL_287_DATA 0x04010100 +#define DDRSS1_CTL_288_DATA 0x00000000 +#define DDRSS1_CTL_289_DATA 0x00000000 +#define DDRSS1_CTL_290_DATA 0x03030300 +#define DDRSS1_CTL_291_DATA 0x00010101 +#define DDRSS1_CTL_292_DATA 0x00000000 +#define DDRSS1_CTL_293_DATA 0x00000000 +#define DDRSS1_CTL_294_DATA 0x00000000 +#define DDRSS1_CTL_295_DATA 0x00000000 +#define DDRSS1_CTL_296_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF +#define DDRSS1_CTL_299_DATA 0x00000000 +#define DDRSS1_CTL_300_DATA 0x00000000 +#define DDRSS1_CTL_301_DATA 0x00000000 +#define DDRSS1_CTL_302_DATA 0x00000000 +#define DDRSS1_CTL_303_DATA 0x00000000 +#define DDRSS1_CTL_304_DATA 0x00000000 +#define DDRSS1_CTL_305_DATA 0x00000000 +#define DDRSS1_CTL_306_DATA 0x00000000 +#define DDRSS1_CTL_307_DATA 0x00000000 +#define DDRSS1_CTL_308_DATA 0x00000000 +#define DDRSS1_CTL_309_DATA 0x00000000 +#define DDRSS1_CTL_310_DATA 0x00000000 +#define DDRSS1_CTL_311_DATA 0x00000000 +#define DDRSS1_CTL_312_DATA 0x00000000 +#define DDRSS1_CTL_313_DATA 0x01000000 +#define DDRSS1_CTL_314_DATA 0x00020201 +#define DDRSS1_CTL_315_DATA 0x01000101 +#define DDRSS1_CTL_316_DATA 0x01010001 +#define DDRSS1_CTL_317_DATA 0x00010101 +#define DDRSS1_CTL_318_DATA 0x050A0A03 +#define DDRSS1_CTL_319_DATA 0x10082323 +#define DDRSS1_CTL_320_DATA 0x00090310 +#define DDRSS1_CTL_321_DATA 0x0B0C030F +#define DDRSS1_CTL_322_DATA 0x0B0C0306 +#define DDRSS1_CTL_323_DATA 0x0C090006 +#define DDRSS1_CTL_324_DATA 0x0100000C +#define DDRSS1_CTL_325_DATA 0x08040801 +#define DDRSS1_CTL_326_DATA 0x00000004 +#define DDRSS1_CTL_327_DATA 0x00000000 +#define DDRSS1_CTL_328_DATA 0x00010000 +#define DDRSS1_CTL_329_DATA 0x00280D00 +#define DDRSS1_CTL_330_DATA 0x00000001 +#define DDRSS1_CTL_331_DATA 0x00030001 +#define DDRSS1_CTL_332_DATA 0x00000000 +#define DDRSS1_CTL_333_DATA 0x00000000 +#define DDRSS1_CTL_334_DATA 0x00000000 +#define DDRSS1_CTL_335_DATA 0x00000000 +#define DDRSS1_CTL_336_DATA 0x00000000 +#define DDRSS1_CTL_337_DATA 0x00000000 +#define DDRSS1_CTL_338_DATA 0x00000000 +#define DDRSS1_CTL_339_DATA 0x00000000 +#define DDRSS1_CTL_340_DATA 0x01000000 +#define DDRSS1_CTL_341_DATA 0x00000001 +#define DDRSS1_CTL_342_DATA 0x00010100 +#define DDRSS1_CTL_343_DATA 0x03030000 +#define DDRSS1_CTL_344_DATA 0x00000000 +#define DDRSS1_CTL_345_DATA 0x00000000 +#define DDRSS1_CTL_346_DATA 0x00000000 +#define DDRSS1_CTL_347_DATA 0x00000000 +#define DDRSS1_CTL_348_DATA 0x00000000 +#define DDRSS1_CTL_349_DATA 0x00000000 +#define DDRSS1_CTL_350_DATA 0x00000000 +#define DDRSS1_CTL_351_DATA 0x00000000 +#define DDRSS1_CTL_352_DATA 0x00000000 +#define DDRSS1_CTL_353_DATA 0x00000000 +#define DDRSS1_CTL_354_DATA 0x00000000 +#define DDRSS1_CTL_355_DATA 0x00000000 +#define DDRSS1_CTL_356_DATA 0x00000000 +#define DDRSS1_CTL_357_DATA 0x00000000 +#define DDRSS1_CTL_358_DATA 0x00000000 +#define DDRSS1_CTL_359_DATA 0x00000000 +#define DDRSS1_CTL_360_DATA 0x000556AA +#define DDRSS1_CTL_361_DATA 0x000AAAAA +#define DDRSS1_CTL_362_DATA 0x000AA955 +#define DDRSS1_CTL_363_DATA 0x00055555 +#define DDRSS1_CTL_364_DATA 0x000B3133 +#define DDRSS1_CTL_365_DATA 0x0004CD33 +#define DDRSS1_CTL_366_DATA 0x0004CECC +#define DDRSS1_CTL_367_DATA 0x000B32CC +#define DDRSS1_CTL_368_DATA 0x00010300 +#define DDRSS1_CTL_369_DATA 0x03000100 +#define DDRSS1_CTL_370_DATA 0x00000000 +#define DDRSS1_CTL_371_DATA 0x00000000 +#define DDRSS1_CTL_372_DATA 0x00000000 +#define DDRSS1_CTL_373_DATA 0x00000000 +#define DDRSS1_CTL_374_DATA 0x00000000 +#define DDRSS1_CTL_375_DATA 0x00000000 +#define DDRSS1_CTL_376_DATA 0x00000000 +#define DDRSS1_CTL_377_DATA 0x00010000 +#define DDRSS1_CTL_378_DATA 0x00000404 +#define DDRSS1_CTL_379_DATA 0x00000000 +#define DDRSS1_CTL_380_DATA 0x00000000 +#define DDRSS1_CTL_381_DATA 0x00000000 +#define DDRSS1_CTL_382_DATA 0x00000000 +#define DDRSS1_CTL_383_DATA 0x00000000 +#define DDRSS1_CTL_384_DATA 0x00000000 +#define DDRSS1_CTL_385_DATA 0x00000000 +#define DDRSS1_CTL_386_DATA 0x00000000 +#define DDRSS1_CTL_387_DATA 0x3A3A1B00 +#define DDRSS1_CTL_388_DATA 0x000A0000 +#define DDRSS1_CTL_389_DATA 0x000000C6 +#define DDRSS1_CTL_390_DATA 0x00000200 +#define DDRSS1_CTL_391_DATA 0x00000200 +#define DDRSS1_CTL_392_DATA 0x00000200 +#define DDRSS1_CTL_393_DATA 0x00000200 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC +#define DDRSS1_CTL_396_DATA 0x00000204 +#define DDRSS1_CTL_397_DATA 0x0000206A +#define DDRSS1_CTL_398_DATA 0x00000200 +#define DDRSS1_CTL_399_DATA 0x00000200 +#define DDRSS1_CTL_400_DATA 0x00000200 +#define DDRSS1_CTL_401_DATA 0x00000200 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A +#define DDRSS1_CTL_406_DATA 0x00000200 +#define DDRSS1_CTL_407_DATA 0x00000200 +#define DDRSS1_CTL_408_DATA 0x00000200 +#define DDRSS1_CTL_409_DATA 0x00000200 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 +#define DDRSS1_CTL_413_DATA 0x03030202 +#define DDRSS1_CTL_414_DATA 0x00000022 +#define DDRSS1_CTL_415_DATA 0x00000000 +#define DDRSS1_CTL_416_DATA 0x00000000 +#define DDRSS1_CTL_417_DATA 0x00001403 +#define DDRSS1_CTL_418_DATA 0x000007D0 +#define DDRSS1_CTL_419_DATA 0x00000000 +#define DDRSS1_CTL_420_DATA 0x00000000 +#define DDRSS1_CTL_421_DATA 0x00030000 +#define DDRSS1_CTL_422_DATA 0x0007001F +#define DDRSS1_CTL_423_DATA 0x001B0033 +#define DDRSS1_CTL_424_DATA 0x001B0033 +#define DDRSS1_CTL_425_DATA 0x00000000 +#define DDRSS1_CTL_426_DATA 0x00000000 +#define DDRSS1_CTL_427_DATA 0x02000000 +#define DDRSS1_CTL_428_DATA 0x01000404 +#define DDRSS1_CTL_429_DATA 0x0B220B22 +#define DDRSS1_CTL_430_DATA 0x00000105 +#define DDRSS1_CTL_431_DATA 0x00010101 +#define DDRSS1_CTL_432_DATA 0x00010101 +#define DDRSS1_CTL_433_DATA 0x00010001 +#define DDRSS1_CTL_434_DATA 0x00000101 +#define DDRSS1_CTL_435_DATA 0x02000201 +#define DDRSS1_CTL_436_DATA 0x02010000 +#define DDRSS1_CTL_437_DATA 0x00000200 +#define DDRSS1_CTL_438_DATA 0x28060000 +#define DDRSS1_CTL_439_DATA 0x00000128 +#define DDRSS1_CTL_440_DATA 0xFFFFFFFF +#define DDRSS1_CTL_441_DATA 0xFFFFFFFF +#define DDRSS1_CTL_442_DATA 0x00000000 +#define DDRSS1_CTL_443_DATA 0x00000000 +#define DDRSS1_CTL_444_DATA 0x00000000 +#define DDRSS1_CTL_445_DATA 0x00000000 +#define DDRSS1_CTL_446_DATA 0x00000000 +#define DDRSS1_CTL_447_DATA 0x00000000 +#define DDRSS1_CTL_448_DATA 0x00000000 +#define DDRSS1_CTL_449_DATA 0x00000000 +#define DDRSS1_CTL_450_DATA 0x00000000 +#define DDRSS1_CTL_451_DATA 0x00000000 +#define DDRSS1_CTL_452_DATA 0x00000000 +#define DDRSS1_CTL_453_DATA 0x00000000 +#define DDRSS1_CTL_454_DATA 0x00000000 +#define DDRSS1_CTL_455_DATA 0x00000000 +#define DDRSS1_CTL_456_DATA 0x00000000 +#define DDRSS1_CTL_457_DATA 0x00000000 +#define DDRSS1_CTL_458_DATA 0x00000000 + +#define DDRSS1_PI_00_DATA 0x00000B00 +#define DDRSS1_PI_01_DATA 0x00000000 +#define DDRSS1_PI_02_DATA 0x00000000 +#define DDRSS1_PI_03_DATA 0x00000000 +#define DDRSS1_PI_04_DATA 0x00000000 +#define DDRSS1_PI_05_DATA 0x00000101 +#define DDRSS1_PI_06_DATA 0x00640000 +#define DDRSS1_PI_07_DATA 0x00000001 +#define DDRSS1_PI_08_DATA 0x00000000 +#define DDRSS1_PI_09_DATA 0x00000000 +#define DDRSS1_PI_10_DATA 0x00000000 +#define DDRSS1_PI_11_DATA 0x00000000 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 +#define DDRSS1_PI_14_DATA 0x0800000F +#define DDRSS1_PI_15_DATA 0x00000103 +#define DDRSS1_PI_16_DATA 0x00000005 +#define DDRSS1_PI_17_DATA 0x00000000 +#define DDRSS1_PI_18_DATA 0x00000000 +#define DDRSS1_PI_19_DATA 0x00000000 +#define DDRSS1_PI_20_DATA 0x00000000 +#define DDRSS1_PI_21_DATA 0x00000000 +#define DDRSS1_PI_22_DATA 0x00000000 +#define DDRSS1_PI_23_DATA 0x00000000 +#define DDRSS1_PI_24_DATA 0x00000000 +#define DDRSS1_PI_25_DATA 0x00000000 +#define DDRSS1_PI_26_DATA 0x00010100 +#define DDRSS1_PI_27_DATA 0x00280A00 +#define DDRSS1_PI_28_DATA 0x00000000 +#define DDRSS1_PI_29_DATA 0x0F000000 +#define DDRSS1_PI_30_DATA 0x00003200 +#define DDRSS1_PI_31_DATA 0x00000000 +#define DDRSS1_PI_32_DATA 0x00000000 +#define DDRSS1_PI_33_DATA 0x01010102 +#define DDRSS1_PI_34_DATA 0x00000000 +#define DDRSS1_PI_35_DATA 0x000000AA +#define DDRSS1_PI_36_DATA 0x00000055 +#define DDRSS1_PI_37_DATA 0x000000B5 +#define DDRSS1_PI_38_DATA 0x0000004A +#define DDRSS1_PI_39_DATA 0x00000056 +#define DDRSS1_PI_40_DATA 0x000000A9 +#define DDRSS1_PI_41_DATA 0x000000A9 +#define DDRSS1_PI_42_DATA 0x000000B5 +#define DDRSS1_PI_43_DATA 0x00000000 +#define DDRSS1_PI_44_DATA 0x00000000 +#define DDRSS1_PI_45_DATA 0x000F0F00 +#define DDRSS1_PI_46_DATA 0x0000001B +#define DDRSS1_PI_47_DATA 0x000007D0 +#define DDRSS1_PI_48_DATA 0x00000300 +#define DDRSS1_PI_49_DATA 0x00000000 +#define DDRSS1_PI_50_DATA 0x00000000 +#define DDRSS1_PI_51_DATA 0x01000000 +#define DDRSS1_PI_52_DATA 0x00010101 +#define DDRSS1_PI_53_DATA 0x00000000 +#define DDRSS1_PI_54_DATA 0x00030000 +#define DDRSS1_PI_55_DATA 0x0F000000 +#define DDRSS1_PI_56_DATA 0x00000017 +#define DDRSS1_PI_57_DATA 0x00000000 +#define DDRSS1_PI_58_DATA 0x00000000 +#define DDRSS1_PI_59_DATA 0x00000000 +#define DDRSS1_PI_60_DATA 0x0A0A140A +#define DDRSS1_PI_61_DATA 0x10020201 +#define DDRSS1_PI_62_DATA 0x00020805 +#define DDRSS1_PI_63_DATA 0x01000404 +#define DDRSS1_PI_64_DATA 0x00000000 +#define DDRSS1_PI_65_DATA 0x00000000 +#define DDRSS1_PI_66_DATA 0x00000100 +#define DDRSS1_PI_67_DATA 0x0002020F +#define DDRSS1_PI_68_DATA 0x00340000 +#define DDRSS1_PI_69_DATA 0x00000000 +#define DDRSS1_PI_70_DATA 0x00000000 +#define DDRSS1_PI_71_DATA 0x0000FFFF +#define DDRSS1_PI_72_DATA 0x01000000 +#define DDRSS1_PI_73_DATA 0x00080000 +#define DDRSS1_PI_74_DATA 0x02000200 +#define DDRSS1_PI_75_DATA 0x01000100 +#define DDRSS1_PI_76_DATA 0x01000000 +#define DDRSS1_PI_77_DATA 0x02000200 +#define DDRSS1_PI_78_DATA 0x00000200 +#define DDRSS1_PI_79_DATA 0x00000000 +#define DDRSS1_PI_80_DATA 0x00000000 +#define DDRSS1_PI_81_DATA 0x00000000 +#define DDRSS1_PI_82_DATA 0x00000000 +#define DDRSS1_PI_83_DATA 0x00000000 +#define DDRSS1_PI_84_DATA 0x00000000 +#define DDRSS1_PI_85_DATA 0x00000000 +#define DDRSS1_PI_86_DATA 0x00000000 +#define DDRSS1_PI_87_DATA 0x00000000 +#define DDRSS1_PI_88_DATA 0x00000000 +#define DDRSS1_PI_89_DATA 0x00000000 +#define DDRSS1_PI_90_DATA 0x00000000 +#define DDRSS1_PI_91_DATA 0x00000400 +#define DDRSS1_PI_92_DATA 0x02010000 +#define DDRSS1_PI_93_DATA 0x00080003 +#define DDRSS1_PI_94_DATA 0x00080000 +#define DDRSS1_PI_95_DATA 0x00000001 +#define DDRSS1_PI_96_DATA 0x00000000 +#define DDRSS1_PI_97_DATA 0x0000AA00 +#define DDRSS1_PI_98_DATA 0x00000000 +#define DDRSS1_PI_99_DATA 0x00000000 +#define DDRSS1_PI_100_DATA 0x00010000 +#define DDRSS1_PI_101_DATA 0x00000000 +#define DDRSS1_PI_102_DATA 0x00000000 +#define DDRSS1_PI_103_DATA 0x00000000 +#define DDRSS1_PI_104_DATA 0x00000000 +#define DDRSS1_PI_105_DATA 0x00000000 +#define DDRSS1_PI_106_DATA 0x00000000 +#define DDRSS1_PI_107_DATA 0x00000000 +#define DDRSS1_PI_108_DATA 0x00000000 +#define DDRSS1_PI_109_DATA 0x00000000 +#define DDRSS1_PI_110_DATA 0x00000000 +#define DDRSS1_PI_111_DATA 0x00000000 +#define DDRSS1_PI_112_DATA 0x00000000 +#define DDRSS1_PI_113_DATA 0x00000000 +#define DDRSS1_PI_114_DATA 0x00000000 +#define DDRSS1_PI_115_DATA 0x00000000 +#define DDRSS1_PI_116_DATA 0x00000000 +#define DDRSS1_PI_117_DATA 0x00000000 +#define DDRSS1_PI_118_DATA 0x00000000 +#define DDRSS1_PI_119_DATA 0x00000000 +#define DDRSS1_PI_120_DATA 0x00000000 +#define DDRSS1_PI_121_DATA 0x00000000 +#define DDRSS1_PI_122_DATA 0x00000000 +#define DDRSS1_PI_123_DATA 0x00000000 +#define DDRSS1_PI_124_DATA 0x00000000 +#define DDRSS1_PI_125_DATA 0x00000008 +#define DDRSS1_PI_126_DATA 0x00000000 +#define DDRSS1_PI_127_DATA 0x00000000 +#define DDRSS1_PI_128_DATA 0x00000000 +#define DDRSS1_PI_129_DATA 0x00000000 +#define DDRSS1_PI_130_DATA 0x00000000 +#define DDRSS1_PI_131_DATA 0x00000000 +#define DDRSS1_PI_132_DATA 0x00000000 +#define DDRSS1_PI_133_DATA 0x00000000 +#define DDRSS1_PI_134_DATA 0x00000002 +#define DDRSS1_PI_135_DATA 0x00000000 +#define DDRSS1_PI_136_DATA 0x00000000 +#define DDRSS1_PI_137_DATA 0x0000000A +#define DDRSS1_PI_138_DATA 0x00000019 +#define DDRSS1_PI_139_DATA 0x00000100 +#define DDRSS1_PI_140_DATA 0x00000000 +#define DDRSS1_PI_141_DATA 0x00000000 +#define DDRSS1_PI_142_DATA 0x00000000 +#define DDRSS1_PI_143_DATA 0x00000000 +#define DDRSS1_PI_144_DATA 0x01000000 +#define DDRSS1_PI_145_DATA 0x00010003 +#define DDRSS1_PI_146_DATA 0x02000101 +#define DDRSS1_PI_147_DATA 0x01030001 +#define DDRSS1_PI_148_DATA 0x00010400 +#define DDRSS1_PI_149_DATA 0x06000105 +#define DDRSS1_PI_150_DATA 0x01070001 +#define DDRSS1_PI_151_DATA 0x00000000 +#define DDRSS1_PI_152_DATA 0x00000000 +#define DDRSS1_PI_153_DATA 0x00000000 +#define DDRSS1_PI_154_DATA 0x00010001 +#define DDRSS1_PI_155_DATA 0x00000000 +#define DDRSS1_PI_156_DATA 0x00000000 +#define DDRSS1_PI_157_DATA 0x00000000 +#define DDRSS1_PI_158_DATA 0x00000000 +#define DDRSS1_PI_159_DATA 0x00000401 +#define DDRSS1_PI_160_DATA 0x00000000 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 +#define DDRSS1_PI_164_DATA 0x00000034 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 +#define DDRSS1_PI_167_DATA 0x02000200 +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 +#define DDRSS1_PI_171_DATA 0x0000032B +#define DDRSS1_PI_172_DATA 0x00001035 +#define DDRSS1_PI_173_DATA 0x0000032B +#define DDRSS1_PI_174_DATA 0x04001035 +#define DDRSS1_PI_175_DATA 0x01010404 +#define DDRSS1_PI_176_DATA 0x00001500 +#define DDRSS1_PI_177_DATA 0x00150015 +#define DDRSS1_PI_178_DATA 0x01000100 +#define DDRSS1_PI_179_DATA 0x00000100 +#define DDRSS1_PI_180_DATA 0x00000000 +#define DDRSS1_PI_181_DATA 0x01010101 +#define DDRSS1_PI_182_DATA 0x00000000 +#define DDRSS1_PI_183_DATA 0x00000000 +#define DDRSS1_PI_184_DATA 0x00000000 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 +#define DDRSS1_PI_187_DATA 0x00040402 +#define DDRSS1_PI_188_DATA 0x000D0035 +#define DDRSS1_PI_189_DATA 0x00218049 +#define DDRSS1_PI_190_DATA 0x00218049 +#define DDRSS1_PI_191_DATA 0x01000101 +#define DDRSS1_PI_192_DATA 0x0004000E +#define DDRSS1_PI_193_DATA 0x00040216 +#define DDRSS1_PI_194_DATA 0x01000216 +#define DDRSS1_PI_195_DATA 0x000F000F +#define DDRSS1_PI_196_DATA 0x02170100 +#define DDRSS1_PI_197_DATA 0x01000217 +#define DDRSS1_PI_198_DATA 0x02170217 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B +#define DDRSS1_PI_201_DATA 0x0A070601 +#define DDRSS1_PI_202_DATA 0x1F130A0D +#define DDRSS1_PI_203_DATA 0x1F130A14 +#define DDRSS1_PI_204_DATA 0x0000C014 +#define DDRSS1_PI_205_DATA 0x00C01000 +#define DDRSS1_PI_206_DATA 0x00C01000 +#define DDRSS1_PI_207_DATA 0x00021000 +#define DDRSS1_PI_208_DATA 0x0024000E +#define DDRSS1_PI_209_DATA 0x00240216 +#define DDRSS1_PI_210_DATA 0x00110216 +#define DDRSS1_PI_211_DATA 0x32000056 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 +#define DDRSS1_PI_214_DATA 0x03013212 +#define DDRSS1_PI_215_DATA 0x00003600 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 +#define DDRSS1_PI_220_DATA 0x0A032001 +#define DDRSS1_PI_221_DATA 0x2C31110A +#define DDRSS1_PI_222_DATA 0x00002918 +#define DDRSS1_PI_223_DATA 0x6000838E +#define DDRSS1_PI_224_DATA 0x1E202008 +#define DDRSS1_PI_225_DATA 0x2C311116 +#define DDRSS1_PI_226_DATA 0x00002918 +#define DDRSS1_PI_227_DATA 0x6000838E +#define DDRSS1_PI_228_DATA 0x1E202008 +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 +#define DDRSS1_PI_235_DATA 0x033B0016 +#define DDRSS1_PI_236_DATA 0x0303033B +#define DDRSS1_PI_237_DATA 0x002AF803 +#define DDRSS1_PI_238_DATA 0x0001ADAF +#define DDRSS1_PI_239_DATA 0x00000005 +#define DDRSS1_PI_240_DATA 0x0000006E +#define DDRSS1_PI_241_DATA 0x00000016 +#define DDRSS1_PI_242_DATA 0x000681C8 +#define DDRSS1_PI_243_DATA 0x0001ADAF +#define DDRSS1_PI_244_DATA 0x00000005 +#define DDRSS1_PI_245_DATA 0x000010A9 +#define DDRSS1_PI_246_DATA 0x0000033B +#define DDRSS1_PI_247_DATA 0x000681C8 +#define DDRSS1_PI_248_DATA 0x0001ADAF +#define DDRSS1_PI_249_DATA 0x00000005 +#define DDRSS1_PI_250_DATA 0x000010A9 +#define DDRSS1_PI_251_DATA 0x0100033B +#define DDRSS1_PI_252_DATA 0x00370040 +#define DDRSS1_PI_253_DATA 0x00010008 +#define DDRSS1_PI_254_DATA 0x08550040 +#define DDRSS1_PI_255_DATA 0x00010040 +#define DDRSS1_PI_256_DATA 0x08550040 +#define DDRSS1_PI_257_DATA 0x00000340 +#define DDRSS1_PI_258_DATA 0x006B006B +#define DDRSS1_PI_259_DATA 0x08040404 +#define DDRSS1_PI_260_DATA 0x00000055 +#define DDRSS1_PI_261_DATA 0x55083C5A +#define DDRSS1_PI_262_DATA 0x5A000000 +#define DDRSS1_PI_263_DATA 0x0055083C +#define DDRSS1_PI_264_DATA 0x3C5A0000 +#define DDRSS1_PI_265_DATA 0x00005508 +#define DDRSS1_PI_266_DATA 0x0C3C5A00 +#define DDRSS1_PI_267_DATA 0x080F0E0D +#define DDRSS1_PI_268_DATA 0x000B0A09 +#define DDRSS1_PI_269_DATA 0x00030201 +#define DDRSS1_PI_270_DATA 0x01000000 +#define DDRSS1_PI_271_DATA 0x04020201 +#define DDRSS1_PI_272_DATA 0x00080804 +#define DDRSS1_PI_273_DATA 0x00000000 +#define DDRSS1_PI_274_DATA 0x00000000 +#define DDRSS1_PI_275_DATA 0x00F30084 +#define DDRSS1_PI_276_DATA 0x00160000 +#define DDRSS1_PI_277_DATA 0x36F33FF4 +#define DDRSS1_PI_278_DATA 0x00160F27 +#define DDRSS1_PI_279_DATA 0x36F33FF4 +#define DDRSS1_PI_280_DATA 0x00160F27 +#define DDRSS1_PI_281_DATA 0x00F30084 +#define DDRSS1_PI_282_DATA 0x00160000 +#define DDRSS1_PI_283_DATA 0x36F33FF4 +#define DDRSS1_PI_284_DATA 0x00160F27 +#define DDRSS1_PI_285_DATA 0x36F33FF4 +#define DDRSS1_PI_286_DATA 0x00160F27 +#define DDRSS1_PI_287_DATA 0x00F30084 +#define DDRSS1_PI_288_DATA 0x00160000 +#define DDRSS1_PI_289_DATA 0x36F33FF4 +#define DDRSS1_PI_290_DATA 0x00160F27 +#define DDRSS1_PI_291_DATA 0x36F33FF4 +#define DDRSS1_PI_292_DATA 0x00160F27 +#define DDRSS1_PI_293_DATA 0x00F30084 +#define DDRSS1_PI_294_DATA 0x00160000 +#define DDRSS1_PI_295_DATA 0x36F33FF4 +#define DDRSS1_PI_296_DATA 0x00160F27 +#define DDRSS1_PI_297_DATA 0x36F33FF4 +#define DDRSS1_PI_298_DATA 0x00160F27 +#define DDRSS1_PI_299_DATA 0x00000000 + +#define DDRSS1_PHY_00_DATA 0x000004F0 +#define DDRSS1_PHY_01_DATA 0x00000000 +#define DDRSS1_PHY_02_DATA 0x00030200 +#define DDRSS1_PHY_03_DATA 0x00000000 +#define DDRSS1_PHY_04_DATA 0x00000000 +#define DDRSS1_PHY_05_DATA 0x01030000 +#define DDRSS1_PHY_06_DATA 0x00010000 +#define DDRSS1_PHY_07_DATA 0x01030004 +#define DDRSS1_PHY_08_DATA 0x01000000 +#define DDRSS1_PHY_09_DATA 0x00000000 +#define DDRSS1_PHY_10_DATA 0x00000000 +#define DDRSS1_PHY_11_DATA 0x01000001 +#define DDRSS1_PHY_12_DATA 0x00000200 +#define DDRSS1_PHY_13_DATA 0x000800C0 +#define DDRSS1_PHY_14_DATA 0x060100CC +#define DDRSS1_PHY_15_DATA 0x00030066 +#define DDRSS1_PHY_16_DATA 0x00000000 +#define DDRSS1_PHY_17_DATA 0x00000301 +#define DDRSS1_PHY_18_DATA 0x0000AAAA +#define DDRSS1_PHY_19_DATA 0x00005555 +#define DDRSS1_PHY_20_DATA 0x0000B5B5 +#define DDRSS1_PHY_21_DATA 0x00004A4A +#define DDRSS1_PHY_22_DATA 0x00005656 +#define DDRSS1_PHY_23_DATA 0x0000A9A9 +#define DDRSS1_PHY_24_DATA 0x0000A9A9 +#define DDRSS1_PHY_25_DATA 0x0000B5B5 +#define DDRSS1_PHY_26_DATA 0x00000000 +#define DDRSS1_PHY_27_DATA 0x00000000 +#define DDRSS1_PHY_28_DATA 0x2A000000 +#define DDRSS1_PHY_29_DATA 0x00000808 +#define DDRSS1_PHY_30_DATA 0x0F000000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 +#define DDRSS1_PHY_33_DATA 0x0C002006 +#define DDRSS1_PHY_34_DATA 0x00000000 +#define DDRSS1_PHY_35_DATA 0x00000000 +#define DDRSS1_PHY_36_DATA 0x55555555 +#define DDRSS1_PHY_37_DATA 0xAAAAAAAA +#define DDRSS1_PHY_38_DATA 0x55555555 +#define DDRSS1_PHY_39_DATA 0xAAAAAAAA +#define DDRSS1_PHY_40_DATA 0x00005555 +#define DDRSS1_PHY_41_DATA 0x01000100 +#define DDRSS1_PHY_42_DATA 0x00800180 +#define DDRSS1_PHY_43_DATA 0x00000001 +#define DDRSS1_PHY_44_DATA 0x00000000 +#define DDRSS1_PHY_45_DATA 0x00000000 +#define DDRSS1_PHY_46_DATA 0x00000000 +#define DDRSS1_PHY_47_DATA 0x00000000 +#define DDRSS1_PHY_48_DATA 0x00000000 +#define DDRSS1_PHY_49_DATA 0x00000000 +#define DDRSS1_PHY_50_DATA 0x00000000 +#define DDRSS1_PHY_51_DATA 0x00000000 +#define DDRSS1_PHY_52_DATA 0x00000000 +#define DDRSS1_PHY_53_DATA 0x00000000 +#define DDRSS1_PHY_54_DATA 0x00000000 +#define DDRSS1_PHY_55_DATA 0x00000000 +#define DDRSS1_PHY_56_DATA 0x00000000 +#define DDRSS1_PHY_57_DATA 0x00000000 +#define DDRSS1_PHY_58_DATA 0x00000000 +#define DDRSS1_PHY_59_DATA 0x00000000 +#define DDRSS1_PHY_60_DATA 0x00000000 +#define DDRSS1_PHY_61_DATA 0x00000000 +#define DDRSS1_PHY_62_DATA 0x00000000 +#define DDRSS1_PHY_63_DATA 0x00000000 +#define DDRSS1_PHY_64_DATA 0x00000000 +#define DDRSS1_PHY_65_DATA 0x00000000 +#define DDRSS1_PHY_66_DATA 0x00000104 +#define DDRSS1_PHY_67_DATA 0x00000120 +#define DDRSS1_PHY_68_DATA 0x00000000 +#define DDRSS1_PHY_69_DATA 0x00000000 +#define DDRSS1_PHY_70_DATA 0x00000000 +#define DDRSS1_PHY_71_DATA 0x00000000 +#define DDRSS1_PHY_72_DATA 0x00000000 +#define DDRSS1_PHY_73_DATA 0x00000000 +#define DDRSS1_PHY_74_DATA 0x00000000 +#define DDRSS1_PHY_75_DATA 0x00000001 +#define DDRSS1_PHY_76_DATA 0x07FF0000 +#define DDRSS1_PHY_77_DATA 0x0080081F +#define DDRSS1_PHY_78_DATA 0x00081020 +#define DDRSS1_PHY_79_DATA 0x04010000 +#define DDRSS1_PHY_80_DATA 0x00000000 +#define DDRSS1_PHY_81_DATA 0x00000000 +#define DDRSS1_PHY_82_DATA 0x00000000 +#define DDRSS1_PHY_83_DATA 0x00000100 +#define DDRSS1_PHY_84_DATA 0x01CC0C01 +#define DDRSS1_PHY_85_DATA 0x1003CC0C +#define DDRSS1_PHY_86_DATA 0x20000140 +#define DDRSS1_PHY_87_DATA 0x07FF0200 +#define DDRSS1_PHY_88_DATA 0x0000DD01 +#define DDRSS1_PHY_89_DATA 0x10100303 +#define DDRSS1_PHY_90_DATA 0x10101010 +#define DDRSS1_PHY_91_DATA 0x10101010 +#define DDRSS1_PHY_92_DATA 0x00021010 +#define DDRSS1_PHY_93_DATA 0x00100010 +#define DDRSS1_PHY_94_DATA 0x00100010 +#define DDRSS1_PHY_95_DATA 0x00100010 +#define DDRSS1_PHY_96_DATA 0x00100010 +#define DDRSS1_PHY_97_DATA 0x00050010 +#define DDRSS1_PHY_98_DATA 0x51517041 +#define DDRSS1_PHY_99_DATA 0x31C06001 +#define DDRSS1_PHY_100_DATA 0x07AB01AB +#define DDRSS1_PHY_101_DATA 0x00C0C001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 +#define DDRSS1_PHY_103_DATA 0x10001000 +#define DDRSS1_PHY_104_DATA 0x0C083E42 +#define DDRSS1_PHY_105_DATA 0x0F0C3701 +#define DDRSS1_PHY_106_DATA 0x01000140 +#define DDRSS1_PHY_107_DATA 0x0C000420 +#define DDRSS1_PHY_108_DATA 0x00000198 +#define DDRSS1_PHY_109_DATA 0x0A0000D0 +#define DDRSS1_PHY_110_DATA 0x00030200 +#define DDRSS1_PHY_111_DATA 0x02800000 +#define DDRSS1_PHY_112_DATA 0x80800000 +#define DDRSS1_PHY_113_DATA 0x000E2010 +#define DDRSS1_PHY_114_DATA 0x76543210 +#define DDRSS1_PHY_115_DATA 0x00000008 +#define DDRSS1_PHY_116_DATA 0x02800280 +#define DDRSS1_PHY_117_DATA 0x02800280 +#define DDRSS1_PHY_118_DATA 0x02800280 +#define DDRSS1_PHY_119_DATA 0x02800280 +#define DDRSS1_PHY_120_DATA 0x00000280 +#define DDRSS1_PHY_121_DATA 0x0000A000 +#define DDRSS1_PHY_122_DATA 0x00A000A0 +#define DDRSS1_PHY_123_DATA 0x00A000A0 +#define DDRSS1_PHY_124_DATA 0x00A000A0 +#define DDRSS1_PHY_125_DATA 0x00A000A0 +#define DDRSS1_PHY_126_DATA 0x00A000A0 +#define DDRSS1_PHY_127_DATA 0x00A000A0 +#define DDRSS1_PHY_128_DATA 0x00A000A0 +#define DDRSS1_PHY_129_DATA 0x00A000A0 +#define DDRSS1_PHY_130_DATA 0x01C200A0 +#define DDRSS1_PHY_131_DATA 0x01A00005 +#define DDRSS1_PHY_132_DATA 0x00000000 +#define DDRSS1_PHY_133_DATA 0x00000000 +#define DDRSS1_PHY_134_DATA 0x00080200 +#define DDRSS1_PHY_135_DATA 0x00000000 +#define DDRSS1_PHY_136_DATA 0x20202020 +#define DDRSS1_PHY_137_DATA 0x20202020 +#define DDRSS1_PHY_138_DATA 0xF0F02020 +#define DDRSS1_PHY_139_DATA 0x00000000 +#define DDRSS1_PHY_140_DATA 0x00000000 +#define DDRSS1_PHY_141_DATA 0x00000000 +#define DDRSS1_PHY_142_DATA 0x00000000 +#define DDRSS1_PHY_143_DATA 0x00000000 +#define DDRSS1_PHY_144_DATA 0x00000000 +#define DDRSS1_PHY_145_DATA 0x00000000 +#define DDRSS1_PHY_146_DATA 0x00000000 +#define DDRSS1_PHY_147_DATA 0x00000000 +#define DDRSS1_PHY_148_DATA 0x00000000 +#define DDRSS1_PHY_149_DATA 0x00000000 +#define DDRSS1_PHY_150_DATA 0x00000000 +#define DDRSS1_PHY_151_DATA 0x00000000 +#define DDRSS1_PHY_152_DATA 0x00000000 +#define DDRSS1_PHY_153_DATA 0x00000000 +#define DDRSS1_PHY_154_DATA 0x00000000 +#define DDRSS1_PHY_155_DATA 0x00000000 +#define DDRSS1_PHY_156_DATA 0x00000000 +#define DDRSS1_PHY_157_DATA 0x00000000 +#define DDRSS1_PHY_158_DATA 0x00000000 +#define DDRSS1_PHY_159_DATA 0x00000000 +#define DDRSS1_PHY_160_DATA 0x00000000 +#define DDRSS1_PHY_161_DATA 0x00000000 +#define DDRSS1_PHY_162_DATA 0x00000000 +#define DDRSS1_PHY_163_DATA 0x00000000 +#define DDRSS1_PHY_164_DATA 0x00000000 +#define DDRSS1_PHY_165_DATA 0x00000000 +#define DDRSS1_PHY_166_DATA 0x00000000 +#define DDRSS1_PHY_167_DATA 0x00000000 +#define DDRSS1_PHY_168_DATA 0x00000000 +#define DDRSS1_PHY_169_DATA 0x00000000 +#define DDRSS1_PHY_170_DATA 0x00000000 +#define DDRSS1_PHY_171_DATA 0x00000000 +#define DDRSS1_PHY_172_DATA 0x00000000 +#define DDRSS1_PHY_173_DATA 0x00000000 +#define DDRSS1_PHY_174_DATA 0x00000000 +#define DDRSS1_PHY_175_DATA 0x00000000 +#define DDRSS1_PHY_176_DATA 0x00000000 +#define DDRSS1_PHY_177_DATA 0x00000000 +#define DDRSS1_PHY_178_DATA 0x00000000 +#define DDRSS1_PHY_179_DATA 0x00000000 +#define DDRSS1_PHY_180_DATA 0x00000000 +#define DDRSS1_PHY_181_DATA 0x00000000 +#define DDRSS1_PHY_182_DATA 0x00000000 +#define DDRSS1_PHY_183_DATA 0x00000000 +#define DDRSS1_PHY_184_DATA 0x00000000 +#define DDRSS1_PHY_185_DATA 0x00000000 +#define DDRSS1_PHY_186_DATA 0x00000000 +#define DDRSS1_PHY_187_DATA 0x00000000 +#define DDRSS1_PHY_188_DATA 0x00000000 +#define DDRSS1_PHY_189_DATA 0x00000000 +#define DDRSS1_PHY_190_DATA 0x00000000 +#define DDRSS1_PHY_191_DATA 0x00000000 +#define DDRSS1_PHY_192_DATA 0x00000000 +#define DDRSS1_PHY_193_DATA 0x00000000 +#define DDRSS1_PHY_194_DATA 0x00000000 +#define DDRSS1_PHY_195_DATA 0x00000000 +#define DDRSS1_PHY_196_DATA 0x00000000 +#define DDRSS1_PHY_197_DATA 0x00000000 +#define DDRSS1_PHY_198_DATA 0x00000000 +#define DDRSS1_PHY_199_DATA 0x00000000 +#define DDRSS1_PHY_200_DATA 0x00000000 +#define DDRSS1_PHY_201_DATA 0x00000000 +#define DDRSS1_PHY_202_DATA 0x00000000 +#define DDRSS1_PHY_203_DATA 0x00000000 +#define DDRSS1_PHY_204_DATA 0x00000000 +#define DDRSS1_PHY_205_DATA 0x00000000 +#define DDRSS1_PHY_206_DATA 0x00000000 +#define DDRSS1_PHY_207_DATA 0x00000000 +#define DDRSS1_PHY_208_DATA 0x00000000 +#define DDRSS1_PHY_209_DATA 0x00000000 +#define DDRSS1_PHY_210_DATA 0x00000000 +#define DDRSS1_PHY_211_DATA 0x00000000 +#define DDRSS1_PHY_212_DATA 0x00000000 +#define DDRSS1_PHY_213_DATA 0x00000000 +#define DDRSS1_PHY_214_DATA 0x00000000 +#define DDRSS1_PHY_215_DATA 0x00000000 +#define DDRSS1_PHY_216_DATA 0x00000000 +#define DDRSS1_PHY_217_DATA 0x00000000 +#define DDRSS1_PHY_218_DATA 0x00000000 +#define DDRSS1_PHY_219_DATA 0x00000000 +#define DDRSS1_PHY_220_DATA 0x00000000 +#define DDRSS1_PHY_221_DATA 0x00000000 +#define DDRSS1_PHY_222_DATA 0x00000000 +#define DDRSS1_PHY_223_DATA 0x00000000 +#define DDRSS1_PHY_224_DATA 0x00000000 +#define DDRSS1_PHY_225_DATA 0x00000000 +#define DDRSS1_PHY_226_DATA 0x00000000 +#define DDRSS1_PHY_227_DATA 0x00000000 +#define DDRSS1_PHY_228_DATA 0x00000000 +#define DDRSS1_PHY_229_DATA 0x00000000 +#define DDRSS1_PHY_230_DATA 0x00000000 +#define DDRSS1_PHY_231_DATA 0x00000000 +#define DDRSS1_PHY_232_DATA 0x00000000 +#define DDRSS1_PHY_233_DATA 0x00000000 +#define DDRSS1_PHY_234_DATA 0x00000000 +#define DDRSS1_PHY_235_DATA 0x00000000 +#define DDRSS1_PHY_236_DATA 0x00000000 +#define DDRSS1_PHY_237_DATA 0x00000000 +#define DDRSS1_PHY_238_DATA 0x00000000 +#define DDRSS1_PHY_239_DATA 0x00000000 +#define DDRSS1_PHY_240_DATA 0x00000000 +#define DDRSS1_PHY_241_DATA 0x00000000 +#define DDRSS1_PHY_242_DATA 0x00000000 +#define DDRSS1_PHY_243_DATA 0x00000000 +#define DDRSS1_PHY_244_DATA 0x00000000 +#define DDRSS1_PHY_245_DATA 0x00000000 +#define DDRSS1_PHY_246_DATA 0x00000000 +#define DDRSS1_PHY_247_DATA 0x00000000 +#define DDRSS1_PHY_248_DATA 0x00000000 +#define DDRSS1_PHY_249_DATA 0x00000000 +#define DDRSS1_PHY_250_DATA 0x00000000 +#define DDRSS1_PHY_251_DATA 0x00000000 +#define DDRSS1_PHY_252_DATA 0x00000000 +#define DDRSS1_PHY_253_DATA 0x00000000 +#define DDRSS1_PHY_254_DATA 0x00000000 +#define DDRSS1_PHY_255_DATA 0x00000000 +#define DDRSS1_PHY_256_DATA 0x000004F0 +#define DDRSS1_PHY_257_DATA 0x00000000 +#define DDRSS1_PHY_258_DATA 0x00030200 +#define DDRSS1_PHY_259_DATA 0x00000000 +#define DDRSS1_PHY_260_DATA 0x00000000 +#define DDRSS1_PHY_261_DATA 0x01030000 +#define DDRSS1_PHY_262_DATA 0x00010000 +#define DDRSS1_PHY_263_DATA 0x01030004 +#define DDRSS1_PHY_264_DATA 0x01000000 +#define DDRSS1_PHY_265_DATA 0x00000000 +#define DDRSS1_PHY_266_DATA 0x00000000 +#define DDRSS1_PHY_267_DATA 0x01000001 +#define DDRSS1_PHY_268_DATA 0x00000200 +#define DDRSS1_PHY_269_DATA 0x000800C0 +#define DDRSS1_PHY_270_DATA 0x060100CC +#define DDRSS1_PHY_271_DATA 0x00030066 +#define DDRSS1_PHY_272_DATA 0x00000000 +#define DDRSS1_PHY_273_DATA 0x00000301 +#define DDRSS1_PHY_274_DATA 0x0000AAAA +#define DDRSS1_PHY_275_DATA 0x00005555 +#define DDRSS1_PHY_276_DATA 0x0000B5B5 +#define DDRSS1_PHY_277_DATA 0x00004A4A +#define DDRSS1_PHY_278_DATA 0x00005656 +#define DDRSS1_PHY_279_DATA 0x0000A9A9 +#define DDRSS1_PHY_280_DATA 0x0000A9A9 +#define DDRSS1_PHY_281_DATA 0x0000B5B5 +#define DDRSS1_PHY_282_DATA 0x00000000 +#define DDRSS1_PHY_283_DATA 0x00000000 +#define DDRSS1_PHY_284_DATA 0x2A000000 +#define DDRSS1_PHY_285_DATA 0x00000808 +#define DDRSS1_PHY_286_DATA 0x0F000000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 +#define DDRSS1_PHY_289_DATA 0x0C002006 +#define DDRSS1_PHY_290_DATA 0x00000000 +#define DDRSS1_PHY_291_DATA 0x00000000 +#define DDRSS1_PHY_292_DATA 0x55555555 +#define DDRSS1_PHY_293_DATA 0xAAAAAAAA +#define DDRSS1_PHY_294_DATA 0x55555555 +#define DDRSS1_PHY_295_DATA 0xAAAAAAAA +#define DDRSS1_PHY_296_DATA 0x00005555 +#define DDRSS1_PHY_297_DATA 0x01000100 +#define DDRSS1_PHY_298_DATA 0x00800180 +#define DDRSS1_PHY_299_DATA 0x00000000 +#define DDRSS1_PHY_300_DATA 0x00000000 +#define DDRSS1_PHY_301_DATA 0x00000000 +#define DDRSS1_PHY_302_DATA 0x00000000 +#define DDRSS1_PHY_303_DATA 0x00000000 +#define DDRSS1_PHY_304_DATA 0x00000000 +#define DDRSS1_PHY_305_DATA 0x00000000 +#define DDRSS1_PHY_306_DATA 0x00000000 +#define DDRSS1_PHY_307_DATA 0x00000000 +#define DDRSS1_PHY_308_DATA 0x00000000 +#define DDRSS1_PHY_309_DATA 0x00000000 +#define DDRSS1_PHY_310_DATA 0x00000000 +#define DDRSS1_PHY_311_DATA 0x00000000 +#define DDRSS1_PHY_312_DATA 0x00000000 +#define DDRSS1_PHY_313_DATA 0x00000000 +#define DDRSS1_PHY_314_DATA 0x00000000 +#define DDRSS1_PHY_315_DATA 0x00000000 +#define DDRSS1_PHY_316_DATA 0x00000000 +#define DDRSS1_PHY_317_DATA 0x00000000 +#define DDRSS1_PHY_318_DATA 0x00000000 +#define DDRSS1_PHY_319_DATA 0x00000000 +#define DDRSS1_PHY_320_DATA 0x00000000 +#define DDRSS1_PHY_321_DATA 0x00000000 +#define DDRSS1_PHY_322_DATA 0x00000104 +#define DDRSS1_PHY_323_DATA 0x00000120 +#define DDRSS1_PHY_324_DATA 0x00000000 +#define DDRSS1_PHY_325_DATA 0x00000000 +#define DDRSS1_PHY_326_DATA 0x00000000 +#define DDRSS1_PHY_327_DATA 0x00000000 +#define DDRSS1_PHY_328_DATA 0x00000000 +#define DDRSS1_PHY_329_DATA 0x00000000 +#define DDRSS1_PHY_330_DATA 0x00000000 +#define DDRSS1_PHY_331_DATA 0x00000001 +#define DDRSS1_PHY_332_DATA 0x07FF0000 +#define DDRSS1_PHY_333_DATA 0x0080081F +#define DDRSS1_PHY_334_DATA 0x00081020 +#define DDRSS1_PHY_335_DATA 0x04010000 +#define DDRSS1_PHY_336_DATA 0x00000000 +#define DDRSS1_PHY_337_DATA 0x00000000 +#define DDRSS1_PHY_338_DATA 0x00000000 +#define DDRSS1_PHY_339_DATA 0x00000100 +#define DDRSS1_PHY_340_DATA 0x01CC0C01 +#define DDRSS1_PHY_341_DATA 0x1003CC0C +#define DDRSS1_PHY_342_DATA 0x20000140 +#define DDRSS1_PHY_343_DATA 0x07FF0200 +#define DDRSS1_PHY_344_DATA 0x0000DD01 +#define DDRSS1_PHY_345_DATA 0x10100303 +#define DDRSS1_PHY_346_DATA 0x10101010 +#define DDRSS1_PHY_347_DATA 0x10101010 +#define DDRSS1_PHY_348_DATA 0x00021010 +#define DDRSS1_PHY_349_DATA 0x00100010 +#define DDRSS1_PHY_350_DATA 0x00100010 +#define DDRSS1_PHY_351_DATA 0x00100010 +#define DDRSS1_PHY_352_DATA 0x00100010 +#define DDRSS1_PHY_353_DATA 0x00050010 +#define DDRSS1_PHY_354_DATA 0x51517041 +#define DDRSS1_PHY_355_DATA 0x31C06001 +#define DDRSS1_PHY_356_DATA 0x07AB01AB +#define DDRSS1_PHY_357_DATA 0x00C0C001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 +#define DDRSS1_PHY_359_DATA 0x10001000 +#define DDRSS1_PHY_360_DATA 0x0C083E42 +#define DDRSS1_PHY_361_DATA 0x0F0C3701 +#define DDRSS1_PHY_362_DATA 0x01000140 +#define DDRSS1_PHY_363_DATA 0x0C000420 +#define DDRSS1_PHY_364_DATA 0x00000198 +#define DDRSS1_PHY_365_DATA 0x0A0000D0 +#define DDRSS1_PHY_366_DATA 0x00030200 +#define DDRSS1_PHY_367_DATA 0x02800000 +#define DDRSS1_PHY_368_DATA 0x80800000 +#define DDRSS1_PHY_369_DATA 0x000E2010 +#define DDRSS1_PHY_370_DATA 0x76543210 +#define DDRSS1_PHY_371_DATA 0x00000008 +#define DDRSS1_PHY_372_DATA 0x02800280 +#define DDRSS1_PHY_373_DATA 0x02800280 +#define DDRSS1_PHY_374_DATA 0x02800280 +#define DDRSS1_PHY_375_DATA 0x02800280 +#define DDRSS1_PHY_376_DATA 0x00000280 +#define DDRSS1_PHY_377_DATA 0x0000A000 +#define DDRSS1_PHY_378_DATA 0x00A000A0 +#define DDRSS1_PHY_379_DATA 0x00A000A0 +#define DDRSS1_PHY_380_DATA 0x00A000A0 +#define DDRSS1_PHY_381_DATA 0x00A000A0 +#define DDRSS1_PHY_382_DATA 0x00A000A0 +#define DDRSS1_PHY_383_DATA 0x00A000A0 +#define DDRSS1_PHY_384_DATA 0x00A000A0 +#define DDRSS1_PHY_385_DATA 0x00A000A0 +#define DDRSS1_PHY_386_DATA 0x01C200A0 +#define DDRSS1_PHY_387_DATA 0x01A00005 +#define DDRSS1_PHY_388_DATA 0x00000000 +#define DDRSS1_PHY_389_DATA 0x00000000 +#define DDRSS1_PHY_390_DATA 0x00080200 +#define DDRSS1_PHY_391_DATA 0x00000000 +#define DDRSS1_PHY_392_DATA 0x20202020 +#define DDRSS1_PHY_393_DATA 0x20202020 +#define DDRSS1_PHY_394_DATA 0xF0F02020 +#define DDRSS1_PHY_395_DATA 0x00000000 +#define DDRSS1_PHY_396_DATA 0x00000000 +#define DDRSS1_PHY_397_DATA 0x00000000 +#define DDRSS1_PHY_398_DATA 0x00000000 +#define DDRSS1_PHY_399_DATA 0x00000000 +#define DDRSS1_PHY_400_DATA 0x00000000 +#define DDRSS1_PHY_401_DATA 0x00000000 +#define DDRSS1_PHY_402_DATA 0x00000000 +#define DDRSS1_PHY_403_DATA 0x00000000 +#define DDRSS1_PHY_404_DATA 0x00000000 +#define DDRSS1_PHY_405_DATA 0x00000000 +#define DDRSS1_PHY_406_DATA 0x00000000 +#define DDRSS1_PHY_407_DATA 0x00000000 +#define DDRSS1_PHY_408_DATA 0x00000000 +#define DDRSS1_PHY_409_DATA 0x00000000 +#define DDRSS1_PHY_410_DATA 0x00000000 +#define DDRSS1_PHY_411_DATA 0x00000000 +#define DDRSS1_PHY_412_DATA 0x00000000 +#define DDRSS1_PHY_413_DATA 0x00000000 +#define DDRSS1_PHY_414_DATA 0x00000000 +#define DDRSS1_PHY_415_DATA 0x00000000 +#define DDRSS1_PHY_416_DATA 0x00000000 +#define DDRSS1_PHY_417_DATA 0x00000000 +#define DDRSS1_PHY_418_DATA 0x00000000 +#define DDRSS1_PHY_419_DATA 0x00000000 +#define DDRSS1_PHY_420_DATA 0x00000000 +#define DDRSS1_PHY_421_DATA 0x00000000 +#define DDRSS1_PHY_422_DATA 0x00000000 +#define DDRSS1_PHY_423_DATA 0x00000000 +#define DDRSS1_PHY_424_DATA 0x00000000 +#define DDRSS1_PHY_425_DATA 0x00000000 +#define DDRSS1_PHY_426_DATA 0x00000000 +#define DDRSS1_PHY_427_DATA 0x00000000 +#define DDRSS1_PHY_428_DATA 0x00000000 +#define DDRSS1_PHY_429_DATA 0x00000000 +#define DDRSS1_PHY_430_DATA 0x00000000 +#define DDRSS1_PHY_431_DATA 0x00000000 +#define DDRSS1_PHY_432_DATA 0x00000000 +#define DDRSS1_PHY_433_DATA 0x00000000 +#define DDRSS1_PHY_434_DATA 0x00000000 +#define DDRSS1_PHY_435_DATA 0x00000000 +#define DDRSS1_PHY_436_DATA 0x00000000 +#define DDRSS1_PHY_437_DATA 0x00000000 +#define DDRSS1_PHY_438_DATA 0x00000000 +#define DDRSS1_PHY_439_DATA 0x00000000 +#define DDRSS1_PHY_440_DATA 0x00000000 +#define DDRSS1_PHY_441_DATA 0x00000000 +#define DDRSS1_PHY_442_DATA 0x00000000 +#define DDRSS1_PHY_443_DATA 0x00000000 +#define DDRSS1_PHY_444_DATA 0x00000000 +#define DDRSS1_PHY_445_DATA 0x00000000 +#define DDRSS1_PHY_446_DATA 0x00000000 +#define DDRSS1_PHY_447_DATA 0x00000000 +#define DDRSS1_PHY_448_DATA 0x00000000 +#define DDRSS1_PHY_449_DATA 0x00000000 +#define DDRSS1_PHY_450_DATA 0x00000000 +#define DDRSS1_PHY_451_DATA 0x00000000 +#define DDRSS1_PHY_452_DATA 0x00000000 +#define DDRSS1_PHY_453_DATA 0x00000000 +#define DDRSS1_PHY_454_DATA 0x00000000 +#define DDRSS1_PHY_455_DATA 0x00000000 +#define DDRSS1_PHY_456_DATA 0x00000000 +#define DDRSS1_PHY_457_DATA 0x00000000 +#define DDRSS1_PHY_458_DATA 0x00000000 +#define DDRSS1_PHY_459_DATA 0x00000000 +#define DDRSS1_PHY_460_DATA 0x00000000 +#define DDRSS1_PHY_461_DATA 0x00000000 +#define DDRSS1_PHY_462_DATA 0x00000000 +#define DDRSS1_PHY_463_DATA 0x00000000 +#define DDRSS1_PHY_464_DATA 0x00000000 +#define DDRSS1_PHY_465_DATA 0x00000000 +#define DDRSS1_PHY_466_DATA 0x00000000 +#define DDRSS1_PHY_467_DATA 0x00000000 +#define DDRSS1_PHY_468_DATA 0x00000000 +#define DDRSS1_PHY_469_DATA 0x00000000 +#define DDRSS1_PHY_470_DATA 0x00000000 +#define DDRSS1_PHY_471_DATA 0x00000000 +#define DDRSS1_PHY_472_DATA 0x00000000 +#define DDRSS1_PHY_473_DATA 0x00000000 +#define DDRSS1_PHY_474_DATA 0x00000000 +#define DDRSS1_PHY_475_DATA 0x00000000 +#define DDRSS1_PHY_476_DATA 0x00000000 +#define DDRSS1_PHY_477_DATA 0x00000000 +#define DDRSS1_PHY_478_DATA 0x00000000 +#define DDRSS1_PHY_479_DATA 0x00000000 +#define DDRSS1_PHY_480_DATA 0x00000000 +#define DDRSS1_PHY_481_DATA 0x00000000 +#define DDRSS1_PHY_482_DATA 0x00000000 +#define DDRSS1_PHY_483_DATA 0x00000000 +#define DDRSS1_PHY_484_DATA 0x00000000 +#define DDRSS1_PHY_485_DATA 0x00000000 +#define DDRSS1_PHY_486_DATA 0x00000000 +#define DDRSS1_PHY_487_DATA 0x00000000 +#define DDRSS1_PHY_488_DATA 0x00000000 +#define DDRSS1_PHY_489_DATA 0x00000000 +#define DDRSS1_PHY_490_DATA 0x00000000 +#define DDRSS1_PHY_491_DATA 0x00000000 +#define DDRSS1_PHY_492_DATA 0x00000000 +#define DDRSS1_PHY_493_DATA 0x00000000 +#define DDRSS1_PHY_494_DATA 0x00000000 +#define DDRSS1_PHY_495_DATA 0x00000000 +#define DDRSS1_PHY_496_DATA 0x00000000 +#define DDRSS1_PHY_497_DATA 0x00000000 +#define DDRSS1_PHY_498_DATA 0x00000000 +#define DDRSS1_PHY_499_DATA 0x00000000 +#define DDRSS1_PHY_500_DATA 0x00000000 +#define DDRSS1_PHY_501_DATA 0x00000000 +#define DDRSS1_PHY_502_DATA 0x00000000 +#define DDRSS1_PHY_503_DATA 0x00000000 +#define DDRSS1_PHY_504_DATA 0x00000000 +#define DDRSS1_PHY_505_DATA 0x00000000 +#define DDRSS1_PHY_506_DATA 0x00000000 +#define DDRSS1_PHY_507_DATA 0x00000000 +#define DDRSS1_PHY_508_DATA 0x00000000 +#define DDRSS1_PHY_509_DATA 0x00000000 +#define DDRSS1_PHY_510_DATA 0x00000000 +#define DDRSS1_PHY_511_DATA 0x00000000 +#define DDRSS1_PHY_512_DATA 0x000004F0 +#define DDRSS1_PHY_513_DATA 0x00000000 +#define DDRSS1_PHY_514_DATA 0x00030200 +#define DDRSS1_PHY_515_DATA 0x00000000 +#define DDRSS1_PHY_516_DATA 0x00000000 +#define DDRSS1_PHY_517_DATA 0x01030000 +#define DDRSS1_PHY_518_DATA 0x00010000 +#define DDRSS1_PHY_519_DATA 0x01030004 +#define DDRSS1_PHY_520_DATA 0x01000000 +#define DDRSS1_PHY_521_DATA 0x00000000 +#define DDRSS1_PHY_522_DATA 0x00000000 +#define DDRSS1_PHY_523_DATA 0x01000001 +#define DDRSS1_PHY_524_DATA 0x00000200 +#define DDRSS1_PHY_525_DATA 0x000800C0 +#define DDRSS1_PHY_526_DATA 0x060100CC +#define DDRSS1_PHY_527_DATA 0x00030066 +#define DDRSS1_PHY_528_DATA 0x00000000 +#define DDRSS1_PHY_529_DATA 0x00000301 +#define DDRSS1_PHY_530_DATA 0x0000AAAA +#define DDRSS1_PHY_531_DATA 0x00005555 +#define DDRSS1_PHY_532_DATA 0x0000B5B5 +#define DDRSS1_PHY_533_DATA 0x00004A4A +#define DDRSS1_PHY_534_DATA 0x00005656 +#define DDRSS1_PHY_535_DATA 0x0000A9A9 +#define DDRSS1_PHY_536_DATA 0x0000A9A9 +#define DDRSS1_PHY_537_DATA 0x0000B5B5 +#define DDRSS1_PHY_538_DATA 0x00000000 +#define DDRSS1_PHY_539_DATA 0x00000000 +#define DDRSS1_PHY_540_DATA 0x2A000000 +#define DDRSS1_PHY_541_DATA 0x00000808 +#define DDRSS1_PHY_542_DATA 0x0F000000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 +#define DDRSS1_PHY_545_DATA 0x0C002006 +#define DDRSS1_PHY_546_DATA 0x00000000 +#define DDRSS1_PHY_547_DATA 0x00000000 +#define DDRSS1_PHY_548_DATA 0x55555555 +#define DDRSS1_PHY_549_DATA 0xAAAAAAAA +#define DDRSS1_PHY_550_DATA 0x55555555 +#define DDRSS1_PHY_551_DATA 0xAAAAAAAA +#define DDRSS1_PHY_552_DATA 0x00005555 +#define DDRSS1_PHY_553_DATA 0x01000100 +#define DDRSS1_PHY_554_DATA 0x00800180 +#define DDRSS1_PHY_555_DATA 0x00000001 +#define DDRSS1_PHY_556_DATA 0x00000000 +#define DDRSS1_PHY_557_DATA 0x00000000 +#define DDRSS1_PHY_558_DATA 0x00000000 +#define DDRSS1_PHY_559_DATA 0x00000000 +#define DDRSS1_PHY_560_DATA 0x00000000 +#define DDRSS1_PHY_561_DATA 0x00000000 +#define DDRSS1_PHY_562_DATA 0x00000000 +#define DDRSS1_PHY_563_DATA 0x00000000 +#define DDRSS1_PHY_564_DATA 0x00000000 +#define DDRSS1_PHY_565_DATA 0x00000000 +#define DDRSS1_PHY_566_DATA 0x00000000 +#define DDRSS1_PHY_567_DATA 0x00000000 +#define DDRSS1_PHY_568_DATA 0x00000000 +#define DDRSS1_PHY_569_DATA 0x00000000 +#define DDRSS1_PHY_570_DATA 0x00000000 +#define DDRSS1_PHY_571_DATA 0x00000000 +#define DDRSS1_PHY_572_DATA 0x00000000 +#define DDRSS1_PHY_573_DATA 0x00000000 +#define DDRSS1_PHY_574_DATA 0x00000000 +#define DDRSS1_PHY_575_DATA 0x00000000 +#define DDRSS1_PHY_576_DATA 0x00000000 +#define DDRSS1_PHY_577_DATA 0x00000000 +#define DDRSS1_PHY_578_DATA 0x00000104 +#define DDRSS1_PHY_579_DATA 0x00000120 +#define DDRSS1_PHY_580_DATA 0x00000000 +#define DDRSS1_PHY_581_DATA 0x00000000 +#define DDRSS1_PHY_582_DATA 0x00000000 +#define DDRSS1_PHY_583_DATA 0x00000000 +#define DDRSS1_PHY_584_DATA 0x00000000 +#define DDRSS1_PHY_585_DATA 0x00000000 +#define DDRSS1_PHY_586_DATA 0x00000000 +#define DDRSS1_PHY_587_DATA 0x00000001 +#define DDRSS1_PHY_588_DATA 0x07FF0000 +#define DDRSS1_PHY_589_DATA 0x0080081F +#define DDRSS1_PHY_590_DATA 0x00081020 +#define DDRSS1_PHY_591_DATA 0x04010000 +#define DDRSS1_PHY_592_DATA 0x00000000 +#define DDRSS1_PHY_593_DATA 0x00000000 +#define DDRSS1_PHY_594_DATA 0x00000000 +#define DDRSS1_PHY_595_DATA 0x00000100 +#define DDRSS1_PHY_596_DATA 0x01CC0C01 +#define DDRSS1_PHY_597_DATA 0x1003CC0C +#define DDRSS1_PHY_598_DATA 0x20000140 +#define DDRSS1_PHY_599_DATA 0x07FF0200 +#define DDRSS1_PHY_600_DATA 0x0000DD01 +#define DDRSS1_PHY_601_DATA 0x10100303 +#define DDRSS1_PHY_602_DATA 0x10101010 +#define DDRSS1_PHY_603_DATA 0x10101010 +#define DDRSS1_PHY_604_DATA 0x00021010 +#define DDRSS1_PHY_605_DATA 0x00100010 +#define DDRSS1_PHY_606_DATA 0x00100010 +#define DDRSS1_PHY_607_DATA 0x00100010 +#define DDRSS1_PHY_608_DATA 0x00100010 +#define DDRSS1_PHY_609_DATA 0x00050010 +#define DDRSS1_PHY_610_DATA 0x51517041 +#define DDRSS1_PHY_611_DATA 0x31C06001 +#define DDRSS1_PHY_612_DATA 0x07AB01AB +#define DDRSS1_PHY_613_DATA 0x00C0C001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 +#define DDRSS1_PHY_615_DATA 0x10001000 +#define DDRSS1_PHY_616_DATA 0x0C083E42 +#define DDRSS1_PHY_617_DATA 0x0F0C3701 +#define DDRSS1_PHY_618_DATA 0x01000140 +#define DDRSS1_PHY_619_DATA 0x0C000420 +#define DDRSS1_PHY_620_DATA 0x00000198 +#define DDRSS1_PHY_621_DATA 0x0A0000D0 +#define DDRSS1_PHY_622_DATA 0x00030200 +#define DDRSS1_PHY_623_DATA 0x02800000 +#define DDRSS1_PHY_624_DATA 0x80800000 +#define DDRSS1_PHY_625_DATA 0x000E2010 +#define DDRSS1_PHY_626_DATA 0x76543210 +#define DDRSS1_PHY_627_DATA 0x00000008 +#define DDRSS1_PHY_628_DATA 0x02800280 +#define DDRSS1_PHY_629_DATA 0x02800280 +#define DDRSS1_PHY_630_DATA 0x02800280 +#define DDRSS1_PHY_631_DATA 0x02800280 +#define DDRSS1_PHY_632_DATA 0x00000280 +#define DDRSS1_PHY_633_DATA 0x0000A000 +#define DDRSS1_PHY_634_DATA 0x00A000A0 +#define DDRSS1_PHY_635_DATA 0x00A000A0 +#define DDRSS1_PHY_636_DATA 0x00A000A0 +#define DDRSS1_PHY_637_DATA 0x00A000A0 +#define DDRSS1_PHY_638_DATA 0x00A000A0 +#define DDRSS1_PHY_639_DATA 0x00A000A0 +#define DDRSS1_PHY_640_DATA 0x00A000A0 +#define DDRSS1_PHY_641_DATA 0x00A000A0 +#define DDRSS1_PHY_642_DATA 0x01C200A0 +#define DDRSS1_PHY_643_DATA 0x01A00005 +#define DDRSS1_PHY_644_DATA 0x00000000 +#define DDRSS1_PHY_645_DATA 0x00000000 +#define DDRSS1_PHY_646_DATA 0x00080200 +#define DDRSS1_PHY_647_DATA 0x00000000 +#define DDRSS1_PHY_648_DATA 0x20202020 +#define DDRSS1_PHY_649_DATA 0x20202020 +#define DDRSS1_PHY_650_DATA 0xF0F02020 +#define DDRSS1_PHY_651_DATA 0x00000000 +#define DDRSS1_PHY_652_DATA 0x00000000 +#define DDRSS1_PHY_653_DATA 0x00000000 +#define DDRSS1_PHY_654_DATA 0x00000000 +#define DDRSS1_PHY_655_DATA 0x00000000 +#define DDRSS1_PHY_656_DATA 0x00000000 +#define DDRSS1_PHY_657_DATA 0x00000000 +#define DDRSS1_PHY_658_DATA 0x00000000 +#define DDRSS1_PHY_659_DATA 0x00000000 +#define DDRSS1_PHY_660_DATA 0x00000000 +#define DDRSS1_PHY_661_DATA 0x00000000 +#define DDRSS1_PHY_662_DATA 0x00000000 +#define DDRSS1_PHY_663_DATA 0x00000000 +#define DDRSS1_PHY_664_DATA 0x00000000 +#define DDRSS1_PHY_665_DATA 0x00000000 +#define DDRSS1_PHY_666_DATA 0x00000000 +#define DDRSS1_PHY_667_DATA 0x00000000 +#define DDRSS1_PHY_668_DATA 0x00000000 +#define DDRSS1_PHY_669_DATA 0x00000000 +#define DDRSS1_PHY_670_DATA 0x00000000 +#define DDRSS1_PHY_671_DATA 0x00000000 +#define DDRSS1_PHY_672_DATA 0x00000000 +#define DDRSS1_PHY_673_DATA 0x00000000 +#define DDRSS1_PHY_674_DATA 0x00000000 +#define DDRSS1_PHY_675_DATA 0x00000000 +#define DDRSS1_PHY_676_DATA 0x00000000 +#define DDRSS1_PHY_677_DATA 0x00000000 +#define DDRSS1_PHY_678_DATA 0x00000000 +#define DDRSS1_PHY_679_DATA 0x00000000 +#define DDRSS1_PHY_680_DATA 0x00000000 +#define DDRSS1_PHY_681_DATA 0x00000000 +#define DDRSS1_PHY_682_DATA 0x00000000 +#define DDRSS1_PHY_683_DATA 0x00000000 +#define DDRSS1_PHY_684_DATA 0x00000000 +#define DDRSS1_PHY_685_DATA 0x00000000 +#define DDRSS1_PHY_686_DATA 0x00000000 +#define DDRSS1_PHY_687_DATA 0x00000000 +#define DDRSS1_PHY_688_DATA 0x00000000 +#define DDRSS1_PHY_689_DATA 0x00000000 +#define DDRSS1_PHY_690_DATA 0x00000000 +#define DDRSS1_PHY_691_DATA 0x00000000 +#define DDRSS1_PHY_692_DATA 0x00000000 +#define DDRSS1_PHY_693_DATA 0x00000000 +#define DDRSS1_PHY_694_DATA 0x00000000 +#define DDRSS1_PHY_695_DATA 0x00000000 +#define DDRSS1_PHY_696_DATA 0x00000000 +#define DDRSS1_PHY_697_DATA 0x00000000 +#define DDRSS1_PHY_698_DATA 0x00000000 +#define DDRSS1_PHY_699_DATA 0x00000000 +#define DDRSS1_PHY_700_DATA 0x00000000 +#define DDRSS1_PHY_701_DATA 0x00000000 +#define DDRSS1_PHY_702_DATA 0x00000000 +#define DDRSS1_PHY_703_DATA 0x00000000 +#define DDRSS1_PHY_704_DATA 0x00000000 +#define DDRSS1_PHY_705_DATA 0x00000000 +#define DDRSS1_PHY_706_DATA 0x00000000 +#define DDRSS1_PHY_707_DATA 0x00000000 +#define DDRSS1_PHY_708_DATA 0x00000000 +#define DDRSS1_PHY_709_DATA 0x00000000 +#define DDRSS1_PHY_710_DATA 0x00000000 +#define DDRSS1_PHY_711_DATA 0x00000000 +#define DDRSS1_PHY_712_DATA 0x00000000 +#define DDRSS1_PHY_713_DATA 0x00000000 +#define DDRSS1_PHY_714_DATA 0x00000000 +#define DDRSS1_PHY_715_DATA 0x00000000 +#define DDRSS1_PHY_716_DATA 0x00000000 +#define DDRSS1_PHY_717_DATA 0x00000000 +#define DDRSS1_PHY_718_DATA 0x00000000 +#define DDRSS1_PHY_719_DATA 0x00000000 +#define DDRSS1_PHY_720_DATA 0x00000000 +#define DDRSS1_PHY_721_DATA 0x00000000 +#define DDRSS1_PHY_722_DATA 0x00000000 +#define DDRSS1_PHY_723_DATA 0x00000000 +#define DDRSS1_PHY_724_DATA 0x00000000 +#define DDRSS1_PHY_725_DATA 0x00000000 +#define DDRSS1_PHY_726_DATA 0x00000000 +#define DDRSS1_PHY_727_DATA 0x00000000 +#define DDRSS1_PHY_728_DATA 0x00000000 +#define DDRSS1_PHY_729_DATA 0x00000000 +#define DDRSS1_PHY_730_DATA 0x00000000 +#define DDRSS1_PHY_731_DATA 0x00000000 +#define DDRSS1_PHY_732_DATA 0x00000000 +#define DDRSS1_PHY_733_DATA 0x00000000 +#define DDRSS1_PHY_734_DATA 0x00000000 +#define DDRSS1_PHY_735_DATA 0x00000000 +#define DDRSS1_PHY_736_DATA 0x00000000 +#define DDRSS1_PHY_737_DATA 0x00000000 +#define DDRSS1_PHY_738_DATA 0x00000000 +#define DDRSS1_PHY_739_DATA 0x00000000 +#define DDRSS1_PHY_740_DATA 0x00000000 +#define DDRSS1_PHY_741_DATA 0x00000000 +#define DDRSS1_PHY_742_DATA 0x00000000 +#define DDRSS1_PHY_743_DATA 0x00000000 +#define DDRSS1_PHY_744_DATA 0x00000000 +#define DDRSS1_PHY_745_DATA 0x00000000 +#define DDRSS1_PHY_746_DATA 0x00000000 +#define DDRSS1_PHY_747_DATA 0x00000000 +#define DDRSS1_PHY_748_DATA 0x00000000 +#define DDRSS1_PHY_749_DATA 0x00000000 +#define DDRSS1_PHY_750_DATA 0x00000000 +#define DDRSS1_PHY_751_DATA 0x00000000 +#define DDRSS1_PHY_752_DATA 0x00000000 +#define DDRSS1_PHY_753_DATA 0x00000000 +#define DDRSS1_PHY_754_DATA 0x00000000 +#define DDRSS1_PHY_755_DATA 0x00000000 +#define DDRSS1_PHY_756_DATA 0x00000000 +#define DDRSS1_PHY_757_DATA 0x00000000 +#define DDRSS1_PHY_758_DATA 0x00000000 +#define DDRSS1_PHY_759_DATA 0x00000000 +#define DDRSS1_PHY_760_DATA 0x00000000 +#define DDRSS1_PHY_761_DATA 0x00000000 +#define DDRSS1_PHY_762_DATA 0x00000000 +#define DDRSS1_PHY_763_DATA 0x00000000 +#define DDRSS1_PHY_764_DATA 0x00000000 +#define DDRSS1_PHY_765_DATA 0x00000000 +#define DDRSS1_PHY_766_DATA 0x00000000 +#define DDRSS1_PHY_767_DATA 0x00000000 +#define DDRSS1_PHY_768_DATA 0x000004F0 +#define DDRSS1_PHY_769_DATA 0x00000000 +#define DDRSS1_PHY_770_DATA 0x00030200 +#define DDRSS1_PHY_771_DATA 0x00000000 +#define DDRSS1_PHY_772_DATA 0x00000000 +#define DDRSS1_PHY_773_DATA 0x01030000 +#define DDRSS1_PHY_774_DATA 0x00010000 +#define DDRSS1_PHY_775_DATA 0x01030004 +#define DDRSS1_PHY_776_DATA 0x01000000 +#define DDRSS1_PHY_777_DATA 0x00000000 +#define DDRSS1_PHY_778_DATA 0x00000000 +#define DDRSS1_PHY_779_DATA 0x01000001 +#define DDRSS1_PHY_780_DATA 0x00000200 +#define DDRSS1_PHY_781_DATA 0x000800C0 +#define DDRSS1_PHY_782_DATA 0x060100CC +#define DDRSS1_PHY_783_DATA 0x00030066 +#define DDRSS1_PHY_784_DATA 0x00000000 +#define DDRSS1_PHY_785_DATA 0x00000301 +#define DDRSS1_PHY_786_DATA 0x0000AAAA +#define DDRSS1_PHY_787_DATA 0x00005555 +#define DDRSS1_PHY_788_DATA 0x0000B5B5 +#define DDRSS1_PHY_789_DATA 0x00004A4A +#define DDRSS1_PHY_790_DATA 0x00005656 +#define DDRSS1_PHY_791_DATA 0x0000A9A9 +#define DDRSS1_PHY_792_DATA 0x0000A9A9 +#define DDRSS1_PHY_793_DATA 0x0000B5B5 +#define DDRSS1_PHY_794_DATA 0x00000000 +#define DDRSS1_PHY_795_DATA 0x00000000 +#define DDRSS1_PHY_796_DATA 0x2A000000 +#define DDRSS1_PHY_797_DATA 0x00000808 +#define DDRSS1_PHY_798_DATA 0x0F000000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 +#define DDRSS1_PHY_801_DATA 0x0C002006 +#define DDRSS1_PHY_802_DATA 0x00000000 +#define DDRSS1_PHY_803_DATA 0x00000000 +#define DDRSS1_PHY_804_DATA 0x55555555 +#define DDRSS1_PHY_805_DATA 0xAAAAAAAA +#define DDRSS1_PHY_806_DATA 0x55555555 +#define DDRSS1_PHY_807_DATA 0xAAAAAAAA +#define DDRSS1_PHY_808_DATA 0x00005555 +#define DDRSS1_PHY_809_DATA 0x01000100 +#define DDRSS1_PHY_810_DATA 0x00800180 +#define DDRSS1_PHY_811_DATA 0x00000000 +#define DDRSS1_PHY_812_DATA 0x00000000 +#define DDRSS1_PHY_813_DATA 0x00000000 +#define DDRSS1_PHY_814_DATA 0x00000000 +#define DDRSS1_PHY_815_DATA 0x00000000 +#define DDRSS1_PHY_816_DATA 0x00000000 +#define DDRSS1_PHY_817_DATA 0x00000000 +#define DDRSS1_PHY_818_DATA 0x00000000 +#define DDRSS1_PHY_819_DATA 0x00000000 +#define DDRSS1_PHY_820_DATA 0x00000000 +#define DDRSS1_PHY_821_DATA 0x00000000 +#define DDRSS1_PHY_822_DATA 0x00000000 +#define DDRSS1_PHY_823_DATA 0x00000000 +#define DDRSS1_PHY_824_DATA 0x00000000 +#define DDRSS1_PHY_825_DATA 0x00000000 +#define DDRSS1_PHY_826_DATA 0x00000000 +#define DDRSS1_PHY_827_DATA 0x00000000 +#define DDRSS1_PHY_828_DATA 0x00000000 +#define DDRSS1_PHY_829_DATA 0x00000000 +#define DDRSS1_PHY_830_DATA 0x00000000 +#define DDRSS1_PHY_831_DATA 0x00000000 +#define DDRSS1_PHY_832_DATA 0x00000000 +#define DDRSS1_PHY_833_DATA 0x00000000 +#define DDRSS1_PHY_834_DATA 0x00000104 +#define DDRSS1_PHY_835_DATA 0x00000120 +#define DDRSS1_PHY_836_DATA 0x00000000 +#define DDRSS1_PHY_837_DATA 0x00000000 +#define DDRSS1_PHY_838_DATA 0x00000000 +#define DDRSS1_PHY_839_DATA 0x00000000 +#define DDRSS1_PHY_840_DATA 0x00000000 +#define DDRSS1_PHY_841_DATA 0x00000000 +#define DDRSS1_PHY_842_DATA 0x00000000 +#define DDRSS1_PHY_843_DATA 0x00000001 +#define DDRSS1_PHY_844_DATA 0x07FF0000 +#define DDRSS1_PHY_845_DATA 0x0080081F +#define DDRSS1_PHY_846_DATA 0x00081020 +#define DDRSS1_PHY_847_DATA 0x04010000 +#define DDRSS1_PHY_848_DATA 0x00000000 +#define DDRSS1_PHY_849_DATA 0x00000000 +#define DDRSS1_PHY_850_DATA 0x00000000 +#define DDRSS1_PHY_851_DATA 0x00000100 +#define DDRSS1_PHY_852_DATA 0x01CC0C01 +#define DDRSS1_PHY_853_DATA 0x1003CC0C +#define DDRSS1_PHY_854_DATA 0x20000140 +#define DDRSS1_PHY_855_DATA 0x07FF0200 +#define DDRSS1_PHY_856_DATA 0x0000DD01 +#define DDRSS1_PHY_857_DATA 0x10100303 +#define DDRSS1_PHY_858_DATA 0x10101010 +#define DDRSS1_PHY_859_DATA 0x10101010 +#define DDRSS1_PHY_860_DATA 0x00021010 +#define DDRSS1_PHY_861_DATA 0x00100010 +#define DDRSS1_PHY_862_DATA 0x00100010 +#define DDRSS1_PHY_863_DATA 0x00100010 +#define DDRSS1_PHY_864_DATA 0x00100010 +#define DDRSS1_PHY_865_DATA 0x00050010 +#define DDRSS1_PHY_866_DATA 0x51517041 +#define DDRSS1_PHY_867_DATA 0x31C06001 +#define DDRSS1_PHY_868_DATA 0x07AB01AB +#define DDRSS1_PHY_869_DATA 0x00C0C001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 +#define DDRSS1_PHY_871_DATA 0x10001000 +#define DDRSS1_PHY_872_DATA 0x0C083E42 +#define DDRSS1_PHY_873_DATA 0x0F0C3701 +#define DDRSS1_PHY_874_DATA 0x01000140 +#define DDRSS1_PHY_875_DATA 0x0C000420 +#define DDRSS1_PHY_876_DATA 0x00000198 +#define DDRSS1_PHY_877_DATA 0x0A0000D0 +#define DDRSS1_PHY_878_DATA 0x00030200 +#define DDRSS1_PHY_879_DATA 0x02800000 +#define DDRSS1_PHY_880_DATA 0x80800000 +#define DDRSS1_PHY_881_DATA 0x000E2010 +#define DDRSS1_PHY_882_DATA 0x76543210 +#define DDRSS1_PHY_883_DATA 0x00000008 +#define DDRSS1_PHY_884_DATA 0x02800280 +#define DDRSS1_PHY_885_DATA 0x02800280 +#define DDRSS1_PHY_886_DATA 0x02800280 +#define DDRSS1_PHY_887_DATA 0x02800280 +#define DDRSS1_PHY_888_DATA 0x00000280 +#define DDRSS1_PHY_889_DATA 0x0000A000 +#define DDRSS1_PHY_890_DATA 0x00A000A0 +#define DDRSS1_PHY_891_DATA 0x00A000A0 +#define DDRSS1_PHY_892_DATA 0x00A000A0 +#define DDRSS1_PHY_893_DATA 0x00A000A0 +#define DDRSS1_PHY_894_DATA 0x00A000A0 +#define DDRSS1_PHY_895_DATA 0x00A000A0 +#define DDRSS1_PHY_896_DATA 0x00A000A0 +#define DDRSS1_PHY_897_DATA 0x00A000A0 +#define DDRSS1_PHY_898_DATA 0x01C200A0 +#define DDRSS1_PHY_899_DATA 0x01A00005 +#define DDRSS1_PHY_900_DATA 0x00000000 +#define DDRSS1_PHY_901_DATA 0x00000000 +#define DDRSS1_PHY_902_DATA 0x00080200 +#define DDRSS1_PHY_903_DATA 0x00000000 +#define DDRSS1_PHY_904_DATA 0x20202020 +#define DDRSS1_PHY_905_DATA 0x20202020 +#define DDRSS1_PHY_906_DATA 0xF0F02020 +#define DDRSS1_PHY_907_DATA 0x00000000 +#define DDRSS1_PHY_908_DATA 0x00000000 +#define DDRSS1_PHY_909_DATA 0x00000000 +#define DDRSS1_PHY_910_DATA 0x00000000 +#define DDRSS1_PHY_911_DATA 0x00000000 +#define DDRSS1_PHY_912_DATA 0x00000000 +#define DDRSS1_PHY_913_DATA 0x00000000 +#define DDRSS1_PHY_914_DATA 0x00000000 +#define DDRSS1_PHY_915_DATA 0x00000000 +#define DDRSS1_PHY_916_DATA 0x00000000 +#define DDRSS1_PHY_917_DATA 0x00000000 +#define DDRSS1_PHY_918_DATA 0x00000000 +#define DDRSS1_PHY_919_DATA 0x00000000 +#define DDRSS1_PHY_920_DATA 0x00000000 +#define DDRSS1_PHY_921_DATA 0x00000000 +#define DDRSS1_PHY_922_DATA 0x00000000 +#define DDRSS1_PHY_923_DATA 0x00000000 +#define DDRSS1_PHY_924_DATA 0x00000000 +#define DDRSS1_PHY_925_DATA 0x00000000 +#define DDRSS1_PHY_926_DATA 0x00000000 +#define DDRSS1_PHY_927_DATA 0x00000000 +#define DDRSS1_PHY_928_DATA 0x00000000 +#define DDRSS1_PHY_929_DATA 0x00000000 +#define DDRSS1_PHY_930_DATA 0x00000000 +#define DDRSS1_PHY_931_DATA 0x00000000 +#define DDRSS1_PHY_932_DATA 0x00000000 +#define DDRSS1_PHY_933_DATA 0x00000000 +#define DDRSS1_PHY_934_DATA 0x00000000 +#define DDRSS1_PHY_935_DATA 0x00000000 +#define DDRSS1_PHY_936_DATA 0x00000000 +#define DDRSS1_PHY_937_DATA 0x00000000 +#define DDRSS1_PHY_938_DATA 0x00000000 +#define DDRSS1_PHY_939_DATA 0x00000000 +#define DDRSS1_PHY_940_DATA 0x00000000 +#define DDRSS1_PHY_941_DATA 0x00000000 +#define DDRSS1_PHY_942_DATA 0x00000000 +#define DDRSS1_PHY_943_DATA 0x00000000 +#define DDRSS1_PHY_944_DATA 0x00000000 +#define DDRSS1_PHY_945_DATA 0x00000000 +#define DDRSS1_PHY_946_DATA 0x00000000 +#define DDRSS1_PHY_947_DATA 0x00000000 +#define DDRSS1_PHY_948_DATA 0x00000000 +#define DDRSS1_PHY_949_DATA 0x00000000 +#define DDRSS1_PHY_950_DATA 0x00000000 +#define DDRSS1_PHY_951_DATA 0x00000000 +#define DDRSS1_PHY_952_DATA 0x00000000 +#define DDRSS1_PHY_953_DATA 0x00000000 +#define DDRSS1_PHY_954_DATA 0x00000000 +#define DDRSS1_PHY_955_DATA 0x00000000 +#define DDRSS1_PHY_956_DATA 0x00000000 +#define DDRSS1_PHY_957_DATA 0x00000000 +#define DDRSS1_PHY_958_DATA 0x00000000 +#define DDRSS1_PHY_959_DATA 0x00000000 +#define DDRSS1_PHY_960_DATA 0x00000000 +#define DDRSS1_PHY_961_DATA 0x00000000 +#define DDRSS1_PHY_962_DATA 0x00000000 +#define DDRSS1_PHY_963_DATA 0x00000000 +#define DDRSS1_PHY_964_DATA 0x00000000 +#define DDRSS1_PHY_965_DATA 0x00000000 +#define DDRSS1_PHY_966_DATA 0x00000000 +#define DDRSS1_PHY_967_DATA 0x00000000 +#define DDRSS1_PHY_968_DATA 0x00000000 +#define DDRSS1_PHY_969_DATA 0x00000000 +#define DDRSS1_PHY_970_DATA 0x00000000 +#define DDRSS1_PHY_971_DATA 0x00000000 +#define DDRSS1_PHY_972_DATA 0x00000000 +#define DDRSS1_PHY_973_DATA 0x00000000 +#define DDRSS1_PHY_974_DATA 0x00000000 +#define DDRSS1_PHY_975_DATA 0x00000000 +#define DDRSS1_PHY_976_DATA 0x00000000 +#define DDRSS1_PHY_977_DATA 0x00000000 +#define DDRSS1_PHY_978_DATA 0x00000000 +#define DDRSS1_PHY_979_DATA 0x00000000 +#define DDRSS1_PHY_980_DATA 0x00000000 +#define DDRSS1_PHY_981_DATA 0x00000000 +#define DDRSS1_PHY_982_DATA 0x00000000 +#define DDRSS1_PHY_983_DATA 0x00000000 +#define DDRSS1_PHY_984_DATA 0x00000000 +#define DDRSS1_PHY_985_DATA 0x00000000 +#define DDRSS1_PHY_986_DATA 0x00000000 +#define DDRSS1_PHY_987_DATA 0x00000000 +#define DDRSS1_PHY_988_DATA 0x00000000 +#define DDRSS1_PHY_989_DATA 0x00000000 +#define DDRSS1_PHY_990_DATA 0x00000000 +#define DDRSS1_PHY_991_DATA 0x00000000 +#define DDRSS1_PHY_992_DATA 0x00000000 +#define DDRSS1_PHY_993_DATA 0x00000000 +#define DDRSS1_PHY_994_DATA 0x00000000 +#define DDRSS1_PHY_995_DATA 0x00000000 +#define DDRSS1_PHY_996_DATA 0x00000000 +#define DDRSS1_PHY_997_DATA 0x00000000 +#define DDRSS1_PHY_998_DATA 0x00000000 +#define DDRSS1_PHY_999_DATA 0x00000000 +#define DDRSS1_PHY_1000_DATA 0x00000000 +#define DDRSS1_PHY_1001_DATA 0x00000000 +#define DDRSS1_PHY_1002_DATA 0x00000000 +#define DDRSS1_PHY_1003_DATA 0x00000000 +#define DDRSS1_PHY_1004_DATA 0x00000000 +#define DDRSS1_PHY_1005_DATA 0x00000000 +#define DDRSS1_PHY_1006_DATA 0x00000000 +#define DDRSS1_PHY_1007_DATA 0x00000000 +#define DDRSS1_PHY_1008_DATA 0x00000000 +#define DDRSS1_PHY_1009_DATA 0x00000000 +#define DDRSS1_PHY_1010_DATA 0x00000000 +#define DDRSS1_PHY_1011_DATA 0x00000000 +#define DDRSS1_PHY_1012_DATA 0x00000000 +#define DDRSS1_PHY_1013_DATA 0x00000000 +#define DDRSS1_PHY_1014_DATA 0x00000000 +#define DDRSS1_PHY_1015_DATA 0x00000000 +#define DDRSS1_PHY_1016_DATA 0x00000000 +#define DDRSS1_PHY_1017_DATA 0x00000000 +#define DDRSS1_PHY_1018_DATA 0x00000000 +#define DDRSS1_PHY_1019_DATA 0x00000000 +#define DDRSS1_PHY_1020_DATA 0x00000000 +#define DDRSS1_PHY_1021_DATA 0x00000000 +#define DDRSS1_PHY_1022_DATA 0x00000000 +#define DDRSS1_PHY_1023_DATA 0x00000000 +#define DDRSS1_PHY_1024_DATA 0x00000000 +#define DDRSS1_PHY_1025_DATA 0x00000000 +#define DDRSS1_PHY_1026_DATA 0x00000000 +#define DDRSS1_PHY_1027_DATA 0x00000000 +#define DDRSS1_PHY_1028_DATA 0x00000000 +#define DDRSS1_PHY_1029_DATA 0x00000100 +#define DDRSS1_PHY_1030_DATA 0x00000200 +#define DDRSS1_PHY_1031_DATA 0x00000000 +#define DDRSS1_PHY_1032_DATA 0x00000000 +#define DDRSS1_PHY_1033_DATA 0x00000000 +#define DDRSS1_PHY_1034_DATA 0x00000000 +#define DDRSS1_PHY_1035_DATA 0x00400000 +#define DDRSS1_PHY_1036_DATA 0x00000080 +#define DDRSS1_PHY_1037_DATA 0x00DCBA98 +#define DDRSS1_PHY_1038_DATA 0x03000000 +#define DDRSS1_PHY_1039_DATA 0x00200000 +#define DDRSS1_PHY_1040_DATA 0x00000000 +#define DDRSS1_PHY_1041_DATA 0x00000000 +#define DDRSS1_PHY_1042_DATA 0x00000000 +#define DDRSS1_PHY_1043_DATA 0x00000000 +#define DDRSS1_PHY_1044_DATA 0x00000000 +#define DDRSS1_PHY_1045_DATA 0x0000002A +#define DDRSS1_PHY_1046_DATA 0x00000015 +#define DDRSS1_PHY_1047_DATA 0x00000015 +#define DDRSS1_PHY_1048_DATA 0x0000002A +#define DDRSS1_PHY_1049_DATA 0x00000033 +#define DDRSS1_PHY_1050_DATA 0x0000000C +#define DDRSS1_PHY_1051_DATA 0x0000000C +#define DDRSS1_PHY_1052_DATA 0x00000033 +#define DDRSS1_PHY_1053_DATA 0x00543210 +#define DDRSS1_PHY_1054_DATA 0x003F0000 +#define DDRSS1_PHY_1055_DATA 0x000F3F3F +#define DDRSS1_PHY_1056_DATA 0x20202003 +#define DDRSS1_PHY_1057_DATA 0x00202020 +#define DDRSS1_PHY_1058_DATA 0x20008008 +#define DDRSS1_PHY_1059_DATA 0x00000810 +#define DDRSS1_PHY_1060_DATA 0x00000F00 +#define DDRSS1_PHY_1061_DATA 0x00000000 +#define DDRSS1_PHY_1062_DATA 0x00000000 +#define DDRSS1_PHY_1063_DATA 0x00000000 +#define DDRSS1_PHY_1064_DATA 0x000305CC +#define DDRSS1_PHY_1065_DATA 0x00030000 +#define DDRSS1_PHY_1066_DATA 0x00000300 +#define DDRSS1_PHY_1067_DATA 0x00000300 +#define DDRSS1_PHY_1068_DATA 0x00000300 +#define DDRSS1_PHY_1069_DATA 0x00000300 +#define DDRSS1_PHY_1070_DATA 0x00000300 +#define DDRSS1_PHY_1071_DATA 0x42080010 +#define DDRSS1_PHY_1072_DATA 0x0000803E +#define DDRSS1_PHY_1073_DATA 0x00000001 +#define DDRSS1_PHY_1074_DATA 0x01000102 +#define DDRSS1_PHY_1075_DATA 0x00008000 +#define DDRSS1_PHY_1076_DATA 0x00000000 +#define DDRSS1_PHY_1077_DATA 0x00000000 +#define DDRSS1_PHY_1078_DATA 0x00000000 +#define DDRSS1_PHY_1079_DATA 0x00000000 +#define DDRSS1_PHY_1080_DATA 0x00000000 +#define DDRSS1_PHY_1081_DATA 0x00000000 +#define DDRSS1_PHY_1082_DATA 0x00000000 +#define DDRSS1_PHY_1083_DATA 0x00000000 +#define DDRSS1_PHY_1084_DATA 0x00000000 +#define DDRSS1_PHY_1085_DATA 0x00000000 +#define DDRSS1_PHY_1086_DATA 0x00000000 +#define DDRSS1_PHY_1087_DATA 0x00000000 +#define DDRSS1_PHY_1088_DATA 0x00000000 +#define DDRSS1_PHY_1089_DATA 0x00000000 +#define DDRSS1_PHY_1090_DATA 0x00000000 +#define DDRSS1_PHY_1091_DATA 0x00000000 +#define DDRSS1_PHY_1092_DATA 0x00000000 +#define DDRSS1_PHY_1093_DATA 0x00000000 +#define DDRSS1_PHY_1094_DATA 0x00000000 +#define DDRSS1_PHY_1095_DATA 0x00000000 +#define DDRSS1_PHY_1096_DATA 0x00000000 +#define DDRSS1_PHY_1097_DATA 0x00000000 +#define DDRSS1_PHY_1098_DATA 0x00000000 +#define DDRSS1_PHY_1099_DATA 0x00000000 +#define DDRSS1_PHY_1100_DATA 0x00000000 +#define DDRSS1_PHY_1101_DATA 0x00000000 +#define DDRSS1_PHY_1102_DATA 0x00000000 +#define DDRSS1_PHY_1103_DATA 0x00000000 +#define DDRSS1_PHY_1104_DATA 0x00000000 +#define DDRSS1_PHY_1105_DATA 0x00000000 +#define DDRSS1_PHY_1106_DATA 0x00000000 +#define DDRSS1_PHY_1107_DATA 0x00000000 +#define DDRSS1_PHY_1108_DATA 0x00000000 +#define DDRSS1_PHY_1109_DATA 0x00000000 +#define DDRSS1_PHY_1110_DATA 0x00000000 +#define DDRSS1_PHY_1111_DATA 0x00000000 +#define DDRSS1_PHY_1112_DATA 0x00000000 +#define DDRSS1_PHY_1113_DATA 0x00000000 +#define DDRSS1_PHY_1114_DATA 0x00000000 +#define DDRSS1_PHY_1115_DATA 0x00000000 +#define DDRSS1_PHY_1116_DATA 0x00000000 +#define DDRSS1_PHY_1117_DATA 0x00000000 +#define DDRSS1_PHY_1118_DATA 0x00000000 +#define DDRSS1_PHY_1119_DATA 0x00000000 +#define DDRSS1_PHY_1120_DATA 0x00000000 +#define DDRSS1_PHY_1121_DATA 0x00000000 +#define DDRSS1_PHY_1122_DATA 0x00000000 +#define DDRSS1_PHY_1123_DATA 0x00000000 +#define DDRSS1_PHY_1124_DATA 0x00000000 +#define DDRSS1_PHY_1125_DATA 0x00000000 +#define DDRSS1_PHY_1126_DATA 0x00000000 +#define DDRSS1_PHY_1127_DATA 0x00000000 +#define DDRSS1_PHY_1128_DATA 0x00000000 +#define DDRSS1_PHY_1129_DATA 0x00000000 +#define DDRSS1_PHY_1130_DATA 0x00000000 +#define DDRSS1_PHY_1131_DATA 0x00000000 +#define DDRSS1_PHY_1132_DATA 0x00000000 +#define DDRSS1_PHY_1133_DATA 0x00000000 +#define DDRSS1_PHY_1134_DATA 0x00000000 +#define DDRSS1_PHY_1135_DATA 0x00000000 +#define DDRSS1_PHY_1136_DATA 0x00000000 +#define DDRSS1_PHY_1137_DATA 0x00000000 +#define DDRSS1_PHY_1138_DATA 0x00000000 +#define DDRSS1_PHY_1139_DATA 0x00000000 +#define DDRSS1_PHY_1140_DATA 0x00000000 +#define DDRSS1_PHY_1141_DATA 0x00000000 +#define DDRSS1_PHY_1142_DATA 0x00000000 +#define DDRSS1_PHY_1143_DATA 0x00000000 +#define DDRSS1_PHY_1144_DATA 0x00000000 +#define DDRSS1_PHY_1145_DATA 0x00000000 +#define DDRSS1_PHY_1146_DATA 0x00000000 +#define DDRSS1_PHY_1147_DATA 0x00000000 +#define DDRSS1_PHY_1148_DATA 0x00000000 +#define DDRSS1_PHY_1149_DATA 0x00000000 +#define DDRSS1_PHY_1150_DATA 0x00000000 +#define DDRSS1_PHY_1151_DATA 0x00000000 +#define DDRSS1_PHY_1152_DATA 0x00000000 +#define DDRSS1_PHY_1153_DATA 0x00000000 +#define DDRSS1_PHY_1154_DATA 0x00000000 +#define DDRSS1_PHY_1155_DATA 0x00000000 +#define DDRSS1_PHY_1156_DATA 0x00000000 +#define DDRSS1_PHY_1157_DATA 0x00000000 +#define DDRSS1_PHY_1158_DATA 0x00000000 +#define DDRSS1_PHY_1159_DATA 0x00000000 +#define DDRSS1_PHY_1160_DATA 0x00000000 +#define DDRSS1_PHY_1161_DATA 0x00000000 +#define DDRSS1_PHY_1162_DATA 0x00000000 +#define DDRSS1_PHY_1163_DATA 0x00000000 +#define DDRSS1_PHY_1164_DATA 0x00000000 +#define DDRSS1_PHY_1165_DATA 0x00000000 +#define DDRSS1_PHY_1166_DATA 0x00000000 +#define DDRSS1_PHY_1167_DATA 0x00000000 +#define DDRSS1_PHY_1168_DATA 0x00000000 +#define DDRSS1_PHY_1169_DATA 0x00000000 +#define DDRSS1_PHY_1170_DATA 0x00000000 +#define DDRSS1_PHY_1171_DATA 0x00000000 +#define DDRSS1_PHY_1172_DATA 0x00000000 +#define DDRSS1_PHY_1173_DATA 0x00000000 +#define DDRSS1_PHY_1174_DATA 0x00000000 +#define DDRSS1_PHY_1175_DATA 0x00000000 +#define DDRSS1_PHY_1176_DATA 0x00000000 +#define DDRSS1_PHY_1177_DATA 0x00000000 +#define DDRSS1_PHY_1178_DATA 0x00000000 +#define DDRSS1_PHY_1179_DATA 0x00000000 +#define DDRSS1_PHY_1180_DATA 0x00000000 +#define DDRSS1_PHY_1181_DATA 0x00000000 +#define DDRSS1_PHY_1182_DATA 0x00000000 +#define DDRSS1_PHY_1183_DATA 0x00000000 +#define DDRSS1_PHY_1184_DATA 0x00000000 +#define DDRSS1_PHY_1185_DATA 0x00000000 +#define DDRSS1_PHY_1186_DATA 0x00000000 +#define DDRSS1_PHY_1187_DATA 0x00000000 +#define DDRSS1_PHY_1188_DATA 0x00000000 +#define DDRSS1_PHY_1189_DATA 0x00000000 +#define DDRSS1_PHY_1190_DATA 0x00000000 +#define DDRSS1_PHY_1191_DATA 0x00000000 +#define DDRSS1_PHY_1192_DATA 0x00000000 +#define DDRSS1_PHY_1193_DATA 0x00000000 +#define DDRSS1_PHY_1194_DATA 0x00000000 +#define DDRSS1_PHY_1195_DATA 0x00000000 +#define DDRSS1_PHY_1196_DATA 0x00000000 +#define DDRSS1_PHY_1197_DATA 0x00000000 +#define DDRSS1_PHY_1198_DATA 0x00000000 +#define DDRSS1_PHY_1199_DATA 0x00000000 +#define DDRSS1_PHY_1200_DATA 0x00000000 +#define DDRSS1_PHY_1201_DATA 0x00000000 +#define DDRSS1_PHY_1202_DATA 0x00000000 +#define DDRSS1_PHY_1203_DATA 0x00000000 +#define DDRSS1_PHY_1204_DATA 0x00000000 +#define DDRSS1_PHY_1205_DATA 0x00000000 +#define DDRSS1_PHY_1206_DATA 0x00000000 +#define DDRSS1_PHY_1207_DATA 0x00000000 +#define DDRSS1_PHY_1208_DATA 0x00000000 +#define DDRSS1_PHY_1209_DATA 0x00000000 +#define DDRSS1_PHY_1210_DATA 0x00000000 +#define DDRSS1_PHY_1211_DATA 0x00000000 +#define DDRSS1_PHY_1212_DATA 0x00000000 +#define DDRSS1_PHY_1213_DATA 0x00000000 +#define DDRSS1_PHY_1214_DATA 0x00000000 +#define DDRSS1_PHY_1215_DATA 0x00000000 +#define DDRSS1_PHY_1216_DATA 0x00000000 +#define DDRSS1_PHY_1217_DATA 0x00000000 +#define DDRSS1_PHY_1218_DATA 0x00000000 +#define DDRSS1_PHY_1219_DATA 0x00000000 +#define DDRSS1_PHY_1220_DATA 0x00000000 +#define DDRSS1_PHY_1221_DATA 0x00000000 +#define DDRSS1_PHY_1222_DATA 0x00000000 +#define DDRSS1_PHY_1223_DATA 0x00000000 +#define DDRSS1_PHY_1224_DATA 0x00000000 +#define DDRSS1_PHY_1225_DATA 0x00000000 +#define DDRSS1_PHY_1226_DATA 0x00000000 +#define DDRSS1_PHY_1227_DATA 0x00000000 +#define DDRSS1_PHY_1228_DATA 0x00000000 +#define DDRSS1_PHY_1229_DATA 0x00000000 +#define DDRSS1_PHY_1230_DATA 0x00000000 +#define DDRSS1_PHY_1231_DATA 0x00000000 +#define DDRSS1_PHY_1232_DATA 0x00000000 +#define DDRSS1_PHY_1233_DATA 0x00000000 +#define DDRSS1_PHY_1234_DATA 0x00000000 +#define DDRSS1_PHY_1235_DATA 0x00000000 +#define DDRSS1_PHY_1236_DATA 0x00000000 +#define DDRSS1_PHY_1237_DATA 0x00000000 +#define DDRSS1_PHY_1238_DATA 0x00000000 +#define DDRSS1_PHY_1239_DATA 0x00000000 +#define DDRSS1_PHY_1240_DATA 0x00000000 +#define DDRSS1_PHY_1241_DATA 0x00000000 +#define DDRSS1_PHY_1242_DATA 0x00000000 +#define DDRSS1_PHY_1243_DATA 0x00000000 +#define DDRSS1_PHY_1244_DATA 0x00000000 +#define DDRSS1_PHY_1245_DATA 0x00000000 +#define DDRSS1_PHY_1246_DATA 0x00000000 +#define DDRSS1_PHY_1247_DATA 0x00000000 +#define DDRSS1_PHY_1248_DATA 0x00000000 +#define DDRSS1_PHY_1249_DATA 0x00000000 +#define DDRSS1_PHY_1250_DATA 0x00000000 +#define DDRSS1_PHY_1251_DATA 0x00000000 +#define DDRSS1_PHY_1252_DATA 0x00000000 +#define DDRSS1_PHY_1253_DATA 0x00000000 +#define DDRSS1_PHY_1254_DATA 0x00000000 +#define DDRSS1_PHY_1255_DATA 0x00000000 +#define DDRSS1_PHY_1256_DATA 0x00000000 +#define DDRSS1_PHY_1257_DATA 0x00000000 +#define DDRSS1_PHY_1258_DATA 0x00000000 +#define DDRSS1_PHY_1259_DATA 0x00000000 +#define DDRSS1_PHY_1260_DATA 0x00000000 +#define DDRSS1_PHY_1261_DATA 0x00000000 +#define DDRSS1_PHY_1262_DATA 0x00000000 +#define DDRSS1_PHY_1263_DATA 0x00000000 +#define DDRSS1_PHY_1264_DATA 0x00000000 +#define DDRSS1_PHY_1265_DATA 0x00000000 +#define DDRSS1_PHY_1266_DATA 0x00000000 +#define DDRSS1_PHY_1267_DATA 0x00000000 +#define DDRSS1_PHY_1268_DATA 0x00000000 +#define DDRSS1_PHY_1269_DATA 0x00000000 +#define DDRSS1_PHY_1270_DATA 0x00000000 +#define DDRSS1_PHY_1271_DATA 0x00000000 +#define DDRSS1_PHY_1272_DATA 0x00000000 +#define DDRSS1_PHY_1273_DATA 0x00000000 +#define DDRSS1_PHY_1274_DATA 0x00000000 +#define DDRSS1_PHY_1275_DATA 0x00000000 +#define DDRSS1_PHY_1276_DATA 0x00000000 +#define DDRSS1_PHY_1277_DATA 0x00000000 +#define DDRSS1_PHY_1278_DATA 0x00000000 +#define DDRSS1_PHY_1279_DATA 0x00000000 +#define DDRSS1_PHY_1280_DATA 0x00000000 +#define DDRSS1_PHY_1281_DATA 0x00010100 +#define DDRSS1_PHY_1282_DATA 0x00000000 +#define DDRSS1_PHY_1283_DATA 0x00000000 +#define DDRSS1_PHY_1284_DATA 0x00050000 +#define DDRSS1_PHY_1285_DATA 0x04000000 +#define DDRSS1_PHY_1286_DATA 0x00000055 +#define DDRSS1_PHY_1287_DATA 0x00000000 +#define DDRSS1_PHY_1288_DATA 0x00000000 +#define DDRSS1_PHY_1289_DATA 0x00000000 +#define DDRSS1_PHY_1290_DATA 0x00000000 +#define DDRSS1_PHY_1291_DATA 0x00002001 +#define DDRSS1_PHY_1292_DATA 0x0000400F +#define DDRSS1_PHY_1293_DATA 0x50020028 +#define DDRSS1_PHY_1294_DATA 0x01010000 +#define DDRSS1_PHY_1295_DATA 0x80080001 +#define DDRSS1_PHY_1296_DATA 0x10200000 +#define DDRSS1_PHY_1297_DATA 0x00000008 +#define DDRSS1_PHY_1298_DATA 0x00000000 +#define DDRSS1_PHY_1299_DATA 0x01090E00 +#define DDRSS1_PHY_1300_DATA 0x00040101 +#define DDRSS1_PHY_1301_DATA 0x0000010F +#define DDRSS1_PHY_1302_DATA 0x00000000 +#define DDRSS1_PHY_1303_DATA 0x00000064 +#define DDRSS1_PHY_1304_DATA 0x00000000 +#define DDRSS1_PHY_1305_DATA 0x01010000 +#define DDRSS1_PHY_1306_DATA 0x01080402 +#define DDRSS1_PHY_1307_DATA 0x01200F02 +#define DDRSS1_PHY_1308_DATA 0x00194280 +#define DDRSS1_PHY_1309_DATA 0x00000004 +#define DDRSS1_PHY_1310_DATA 0x00042000 +#define DDRSS1_PHY_1311_DATA 0x00000000 +#define DDRSS1_PHY_1312_DATA 0x00000000 +#define DDRSS1_PHY_1313_DATA 0x00000000 +#define DDRSS1_PHY_1314_DATA 0x00000000 +#define DDRSS1_PHY_1315_DATA 0x00000000 +#define DDRSS1_PHY_1316_DATA 0x00000000 +#define DDRSS1_PHY_1317_DATA 0x01000000 +#define DDRSS1_PHY_1318_DATA 0x00000705 +#define DDRSS1_PHY_1319_DATA 0x00000054 +#define DDRSS1_PHY_1320_DATA 0x00030820 +#define DDRSS1_PHY_1321_DATA 0x00010820 +#define DDRSS1_PHY_1322_DATA 0x00010820 +#define DDRSS1_PHY_1323_DATA 0x00010820 +#define DDRSS1_PHY_1324_DATA 0x00010820 +#define DDRSS1_PHY_1325_DATA 0x00010820 +#define DDRSS1_PHY_1326_DATA 0x00010820 +#define DDRSS1_PHY_1327_DATA 0x00010820 +#define DDRSS1_PHY_1328_DATA 0x00010820 +#define DDRSS1_PHY_1329_DATA 0x00000000 +#define DDRSS1_PHY_1330_DATA 0x00000074 +#define DDRSS1_PHY_1331_DATA 0x00000400 +#define DDRSS1_PHY_1332_DATA 0x00000108 +#define DDRSS1_PHY_1333_DATA 0x00000000 +#define DDRSS1_PHY_1334_DATA 0x00000000 +#define DDRSS1_PHY_1335_DATA 0x00000000 +#define DDRSS1_PHY_1336_DATA 0x00000000 +#define DDRSS1_PHY_1337_DATA 0x00000000 +#define DDRSS1_PHY_1338_DATA 0x03000000 +#define DDRSS1_PHY_1339_DATA 0x00000000 +#define DDRSS1_PHY_1340_DATA 0x00000000 +#define DDRSS1_PHY_1341_DATA 0x00000000 +#define DDRSS1_PHY_1342_DATA 0x04102006 +#define DDRSS1_PHY_1343_DATA 0x00041020 +#define DDRSS1_PHY_1344_DATA 0x01C98C98 +#define DDRSS1_PHY_1345_DATA 0x3F400000 +#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS1_PHY_1347_DATA 0x0000001F +#define DDRSS1_PHY_1348_DATA 0x00000000 +#define DDRSS1_PHY_1349_DATA 0x00000000 +#define DDRSS1_PHY_1350_DATA 0x00000000 +#define DDRSS1_PHY_1351_DATA 0x00010000 +#define DDRSS1_PHY_1352_DATA 0x00000000 +#define DDRSS1_PHY_1353_DATA 0x00000000 +#define DDRSS1_PHY_1354_DATA 0x00000000 +#define DDRSS1_PHY_1355_DATA 0x00000000 +#define DDRSS1_PHY_1356_DATA 0x76543210 +#define DDRSS1_PHY_1357_DATA 0x00010198 +#define DDRSS1_PHY_1358_DATA 0x00000000 +#define DDRSS1_PHY_1359_DATA 0x00000000 +#define DDRSS1_PHY_1360_DATA 0x00000000 +#define DDRSS1_PHY_1361_DATA 0x00040700 +#define DDRSS1_PHY_1362_DATA 0x00000000 +#define DDRSS1_PHY_1363_DATA 0x00000000 +#define DDRSS1_PHY_1364_DATA 0x00000000 +#define DDRSS1_PHY_1365_DATA 0x00000000 +#define DDRSS1_PHY_1366_DATA 0x00000000 +#define DDRSS1_PHY_1367_DATA 0x00000002 +#define DDRSS1_PHY_1368_DATA 0x00000000 +#define DDRSS1_PHY_1369_DATA 0x00000000 +#define DDRSS1_PHY_1370_DATA 0x00000000 +#define DDRSS1_PHY_1371_DATA 0x00000000 +#define DDRSS1_PHY_1372_DATA 0x00000000 +#define DDRSS1_PHY_1373_DATA 0x00000000 +#define DDRSS1_PHY_1374_DATA 0x00080000 +#define DDRSS1_PHY_1375_DATA 0x000007FF +#define DDRSS1_PHY_1376_DATA 0x00000000 +#define DDRSS1_PHY_1377_DATA 0x00000000 +#define DDRSS1_PHY_1378_DATA 0x00000000 +#define DDRSS1_PHY_1379_DATA 0x00000000 +#define DDRSS1_PHY_1380_DATA 0x00000000 +#define DDRSS1_PHY_1381_DATA 0x00000000 +#define DDRSS1_PHY_1382_DATA 0x000FFFFF +#define DDRSS1_PHY_1383_DATA 0x000FFFFF +#define DDRSS1_PHY_1384_DATA 0x0000FFFF +#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS1_PHY_1386_DATA 0x030FFFFF +#define DDRSS1_PHY_1387_DATA 0x01FFFFFF +#define DDRSS1_PHY_1388_DATA 0x0000FFFF +#define DDRSS1_PHY_1389_DATA 0x00000000 +#define DDRSS1_PHY_1390_DATA 0x00000000 +#define DDRSS1_PHY_1391_DATA 0x00000000 +#define DDRSS1_PHY_1392_DATA 0x00000000 +#define DDRSS1_PHY_1393_DATA 0x0001F7C0 +#define DDRSS1_PHY_1394_DATA 0x00000003 +#define DDRSS1_PHY_1395_DATA 0x00000000 +#define DDRSS1_PHY_1396_DATA 0x00001142 +#define DDRSS1_PHY_1397_DATA 0x040207AB +#define DDRSS1_PHY_1398_DATA 0x01000080 +#define DDRSS1_PHY_1399_DATA 0x03900390 +#define DDRSS1_PHY_1400_DATA 0x03900390 +#define DDRSS1_PHY_1401_DATA 0x00000390 +#define DDRSS1_PHY_1402_DATA 0x00000390 +#define DDRSS1_PHY_1403_DATA 0x00000390 +#define DDRSS1_PHY_1404_DATA 0x00000390 +#define DDRSS1_PHY_1405_DATA 0x00000005 +#define DDRSS1_PHY_1406_DATA 0x01813FCC +#define DDRSS1_PHY_1407_DATA 0x000000CC +#define DDRSS1_PHY_1408_DATA 0x0C000DFF +#define DDRSS1_PHY_1409_DATA 0x30000DFF +#define DDRSS1_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1411_DATA 0x000100F0 +#define DDRSS1_PHY_1412_DATA 0x780DFFCC +#define DDRSS1_PHY_1413_DATA 0x00007E31 +#define DDRSS1_PHY_1414_DATA 0x000CBF11 +#define DDRSS1_PHY_1415_DATA 0x01990010 +#define DDRSS1_PHY_1416_DATA 0x000CBF11 +#define DDRSS1_PHY_1417_DATA 0x01990010 +#define DDRSS1_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1419_DATA 0x00EF00F0 +#define DDRSS1_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1421_DATA 0x01FF00F0 +#define DDRSS1_PHY_1422_DATA 0x20040006 + + diff --git a/arch/arm/dts/k3-am68-sk-r5-base-board.dts b/arch/arm/dts/k3-am68-sk-r5-base-board.dts index b61d22b3b4b..c43e7a1c46e 100644 --- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts +++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-am68-sk-base-board.dts" -#include "k3-j721s2-ddr-evm-lp4-4266.dtsi" +#include "k3-am68-ddr-sk-lp4-4266.dtsi" #include "k3-j721s2-ddr.dtsi" #include "k3-am68-sk-base-board-u-boot.dtsi" #include "k3-j721s2-r5.dtsi" diff --git a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi index 5b8b8539da3..c3a66ac8dae 100644 --- a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi +++ b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2025 Toradex - https://www.toradex.com/ */ -#define SPL_BOARD_DTB "spl/dts/k3-am69-aquila-dev.dtb" +#define SPL_BOARD_DTB "spl/dts/ti/k3-am69-aquila-dev.dtb" #define BOARD_DESCRIPTION "k3-am69-aquila" #define UBOOT_BOARD_DESCRIPTION "U-Boot for AM69 Aquila board" @@ -12,6 +12,11 @@ #if defined(CONFIG_CPU_V7R) &binman { + tiboot3_am69_gp { + insert-template = <&tiboot3_j784s4_gp>; + filename = "tiboot3-am69-gp-aquila.bin"; + }; + tiboot3-am69-hs { insert-template = <&tiboot3_j784s4_hs>; filename = "tiboot3-am69-hs-aquila.bin"; @@ -28,6 +33,10 @@ filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin"; }; +&ti_fs_gp { + filename = "ti-sysfw/ti-fs-firmware-j784s4-gp.bin"; +}; + &sysfw_inner_cert { filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin"; }; @@ -78,6 +87,72 @@ u-boot-unsigned { insert-template = <&u_boot_unsigned>; }; + + firmware-aquila-am69-gp.bin { + filename = "firmware-aquila-am69-gp.bin"; + + blob-ext@1 { + filename = "tiboot3-am69-gp-aquila.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin_unsigned"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img_unsigned"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-aquila-am69-hs.bin { + filename = "firmware-aquila-am69-hs.bin"; + + blob-ext@1 { + filename = "tiboot3-am69-hs-aquila.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-aquila-am69-hs-fs.bin { + filename = "firmware-aquila-am69-hs-fs.bin"; + + blob-ext@1 { + filename = "tiboot3-am69-hs-fs-aquila.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; }; #endif diff --git a/arch/arm/dts/k3-am69-aquila-dev.dts b/arch/arm/dts/k3-am69-aquila-dev.dts deleted file mode 100644 index c7ce804eac7..00000000000 --- a/arch/arm/dts/k3-am69-aquila-dev.dts +++ /dev/null @@ -1,576 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2025 Toradex - * - * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 - * https://www.toradex.com/products/carrier-board/aquila-development-board-kit - */ - -/dts-v1/; - -#include <dt-bindings/pwm/pwm.h> -#include "k3-am69-aquila.dtsi" - -/ { - model = "Toradex Aquila AM69 on Aquila Development Board"; - compatible = "toradex,aquila-am69-dev", - "toradex,aquila-am69", - "ti,j784s4"; - - aliases { - eeprom1 = &carrier_eeprom; - }; - - reg_1v8_sw: regulator-1v8-sw { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "Carrier_1V8"; - }; - - reg_3v3_dp: regulator-3v3-dp { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_21_dp>; - /* Aquila GPIO_21_DP (AQUILA B57) */ - gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "DP_3V3"; - startup-delay-us = <10000>; - }; - - dp0-connector { - compatible = "dp-connector"; - dp-pwr-supply = <®_3v3_dp>; - label = "Display Port"; - type = "full-size"; - - port { - dp0_connector_in: endpoint { - remote-endpoint = <&dp0_out>; - }; - }; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,name = "aquila-wm8904"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Microphone Jack", "MICBIAS", - "IN1L", "Microphone Jack", - "IN1R", "Digital Mic"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Microphone", "Digital Mic", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; - - codec_dai: simple-audio-card,codec { - sound-dai = <&wm8904_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&mcasp4>; - }; - }; -}; - -/* Aquila CTRL_PWR_BTN_MICO# */ -&aquila_key_power { - status = "okay"; -}; - -/* Aquila CTRL_WAKE1_MICO# */ -&aquila_key_wake { - status = "okay"; -}; - -/* On-module ETH_1 MDIO */ -&davinci_mdio { - status = "okay"; -}; - -&dp0_ports { - port@4 { - reg = <4>; - dp0_out: endpoint { - remote-endpoint = <&dp0_connector_in>; - }; - }; -}; - -&dss { - status = "okay"; -}; - -&main0_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main0_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main0_alert1>; - }; - }; -}; - -&main1_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main1_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main1_alert1>; - }; - }; -}; - -&main2_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main2_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main2_alert1>; - }; - }; -}; - -&main3_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main3_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main3_alert1>; - }; - }; -}; - -&main4_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&main4_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&main4_alert1>; - }; - }; -}; - -/* Aquila ETH_2 */ -&main_cpsw0 { - status = "okay"; -}; - -/* Aquila ETH_2 SGMII PHY */ -&main_cpsw0_port8 { - phy-handle = <&cpsw0_port8_phy4>; - status = "okay"; -}; - -/* Aquila ETH_2_XGMII_MDIO */ -&main_cpsw0_mdio { - status = "okay"; - - cpsw0_port8_phy4: ethernet-phy@4 { - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth2_int>; - interrupt-parent = <&main_gpio0>; - interrupts = <44 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -/* Aquila PWM_1 */ -&main_ehrpwm0 { - status = "okay"; -}; - -/* Aquila PWM_4_DP */ -&main_ehrpwm2 { - status = "okay"; -}; - -/* Aquila PWM_2 */ -&main_ehrpwm1 { - status = "okay"; -}; - -/* Aquila PWM_3_DSI */ -&main_ehrpwm5 { - status = "okay"; -}; - -&main_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_01>, /* Aquila GPIO_01 */ - <&pinctrl_gpio_02>, /* Aquila GPIO_02 */ - <&pinctrl_gpio_03>; /* Aquila GPIO_03 */ -}; - -/* Aquila I2C_3_DSI1 */ -&main_i2c0 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - /* I2C on DSI Connector Pin #4 and #6 */ - i2c_dsi_0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* I2C on DSI Connector Pin #52 and #54 */ - i2c_dsi_1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -/* Aquila I2C_4_CSI1 */ -&main_i2c1 { - status = "okay"; -}; - -/* Aquila I2C_5_CSI2 */ -&main_i2c2 { - status = "okay"; -}; - -/* Aquila I2C_6 */ -&main_i2c5 { - status = "okay"; -}; - -/* Aquila CAN_1 */ -&main_mcan10 { - status = "okay"; -}; - -/* Aquila CAN_3 */ -&main_mcan13 { - status = "okay"; -}; - -/* Aquila SD_1 */ -&main_sdhci1 { - status = "okay"; -}; - -/* Aquila SPI_2 */ -&main_spi0 { - status = "okay"; -}; - -/* Aquila SPI_1 */ -&main_spi2 { - status = "okay"; -}; - -/* Aquila UART_1 */ -&main_uart4 { - status = "okay"; -}; - -/* Aquila UART_3, used as the Linux console */ -&main_uart8 { - status = "okay"; -}; - -/* Aquila I2S_1 */ -&mcasp4 { - status = "okay"; -}; - -&mcu_cpsw { - status = "okay"; -}; - -/* On-module ETH_1 RGMII */ -&mcu_cpsw_port1 { - status = "okay"; -}; - -/* Aquila I2C_1 */ -&mcu_i2c0 { - clock-frequency = <100000>; - status = "okay"; - - fan_controller: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #pwm-cells = <2>; - - fan: fan { - cooling-levels = <102 179 255>; - #cooling-cells = <2>; - pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; - }; - }; - - wm8904_1a: audio-codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audio_extrefclk1>; - #sound-dai-cells = <0>; - clocks = <&audio_refclk1>; - clock-names = "mclk"; - AVDD-supply = <®_1v8_sw>; - CPVDD-supply = <®_1v8_sw>; - DBVDD-supply = <®_1v8_sw>; - DCVDD-supply = <®_1v8_sw>; - MICVDD-supply = <®_1v8_sw>; - - wlf,drc-cfg-names = "default", "peaklimiter"; - /* - * Config registers per name, respectively: - * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 - * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 - */ - wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, - /bits/ 16 <0x04af 0x324b 0x0010 0x0408>; - - /* GPIO1 = DMIC_CLK, don't touch others */ - wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; - - wlf,in1r-as-dmicdat2; - }; - - /* Current measurement into module VCC */ - hwmon@41 { - compatible = "ti,ina226"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - - temperature-sensor@4f { - compatible = "ti,tmp1075"; - reg = <0x4f>; - }; - - /* USB-C OTG (TCPC USB PD PHY) */ - tcpc@52 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x52>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_int>; - interrupt-parent = <&main_gpio0>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; - - connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C OTG"; - power-role = "dual"; - try-power-role = "sink"; - self-powered; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - op-sink-microwatt = <1000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_1_con_hs: endpoint { - remote-endpoint = <&usb0_hs>; - }; - }; - - port@1 { - reg = <1>; - - usb_1_con_ss: endpoint { - remote-endpoint = <&usb0_ss_mux>; - }; - }; - }; - }; - }; - - carrier_eeprom: eeprom@57 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x57>; - pagesize = <16>; - }; -}; - -/* Aquila I2C_2 */ -&mcu_i2c1 { - status = "okay"; -}; - -/* Aquila CAN_2 */ -&mcu_mcan0 { - status = "okay"; -}; - -/* Aquila CAN_4 */ -&mcu_mcan1 { - status = "okay"; -}; - -/* Aquila UART_4 */ -&mcu_uart0 { - status = "okay"; -}; - -&mhdp { - status = "okay"; -}; - -/* Aquila QSPI_1 */ -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_ospi0_4bit>, <&pinctrl_mcu_ospi0_cs0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-max-frequency = <66000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - cdns,read-delay = <0>; - cdns,tchsh-ns = <3>; - cdns,tsd2d-ns = <10>; - cdns,tshsl-ns = <30>; - cdns,tslch-ns = <8>; - }; -}; - -/* Aquila PCIE_1 */ -&pcie0_rc { - status = "okay"; -}; - -/* Aquila PCIE_2 */ -&pcie1_rc { - status = "okay"; -}; - -&serdes2 { - status = "okay"; -}; - -&serdes4 { - status = "okay"; -}; - -&serdes_wiz2 { - status = "okay"; -}; - -&serdes_wiz4 { - status = "okay"; -}; - -/* Aquila ADC_[1-4] */ -&tscadc0 { - status = "okay"; -}; - -&usbss0 { - status = "okay"; -}; - -&usb0ss_mux { - status = "okay"; - - port { - usb0_ss_mux: endpoint { - remote-endpoint = <&usb_1_con_ss>; - }; - }; -}; - -&usb0 { - status = "okay"; - - port { - usb0_hs: endpoint { - remote-endpoint = <&usb_1_con_hs>; - }; - }; -}; - -&wkup0_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&wkup0_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&wkup0_alert1>; - }; - }; -}; - -&wkup1_thermal { - cooling-maps { - map0 { - cooling-device = <&fan 1 1>; - trip = <&wkup1_alert0>; - }; - - map1 { - cooling-device = <&fan 2 2>; - trip = <&wkup1_alert1>; - }; - }; -}; - -&wkup_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_04>, /* Aquila GPIO_04 */ - <&pinctrl_gpio_05>, /* Aquila GPIO_05 */ - <&pinctrl_gpio_06>, /* Aquila GPIO_06 */ - <&pinctrl_gpio_07>, /* Aquila GPIO_07 */ - <&pinctrl_gpio_08>; /* Aquila GPIO_08 */ -}; - -/* Aquila UART_2, through RS485 transceiver */ -&wkup_uart0 { - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - status = "okay"; -}; diff --git a/arch/arm/dts/k3-am69-aquila.dtsi b/arch/arm/dts/k3-am69-aquila.dtsi deleted file mode 100644 index 5e1f92fc85f..00000000000 --- a/arch/arm/dts/k3-am69-aquila.dtsi +++ /dev/null @@ -1,1837 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2025 Toradex - * - * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/phy/phy-cadence.h> -#include <dt-bindings/usb/pd.h> -#include "k3-j784s4.dtsi" - -/ { - chosen { - stdout-path = "serial2:115200n8"; - }; - - aliases { - can0 = &main_mcan10; - can1 = &mcu_mcan0; - can2 = &main_mcan13; - can3 = &mcu_mcan1; - eeprom0 = &som_eeprom; - ethernet0 = &mcu_cpsw_port1; - ethernet1 = &main_cpsw0_port8; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &mcu_i2c1; - i2c3 = &main_i2c0; - i2c4 = &main_i2c1; - i2c5 = &main_i2c2; - i2c6 = &main_i2c5; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - rtc0 = &rtc_i2c; - serial0 = &main_uart4; - serial1 = &wkup_uart0; - serial2 = &main_uart8; - serial3 = &mcu_uart0; - usb0 = &usb0; - }; - - aquila_key_power: gpio-key-power { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwr_btn_int>; - status = "disabled"; - - key-power { - /* Aquila CTRL_PWR_BTN_MICO# (AQUILA B93) */ - gpios = <&wkup_gpio0 36 GPIO_ACTIVE_LOW>; - label = "Power Button"; - linux,code = <KEY_POWER>; - }; - }; - - aquila_key_wake: gpio-key-wakeup { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; - status = "disabled"; - - key-wakeup { - /* Aquila CTRL_WAKE1_MICO# (AQUILA D6) */ - gpios = <&wkup_gpio0 49 GPIO_ACTIVE_LOW>; - label = "Wake Up"; - linux,code = <KEY_WAKEUP>; - wakeup-source; - }; - }; - - /* Aquila CTRL_RESET_MICO# (AQUILA B92) */ - gpio-restart { - compatible = "gpio-restart"; - /* COLD_RESET_REQ */ - gpios = <&som_gpio_expander 1 GPIO_ACTIVE_HIGH>; - priority = <192>; - }; - - /* PWR_DOWN_REQ */ - gpio-poweroff { - compatible = "gpio-poweroff"; - /* PWR_DOWN_REQ */ - gpios = <&som_gpio_expander 2 GPIO_ACTIVE_HIGH>; - timeout-ms = <3000>; - }; - - memory@80000000 { - device_type = "memory"; - /* 32G RAM */ - reg = <0x00 0x80000000 0x00 0x80000000>, - <0x08 0x80000000 0x07 0x80000000>; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - }; - - /* Module Power Supply (VCC) */ - reg_vin: regulator-vin { - compatible = "regulator-fixed"; - regulator-name = "+V_IN"; - }; - - /* Enabled by EN_3V3_VIO (PMIC_GPIO_9) */ - reg_1v1_usb_bridge: regulator-1v1-vio { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "+V1.1_VIO"; - vin-supply = <®_vin>; - }; - - reg_3v3_wifi: regulator-3v3-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_en_3v3_wifi>; - gpio = <&wkup_gpio0 57 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_WIFI"; - startup-delay-us = <20000>; - vin-supply = <®_vin>; - }; - - reg_1v8_stby: regulator-1v8-stby { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_STBY"; - vin-supply = <®_vin>; - }; - - /* Aquila SD_1_PWR_EN */ - reg_sdhc1_vmmc: regulator-sdhci1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1_pwr_en>; - /* Aquila SD_1_PWR_EN (AQUILA A6) */ - gpio = <&main_gpio0 52 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <100000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+3V3_SD"; - startup-delay-us = <20000>; - }; - - reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { - compatible = "regulator-gpio"; - /* SDIO_PWR_SEL_3.3V */ - gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+VDD_SD_DV"; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - /* On-module USB_1_SS mux */ - usb0ss_mux: gpio-sbu-mux { - compatible = "ti,tmuxhs4212", "gpio-sbu-mux"; - orientation-switch; - /* USB_MUX_SEL */ - select-gpios = <&som_gpio_expander 0 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; -}; - -&main_pmx0 { - /* Aquila DP_1_HPD */ - pinctrl_main_dp0_hpd: main-dp0-hpd-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ /* AQUILA B59 */ - >; - }; - - /* Aquila PWM_1 */ - pinctrl_main_ehrpwm0_b: main-ehrpwm0b-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x064, PIN_OUTPUT, 9) /* (AF38) MCAN0_TX.EHRPWM0_B */ /* AQUILA C25 */ - >; - }; - - /* Aquila PWM_2 */ - pinctrl_main_ehrpwm1_a: main-ehrpwm1a-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x060, PIN_OUTPUT, 9) /* (AE36) MCASP2_AXR1.EHRPWM1_A */ /* AQUILA C26 */ - >; - }; - - /* Aquila PWM_3_DSI */ - pinctrl_main_ehrpwm5_a: main-ehrpwm5a-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x084, PIN_OUTPUT, 9) /* (AG38) MCASP0_AXR5.EHRPWM5_A */ /* AQUILA B46 */ - >; - }; - - /* Aquila PWM_4_DP */ - pinctrl_main_ehrpwm2_a: main-ehrpwm2a-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x040, PIN_INPUT, 9) /* (AF37) MCASP0_AXR0.EHRPWM2_A */ /* AQUILA B58 */ - >; - }; - - /* PMIC_INT# */ - pinctrl_pmic_int: main-gpio0-0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTn.GPIO0_0 */ - >; - }; - - /* Aquila GPIO_09_CSI_1 */ - pinctrl_gpio_09_csi_1: main-gpio0-1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ /* AQUILA B17 */ - >; - }; - - /* Aquila GPIO_10_CSI_1 */ - pinctrl_gpio_10_csi_1: main-gpio0-2-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ /* AQUILA B18 */ - >; - }; - - /* Aquila USB_1_OC# */ - pinctrl_usb1_oc: main-gpio0-10-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x028, PIN_INPUT, 7) /* (AE33) MCAN16_RX.GPIO0_10 */ /* AQUILA B75 */ - >; - }; - - /* Aquila USB_1_EN */ - pinctrl_usb1_en_gpio: main-gpio0-11-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x02c, PIN_INPUT, 7) /* (AL32) GPIO0_11 */ /* AQUILA B77 */ - >; - }; - - /* Aquila GPIO_17_DSI_1 */ - pinctrl_gpio_17_dsi_1: main-gpio0-12-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x030, PIN_INPUT, 7) /* (AK37) GPIO0_12 */ /* AQUILA B42 */ - >; - }; - - /* Aquila GPIO_19_DSI_1 */ - pinctrl_gpio_19_dsi_1: main-gpio0-13-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ /* AQUILA B44 */ - >; - }; - - /* Aquila GPIO_02 */ - pinctrl_gpio_02: main-gpio0-17-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x044, PIN_INPUT, 7) /* (AG37) MCASP0_AXR1.GPIO0_17 */ /* AQUILA D24 */ - >; - }; - - /* Aquila GPIO_20_DSI_1 */ - pinctrl_gpio_20_dsi_1: main-gpio0-18-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x048, PIN_INPUT, 7) /* (AK33) MCASP0_AXR2.GPIO0_18 */ /* AQUILA B45 */ - >; - }; - - /* Aquila GPIO_21_DP */ - pinctrl_gpio_21_dp: main-gpio0-21-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x054, PIN_INPUT, 7) /* (AD37) MCASP2_ACLKX.GPIO0_21 */ /* AQUILA B57 */ - >; - }; - - /* Aquila USB_1_INT# */ - pinctrl_usb1_int: main-gpio0-28-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x070, PIN_INPUT, 7) /* (AH38) MCAN1_RX.GPIO0_28 */ /* AQUILA B74 */ - >; - }; - - /* Aquila GPIO_03 */ - pinctrl_gpio_03: main-gpio0-29-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x074, PIN_INPUT, 7) /* (AC33) MCAN2_TX.GPIO0_29 */ /* AQUILA D25 */ - >; - }; - - /* Aquila GPIO_18_DSI_1 */ - pinctrl_gpio_18_dsi_1: main-gpio0-31-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x07c, PIN_INPUT, 7) /* (AJ38) MCASP0_AXR3.GPIO0_31 */ /* AQUILA B43 */ - >; - }; - - /* Aquila PCIE_1_RESET# */ - pinctrl_pcie0_reset: main-gpio0-32-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x080, PIN_INPUT, 7) /* (AK34) MCASP0_AXR4.GPIO0_32 */ /* AQUILA C38 */ - >; - }; - - /* Aquila PWM_3_DSI as GPIO */ - pinctrl_pwm3_dsi_gpio: main-gpio0-33-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x084, PIN_INPUT, 7) /* (AG38) MCASP0_AXR5.GPIO0_33 */ /* AQUILA B46 */ - >; - }; - - /* Aquila GPIO_01 */ - pinctrl_gpio_01: main-gpio0-34-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x088, PIN_INPUT, 7) /* (AF36) MCASP0_AXR6.GPIO0_34 */ /* AQUILA D23 */ - >; - }; - - /* Aquila PCIE_2_RESET# */ - pinctrl_pcie1_reset: main-gpio0-41-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ /* AQUILA C35 */ - >; - }; - - /* Aquila ETH_2_xGMII_INT# */ - pinctrl_eth2_int: main-gpio0-44-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 7) /* (AL33) MCASP1_AXR3.GPIO0_44 */ /* AQUILA B81 */ - >; - }; - - /* Aquila GPIO_11_CSI_1 */ - pinctrl_gpio_11_csi_1: main-gpio0-47-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ /* AQUILA A11 */ - >; - }; - - /* Aquila GPIO_12_CSI_1 */ - pinctrl_gpio_12_csi_1: main-gpio0-48-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ /* AQUILA B19 */ - >; - }; - - /* Aquila SD_1_PWR_EN */ - pinctrl_sd1_pwr_en: main-gpio0-52-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0d0, PIN_INPUT, 7) /* (AP38) SPI0_CS1.GPIO0_52 */ /* AQUILA A6 */ - >; - }; - - /* Aquila SD_1_CD# as GPIO */ - pinctrl_sd1_cd_gpio: main-gpio0-58-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0e8, PIN_INPUT_PULLUP, 7) /* (AR38) TIMER_IO0.GPIO0_58 */ /* AQUILA A1 */ - >; - }; - - /* Aquila I2C_3_DSI1 */ - pinctrl_main_i2c0: main-i2c0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ /* AQUILA B41 */ - J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ /* AQUILA B40 */ - >; - }; - - /* Aquila I2C_4_CSI1 */ - pinctrl_main_i2c1: main-i2c1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x020, PIN_INPUT_PULLUP, 12) /* (AJ35) MCAN15_RX.I2C1_SCL */ /* AQUILA A13 */ - J784S4_IOPAD(0x024, PIN_INPUT_PULLUP, 12) /* (AH34) MCAN16_TX.I2C1_SDA */ /* AQUILA A12 */ - >; - }; - - /* Aquila I2C_5_CSI2 */ - pinctrl_main_i2c2: main-i2c2-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x04c, PIN_INPUT_PULLUP, 13) /* (AC32) MCASP1_AXR1.I2C2_SCL */ /* AQUILA C6 */ - J784S4_IOPAD(0x050, PIN_INPUT_PULLUP, 13) /* (AC37) MCASP1_AXR2.I2C2_SDA */ /* AQUILA C5 */ - >; - }; - - /* Aquila I2C_6 */ - pinctrl_main_i2c5: main-i2c5-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x01c, PIN_INPUT_PULLUP, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ /* AQUILA C19 */ - J784S4_IOPAD(0x018, PIN_INPUT_PULLUP, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ /* AQUILA C18 */ - >; - }; - - /* Aquila I2S_1_MCLK */ - pinctrl_audio_extrefclk1: audio-extrefclk1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ /* AQUILA B24 */ - >; - }; - - /* Aquila CAN_1 */ - pinctrl_main_mcan10: main-mcan10-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0b8, PIN_INPUT, 0) /* (AC34) MCASP1_ACLKX.MCAN10_RX */ /* AQUILA B49 */ - J784S4_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (AL34) MCASP1_AXR4.MCAN10_TX */ /* AQUILA B48 */ - >; - }; - - /* Aquila CAN_3 */ - pinctrl_main_mcan13: main-mcan13-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x010, PIN_INPUT, 0) /* (AH33) MCAN13_RX */ /* AQUILA B54 */ - J784S4_IOPAD(0x00c, PIN_OUTPUT, 0) /* (AF33) MCAN13_TX */ /* AQUILA B53 */ - >; - }; - - /* Aquila I2S_1 */ - pinctrl_main_mcasp4: main-mcasp4-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0c8, PIN_INPUT, 1) /* (AJ32) EXT_REFCLK1.MCASP4_ACLKX */ /* AQUILA B20 */ - J784S4_IOPAD(0x06c, PIN_INPUT, 1) /* (AJ37) MCAN1_TX.MCASP4_AFSX */ /* AQUILA B21 */ - J784S4_IOPAD(0x068, PIN_OUTPUT, 1) /* (AE38) MCAN0_RX.MCASP4_AXR1 */ /* AQUILA B22 */ - J784S4_IOPAD(0x0c4, PIN_INPUT, 1) /* (AD36) ECAP0_IN_APWM_OUT.MCASP4_AXR2 */ /* AQUILA B23 */ - >; - }; - - /* Aquila ETH_2_XGMII_MDIO */ - pinctrl_main_mdio1: main-mdio1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x058, PIN_OUTPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ /* AQUILA B90 */ - J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ /* AQUILA B89 */ - >; - }; - - /* Aquila SD_1 */ - pinctrl_main_mmc1: main-mmc1-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ /* AQUILA A5 */ - J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ /* AQUILA A7 */ - J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ - J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ /* AQUILA A3 */ - J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ /* AQUILA A2 */ - J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ /* AQUILA A10 */ - J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ /* AQUILA A8 */ - >; - }; - - /* Aquila SPI_2 */ - pinctrl_main_spi0: main-spi0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AN38) SPI0_CLK */ /* AQUILA D14 */ - J784S4_IOPAD(0x0d8, PIN_INPUT, 0) /* (AM35) SPI0_D0 */ /* AQUILA D15 */ - J784S4_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (AM36) SPI0_D1 */ /* AQUILA D17 */ - >; - }; - - /* Aquila SPI_2 CS */ - pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */ - >; - }; - - /* Aquila SPI_1 */ - pinctrl_main_spi2: main-spi2-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x0a0, PIN_OUTPUT, 10) /* (AD34) MCASP0_AXR12.SPI2_CLK */ /* AQUILA D12 */ - J784S4_IOPAD(0x0a8, PIN_INPUT, 10) /* (AF34) MCASP0_AXR14.SPI2_D0 */ /* AQUILA D10 */ - J784S4_IOPAD(0x0ac, PIN_OUTPUT, 10) /* (AE34) MCASP0_AXR15.SPI2_D1 */ /* AQUILA D11 */ - >; - }; - - /* Aquila SPI_1 CS */ - pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */ - >; - }; - - /* Aquila UART_1 */ - pinctrl_main_uart4: main-uart4-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x094, PIN_INPUT, 11) /* (AG35) MCASP0_AXR9.UART4_CTSn */ /* AQUILA B36 */ - J784S4_IOPAD(0x098, PIN_OUTPUT, 11) /* (AH36) MCASP0_AXR10.UART4_RTSn */ /* AQUILA B38 */ - J784S4_IOPAD(0x08c, PIN_INPUT, 11) /* (AE35) MCASP0_AXR7.UART4_RXD */ /* AQUILA B35 */ - J784S4_IOPAD(0x090, PIN_OUTPUT, 11) /* (AC35) MCASP0_AXR8.UART4_TXD */ /* AQUILA B37 */ - >; - }; - - /* Aquila UART_3, used as the Linux console */ - pinctrl_main_uart8: main-uart8-default-pins { - pinctrl-single,pins = < - J784S4_IOPAD(0x038, PIN_INPUT, 11) /* (AK35) MCASP0_ACLKX.UART8_RXD */ /* AQUILA D19 */ - J784S4_IOPAD(0x03c, PIN_OUTPUT, 11) /* (AK38) MCASP0_AFSX.UART8_TXD */ /* AQUILA D20 */ - >; - }; -}; - -&wkup_pmx0 { - /* Aquila QSPI_1 (4-bit) */ - pinctrl_mcu_ospi0_4bit: mcu-ospi0-4bit-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ /* AQUILA B65 */ - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ /* AQUILA B68 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ /* AQUILA B67 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ /* AQUILA B61 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ /* AQUILA B60 */ - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ /* AQUILA B63 */ - >; - }; - - /* Aquila QSPI_1 (8-bit) */ - pinctrl_mcu_ospi0_8bit: mcu-ospi0-8bit-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ /* AQUILA B65 */ - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ /* AQUILA B68 */ - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ /* AQUILA B67 */ - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ /* AQUILA B61 */ - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ /* AQUILA B60 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ /* AQUILA B70 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ /* AQUILA B71 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ /* AQUILA B72 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ /* AQUILA B73 */ - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ /* AQUILA B63 */ - >; - }; - - /* Aquila QSPI_1_CS1# */ - pinctrl_mcu_ospi0_cs0: mcu-ospi0-cs0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ /* AQUILA B66 */ - >; - }; - - /* Aquila QSPI_1_CS2# */ - pinctrl_mcu_ospi0_cs1: mcu-ospi0-cs1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (A33) MCU_OSPI0_CSn1 */ /* AQUILA B62 */ - >; - }; - - /* Aquila QSPI_1_SCK as GPIO */ - pinctrl_wkup_gpio_16: wkup-gpio0-16-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (E32) MCU_OSPI0_CLK.WKUP_GPIO0_16 */ /* AQUILA B65 */ - >; - }; - - /* Aquila GPIO_04 */ - pinctrl_gpio_04: wkup-gpio0-17-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (D32) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */ /* AQUILA C20 */ - >; - }; - - /* Aquila QSPI_1_DQS as GPIO */ - pinctrl_wkup_gpio_18: wkup-gpio0-18-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (C34) MCU_OSPI0_DQS.WKUP_GPIO0_18 */ /* AQUILA B63 */ - >; - }; - - /* Aquila QSPI_1_IO0 as GPIO */ - pinctrl_wkup_gpio_19: wkup-gpio0-19-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (B33) MCU_OSPI0_D0.WKUP_GPIO0_19 */ /* AQUILA B68 */ - >; - }; - - /* Aquila QSPI_1_IO1 as GPIO */ - pinctrl_wkup_gpio_20: wkup-gpio0-20-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (B32) MCU_OSPI0_D1.WKUP_GPIO0_20 */ /* AQUILA B67 */ - >; - }; - - /* Aquila QSPI_1_IO2 as GPIO */ - pinctrl_wkup_gpio_21: wkup-gpio0-21-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (C33) MCU_OSPI0_D2.WKUP_GPIO0_21 */ /* AQUILA B61 */ - >; - }; - - /* Aquila QSPI_1_IO3 as GPIO */ - pinctrl_wkup_gpio_22: wkup-gpio0-22-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 7) /* (C35) MCU_OSPI0_D3.WKUP_GPIO0_22 */ /* AQUILA B60 */ - >; - }; - - /* Aquila QSPI_1_IO4 as GPIO */ - pinctrl_wkup_gpio_23: wkup-gpio0-23-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (D33) MCU_OSPI0_D4.WKUP_GPIO0_23 */ /* AQUILA B70 */ - >; - }; - - /* Aquila QSPI_1_IO5 as GPIO */ - pinctrl_wkup_gpio_24: wkup-gpio0-24-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (D34) MCU_OSPI0_D5.WKUP_GPIO0_24 */ /* AQUILA B71 */ - >; - }; - - /* Aquila QSPI_1_IO6 as GPIO */ - pinctrl_wkup_gpio_25: wkup-gpio0-25-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (E34) MCU_OSPI0_D6.WKUP_GPIO0_25 */ /* AQUILA B72 */ - >; - }; - - /* Aquila QSPI_1_IO7 as GPIO */ - pinctrl_wkup_gpio_26: wkup-gpio0-26-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (E33) MCU_OSPI0_D7.WKUP_GPIO0_26 */ /* AQUILA B73 */ - >; - }; - - /* Aquila QSPI_1_CS#1 as GPIO */ - pinctrl_wkup_gpio_27: wkup-gpio0-27-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 7) /* (A32) MCU_OSPI0_CSn0.WKUP_GPIO0_27 */ /* AQUILA B66 */ - >; - }; - - /* Aquila QSPI_1_CS#2 as GPIO */ - pinctrl_wkup_gpio_28: wkup-gpio0-28-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 7) /* (A33) MCU_OSPI0_CSn1.WKUP_GPIO0_28 */ /* AQUILA B62 */ - >; - }; -}; - -&wkup_pmx1 { - /* Aquila UART_4 (RXD) */ - pinctrl_mcu_uart0_rx: mcu-uart0-rx-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 4) /* (D31) MCU_OSPI1_D1.MCU_UART0_RXD */ /* AQUILA D21 */ - >; - }; - - /* Aquila GPIO_05 */ - pinctrl_gpio_05: wkup-gpio0-29-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (B34) MCU_OSPI0_CSn2.WKUP_GPIO0_29 */ /* AQUILA C21 */ - >; - }; - - /* Aquila GPIO_06 */ - pinctrl_gpio_06: wkup-gpio0-30-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (C32) MCU_OSPI0_CSn3.WKUP_GPIO0_30 */ /* AQUILA C22 */ - >; - }; - - /* Aquila GPIO_07 */ - pinctrl_gpio_07: wkup-gpio0-31-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (F32) MCU_OSPI1_CLK.WKUP_GPIO0_31 */ /* AQUILA C23 */ - >; - }; - - /* Aquila GPIO_13_CSI_2 */ - pinctrl_gpio_13_csi_2: wkup-gpio0-32-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (C31) MCU_OSPI1_LBCLKO.WKUP_GPIO0_32 */ /* AQUILA C1 */ - >; - }; - - /* Aquila GPIO_14_CSI_2 */ - pinctrl_gpio_14_csi_2: wkup-gpio0-33-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (F31) MCU_OSPI1_DQS.WKUP_GPIO0_33 */ /* AQUILA C2 */ - >; - }; - - /* RTC_IRQ# */ - pinctrl_rtc_irq: wkup-gpio0-34-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (E35) MCU_OSPI1_D0.WKUP_GPIO0_34 */ - >; - }; - - /* Aquila CTRL_PWR_BTN_MICO# (PWR_BTN_INT#) */ - pinctrl_pwr_btn_int: wkup-gpio0-36-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT_PULLUP, 7) /* (G31) MCU_OSPI1_D2.WKUP_GPIO0_36 */ /* AQUILA B92 */ - >; - }; - - /* Aquila GPIO_15_CSI_2 */ - pinctrl_gpio_15_csi_2: wkup-gpio0-37-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (F33) MCU_OSPI1_D3.WKUP_GPIO0_37 */ /* AQUILA C3 */ - >; - }; - - /* Aquila GPIO_08 */ - pinctrl_gpio_08: wkup-gpio0-38-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (G32) MCU_OSPI1_CSn0.WKUP_GPIO0_38 */ /* AQUILA C24 */ - >; - }; - - /* Aquila GPIO_16_CSI_2 */ - pinctrl_gpio_16_csi_2: wkup-gpio0-39-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ /* AQUILA C4 */ - >; - }; -}; - -&wkup_pmx2 { - /* Aquila ADC_[1-4] */ - pinctrl_mcu_adc0: mcu-adc0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (P36) MCU_ADC0_AIN0 */ /* AQUILA D1 */ - J784S4_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V36) MCU_ADC0_AIN1 */ /* AQUILA D2 */ - J784S4_WKUP_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (T34) MCU_ADC0_AIN2 */ /* AQUILA D3 */ - J784S4_WKUP_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (T36) MCU_ADC0_AIN3 */ /* AQUILA D4 */ - >; - }; - - /* Aquila CTRL_MCLK_MOCI */ - pinctrl_mcu_clkout0: mcu-clkout0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x084, PIN_OUTPUT, 6) /* (M38) WKUP_GPIO0_11.MCU_CLKOUT0 */ /* AQUILA A14 */ - >; - }; - - /* Aquila I2C_1 */ - pinctrl_mcu_i2c0: mcu-i2c0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (M35) MCU_I2C0_SCL */ /* AQUILA D8 */ - J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (G34) MCU_I2C0_SDA */ /* AQUILA D7 */ - >; - }; - - /* Aquila I2C_2 */ - pinctrl_mcu_i2c1: mcu-i2c1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ /* AQUILA C17 */ - J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ /* AQUILA C16 */ - >; - }; - - /* Aquila CAN_2 */ - pinctrl_mcu_mcan0: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ /* AQUILA B51 */ - J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ /* AQUILA B50 */ - >; - }; - - /* Aquila CAN_4 */ - pinctrl_mcu_mcan1: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ /* AQUILA B56 */ - J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ /* AQUILA B55 */ - >; - }; - - /* On-module ETH_1 MDIO */ - pinctrl_mcu_mdio: mcu-mdio-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ - J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ - >; - }; - - /* On-module ETH_1 RGMII */ - pinctrl_mcu_rgmii1: mcu-rgmii1-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ - J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ - J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ - J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ - J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ - J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ - J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ - J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ - J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ - J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ - J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ - J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ - >; - }; - - /* On-module SPI (TPM_SPI) */ - pinctrl_mcu_spi0: mcu-spi0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (G38) MCU_SPI0_CLK */ - J784S4_WKUP_IOPAD(0x044, PIN_OUTPUT, 0) /* (F37) MCU_SPI0_CS0 */ - J784S4_WKUP_IOPAD(0x03c, PIN_INPUT, 0) /* (H36) MCU_SPI0_D0 */ - J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (J38) MCU_SPI0_D1 */ - >; - }; - - /* Aquila UART_4 (TX) */ - pinctrl_mcu_uart0_tx: mcu-uart0-tx-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 2) /* (L33) WKUP_GPIO0_10.MCU_UART0_TXD */ /* AQUILA D22 */ - >; - }; - - /* On-module Wi-Fi Power Enable */ - pinctrl_en_3v3_wifi: wkup-gpio0-57-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ - >; - }; - - /* On-module TPM IRQ# */ - pinctrl_tpm_irq: wkup-gpio0-81-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 7) /* (V34) MCU_ADC1_AIN2.WKUP_GPIO0_81 */ - >; - }; - - /* On-module I2C - WKUP_I2C0 */ - pinctrl_wkup_i2c0: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ - J784S4_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ - >; - }; - - /* Aquila UART_2 */ - pinctrl_wkup_uart0: wkup-uart0-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ /* AQUILA B32 */ - J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ /* AQUILA B34 */ - J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ /* AQUILA B31 */ - J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ /* AQUILA B33 */ - >; - }; -}; - -&wkup_pmx3 { - /* Aquila CTRL_WAKE1_MICO# */ - pinctrl_ctrl_wake1_mico: wkup-gpio0-49-default-pins { - pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x000, PIN_INPUT_PULLUP, 7) /* (M33) WKUP_GPIO0_49 */ /* AQUILA D6 */ - >; - }; -}; - -/* Aquila I2S_1_MCLK */ -&audio_refclk1 { - assigned-clock-rates = <24576000>; -}; - -/* On-module ETH_1 MDIO */ -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_mdio>; - status = "disabled"; - - mcu_phy0: ethernet-phy@0 { - reg = <0>; - interrupt-parent = <&wkup_gpio0>; - interrupts = <79 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -&dss { - assigned-clocks = <&k3_clks 218 2>, - <&k3_clks 218 5>; - assigned-clock-parents = <&k3_clks 218 3>, - <&k3_clks 218 7>; - status = "disabled"; -}; - -&dss_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpi0_out: endpoint { - remote-endpoint = <&dp0_in>; - }; - }; -}; - -&dp0_ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dp0_in: endpoint { - remote-endpoint = <&dpi0_out>; - }; - }; -}; - -&main0_crit { - temperature = <105000>; -}; - -&main0_thermal { - trips { - main0_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main0_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&main1_crit { - temperature = <105000>; -}; - -&main1_thermal { - trips { - main1_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main1_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&main2_crit { - temperature = <105000>; -}; - -&main2_thermal { - trips { - main2_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main2_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&main3_crit { - temperature = <105000>; -}; - -&main3_thermal { - trips { - main3_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main3_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&main4_crit { - temperature = <105000>; -}; - -&main4_thermal { - trips { - main4_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - main4_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -/* Aquila ETH_2 SGMII PHY */ -&main_cpsw0_port8 { - phy-mode = "sgmii"; - phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_sgmii_link>; - phy-names = "mac", "serdes"; - status = "disabled"; -}; - -/* Aquila ETH_2_XGMII_MDIO */ -&main_cpsw0_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mdio1>; -}; - -/* Aquila PWM_1 */ -&main_ehrpwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_ehrpwm0_b>; - status = "disabled"; -}; - -/* Aquila PWM_2 */ -&main_ehrpwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_ehrpwm1_a>; - status = "disabled"; -}; - -/* Aquila PWM_4_DP */ -&main_ehrpwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_ehrpwm2_a>; - status = "disabled"; -}; - -/* Aquila PWM_3_DSI */ -&main_ehrpwm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_ehrpwm5_a>; - status = "disabled"; -}; - -&main_gpio0 { - gpio-line-names = - "", /* 0 */ - "AQUILA_B17", - "AQUILA_B18", - "AQUILA_B53", - "AQUILA_B54", - "AQUILA_B59", - "AQUILA_C18", - "AQUILA_C19", - "AQUILA_A13", - "AQUILA_A12", - "AQUILA_B75", /* 10 */ - "AQUILA_B77", - "AQUILA_B42", - "AQUILA_B44", - "AQUILA_D19", - "AQUILA_D20", - "AQUILA_B58", - "AQUILA_D24", - "AQUILA_B45", - "AQUILA_C06", - "AQUILA_C05", /* 20 */ - "AQUILA_B57", - "AQUILA_B90", - "AQUILA_B89", - "AQUILA_C26", - "AQUILA_C25", - "AQUILA_B22", - "AQUILA_B21", - "AQUILA_B74", - "AQUILA_D25", - "AQUILA_B24", /* 30 */ - "AQUILA_B43", - "AQUILA_C38", - "AQUILA_B46", - "AQUILA_D23", - "AQUILA_B35", - "AQUILA_B37", - "AQUILA_B36", - "AQUILA_B38", - "AQUILA_D09", - "AQUILA_D12", /* 40 */ - "AQUILA_C35", - "AQUILA_D10", - "AQUILA_D11", - "AQUILA_B81", - "AQUILA_B48", - "AQUILA_B49", - "AQUILA_A11", - "AQUILA_B19", - "AQUILA_B23", - "AQUILA_B20", /* 50 */ - "AQUILA_D16", - "AQUILA_A06", - "AQUILA_D14", - "AQUILA_D15", - "AQUILA_D17", - "AQUILA_B41", - "AQUILA_B40", - "AQUILA_A01", - "", - "AQUILA_A08", /* 60 */ - "AQUILA_A10", - "AQUILA_A02", - "AQUILA_A03", - "AQUILA_A05", - "AQUILA_A07"; - - status = "okay"; -}; - -/* Aquila I2C_3_DSI1 */ -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c0>; - clock-frequency = <100000>; - status = "disabled"; -}; - -/* Aquila I2C_4_CSI1 */ -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c1>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila I2C_5_CSI2 */ -&main_i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c2>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila I2C_6 */ -&main_i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c5>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila CAN_1 */ -&main_mcan10 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mcan10>; - status = "disabled"; -}; - -/* Aquila CAN_3 */ -&main_mcan13 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mcan13>; - status = "disabled"; -}; - -/* On-module eMMC */ -&main_sdhci0 { - disable-wp; - non-removable; - ti,driver-strength-ohm = <50>; - status = "okay"; -}; - -/* Aquila SD_1 */ -&main_sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mmc1>, <&pinctrl_sd1_cd_gpio>; - cd-gpios = <&main_gpio0 58 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <®_sdhc1_vmmc>; - vqmmc-supply = <®_sdhc1_vqmmc>; - ti,driver-strength-ohm = <50>; - ti,fails-without-test-cd; - status = "disabled"; -}; - -/* Aquila SPI_2 */ -&main_spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>; - status = "disabled"; -}; - -/* Aquila SPI_1 */ -&main_spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>; - status = "disabled"; -}; - -/* Aquila UART_1 */ -&main_uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_uart4>; - status = "disabled"; -}; - -/* Aquila UART_3, used as the Linux console */ -&main_uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_uart8>; - status = "disabled"; -}; - -/* Aquila I2S_1 */ -&mcasp4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mcasp4>; - op-mode = <0>; /* MCASP_I2S_MODE */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 0 1 2 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tdm-slots = <2>; - #sound-dai-cells = <0>; - status = "disabled"; -}; - -&mcu_cpsw { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_rgmii1>; - status = "disabled"; -}; - -/* On-module ETH_1 RGMII */ -&mcu_cpsw_port1 { - phy-handle = <&mcu_phy0>; - phy-mode = "rgmii-id"; - status = "disabled"; -}; - -/* Aquila I2C_1 */ -&mcu_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_i2c0>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila I2C_2 */ -&mcu_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_i2c1>; - clock-frequency = <400000>; - status = "disabled"; -}; - -/* Aquila CAN_2 */ -&mcu_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_mcan0>; - status = "disabled"; -}; - -/* Aquila CAN_4 */ -&mcu_mcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_mcan1>; - status = "disabled"; -}; - -/* On-module SPI (TPM_SPI) */ -&mcu_spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_spi0>; - status = "okay"; - - tpm@0 { - compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpm_irq>; - interrupt-parent = <&wkup_gpio0>; - interrupts = <81 IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <33000000>; - }; -}; - -/* Aquila UART_4 */ -&mcu_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_uart0_rx>, <&pinctrl_mcu_uart0_tx>; - status = "disabled"; -}; - -&mhdp { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_dp0_hpd>; - phy-names = "dpphy"; - phys = <&serdes4_dp0_link>; - status = "disabled"; -}; - -/* Aquila QSPI_1 */ -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_ospi0_8bit>, <&pinctrl_mcu_ospi0_cs0>; - status = "disabled"; -}; - -/* Aquila PCIE_1 */ -&pcie0_rc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie0_reset>; - clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; - clock-names = "fck", "pcie_refclk"; - num-lanes = <2>; - phy-names = "pcie-phy"; - phys = <&serdes1_pcie0_2l_link>; - reset-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; - ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>; - status = "disabled"; -}; - -/* Aquila PCIE_2 */ -&pcie1_rc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie1_reset>; - clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; - clock-names = "fck", "pcie_refclk"; - num-lanes = <2>; - phy-names = "pcie-phy"; - phys = <&serdes0_pcie1_2l_link>; - reset-gpios = <&main_gpio0 41 GPIO_ACTIVE_HIGH>; - ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; - status = "disabled"; -}; - -/* On-module PCIe USB Bridge */ -&pcie2_rc { - clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; - clock-names = "fck", "pcie_refclk"; - num-lanes = <1>; - phy-names = "pcie-phy"; - phys = <&serdes1_pcie2_1l_link>; - reset-gpios = <&som_gpio_expander 3 GPIO_ACTIVE_HIGH>; - ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>; - status = "okay"; - - pci@0,0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - usb@0 { - compatible = "pci104c,8241"; - reg = <0x0 0x0 0x0 0x0 0x0>; - ti,pwron-active-high; - }; - }; -}; - -/* PCIE for On-module Wi-Fi */ -&pcie3_rc { - clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; - clock-names = "fck", "pcie_refclk"; - num-lanes = <1>; - phy-names = "pcie-phy"; - phys = <&serdes0_pcie3_1l_link>; - reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_HIGH>; - ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>; - status = "okay"; -}; - -&serdes0 { - status = "okay"; - - /* Aquila PCIE_2 */ - serdes0_pcie1_2l_link: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; - cdns,num-lanes = <2>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; - - /* On-module PCIe Wi-Fi */ - serdes0_pcie3_1l_link: phy@2 { - reg = <2>; - #phy-cells = <0>; - resets = <&serdes_wiz0 3>; - cdns,num-lanes = <1>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; - - /* Aquila USB0 SS */ - serdes0_usb0_ss_link: phy@3 { - reg = <3>; - #phy-cells = <0>; - resets = <&serdes_wiz0 4>; - cdns,num-lanes = <1>; - cdns,phy-type = <PHY_TYPE_USB3>; - }; -}; - -&serdes1 { - status = "okay"; - - /* Aquila PCIE_1 */ - serdes1_pcie0_2l_link: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; - cdns,num-lanes = <2>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; - - /* On-module PCIe USB Bridge */ - serdes1_pcie2_1l_link: phy@2 { - reg = <2>; - #phy-cells = <0>; - resets = <&serdes_wiz1 3>; - cdns,num-lanes = <1>; - cdns,phy-type = <PHY_TYPE_PCIE>; - }; -}; - -&serdes2 { - status = "disabled"; - - /* Aquila ETH_2 xGMII */ - serdes2_sgmii_link: phy@3 { - reg = <3>; - #phy-cells = <0>; - resets = <&serdes_wiz2 4>; - cdns,num-lanes = <1>; - cdns,phy-type = <PHY_TYPE_SGMII>; - }; -}; - -&serdes4 { - status = "disabled"; - - /* Aquila DP_1 */ - serdes4_dp0_link: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, - <&serdes_wiz4 3>, <&serdes_wiz4 4>; - cdns,max-bit-rate = <5400>; - cdns,num-lanes = <4>; - cdns,phy-type = <PHY_TYPE_DP>; - }; -}; - -&serdes_refclk { - clock-frequency = <100000000>; - status = "okay"; -}; - -&serdes_ln_ctrl { - idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, /* Aquila PCIE_2 L0 */ - <J784S4_SERDES0_LANE1_PCIE1_LANE1>, /* Aquila PCIE_2 L1 */ - <J784S4_SERDES0_LANE2_PCIE3_LANE0>, /* On-module PCIe Wi-Fi */ - <J784S4_SERDES0_LANE3_USB>, /* Aquila USB0 SS */ - <J784S4_SERDES1_LANE0_PCIE0_LANE0>, /* Aquila PCIE_1 L0 */ - <J784S4_SERDES1_LANE1_PCIE0_LANE1>, /* Aquila PCIE_1 L1 */ - <J784S4_SERDES1_LANE2_PCIE2_LANE0>, /* On-module PCIe USB Bridge */ - <J784S4_SERDES1_LANE3_QSGMII_LANE2>, /* Aquila SGMII MSP_9 */ - <J784S4_SERDES2_LANE0_QSGMII_LANE5>, /* Aquila SGMII MSP_6 */ - <J784S4_SERDES2_LANE1_QSGMII_LANE6>, /* Aquila SGMII MSP_7 */ - <J784S4_SERDES2_LANE2_QSGMII_LANE7>, /* Aquila SGMII MSP_8 */ - <J784S4_SERDES2_LANE3_QSGMII_LANE8>, /* Aquila ETH_2 xGMII */ - <J784S4_SERDES4_LANE0_EDP_LANE0>, /* Aquila DP L0 */ - <J784S4_SERDES4_LANE1_EDP_LANE1>, /* Aquila DP L1 */ - <J784S4_SERDES4_LANE2_EDP_LANE2>, /* Aquila DP L2 */ - <J784S4_SERDES4_LANE3_EDP_LANE3>; /* Aquila DP L3 */ -}; - -&serdes_wiz0 { - status = "okay"; -}; - -&serdes_wiz1 { - status = "okay"; -}; - -&serdes_wiz2 { - status = "disabled"; -}; - -&serdes_wiz4 { - status = "disabled"; -}; - -/* Aquila ADC_[1-4] */ -&tscadc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_adc0>; - status = "disabled"; - - adc { - ti,adc-channels = <0 1 2 3>; - }; -}; - -&usb0 { - phys = <&serdes0_usb0_ss_link>; - phy-names = "cdns3,usb3-phy"; - dr_mode = "otg"; - maximum-speed = "super-speed"; - usb-role-switch; - status = "disabled"; -}; - -&usb_serdes_mux { - idle-states = <0>; /* USB0 to SERDES lane 3 */ -}; - -&usbss0 { - ti,vbus-divider; - status = "disabled"; -}; - -&wkup_gpio0 { - gpio-line-names = - "", /* 0 */ - "", - "", - "AQUILA_C53", - "AQUILA_B55", - "AQUILA_B56", - "AQUILA_B32", - "AQUILA_B34", - "AQUILA_C17", - "AQUILA_C16", - "AQUILA_D22", /* 10 */ - "", - "", - "", - "", - "", - "AQUILA_B65", - "AQUILA_C20", - "AQUILA_B63", - "AQUILA_B68", - "AQUILA_B67", /* 20 */ - "AQUILA_B61", - "AQUILA_B60", - "AQUILA_B70", - "AQUILA_B71", - "AQUILA_B72", - "AQUILC_B73", - "AQUILA_B66", - "AQUILA_B62", - "AQUILA_C21", - "AQUILA_C22", /* 30 */ - "AQUILA_C23", - "AQUILA_C01", - "AQUILA_C02", - "", - "AQUILA_D21", - "", - "AQUILA_C03", - "AQUILA_C24", - "AQUILA_C04", - "AQUILA_B84", /* 40 */ - "", - "AQUILA_B86", - "AQUILA_B87", - "", - "", - "AQUILA_B83", - "", - "", - "", - "", /* 50 */ - "", - "", - "", - "", - "", - "", - "", - "AQUILA_B31", - "AQUILA_B33", - "AQUILA_B50", /* 60 */ - "AQUILA_B51", - "", - "", - "", - "AQUILA_D08", - "", - "", - "", - "", - "", /* 70 */ - "AQUILA_D01", - "AQUILA_D02", - "AQUILA_D03", - "AQUILA_D04", - "AQUILA_D54", - "AQUILA_D55", - "AQUILA_C55", - "AQUILA_C56", - "", - "AQUILA_C36", /* 80 */ - "", - "", - "", - "", - "", - "", - "AQUILA_D07", - ""; - - status = "okay"; -}; - -/* On-module I2C - WKUP_I2C0 */ -&wkup_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_i2c0>; - clock-frequency = <400000>; - status = "okay"; - - som_gpio_expander: gpio@21 { - compatible = "ti,tca6408"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "USB_MUX_SEL", - "COLD_RESET_REQ", - "PWR_DOWN_REQ", - "PCIE_3_RESET#", - "PCIE_4_RESET#", - "WIFI_DISABLE", - "BT_DISABLE", - "SDIO_PWR_SEL_3.3V"; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - tps62873a: regulator@40 { - compatible = "ti,tps62873"; - reg = <0x40>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <900000>; - regulator-min-microvolt = <600000>; - regulator-name = "+VDD_CPU_AVS"; - }; - - tps62873b: regulator@43 { - compatible = "ti,tps62873"; - reg = <0x43>; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <840000>; - regulator-min-microvolt = <760000>; - regulator-name = "+V0.8_VDD_CORE"; - }; - - pmic_tps6594: pmic@48 { - compatible = "ti,tps6594-q1"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic_int>; - interrupt-parent = <&main_gpio0>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - #gpio-cells = <2>; - gpio-controller; - buck12-supply = <®_vin>; - buck3-supply = <®_vin>; - buck4-supply = <®_vin>; - buck5-supply = <®_vin>; - ldo1-supply = <®_vin>; - ldo2-supply = <®_vin>; - ldo3-supply = <®_vin>; - ldo4-supply = <®_vin>; - system-power-controller; - ti,primary-pmic; - - regulators { - reg_vdd_ddr: buck12 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "+V1.1_VDD_DDR (PMIC BUCK12)"; - }; - - reg_vdd_ram: buck3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; - regulator-name = "+V0.85_VDD_RAM (PMIC BUCK3)"; - }; - - reg_vdd_io: buck4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_VDD_IO (PMIC BUCK4)"; - }; - - reg_3v3_vio: buck5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_VIO (PMIC BUCK5)"; - }; - - reg_vda_phy: ldo1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_VDA_PHY (PMIC LDO1)"; - }; - - reg_2v5_eth: ldo2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <2500000>; - regulator-name = "+V2.5_ETH (PMIC LDO2)"; - }; - - reg_vda_dll: ldo3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <800000>; - regulator-min-microvolt = <800000>; - regulator-name = "+V0.8_VDA_DLL (PMIC LDO3)"; - }; - - reg_vda_pll: ldo4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V0.8_VDA_PLL (PMIC LDO4)"; - }; - }; - }; - - temperature-sensor@4f { - compatible = "ti,tmp1075"; - reg = <0x4f>; - }; - - som_eeprom: eeprom@50 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&wkup0_crit { - temperature = <105000>; -}; - -&wkup0_thermal { - trips { - wkup0_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - wkup0_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&wkup1_crit { - temperature = <105000>; -}; - -&wkup1_thermal { - trips { - wkup1_alert0: trip-point0 { - temperature = <70000>; - hysteresis = <2000>; - type = "active"; - }; - - wkup1_alert1: trip-point1 { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - }; -}; - -&wkup_gpio_intr { - status = "okay"; -}; - -/* Aquila UART_2 */ -&wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_uart0>; - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi b/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi new file mode 100644 index 00000000000..6d9c7a6bb06 --- /dev/null +++ b/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi @@ -0,0 +1,8786 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:56:24 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 2 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 3 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS2_PLL_FHS_CNT 5 +#define DDRSS3_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_0 27500000 +#define DDRSS_PLL_FREQUENCY_1 1066500000 +#define DDRSS_PLL_FREQUENCY_2 1066500000 + +#define MULTI_DDR_CFG_INTRLV_GRAN 0 +#define MULTI_DDR_CFG_INTRLV_SIZE 12 +#define MULTI_DDR_CFG_ECC_ENABLE 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 24 +#define MULTI_DDR_CFG_EMIFS_ACTIVE 15 + +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay +#define DDR2_CTL_NODE_STAT okay +#define DDR3_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000007 +#define DDR_REG1_SIZE_LSB 0x80000000 + + +#define DDRSS0_CTL_00_DATA 0x00000B00 +#define DDRSS0_CTL_01_DATA 0x00000000 +#define DDRSS0_CTL_02_DATA 0x00000000 +#define DDRSS0_CTL_03_DATA 0x00000000 +#define DDRSS0_CTL_04_DATA 0x00000000 +#define DDRSS0_CTL_05_DATA 0x00000000 +#define DDRSS0_CTL_06_DATA 0x00000000 +#define DDRSS0_CTL_07_DATA 0x00002AF8 +#define DDRSS0_CTL_08_DATA 0x0001ADAF +#define DDRSS0_CTL_09_DATA 0x00000005 +#define DDRSS0_CTL_10_DATA 0x0000006E +#define DDRSS0_CTL_11_DATA 0x000681C8 +#define DDRSS0_CTL_12_DATA 0x004111C9 +#define DDRSS0_CTL_13_DATA 0x00000005 +#define DDRSS0_CTL_14_DATA 0x000010A9 +#define DDRSS0_CTL_15_DATA 0x000681C8 +#define DDRSS0_CTL_16_DATA 0x004111C9 +#define DDRSS0_CTL_17_DATA 0x00000005 +#define DDRSS0_CTL_18_DATA 0x000010A9 +#define DDRSS0_CTL_19_DATA 0x01010000 +#define DDRSS0_CTL_20_DATA 0x01011001 +#define DDRSS0_CTL_21_DATA 0x02010000 +#define DDRSS0_CTL_22_DATA 0x00020100 +#define DDRSS0_CTL_23_DATA 0x0000000B +#define DDRSS0_CTL_24_DATA 0x0000001C +#define DDRSS0_CTL_25_DATA 0x00000000 +#define DDRSS0_CTL_26_DATA 0x00000000 +#define DDRSS0_CTL_27_DATA 0x03020200 +#define DDRSS0_CTL_28_DATA 0x00005656 +#define DDRSS0_CTL_29_DATA 0x00100000 +#define DDRSS0_CTL_30_DATA 0x00000000 +#define DDRSS0_CTL_31_DATA 0x00000000 +#define DDRSS0_CTL_32_DATA 0x00000000 +#define DDRSS0_CTL_33_DATA 0x00000000 +#define DDRSS0_CTL_34_DATA 0x040C0000 +#define DDRSS0_CTL_35_DATA 0x12501250 +#define DDRSS0_CTL_36_DATA 0x00050804 +#define DDRSS0_CTL_37_DATA 0x09040008 +#define DDRSS0_CTL_38_DATA 0x15000204 +#define DDRSS0_CTL_39_DATA 0x1760008B +#define DDRSS0_CTL_40_DATA 0x1500422B +#define DDRSS0_CTL_41_DATA 0x1760008B +#define DDRSS0_CTL_42_DATA 0x2000422B +#define DDRSS0_CTL_43_DATA 0x000A0A09 +#define DDRSS0_CTL_44_DATA 0x040003C5 +#define DDRSS0_CTL_45_DATA 0x1E161104 +#define DDRSS0_CTL_46_DATA 0x1000922C +#define DDRSS0_CTL_47_DATA 0x1E161110 +#define DDRSS0_CTL_48_DATA 0x1000922C +#define DDRSS0_CTL_49_DATA 0x02030410 +#define DDRSS0_CTL_50_DATA 0x2C060500 +#define DDRSS0_CTL_51_DATA 0x08292C29 +#define DDRSS0_CTL_52_DATA 0x14000E0A +#define DDRSS0_CTL_53_DATA 0x04010A0A +#define DDRSS0_CTL_54_DATA 0x01010004 +#define DDRSS0_CTL_55_DATA 0x0454540A +#define DDRSS0_CTL_56_DATA 0x04313104 +#define DDRSS0_CTL_57_DATA 0x00003131 +#define DDRSS0_CTL_58_DATA 0x00010100 +#define DDRSS0_CTL_59_DATA 0x03010000 +#define DDRSS0_CTL_60_DATA 0x00001508 +#define DDRSS0_CTL_61_DATA 0x00000068 +#define DDRSS0_CTL_62_DATA 0x0000032B +#define DDRSS0_CTL_63_DATA 0x00001035 +#define DDRSS0_CTL_64_DATA 0x0000032B +#define DDRSS0_CTL_65_DATA 0x00001035 +#define DDRSS0_CTL_66_DATA 0x00000005 +#define DDRSS0_CTL_67_DATA 0x00050000 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 +#define DDRSS0_CTL_71_DATA 0x00120103 +#define DDRSS0_CTL_72_DATA 0x00100005 +#define DDRSS0_CTL_73_DATA 0x2F080010 +#define DDRSS0_CTL_74_DATA 0x0505012F +#define DDRSS0_CTL_75_DATA 0x0401030A +#define DDRSS0_CTL_76_DATA 0x041E100B +#define DDRSS0_CTL_77_DATA 0x100B0401 +#define DDRSS0_CTL_78_DATA 0x0001041E +#define DDRSS0_CTL_79_DATA 0x00160016 +#define DDRSS0_CTL_80_DATA 0x033B033B +#define DDRSS0_CTL_81_DATA 0x033B033B +#define DDRSS0_CTL_82_DATA 0x03050505 +#define DDRSS0_CTL_83_DATA 0x03010303 +#define DDRSS0_CTL_84_DATA 0x200B100B +#define DDRSS0_CTL_85_DATA 0x04041004 +#define DDRSS0_CTL_86_DATA 0x200B100B +#define DDRSS0_CTL_87_DATA 0x04041004 +#define DDRSS0_CTL_88_DATA 0x03010000 +#define DDRSS0_CTL_89_DATA 0x00010000 +#define DDRSS0_CTL_90_DATA 0x00000000 +#define DDRSS0_CTL_91_DATA 0x00000000 +#define DDRSS0_CTL_92_DATA 0x01000000 +#define DDRSS0_CTL_93_DATA 0x80104002 +#define DDRSS0_CTL_94_DATA 0x00000000 +#define DDRSS0_CTL_95_DATA 0x00040005 +#define DDRSS0_CTL_96_DATA 0x00000000 +#define DDRSS0_CTL_97_DATA 0x00050000 +#define DDRSS0_CTL_98_DATA 0x00000004 +#define DDRSS0_CTL_99_DATA 0x00000000 +#define DDRSS0_CTL_100_DATA 0x00040005 +#define DDRSS0_CTL_101_DATA 0x00000000 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 +#define DDRSS0_CTL_107_DATA 0x00000000 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 +#define DDRSS0_CTL_114_DATA 0x00000000 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 +#define DDRSS0_CTL_121_DATA 0x00000000 +#define DDRSS0_CTL_122_DATA 0x00007173 +#define DDRSS0_CTL_123_DATA 0x00000000 +#define DDRSS0_CTL_124_DATA 0x00000000 +#define DDRSS0_CTL_125_DATA 0x00000000 +#define DDRSS0_CTL_126_DATA 0x00000000 +#define DDRSS0_CTL_127_DATA 0x00000000 +#define DDRSS0_CTL_128_DATA 0x00000000 +#define DDRSS0_CTL_129_DATA 0x00000000 +#define DDRSS0_CTL_130_DATA 0x00000000 +#define DDRSS0_CTL_131_DATA 0x0B030500 +#define DDRSS0_CTL_132_DATA 0x00040B04 +#define DDRSS0_CTL_133_DATA 0x0A090000 +#define DDRSS0_CTL_134_DATA 0x0A090701 +#define DDRSS0_CTL_135_DATA 0x0900000E +#define DDRSS0_CTL_136_DATA 0x0907010A +#define DDRSS0_CTL_137_DATA 0x00000E0A +#define DDRSS0_CTL_138_DATA 0x07010A09 +#define DDRSS0_CTL_139_DATA 0x000E0A09 +#define DDRSS0_CTL_140_DATA 0x07000401 +#define DDRSS0_CTL_141_DATA 0x00000000 +#define DDRSS0_CTL_142_DATA 0x00000000 +#define DDRSS0_CTL_143_DATA 0x00000000 +#define DDRSS0_CTL_144_DATA 0x00000000 +#define DDRSS0_CTL_145_DATA 0x00000000 +#define DDRSS0_CTL_146_DATA 0x00000000 +#define DDRSS0_CTL_147_DATA 0x00000000 +#define DDRSS0_CTL_148_DATA 0x08080000 +#define DDRSS0_CTL_149_DATA 0x01000000 +#define DDRSS0_CTL_150_DATA 0x800000C0 +#define DDRSS0_CTL_151_DATA 0x800000C0 +#define DDRSS0_CTL_152_DATA 0x800000C0 +#define DDRSS0_CTL_153_DATA 0x00000000 +#define DDRSS0_CTL_154_DATA 0x00001500 +#define DDRSS0_CTL_155_DATA 0x00000000 +#define DDRSS0_CTL_156_DATA 0x00000001 +#define DDRSS0_CTL_157_DATA 0x00000002 +#define DDRSS0_CTL_158_DATA 0x0000100E +#define DDRSS0_CTL_159_DATA 0x00000000 +#define DDRSS0_CTL_160_DATA 0x00000000 +#define DDRSS0_CTL_161_DATA 0x00000000 +#define DDRSS0_CTL_162_DATA 0x00000000 +#define DDRSS0_CTL_163_DATA 0x00000000 +#define DDRSS0_CTL_164_DATA 0x000B0000 +#define DDRSS0_CTL_165_DATA 0x000E0006 +#define DDRSS0_CTL_166_DATA 0x000E0404 +#define DDRSS0_CTL_167_DATA 0x00D601AB +#define DDRSS0_CTL_168_DATA 0x10100216 +#define DDRSS0_CTL_169_DATA 0x01AB0216 +#define DDRSS0_CTL_170_DATA 0x021600D6 +#define DDRSS0_CTL_171_DATA 0x02161010 +#define DDRSS0_CTL_172_DATA 0x00000000 +#define DDRSS0_CTL_173_DATA 0x00000000 +#define DDRSS0_CTL_174_DATA 0x00000000 +#define DDRSS0_CTL_175_DATA 0x3FF40084 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 +#define DDRSS0_CTL_178_DATA 0x35000000 +#define DDRSS0_CTL_179_DATA 0x27270035 +#define DDRSS0_CTL_180_DATA 0x0F0F0000 +#define DDRSS0_CTL_181_DATA 0x16000000 +#define DDRSS0_CTL_182_DATA 0x00841616 +#define DDRSS0_CTL_183_DATA 0x3FF43FF4 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 +#define DDRSS0_CTL_185_DATA 0x00000000 +#define DDRSS0_CTL_186_DATA 0x00353500 +#define DDRSS0_CTL_187_DATA 0x00002727 +#define DDRSS0_CTL_188_DATA 0x00000F0F +#define DDRSS0_CTL_189_DATA 0x16161600 +#define DDRSS0_CTL_190_DATA 0x00000020 +#define DDRSS0_CTL_191_DATA 0x01000000 +#define DDRSS0_CTL_192_DATA 0x00000001 +#define DDRSS0_CTL_193_DATA 0x00000000 +#define DDRSS0_CTL_194_DATA 0x01000000 +#define DDRSS0_CTL_195_DATA 0x00000001 +#define DDRSS0_CTL_196_DATA 0x00000000 +#define DDRSS0_CTL_197_DATA 0x00000000 +#define DDRSS0_CTL_198_DATA 0x00000000 +#define DDRSS0_CTL_199_DATA 0x00000000 +#define DDRSS0_CTL_200_DATA 0x00000000 +#define DDRSS0_CTL_201_DATA 0x00000000 +#define DDRSS0_CTL_202_DATA 0x00000000 +#define DDRSS0_CTL_203_DATA 0x00000000 +#define DDRSS0_CTL_204_DATA 0x00000000 +#define DDRSS0_CTL_205_DATA 0x00000000 +#define DDRSS0_CTL_206_DATA 0x02000000 +#define DDRSS0_CTL_207_DATA 0x01080101 +#define DDRSS0_CTL_208_DATA 0x00000000 +#define DDRSS0_CTL_209_DATA 0x00000000 +#define DDRSS0_CTL_210_DATA 0x00000000 +#define DDRSS0_CTL_211_DATA 0x00000000 +#define DDRSS0_CTL_212_DATA 0x00000000 +#define DDRSS0_CTL_213_DATA 0x00000000 +#define DDRSS0_CTL_214_DATA 0x00000000 +#define DDRSS0_CTL_215_DATA 0x00000000 +#define DDRSS0_CTL_216_DATA 0x00000000 +#define DDRSS0_CTL_217_DATA 0x00000000 +#define DDRSS0_CTL_218_DATA 0x00000000 +#define DDRSS0_CTL_219_DATA 0x00000000 +#define DDRSS0_CTL_220_DATA 0x00000000 +#define DDRSS0_CTL_221_DATA 0x00000000 +#define DDRSS0_CTL_222_DATA 0x00001000 +#define DDRSS0_CTL_223_DATA 0x006403E8 +#define DDRSS0_CTL_224_DATA 0x00000000 +#define DDRSS0_CTL_225_DATA 0x00000000 +#define DDRSS0_CTL_226_DATA 0x00000000 +#define DDRSS0_CTL_227_DATA 0x15110000 +#define DDRSS0_CTL_228_DATA 0x00040C18 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 +#define DDRSS0_CTL_231_DATA 0x00000000 +#define DDRSS0_CTL_232_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 +#define DDRSS0_CTL_235_DATA 0x00000000 +#define DDRSS0_CTL_236_DATA 0x00000000 +#define DDRSS0_CTL_237_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 +#define DDRSS0_CTL_240_DATA 0x00000000 +#define DDRSS0_CTL_241_DATA 0x00000000 +#define DDRSS0_CTL_242_DATA 0x00030000 +#define DDRSS0_CTL_243_DATA 0x00000000 +#define DDRSS0_CTL_244_DATA 0x00000000 +#define DDRSS0_CTL_245_DATA 0x00000000 +#define DDRSS0_CTL_246_DATA 0x00000000 +#define DDRSS0_CTL_247_DATA 0x00000000 +#define DDRSS0_CTL_248_DATA 0x00000000 +#define DDRSS0_CTL_249_DATA 0x00000000 +#define DDRSS0_CTL_250_DATA 0x00000000 +#define DDRSS0_CTL_251_DATA 0x00000000 +#define DDRSS0_CTL_252_DATA 0x00000000 +#define DDRSS0_CTL_253_DATA 0x00000000 +#define DDRSS0_CTL_254_DATA 0x00000000 +#define DDRSS0_CTL_255_DATA 0x00000000 +#define DDRSS0_CTL_256_DATA 0x00000000 +#define DDRSS0_CTL_257_DATA 0x01000200 +#define DDRSS0_CTL_258_DATA 0x00370040 +#define DDRSS0_CTL_259_DATA 0x00020008 +#define DDRSS0_CTL_260_DATA 0x00400100 +#define DDRSS0_CTL_261_DATA 0x00400855 +#define DDRSS0_CTL_262_DATA 0x01000200 +#define DDRSS0_CTL_263_DATA 0x08550040 +#define DDRSS0_CTL_264_DATA 0x00000040 +#define DDRSS0_CTL_265_DATA 0x006B0003 +#define DDRSS0_CTL_266_DATA 0x0100006B +#define DDRSS0_CTL_267_DATA 0x03030303 +#define DDRSS0_CTL_268_DATA 0x00000000 +#define DDRSS0_CTL_269_DATA 0x00000202 +#define DDRSS0_CTL_270_DATA 0x00001FFF +#define DDRSS0_CTL_271_DATA 0x3FFF2000 +#define DDRSS0_CTL_272_DATA 0x03FF0000 +#define DDRSS0_CTL_273_DATA 0x000103FF +#define DDRSS0_CTL_274_DATA 0x0FFF0B00 +#define DDRSS0_CTL_275_DATA 0x01010001 +#define DDRSS0_CTL_276_DATA 0x01010101 +#define DDRSS0_CTL_277_DATA 0x01180101 +#define DDRSS0_CTL_278_DATA 0x00030000 +#define DDRSS0_CTL_279_DATA 0x00000000 +#define DDRSS0_CTL_280_DATA 0x00000000 +#define DDRSS0_CTL_281_DATA 0x00000000 +#define DDRSS0_CTL_282_DATA 0x00000000 +#define DDRSS0_CTL_283_DATA 0x00000000 +#define DDRSS0_CTL_284_DATA 0x00000000 +#define DDRSS0_CTL_285_DATA 0x00000000 +#define DDRSS0_CTL_286_DATA 0x00040101 +#define DDRSS0_CTL_287_DATA 0x04010100 +#define DDRSS0_CTL_288_DATA 0x00000000 +#define DDRSS0_CTL_289_DATA 0x00000000 +#define DDRSS0_CTL_290_DATA 0x03030300 +#define DDRSS0_CTL_291_DATA 0x00010101 +#define DDRSS0_CTL_292_DATA 0x00000000 +#define DDRSS0_CTL_293_DATA 0x00000000 +#define DDRSS0_CTL_294_DATA 0x00000000 +#define DDRSS0_CTL_295_DATA 0x00000000 +#define DDRSS0_CTL_296_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF +#define DDRSS0_CTL_299_DATA 0x00000000 +#define DDRSS0_CTL_300_DATA 0x00000000 +#define DDRSS0_CTL_301_DATA 0x00000000 +#define DDRSS0_CTL_302_DATA 0x00000000 +#define DDRSS0_CTL_303_DATA 0x00000000 +#define DDRSS0_CTL_304_DATA 0x00000000 +#define DDRSS0_CTL_305_DATA 0x00000000 +#define DDRSS0_CTL_306_DATA 0x00000000 +#define DDRSS0_CTL_307_DATA 0x00000000 +#define DDRSS0_CTL_308_DATA 0x00000000 +#define DDRSS0_CTL_309_DATA 0x00000000 +#define DDRSS0_CTL_310_DATA 0x00000000 +#define DDRSS0_CTL_311_DATA 0x00000000 +#define DDRSS0_CTL_312_DATA 0x00000000 +#define DDRSS0_CTL_313_DATA 0x01000000 +#define DDRSS0_CTL_314_DATA 0x00020201 +#define DDRSS0_CTL_315_DATA 0x01000101 +#define DDRSS0_CTL_316_DATA 0x01010001 +#define DDRSS0_CTL_317_DATA 0x00010101 +#define DDRSS0_CTL_318_DATA 0x050A0A03 +#define DDRSS0_CTL_319_DATA 0x10082323 +#define DDRSS0_CTL_320_DATA 0x00090310 +#define DDRSS0_CTL_321_DATA 0x0B0C030F +#define DDRSS0_CTL_322_DATA 0x0B0C0306 +#define DDRSS0_CTL_323_DATA 0x0C090006 +#define DDRSS0_CTL_324_DATA 0x0100000C +#define DDRSS0_CTL_325_DATA 0x08040801 +#define DDRSS0_CTL_326_DATA 0x00000004 +#define DDRSS0_CTL_327_DATA 0x00000000 +#define DDRSS0_CTL_328_DATA 0x00010000 +#define DDRSS0_CTL_329_DATA 0x00280D00 +#define DDRSS0_CTL_330_DATA 0x00000001 +#define DDRSS0_CTL_331_DATA 0x00030001 +#define DDRSS0_CTL_332_DATA 0x00000000 +#define DDRSS0_CTL_333_DATA 0x00000000 +#define DDRSS0_CTL_334_DATA 0x00000000 +#define DDRSS0_CTL_335_DATA 0x00000000 +#define DDRSS0_CTL_336_DATA 0x00000000 +#define DDRSS0_CTL_337_DATA 0x00000000 +#define DDRSS0_CTL_338_DATA 0x00000000 +#define DDRSS0_CTL_339_DATA 0x00000000 +#define DDRSS0_CTL_340_DATA 0x01000000 +#define DDRSS0_CTL_341_DATA 0x00000001 +#define DDRSS0_CTL_342_DATA 0x00010100 +#define DDRSS0_CTL_343_DATA 0x03030000 +#define DDRSS0_CTL_344_DATA 0x00000000 +#define DDRSS0_CTL_345_DATA 0x00000000 +#define DDRSS0_CTL_346_DATA 0x00000000 +#define DDRSS0_CTL_347_DATA 0x00000000 +#define DDRSS0_CTL_348_DATA 0x00000000 +#define DDRSS0_CTL_349_DATA 0x00000000 +#define DDRSS0_CTL_350_DATA 0x00000000 +#define DDRSS0_CTL_351_DATA 0x00000000 +#define DDRSS0_CTL_352_DATA 0x00000000 +#define DDRSS0_CTL_353_DATA 0x00000000 +#define DDRSS0_CTL_354_DATA 0x00000000 +#define DDRSS0_CTL_355_DATA 0x00000000 +#define DDRSS0_CTL_356_DATA 0x00000000 +#define DDRSS0_CTL_357_DATA 0x00000000 +#define DDRSS0_CTL_358_DATA 0x00000000 +#define DDRSS0_CTL_359_DATA 0x00000000 +#define DDRSS0_CTL_360_DATA 0x000556AA +#define DDRSS0_CTL_361_DATA 0x000AAAAA +#define DDRSS0_CTL_362_DATA 0x000AA955 +#define DDRSS0_CTL_363_DATA 0x00055555 +#define DDRSS0_CTL_364_DATA 0x000B3133 +#define DDRSS0_CTL_365_DATA 0x0004CD33 +#define DDRSS0_CTL_366_DATA 0x0004CECC +#define DDRSS0_CTL_367_DATA 0x000B32CC +#define DDRSS0_CTL_368_DATA 0x00010300 +#define DDRSS0_CTL_369_DATA 0x03000100 +#define DDRSS0_CTL_370_DATA 0x00000000 +#define DDRSS0_CTL_371_DATA 0x00000000 +#define DDRSS0_CTL_372_DATA 0x00000000 +#define DDRSS0_CTL_373_DATA 0x00000000 +#define DDRSS0_CTL_374_DATA 0x00000000 +#define DDRSS0_CTL_375_DATA 0x00000000 +#define DDRSS0_CTL_376_DATA 0x00000000 +#define DDRSS0_CTL_377_DATA 0x00010000 +#define DDRSS0_CTL_378_DATA 0x00000404 +#define DDRSS0_CTL_379_DATA 0x00000000 +#define DDRSS0_CTL_380_DATA 0x00000000 +#define DDRSS0_CTL_381_DATA 0x00000000 +#define DDRSS0_CTL_382_DATA 0x00000000 +#define DDRSS0_CTL_383_DATA 0x00000000 +#define DDRSS0_CTL_384_DATA 0x00000000 +#define DDRSS0_CTL_385_DATA 0x00000000 +#define DDRSS0_CTL_386_DATA 0x00000000 +#define DDRSS0_CTL_387_DATA 0x3A3A1B00 +#define DDRSS0_CTL_388_DATA 0x000A0000 +#define DDRSS0_CTL_389_DATA 0x000000C6 +#define DDRSS0_CTL_390_DATA 0x00000200 +#define DDRSS0_CTL_391_DATA 0x00000200 +#define DDRSS0_CTL_392_DATA 0x00000200 +#define DDRSS0_CTL_393_DATA 0x00000200 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC +#define DDRSS0_CTL_396_DATA 0x00000204 +#define DDRSS0_CTL_397_DATA 0x0000206A +#define DDRSS0_CTL_398_DATA 0x00000200 +#define DDRSS0_CTL_399_DATA 0x00000200 +#define DDRSS0_CTL_400_DATA 0x00000200 +#define DDRSS0_CTL_401_DATA 0x00000200 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A +#define DDRSS0_CTL_406_DATA 0x00000200 +#define DDRSS0_CTL_407_DATA 0x00000200 +#define DDRSS0_CTL_408_DATA 0x00000200 +#define DDRSS0_CTL_409_DATA 0x00000200 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 +#define DDRSS0_CTL_413_DATA 0x03030202 +#define DDRSS0_CTL_414_DATA 0x00000022 +#define DDRSS0_CTL_415_DATA 0x00000000 +#define DDRSS0_CTL_416_DATA 0x00000000 +#define DDRSS0_CTL_417_DATA 0x00001403 +#define DDRSS0_CTL_418_DATA 0x000007D0 +#define DDRSS0_CTL_419_DATA 0x00000000 +#define DDRSS0_CTL_420_DATA 0x00000000 +#define DDRSS0_CTL_421_DATA 0x00030000 +#define DDRSS0_CTL_422_DATA 0x0007001F +#define DDRSS0_CTL_423_DATA 0x001B0033 +#define DDRSS0_CTL_424_DATA 0x001B0033 +#define DDRSS0_CTL_425_DATA 0x00000000 +#define DDRSS0_CTL_426_DATA 0x00000000 +#define DDRSS0_CTL_427_DATA 0x02000000 +#define DDRSS0_CTL_428_DATA 0x01000404 +#define DDRSS0_CTL_429_DATA 0x0B220B22 +#define DDRSS0_CTL_430_DATA 0x00000105 +#define DDRSS0_CTL_431_DATA 0x00010101 +#define DDRSS0_CTL_432_DATA 0x00010101 +#define DDRSS0_CTL_433_DATA 0x00010001 +#define DDRSS0_CTL_434_DATA 0x00000101 +#define DDRSS0_CTL_435_DATA 0x02000201 +#define DDRSS0_CTL_436_DATA 0x02010000 +#define DDRSS0_CTL_437_DATA 0x00000200 +#define DDRSS0_CTL_438_DATA 0x28060000 +#define DDRSS0_CTL_439_DATA 0x00000128 +#define DDRSS0_CTL_440_DATA 0xFFFFFFFF +#define DDRSS0_CTL_441_DATA 0xFFFFFFFF +#define DDRSS0_CTL_442_DATA 0x00000000 +#define DDRSS0_CTL_443_DATA 0x00000000 +#define DDRSS0_CTL_444_DATA 0x00000000 +#define DDRSS0_CTL_445_DATA 0x00000000 +#define DDRSS0_CTL_446_DATA 0x00000000 +#define DDRSS0_CTL_447_DATA 0x00000000 +#define DDRSS0_CTL_448_DATA 0x00000000 +#define DDRSS0_CTL_449_DATA 0x00000000 +#define DDRSS0_CTL_450_DATA 0x00000000 +#define DDRSS0_CTL_451_DATA 0x00000000 +#define DDRSS0_CTL_452_DATA 0x00000000 +#define DDRSS0_CTL_453_DATA 0x00000000 +#define DDRSS0_CTL_454_DATA 0x00000000 +#define DDRSS0_CTL_455_DATA 0x00000000 +#define DDRSS0_CTL_456_DATA 0x00000000 +#define DDRSS0_CTL_457_DATA 0x00000000 +#define DDRSS0_CTL_458_DATA 0x00000000 + +#define DDRSS0_PI_00_DATA 0x00000B00 +#define DDRSS0_PI_01_DATA 0x00000000 +#define DDRSS0_PI_02_DATA 0x00000000 +#define DDRSS0_PI_03_DATA 0x00000000 +#define DDRSS0_PI_04_DATA 0x00000000 +#define DDRSS0_PI_05_DATA 0x00000101 +#define DDRSS0_PI_06_DATA 0x00640000 +#define DDRSS0_PI_07_DATA 0x00000001 +#define DDRSS0_PI_08_DATA 0x00000000 +#define DDRSS0_PI_09_DATA 0x00000000 +#define DDRSS0_PI_10_DATA 0x00000000 +#define DDRSS0_PI_11_DATA 0x00000000 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 +#define DDRSS0_PI_14_DATA 0x0800000F +#define DDRSS0_PI_15_DATA 0x00000103 +#define DDRSS0_PI_16_DATA 0x00000005 +#define DDRSS0_PI_17_DATA 0x00000000 +#define DDRSS0_PI_18_DATA 0x00000000 +#define DDRSS0_PI_19_DATA 0x00000000 +#define DDRSS0_PI_20_DATA 0x00000000 +#define DDRSS0_PI_21_DATA 0x00000000 +#define DDRSS0_PI_22_DATA 0x00000000 +#define DDRSS0_PI_23_DATA 0x00000000 +#define DDRSS0_PI_24_DATA 0x00000000 +#define DDRSS0_PI_25_DATA 0x00000000 +#define DDRSS0_PI_26_DATA 0x00010100 +#define DDRSS0_PI_27_DATA 0x00280A00 +#define DDRSS0_PI_28_DATA 0x00000000 +#define DDRSS0_PI_29_DATA 0x0F000000 +#define DDRSS0_PI_30_DATA 0x00003200 +#define DDRSS0_PI_31_DATA 0x00000000 +#define DDRSS0_PI_32_DATA 0x00000000 +#define DDRSS0_PI_33_DATA 0x01010102 +#define DDRSS0_PI_34_DATA 0x00000000 +#define DDRSS0_PI_35_DATA 0x000000AA +#define DDRSS0_PI_36_DATA 0x00000055 +#define DDRSS0_PI_37_DATA 0x000000B5 +#define DDRSS0_PI_38_DATA 0x0000004A +#define DDRSS0_PI_39_DATA 0x00000056 +#define DDRSS0_PI_40_DATA 0x000000A9 +#define DDRSS0_PI_41_DATA 0x000000A9 +#define DDRSS0_PI_42_DATA 0x000000B5 +#define DDRSS0_PI_43_DATA 0x00000000 +#define DDRSS0_PI_44_DATA 0x00000000 +#define DDRSS0_PI_45_DATA 0x000F0F00 +#define DDRSS0_PI_46_DATA 0x0000001B +#define DDRSS0_PI_47_DATA 0x000007D0 +#define DDRSS0_PI_48_DATA 0x00000300 +#define DDRSS0_PI_49_DATA 0x00000000 +#define DDRSS0_PI_50_DATA 0x00000000 +#define DDRSS0_PI_51_DATA 0x01000000 +#define DDRSS0_PI_52_DATA 0x00010101 +#define DDRSS0_PI_53_DATA 0x00000000 +#define DDRSS0_PI_54_DATA 0x00030000 +#define DDRSS0_PI_55_DATA 0x0F000000 +#define DDRSS0_PI_56_DATA 0x00000017 +#define DDRSS0_PI_57_DATA 0x00000000 +#define DDRSS0_PI_58_DATA 0x00000000 +#define DDRSS0_PI_59_DATA 0x00000000 +#define DDRSS0_PI_60_DATA 0x0A0A140A +#define DDRSS0_PI_61_DATA 0x10020201 +#define DDRSS0_PI_62_DATA 0x00020805 +#define DDRSS0_PI_63_DATA 0x01000404 +#define DDRSS0_PI_64_DATA 0x00000000 +#define DDRSS0_PI_65_DATA 0x00000000 +#define DDRSS0_PI_66_DATA 0x00000100 +#define DDRSS0_PI_67_DATA 0x0002020F +#define DDRSS0_PI_68_DATA 0x00340000 +#define DDRSS0_PI_69_DATA 0x00000000 +#define DDRSS0_PI_70_DATA 0x00000000 +#define DDRSS0_PI_71_DATA 0x0000FFFF +#define DDRSS0_PI_72_DATA 0x01000000 +#define DDRSS0_PI_73_DATA 0x00080000 +#define DDRSS0_PI_74_DATA 0x02000200 +#define DDRSS0_PI_75_DATA 0x01000100 +#define DDRSS0_PI_76_DATA 0x01000000 +#define DDRSS0_PI_77_DATA 0x02000200 +#define DDRSS0_PI_78_DATA 0x00000200 +#define DDRSS0_PI_79_DATA 0x00000000 +#define DDRSS0_PI_80_DATA 0x00000000 +#define DDRSS0_PI_81_DATA 0x00000000 +#define DDRSS0_PI_82_DATA 0x00000000 +#define DDRSS0_PI_83_DATA 0x00000000 +#define DDRSS0_PI_84_DATA 0x00000000 +#define DDRSS0_PI_85_DATA 0x00000000 +#define DDRSS0_PI_86_DATA 0x00000000 +#define DDRSS0_PI_87_DATA 0x00000000 +#define DDRSS0_PI_88_DATA 0x00000000 +#define DDRSS0_PI_89_DATA 0x00000000 +#define DDRSS0_PI_90_DATA 0x00000000 +#define DDRSS0_PI_91_DATA 0x00000400 +#define DDRSS0_PI_92_DATA 0x02010000 +#define DDRSS0_PI_93_DATA 0x00080003 +#define DDRSS0_PI_94_DATA 0x00080000 +#define DDRSS0_PI_95_DATA 0x00000001 +#define DDRSS0_PI_96_DATA 0x00000000 +#define DDRSS0_PI_97_DATA 0x0000AA00 +#define DDRSS0_PI_98_DATA 0x00000000 +#define DDRSS0_PI_99_DATA 0x00000000 +#define DDRSS0_PI_100_DATA 0x00010000 +#define DDRSS0_PI_101_DATA 0x00000000 +#define DDRSS0_PI_102_DATA 0x00000000 +#define DDRSS0_PI_103_DATA 0x00000000 +#define DDRSS0_PI_104_DATA 0x00000000 +#define DDRSS0_PI_105_DATA 0x00000000 +#define DDRSS0_PI_106_DATA 0x00000000 +#define DDRSS0_PI_107_DATA 0x00000000 +#define DDRSS0_PI_108_DATA 0x00000000 +#define DDRSS0_PI_109_DATA 0x00000000 +#define DDRSS0_PI_110_DATA 0x00000000 +#define DDRSS0_PI_111_DATA 0x00000000 +#define DDRSS0_PI_112_DATA 0x00000000 +#define DDRSS0_PI_113_DATA 0x00000000 +#define DDRSS0_PI_114_DATA 0x00000000 +#define DDRSS0_PI_115_DATA 0x00000000 +#define DDRSS0_PI_116_DATA 0x00000000 +#define DDRSS0_PI_117_DATA 0x00000000 +#define DDRSS0_PI_118_DATA 0x00000000 +#define DDRSS0_PI_119_DATA 0x00000000 +#define DDRSS0_PI_120_DATA 0x00000000 +#define DDRSS0_PI_121_DATA 0x00000000 +#define DDRSS0_PI_122_DATA 0x00000000 +#define DDRSS0_PI_123_DATA 0x00000000 +#define DDRSS0_PI_124_DATA 0x00000000 +#define DDRSS0_PI_125_DATA 0x00000008 +#define DDRSS0_PI_126_DATA 0x00000000 +#define DDRSS0_PI_127_DATA 0x00000000 +#define DDRSS0_PI_128_DATA 0x00000000 +#define DDRSS0_PI_129_DATA 0x00000000 +#define DDRSS0_PI_130_DATA 0x00000000 +#define DDRSS0_PI_131_DATA 0x00000000 +#define DDRSS0_PI_132_DATA 0x00000000 +#define DDRSS0_PI_133_DATA 0x00000000 +#define DDRSS0_PI_134_DATA 0x00000002 +#define DDRSS0_PI_135_DATA 0x00000000 +#define DDRSS0_PI_136_DATA 0x00000000 +#define DDRSS0_PI_137_DATA 0x0000000A +#define DDRSS0_PI_138_DATA 0x00000019 +#define DDRSS0_PI_139_DATA 0x00000100 +#define DDRSS0_PI_140_DATA 0x00000000 +#define DDRSS0_PI_141_DATA 0x00000000 +#define DDRSS0_PI_142_DATA 0x00000000 +#define DDRSS0_PI_143_DATA 0x00000000 +#define DDRSS0_PI_144_DATA 0x01000000 +#define DDRSS0_PI_145_DATA 0x00010003 +#define DDRSS0_PI_146_DATA 0x02000101 +#define DDRSS0_PI_147_DATA 0x01030001 +#define DDRSS0_PI_148_DATA 0x00010400 +#define DDRSS0_PI_149_DATA 0x06000105 +#define DDRSS0_PI_150_DATA 0x01070001 +#define DDRSS0_PI_151_DATA 0x00000000 +#define DDRSS0_PI_152_DATA 0x00000000 +#define DDRSS0_PI_153_DATA 0x00000000 +#define DDRSS0_PI_154_DATA 0x00010001 +#define DDRSS0_PI_155_DATA 0x00000000 +#define DDRSS0_PI_156_DATA 0x00000000 +#define DDRSS0_PI_157_DATA 0x00000000 +#define DDRSS0_PI_158_DATA 0x00000000 +#define DDRSS0_PI_159_DATA 0x00000401 +#define DDRSS0_PI_160_DATA 0x00000000 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 +#define DDRSS0_PI_164_DATA 0x00000034 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 +#define DDRSS0_PI_167_DATA 0x02000200 +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 +#define DDRSS0_PI_171_DATA 0x0000032B +#define DDRSS0_PI_172_DATA 0x00001035 +#define DDRSS0_PI_173_DATA 0x0000032B +#define DDRSS0_PI_174_DATA 0x04001035 +#define DDRSS0_PI_175_DATA 0x01010404 +#define DDRSS0_PI_176_DATA 0x00001500 +#define DDRSS0_PI_177_DATA 0x00150015 +#define DDRSS0_PI_178_DATA 0x01000100 +#define DDRSS0_PI_179_DATA 0x00000100 +#define DDRSS0_PI_180_DATA 0x00000000 +#define DDRSS0_PI_181_DATA 0x01010101 +#define DDRSS0_PI_182_DATA 0x00000000 +#define DDRSS0_PI_183_DATA 0x00000000 +#define DDRSS0_PI_184_DATA 0x00000000 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 +#define DDRSS0_PI_187_DATA 0x00040402 +#define DDRSS0_PI_188_DATA 0x000D0035 +#define DDRSS0_PI_189_DATA 0x00218049 +#define DDRSS0_PI_190_DATA 0x00218049 +#define DDRSS0_PI_191_DATA 0x01000101 +#define DDRSS0_PI_192_DATA 0x0004000E +#define DDRSS0_PI_193_DATA 0x00040216 +#define DDRSS0_PI_194_DATA 0x01000216 +#define DDRSS0_PI_195_DATA 0x000F000F +#define DDRSS0_PI_196_DATA 0x02170100 +#define DDRSS0_PI_197_DATA 0x01000217 +#define DDRSS0_PI_198_DATA 0x02170217 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B +#define DDRSS0_PI_201_DATA 0x0A070601 +#define DDRSS0_PI_202_DATA 0x1F130A0D +#define DDRSS0_PI_203_DATA 0x1F130A14 +#define DDRSS0_PI_204_DATA 0x0000C014 +#define DDRSS0_PI_205_DATA 0x00C01000 +#define DDRSS0_PI_206_DATA 0x00C01000 +#define DDRSS0_PI_207_DATA 0x00021000 +#define DDRSS0_PI_208_DATA 0x0024000E +#define DDRSS0_PI_209_DATA 0x00240216 +#define DDRSS0_PI_210_DATA 0x00110216 +#define DDRSS0_PI_211_DATA 0x32000056 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 +#define DDRSS0_PI_214_DATA 0x03013212 +#define DDRSS0_PI_215_DATA 0x00003600 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 +#define DDRSS0_PI_220_DATA 0x0A032001 +#define DDRSS0_PI_221_DATA 0x2C31110A +#define DDRSS0_PI_222_DATA 0x00002918 +#define DDRSS0_PI_223_DATA 0x6000838E +#define DDRSS0_PI_224_DATA 0x1E202008 +#define DDRSS0_PI_225_DATA 0x2C311116 +#define DDRSS0_PI_226_DATA 0x00002918 +#define DDRSS0_PI_227_DATA 0x6000838E +#define DDRSS0_PI_228_DATA 0x1E202008 +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 +#define DDRSS0_PI_235_DATA 0x033B0016 +#define DDRSS0_PI_236_DATA 0x0303033B +#define DDRSS0_PI_237_DATA 0x002AF803 +#define DDRSS0_PI_238_DATA 0x0001ADAF +#define DDRSS0_PI_239_DATA 0x00000005 +#define DDRSS0_PI_240_DATA 0x0000006E +#define DDRSS0_PI_241_DATA 0x00000016 +#define DDRSS0_PI_242_DATA 0x000681C8 +#define DDRSS0_PI_243_DATA 0x0001ADAF +#define DDRSS0_PI_244_DATA 0x00000005 +#define DDRSS0_PI_245_DATA 0x000010A9 +#define DDRSS0_PI_246_DATA 0x0000033B +#define DDRSS0_PI_247_DATA 0x000681C8 +#define DDRSS0_PI_248_DATA 0x0001ADAF +#define DDRSS0_PI_249_DATA 0x00000005 +#define DDRSS0_PI_250_DATA 0x000010A9 +#define DDRSS0_PI_251_DATA 0x0100033B +#define DDRSS0_PI_252_DATA 0x00370040 +#define DDRSS0_PI_253_DATA 0x00010008 +#define DDRSS0_PI_254_DATA 0x08550040 +#define DDRSS0_PI_255_DATA 0x00010040 +#define DDRSS0_PI_256_DATA 0x08550040 +#define DDRSS0_PI_257_DATA 0x00000340 +#define DDRSS0_PI_258_DATA 0x006B006B +#define DDRSS0_PI_259_DATA 0x08040404 +#define DDRSS0_PI_260_DATA 0x00000055 +#define DDRSS0_PI_261_DATA 0x55083C5A +#define DDRSS0_PI_262_DATA 0x5A000000 +#define DDRSS0_PI_263_DATA 0x0055083C +#define DDRSS0_PI_264_DATA 0x3C5A0000 +#define DDRSS0_PI_265_DATA 0x00005508 +#define DDRSS0_PI_266_DATA 0x0C3C5A00 +#define DDRSS0_PI_267_DATA 0x080F0E0D +#define DDRSS0_PI_268_DATA 0x000B0A09 +#define DDRSS0_PI_269_DATA 0x00030201 +#define DDRSS0_PI_270_DATA 0x01000000 +#define DDRSS0_PI_271_DATA 0x04020201 +#define DDRSS0_PI_272_DATA 0x00080804 +#define DDRSS0_PI_273_DATA 0x00000000 +#define DDRSS0_PI_274_DATA 0x00000000 +#define DDRSS0_PI_275_DATA 0x00F30084 +#define DDRSS0_PI_276_DATA 0x00160000 +#define DDRSS0_PI_277_DATA 0x35F33FF4 +#define DDRSS0_PI_278_DATA 0x00160F27 +#define DDRSS0_PI_279_DATA 0x35F33FF4 +#define DDRSS0_PI_280_DATA 0x00160F27 +#define DDRSS0_PI_281_DATA 0x00F30084 +#define DDRSS0_PI_282_DATA 0x00160000 +#define DDRSS0_PI_283_DATA 0x35F33FF4 +#define DDRSS0_PI_284_DATA 0x00160F27 +#define DDRSS0_PI_285_DATA 0x35F33FF4 +#define DDRSS0_PI_286_DATA 0x00160F27 +#define DDRSS0_PI_287_DATA 0x00F30084 +#define DDRSS0_PI_288_DATA 0x00160000 +#define DDRSS0_PI_289_DATA 0x35F33FF4 +#define DDRSS0_PI_290_DATA 0x00160F27 +#define DDRSS0_PI_291_DATA 0x35F33FF4 +#define DDRSS0_PI_292_DATA 0x00160F27 +#define DDRSS0_PI_293_DATA 0x00F30084 +#define DDRSS0_PI_294_DATA 0x00160000 +#define DDRSS0_PI_295_DATA 0x35F33FF4 +#define DDRSS0_PI_296_DATA 0x00160F27 +#define DDRSS0_PI_297_DATA 0x35F33FF4 +#define DDRSS0_PI_298_DATA 0x00160F27 +#define DDRSS0_PI_299_DATA 0x00000000 + +#define DDRSS0_PHY_00_DATA 0x000004F0 +#define DDRSS0_PHY_01_DATA 0x00000000 +#define DDRSS0_PHY_02_DATA 0x00030200 +#define DDRSS0_PHY_03_DATA 0x00000000 +#define DDRSS0_PHY_04_DATA 0x00000000 +#define DDRSS0_PHY_05_DATA 0x01030000 +#define DDRSS0_PHY_06_DATA 0x00010000 +#define DDRSS0_PHY_07_DATA 0x01030004 +#define DDRSS0_PHY_08_DATA 0x01000000 +#define DDRSS0_PHY_09_DATA 0x00000000 +#define DDRSS0_PHY_10_DATA 0x00000000 +#define DDRSS0_PHY_11_DATA 0x01000001 +#define DDRSS0_PHY_12_DATA 0x00000200 +#define DDRSS0_PHY_13_DATA 0x000800C0 +#define DDRSS0_PHY_14_DATA 0x060100CC +#define DDRSS0_PHY_15_DATA 0x00030066 +#define DDRSS0_PHY_16_DATA 0x00000000 +#define DDRSS0_PHY_17_DATA 0x00000301 +#define DDRSS0_PHY_18_DATA 0x0000AAAA +#define DDRSS0_PHY_19_DATA 0x00005555 +#define DDRSS0_PHY_20_DATA 0x0000B5B5 +#define DDRSS0_PHY_21_DATA 0x00004A4A +#define DDRSS0_PHY_22_DATA 0x00005656 +#define DDRSS0_PHY_23_DATA 0x0000A9A9 +#define DDRSS0_PHY_24_DATA 0x0000A9A9 +#define DDRSS0_PHY_25_DATA 0x0000B5B5 +#define DDRSS0_PHY_26_DATA 0x00000000 +#define DDRSS0_PHY_27_DATA 0x00000000 +#define DDRSS0_PHY_28_DATA 0x2A000000 +#define DDRSS0_PHY_29_DATA 0x00000808 +#define DDRSS0_PHY_30_DATA 0x0F000000 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002006 +#define DDRSS0_PHY_34_DATA 0x00000000 +#define DDRSS0_PHY_35_DATA 0x00000000 +#define DDRSS0_PHY_36_DATA 0x55555555 +#define DDRSS0_PHY_37_DATA 0xAAAAAAAA +#define DDRSS0_PHY_38_DATA 0x55555555 +#define DDRSS0_PHY_39_DATA 0xAAAAAAAA +#define DDRSS0_PHY_40_DATA 0x00005555 +#define DDRSS0_PHY_41_DATA 0x01000100 +#define DDRSS0_PHY_42_DATA 0x00800180 +#define DDRSS0_PHY_43_DATA 0x00000001 +#define DDRSS0_PHY_44_DATA 0x00000000 +#define DDRSS0_PHY_45_DATA 0x00000000 +#define DDRSS0_PHY_46_DATA 0x00000000 +#define DDRSS0_PHY_47_DATA 0x00000000 +#define DDRSS0_PHY_48_DATA 0x00000000 +#define DDRSS0_PHY_49_DATA 0x00000000 +#define DDRSS0_PHY_50_DATA 0x00000000 +#define DDRSS0_PHY_51_DATA 0x00000000 +#define DDRSS0_PHY_52_DATA 0x00000000 +#define DDRSS0_PHY_53_DATA 0x00000000 +#define DDRSS0_PHY_54_DATA 0x00000000 +#define DDRSS0_PHY_55_DATA 0x00000000 +#define DDRSS0_PHY_56_DATA 0x00000000 +#define DDRSS0_PHY_57_DATA 0x00000000 +#define DDRSS0_PHY_58_DATA 0x00000000 +#define DDRSS0_PHY_59_DATA 0x00000000 +#define DDRSS0_PHY_60_DATA 0x00000000 +#define DDRSS0_PHY_61_DATA 0x00000000 +#define DDRSS0_PHY_62_DATA 0x00000000 +#define DDRSS0_PHY_63_DATA 0x00000000 +#define DDRSS0_PHY_64_DATA 0x00000000 +#define DDRSS0_PHY_65_DATA 0x00000000 +#define DDRSS0_PHY_66_DATA 0x00000104 +#define DDRSS0_PHY_67_DATA 0x00000120 +#define DDRSS0_PHY_68_DATA 0x00000000 +#define DDRSS0_PHY_69_DATA 0x00000000 +#define DDRSS0_PHY_70_DATA 0x00000000 +#define DDRSS0_PHY_71_DATA 0x00000000 +#define DDRSS0_PHY_72_DATA 0x00000000 +#define DDRSS0_PHY_73_DATA 0x00000000 +#define DDRSS0_PHY_74_DATA 0x00000000 +#define DDRSS0_PHY_75_DATA 0x00000001 +#define DDRSS0_PHY_76_DATA 0x07FF0000 +#define DDRSS0_PHY_77_DATA 0x0080081F +#define DDRSS0_PHY_78_DATA 0x00081020 +#define DDRSS0_PHY_79_DATA 0x04010000 +#define DDRSS0_PHY_80_DATA 0x00000000 +#define DDRSS0_PHY_81_DATA 0x00000000 +#define DDRSS0_PHY_82_DATA 0x00000000 +#define DDRSS0_PHY_83_DATA 0x00000100 +#define DDRSS0_PHY_84_DATA 0x01CC0C01 +#define DDRSS0_PHY_85_DATA 0x1003CC0C +#define DDRSS0_PHY_86_DATA 0x20000140 +#define DDRSS0_PHY_87_DATA 0x07FF0200 +#define DDRSS0_PHY_88_DATA 0x0000DD01 +#define DDRSS0_PHY_89_DATA 0x10100303 +#define DDRSS0_PHY_90_DATA 0x10101010 +#define DDRSS0_PHY_91_DATA 0x10101010 +#define DDRSS0_PHY_92_DATA 0x00021010 +#define DDRSS0_PHY_93_DATA 0x00100010 +#define DDRSS0_PHY_94_DATA 0x00100010 +#define DDRSS0_PHY_95_DATA 0x00100010 +#define DDRSS0_PHY_96_DATA 0x00100010 +#define DDRSS0_PHY_97_DATA 0x00050010 +#define DDRSS0_PHY_98_DATA 0x51517041 +#define DDRSS0_PHY_99_DATA 0x31C06001 +#define DDRSS0_PHY_100_DATA 0x07AB01AB +#define DDRSS0_PHY_101_DATA 0x00C0C001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 +#define DDRSS0_PHY_103_DATA 0x10001000 +#define DDRSS0_PHY_104_DATA 0x0C083E42 +#define DDRSS0_PHY_105_DATA 0x0F0C3701 +#define DDRSS0_PHY_106_DATA 0x01000140 +#define DDRSS0_PHY_107_DATA 0x0C000420 +#define DDRSS0_PHY_108_DATA 0x00000198 +#define DDRSS0_PHY_109_DATA 0x0A0000D0 +#define DDRSS0_PHY_110_DATA 0x00030200 +#define DDRSS0_PHY_111_DATA 0x02800000 +#define DDRSS0_PHY_112_DATA 0x80800000 +#define DDRSS0_PHY_113_DATA 0x000E2010 +#define DDRSS0_PHY_114_DATA 0x76543210 +#define DDRSS0_PHY_115_DATA 0x00000008 +#define DDRSS0_PHY_116_DATA 0x02800280 +#define DDRSS0_PHY_117_DATA 0x02800280 +#define DDRSS0_PHY_118_DATA 0x02800280 +#define DDRSS0_PHY_119_DATA 0x02800280 +#define DDRSS0_PHY_120_DATA 0x00000280 +#define DDRSS0_PHY_121_DATA 0x0000A000 +#define DDRSS0_PHY_122_DATA 0x00A000A0 +#define DDRSS0_PHY_123_DATA 0x00A000A0 +#define DDRSS0_PHY_124_DATA 0x00A000A0 +#define DDRSS0_PHY_125_DATA 0x00A000A0 +#define DDRSS0_PHY_126_DATA 0x00A000A0 +#define DDRSS0_PHY_127_DATA 0x00A000A0 +#define DDRSS0_PHY_128_DATA 0x00A000A0 +#define DDRSS0_PHY_129_DATA 0x00A000A0 +#define DDRSS0_PHY_130_DATA 0x01C200A0 +#define DDRSS0_PHY_131_DATA 0x01A00005 +#define DDRSS0_PHY_132_DATA 0x00000000 +#define DDRSS0_PHY_133_DATA 0x00000000 +#define DDRSS0_PHY_134_DATA 0x00080200 +#define DDRSS0_PHY_135_DATA 0x00000000 +#define DDRSS0_PHY_136_DATA 0x20202000 +#define DDRSS0_PHY_137_DATA 0x20202020 +#define DDRSS0_PHY_138_DATA 0xF0F02020 +#define DDRSS0_PHY_139_DATA 0x00000000 +#define DDRSS0_PHY_140_DATA 0x00000000 +#define DDRSS0_PHY_141_DATA 0x00000000 +#define DDRSS0_PHY_142_DATA 0x00000000 +#define DDRSS0_PHY_143_DATA 0x00000000 +#define DDRSS0_PHY_144_DATA 0x00000000 +#define DDRSS0_PHY_145_DATA 0x00000000 +#define DDRSS0_PHY_146_DATA 0x00000000 +#define DDRSS0_PHY_147_DATA 0x00000000 +#define DDRSS0_PHY_148_DATA 0x00000000 +#define DDRSS0_PHY_149_DATA 0x00000000 +#define DDRSS0_PHY_150_DATA 0x00000000 +#define DDRSS0_PHY_151_DATA 0x00000000 +#define DDRSS0_PHY_152_DATA 0x00000000 +#define DDRSS0_PHY_153_DATA 0x00000000 +#define DDRSS0_PHY_154_DATA 0x00000000 +#define DDRSS0_PHY_155_DATA 0x00000000 +#define DDRSS0_PHY_156_DATA 0x00000000 +#define DDRSS0_PHY_157_DATA 0x00000000 +#define DDRSS0_PHY_158_DATA 0x00000000 +#define DDRSS0_PHY_159_DATA 0x00000000 +#define DDRSS0_PHY_160_DATA 0x00000000 +#define DDRSS0_PHY_161_DATA 0x00000000 +#define DDRSS0_PHY_162_DATA 0x00000000 +#define DDRSS0_PHY_163_DATA 0x00000000 +#define DDRSS0_PHY_164_DATA 0x00000000 +#define DDRSS0_PHY_165_DATA 0x00000000 +#define DDRSS0_PHY_166_DATA 0x00000000 +#define DDRSS0_PHY_167_DATA 0x00000000 +#define DDRSS0_PHY_168_DATA 0x00000000 +#define DDRSS0_PHY_169_DATA 0x00000000 +#define DDRSS0_PHY_170_DATA 0x00000000 +#define DDRSS0_PHY_171_DATA 0x00000000 +#define DDRSS0_PHY_172_DATA 0x00000000 +#define DDRSS0_PHY_173_DATA 0x00000000 +#define DDRSS0_PHY_174_DATA 0x00000000 +#define DDRSS0_PHY_175_DATA 0x00000000 +#define DDRSS0_PHY_176_DATA 0x00000000 +#define DDRSS0_PHY_177_DATA 0x00000000 +#define DDRSS0_PHY_178_DATA 0x00000000 +#define DDRSS0_PHY_179_DATA 0x00000000 +#define DDRSS0_PHY_180_DATA 0x00000000 +#define DDRSS0_PHY_181_DATA 0x00000000 +#define DDRSS0_PHY_182_DATA 0x00000000 +#define DDRSS0_PHY_183_DATA 0x00000000 +#define DDRSS0_PHY_184_DATA 0x00000000 +#define DDRSS0_PHY_185_DATA 0x00000000 +#define DDRSS0_PHY_186_DATA 0x00000000 +#define DDRSS0_PHY_187_DATA 0x00000000 +#define DDRSS0_PHY_188_DATA 0x00000000 +#define DDRSS0_PHY_189_DATA 0x00000000 +#define DDRSS0_PHY_190_DATA 0x00000000 +#define DDRSS0_PHY_191_DATA 0x00000000 +#define DDRSS0_PHY_192_DATA 0x00000000 +#define DDRSS0_PHY_193_DATA 0x00000000 +#define DDRSS0_PHY_194_DATA 0x00000000 +#define DDRSS0_PHY_195_DATA 0x00000000 +#define DDRSS0_PHY_196_DATA 0x00000000 +#define DDRSS0_PHY_197_DATA 0x00000000 +#define DDRSS0_PHY_198_DATA 0x00000000 +#define DDRSS0_PHY_199_DATA 0x00000000 +#define DDRSS0_PHY_200_DATA 0x00000000 +#define DDRSS0_PHY_201_DATA 0x00000000 +#define DDRSS0_PHY_202_DATA 0x00000000 +#define DDRSS0_PHY_203_DATA 0x00000000 +#define DDRSS0_PHY_204_DATA 0x00000000 +#define DDRSS0_PHY_205_DATA 0x00000000 +#define DDRSS0_PHY_206_DATA 0x00000000 +#define DDRSS0_PHY_207_DATA 0x00000000 +#define DDRSS0_PHY_208_DATA 0x00000000 +#define DDRSS0_PHY_209_DATA 0x00000000 +#define DDRSS0_PHY_210_DATA 0x00000000 +#define DDRSS0_PHY_211_DATA 0x00000000 +#define DDRSS0_PHY_212_DATA 0x00000000 +#define DDRSS0_PHY_213_DATA 0x00000000 +#define DDRSS0_PHY_214_DATA 0x00000000 +#define DDRSS0_PHY_215_DATA 0x00000000 +#define DDRSS0_PHY_216_DATA 0x00000000 +#define DDRSS0_PHY_217_DATA 0x00000000 +#define DDRSS0_PHY_218_DATA 0x00000000 +#define DDRSS0_PHY_219_DATA 0x00000000 +#define DDRSS0_PHY_220_DATA 0x00000000 +#define DDRSS0_PHY_221_DATA 0x00000000 +#define DDRSS0_PHY_222_DATA 0x00000000 +#define DDRSS0_PHY_223_DATA 0x00000000 +#define DDRSS0_PHY_224_DATA 0x00000000 +#define DDRSS0_PHY_225_DATA 0x00000000 +#define DDRSS0_PHY_226_DATA 0x00000000 +#define DDRSS0_PHY_227_DATA 0x00000000 +#define DDRSS0_PHY_228_DATA 0x00000000 +#define DDRSS0_PHY_229_DATA 0x00000000 +#define DDRSS0_PHY_230_DATA 0x00000000 +#define DDRSS0_PHY_231_DATA 0x00000000 +#define DDRSS0_PHY_232_DATA 0x00000000 +#define DDRSS0_PHY_233_DATA 0x00000000 +#define DDRSS0_PHY_234_DATA 0x00000000 +#define DDRSS0_PHY_235_DATA 0x00000000 +#define DDRSS0_PHY_236_DATA 0x00000000 +#define DDRSS0_PHY_237_DATA 0x00000000 +#define DDRSS0_PHY_238_DATA 0x00000000 +#define DDRSS0_PHY_239_DATA 0x00000000 +#define DDRSS0_PHY_240_DATA 0x00000000 +#define DDRSS0_PHY_241_DATA 0x00000000 +#define DDRSS0_PHY_242_DATA 0x00000000 +#define DDRSS0_PHY_243_DATA 0x00000000 +#define DDRSS0_PHY_244_DATA 0x00000000 +#define DDRSS0_PHY_245_DATA 0x00000000 +#define DDRSS0_PHY_246_DATA 0x00000000 +#define DDRSS0_PHY_247_DATA 0x00000000 +#define DDRSS0_PHY_248_DATA 0x00000000 +#define DDRSS0_PHY_249_DATA 0x00000000 +#define DDRSS0_PHY_250_DATA 0x00000000 +#define DDRSS0_PHY_251_DATA 0x00000000 +#define DDRSS0_PHY_252_DATA 0x00000000 +#define DDRSS0_PHY_253_DATA 0x00000000 +#define DDRSS0_PHY_254_DATA 0x00000000 +#define DDRSS0_PHY_255_DATA 0x00000000 +#define DDRSS0_PHY_256_DATA 0x000004F0 +#define DDRSS0_PHY_257_DATA 0x00000000 +#define DDRSS0_PHY_258_DATA 0x00030200 +#define DDRSS0_PHY_259_DATA 0x00000000 +#define DDRSS0_PHY_260_DATA 0x00000000 +#define DDRSS0_PHY_261_DATA 0x01030000 +#define DDRSS0_PHY_262_DATA 0x00010000 +#define DDRSS0_PHY_263_DATA 0x01030004 +#define DDRSS0_PHY_264_DATA 0x01000000 +#define DDRSS0_PHY_265_DATA 0x00000000 +#define DDRSS0_PHY_266_DATA 0x00000000 +#define DDRSS0_PHY_267_DATA 0x01000001 +#define DDRSS0_PHY_268_DATA 0x00000200 +#define DDRSS0_PHY_269_DATA 0x000800C0 +#define DDRSS0_PHY_270_DATA 0x060100CC +#define DDRSS0_PHY_271_DATA 0x00030066 +#define DDRSS0_PHY_272_DATA 0x00000000 +#define DDRSS0_PHY_273_DATA 0x00000301 +#define DDRSS0_PHY_274_DATA 0x0000AAAA +#define DDRSS0_PHY_275_DATA 0x00005555 +#define DDRSS0_PHY_276_DATA 0x0000B5B5 +#define DDRSS0_PHY_277_DATA 0x00004A4A +#define DDRSS0_PHY_278_DATA 0x00005656 +#define DDRSS0_PHY_279_DATA 0x0000A9A9 +#define DDRSS0_PHY_280_DATA 0x0000A9A9 +#define DDRSS0_PHY_281_DATA 0x0000B5B5 +#define DDRSS0_PHY_282_DATA 0x00000000 +#define DDRSS0_PHY_283_DATA 0x00000000 +#define DDRSS0_PHY_284_DATA 0x2A000000 +#define DDRSS0_PHY_285_DATA 0x00000808 +#define DDRSS0_PHY_286_DATA 0x0F000000 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002006 +#define DDRSS0_PHY_290_DATA 0x00000000 +#define DDRSS0_PHY_291_DATA 0x00000000 +#define DDRSS0_PHY_292_DATA 0x55555555 +#define DDRSS0_PHY_293_DATA 0xAAAAAAAA +#define DDRSS0_PHY_294_DATA 0x55555555 +#define DDRSS0_PHY_295_DATA 0xAAAAAAAA +#define DDRSS0_PHY_296_DATA 0x00005555 +#define DDRSS0_PHY_297_DATA 0x01000100 +#define DDRSS0_PHY_298_DATA 0x00800180 +#define DDRSS0_PHY_299_DATA 0x00000000 +#define DDRSS0_PHY_300_DATA 0x00000000 +#define DDRSS0_PHY_301_DATA 0x00000000 +#define DDRSS0_PHY_302_DATA 0x00000000 +#define DDRSS0_PHY_303_DATA 0x00000000 +#define DDRSS0_PHY_304_DATA 0x00000000 +#define DDRSS0_PHY_305_DATA 0x00000000 +#define DDRSS0_PHY_306_DATA 0x00000000 +#define DDRSS0_PHY_307_DATA 0x00000000 +#define DDRSS0_PHY_308_DATA 0x00000000 +#define DDRSS0_PHY_309_DATA 0x00000000 +#define DDRSS0_PHY_310_DATA 0x00000000 +#define DDRSS0_PHY_311_DATA 0x00000000 +#define DDRSS0_PHY_312_DATA 0x00000000 +#define DDRSS0_PHY_313_DATA 0x00000000 +#define DDRSS0_PHY_314_DATA 0x00000000 +#define DDRSS0_PHY_315_DATA 0x00000000 +#define DDRSS0_PHY_316_DATA 0x00000000 +#define DDRSS0_PHY_317_DATA 0x00000000 +#define DDRSS0_PHY_318_DATA 0x00000000 +#define DDRSS0_PHY_319_DATA 0x00000000 +#define DDRSS0_PHY_320_DATA 0x00000000 +#define DDRSS0_PHY_321_DATA 0x00000000 +#define DDRSS0_PHY_322_DATA 0x00000104 +#define DDRSS0_PHY_323_DATA 0x00000120 +#define DDRSS0_PHY_324_DATA 0x00000000 +#define DDRSS0_PHY_325_DATA 0x00000000 +#define DDRSS0_PHY_326_DATA 0x00000000 +#define DDRSS0_PHY_327_DATA 0x00000000 +#define DDRSS0_PHY_328_DATA 0x00000000 +#define DDRSS0_PHY_329_DATA 0x00000000 +#define DDRSS0_PHY_330_DATA 0x00000000 +#define DDRSS0_PHY_331_DATA 0x00000001 +#define DDRSS0_PHY_332_DATA 0x07FF0000 +#define DDRSS0_PHY_333_DATA 0x0080081F +#define DDRSS0_PHY_334_DATA 0x00081020 +#define DDRSS0_PHY_335_DATA 0x04010000 +#define DDRSS0_PHY_336_DATA 0x00000000 +#define DDRSS0_PHY_337_DATA 0x00000000 +#define DDRSS0_PHY_338_DATA 0x00000000 +#define DDRSS0_PHY_339_DATA 0x00000100 +#define DDRSS0_PHY_340_DATA 0x01CC0C01 +#define DDRSS0_PHY_341_DATA 0x1003CC0C +#define DDRSS0_PHY_342_DATA 0x20000140 +#define DDRSS0_PHY_343_DATA 0x07FF0200 +#define DDRSS0_PHY_344_DATA 0x0000DD01 +#define DDRSS0_PHY_345_DATA 0x10100303 +#define DDRSS0_PHY_346_DATA 0x10101010 +#define DDRSS0_PHY_347_DATA 0x10101010 +#define DDRSS0_PHY_348_DATA 0x00021010 +#define DDRSS0_PHY_349_DATA 0x00100010 +#define DDRSS0_PHY_350_DATA 0x00100010 +#define DDRSS0_PHY_351_DATA 0x00100010 +#define DDRSS0_PHY_352_DATA 0x00100010 +#define DDRSS0_PHY_353_DATA 0x00050010 +#define DDRSS0_PHY_354_DATA 0x51517041 +#define DDRSS0_PHY_355_DATA 0x31C06001 +#define DDRSS0_PHY_356_DATA 0x07AB01AB +#define DDRSS0_PHY_357_DATA 0x00C0C001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 +#define DDRSS0_PHY_359_DATA 0x10001000 +#define DDRSS0_PHY_360_DATA 0x0C083E42 +#define DDRSS0_PHY_361_DATA 0x0F0C3701 +#define DDRSS0_PHY_362_DATA 0x01000140 +#define DDRSS0_PHY_363_DATA 0x0C000420 +#define DDRSS0_PHY_364_DATA 0x00000198 +#define DDRSS0_PHY_365_DATA 0x0A0000D0 +#define DDRSS0_PHY_366_DATA 0x00030200 +#define DDRSS0_PHY_367_DATA 0x02800000 +#define DDRSS0_PHY_368_DATA 0x80800000 +#define DDRSS0_PHY_369_DATA 0x000E2010 +#define DDRSS0_PHY_370_DATA 0x76543210 +#define DDRSS0_PHY_371_DATA 0x00000008 +#define DDRSS0_PHY_372_DATA 0x02800280 +#define DDRSS0_PHY_373_DATA 0x02800280 +#define DDRSS0_PHY_374_DATA 0x02800280 +#define DDRSS0_PHY_375_DATA 0x02800280 +#define DDRSS0_PHY_376_DATA 0x00000280 +#define DDRSS0_PHY_377_DATA 0x0000A000 +#define DDRSS0_PHY_378_DATA 0x00A000A0 +#define DDRSS0_PHY_379_DATA 0x00A000A0 +#define DDRSS0_PHY_380_DATA 0x00A000A0 +#define DDRSS0_PHY_381_DATA 0x00A000A0 +#define DDRSS0_PHY_382_DATA 0x00A000A0 +#define DDRSS0_PHY_383_DATA 0x00A000A0 +#define DDRSS0_PHY_384_DATA 0x00A000A0 +#define DDRSS0_PHY_385_DATA 0x00A000A0 +#define DDRSS0_PHY_386_DATA 0x01C200A0 +#define DDRSS0_PHY_387_DATA 0x01A00005 +#define DDRSS0_PHY_388_DATA 0x00000000 +#define DDRSS0_PHY_389_DATA 0x00000000 +#define DDRSS0_PHY_390_DATA 0x00080200 +#define DDRSS0_PHY_391_DATA 0x00000000 +#define DDRSS0_PHY_392_DATA 0x20202000 +#define DDRSS0_PHY_393_DATA 0x20202020 +#define DDRSS0_PHY_394_DATA 0xF0F02020 +#define DDRSS0_PHY_395_DATA 0x00000000 +#define DDRSS0_PHY_396_DATA 0x00000000 +#define DDRSS0_PHY_397_DATA 0x00000000 +#define DDRSS0_PHY_398_DATA 0x00000000 +#define DDRSS0_PHY_399_DATA 0x00000000 +#define DDRSS0_PHY_400_DATA 0x00000000 +#define DDRSS0_PHY_401_DATA 0x00000000 +#define DDRSS0_PHY_402_DATA 0x00000000 +#define DDRSS0_PHY_403_DATA 0x00000000 +#define DDRSS0_PHY_404_DATA 0x00000000 +#define DDRSS0_PHY_405_DATA 0x00000000 +#define DDRSS0_PHY_406_DATA 0x00000000 +#define DDRSS0_PHY_407_DATA 0x00000000 +#define DDRSS0_PHY_408_DATA 0x00000000 +#define DDRSS0_PHY_409_DATA 0x00000000 +#define DDRSS0_PHY_410_DATA 0x00000000 +#define DDRSS0_PHY_411_DATA 0x00000000 +#define DDRSS0_PHY_412_DATA 0x00000000 +#define DDRSS0_PHY_413_DATA 0x00000000 +#define DDRSS0_PHY_414_DATA 0x00000000 +#define DDRSS0_PHY_415_DATA 0x00000000 +#define DDRSS0_PHY_416_DATA 0x00000000 +#define DDRSS0_PHY_417_DATA 0x00000000 +#define DDRSS0_PHY_418_DATA 0x00000000 +#define DDRSS0_PHY_419_DATA 0x00000000 +#define DDRSS0_PHY_420_DATA 0x00000000 +#define DDRSS0_PHY_421_DATA 0x00000000 +#define DDRSS0_PHY_422_DATA 0x00000000 +#define DDRSS0_PHY_423_DATA 0x00000000 +#define DDRSS0_PHY_424_DATA 0x00000000 +#define DDRSS0_PHY_425_DATA 0x00000000 +#define DDRSS0_PHY_426_DATA 0x00000000 +#define DDRSS0_PHY_427_DATA 0x00000000 +#define DDRSS0_PHY_428_DATA 0x00000000 +#define DDRSS0_PHY_429_DATA 0x00000000 +#define DDRSS0_PHY_430_DATA 0x00000000 +#define DDRSS0_PHY_431_DATA 0x00000000 +#define DDRSS0_PHY_432_DATA 0x00000000 +#define DDRSS0_PHY_433_DATA 0x00000000 +#define DDRSS0_PHY_434_DATA 0x00000000 +#define DDRSS0_PHY_435_DATA 0x00000000 +#define DDRSS0_PHY_436_DATA 0x00000000 +#define DDRSS0_PHY_437_DATA 0x00000000 +#define DDRSS0_PHY_438_DATA 0x00000000 +#define DDRSS0_PHY_439_DATA 0x00000000 +#define DDRSS0_PHY_440_DATA 0x00000000 +#define DDRSS0_PHY_441_DATA 0x00000000 +#define DDRSS0_PHY_442_DATA 0x00000000 +#define DDRSS0_PHY_443_DATA 0x00000000 +#define DDRSS0_PHY_444_DATA 0x00000000 +#define DDRSS0_PHY_445_DATA 0x00000000 +#define DDRSS0_PHY_446_DATA 0x00000000 +#define DDRSS0_PHY_447_DATA 0x00000000 +#define DDRSS0_PHY_448_DATA 0x00000000 +#define DDRSS0_PHY_449_DATA 0x00000000 +#define DDRSS0_PHY_450_DATA 0x00000000 +#define DDRSS0_PHY_451_DATA 0x00000000 +#define DDRSS0_PHY_452_DATA 0x00000000 +#define DDRSS0_PHY_453_DATA 0x00000000 +#define DDRSS0_PHY_454_DATA 0x00000000 +#define DDRSS0_PHY_455_DATA 0x00000000 +#define DDRSS0_PHY_456_DATA 0x00000000 +#define DDRSS0_PHY_457_DATA 0x00000000 +#define DDRSS0_PHY_458_DATA 0x00000000 +#define DDRSS0_PHY_459_DATA 0x00000000 +#define DDRSS0_PHY_460_DATA 0x00000000 +#define DDRSS0_PHY_461_DATA 0x00000000 +#define DDRSS0_PHY_462_DATA 0x00000000 +#define DDRSS0_PHY_463_DATA 0x00000000 +#define DDRSS0_PHY_464_DATA 0x00000000 +#define DDRSS0_PHY_465_DATA 0x00000000 +#define DDRSS0_PHY_466_DATA 0x00000000 +#define DDRSS0_PHY_467_DATA 0x00000000 +#define DDRSS0_PHY_468_DATA 0x00000000 +#define DDRSS0_PHY_469_DATA 0x00000000 +#define DDRSS0_PHY_470_DATA 0x00000000 +#define DDRSS0_PHY_471_DATA 0x00000000 +#define DDRSS0_PHY_472_DATA 0x00000000 +#define DDRSS0_PHY_473_DATA 0x00000000 +#define DDRSS0_PHY_474_DATA 0x00000000 +#define DDRSS0_PHY_475_DATA 0x00000000 +#define DDRSS0_PHY_476_DATA 0x00000000 +#define DDRSS0_PHY_477_DATA 0x00000000 +#define DDRSS0_PHY_478_DATA 0x00000000 +#define DDRSS0_PHY_479_DATA 0x00000000 +#define DDRSS0_PHY_480_DATA 0x00000000 +#define DDRSS0_PHY_481_DATA 0x00000000 +#define DDRSS0_PHY_482_DATA 0x00000000 +#define DDRSS0_PHY_483_DATA 0x00000000 +#define DDRSS0_PHY_484_DATA 0x00000000 +#define DDRSS0_PHY_485_DATA 0x00000000 +#define DDRSS0_PHY_486_DATA 0x00000000 +#define DDRSS0_PHY_487_DATA 0x00000000 +#define DDRSS0_PHY_488_DATA 0x00000000 +#define DDRSS0_PHY_489_DATA 0x00000000 +#define DDRSS0_PHY_490_DATA 0x00000000 +#define DDRSS0_PHY_491_DATA 0x00000000 +#define DDRSS0_PHY_492_DATA 0x00000000 +#define DDRSS0_PHY_493_DATA 0x00000000 +#define DDRSS0_PHY_494_DATA 0x00000000 +#define DDRSS0_PHY_495_DATA 0x00000000 +#define DDRSS0_PHY_496_DATA 0x00000000 +#define DDRSS0_PHY_497_DATA 0x00000000 +#define DDRSS0_PHY_498_DATA 0x00000000 +#define DDRSS0_PHY_499_DATA 0x00000000 +#define DDRSS0_PHY_500_DATA 0x00000000 +#define DDRSS0_PHY_501_DATA 0x00000000 +#define DDRSS0_PHY_502_DATA 0x00000000 +#define DDRSS0_PHY_503_DATA 0x00000000 +#define DDRSS0_PHY_504_DATA 0x00000000 +#define DDRSS0_PHY_505_DATA 0x00000000 +#define DDRSS0_PHY_506_DATA 0x00000000 +#define DDRSS0_PHY_507_DATA 0x00000000 +#define DDRSS0_PHY_508_DATA 0x00000000 +#define DDRSS0_PHY_509_DATA 0x00000000 +#define DDRSS0_PHY_510_DATA 0x00000000 +#define DDRSS0_PHY_511_DATA 0x00000000 +#define DDRSS0_PHY_512_DATA 0x000004F0 +#define DDRSS0_PHY_513_DATA 0x00000000 +#define DDRSS0_PHY_514_DATA 0x00030200 +#define DDRSS0_PHY_515_DATA 0x00000000 +#define DDRSS0_PHY_516_DATA 0x00000000 +#define DDRSS0_PHY_517_DATA 0x01030000 +#define DDRSS0_PHY_518_DATA 0x00010000 +#define DDRSS0_PHY_519_DATA 0x01030004 +#define DDRSS0_PHY_520_DATA 0x01000000 +#define DDRSS0_PHY_521_DATA 0x00000000 +#define DDRSS0_PHY_522_DATA 0x00000000 +#define DDRSS0_PHY_523_DATA 0x01000001 +#define DDRSS0_PHY_524_DATA 0x00000200 +#define DDRSS0_PHY_525_DATA 0x000800C0 +#define DDRSS0_PHY_526_DATA 0x060100CC +#define DDRSS0_PHY_527_DATA 0x00030066 +#define DDRSS0_PHY_528_DATA 0x00000000 +#define DDRSS0_PHY_529_DATA 0x00000301 +#define DDRSS0_PHY_530_DATA 0x0000AAAA +#define DDRSS0_PHY_531_DATA 0x00005555 +#define DDRSS0_PHY_532_DATA 0x0000B5B5 +#define DDRSS0_PHY_533_DATA 0x00004A4A +#define DDRSS0_PHY_534_DATA 0x00005656 +#define DDRSS0_PHY_535_DATA 0x0000A9A9 +#define DDRSS0_PHY_536_DATA 0x0000A9A9 +#define DDRSS0_PHY_537_DATA 0x0000B5B5 +#define DDRSS0_PHY_538_DATA 0x00000000 +#define DDRSS0_PHY_539_DATA 0x00000000 +#define DDRSS0_PHY_540_DATA 0x2A000000 +#define DDRSS0_PHY_541_DATA 0x00000808 +#define DDRSS0_PHY_542_DATA 0x0F000000 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002006 +#define DDRSS0_PHY_546_DATA 0x00000000 +#define DDRSS0_PHY_547_DATA 0x00000000 +#define DDRSS0_PHY_548_DATA 0x55555555 +#define DDRSS0_PHY_549_DATA 0xAAAAAAAA +#define DDRSS0_PHY_550_DATA 0x55555555 +#define DDRSS0_PHY_551_DATA 0xAAAAAAAA +#define DDRSS0_PHY_552_DATA 0x00005555 +#define DDRSS0_PHY_553_DATA 0x01000100 +#define DDRSS0_PHY_554_DATA 0x00800180 +#define DDRSS0_PHY_555_DATA 0x00000001 +#define DDRSS0_PHY_556_DATA 0x00000000 +#define DDRSS0_PHY_557_DATA 0x00000000 +#define DDRSS0_PHY_558_DATA 0x00000000 +#define DDRSS0_PHY_559_DATA 0x00000000 +#define DDRSS0_PHY_560_DATA 0x00000000 +#define DDRSS0_PHY_561_DATA 0x00000000 +#define DDRSS0_PHY_562_DATA 0x00000000 +#define DDRSS0_PHY_563_DATA 0x00000000 +#define DDRSS0_PHY_564_DATA 0x00000000 +#define DDRSS0_PHY_565_DATA 0x00000000 +#define DDRSS0_PHY_566_DATA 0x00000000 +#define DDRSS0_PHY_567_DATA 0x00000000 +#define DDRSS0_PHY_568_DATA 0x00000000 +#define DDRSS0_PHY_569_DATA 0x00000000 +#define DDRSS0_PHY_570_DATA 0x00000000 +#define DDRSS0_PHY_571_DATA 0x00000000 +#define DDRSS0_PHY_572_DATA 0x00000000 +#define DDRSS0_PHY_573_DATA 0x00000000 +#define DDRSS0_PHY_574_DATA 0x00000000 +#define DDRSS0_PHY_575_DATA 0x00000000 +#define DDRSS0_PHY_576_DATA 0x00000000 +#define DDRSS0_PHY_577_DATA 0x00000000 +#define DDRSS0_PHY_578_DATA 0x00000104 +#define DDRSS0_PHY_579_DATA 0x00000120 +#define DDRSS0_PHY_580_DATA 0x00000000 +#define DDRSS0_PHY_581_DATA 0x00000000 +#define DDRSS0_PHY_582_DATA 0x00000000 +#define DDRSS0_PHY_583_DATA 0x00000000 +#define DDRSS0_PHY_584_DATA 0x00000000 +#define DDRSS0_PHY_585_DATA 0x00000000 +#define DDRSS0_PHY_586_DATA 0x00000000 +#define DDRSS0_PHY_587_DATA 0x00000001 +#define DDRSS0_PHY_588_DATA 0x07FF0000 +#define DDRSS0_PHY_589_DATA 0x0080081F +#define DDRSS0_PHY_590_DATA 0x00081020 +#define DDRSS0_PHY_591_DATA 0x04010000 +#define DDRSS0_PHY_592_DATA 0x00000000 +#define DDRSS0_PHY_593_DATA 0x00000000 +#define DDRSS0_PHY_594_DATA 0x00000000 +#define DDRSS0_PHY_595_DATA 0x00000100 +#define DDRSS0_PHY_596_DATA 0x01CC0C01 +#define DDRSS0_PHY_597_DATA 0x1003CC0C +#define DDRSS0_PHY_598_DATA 0x20000140 +#define DDRSS0_PHY_599_DATA 0x07FF0200 +#define DDRSS0_PHY_600_DATA 0x0000DD01 +#define DDRSS0_PHY_601_DATA 0x10100303 +#define DDRSS0_PHY_602_DATA 0x10101010 +#define DDRSS0_PHY_603_DATA 0x10101010 +#define DDRSS0_PHY_604_DATA 0x00021010 +#define DDRSS0_PHY_605_DATA 0x00100010 +#define DDRSS0_PHY_606_DATA 0x00100010 +#define DDRSS0_PHY_607_DATA 0x00100010 +#define DDRSS0_PHY_608_DATA 0x00100010 +#define DDRSS0_PHY_609_DATA 0x00050010 +#define DDRSS0_PHY_610_DATA 0x51517041 +#define DDRSS0_PHY_611_DATA 0x31C06001 +#define DDRSS0_PHY_612_DATA 0x07AB01AB +#define DDRSS0_PHY_613_DATA 0x00C0C001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 +#define DDRSS0_PHY_615_DATA 0x10001000 +#define DDRSS0_PHY_616_DATA 0x0C083E42 +#define DDRSS0_PHY_617_DATA 0x0F0C3701 +#define DDRSS0_PHY_618_DATA 0x01000140 +#define DDRSS0_PHY_619_DATA 0x0C000420 +#define DDRSS0_PHY_620_DATA 0x00000198 +#define DDRSS0_PHY_621_DATA 0x0A0000D0 +#define DDRSS0_PHY_622_DATA 0x00030200 +#define DDRSS0_PHY_623_DATA 0x02800000 +#define DDRSS0_PHY_624_DATA 0x80800000 +#define DDRSS0_PHY_625_DATA 0x000E2010 +#define DDRSS0_PHY_626_DATA 0x76543210 +#define DDRSS0_PHY_627_DATA 0x00000008 +#define DDRSS0_PHY_628_DATA 0x02800280 +#define DDRSS0_PHY_629_DATA 0x02800280 +#define DDRSS0_PHY_630_DATA 0x02800280 +#define DDRSS0_PHY_631_DATA 0x02800280 +#define DDRSS0_PHY_632_DATA 0x00000280 +#define DDRSS0_PHY_633_DATA 0x0000A000 +#define DDRSS0_PHY_634_DATA 0x00A000A0 +#define DDRSS0_PHY_635_DATA 0x00A000A0 +#define DDRSS0_PHY_636_DATA 0x00A000A0 +#define DDRSS0_PHY_637_DATA 0x00A000A0 +#define DDRSS0_PHY_638_DATA 0x00A000A0 +#define DDRSS0_PHY_639_DATA 0x00A000A0 +#define DDRSS0_PHY_640_DATA 0x00A000A0 +#define DDRSS0_PHY_641_DATA 0x00A000A0 +#define DDRSS0_PHY_642_DATA 0x01C200A0 +#define DDRSS0_PHY_643_DATA 0x01A00005 +#define DDRSS0_PHY_644_DATA 0x00000000 +#define DDRSS0_PHY_645_DATA 0x00000000 +#define DDRSS0_PHY_646_DATA 0x00080200 +#define DDRSS0_PHY_647_DATA 0x00000000 +#define DDRSS0_PHY_648_DATA 0x20202000 +#define DDRSS0_PHY_649_DATA 0x20202020 +#define DDRSS0_PHY_650_DATA 0xF0F02020 +#define DDRSS0_PHY_651_DATA 0x00000000 +#define DDRSS0_PHY_652_DATA 0x00000000 +#define DDRSS0_PHY_653_DATA 0x00000000 +#define DDRSS0_PHY_654_DATA 0x00000000 +#define DDRSS0_PHY_655_DATA 0x00000000 +#define DDRSS0_PHY_656_DATA 0x00000000 +#define DDRSS0_PHY_657_DATA 0x00000000 +#define DDRSS0_PHY_658_DATA 0x00000000 +#define DDRSS0_PHY_659_DATA 0x00000000 +#define DDRSS0_PHY_660_DATA 0x00000000 +#define DDRSS0_PHY_661_DATA 0x00000000 +#define DDRSS0_PHY_662_DATA 0x00000000 +#define DDRSS0_PHY_663_DATA 0x00000000 +#define DDRSS0_PHY_664_DATA 0x00000000 +#define DDRSS0_PHY_665_DATA 0x00000000 +#define DDRSS0_PHY_666_DATA 0x00000000 +#define DDRSS0_PHY_667_DATA 0x00000000 +#define DDRSS0_PHY_668_DATA 0x00000000 +#define DDRSS0_PHY_669_DATA 0x00000000 +#define DDRSS0_PHY_670_DATA 0x00000000 +#define DDRSS0_PHY_671_DATA 0x00000000 +#define DDRSS0_PHY_672_DATA 0x00000000 +#define DDRSS0_PHY_673_DATA 0x00000000 +#define DDRSS0_PHY_674_DATA 0x00000000 +#define DDRSS0_PHY_675_DATA 0x00000000 +#define DDRSS0_PHY_676_DATA 0x00000000 +#define DDRSS0_PHY_677_DATA 0x00000000 +#define DDRSS0_PHY_678_DATA 0x00000000 +#define DDRSS0_PHY_679_DATA 0x00000000 +#define DDRSS0_PHY_680_DATA 0x00000000 +#define DDRSS0_PHY_681_DATA 0x00000000 +#define DDRSS0_PHY_682_DATA 0x00000000 +#define DDRSS0_PHY_683_DATA 0x00000000 +#define DDRSS0_PHY_684_DATA 0x00000000 +#define DDRSS0_PHY_685_DATA 0x00000000 +#define DDRSS0_PHY_686_DATA 0x00000000 +#define DDRSS0_PHY_687_DATA 0x00000000 +#define DDRSS0_PHY_688_DATA 0x00000000 +#define DDRSS0_PHY_689_DATA 0x00000000 +#define DDRSS0_PHY_690_DATA 0x00000000 +#define DDRSS0_PHY_691_DATA 0x00000000 +#define DDRSS0_PHY_692_DATA 0x00000000 +#define DDRSS0_PHY_693_DATA 0x00000000 +#define DDRSS0_PHY_694_DATA 0x00000000 +#define DDRSS0_PHY_695_DATA 0x00000000 +#define DDRSS0_PHY_696_DATA 0x00000000 +#define DDRSS0_PHY_697_DATA 0x00000000 +#define DDRSS0_PHY_698_DATA 0x00000000 +#define DDRSS0_PHY_699_DATA 0x00000000 +#define DDRSS0_PHY_700_DATA 0x00000000 +#define DDRSS0_PHY_701_DATA 0x00000000 +#define DDRSS0_PHY_702_DATA 0x00000000 +#define DDRSS0_PHY_703_DATA 0x00000000 +#define DDRSS0_PHY_704_DATA 0x00000000 +#define DDRSS0_PHY_705_DATA 0x00000000 +#define DDRSS0_PHY_706_DATA 0x00000000 +#define DDRSS0_PHY_707_DATA 0x00000000 +#define DDRSS0_PHY_708_DATA 0x00000000 +#define DDRSS0_PHY_709_DATA 0x00000000 +#define DDRSS0_PHY_710_DATA 0x00000000 +#define DDRSS0_PHY_711_DATA 0x00000000 +#define DDRSS0_PHY_712_DATA 0x00000000 +#define DDRSS0_PHY_713_DATA 0x00000000 +#define DDRSS0_PHY_714_DATA 0x00000000 +#define DDRSS0_PHY_715_DATA 0x00000000 +#define DDRSS0_PHY_716_DATA 0x00000000 +#define DDRSS0_PHY_717_DATA 0x00000000 +#define DDRSS0_PHY_718_DATA 0x00000000 +#define DDRSS0_PHY_719_DATA 0x00000000 +#define DDRSS0_PHY_720_DATA 0x00000000 +#define DDRSS0_PHY_721_DATA 0x00000000 +#define DDRSS0_PHY_722_DATA 0x00000000 +#define DDRSS0_PHY_723_DATA 0x00000000 +#define DDRSS0_PHY_724_DATA 0x00000000 +#define DDRSS0_PHY_725_DATA 0x00000000 +#define DDRSS0_PHY_726_DATA 0x00000000 +#define DDRSS0_PHY_727_DATA 0x00000000 +#define DDRSS0_PHY_728_DATA 0x00000000 +#define DDRSS0_PHY_729_DATA 0x00000000 +#define DDRSS0_PHY_730_DATA 0x00000000 +#define DDRSS0_PHY_731_DATA 0x00000000 +#define DDRSS0_PHY_732_DATA 0x00000000 +#define DDRSS0_PHY_733_DATA 0x00000000 +#define DDRSS0_PHY_734_DATA 0x00000000 +#define DDRSS0_PHY_735_DATA 0x00000000 +#define DDRSS0_PHY_736_DATA 0x00000000 +#define DDRSS0_PHY_737_DATA 0x00000000 +#define DDRSS0_PHY_738_DATA 0x00000000 +#define DDRSS0_PHY_739_DATA 0x00000000 +#define DDRSS0_PHY_740_DATA 0x00000000 +#define DDRSS0_PHY_741_DATA 0x00000000 +#define DDRSS0_PHY_742_DATA 0x00000000 +#define DDRSS0_PHY_743_DATA 0x00000000 +#define DDRSS0_PHY_744_DATA 0x00000000 +#define DDRSS0_PHY_745_DATA 0x00000000 +#define DDRSS0_PHY_746_DATA 0x00000000 +#define DDRSS0_PHY_747_DATA 0x00000000 +#define DDRSS0_PHY_748_DATA 0x00000000 +#define DDRSS0_PHY_749_DATA 0x00000000 +#define DDRSS0_PHY_750_DATA 0x00000000 +#define DDRSS0_PHY_751_DATA 0x00000000 +#define DDRSS0_PHY_752_DATA 0x00000000 +#define DDRSS0_PHY_753_DATA 0x00000000 +#define DDRSS0_PHY_754_DATA 0x00000000 +#define DDRSS0_PHY_755_DATA 0x00000000 +#define DDRSS0_PHY_756_DATA 0x00000000 +#define DDRSS0_PHY_757_DATA 0x00000000 +#define DDRSS0_PHY_758_DATA 0x00000000 +#define DDRSS0_PHY_759_DATA 0x00000000 +#define DDRSS0_PHY_760_DATA 0x00000000 +#define DDRSS0_PHY_761_DATA 0x00000000 +#define DDRSS0_PHY_762_DATA 0x00000000 +#define DDRSS0_PHY_763_DATA 0x00000000 +#define DDRSS0_PHY_764_DATA 0x00000000 +#define DDRSS0_PHY_765_DATA 0x00000000 +#define DDRSS0_PHY_766_DATA 0x00000000 +#define DDRSS0_PHY_767_DATA 0x00000000 +#define DDRSS0_PHY_768_DATA 0x000004F0 +#define DDRSS0_PHY_769_DATA 0x00000000 +#define DDRSS0_PHY_770_DATA 0x00030200 +#define DDRSS0_PHY_771_DATA 0x00000000 +#define DDRSS0_PHY_772_DATA 0x00000000 +#define DDRSS0_PHY_773_DATA 0x01030000 +#define DDRSS0_PHY_774_DATA 0x00010000 +#define DDRSS0_PHY_775_DATA 0x01030004 +#define DDRSS0_PHY_776_DATA 0x01000000 +#define DDRSS0_PHY_777_DATA 0x00000000 +#define DDRSS0_PHY_778_DATA 0x00000000 +#define DDRSS0_PHY_779_DATA 0x01000001 +#define DDRSS0_PHY_780_DATA 0x00000200 +#define DDRSS0_PHY_781_DATA 0x000800C0 +#define DDRSS0_PHY_782_DATA 0x060100CC +#define DDRSS0_PHY_783_DATA 0x00030066 +#define DDRSS0_PHY_784_DATA 0x00000000 +#define DDRSS0_PHY_785_DATA 0x00000301 +#define DDRSS0_PHY_786_DATA 0x0000AAAA +#define DDRSS0_PHY_787_DATA 0x00005555 +#define DDRSS0_PHY_788_DATA 0x0000B5B5 +#define DDRSS0_PHY_789_DATA 0x00004A4A +#define DDRSS0_PHY_790_DATA 0x00005656 +#define DDRSS0_PHY_791_DATA 0x0000A9A9 +#define DDRSS0_PHY_792_DATA 0x0000A9A9 +#define DDRSS0_PHY_793_DATA 0x0000B5B5 +#define DDRSS0_PHY_794_DATA 0x00000000 +#define DDRSS0_PHY_795_DATA 0x00000000 +#define DDRSS0_PHY_796_DATA 0x2A000000 +#define DDRSS0_PHY_797_DATA 0x00000808 +#define DDRSS0_PHY_798_DATA 0x0F000000 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002006 +#define DDRSS0_PHY_802_DATA 0x00000000 +#define DDRSS0_PHY_803_DATA 0x00000000 +#define DDRSS0_PHY_804_DATA 0x55555555 +#define DDRSS0_PHY_805_DATA 0xAAAAAAAA +#define DDRSS0_PHY_806_DATA 0x55555555 +#define DDRSS0_PHY_807_DATA 0xAAAAAAAA +#define DDRSS0_PHY_808_DATA 0x00005555 +#define DDRSS0_PHY_809_DATA 0x01000100 +#define DDRSS0_PHY_810_DATA 0x00800180 +#define DDRSS0_PHY_811_DATA 0x00000000 +#define DDRSS0_PHY_812_DATA 0x00000000 +#define DDRSS0_PHY_813_DATA 0x00000000 +#define DDRSS0_PHY_814_DATA 0x00000000 +#define DDRSS0_PHY_815_DATA 0x00000000 +#define DDRSS0_PHY_816_DATA 0x00000000 +#define DDRSS0_PHY_817_DATA 0x00000000 +#define DDRSS0_PHY_818_DATA 0x00000000 +#define DDRSS0_PHY_819_DATA 0x00000000 +#define DDRSS0_PHY_820_DATA 0x00000000 +#define DDRSS0_PHY_821_DATA 0x00000000 +#define DDRSS0_PHY_822_DATA 0x00000000 +#define DDRSS0_PHY_823_DATA 0x00000000 +#define DDRSS0_PHY_824_DATA 0x00000000 +#define DDRSS0_PHY_825_DATA 0x00000000 +#define DDRSS0_PHY_826_DATA 0x00000000 +#define DDRSS0_PHY_827_DATA 0x00000000 +#define DDRSS0_PHY_828_DATA 0x00000000 +#define DDRSS0_PHY_829_DATA 0x00000000 +#define DDRSS0_PHY_830_DATA 0x00000000 +#define DDRSS0_PHY_831_DATA 0x00000000 +#define DDRSS0_PHY_832_DATA 0x00000000 +#define DDRSS0_PHY_833_DATA 0x00000000 +#define DDRSS0_PHY_834_DATA 0x00000104 +#define DDRSS0_PHY_835_DATA 0x00000120 +#define DDRSS0_PHY_836_DATA 0x00000000 +#define DDRSS0_PHY_837_DATA 0x00000000 +#define DDRSS0_PHY_838_DATA 0x00000000 +#define DDRSS0_PHY_839_DATA 0x00000000 +#define DDRSS0_PHY_840_DATA 0x00000000 +#define DDRSS0_PHY_841_DATA 0x00000000 +#define DDRSS0_PHY_842_DATA 0x00000000 +#define DDRSS0_PHY_843_DATA 0x00000001 +#define DDRSS0_PHY_844_DATA 0x07FF0000 +#define DDRSS0_PHY_845_DATA 0x0080081F +#define DDRSS0_PHY_846_DATA 0x00081020 +#define DDRSS0_PHY_847_DATA 0x04010000 +#define DDRSS0_PHY_848_DATA 0x00000000 +#define DDRSS0_PHY_849_DATA 0x00000000 +#define DDRSS0_PHY_850_DATA 0x00000000 +#define DDRSS0_PHY_851_DATA 0x00000100 +#define DDRSS0_PHY_852_DATA 0x01CC0C01 +#define DDRSS0_PHY_853_DATA 0x1003CC0C +#define DDRSS0_PHY_854_DATA 0x20000140 +#define DDRSS0_PHY_855_DATA 0x07FF0200 +#define DDRSS0_PHY_856_DATA 0x0000DD01 +#define DDRSS0_PHY_857_DATA 0x10100303 +#define DDRSS0_PHY_858_DATA 0x10101010 +#define DDRSS0_PHY_859_DATA 0x10101010 +#define DDRSS0_PHY_860_DATA 0x00021010 +#define DDRSS0_PHY_861_DATA 0x00100010 +#define DDRSS0_PHY_862_DATA 0x00100010 +#define DDRSS0_PHY_863_DATA 0x00100010 +#define DDRSS0_PHY_864_DATA 0x00100010 +#define DDRSS0_PHY_865_DATA 0x00050010 +#define DDRSS0_PHY_866_DATA 0x51517041 +#define DDRSS0_PHY_867_DATA 0x31C06001 +#define DDRSS0_PHY_868_DATA 0x07AB01AB +#define DDRSS0_PHY_869_DATA 0x00C0C001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 +#define DDRSS0_PHY_871_DATA 0x10001000 +#define DDRSS0_PHY_872_DATA 0x0C083E42 +#define DDRSS0_PHY_873_DATA 0x0F0C3701 +#define DDRSS0_PHY_874_DATA 0x01000140 +#define DDRSS0_PHY_875_DATA 0x0C000420 +#define DDRSS0_PHY_876_DATA 0x00000198 +#define DDRSS0_PHY_877_DATA 0x0A0000D0 +#define DDRSS0_PHY_878_DATA 0x00030200 +#define DDRSS0_PHY_879_DATA 0x02800000 +#define DDRSS0_PHY_880_DATA 0x80800000 +#define DDRSS0_PHY_881_DATA 0x000E2010 +#define DDRSS0_PHY_882_DATA 0x76543210 +#define DDRSS0_PHY_883_DATA 0x00000008 +#define DDRSS0_PHY_884_DATA 0x02800280 +#define DDRSS0_PHY_885_DATA 0x02800280 +#define DDRSS0_PHY_886_DATA 0x02800280 +#define DDRSS0_PHY_887_DATA 0x02800280 +#define DDRSS0_PHY_888_DATA 0x00000280 +#define DDRSS0_PHY_889_DATA 0x0000A000 +#define DDRSS0_PHY_890_DATA 0x00A000A0 +#define DDRSS0_PHY_891_DATA 0x00A000A0 +#define DDRSS0_PHY_892_DATA 0x00A000A0 +#define DDRSS0_PHY_893_DATA 0x00A000A0 +#define DDRSS0_PHY_894_DATA 0x00A000A0 +#define DDRSS0_PHY_895_DATA 0x00A000A0 +#define DDRSS0_PHY_896_DATA 0x00A000A0 +#define DDRSS0_PHY_897_DATA 0x00A000A0 +#define DDRSS0_PHY_898_DATA 0x01C200A0 +#define DDRSS0_PHY_899_DATA 0x01A00005 +#define DDRSS0_PHY_900_DATA 0x00000000 +#define DDRSS0_PHY_901_DATA 0x00000000 +#define DDRSS0_PHY_902_DATA 0x00080200 +#define DDRSS0_PHY_903_DATA 0x00000000 +#define DDRSS0_PHY_904_DATA 0x20202000 +#define DDRSS0_PHY_905_DATA 0x20202020 +#define DDRSS0_PHY_906_DATA 0xF0F02020 +#define DDRSS0_PHY_907_DATA 0x00000000 +#define DDRSS0_PHY_908_DATA 0x00000000 +#define DDRSS0_PHY_909_DATA 0x00000000 +#define DDRSS0_PHY_910_DATA 0x00000000 +#define DDRSS0_PHY_911_DATA 0x00000000 +#define DDRSS0_PHY_912_DATA 0x00000000 +#define DDRSS0_PHY_913_DATA 0x00000000 +#define DDRSS0_PHY_914_DATA 0x00000000 +#define DDRSS0_PHY_915_DATA 0x00000000 +#define DDRSS0_PHY_916_DATA 0x00000000 +#define DDRSS0_PHY_917_DATA 0x00000000 +#define DDRSS0_PHY_918_DATA 0x00000000 +#define DDRSS0_PHY_919_DATA 0x00000000 +#define DDRSS0_PHY_920_DATA 0x00000000 +#define DDRSS0_PHY_921_DATA 0x00000000 +#define DDRSS0_PHY_922_DATA 0x00000000 +#define DDRSS0_PHY_923_DATA 0x00000000 +#define DDRSS0_PHY_924_DATA 0x00000000 +#define DDRSS0_PHY_925_DATA 0x00000000 +#define DDRSS0_PHY_926_DATA 0x00000000 +#define DDRSS0_PHY_927_DATA 0x00000000 +#define DDRSS0_PHY_928_DATA 0x00000000 +#define DDRSS0_PHY_929_DATA 0x00000000 +#define DDRSS0_PHY_930_DATA 0x00000000 +#define DDRSS0_PHY_931_DATA 0x00000000 +#define DDRSS0_PHY_932_DATA 0x00000000 +#define DDRSS0_PHY_933_DATA 0x00000000 +#define DDRSS0_PHY_934_DATA 0x00000000 +#define DDRSS0_PHY_935_DATA 0x00000000 +#define DDRSS0_PHY_936_DATA 0x00000000 +#define DDRSS0_PHY_937_DATA 0x00000000 +#define DDRSS0_PHY_938_DATA 0x00000000 +#define DDRSS0_PHY_939_DATA 0x00000000 +#define DDRSS0_PHY_940_DATA 0x00000000 +#define DDRSS0_PHY_941_DATA 0x00000000 +#define DDRSS0_PHY_942_DATA 0x00000000 +#define DDRSS0_PHY_943_DATA 0x00000000 +#define DDRSS0_PHY_944_DATA 0x00000000 +#define DDRSS0_PHY_945_DATA 0x00000000 +#define DDRSS0_PHY_946_DATA 0x00000000 +#define DDRSS0_PHY_947_DATA 0x00000000 +#define DDRSS0_PHY_948_DATA 0x00000000 +#define DDRSS0_PHY_949_DATA 0x00000000 +#define DDRSS0_PHY_950_DATA 0x00000000 +#define DDRSS0_PHY_951_DATA 0x00000000 +#define DDRSS0_PHY_952_DATA 0x00000000 +#define DDRSS0_PHY_953_DATA 0x00000000 +#define DDRSS0_PHY_954_DATA 0x00000000 +#define DDRSS0_PHY_955_DATA 0x00000000 +#define DDRSS0_PHY_956_DATA 0x00000000 +#define DDRSS0_PHY_957_DATA 0x00000000 +#define DDRSS0_PHY_958_DATA 0x00000000 +#define DDRSS0_PHY_959_DATA 0x00000000 +#define DDRSS0_PHY_960_DATA 0x00000000 +#define DDRSS0_PHY_961_DATA 0x00000000 +#define DDRSS0_PHY_962_DATA 0x00000000 +#define DDRSS0_PHY_963_DATA 0x00000000 +#define DDRSS0_PHY_964_DATA 0x00000000 +#define DDRSS0_PHY_965_DATA 0x00000000 +#define DDRSS0_PHY_966_DATA 0x00000000 +#define DDRSS0_PHY_967_DATA 0x00000000 +#define DDRSS0_PHY_968_DATA 0x00000000 +#define DDRSS0_PHY_969_DATA 0x00000000 +#define DDRSS0_PHY_970_DATA 0x00000000 +#define DDRSS0_PHY_971_DATA 0x00000000 +#define DDRSS0_PHY_972_DATA 0x00000000 +#define DDRSS0_PHY_973_DATA 0x00000000 +#define DDRSS0_PHY_974_DATA 0x00000000 +#define DDRSS0_PHY_975_DATA 0x00000000 +#define DDRSS0_PHY_976_DATA 0x00000000 +#define DDRSS0_PHY_977_DATA 0x00000000 +#define DDRSS0_PHY_978_DATA 0x00000000 +#define DDRSS0_PHY_979_DATA 0x00000000 +#define DDRSS0_PHY_980_DATA 0x00000000 +#define DDRSS0_PHY_981_DATA 0x00000000 +#define DDRSS0_PHY_982_DATA 0x00000000 +#define DDRSS0_PHY_983_DATA 0x00000000 +#define DDRSS0_PHY_984_DATA 0x00000000 +#define DDRSS0_PHY_985_DATA 0x00000000 +#define DDRSS0_PHY_986_DATA 0x00000000 +#define DDRSS0_PHY_987_DATA 0x00000000 +#define DDRSS0_PHY_988_DATA 0x00000000 +#define DDRSS0_PHY_989_DATA 0x00000000 +#define DDRSS0_PHY_990_DATA 0x00000000 +#define DDRSS0_PHY_991_DATA 0x00000000 +#define DDRSS0_PHY_992_DATA 0x00000000 +#define DDRSS0_PHY_993_DATA 0x00000000 +#define DDRSS0_PHY_994_DATA 0x00000000 +#define DDRSS0_PHY_995_DATA 0x00000000 +#define DDRSS0_PHY_996_DATA 0x00000000 +#define DDRSS0_PHY_997_DATA 0x00000000 +#define DDRSS0_PHY_998_DATA 0x00000000 +#define DDRSS0_PHY_999_DATA 0x00000000 +#define DDRSS0_PHY_1000_DATA 0x00000000 +#define DDRSS0_PHY_1001_DATA 0x00000000 +#define DDRSS0_PHY_1002_DATA 0x00000000 +#define DDRSS0_PHY_1003_DATA 0x00000000 +#define DDRSS0_PHY_1004_DATA 0x00000000 +#define DDRSS0_PHY_1005_DATA 0x00000000 +#define DDRSS0_PHY_1006_DATA 0x00000000 +#define DDRSS0_PHY_1007_DATA 0x00000000 +#define DDRSS0_PHY_1008_DATA 0x00000000 +#define DDRSS0_PHY_1009_DATA 0x00000000 +#define DDRSS0_PHY_1010_DATA 0x00000000 +#define DDRSS0_PHY_1011_DATA 0x00000000 +#define DDRSS0_PHY_1012_DATA 0x00000000 +#define DDRSS0_PHY_1013_DATA 0x00000000 +#define DDRSS0_PHY_1014_DATA 0x00000000 +#define DDRSS0_PHY_1015_DATA 0x00000000 +#define DDRSS0_PHY_1016_DATA 0x00000000 +#define DDRSS0_PHY_1017_DATA 0x00000000 +#define DDRSS0_PHY_1018_DATA 0x00000000 +#define DDRSS0_PHY_1019_DATA 0x00000000 +#define DDRSS0_PHY_1020_DATA 0x00000000 +#define DDRSS0_PHY_1021_DATA 0x00000000 +#define DDRSS0_PHY_1022_DATA 0x00000000 +#define DDRSS0_PHY_1023_DATA 0x00000000 +#define DDRSS0_PHY_1024_DATA 0x00000000 +#define DDRSS0_PHY_1025_DATA 0x00000000 +#define DDRSS0_PHY_1026_DATA 0x00000000 +#define DDRSS0_PHY_1027_DATA 0x00000000 +#define DDRSS0_PHY_1028_DATA 0x00000000 +#define DDRSS0_PHY_1029_DATA 0x00000100 +#define DDRSS0_PHY_1030_DATA 0x00000200 +#define DDRSS0_PHY_1031_DATA 0x00000000 +#define DDRSS0_PHY_1032_DATA 0x00000000 +#define DDRSS0_PHY_1033_DATA 0x00000000 +#define DDRSS0_PHY_1034_DATA 0x00000000 +#define DDRSS0_PHY_1035_DATA 0x00400000 +#define DDRSS0_PHY_1036_DATA 0x00000080 +#define DDRSS0_PHY_1037_DATA 0x00DCBA98 +#define DDRSS0_PHY_1038_DATA 0x03000000 +#define DDRSS0_PHY_1039_DATA 0x00200000 +#define DDRSS0_PHY_1040_DATA 0x00000000 +#define DDRSS0_PHY_1041_DATA 0x00000000 +#define DDRSS0_PHY_1042_DATA 0x00000000 +#define DDRSS0_PHY_1043_DATA 0x00000000 +#define DDRSS0_PHY_1044_DATA 0x00000000 +#define DDRSS0_PHY_1045_DATA 0x0000002A +#define DDRSS0_PHY_1046_DATA 0x00000015 +#define DDRSS0_PHY_1047_DATA 0x00000015 +#define DDRSS0_PHY_1048_DATA 0x0000002A +#define DDRSS0_PHY_1049_DATA 0x00000033 +#define DDRSS0_PHY_1050_DATA 0x0000000C +#define DDRSS0_PHY_1051_DATA 0x0000000C +#define DDRSS0_PHY_1052_DATA 0x00000033 +#define DDRSS0_PHY_1053_DATA 0x00543210 +#define DDRSS0_PHY_1054_DATA 0x003F0000 +#define DDRSS0_PHY_1055_DATA 0x000F3F3F +#define DDRSS0_PHY_1056_DATA 0x20202003 +#define DDRSS0_PHY_1057_DATA 0x00202020 +#define DDRSS0_PHY_1058_DATA 0x20008008 +#define DDRSS0_PHY_1059_DATA 0x00000810 +#define DDRSS0_PHY_1060_DATA 0x00000F00 +#define DDRSS0_PHY_1061_DATA 0x00000000 +#define DDRSS0_PHY_1062_DATA 0x00000000 +#define DDRSS0_PHY_1063_DATA 0x00000000 +#define DDRSS0_PHY_1064_DATA 0x000305CC +#define DDRSS0_PHY_1065_DATA 0x00030000 +#define DDRSS0_PHY_1066_DATA 0x00000300 +#define DDRSS0_PHY_1067_DATA 0x00000300 +#define DDRSS0_PHY_1068_DATA 0x00000300 +#define DDRSS0_PHY_1069_DATA 0x00000300 +#define DDRSS0_PHY_1070_DATA 0x00000300 +#define DDRSS0_PHY_1071_DATA 0x42080010 +#define DDRSS0_PHY_1072_DATA 0x0000803E +#define DDRSS0_PHY_1073_DATA 0x00000001 +#define DDRSS0_PHY_1074_DATA 0x01000102 +#define DDRSS0_PHY_1075_DATA 0x00008000 +#define DDRSS0_PHY_1076_DATA 0x00000000 +#define DDRSS0_PHY_1077_DATA 0x00000000 +#define DDRSS0_PHY_1078_DATA 0x00000000 +#define DDRSS0_PHY_1079_DATA 0x00000000 +#define DDRSS0_PHY_1080_DATA 0x00000000 +#define DDRSS0_PHY_1081_DATA 0x00000000 +#define DDRSS0_PHY_1082_DATA 0x00000000 +#define DDRSS0_PHY_1083_DATA 0x00000000 +#define DDRSS0_PHY_1084_DATA 0x00000000 +#define DDRSS0_PHY_1085_DATA 0x00000000 +#define DDRSS0_PHY_1086_DATA 0x00000000 +#define DDRSS0_PHY_1087_DATA 0x00000000 +#define DDRSS0_PHY_1088_DATA 0x00000000 +#define DDRSS0_PHY_1089_DATA 0x00000000 +#define DDRSS0_PHY_1090_DATA 0x00000000 +#define DDRSS0_PHY_1091_DATA 0x00000000 +#define DDRSS0_PHY_1092_DATA 0x00000000 +#define DDRSS0_PHY_1093_DATA 0x00000000 +#define DDRSS0_PHY_1094_DATA 0x00000000 +#define DDRSS0_PHY_1095_DATA 0x00000000 +#define DDRSS0_PHY_1096_DATA 0x00000000 +#define DDRSS0_PHY_1097_DATA 0x00000000 +#define DDRSS0_PHY_1098_DATA 0x00000000 +#define DDRSS0_PHY_1099_DATA 0x00000000 +#define DDRSS0_PHY_1100_DATA 0x00000000 +#define DDRSS0_PHY_1101_DATA 0x00000000 +#define DDRSS0_PHY_1102_DATA 0x00000000 +#define DDRSS0_PHY_1103_DATA 0x00000000 +#define DDRSS0_PHY_1104_DATA 0x00000000 +#define DDRSS0_PHY_1105_DATA 0x00000000 +#define DDRSS0_PHY_1106_DATA 0x00000000 +#define DDRSS0_PHY_1107_DATA 0x00000000 +#define DDRSS0_PHY_1108_DATA 0x00000000 +#define DDRSS0_PHY_1109_DATA 0x00000000 +#define DDRSS0_PHY_1110_DATA 0x00000000 +#define DDRSS0_PHY_1111_DATA 0x00000000 +#define DDRSS0_PHY_1112_DATA 0x00000000 +#define DDRSS0_PHY_1113_DATA 0x00000000 +#define DDRSS0_PHY_1114_DATA 0x00000000 +#define DDRSS0_PHY_1115_DATA 0x00000000 +#define DDRSS0_PHY_1116_DATA 0x00000000 +#define DDRSS0_PHY_1117_DATA 0x00000000 +#define DDRSS0_PHY_1118_DATA 0x00000000 +#define DDRSS0_PHY_1119_DATA 0x00000000 +#define DDRSS0_PHY_1120_DATA 0x00000000 +#define DDRSS0_PHY_1121_DATA 0x00000000 +#define DDRSS0_PHY_1122_DATA 0x00000000 +#define DDRSS0_PHY_1123_DATA 0x00000000 +#define DDRSS0_PHY_1124_DATA 0x00000000 +#define DDRSS0_PHY_1125_DATA 0x00000000 +#define DDRSS0_PHY_1126_DATA 0x00000000 +#define DDRSS0_PHY_1127_DATA 0x00000000 +#define DDRSS0_PHY_1128_DATA 0x00000000 +#define DDRSS0_PHY_1129_DATA 0x00000000 +#define DDRSS0_PHY_1130_DATA 0x00000000 +#define DDRSS0_PHY_1131_DATA 0x00000000 +#define DDRSS0_PHY_1132_DATA 0x00000000 +#define DDRSS0_PHY_1133_DATA 0x00000000 +#define DDRSS0_PHY_1134_DATA 0x00000000 +#define DDRSS0_PHY_1135_DATA 0x00000000 +#define DDRSS0_PHY_1136_DATA 0x00000000 +#define DDRSS0_PHY_1137_DATA 0x00000000 +#define DDRSS0_PHY_1138_DATA 0x00000000 +#define DDRSS0_PHY_1139_DATA 0x00000000 +#define DDRSS0_PHY_1140_DATA 0x00000000 +#define DDRSS0_PHY_1141_DATA 0x00000000 +#define DDRSS0_PHY_1142_DATA 0x00000000 +#define DDRSS0_PHY_1143_DATA 0x00000000 +#define DDRSS0_PHY_1144_DATA 0x00000000 +#define DDRSS0_PHY_1145_DATA 0x00000000 +#define DDRSS0_PHY_1146_DATA 0x00000000 +#define DDRSS0_PHY_1147_DATA 0x00000000 +#define DDRSS0_PHY_1148_DATA 0x00000000 +#define DDRSS0_PHY_1149_DATA 0x00000000 +#define DDRSS0_PHY_1150_DATA 0x00000000 +#define DDRSS0_PHY_1151_DATA 0x00000000 +#define DDRSS0_PHY_1152_DATA 0x00000000 +#define DDRSS0_PHY_1153_DATA 0x00000000 +#define DDRSS0_PHY_1154_DATA 0x00000000 +#define DDRSS0_PHY_1155_DATA 0x00000000 +#define DDRSS0_PHY_1156_DATA 0x00000000 +#define DDRSS0_PHY_1157_DATA 0x00000000 +#define DDRSS0_PHY_1158_DATA 0x00000000 +#define DDRSS0_PHY_1159_DATA 0x00000000 +#define DDRSS0_PHY_1160_DATA 0x00000000 +#define DDRSS0_PHY_1161_DATA 0x00000000 +#define DDRSS0_PHY_1162_DATA 0x00000000 +#define DDRSS0_PHY_1163_DATA 0x00000000 +#define DDRSS0_PHY_1164_DATA 0x00000000 +#define DDRSS0_PHY_1165_DATA 0x00000000 +#define DDRSS0_PHY_1166_DATA 0x00000000 +#define DDRSS0_PHY_1167_DATA 0x00000000 +#define DDRSS0_PHY_1168_DATA 0x00000000 +#define DDRSS0_PHY_1169_DATA 0x00000000 +#define DDRSS0_PHY_1170_DATA 0x00000000 +#define DDRSS0_PHY_1171_DATA 0x00000000 +#define DDRSS0_PHY_1172_DATA 0x00000000 +#define DDRSS0_PHY_1173_DATA 0x00000000 +#define DDRSS0_PHY_1174_DATA 0x00000000 +#define DDRSS0_PHY_1175_DATA 0x00000000 +#define DDRSS0_PHY_1176_DATA 0x00000000 +#define DDRSS0_PHY_1177_DATA 0x00000000 +#define DDRSS0_PHY_1178_DATA 0x00000000 +#define DDRSS0_PHY_1179_DATA 0x00000000 +#define DDRSS0_PHY_1180_DATA 0x00000000 +#define DDRSS0_PHY_1181_DATA 0x00000000 +#define DDRSS0_PHY_1182_DATA 0x00000000 +#define DDRSS0_PHY_1183_DATA 0x00000000 +#define DDRSS0_PHY_1184_DATA 0x00000000 +#define DDRSS0_PHY_1185_DATA 0x00000000 +#define DDRSS0_PHY_1186_DATA 0x00000000 +#define DDRSS0_PHY_1187_DATA 0x00000000 +#define DDRSS0_PHY_1188_DATA 0x00000000 +#define DDRSS0_PHY_1189_DATA 0x00000000 +#define DDRSS0_PHY_1190_DATA 0x00000000 +#define DDRSS0_PHY_1191_DATA 0x00000000 +#define DDRSS0_PHY_1192_DATA 0x00000000 +#define DDRSS0_PHY_1193_DATA 0x00000000 +#define DDRSS0_PHY_1194_DATA 0x00000000 +#define DDRSS0_PHY_1195_DATA 0x00000000 +#define DDRSS0_PHY_1196_DATA 0x00000000 +#define DDRSS0_PHY_1197_DATA 0x00000000 +#define DDRSS0_PHY_1198_DATA 0x00000000 +#define DDRSS0_PHY_1199_DATA 0x00000000 +#define DDRSS0_PHY_1200_DATA 0x00000000 +#define DDRSS0_PHY_1201_DATA 0x00000000 +#define DDRSS0_PHY_1202_DATA 0x00000000 +#define DDRSS0_PHY_1203_DATA 0x00000000 +#define DDRSS0_PHY_1204_DATA 0x00000000 +#define DDRSS0_PHY_1205_DATA 0x00000000 +#define DDRSS0_PHY_1206_DATA 0x00000000 +#define DDRSS0_PHY_1207_DATA 0x00000000 +#define DDRSS0_PHY_1208_DATA 0x00000000 +#define DDRSS0_PHY_1209_DATA 0x00000000 +#define DDRSS0_PHY_1210_DATA 0x00000000 +#define DDRSS0_PHY_1211_DATA 0x00000000 +#define DDRSS0_PHY_1212_DATA 0x00000000 +#define DDRSS0_PHY_1213_DATA 0x00000000 +#define DDRSS0_PHY_1214_DATA 0x00000000 +#define DDRSS0_PHY_1215_DATA 0x00000000 +#define DDRSS0_PHY_1216_DATA 0x00000000 +#define DDRSS0_PHY_1217_DATA 0x00000000 +#define DDRSS0_PHY_1218_DATA 0x00000000 +#define DDRSS0_PHY_1219_DATA 0x00000000 +#define DDRSS0_PHY_1220_DATA 0x00000000 +#define DDRSS0_PHY_1221_DATA 0x00000000 +#define DDRSS0_PHY_1222_DATA 0x00000000 +#define DDRSS0_PHY_1223_DATA 0x00000000 +#define DDRSS0_PHY_1224_DATA 0x00000000 +#define DDRSS0_PHY_1225_DATA 0x00000000 +#define DDRSS0_PHY_1226_DATA 0x00000000 +#define DDRSS0_PHY_1227_DATA 0x00000000 +#define DDRSS0_PHY_1228_DATA 0x00000000 +#define DDRSS0_PHY_1229_DATA 0x00000000 +#define DDRSS0_PHY_1230_DATA 0x00000000 +#define DDRSS0_PHY_1231_DATA 0x00000000 +#define DDRSS0_PHY_1232_DATA 0x00000000 +#define DDRSS0_PHY_1233_DATA 0x00000000 +#define DDRSS0_PHY_1234_DATA 0x00000000 +#define DDRSS0_PHY_1235_DATA 0x00000000 +#define DDRSS0_PHY_1236_DATA 0x00000000 +#define DDRSS0_PHY_1237_DATA 0x00000000 +#define DDRSS0_PHY_1238_DATA 0x00000000 +#define DDRSS0_PHY_1239_DATA 0x00000000 +#define DDRSS0_PHY_1240_DATA 0x00000000 +#define DDRSS0_PHY_1241_DATA 0x00000000 +#define DDRSS0_PHY_1242_DATA 0x00000000 +#define DDRSS0_PHY_1243_DATA 0x00000000 +#define DDRSS0_PHY_1244_DATA 0x00000000 +#define DDRSS0_PHY_1245_DATA 0x00000000 +#define DDRSS0_PHY_1246_DATA 0x00000000 +#define DDRSS0_PHY_1247_DATA 0x00000000 +#define DDRSS0_PHY_1248_DATA 0x00000000 +#define DDRSS0_PHY_1249_DATA 0x00000000 +#define DDRSS0_PHY_1250_DATA 0x00000000 +#define DDRSS0_PHY_1251_DATA 0x00000000 +#define DDRSS0_PHY_1252_DATA 0x00000000 +#define DDRSS0_PHY_1253_DATA 0x00000000 +#define DDRSS0_PHY_1254_DATA 0x00000000 +#define DDRSS0_PHY_1255_DATA 0x00000000 +#define DDRSS0_PHY_1256_DATA 0x00000000 +#define DDRSS0_PHY_1257_DATA 0x00000000 +#define DDRSS0_PHY_1258_DATA 0x00000000 +#define DDRSS0_PHY_1259_DATA 0x00000000 +#define DDRSS0_PHY_1260_DATA 0x00000000 +#define DDRSS0_PHY_1261_DATA 0x00000000 +#define DDRSS0_PHY_1262_DATA 0x00000000 +#define DDRSS0_PHY_1263_DATA 0x00000000 +#define DDRSS0_PHY_1264_DATA 0x00000000 +#define DDRSS0_PHY_1265_DATA 0x00000000 +#define DDRSS0_PHY_1266_DATA 0x00000000 +#define DDRSS0_PHY_1267_DATA 0x00000000 +#define DDRSS0_PHY_1268_DATA 0x00000000 +#define DDRSS0_PHY_1269_DATA 0x00000000 +#define DDRSS0_PHY_1270_DATA 0x00000000 +#define DDRSS0_PHY_1271_DATA 0x00000000 +#define DDRSS0_PHY_1272_DATA 0x00000000 +#define DDRSS0_PHY_1273_DATA 0x00000000 +#define DDRSS0_PHY_1274_DATA 0x00000000 +#define DDRSS0_PHY_1275_DATA 0x00000000 +#define DDRSS0_PHY_1276_DATA 0x00000000 +#define DDRSS0_PHY_1277_DATA 0x00000000 +#define DDRSS0_PHY_1278_DATA 0x00000000 +#define DDRSS0_PHY_1279_DATA 0x00000000 +#define DDRSS0_PHY_1280_DATA 0x00000000 +#define DDRSS0_PHY_1281_DATA 0x00010100 +#define DDRSS0_PHY_1282_DATA 0x00000000 +#define DDRSS0_PHY_1283_DATA 0x00000000 +#define DDRSS0_PHY_1284_DATA 0x00050000 +#define DDRSS0_PHY_1285_DATA 0x04000000 +#define DDRSS0_PHY_1286_DATA 0x00000055 +#define DDRSS0_PHY_1287_DATA 0x00000000 +#define DDRSS0_PHY_1288_DATA 0x00000000 +#define DDRSS0_PHY_1289_DATA 0x00000000 +#define DDRSS0_PHY_1290_DATA 0x00000000 +#define DDRSS0_PHY_1291_DATA 0x00002001 +#define DDRSS0_PHY_1292_DATA 0x0000400F +#define DDRSS0_PHY_1293_DATA 0x50020028 +#define DDRSS0_PHY_1294_DATA 0x01010000 +#define DDRSS0_PHY_1295_DATA 0x80080001 +#define DDRSS0_PHY_1296_DATA 0x10200000 +#define DDRSS0_PHY_1297_DATA 0x00000008 +#define DDRSS0_PHY_1298_DATA 0x00000000 +#define DDRSS0_PHY_1299_DATA 0x01090E00 +#define DDRSS0_PHY_1300_DATA 0x00040101 +#define DDRSS0_PHY_1301_DATA 0x0000010F +#define DDRSS0_PHY_1302_DATA 0x00000000 +#define DDRSS0_PHY_1303_DATA 0x00000064 +#define DDRSS0_PHY_1304_DATA 0x00000000 +#define DDRSS0_PHY_1305_DATA 0x01010000 +#define DDRSS0_PHY_1306_DATA 0x01080402 +#define DDRSS0_PHY_1307_DATA 0x01200F02 +#define DDRSS0_PHY_1308_DATA 0x00194280 +#define DDRSS0_PHY_1309_DATA 0x00000004 +#define DDRSS0_PHY_1310_DATA 0x00042000 +#define DDRSS0_PHY_1311_DATA 0x00000000 +#define DDRSS0_PHY_1312_DATA 0x00000000 +#define DDRSS0_PHY_1313_DATA 0x00000000 +#define DDRSS0_PHY_1314_DATA 0x00000000 +#define DDRSS0_PHY_1315_DATA 0x00000000 +#define DDRSS0_PHY_1316_DATA 0x00000000 +#define DDRSS0_PHY_1317_DATA 0x01000000 +#define DDRSS0_PHY_1318_DATA 0x00000705 +#define DDRSS0_PHY_1319_DATA 0x00000054 +#define DDRSS0_PHY_1320_DATA 0x00030820 +#define DDRSS0_PHY_1321_DATA 0x00010820 +#define DDRSS0_PHY_1322_DATA 0x00010820 +#define DDRSS0_PHY_1323_DATA 0x00010820 +#define DDRSS0_PHY_1324_DATA 0x00010820 +#define DDRSS0_PHY_1325_DATA 0x00010820 +#define DDRSS0_PHY_1326_DATA 0x00010820 +#define DDRSS0_PHY_1327_DATA 0x00010820 +#define DDRSS0_PHY_1328_DATA 0x00010820 +#define DDRSS0_PHY_1329_DATA 0x00000000 +#define DDRSS0_PHY_1330_DATA 0x00000074 +#define DDRSS0_PHY_1331_DATA 0x00000400 +#define DDRSS0_PHY_1332_DATA 0x00000108 +#define DDRSS0_PHY_1333_DATA 0x00000000 +#define DDRSS0_PHY_1334_DATA 0x00000000 +#define DDRSS0_PHY_1335_DATA 0x00000000 +#define DDRSS0_PHY_1336_DATA 0x00000000 +#define DDRSS0_PHY_1337_DATA 0x00000000 +#define DDRSS0_PHY_1338_DATA 0x03000000 +#define DDRSS0_PHY_1339_DATA 0x00000000 +#define DDRSS0_PHY_1340_DATA 0x00000000 +#define DDRSS0_PHY_1341_DATA 0x00000000 +#define DDRSS0_PHY_1342_DATA 0x04102006 +#define DDRSS0_PHY_1343_DATA 0x00041020 +#define DDRSS0_PHY_1344_DATA 0x01C98C98 +#define DDRSS0_PHY_1345_DATA 0x3F400000 +#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS0_PHY_1347_DATA 0x0000001F +#define DDRSS0_PHY_1348_DATA 0x00000000 +#define DDRSS0_PHY_1349_DATA 0x00000000 +#define DDRSS0_PHY_1350_DATA 0x00000000 +#define DDRSS0_PHY_1351_DATA 0x00010000 +#define DDRSS0_PHY_1352_DATA 0x00000000 +#define DDRSS0_PHY_1353_DATA 0x00000000 +#define DDRSS0_PHY_1354_DATA 0x00000000 +#define DDRSS0_PHY_1355_DATA 0x00000000 +#define DDRSS0_PHY_1356_DATA 0x76543210 +#define DDRSS0_PHY_1357_DATA 0x00010198 +#define DDRSS0_PHY_1358_DATA 0x00000000 +#define DDRSS0_PHY_1359_DATA 0x00000000 +#define DDRSS0_PHY_1360_DATA 0x00000000 +#define DDRSS0_PHY_1361_DATA 0x00040700 +#define DDRSS0_PHY_1362_DATA 0x00000000 +#define DDRSS0_PHY_1363_DATA 0x00000000 +#define DDRSS0_PHY_1364_DATA 0x00000000 +#define DDRSS0_PHY_1365_DATA 0x00000000 +#define DDRSS0_PHY_1366_DATA 0x00000000 +#define DDRSS0_PHY_1367_DATA 0x00000002 +#define DDRSS0_PHY_1368_DATA 0x00000000 +#define DDRSS0_PHY_1369_DATA 0x00000000 +#define DDRSS0_PHY_1370_DATA 0x00000000 +#define DDRSS0_PHY_1371_DATA 0x00000000 +#define DDRSS0_PHY_1372_DATA 0x00000000 +#define DDRSS0_PHY_1373_DATA 0x00000000 +#define DDRSS0_PHY_1374_DATA 0x00080000 +#define DDRSS0_PHY_1375_DATA 0x000007FF +#define DDRSS0_PHY_1376_DATA 0x00000000 +#define DDRSS0_PHY_1377_DATA 0x00000000 +#define DDRSS0_PHY_1378_DATA 0x00000000 +#define DDRSS0_PHY_1379_DATA 0x00000000 +#define DDRSS0_PHY_1380_DATA 0x00000000 +#define DDRSS0_PHY_1381_DATA 0x00000000 +#define DDRSS0_PHY_1382_DATA 0x000FFFFF +#define DDRSS0_PHY_1383_DATA 0x000FFFFF +#define DDRSS0_PHY_1384_DATA 0x0000FFFF +#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS0_PHY_1386_DATA 0x030FFFFF +#define DDRSS0_PHY_1387_DATA 0x01FFFFFF +#define DDRSS0_PHY_1388_DATA 0x0000FFFF +#define DDRSS0_PHY_1389_DATA 0x00000000 +#define DDRSS0_PHY_1390_DATA 0x00000000 +#define DDRSS0_PHY_1391_DATA 0x00000000 +#define DDRSS0_PHY_1392_DATA 0x00000000 +#define DDRSS0_PHY_1393_DATA 0x0001F7C0 +#define DDRSS0_PHY_1394_DATA 0x00000003 +#define DDRSS0_PHY_1395_DATA 0x00000000 +#define DDRSS0_PHY_1396_DATA 0x00001142 +#define DDRSS0_PHY_1397_DATA 0x040207AB +#define DDRSS0_PHY_1398_DATA 0x01000080 +#define DDRSS0_PHY_1399_DATA 0x03900390 +#define DDRSS0_PHY_1400_DATA 0x03900390 +#define DDRSS0_PHY_1401_DATA 0x00000390 +#define DDRSS0_PHY_1402_DATA 0x00000390 +#define DDRSS0_PHY_1403_DATA 0x00000390 +#define DDRSS0_PHY_1404_DATA 0x00000390 +#define DDRSS0_PHY_1405_DATA 0x00000005 +#define DDRSS0_PHY_1406_DATA 0x01813FCC +#define DDRSS0_PHY_1407_DATA 0x000000CC +#define DDRSS0_PHY_1408_DATA 0x0C000DFF +#define DDRSS0_PHY_1409_DATA 0x30000DFF +#define DDRSS0_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1411_DATA 0x000100F0 +#define DDRSS0_PHY_1412_DATA 0x780DFFCC +#define DDRSS0_PHY_1413_DATA 0x00007E31 +#define DDRSS0_PHY_1414_DATA 0x000CBF11 +#define DDRSS0_PHY_1415_DATA 0x01990010 +#define DDRSS0_PHY_1416_DATA 0x000CBF11 +#define DDRSS0_PHY_1417_DATA 0x01990010 +#define DDRSS0_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1419_DATA 0x00EF00F0 +#define DDRSS0_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS0_PHY_1421_DATA 0x01FF00F0 +#define DDRSS0_PHY_1422_DATA 0x20040006 + +#define DDRSS1_CTL_00_DATA 0x00000B00 +#define DDRSS1_CTL_01_DATA 0x00000000 +#define DDRSS1_CTL_02_DATA 0x00000000 +#define DDRSS1_CTL_03_DATA 0x00000000 +#define DDRSS1_CTL_04_DATA 0x00000000 +#define DDRSS1_CTL_05_DATA 0x00000000 +#define DDRSS1_CTL_06_DATA 0x00000000 +#define DDRSS1_CTL_07_DATA 0x00002AF8 +#define DDRSS1_CTL_08_DATA 0x0001ADAF +#define DDRSS1_CTL_09_DATA 0x00000005 +#define DDRSS1_CTL_10_DATA 0x0000006E +#define DDRSS1_CTL_11_DATA 0x000681C8 +#define DDRSS1_CTL_12_DATA 0x004111C9 +#define DDRSS1_CTL_13_DATA 0x00000005 +#define DDRSS1_CTL_14_DATA 0x000010A9 +#define DDRSS1_CTL_15_DATA 0x000681C8 +#define DDRSS1_CTL_16_DATA 0x004111C9 +#define DDRSS1_CTL_17_DATA 0x00000005 +#define DDRSS1_CTL_18_DATA 0x000010A9 +#define DDRSS1_CTL_19_DATA 0x01010000 +#define DDRSS1_CTL_20_DATA 0x01011001 +#define DDRSS1_CTL_21_DATA 0x02010000 +#define DDRSS1_CTL_22_DATA 0x00020100 +#define DDRSS1_CTL_23_DATA 0x0000000B +#define DDRSS1_CTL_24_DATA 0x0000001C +#define DDRSS1_CTL_25_DATA 0x00000000 +#define DDRSS1_CTL_26_DATA 0x00000000 +#define DDRSS1_CTL_27_DATA 0x03020200 +#define DDRSS1_CTL_28_DATA 0x00005656 +#define DDRSS1_CTL_29_DATA 0x00100000 +#define DDRSS1_CTL_30_DATA 0x00000000 +#define DDRSS1_CTL_31_DATA 0x00000000 +#define DDRSS1_CTL_32_DATA 0x00000000 +#define DDRSS1_CTL_33_DATA 0x00000000 +#define DDRSS1_CTL_34_DATA 0x040C0000 +#define DDRSS1_CTL_35_DATA 0x12501250 +#define DDRSS1_CTL_36_DATA 0x00050804 +#define DDRSS1_CTL_37_DATA 0x09040008 +#define DDRSS1_CTL_38_DATA 0x15000204 +#define DDRSS1_CTL_39_DATA 0x1760008B +#define DDRSS1_CTL_40_DATA 0x1500422B +#define DDRSS1_CTL_41_DATA 0x1760008B +#define DDRSS1_CTL_42_DATA 0x2000422B +#define DDRSS1_CTL_43_DATA 0x000A0A09 +#define DDRSS1_CTL_44_DATA 0x040003C5 +#define DDRSS1_CTL_45_DATA 0x1E161104 +#define DDRSS1_CTL_46_DATA 0x1000922C +#define DDRSS1_CTL_47_DATA 0x1E161110 +#define DDRSS1_CTL_48_DATA 0x1000922C +#define DDRSS1_CTL_49_DATA 0x02030410 +#define DDRSS1_CTL_50_DATA 0x2C060500 +#define DDRSS1_CTL_51_DATA 0x08292C29 +#define DDRSS1_CTL_52_DATA 0x14000E0A +#define DDRSS1_CTL_53_DATA 0x04010A0A +#define DDRSS1_CTL_54_DATA 0x01010004 +#define DDRSS1_CTL_55_DATA 0x0454540A +#define DDRSS1_CTL_56_DATA 0x04313104 +#define DDRSS1_CTL_57_DATA 0x00003131 +#define DDRSS1_CTL_58_DATA 0x00010100 +#define DDRSS1_CTL_59_DATA 0x03010000 +#define DDRSS1_CTL_60_DATA 0x00001508 +#define DDRSS1_CTL_61_DATA 0x00000068 +#define DDRSS1_CTL_62_DATA 0x0000032B +#define DDRSS1_CTL_63_DATA 0x00001035 +#define DDRSS1_CTL_64_DATA 0x0000032B +#define DDRSS1_CTL_65_DATA 0x00001035 +#define DDRSS1_CTL_66_DATA 0x00000005 +#define DDRSS1_CTL_67_DATA 0x00050000 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 +#define DDRSS1_CTL_71_DATA 0x00120103 +#define DDRSS1_CTL_72_DATA 0x00100005 +#define DDRSS1_CTL_73_DATA 0x2F080010 +#define DDRSS1_CTL_74_DATA 0x0505012F +#define DDRSS1_CTL_75_DATA 0x0401030A +#define DDRSS1_CTL_76_DATA 0x041E100B +#define DDRSS1_CTL_77_DATA 0x100B0401 +#define DDRSS1_CTL_78_DATA 0x0001041E +#define DDRSS1_CTL_79_DATA 0x00160016 +#define DDRSS1_CTL_80_DATA 0x033B033B +#define DDRSS1_CTL_81_DATA 0x033B033B +#define DDRSS1_CTL_82_DATA 0x03050505 +#define DDRSS1_CTL_83_DATA 0x03010303 +#define DDRSS1_CTL_84_DATA 0x200B100B +#define DDRSS1_CTL_85_DATA 0x04041004 +#define DDRSS1_CTL_86_DATA 0x200B100B +#define DDRSS1_CTL_87_DATA 0x04041004 +#define DDRSS1_CTL_88_DATA 0x03010000 +#define DDRSS1_CTL_89_DATA 0x00010000 +#define DDRSS1_CTL_90_DATA 0x00000000 +#define DDRSS1_CTL_91_DATA 0x00000000 +#define DDRSS1_CTL_92_DATA 0x01000000 +#define DDRSS1_CTL_93_DATA 0x80104002 +#define DDRSS1_CTL_94_DATA 0x00000000 +#define DDRSS1_CTL_95_DATA 0x00040005 +#define DDRSS1_CTL_96_DATA 0x00000000 +#define DDRSS1_CTL_97_DATA 0x00050000 +#define DDRSS1_CTL_98_DATA 0x00000004 +#define DDRSS1_CTL_99_DATA 0x00000000 +#define DDRSS1_CTL_100_DATA 0x00040005 +#define DDRSS1_CTL_101_DATA 0x00000000 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 +#define DDRSS1_CTL_107_DATA 0x00000000 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 +#define DDRSS1_CTL_114_DATA 0x00000000 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 +#define DDRSS1_CTL_121_DATA 0x00000000 +#define DDRSS1_CTL_122_DATA 0x00007173 +#define DDRSS1_CTL_123_DATA 0x00000000 +#define DDRSS1_CTL_124_DATA 0x00000000 +#define DDRSS1_CTL_125_DATA 0x00000000 +#define DDRSS1_CTL_126_DATA 0x00000000 +#define DDRSS1_CTL_127_DATA 0x00000000 +#define DDRSS1_CTL_128_DATA 0x00000000 +#define DDRSS1_CTL_129_DATA 0x00000000 +#define DDRSS1_CTL_130_DATA 0x00000000 +#define DDRSS1_CTL_131_DATA 0x0B030500 +#define DDRSS1_CTL_132_DATA 0x00040B04 +#define DDRSS1_CTL_133_DATA 0x0A090000 +#define DDRSS1_CTL_134_DATA 0x0A090701 +#define DDRSS1_CTL_135_DATA 0x0900000E +#define DDRSS1_CTL_136_DATA 0x0907010A +#define DDRSS1_CTL_137_DATA 0x00000E0A +#define DDRSS1_CTL_138_DATA 0x07010A09 +#define DDRSS1_CTL_139_DATA 0x000E0A09 +#define DDRSS1_CTL_140_DATA 0x07000401 +#define DDRSS1_CTL_141_DATA 0x00000000 +#define DDRSS1_CTL_142_DATA 0x00000000 +#define DDRSS1_CTL_143_DATA 0x00000000 +#define DDRSS1_CTL_144_DATA 0x00000000 +#define DDRSS1_CTL_145_DATA 0x00000000 +#define DDRSS1_CTL_146_DATA 0x00000000 +#define DDRSS1_CTL_147_DATA 0x00000000 +#define DDRSS1_CTL_148_DATA 0x08080000 +#define DDRSS1_CTL_149_DATA 0x01000000 +#define DDRSS1_CTL_150_DATA 0x800000C0 +#define DDRSS1_CTL_151_DATA 0x800000C0 +#define DDRSS1_CTL_152_DATA 0x800000C0 +#define DDRSS1_CTL_153_DATA 0x00000000 +#define DDRSS1_CTL_154_DATA 0x00001500 +#define DDRSS1_CTL_155_DATA 0x00000000 +#define DDRSS1_CTL_156_DATA 0x00000001 +#define DDRSS1_CTL_157_DATA 0x00000002 +#define DDRSS1_CTL_158_DATA 0x0000100E +#define DDRSS1_CTL_159_DATA 0x00000000 +#define DDRSS1_CTL_160_DATA 0x00000000 +#define DDRSS1_CTL_161_DATA 0x00000000 +#define DDRSS1_CTL_162_DATA 0x00000000 +#define DDRSS1_CTL_163_DATA 0x00000000 +#define DDRSS1_CTL_164_DATA 0x000B0000 +#define DDRSS1_CTL_165_DATA 0x000E0006 +#define DDRSS1_CTL_166_DATA 0x000E0404 +#define DDRSS1_CTL_167_DATA 0x00D601AB +#define DDRSS1_CTL_168_DATA 0x10100216 +#define DDRSS1_CTL_169_DATA 0x01AB0216 +#define DDRSS1_CTL_170_DATA 0x021600D6 +#define DDRSS1_CTL_171_DATA 0x02161010 +#define DDRSS1_CTL_172_DATA 0x00000000 +#define DDRSS1_CTL_173_DATA 0x00000000 +#define DDRSS1_CTL_174_DATA 0x00000000 +#define DDRSS1_CTL_175_DATA 0x3FF40084 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x35000000 +#define DDRSS1_CTL_179_DATA 0x27270035 +#define DDRSS1_CTL_180_DATA 0x0F0F0000 +#define DDRSS1_CTL_181_DATA 0x16000000 +#define DDRSS1_CTL_182_DATA 0x00841616 +#define DDRSS1_CTL_183_DATA 0x3FF43FF4 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 +#define DDRSS1_CTL_185_DATA 0x00000000 +#define DDRSS1_CTL_186_DATA 0x00353500 +#define DDRSS1_CTL_187_DATA 0x00002727 +#define DDRSS1_CTL_188_DATA 0x00000F0F +#define DDRSS1_CTL_189_DATA 0x16161600 +#define DDRSS1_CTL_190_DATA 0x00000020 +#define DDRSS1_CTL_191_DATA 0x01000000 +#define DDRSS1_CTL_192_DATA 0x00000001 +#define DDRSS1_CTL_193_DATA 0x00000000 +#define DDRSS1_CTL_194_DATA 0x01000000 +#define DDRSS1_CTL_195_DATA 0x00000001 +#define DDRSS1_CTL_196_DATA 0x00000000 +#define DDRSS1_CTL_197_DATA 0x00000000 +#define DDRSS1_CTL_198_DATA 0x00000000 +#define DDRSS1_CTL_199_DATA 0x00000000 +#define DDRSS1_CTL_200_DATA 0x00000000 +#define DDRSS1_CTL_201_DATA 0x00000000 +#define DDRSS1_CTL_202_DATA 0x00000000 +#define DDRSS1_CTL_203_DATA 0x00000000 +#define DDRSS1_CTL_204_DATA 0x00000000 +#define DDRSS1_CTL_205_DATA 0x00000000 +#define DDRSS1_CTL_206_DATA 0x02000000 +#define DDRSS1_CTL_207_DATA 0x01080101 +#define DDRSS1_CTL_208_DATA 0x00000000 +#define DDRSS1_CTL_209_DATA 0x00000000 +#define DDRSS1_CTL_210_DATA 0x00000000 +#define DDRSS1_CTL_211_DATA 0x00000000 +#define DDRSS1_CTL_212_DATA 0x00000000 +#define DDRSS1_CTL_213_DATA 0x00000000 +#define DDRSS1_CTL_214_DATA 0x00000000 +#define DDRSS1_CTL_215_DATA 0x00000000 +#define DDRSS1_CTL_216_DATA 0x00000000 +#define DDRSS1_CTL_217_DATA 0x00000000 +#define DDRSS1_CTL_218_DATA 0x00000000 +#define DDRSS1_CTL_219_DATA 0x00000000 +#define DDRSS1_CTL_220_DATA 0x00000000 +#define DDRSS1_CTL_221_DATA 0x00000000 +#define DDRSS1_CTL_222_DATA 0x00001000 +#define DDRSS1_CTL_223_DATA 0x006403E8 +#define DDRSS1_CTL_224_DATA 0x00000000 +#define DDRSS1_CTL_225_DATA 0x00000000 +#define DDRSS1_CTL_226_DATA 0x00000000 +#define DDRSS1_CTL_227_DATA 0x15110000 +#define DDRSS1_CTL_228_DATA 0x00040C18 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 +#define DDRSS1_CTL_231_DATA 0x00000000 +#define DDRSS1_CTL_232_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 +#define DDRSS1_CTL_235_DATA 0x00000000 +#define DDRSS1_CTL_236_DATA 0x00000000 +#define DDRSS1_CTL_237_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 +#define DDRSS1_CTL_240_DATA 0x00000000 +#define DDRSS1_CTL_241_DATA 0x00000000 +#define DDRSS1_CTL_242_DATA 0x00030000 +#define DDRSS1_CTL_243_DATA 0x00000000 +#define DDRSS1_CTL_244_DATA 0x00000000 +#define DDRSS1_CTL_245_DATA 0x00000000 +#define DDRSS1_CTL_246_DATA 0x00000000 +#define DDRSS1_CTL_247_DATA 0x00000000 +#define DDRSS1_CTL_248_DATA 0x00000000 +#define DDRSS1_CTL_249_DATA 0x00000000 +#define DDRSS1_CTL_250_DATA 0x00000000 +#define DDRSS1_CTL_251_DATA 0x00000000 +#define DDRSS1_CTL_252_DATA 0x00000000 +#define DDRSS1_CTL_253_DATA 0x00000000 +#define DDRSS1_CTL_254_DATA 0x00000000 +#define DDRSS1_CTL_255_DATA 0x00000000 +#define DDRSS1_CTL_256_DATA 0x00000000 +#define DDRSS1_CTL_257_DATA 0x01000200 +#define DDRSS1_CTL_258_DATA 0x00370040 +#define DDRSS1_CTL_259_DATA 0x00020008 +#define DDRSS1_CTL_260_DATA 0x00400100 +#define DDRSS1_CTL_261_DATA 0x00400855 +#define DDRSS1_CTL_262_DATA 0x01000200 +#define DDRSS1_CTL_263_DATA 0x08550040 +#define DDRSS1_CTL_264_DATA 0x00000040 +#define DDRSS1_CTL_265_DATA 0x006B0003 +#define DDRSS1_CTL_266_DATA 0x0100006B +#define DDRSS1_CTL_267_DATA 0x03030303 +#define DDRSS1_CTL_268_DATA 0x00000000 +#define DDRSS1_CTL_269_DATA 0x00000202 +#define DDRSS1_CTL_270_DATA 0x00001FFF +#define DDRSS1_CTL_271_DATA 0x3FFF2000 +#define DDRSS1_CTL_272_DATA 0x03FF0000 +#define DDRSS1_CTL_273_DATA 0x000103FF +#define DDRSS1_CTL_274_DATA 0x0FFF0B00 +#define DDRSS1_CTL_275_DATA 0x01010001 +#define DDRSS1_CTL_276_DATA 0x01010101 +#define DDRSS1_CTL_277_DATA 0x01180101 +#define DDRSS1_CTL_278_DATA 0x00030000 +#define DDRSS1_CTL_279_DATA 0x00000000 +#define DDRSS1_CTL_280_DATA 0x00000000 +#define DDRSS1_CTL_281_DATA 0x00000000 +#define DDRSS1_CTL_282_DATA 0x00000000 +#define DDRSS1_CTL_283_DATA 0x00000000 +#define DDRSS1_CTL_284_DATA 0x00000000 +#define DDRSS1_CTL_285_DATA 0x00000000 +#define DDRSS1_CTL_286_DATA 0x00040101 +#define DDRSS1_CTL_287_DATA 0x04010100 +#define DDRSS1_CTL_288_DATA 0x00000000 +#define DDRSS1_CTL_289_DATA 0x00000000 +#define DDRSS1_CTL_290_DATA 0x03030300 +#define DDRSS1_CTL_291_DATA 0x00010101 +#define DDRSS1_CTL_292_DATA 0x00000000 +#define DDRSS1_CTL_293_DATA 0x00000000 +#define DDRSS1_CTL_294_DATA 0x00000000 +#define DDRSS1_CTL_295_DATA 0x00000000 +#define DDRSS1_CTL_296_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF +#define DDRSS1_CTL_299_DATA 0x00000000 +#define DDRSS1_CTL_300_DATA 0x00000000 +#define DDRSS1_CTL_301_DATA 0x00000000 +#define DDRSS1_CTL_302_DATA 0x00000000 +#define DDRSS1_CTL_303_DATA 0x00000000 +#define DDRSS1_CTL_304_DATA 0x00000000 +#define DDRSS1_CTL_305_DATA 0x00000000 +#define DDRSS1_CTL_306_DATA 0x00000000 +#define DDRSS1_CTL_307_DATA 0x00000000 +#define DDRSS1_CTL_308_DATA 0x00000000 +#define DDRSS1_CTL_309_DATA 0x00000000 +#define DDRSS1_CTL_310_DATA 0x00000000 +#define DDRSS1_CTL_311_DATA 0x00000000 +#define DDRSS1_CTL_312_DATA 0x00000000 +#define DDRSS1_CTL_313_DATA 0x01000000 +#define DDRSS1_CTL_314_DATA 0x00020201 +#define DDRSS1_CTL_315_DATA 0x01000101 +#define DDRSS1_CTL_316_DATA 0x01010001 +#define DDRSS1_CTL_317_DATA 0x00010101 +#define DDRSS1_CTL_318_DATA 0x050A0A03 +#define DDRSS1_CTL_319_DATA 0x10082323 +#define DDRSS1_CTL_320_DATA 0x00090310 +#define DDRSS1_CTL_321_DATA 0x0B0C030F +#define DDRSS1_CTL_322_DATA 0x0B0C0306 +#define DDRSS1_CTL_323_DATA 0x0C090006 +#define DDRSS1_CTL_324_DATA 0x0100000C +#define DDRSS1_CTL_325_DATA 0x08040801 +#define DDRSS1_CTL_326_DATA 0x00000004 +#define DDRSS1_CTL_327_DATA 0x00000000 +#define DDRSS1_CTL_328_DATA 0x00010000 +#define DDRSS1_CTL_329_DATA 0x00280D00 +#define DDRSS1_CTL_330_DATA 0x00000001 +#define DDRSS1_CTL_331_DATA 0x00030001 +#define DDRSS1_CTL_332_DATA 0x00000000 +#define DDRSS1_CTL_333_DATA 0x00000000 +#define DDRSS1_CTL_334_DATA 0x00000000 +#define DDRSS1_CTL_335_DATA 0x00000000 +#define DDRSS1_CTL_336_DATA 0x00000000 +#define DDRSS1_CTL_337_DATA 0x00000000 +#define DDRSS1_CTL_338_DATA 0x00000000 +#define DDRSS1_CTL_339_DATA 0x00000000 +#define DDRSS1_CTL_340_DATA 0x01000000 +#define DDRSS1_CTL_341_DATA 0x00000001 +#define DDRSS1_CTL_342_DATA 0x00010100 +#define DDRSS1_CTL_343_DATA 0x03030000 +#define DDRSS1_CTL_344_DATA 0x00000000 +#define DDRSS1_CTL_345_DATA 0x00000000 +#define DDRSS1_CTL_346_DATA 0x00000000 +#define DDRSS1_CTL_347_DATA 0x00000000 +#define DDRSS1_CTL_348_DATA 0x00000000 +#define DDRSS1_CTL_349_DATA 0x00000000 +#define DDRSS1_CTL_350_DATA 0x00000000 +#define DDRSS1_CTL_351_DATA 0x00000000 +#define DDRSS1_CTL_352_DATA 0x00000000 +#define DDRSS1_CTL_353_DATA 0x00000000 +#define DDRSS1_CTL_354_DATA 0x00000000 +#define DDRSS1_CTL_355_DATA 0x00000000 +#define DDRSS1_CTL_356_DATA 0x00000000 +#define DDRSS1_CTL_357_DATA 0x00000000 +#define DDRSS1_CTL_358_DATA 0x00000000 +#define DDRSS1_CTL_359_DATA 0x00000000 +#define DDRSS1_CTL_360_DATA 0x000556AA +#define DDRSS1_CTL_361_DATA 0x000AAAAA +#define DDRSS1_CTL_362_DATA 0x000AA955 +#define DDRSS1_CTL_363_DATA 0x00055555 +#define DDRSS1_CTL_364_DATA 0x000B3133 +#define DDRSS1_CTL_365_DATA 0x0004CD33 +#define DDRSS1_CTL_366_DATA 0x0004CECC +#define DDRSS1_CTL_367_DATA 0x000B32CC +#define DDRSS1_CTL_368_DATA 0x00010300 +#define DDRSS1_CTL_369_DATA 0x03000100 +#define DDRSS1_CTL_370_DATA 0x00000000 +#define DDRSS1_CTL_371_DATA 0x00000000 +#define DDRSS1_CTL_372_DATA 0x00000000 +#define DDRSS1_CTL_373_DATA 0x00000000 +#define DDRSS1_CTL_374_DATA 0x00000000 +#define DDRSS1_CTL_375_DATA 0x00000000 +#define DDRSS1_CTL_376_DATA 0x00000000 +#define DDRSS1_CTL_377_DATA 0x00010000 +#define DDRSS1_CTL_378_DATA 0x00000404 +#define DDRSS1_CTL_379_DATA 0x00000000 +#define DDRSS1_CTL_380_DATA 0x00000000 +#define DDRSS1_CTL_381_DATA 0x00000000 +#define DDRSS1_CTL_382_DATA 0x00000000 +#define DDRSS1_CTL_383_DATA 0x00000000 +#define DDRSS1_CTL_384_DATA 0x00000000 +#define DDRSS1_CTL_385_DATA 0x00000000 +#define DDRSS1_CTL_386_DATA 0x00000000 +#define DDRSS1_CTL_387_DATA 0x3A3A1B00 +#define DDRSS1_CTL_388_DATA 0x000A0000 +#define DDRSS1_CTL_389_DATA 0x000000C6 +#define DDRSS1_CTL_390_DATA 0x00000200 +#define DDRSS1_CTL_391_DATA 0x00000200 +#define DDRSS1_CTL_392_DATA 0x00000200 +#define DDRSS1_CTL_393_DATA 0x00000200 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC +#define DDRSS1_CTL_396_DATA 0x00000204 +#define DDRSS1_CTL_397_DATA 0x0000206A +#define DDRSS1_CTL_398_DATA 0x00000200 +#define DDRSS1_CTL_399_DATA 0x00000200 +#define DDRSS1_CTL_400_DATA 0x00000200 +#define DDRSS1_CTL_401_DATA 0x00000200 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A +#define DDRSS1_CTL_406_DATA 0x00000200 +#define DDRSS1_CTL_407_DATA 0x00000200 +#define DDRSS1_CTL_408_DATA 0x00000200 +#define DDRSS1_CTL_409_DATA 0x00000200 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 +#define DDRSS1_CTL_413_DATA 0x03030202 +#define DDRSS1_CTL_414_DATA 0x00000022 +#define DDRSS1_CTL_415_DATA 0x00000000 +#define DDRSS1_CTL_416_DATA 0x00000000 +#define DDRSS1_CTL_417_DATA 0x00001403 +#define DDRSS1_CTL_418_DATA 0x000007D0 +#define DDRSS1_CTL_419_DATA 0x00000000 +#define DDRSS1_CTL_420_DATA 0x00000000 +#define DDRSS1_CTL_421_DATA 0x00030000 +#define DDRSS1_CTL_422_DATA 0x0007001F +#define DDRSS1_CTL_423_DATA 0x001B0033 +#define DDRSS1_CTL_424_DATA 0x001B0033 +#define DDRSS1_CTL_425_DATA 0x00000000 +#define DDRSS1_CTL_426_DATA 0x00000000 +#define DDRSS1_CTL_427_DATA 0x02000000 +#define DDRSS1_CTL_428_DATA 0x01000404 +#define DDRSS1_CTL_429_DATA 0x0B220B22 +#define DDRSS1_CTL_430_DATA 0x00000105 +#define DDRSS1_CTL_431_DATA 0x00010101 +#define DDRSS1_CTL_432_DATA 0x00010101 +#define DDRSS1_CTL_433_DATA 0x00010001 +#define DDRSS1_CTL_434_DATA 0x00000101 +#define DDRSS1_CTL_435_DATA 0x02000201 +#define DDRSS1_CTL_436_DATA 0x02010000 +#define DDRSS1_CTL_437_DATA 0x00000200 +#define DDRSS1_CTL_438_DATA 0x28060000 +#define DDRSS1_CTL_439_DATA 0x00000128 +#define DDRSS1_CTL_440_DATA 0xFFFFFFFF +#define DDRSS1_CTL_441_DATA 0xFFFFFFFF +#define DDRSS1_CTL_442_DATA 0x00000000 +#define DDRSS1_CTL_443_DATA 0x00000000 +#define DDRSS1_CTL_444_DATA 0x00000000 +#define DDRSS1_CTL_445_DATA 0x00000000 +#define DDRSS1_CTL_446_DATA 0x00000000 +#define DDRSS1_CTL_447_DATA 0x00000000 +#define DDRSS1_CTL_448_DATA 0x00000000 +#define DDRSS1_CTL_449_DATA 0x00000000 +#define DDRSS1_CTL_450_DATA 0x00000000 +#define DDRSS1_CTL_451_DATA 0x00000000 +#define DDRSS1_CTL_452_DATA 0x00000000 +#define DDRSS1_CTL_453_DATA 0x00000000 +#define DDRSS1_CTL_454_DATA 0x00000000 +#define DDRSS1_CTL_455_DATA 0x00000000 +#define DDRSS1_CTL_456_DATA 0x00000000 +#define DDRSS1_CTL_457_DATA 0x00000000 +#define DDRSS1_CTL_458_DATA 0x00000000 + +#define DDRSS1_PI_00_DATA 0x00000B00 +#define DDRSS1_PI_01_DATA 0x00000000 +#define DDRSS1_PI_02_DATA 0x00000000 +#define DDRSS1_PI_03_DATA 0x00000000 +#define DDRSS1_PI_04_DATA 0x00000000 +#define DDRSS1_PI_05_DATA 0x00000101 +#define DDRSS1_PI_06_DATA 0x00640000 +#define DDRSS1_PI_07_DATA 0x00000001 +#define DDRSS1_PI_08_DATA 0x00000000 +#define DDRSS1_PI_09_DATA 0x00000000 +#define DDRSS1_PI_10_DATA 0x00000000 +#define DDRSS1_PI_11_DATA 0x00000000 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 +#define DDRSS1_PI_14_DATA 0x0800000F +#define DDRSS1_PI_15_DATA 0x00000103 +#define DDRSS1_PI_16_DATA 0x00000005 +#define DDRSS1_PI_17_DATA 0x00000000 +#define DDRSS1_PI_18_DATA 0x00000000 +#define DDRSS1_PI_19_DATA 0x00000000 +#define DDRSS1_PI_20_DATA 0x00000000 +#define DDRSS1_PI_21_DATA 0x00000000 +#define DDRSS1_PI_22_DATA 0x00000000 +#define DDRSS1_PI_23_DATA 0x00000000 +#define DDRSS1_PI_24_DATA 0x00000000 +#define DDRSS1_PI_25_DATA 0x00000000 +#define DDRSS1_PI_26_DATA 0x00010100 +#define DDRSS1_PI_27_DATA 0x00280A00 +#define DDRSS1_PI_28_DATA 0x00000000 +#define DDRSS1_PI_29_DATA 0x0F000000 +#define DDRSS1_PI_30_DATA 0x00003200 +#define DDRSS1_PI_31_DATA 0x00000000 +#define DDRSS1_PI_32_DATA 0x00000000 +#define DDRSS1_PI_33_DATA 0x01010102 +#define DDRSS1_PI_34_DATA 0x00000000 +#define DDRSS1_PI_35_DATA 0x000000AA +#define DDRSS1_PI_36_DATA 0x00000055 +#define DDRSS1_PI_37_DATA 0x000000B5 +#define DDRSS1_PI_38_DATA 0x0000004A +#define DDRSS1_PI_39_DATA 0x00000056 +#define DDRSS1_PI_40_DATA 0x000000A9 +#define DDRSS1_PI_41_DATA 0x000000A9 +#define DDRSS1_PI_42_DATA 0x000000B5 +#define DDRSS1_PI_43_DATA 0x00000000 +#define DDRSS1_PI_44_DATA 0x00000000 +#define DDRSS1_PI_45_DATA 0x000F0F00 +#define DDRSS1_PI_46_DATA 0x0000001B +#define DDRSS1_PI_47_DATA 0x000007D0 +#define DDRSS1_PI_48_DATA 0x00000300 +#define DDRSS1_PI_49_DATA 0x00000000 +#define DDRSS1_PI_50_DATA 0x00000000 +#define DDRSS1_PI_51_DATA 0x01000000 +#define DDRSS1_PI_52_DATA 0x00010101 +#define DDRSS1_PI_53_DATA 0x00000000 +#define DDRSS1_PI_54_DATA 0x00030000 +#define DDRSS1_PI_55_DATA 0x0F000000 +#define DDRSS1_PI_56_DATA 0x00000017 +#define DDRSS1_PI_57_DATA 0x00000000 +#define DDRSS1_PI_58_DATA 0x00000000 +#define DDRSS1_PI_59_DATA 0x00000000 +#define DDRSS1_PI_60_DATA 0x0A0A140A +#define DDRSS1_PI_61_DATA 0x10020201 +#define DDRSS1_PI_62_DATA 0x00020805 +#define DDRSS1_PI_63_DATA 0x01000404 +#define DDRSS1_PI_64_DATA 0x00000000 +#define DDRSS1_PI_65_DATA 0x00000000 +#define DDRSS1_PI_66_DATA 0x00000100 +#define DDRSS1_PI_67_DATA 0x0002020F +#define DDRSS1_PI_68_DATA 0x00340000 +#define DDRSS1_PI_69_DATA 0x00000000 +#define DDRSS1_PI_70_DATA 0x00000000 +#define DDRSS1_PI_71_DATA 0x0000FFFF +#define DDRSS1_PI_72_DATA 0x01000000 +#define DDRSS1_PI_73_DATA 0x00080000 +#define DDRSS1_PI_74_DATA 0x02000200 +#define DDRSS1_PI_75_DATA 0x01000100 +#define DDRSS1_PI_76_DATA 0x01000000 +#define DDRSS1_PI_77_DATA 0x02000200 +#define DDRSS1_PI_78_DATA 0x00000200 +#define DDRSS1_PI_79_DATA 0x00000000 +#define DDRSS1_PI_80_DATA 0x00000000 +#define DDRSS1_PI_81_DATA 0x00000000 +#define DDRSS1_PI_82_DATA 0x00000000 +#define DDRSS1_PI_83_DATA 0x00000000 +#define DDRSS1_PI_84_DATA 0x00000000 +#define DDRSS1_PI_85_DATA 0x00000000 +#define DDRSS1_PI_86_DATA 0x00000000 +#define DDRSS1_PI_87_DATA 0x00000000 +#define DDRSS1_PI_88_DATA 0x00000000 +#define DDRSS1_PI_89_DATA 0x00000000 +#define DDRSS1_PI_90_DATA 0x00000000 +#define DDRSS1_PI_91_DATA 0x00000400 +#define DDRSS1_PI_92_DATA 0x02010000 +#define DDRSS1_PI_93_DATA 0x00080003 +#define DDRSS1_PI_94_DATA 0x00080000 +#define DDRSS1_PI_95_DATA 0x00000001 +#define DDRSS1_PI_96_DATA 0x00000000 +#define DDRSS1_PI_97_DATA 0x0000AA00 +#define DDRSS1_PI_98_DATA 0x00000000 +#define DDRSS1_PI_99_DATA 0x00000000 +#define DDRSS1_PI_100_DATA 0x00010000 +#define DDRSS1_PI_101_DATA 0x00000000 +#define DDRSS1_PI_102_DATA 0x00000000 +#define DDRSS1_PI_103_DATA 0x00000000 +#define DDRSS1_PI_104_DATA 0x00000000 +#define DDRSS1_PI_105_DATA 0x00000000 +#define DDRSS1_PI_106_DATA 0x00000000 +#define DDRSS1_PI_107_DATA 0x00000000 +#define DDRSS1_PI_108_DATA 0x00000000 +#define DDRSS1_PI_109_DATA 0x00000000 +#define DDRSS1_PI_110_DATA 0x00000000 +#define DDRSS1_PI_111_DATA 0x00000000 +#define DDRSS1_PI_112_DATA 0x00000000 +#define DDRSS1_PI_113_DATA 0x00000000 +#define DDRSS1_PI_114_DATA 0x00000000 +#define DDRSS1_PI_115_DATA 0x00000000 +#define DDRSS1_PI_116_DATA 0x00000000 +#define DDRSS1_PI_117_DATA 0x00000000 +#define DDRSS1_PI_118_DATA 0x00000000 +#define DDRSS1_PI_119_DATA 0x00000000 +#define DDRSS1_PI_120_DATA 0x00000000 +#define DDRSS1_PI_121_DATA 0x00000000 +#define DDRSS1_PI_122_DATA 0x00000000 +#define DDRSS1_PI_123_DATA 0x00000000 +#define DDRSS1_PI_124_DATA 0x00000000 +#define DDRSS1_PI_125_DATA 0x00000008 +#define DDRSS1_PI_126_DATA 0x00000000 +#define DDRSS1_PI_127_DATA 0x00000000 +#define DDRSS1_PI_128_DATA 0x00000000 +#define DDRSS1_PI_129_DATA 0x00000000 +#define DDRSS1_PI_130_DATA 0x00000000 +#define DDRSS1_PI_131_DATA 0x00000000 +#define DDRSS1_PI_132_DATA 0x00000000 +#define DDRSS1_PI_133_DATA 0x00000000 +#define DDRSS1_PI_134_DATA 0x00000002 +#define DDRSS1_PI_135_DATA 0x00000000 +#define DDRSS1_PI_136_DATA 0x00000000 +#define DDRSS1_PI_137_DATA 0x0000000A +#define DDRSS1_PI_138_DATA 0x00000019 +#define DDRSS1_PI_139_DATA 0x00000100 +#define DDRSS1_PI_140_DATA 0x00000000 +#define DDRSS1_PI_141_DATA 0x00000000 +#define DDRSS1_PI_142_DATA 0x00000000 +#define DDRSS1_PI_143_DATA 0x00000000 +#define DDRSS1_PI_144_DATA 0x01000000 +#define DDRSS1_PI_145_DATA 0x00010003 +#define DDRSS1_PI_146_DATA 0x02000101 +#define DDRSS1_PI_147_DATA 0x01030001 +#define DDRSS1_PI_148_DATA 0x00010400 +#define DDRSS1_PI_149_DATA 0x06000105 +#define DDRSS1_PI_150_DATA 0x01070001 +#define DDRSS1_PI_151_DATA 0x00000000 +#define DDRSS1_PI_152_DATA 0x00000000 +#define DDRSS1_PI_153_DATA 0x00000000 +#define DDRSS1_PI_154_DATA 0x00010001 +#define DDRSS1_PI_155_DATA 0x00000000 +#define DDRSS1_PI_156_DATA 0x00000000 +#define DDRSS1_PI_157_DATA 0x00000000 +#define DDRSS1_PI_158_DATA 0x00000000 +#define DDRSS1_PI_159_DATA 0x00000401 +#define DDRSS1_PI_160_DATA 0x00000000 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 +#define DDRSS1_PI_164_DATA 0x00000034 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 +#define DDRSS1_PI_167_DATA 0x02000200 +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 +#define DDRSS1_PI_171_DATA 0x0000032B +#define DDRSS1_PI_172_DATA 0x00001035 +#define DDRSS1_PI_173_DATA 0x0000032B +#define DDRSS1_PI_174_DATA 0x04001035 +#define DDRSS1_PI_175_DATA 0x01010404 +#define DDRSS1_PI_176_DATA 0x00001500 +#define DDRSS1_PI_177_DATA 0x00150015 +#define DDRSS1_PI_178_DATA 0x01000100 +#define DDRSS1_PI_179_DATA 0x00000100 +#define DDRSS1_PI_180_DATA 0x00000000 +#define DDRSS1_PI_181_DATA 0x01010101 +#define DDRSS1_PI_182_DATA 0x00000000 +#define DDRSS1_PI_183_DATA 0x00000000 +#define DDRSS1_PI_184_DATA 0x00000000 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 +#define DDRSS1_PI_187_DATA 0x00040402 +#define DDRSS1_PI_188_DATA 0x000D0035 +#define DDRSS1_PI_189_DATA 0x00218049 +#define DDRSS1_PI_190_DATA 0x00218049 +#define DDRSS1_PI_191_DATA 0x01000101 +#define DDRSS1_PI_192_DATA 0x0004000E +#define DDRSS1_PI_193_DATA 0x00040216 +#define DDRSS1_PI_194_DATA 0x01000216 +#define DDRSS1_PI_195_DATA 0x000F000F +#define DDRSS1_PI_196_DATA 0x02170100 +#define DDRSS1_PI_197_DATA 0x01000217 +#define DDRSS1_PI_198_DATA 0x02170217 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B +#define DDRSS1_PI_201_DATA 0x0A070601 +#define DDRSS1_PI_202_DATA 0x1F130A0D +#define DDRSS1_PI_203_DATA 0x1F130A14 +#define DDRSS1_PI_204_DATA 0x0000C014 +#define DDRSS1_PI_205_DATA 0x00C01000 +#define DDRSS1_PI_206_DATA 0x00C01000 +#define DDRSS1_PI_207_DATA 0x00021000 +#define DDRSS1_PI_208_DATA 0x0024000E +#define DDRSS1_PI_209_DATA 0x00240216 +#define DDRSS1_PI_210_DATA 0x00110216 +#define DDRSS1_PI_211_DATA 0x32000056 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 +#define DDRSS1_PI_214_DATA 0x03013212 +#define DDRSS1_PI_215_DATA 0x00003600 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 +#define DDRSS1_PI_220_DATA 0x0A032001 +#define DDRSS1_PI_221_DATA 0x2C31110A +#define DDRSS1_PI_222_DATA 0x00002918 +#define DDRSS1_PI_223_DATA 0x6000838E +#define DDRSS1_PI_224_DATA 0x1E202008 +#define DDRSS1_PI_225_DATA 0x2C311116 +#define DDRSS1_PI_226_DATA 0x00002918 +#define DDRSS1_PI_227_DATA 0x6000838E +#define DDRSS1_PI_228_DATA 0x1E202008 +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 +#define DDRSS1_PI_235_DATA 0x033B0016 +#define DDRSS1_PI_236_DATA 0x0303033B +#define DDRSS1_PI_237_DATA 0x002AF803 +#define DDRSS1_PI_238_DATA 0x0001ADAF +#define DDRSS1_PI_239_DATA 0x00000005 +#define DDRSS1_PI_240_DATA 0x0000006E +#define DDRSS1_PI_241_DATA 0x00000016 +#define DDRSS1_PI_242_DATA 0x000681C8 +#define DDRSS1_PI_243_DATA 0x0001ADAF +#define DDRSS1_PI_244_DATA 0x00000005 +#define DDRSS1_PI_245_DATA 0x000010A9 +#define DDRSS1_PI_246_DATA 0x0000033B +#define DDRSS1_PI_247_DATA 0x000681C8 +#define DDRSS1_PI_248_DATA 0x0001ADAF +#define DDRSS1_PI_249_DATA 0x00000005 +#define DDRSS1_PI_250_DATA 0x000010A9 +#define DDRSS1_PI_251_DATA 0x0100033B +#define DDRSS1_PI_252_DATA 0x00370040 +#define DDRSS1_PI_253_DATA 0x00010008 +#define DDRSS1_PI_254_DATA 0x08550040 +#define DDRSS1_PI_255_DATA 0x00010040 +#define DDRSS1_PI_256_DATA 0x08550040 +#define DDRSS1_PI_257_DATA 0x00000340 +#define DDRSS1_PI_258_DATA 0x006B006B +#define DDRSS1_PI_259_DATA 0x08040404 +#define DDRSS1_PI_260_DATA 0x00000055 +#define DDRSS1_PI_261_DATA 0x55083C5A +#define DDRSS1_PI_262_DATA 0x5A000000 +#define DDRSS1_PI_263_DATA 0x0055083C +#define DDRSS1_PI_264_DATA 0x3C5A0000 +#define DDRSS1_PI_265_DATA 0x00005508 +#define DDRSS1_PI_266_DATA 0x0C3C5A00 +#define DDRSS1_PI_267_DATA 0x080F0E0D +#define DDRSS1_PI_268_DATA 0x000B0A09 +#define DDRSS1_PI_269_DATA 0x00030201 +#define DDRSS1_PI_270_DATA 0x01000000 +#define DDRSS1_PI_271_DATA 0x04020201 +#define DDRSS1_PI_272_DATA 0x00080804 +#define DDRSS1_PI_273_DATA 0x00000000 +#define DDRSS1_PI_274_DATA 0x00000000 +#define DDRSS1_PI_275_DATA 0x00F30084 +#define DDRSS1_PI_276_DATA 0x00160000 +#define DDRSS1_PI_277_DATA 0x35F33FF4 +#define DDRSS1_PI_278_DATA 0x00160F27 +#define DDRSS1_PI_279_DATA 0x35F33FF4 +#define DDRSS1_PI_280_DATA 0x00160F27 +#define DDRSS1_PI_281_DATA 0x00F30084 +#define DDRSS1_PI_282_DATA 0x00160000 +#define DDRSS1_PI_283_DATA 0x35F33FF4 +#define DDRSS1_PI_284_DATA 0x00160F27 +#define DDRSS1_PI_285_DATA 0x35F33FF4 +#define DDRSS1_PI_286_DATA 0x00160F27 +#define DDRSS1_PI_287_DATA 0x00F30084 +#define DDRSS1_PI_288_DATA 0x00160000 +#define DDRSS1_PI_289_DATA 0x35F33FF4 +#define DDRSS1_PI_290_DATA 0x00160F27 +#define DDRSS1_PI_291_DATA 0x35F33FF4 +#define DDRSS1_PI_292_DATA 0x00160F27 +#define DDRSS1_PI_293_DATA 0x00F30084 +#define DDRSS1_PI_294_DATA 0x00160000 +#define DDRSS1_PI_295_DATA 0x35F33FF4 +#define DDRSS1_PI_296_DATA 0x00160F27 +#define DDRSS1_PI_297_DATA 0x35F33FF4 +#define DDRSS1_PI_298_DATA 0x00160F27 +#define DDRSS1_PI_299_DATA 0x00000000 + +#define DDRSS1_PHY_00_DATA 0x000004F0 +#define DDRSS1_PHY_01_DATA 0x00000000 +#define DDRSS1_PHY_02_DATA 0x00030200 +#define DDRSS1_PHY_03_DATA 0x00000000 +#define DDRSS1_PHY_04_DATA 0x00000000 +#define DDRSS1_PHY_05_DATA 0x01030000 +#define DDRSS1_PHY_06_DATA 0x00010000 +#define DDRSS1_PHY_07_DATA 0x01030004 +#define DDRSS1_PHY_08_DATA 0x01000000 +#define DDRSS1_PHY_09_DATA 0x00000000 +#define DDRSS1_PHY_10_DATA 0x00000000 +#define DDRSS1_PHY_11_DATA 0x01000001 +#define DDRSS1_PHY_12_DATA 0x00000200 +#define DDRSS1_PHY_13_DATA 0x000800C0 +#define DDRSS1_PHY_14_DATA 0x060100CC +#define DDRSS1_PHY_15_DATA 0x00030066 +#define DDRSS1_PHY_16_DATA 0x00000000 +#define DDRSS1_PHY_17_DATA 0x00000301 +#define DDRSS1_PHY_18_DATA 0x0000AAAA +#define DDRSS1_PHY_19_DATA 0x00005555 +#define DDRSS1_PHY_20_DATA 0x0000B5B5 +#define DDRSS1_PHY_21_DATA 0x00004A4A +#define DDRSS1_PHY_22_DATA 0x00005656 +#define DDRSS1_PHY_23_DATA 0x0000A9A9 +#define DDRSS1_PHY_24_DATA 0x0000A9A9 +#define DDRSS1_PHY_25_DATA 0x0000B5B5 +#define DDRSS1_PHY_26_DATA 0x00000000 +#define DDRSS1_PHY_27_DATA 0x00000000 +#define DDRSS1_PHY_28_DATA 0x2A000000 +#define DDRSS1_PHY_29_DATA 0x00000808 +#define DDRSS1_PHY_30_DATA 0x0F000000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 +#define DDRSS1_PHY_33_DATA 0x0C002006 +#define DDRSS1_PHY_34_DATA 0x00000000 +#define DDRSS1_PHY_35_DATA 0x00000000 +#define DDRSS1_PHY_36_DATA 0x55555555 +#define DDRSS1_PHY_37_DATA 0xAAAAAAAA +#define DDRSS1_PHY_38_DATA 0x55555555 +#define DDRSS1_PHY_39_DATA 0xAAAAAAAA +#define DDRSS1_PHY_40_DATA 0x00005555 +#define DDRSS1_PHY_41_DATA 0x01000100 +#define DDRSS1_PHY_42_DATA 0x00800180 +#define DDRSS1_PHY_43_DATA 0x00000001 +#define DDRSS1_PHY_44_DATA 0x00000000 +#define DDRSS1_PHY_45_DATA 0x00000000 +#define DDRSS1_PHY_46_DATA 0x00000000 +#define DDRSS1_PHY_47_DATA 0x00000000 +#define DDRSS1_PHY_48_DATA 0x00000000 +#define DDRSS1_PHY_49_DATA 0x00000000 +#define DDRSS1_PHY_50_DATA 0x00000000 +#define DDRSS1_PHY_51_DATA 0x00000000 +#define DDRSS1_PHY_52_DATA 0x00000000 +#define DDRSS1_PHY_53_DATA 0x00000000 +#define DDRSS1_PHY_54_DATA 0x00000000 +#define DDRSS1_PHY_55_DATA 0x00000000 +#define DDRSS1_PHY_56_DATA 0x00000000 +#define DDRSS1_PHY_57_DATA 0x00000000 +#define DDRSS1_PHY_58_DATA 0x00000000 +#define DDRSS1_PHY_59_DATA 0x00000000 +#define DDRSS1_PHY_60_DATA 0x00000000 +#define DDRSS1_PHY_61_DATA 0x00000000 +#define DDRSS1_PHY_62_DATA 0x00000000 +#define DDRSS1_PHY_63_DATA 0x00000000 +#define DDRSS1_PHY_64_DATA 0x00000000 +#define DDRSS1_PHY_65_DATA 0x00000000 +#define DDRSS1_PHY_66_DATA 0x00000104 +#define DDRSS1_PHY_67_DATA 0x00000120 +#define DDRSS1_PHY_68_DATA 0x00000000 +#define DDRSS1_PHY_69_DATA 0x00000000 +#define DDRSS1_PHY_70_DATA 0x00000000 +#define DDRSS1_PHY_71_DATA 0x00000000 +#define DDRSS1_PHY_72_DATA 0x00000000 +#define DDRSS1_PHY_73_DATA 0x00000000 +#define DDRSS1_PHY_74_DATA 0x00000000 +#define DDRSS1_PHY_75_DATA 0x00000001 +#define DDRSS1_PHY_76_DATA 0x07FF0000 +#define DDRSS1_PHY_77_DATA 0x0080081F +#define DDRSS1_PHY_78_DATA 0x00081020 +#define DDRSS1_PHY_79_DATA 0x04010000 +#define DDRSS1_PHY_80_DATA 0x00000000 +#define DDRSS1_PHY_81_DATA 0x00000000 +#define DDRSS1_PHY_82_DATA 0x00000000 +#define DDRSS1_PHY_83_DATA 0x00000100 +#define DDRSS1_PHY_84_DATA 0x01CC0C01 +#define DDRSS1_PHY_85_DATA 0x1003CC0C +#define DDRSS1_PHY_86_DATA 0x20000140 +#define DDRSS1_PHY_87_DATA 0x07FF0200 +#define DDRSS1_PHY_88_DATA 0x0000DD01 +#define DDRSS1_PHY_89_DATA 0x10100303 +#define DDRSS1_PHY_90_DATA 0x10101010 +#define DDRSS1_PHY_91_DATA 0x10101010 +#define DDRSS1_PHY_92_DATA 0x00021010 +#define DDRSS1_PHY_93_DATA 0x00100010 +#define DDRSS1_PHY_94_DATA 0x00100010 +#define DDRSS1_PHY_95_DATA 0x00100010 +#define DDRSS1_PHY_96_DATA 0x00100010 +#define DDRSS1_PHY_97_DATA 0x00050010 +#define DDRSS1_PHY_98_DATA 0x51517041 +#define DDRSS1_PHY_99_DATA 0x31C06001 +#define DDRSS1_PHY_100_DATA 0x07AB01AB +#define DDRSS1_PHY_101_DATA 0x00C0C001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 +#define DDRSS1_PHY_103_DATA 0x10001000 +#define DDRSS1_PHY_104_DATA 0x0C083E42 +#define DDRSS1_PHY_105_DATA 0x0F0C3701 +#define DDRSS1_PHY_106_DATA 0x01000140 +#define DDRSS1_PHY_107_DATA 0x0C000420 +#define DDRSS1_PHY_108_DATA 0x00000198 +#define DDRSS1_PHY_109_DATA 0x0A0000D0 +#define DDRSS1_PHY_110_DATA 0x00030200 +#define DDRSS1_PHY_111_DATA 0x02800000 +#define DDRSS1_PHY_112_DATA 0x80800000 +#define DDRSS1_PHY_113_DATA 0x000E2010 +#define DDRSS1_PHY_114_DATA 0x76543210 +#define DDRSS1_PHY_115_DATA 0x00000008 +#define DDRSS1_PHY_116_DATA 0x02800280 +#define DDRSS1_PHY_117_DATA 0x02800280 +#define DDRSS1_PHY_118_DATA 0x02800280 +#define DDRSS1_PHY_119_DATA 0x02800280 +#define DDRSS1_PHY_120_DATA 0x00000280 +#define DDRSS1_PHY_121_DATA 0x0000A000 +#define DDRSS1_PHY_122_DATA 0x00A000A0 +#define DDRSS1_PHY_123_DATA 0x00A000A0 +#define DDRSS1_PHY_124_DATA 0x00A000A0 +#define DDRSS1_PHY_125_DATA 0x00A000A0 +#define DDRSS1_PHY_126_DATA 0x00A000A0 +#define DDRSS1_PHY_127_DATA 0x00A000A0 +#define DDRSS1_PHY_128_DATA 0x00A000A0 +#define DDRSS1_PHY_129_DATA 0x00A000A0 +#define DDRSS1_PHY_130_DATA 0x01C200A0 +#define DDRSS1_PHY_131_DATA 0x01A00005 +#define DDRSS1_PHY_132_DATA 0x00000000 +#define DDRSS1_PHY_133_DATA 0x00000000 +#define DDRSS1_PHY_134_DATA 0x00080200 +#define DDRSS1_PHY_135_DATA 0x00000000 +#define DDRSS1_PHY_136_DATA 0x20202000 +#define DDRSS1_PHY_137_DATA 0x20202020 +#define DDRSS1_PHY_138_DATA 0xF0F02020 +#define DDRSS1_PHY_139_DATA 0x00000000 +#define DDRSS1_PHY_140_DATA 0x00000000 +#define DDRSS1_PHY_141_DATA 0x00000000 +#define DDRSS1_PHY_142_DATA 0x00000000 +#define DDRSS1_PHY_143_DATA 0x00000000 +#define DDRSS1_PHY_144_DATA 0x00000000 +#define DDRSS1_PHY_145_DATA 0x00000000 +#define DDRSS1_PHY_146_DATA 0x00000000 +#define DDRSS1_PHY_147_DATA 0x00000000 +#define DDRSS1_PHY_148_DATA 0x00000000 +#define DDRSS1_PHY_149_DATA 0x00000000 +#define DDRSS1_PHY_150_DATA 0x00000000 +#define DDRSS1_PHY_151_DATA 0x00000000 +#define DDRSS1_PHY_152_DATA 0x00000000 +#define DDRSS1_PHY_153_DATA 0x00000000 +#define DDRSS1_PHY_154_DATA 0x00000000 +#define DDRSS1_PHY_155_DATA 0x00000000 +#define DDRSS1_PHY_156_DATA 0x00000000 +#define DDRSS1_PHY_157_DATA 0x00000000 +#define DDRSS1_PHY_158_DATA 0x00000000 +#define DDRSS1_PHY_159_DATA 0x00000000 +#define DDRSS1_PHY_160_DATA 0x00000000 +#define DDRSS1_PHY_161_DATA 0x00000000 +#define DDRSS1_PHY_162_DATA 0x00000000 +#define DDRSS1_PHY_163_DATA 0x00000000 +#define DDRSS1_PHY_164_DATA 0x00000000 +#define DDRSS1_PHY_165_DATA 0x00000000 +#define DDRSS1_PHY_166_DATA 0x00000000 +#define DDRSS1_PHY_167_DATA 0x00000000 +#define DDRSS1_PHY_168_DATA 0x00000000 +#define DDRSS1_PHY_169_DATA 0x00000000 +#define DDRSS1_PHY_170_DATA 0x00000000 +#define DDRSS1_PHY_171_DATA 0x00000000 +#define DDRSS1_PHY_172_DATA 0x00000000 +#define DDRSS1_PHY_173_DATA 0x00000000 +#define DDRSS1_PHY_174_DATA 0x00000000 +#define DDRSS1_PHY_175_DATA 0x00000000 +#define DDRSS1_PHY_176_DATA 0x00000000 +#define DDRSS1_PHY_177_DATA 0x00000000 +#define DDRSS1_PHY_178_DATA 0x00000000 +#define DDRSS1_PHY_179_DATA 0x00000000 +#define DDRSS1_PHY_180_DATA 0x00000000 +#define DDRSS1_PHY_181_DATA 0x00000000 +#define DDRSS1_PHY_182_DATA 0x00000000 +#define DDRSS1_PHY_183_DATA 0x00000000 +#define DDRSS1_PHY_184_DATA 0x00000000 +#define DDRSS1_PHY_185_DATA 0x00000000 +#define DDRSS1_PHY_186_DATA 0x00000000 +#define DDRSS1_PHY_187_DATA 0x00000000 +#define DDRSS1_PHY_188_DATA 0x00000000 +#define DDRSS1_PHY_189_DATA 0x00000000 +#define DDRSS1_PHY_190_DATA 0x00000000 +#define DDRSS1_PHY_191_DATA 0x00000000 +#define DDRSS1_PHY_192_DATA 0x00000000 +#define DDRSS1_PHY_193_DATA 0x00000000 +#define DDRSS1_PHY_194_DATA 0x00000000 +#define DDRSS1_PHY_195_DATA 0x00000000 +#define DDRSS1_PHY_196_DATA 0x00000000 +#define DDRSS1_PHY_197_DATA 0x00000000 +#define DDRSS1_PHY_198_DATA 0x00000000 +#define DDRSS1_PHY_199_DATA 0x00000000 +#define DDRSS1_PHY_200_DATA 0x00000000 +#define DDRSS1_PHY_201_DATA 0x00000000 +#define DDRSS1_PHY_202_DATA 0x00000000 +#define DDRSS1_PHY_203_DATA 0x00000000 +#define DDRSS1_PHY_204_DATA 0x00000000 +#define DDRSS1_PHY_205_DATA 0x00000000 +#define DDRSS1_PHY_206_DATA 0x00000000 +#define DDRSS1_PHY_207_DATA 0x00000000 +#define DDRSS1_PHY_208_DATA 0x00000000 +#define DDRSS1_PHY_209_DATA 0x00000000 +#define DDRSS1_PHY_210_DATA 0x00000000 +#define DDRSS1_PHY_211_DATA 0x00000000 +#define DDRSS1_PHY_212_DATA 0x00000000 +#define DDRSS1_PHY_213_DATA 0x00000000 +#define DDRSS1_PHY_214_DATA 0x00000000 +#define DDRSS1_PHY_215_DATA 0x00000000 +#define DDRSS1_PHY_216_DATA 0x00000000 +#define DDRSS1_PHY_217_DATA 0x00000000 +#define DDRSS1_PHY_218_DATA 0x00000000 +#define DDRSS1_PHY_219_DATA 0x00000000 +#define DDRSS1_PHY_220_DATA 0x00000000 +#define DDRSS1_PHY_221_DATA 0x00000000 +#define DDRSS1_PHY_222_DATA 0x00000000 +#define DDRSS1_PHY_223_DATA 0x00000000 +#define DDRSS1_PHY_224_DATA 0x00000000 +#define DDRSS1_PHY_225_DATA 0x00000000 +#define DDRSS1_PHY_226_DATA 0x00000000 +#define DDRSS1_PHY_227_DATA 0x00000000 +#define DDRSS1_PHY_228_DATA 0x00000000 +#define DDRSS1_PHY_229_DATA 0x00000000 +#define DDRSS1_PHY_230_DATA 0x00000000 +#define DDRSS1_PHY_231_DATA 0x00000000 +#define DDRSS1_PHY_232_DATA 0x00000000 +#define DDRSS1_PHY_233_DATA 0x00000000 +#define DDRSS1_PHY_234_DATA 0x00000000 +#define DDRSS1_PHY_235_DATA 0x00000000 +#define DDRSS1_PHY_236_DATA 0x00000000 +#define DDRSS1_PHY_237_DATA 0x00000000 +#define DDRSS1_PHY_238_DATA 0x00000000 +#define DDRSS1_PHY_239_DATA 0x00000000 +#define DDRSS1_PHY_240_DATA 0x00000000 +#define DDRSS1_PHY_241_DATA 0x00000000 +#define DDRSS1_PHY_242_DATA 0x00000000 +#define DDRSS1_PHY_243_DATA 0x00000000 +#define DDRSS1_PHY_244_DATA 0x00000000 +#define DDRSS1_PHY_245_DATA 0x00000000 +#define DDRSS1_PHY_246_DATA 0x00000000 +#define DDRSS1_PHY_247_DATA 0x00000000 +#define DDRSS1_PHY_248_DATA 0x00000000 +#define DDRSS1_PHY_249_DATA 0x00000000 +#define DDRSS1_PHY_250_DATA 0x00000000 +#define DDRSS1_PHY_251_DATA 0x00000000 +#define DDRSS1_PHY_252_DATA 0x00000000 +#define DDRSS1_PHY_253_DATA 0x00000000 +#define DDRSS1_PHY_254_DATA 0x00000000 +#define DDRSS1_PHY_255_DATA 0x00000000 +#define DDRSS1_PHY_256_DATA 0x000004F0 +#define DDRSS1_PHY_257_DATA 0x00000000 +#define DDRSS1_PHY_258_DATA 0x00030200 +#define DDRSS1_PHY_259_DATA 0x00000000 +#define DDRSS1_PHY_260_DATA 0x00000000 +#define DDRSS1_PHY_261_DATA 0x01030000 +#define DDRSS1_PHY_262_DATA 0x00010000 +#define DDRSS1_PHY_263_DATA 0x01030004 +#define DDRSS1_PHY_264_DATA 0x01000000 +#define DDRSS1_PHY_265_DATA 0x00000000 +#define DDRSS1_PHY_266_DATA 0x00000000 +#define DDRSS1_PHY_267_DATA 0x01000001 +#define DDRSS1_PHY_268_DATA 0x00000200 +#define DDRSS1_PHY_269_DATA 0x000800C0 +#define DDRSS1_PHY_270_DATA 0x060100CC +#define DDRSS1_PHY_271_DATA 0x00030066 +#define DDRSS1_PHY_272_DATA 0x00000000 +#define DDRSS1_PHY_273_DATA 0x00000301 +#define DDRSS1_PHY_274_DATA 0x0000AAAA +#define DDRSS1_PHY_275_DATA 0x00005555 +#define DDRSS1_PHY_276_DATA 0x0000B5B5 +#define DDRSS1_PHY_277_DATA 0x00004A4A +#define DDRSS1_PHY_278_DATA 0x00005656 +#define DDRSS1_PHY_279_DATA 0x0000A9A9 +#define DDRSS1_PHY_280_DATA 0x0000A9A9 +#define DDRSS1_PHY_281_DATA 0x0000B5B5 +#define DDRSS1_PHY_282_DATA 0x00000000 +#define DDRSS1_PHY_283_DATA 0x00000000 +#define DDRSS1_PHY_284_DATA 0x2A000000 +#define DDRSS1_PHY_285_DATA 0x00000808 +#define DDRSS1_PHY_286_DATA 0x0F000000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 +#define DDRSS1_PHY_289_DATA 0x0C002006 +#define DDRSS1_PHY_290_DATA 0x00000000 +#define DDRSS1_PHY_291_DATA 0x00000000 +#define DDRSS1_PHY_292_DATA 0x55555555 +#define DDRSS1_PHY_293_DATA 0xAAAAAAAA +#define DDRSS1_PHY_294_DATA 0x55555555 +#define DDRSS1_PHY_295_DATA 0xAAAAAAAA +#define DDRSS1_PHY_296_DATA 0x00005555 +#define DDRSS1_PHY_297_DATA 0x01000100 +#define DDRSS1_PHY_298_DATA 0x00800180 +#define DDRSS1_PHY_299_DATA 0x00000000 +#define DDRSS1_PHY_300_DATA 0x00000000 +#define DDRSS1_PHY_301_DATA 0x00000000 +#define DDRSS1_PHY_302_DATA 0x00000000 +#define DDRSS1_PHY_303_DATA 0x00000000 +#define DDRSS1_PHY_304_DATA 0x00000000 +#define DDRSS1_PHY_305_DATA 0x00000000 +#define DDRSS1_PHY_306_DATA 0x00000000 +#define DDRSS1_PHY_307_DATA 0x00000000 +#define DDRSS1_PHY_308_DATA 0x00000000 +#define DDRSS1_PHY_309_DATA 0x00000000 +#define DDRSS1_PHY_310_DATA 0x00000000 +#define DDRSS1_PHY_311_DATA 0x00000000 +#define DDRSS1_PHY_312_DATA 0x00000000 +#define DDRSS1_PHY_313_DATA 0x00000000 +#define DDRSS1_PHY_314_DATA 0x00000000 +#define DDRSS1_PHY_315_DATA 0x00000000 +#define DDRSS1_PHY_316_DATA 0x00000000 +#define DDRSS1_PHY_317_DATA 0x00000000 +#define DDRSS1_PHY_318_DATA 0x00000000 +#define DDRSS1_PHY_319_DATA 0x00000000 +#define DDRSS1_PHY_320_DATA 0x00000000 +#define DDRSS1_PHY_321_DATA 0x00000000 +#define DDRSS1_PHY_322_DATA 0x00000104 +#define DDRSS1_PHY_323_DATA 0x00000120 +#define DDRSS1_PHY_324_DATA 0x00000000 +#define DDRSS1_PHY_325_DATA 0x00000000 +#define DDRSS1_PHY_326_DATA 0x00000000 +#define DDRSS1_PHY_327_DATA 0x00000000 +#define DDRSS1_PHY_328_DATA 0x00000000 +#define DDRSS1_PHY_329_DATA 0x00000000 +#define DDRSS1_PHY_330_DATA 0x00000000 +#define DDRSS1_PHY_331_DATA 0x00000001 +#define DDRSS1_PHY_332_DATA 0x07FF0000 +#define DDRSS1_PHY_333_DATA 0x0080081F +#define DDRSS1_PHY_334_DATA 0x00081020 +#define DDRSS1_PHY_335_DATA 0x04010000 +#define DDRSS1_PHY_336_DATA 0x00000000 +#define DDRSS1_PHY_337_DATA 0x00000000 +#define DDRSS1_PHY_338_DATA 0x00000000 +#define DDRSS1_PHY_339_DATA 0x00000100 +#define DDRSS1_PHY_340_DATA 0x01CC0C01 +#define DDRSS1_PHY_341_DATA 0x1003CC0C +#define DDRSS1_PHY_342_DATA 0x20000140 +#define DDRSS1_PHY_343_DATA 0x07FF0200 +#define DDRSS1_PHY_344_DATA 0x0000DD01 +#define DDRSS1_PHY_345_DATA 0x10100303 +#define DDRSS1_PHY_346_DATA 0x10101010 +#define DDRSS1_PHY_347_DATA 0x10101010 +#define DDRSS1_PHY_348_DATA 0x00021010 +#define DDRSS1_PHY_349_DATA 0x00100010 +#define DDRSS1_PHY_350_DATA 0x00100010 +#define DDRSS1_PHY_351_DATA 0x00100010 +#define DDRSS1_PHY_352_DATA 0x00100010 +#define DDRSS1_PHY_353_DATA 0x00050010 +#define DDRSS1_PHY_354_DATA 0x51517041 +#define DDRSS1_PHY_355_DATA 0x31C06001 +#define DDRSS1_PHY_356_DATA 0x07AB01AB +#define DDRSS1_PHY_357_DATA 0x00C0C001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 +#define DDRSS1_PHY_359_DATA 0x10001000 +#define DDRSS1_PHY_360_DATA 0x0C083E42 +#define DDRSS1_PHY_361_DATA 0x0F0C3701 +#define DDRSS1_PHY_362_DATA 0x01000140 +#define DDRSS1_PHY_363_DATA 0x0C000420 +#define DDRSS1_PHY_364_DATA 0x00000198 +#define DDRSS1_PHY_365_DATA 0x0A0000D0 +#define DDRSS1_PHY_366_DATA 0x00030200 +#define DDRSS1_PHY_367_DATA 0x02800000 +#define DDRSS1_PHY_368_DATA 0x80800000 +#define DDRSS1_PHY_369_DATA 0x000E2010 +#define DDRSS1_PHY_370_DATA 0x76543210 +#define DDRSS1_PHY_371_DATA 0x00000008 +#define DDRSS1_PHY_372_DATA 0x02800280 +#define DDRSS1_PHY_373_DATA 0x02800280 +#define DDRSS1_PHY_374_DATA 0x02800280 +#define DDRSS1_PHY_375_DATA 0x02800280 +#define DDRSS1_PHY_376_DATA 0x00000280 +#define DDRSS1_PHY_377_DATA 0x0000A000 +#define DDRSS1_PHY_378_DATA 0x00A000A0 +#define DDRSS1_PHY_379_DATA 0x00A000A0 +#define DDRSS1_PHY_380_DATA 0x00A000A0 +#define DDRSS1_PHY_381_DATA 0x00A000A0 +#define DDRSS1_PHY_382_DATA 0x00A000A0 +#define DDRSS1_PHY_383_DATA 0x00A000A0 +#define DDRSS1_PHY_384_DATA 0x00A000A0 +#define DDRSS1_PHY_385_DATA 0x00A000A0 +#define DDRSS1_PHY_386_DATA 0x01C200A0 +#define DDRSS1_PHY_387_DATA 0x01A00005 +#define DDRSS1_PHY_388_DATA 0x00000000 +#define DDRSS1_PHY_389_DATA 0x00000000 +#define DDRSS1_PHY_390_DATA 0x00080200 +#define DDRSS1_PHY_391_DATA 0x00000000 +#define DDRSS1_PHY_392_DATA 0x20202000 +#define DDRSS1_PHY_393_DATA 0x20202020 +#define DDRSS1_PHY_394_DATA 0xF0F02020 +#define DDRSS1_PHY_395_DATA 0x00000000 +#define DDRSS1_PHY_396_DATA 0x00000000 +#define DDRSS1_PHY_397_DATA 0x00000000 +#define DDRSS1_PHY_398_DATA 0x00000000 +#define DDRSS1_PHY_399_DATA 0x00000000 +#define DDRSS1_PHY_400_DATA 0x00000000 +#define DDRSS1_PHY_401_DATA 0x00000000 +#define DDRSS1_PHY_402_DATA 0x00000000 +#define DDRSS1_PHY_403_DATA 0x00000000 +#define DDRSS1_PHY_404_DATA 0x00000000 +#define DDRSS1_PHY_405_DATA 0x00000000 +#define DDRSS1_PHY_406_DATA 0x00000000 +#define DDRSS1_PHY_407_DATA 0x00000000 +#define DDRSS1_PHY_408_DATA 0x00000000 +#define DDRSS1_PHY_409_DATA 0x00000000 +#define DDRSS1_PHY_410_DATA 0x00000000 +#define DDRSS1_PHY_411_DATA 0x00000000 +#define DDRSS1_PHY_412_DATA 0x00000000 +#define DDRSS1_PHY_413_DATA 0x00000000 +#define DDRSS1_PHY_414_DATA 0x00000000 +#define DDRSS1_PHY_415_DATA 0x00000000 +#define DDRSS1_PHY_416_DATA 0x00000000 +#define DDRSS1_PHY_417_DATA 0x00000000 +#define DDRSS1_PHY_418_DATA 0x00000000 +#define DDRSS1_PHY_419_DATA 0x00000000 +#define DDRSS1_PHY_420_DATA 0x00000000 +#define DDRSS1_PHY_421_DATA 0x00000000 +#define DDRSS1_PHY_422_DATA 0x00000000 +#define DDRSS1_PHY_423_DATA 0x00000000 +#define DDRSS1_PHY_424_DATA 0x00000000 +#define DDRSS1_PHY_425_DATA 0x00000000 +#define DDRSS1_PHY_426_DATA 0x00000000 +#define DDRSS1_PHY_427_DATA 0x00000000 +#define DDRSS1_PHY_428_DATA 0x00000000 +#define DDRSS1_PHY_429_DATA 0x00000000 +#define DDRSS1_PHY_430_DATA 0x00000000 +#define DDRSS1_PHY_431_DATA 0x00000000 +#define DDRSS1_PHY_432_DATA 0x00000000 +#define DDRSS1_PHY_433_DATA 0x00000000 +#define DDRSS1_PHY_434_DATA 0x00000000 +#define DDRSS1_PHY_435_DATA 0x00000000 +#define DDRSS1_PHY_436_DATA 0x00000000 +#define DDRSS1_PHY_437_DATA 0x00000000 +#define DDRSS1_PHY_438_DATA 0x00000000 +#define DDRSS1_PHY_439_DATA 0x00000000 +#define DDRSS1_PHY_440_DATA 0x00000000 +#define DDRSS1_PHY_441_DATA 0x00000000 +#define DDRSS1_PHY_442_DATA 0x00000000 +#define DDRSS1_PHY_443_DATA 0x00000000 +#define DDRSS1_PHY_444_DATA 0x00000000 +#define DDRSS1_PHY_445_DATA 0x00000000 +#define DDRSS1_PHY_446_DATA 0x00000000 +#define DDRSS1_PHY_447_DATA 0x00000000 +#define DDRSS1_PHY_448_DATA 0x00000000 +#define DDRSS1_PHY_449_DATA 0x00000000 +#define DDRSS1_PHY_450_DATA 0x00000000 +#define DDRSS1_PHY_451_DATA 0x00000000 +#define DDRSS1_PHY_452_DATA 0x00000000 +#define DDRSS1_PHY_453_DATA 0x00000000 +#define DDRSS1_PHY_454_DATA 0x00000000 +#define DDRSS1_PHY_455_DATA 0x00000000 +#define DDRSS1_PHY_456_DATA 0x00000000 +#define DDRSS1_PHY_457_DATA 0x00000000 +#define DDRSS1_PHY_458_DATA 0x00000000 +#define DDRSS1_PHY_459_DATA 0x00000000 +#define DDRSS1_PHY_460_DATA 0x00000000 +#define DDRSS1_PHY_461_DATA 0x00000000 +#define DDRSS1_PHY_462_DATA 0x00000000 +#define DDRSS1_PHY_463_DATA 0x00000000 +#define DDRSS1_PHY_464_DATA 0x00000000 +#define DDRSS1_PHY_465_DATA 0x00000000 +#define DDRSS1_PHY_466_DATA 0x00000000 +#define DDRSS1_PHY_467_DATA 0x00000000 +#define DDRSS1_PHY_468_DATA 0x00000000 +#define DDRSS1_PHY_469_DATA 0x00000000 +#define DDRSS1_PHY_470_DATA 0x00000000 +#define DDRSS1_PHY_471_DATA 0x00000000 +#define DDRSS1_PHY_472_DATA 0x00000000 +#define DDRSS1_PHY_473_DATA 0x00000000 +#define DDRSS1_PHY_474_DATA 0x00000000 +#define DDRSS1_PHY_475_DATA 0x00000000 +#define DDRSS1_PHY_476_DATA 0x00000000 +#define DDRSS1_PHY_477_DATA 0x00000000 +#define DDRSS1_PHY_478_DATA 0x00000000 +#define DDRSS1_PHY_479_DATA 0x00000000 +#define DDRSS1_PHY_480_DATA 0x00000000 +#define DDRSS1_PHY_481_DATA 0x00000000 +#define DDRSS1_PHY_482_DATA 0x00000000 +#define DDRSS1_PHY_483_DATA 0x00000000 +#define DDRSS1_PHY_484_DATA 0x00000000 +#define DDRSS1_PHY_485_DATA 0x00000000 +#define DDRSS1_PHY_486_DATA 0x00000000 +#define DDRSS1_PHY_487_DATA 0x00000000 +#define DDRSS1_PHY_488_DATA 0x00000000 +#define DDRSS1_PHY_489_DATA 0x00000000 +#define DDRSS1_PHY_490_DATA 0x00000000 +#define DDRSS1_PHY_491_DATA 0x00000000 +#define DDRSS1_PHY_492_DATA 0x00000000 +#define DDRSS1_PHY_493_DATA 0x00000000 +#define DDRSS1_PHY_494_DATA 0x00000000 +#define DDRSS1_PHY_495_DATA 0x00000000 +#define DDRSS1_PHY_496_DATA 0x00000000 +#define DDRSS1_PHY_497_DATA 0x00000000 +#define DDRSS1_PHY_498_DATA 0x00000000 +#define DDRSS1_PHY_499_DATA 0x00000000 +#define DDRSS1_PHY_500_DATA 0x00000000 +#define DDRSS1_PHY_501_DATA 0x00000000 +#define DDRSS1_PHY_502_DATA 0x00000000 +#define DDRSS1_PHY_503_DATA 0x00000000 +#define DDRSS1_PHY_504_DATA 0x00000000 +#define DDRSS1_PHY_505_DATA 0x00000000 +#define DDRSS1_PHY_506_DATA 0x00000000 +#define DDRSS1_PHY_507_DATA 0x00000000 +#define DDRSS1_PHY_508_DATA 0x00000000 +#define DDRSS1_PHY_509_DATA 0x00000000 +#define DDRSS1_PHY_510_DATA 0x00000000 +#define DDRSS1_PHY_511_DATA 0x00000000 +#define DDRSS1_PHY_512_DATA 0x000004F0 +#define DDRSS1_PHY_513_DATA 0x00000000 +#define DDRSS1_PHY_514_DATA 0x00030200 +#define DDRSS1_PHY_515_DATA 0x00000000 +#define DDRSS1_PHY_516_DATA 0x00000000 +#define DDRSS1_PHY_517_DATA 0x01030000 +#define DDRSS1_PHY_518_DATA 0x00010000 +#define DDRSS1_PHY_519_DATA 0x01030004 +#define DDRSS1_PHY_520_DATA 0x01000000 +#define DDRSS1_PHY_521_DATA 0x00000000 +#define DDRSS1_PHY_522_DATA 0x00000000 +#define DDRSS1_PHY_523_DATA 0x01000001 +#define DDRSS1_PHY_524_DATA 0x00000200 +#define DDRSS1_PHY_525_DATA 0x000800C0 +#define DDRSS1_PHY_526_DATA 0x060100CC +#define DDRSS1_PHY_527_DATA 0x00030066 +#define DDRSS1_PHY_528_DATA 0x00000000 +#define DDRSS1_PHY_529_DATA 0x00000301 +#define DDRSS1_PHY_530_DATA 0x0000AAAA +#define DDRSS1_PHY_531_DATA 0x00005555 +#define DDRSS1_PHY_532_DATA 0x0000B5B5 +#define DDRSS1_PHY_533_DATA 0x00004A4A +#define DDRSS1_PHY_534_DATA 0x00005656 +#define DDRSS1_PHY_535_DATA 0x0000A9A9 +#define DDRSS1_PHY_536_DATA 0x0000A9A9 +#define DDRSS1_PHY_537_DATA 0x0000B5B5 +#define DDRSS1_PHY_538_DATA 0x00000000 +#define DDRSS1_PHY_539_DATA 0x00000000 +#define DDRSS1_PHY_540_DATA 0x2A000000 +#define DDRSS1_PHY_541_DATA 0x00000808 +#define DDRSS1_PHY_542_DATA 0x0F000000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 +#define DDRSS1_PHY_545_DATA 0x0C002006 +#define DDRSS1_PHY_546_DATA 0x00000000 +#define DDRSS1_PHY_547_DATA 0x00000000 +#define DDRSS1_PHY_548_DATA 0x55555555 +#define DDRSS1_PHY_549_DATA 0xAAAAAAAA +#define DDRSS1_PHY_550_DATA 0x55555555 +#define DDRSS1_PHY_551_DATA 0xAAAAAAAA +#define DDRSS1_PHY_552_DATA 0x00005555 +#define DDRSS1_PHY_553_DATA 0x01000100 +#define DDRSS1_PHY_554_DATA 0x00800180 +#define DDRSS1_PHY_555_DATA 0x00000001 +#define DDRSS1_PHY_556_DATA 0x00000000 +#define DDRSS1_PHY_557_DATA 0x00000000 +#define DDRSS1_PHY_558_DATA 0x00000000 +#define DDRSS1_PHY_559_DATA 0x00000000 +#define DDRSS1_PHY_560_DATA 0x00000000 +#define DDRSS1_PHY_561_DATA 0x00000000 +#define DDRSS1_PHY_562_DATA 0x00000000 +#define DDRSS1_PHY_563_DATA 0x00000000 +#define DDRSS1_PHY_564_DATA 0x00000000 +#define DDRSS1_PHY_565_DATA 0x00000000 +#define DDRSS1_PHY_566_DATA 0x00000000 +#define DDRSS1_PHY_567_DATA 0x00000000 +#define DDRSS1_PHY_568_DATA 0x00000000 +#define DDRSS1_PHY_569_DATA 0x00000000 +#define DDRSS1_PHY_570_DATA 0x00000000 +#define DDRSS1_PHY_571_DATA 0x00000000 +#define DDRSS1_PHY_572_DATA 0x00000000 +#define DDRSS1_PHY_573_DATA 0x00000000 +#define DDRSS1_PHY_574_DATA 0x00000000 +#define DDRSS1_PHY_575_DATA 0x00000000 +#define DDRSS1_PHY_576_DATA 0x00000000 +#define DDRSS1_PHY_577_DATA 0x00000000 +#define DDRSS1_PHY_578_DATA 0x00000104 +#define DDRSS1_PHY_579_DATA 0x00000120 +#define DDRSS1_PHY_580_DATA 0x00000000 +#define DDRSS1_PHY_581_DATA 0x00000000 +#define DDRSS1_PHY_582_DATA 0x00000000 +#define DDRSS1_PHY_583_DATA 0x00000000 +#define DDRSS1_PHY_584_DATA 0x00000000 +#define DDRSS1_PHY_585_DATA 0x00000000 +#define DDRSS1_PHY_586_DATA 0x00000000 +#define DDRSS1_PHY_587_DATA 0x00000001 +#define DDRSS1_PHY_588_DATA 0x07FF0000 +#define DDRSS1_PHY_589_DATA 0x0080081F +#define DDRSS1_PHY_590_DATA 0x00081020 +#define DDRSS1_PHY_591_DATA 0x04010000 +#define DDRSS1_PHY_592_DATA 0x00000000 +#define DDRSS1_PHY_593_DATA 0x00000000 +#define DDRSS1_PHY_594_DATA 0x00000000 +#define DDRSS1_PHY_595_DATA 0x00000100 +#define DDRSS1_PHY_596_DATA 0x01CC0C01 +#define DDRSS1_PHY_597_DATA 0x1003CC0C +#define DDRSS1_PHY_598_DATA 0x20000140 +#define DDRSS1_PHY_599_DATA 0x07FF0200 +#define DDRSS1_PHY_600_DATA 0x0000DD01 +#define DDRSS1_PHY_601_DATA 0x10100303 +#define DDRSS1_PHY_602_DATA 0x10101010 +#define DDRSS1_PHY_603_DATA 0x10101010 +#define DDRSS1_PHY_604_DATA 0x00021010 +#define DDRSS1_PHY_605_DATA 0x00100010 +#define DDRSS1_PHY_606_DATA 0x00100010 +#define DDRSS1_PHY_607_DATA 0x00100010 +#define DDRSS1_PHY_608_DATA 0x00100010 +#define DDRSS1_PHY_609_DATA 0x00050010 +#define DDRSS1_PHY_610_DATA 0x51517041 +#define DDRSS1_PHY_611_DATA 0x31C06001 +#define DDRSS1_PHY_612_DATA 0x07AB01AB +#define DDRSS1_PHY_613_DATA 0x00C0C001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 +#define DDRSS1_PHY_615_DATA 0x10001000 +#define DDRSS1_PHY_616_DATA 0x0C083E42 +#define DDRSS1_PHY_617_DATA 0x0F0C3701 +#define DDRSS1_PHY_618_DATA 0x01000140 +#define DDRSS1_PHY_619_DATA 0x0C000420 +#define DDRSS1_PHY_620_DATA 0x00000198 +#define DDRSS1_PHY_621_DATA 0x0A0000D0 +#define DDRSS1_PHY_622_DATA 0x00030200 +#define DDRSS1_PHY_623_DATA 0x02800000 +#define DDRSS1_PHY_624_DATA 0x80800000 +#define DDRSS1_PHY_625_DATA 0x000E2010 +#define DDRSS1_PHY_626_DATA 0x76543210 +#define DDRSS1_PHY_627_DATA 0x00000008 +#define DDRSS1_PHY_628_DATA 0x02800280 +#define DDRSS1_PHY_629_DATA 0x02800280 +#define DDRSS1_PHY_630_DATA 0x02800280 +#define DDRSS1_PHY_631_DATA 0x02800280 +#define DDRSS1_PHY_632_DATA 0x00000280 +#define DDRSS1_PHY_633_DATA 0x0000A000 +#define DDRSS1_PHY_634_DATA 0x00A000A0 +#define DDRSS1_PHY_635_DATA 0x00A000A0 +#define DDRSS1_PHY_636_DATA 0x00A000A0 +#define DDRSS1_PHY_637_DATA 0x00A000A0 +#define DDRSS1_PHY_638_DATA 0x00A000A0 +#define DDRSS1_PHY_639_DATA 0x00A000A0 +#define DDRSS1_PHY_640_DATA 0x00A000A0 +#define DDRSS1_PHY_641_DATA 0x00A000A0 +#define DDRSS1_PHY_642_DATA 0x01C200A0 +#define DDRSS1_PHY_643_DATA 0x01A00005 +#define DDRSS1_PHY_644_DATA 0x00000000 +#define DDRSS1_PHY_645_DATA 0x00000000 +#define DDRSS1_PHY_646_DATA 0x00080200 +#define DDRSS1_PHY_647_DATA 0x00000000 +#define DDRSS1_PHY_648_DATA 0x20202000 +#define DDRSS1_PHY_649_DATA 0x20202020 +#define DDRSS1_PHY_650_DATA 0xF0F02020 +#define DDRSS1_PHY_651_DATA 0x00000000 +#define DDRSS1_PHY_652_DATA 0x00000000 +#define DDRSS1_PHY_653_DATA 0x00000000 +#define DDRSS1_PHY_654_DATA 0x00000000 +#define DDRSS1_PHY_655_DATA 0x00000000 +#define DDRSS1_PHY_656_DATA 0x00000000 +#define DDRSS1_PHY_657_DATA 0x00000000 +#define DDRSS1_PHY_658_DATA 0x00000000 +#define DDRSS1_PHY_659_DATA 0x00000000 +#define DDRSS1_PHY_660_DATA 0x00000000 +#define DDRSS1_PHY_661_DATA 0x00000000 +#define DDRSS1_PHY_662_DATA 0x00000000 +#define DDRSS1_PHY_663_DATA 0x00000000 +#define DDRSS1_PHY_664_DATA 0x00000000 +#define DDRSS1_PHY_665_DATA 0x00000000 +#define DDRSS1_PHY_666_DATA 0x00000000 +#define DDRSS1_PHY_667_DATA 0x00000000 +#define DDRSS1_PHY_668_DATA 0x00000000 +#define DDRSS1_PHY_669_DATA 0x00000000 +#define DDRSS1_PHY_670_DATA 0x00000000 +#define DDRSS1_PHY_671_DATA 0x00000000 +#define DDRSS1_PHY_672_DATA 0x00000000 +#define DDRSS1_PHY_673_DATA 0x00000000 +#define DDRSS1_PHY_674_DATA 0x00000000 +#define DDRSS1_PHY_675_DATA 0x00000000 +#define DDRSS1_PHY_676_DATA 0x00000000 +#define DDRSS1_PHY_677_DATA 0x00000000 +#define DDRSS1_PHY_678_DATA 0x00000000 +#define DDRSS1_PHY_679_DATA 0x00000000 +#define DDRSS1_PHY_680_DATA 0x00000000 +#define DDRSS1_PHY_681_DATA 0x00000000 +#define DDRSS1_PHY_682_DATA 0x00000000 +#define DDRSS1_PHY_683_DATA 0x00000000 +#define DDRSS1_PHY_684_DATA 0x00000000 +#define DDRSS1_PHY_685_DATA 0x00000000 +#define DDRSS1_PHY_686_DATA 0x00000000 +#define DDRSS1_PHY_687_DATA 0x00000000 +#define DDRSS1_PHY_688_DATA 0x00000000 +#define DDRSS1_PHY_689_DATA 0x00000000 +#define DDRSS1_PHY_690_DATA 0x00000000 +#define DDRSS1_PHY_691_DATA 0x00000000 +#define DDRSS1_PHY_692_DATA 0x00000000 +#define DDRSS1_PHY_693_DATA 0x00000000 +#define DDRSS1_PHY_694_DATA 0x00000000 +#define DDRSS1_PHY_695_DATA 0x00000000 +#define DDRSS1_PHY_696_DATA 0x00000000 +#define DDRSS1_PHY_697_DATA 0x00000000 +#define DDRSS1_PHY_698_DATA 0x00000000 +#define DDRSS1_PHY_699_DATA 0x00000000 +#define DDRSS1_PHY_700_DATA 0x00000000 +#define DDRSS1_PHY_701_DATA 0x00000000 +#define DDRSS1_PHY_702_DATA 0x00000000 +#define DDRSS1_PHY_703_DATA 0x00000000 +#define DDRSS1_PHY_704_DATA 0x00000000 +#define DDRSS1_PHY_705_DATA 0x00000000 +#define DDRSS1_PHY_706_DATA 0x00000000 +#define DDRSS1_PHY_707_DATA 0x00000000 +#define DDRSS1_PHY_708_DATA 0x00000000 +#define DDRSS1_PHY_709_DATA 0x00000000 +#define DDRSS1_PHY_710_DATA 0x00000000 +#define DDRSS1_PHY_711_DATA 0x00000000 +#define DDRSS1_PHY_712_DATA 0x00000000 +#define DDRSS1_PHY_713_DATA 0x00000000 +#define DDRSS1_PHY_714_DATA 0x00000000 +#define DDRSS1_PHY_715_DATA 0x00000000 +#define DDRSS1_PHY_716_DATA 0x00000000 +#define DDRSS1_PHY_717_DATA 0x00000000 +#define DDRSS1_PHY_718_DATA 0x00000000 +#define DDRSS1_PHY_719_DATA 0x00000000 +#define DDRSS1_PHY_720_DATA 0x00000000 +#define DDRSS1_PHY_721_DATA 0x00000000 +#define DDRSS1_PHY_722_DATA 0x00000000 +#define DDRSS1_PHY_723_DATA 0x00000000 +#define DDRSS1_PHY_724_DATA 0x00000000 +#define DDRSS1_PHY_725_DATA 0x00000000 +#define DDRSS1_PHY_726_DATA 0x00000000 +#define DDRSS1_PHY_727_DATA 0x00000000 +#define DDRSS1_PHY_728_DATA 0x00000000 +#define DDRSS1_PHY_729_DATA 0x00000000 +#define DDRSS1_PHY_730_DATA 0x00000000 +#define DDRSS1_PHY_731_DATA 0x00000000 +#define DDRSS1_PHY_732_DATA 0x00000000 +#define DDRSS1_PHY_733_DATA 0x00000000 +#define DDRSS1_PHY_734_DATA 0x00000000 +#define DDRSS1_PHY_735_DATA 0x00000000 +#define DDRSS1_PHY_736_DATA 0x00000000 +#define DDRSS1_PHY_737_DATA 0x00000000 +#define DDRSS1_PHY_738_DATA 0x00000000 +#define DDRSS1_PHY_739_DATA 0x00000000 +#define DDRSS1_PHY_740_DATA 0x00000000 +#define DDRSS1_PHY_741_DATA 0x00000000 +#define DDRSS1_PHY_742_DATA 0x00000000 +#define DDRSS1_PHY_743_DATA 0x00000000 +#define DDRSS1_PHY_744_DATA 0x00000000 +#define DDRSS1_PHY_745_DATA 0x00000000 +#define DDRSS1_PHY_746_DATA 0x00000000 +#define DDRSS1_PHY_747_DATA 0x00000000 +#define DDRSS1_PHY_748_DATA 0x00000000 +#define DDRSS1_PHY_749_DATA 0x00000000 +#define DDRSS1_PHY_750_DATA 0x00000000 +#define DDRSS1_PHY_751_DATA 0x00000000 +#define DDRSS1_PHY_752_DATA 0x00000000 +#define DDRSS1_PHY_753_DATA 0x00000000 +#define DDRSS1_PHY_754_DATA 0x00000000 +#define DDRSS1_PHY_755_DATA 0x00000000 +#define DDRSS1_PHY_756_DATA 0x00000000 +#define DDRSS1_PHY_757_DATA 0x00000000 +#define DDRSS1_PHY_758_DATA 0x00000000 +#define DDRSS1_PHY_759_DATA 0x00000000 +#define DDRSS1_PHY_760_DATA 0x00000000 +#define DDRSS1_PHY_761_DATA 0x00000000 +#define DDRSS1_PHY_762_DATA 0x00000000 +#define DDRSS1_PHY_763_DATA 0x00000000 +#define DDRSS1_PHY_764_DATA 0x00000000 +#define DDRSS1_PHY_765_DATA 0x00000000 +#define DDRSS1_PHY_766_DATA 0x00000000 +#define DDRSS1_PHY_767_DATA 0x00000000 +#define DDRSS1_PHY_768_DATA 0x000004F0 +#define DDRSS1_PHY_769_DATA 0x00000000 +#define DDRSS1_PHY_770_DATA 0x00030200 +#define DDRSS1_PHY_771_DATA 0x00000000 +#define DDRSS1_PHY_772_DATA 0x00000000 +#define DDRSS1_PHY_773_DATA 0x01030000 +#define DDRSS1_PHY_774_DATA 0x00010000 +#define DDRSS1_PHY_775_DATA 0x01030004 +#define DDRSS1_PHY_776_DATA 0x01000000 +#define DDRSS1_PHY_777_DATA 0x00000000 +#define DDRSS1_PHY_778_DATA 0x00000000 +#define DDRSS1_PHY_779_DATA 0x01000001 +#define DDRSS1_PHY_780_DATA 0x00000200 +#define DDRSS1_PHY_781_DATA 0x000800C0 +#define DDRSS1_PHY_782_DATA 0x060100CC +#define DDRSS1_PHY_783_DATA 0x00030066 +#define DDRSS1_PHY_784_DATA 0x00000000 +#define DDRSS1_PHY_785_DATA 0x00000301 +#define DDRSS1_PHY_786_DATA 0x0000AAAA +#define DDRSS1_PHY_787_DATA 0x00005555 +#define DDRSS1_PHY_788_DATA 0x0000B5B5 +#define DDRSS1_PHY_789_DATA 0x00004A4A +#define DDRSS1_PHY_790_DATA 0x00005656 +#define DDRSS1_PHY_791_DATA 0x0000A9A9 +#define DDRSS1_PHY_792_DATA 0x0000A9A9 +#define DDRSS1_PHY_793_DATA 0x0000B5B5 +#define DDRSS1_PHY_794_DATA 0x00000000 +#define DDRSS1_PHY_795_DATA 0x00000000 +#define DDRSS1_PHY_796_DATA 0x2A000000 +#define DDRSS1_PHY_797_DATA 0x00000808 +#define DDRSS1_PHY_798_DATA 0x0F000000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 +#define DDRSS1_PHY_801_DATA 0x0C002006 +#define DDRSS1_PHY_802_DATA 0x00000000 +#define DDRSS1_PHY_803_DATA 0x00000000 +#define DDRSS1_PHY_804_DATA 0x55555555 +#define DDRSS1_PHY_805_DATA 0xAAAAAAAA +#define DDRSS1_PHY_806_DATA 0x55555555 +#define DDRSS1_PHY_807_DATA 0xAAAAAAAA +#define DDRSS1_PHY_808_DATA 0x00005555 +#define DDRSS1_PHY_809_DATA 0x01000100 +#define DDRSS1_PHY_810_DATA 0x00800180 +#define DDRSS1_PHY_811_DATA 0x00000000 +#define DDRSS1_PHY_812_DATA 0x00000000 +#define DDRSS1_PHY_813_DATA 0x00000000 +#define DDRSS1_PHY_814_DATA 0x00000000 +#define DDRSS1_PHY_815_DATA 0x00000000 +#define DDRSS1_PHY_816_DATA 0x00000000 +#define DDRSS1_PHY_817_DATA 0x00000000 +#define DDRSS1_PHY_818_DATA 0x00000000 +#define DDRSS1_PHY_819_DATA 0x00000000 +#define DDRSS1_PHY_820_DATA 0x00000000 +#define DDRSS1_PHY_821_DATA 0x00000000 +#define DDRSS1_PHY_822_DATA 0x00000000 +#define DDRSS1_PHY_823_DATA 0x00000000 +#define DDRSS1_PHY_824_DATA 0x00000000 +#define DDRSS1_PHY_825_DATA 0x00000000 +#define DDRSS1_PHY_826_DATA 0x00000000 +#define DDRSS1_PHY_827_DATA 0x00000000 +#define DDRSS1_PHY_828_DATA 0x00000000 +#define DDRSS1_PHY_829_DATA 0x00000000 +#define DDRSS1_PHY_830_DATA 0x00000000 +#define DDRSS1_PHY_831_DATA 0x00000000 +#define DDRSS1_PHY_832_DATA 0x00000000 +#define DDRSS1_PHY_833_DATA 0x00000000 +#define DDRSS1_PHY_834_DATA 0x00000104 +#define DDRSS1_PHY_835_DATA 0x00000120 +#define DDRSS1_PHY_836_DATA 0x00000000 +#define DDRSS1_PHY_837_DATA 0x00000000 +#define DDRSS1_PHY_838_DATA 0x00000000 +#define DDRSS1_PHY_839_DATA 0x00000000 +#define DDRSS1_PHY_840_DATA 0x00000000 +#define DDRSS1_PHY_841_DATA 0x00000000 +#define DDRSS1_PHY_842_DATA 0x00000000 +#define DDRSS1_PHY_843_DATA 0x00000001 +#define DDRSS1_PHY_844_DATA 0x07FF0000 +#define DDRSS1_PHY_845_DATA 0x0080081F +#define DDRSS1_PHY_846_DATA 0x00081020 +#define DDRSS1_PHY_847_DATA 0x04010000 +#define DDRSS1_PHY_848_DATA 0x00000000 +#define DDRSS1_PHY_849_DATA 0x00000000 +#define DDRSS1_PHY_850_DATA 0x00000000 +#define DDRSS1_PHY_851_DATA 0x00000100 +#define DDRSS1_PHY_852_DATA 0x01CC0C01 +#define DDRSS1_PHY_853_DATA 0x1003CC0C +#define DDRSS1_PHY_854_DATA 0x20000140 +#define DDRSS1_PHY_855_DATA 0x07FF0200 +#define DDRSS1_PHY_856_DATA 0x0000DD01 +#define DDRSS1_PHY_857_DATA 0x10100303 +#define DDRSS1_PHY_858_DATA 0x10101010 +#define DDRSS1_PHY_859_DATA 0x10101010 +#define DDRSS1_PHY_860_DATA 0x00021010 +#define DDRSS1_PHY_861_DATA 0x00100010 +#define DDRSS1_PHY_862_DATA 0x00100010 +#define DDRSS1_PHY_863_DATA 0x00100010 +#define DDRSS1_PHY_864_DATA 0x00100010 +#define DDRSS1_PHY_865_DATA 0x00050010 +#define DDRSS1_PHY_866_DATA 0x51517041 +#define DDRSS1_PHY_867_DATA 0x31C06001 +#define DDRSS1_PHY_868_DATA 0x07AB01AB +#define DDRSS1_PHY_869_DATA 0x00C0C001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 +#define DDRSS1_PHY_871_DATA 0x10001000 +#define DDRSS1_PHY_872_DATA 0x0C083E42 +#define DDRSS1_PHY_873_DATA 0x0F0C3701 +#define DDRSS1_PHY_874_DATA 0x01000140 +#define DDRSS1_PHY_875_DATA 0x0C000420 +#define DDRSS1_PHY_876_DATA 0x00000198 +#define DDRSS1_PHY_877_DATA 0x0A0000D0 +#define DDRSS1_PHY_878_DATA 0x00030200 +#define DDRSS1_PHY_879_DATA 0x02800000 +#define DDRSS1_PHY_880_DATA 0x80800000 +#define DDRSS1_PHY_881_DATA 0x000E2010 +#define DDRSS1_PHY_882_DATA 0x76543210 +#define DDRSS1_PHY_883_DATA 0x00000008 +#define DDRSS1_PHY_884_DATA 0x02800280 +#define DDRSS1_PHY_885_DATA 0x02800280 +#define DDRSS1_PHY_886_DATA 0x02800280 +#define DDRSS1_PHY_887_DATA 0x02800280 +#define DDRSS1_PHY_888_DATA 0x00000280 +#define DDRSS1_PHY_889_DATA 0x0000A000 +#define DDRSS1_PHY_890_DATA 0x00A000A0 +#define DDRSS1_PHY_891_DATA 0x00A000A0 +#define DDRSS1_PHY_892_DATA 0x00A000A0 +#define DDRSS1_PHY_893_DATA 0x00A000A0 +#define DDRSS1_PHY_894_DATA 0x00A000A0 +#define DDRSS1_PHY_895_DATA 0x00A000A0 +#define DDRSS1_PHY_896_DATA 0x00A000A0 +#define DDRSS1_PHY_897_DATA 0x00A000A0 +#define DDRSS1_PHY_898_DATA 0x01C200A0 +#define DDRSS1_PHY_899_DATA 0x01A00005 +#define DDRSS1_PHY_900_DATA 0x00000000 +#define DDRSS1_PHY_901_DATA 0x00000000 +#define DDRSS1_PHY_902_DATA 0x00080200 +#define DDRSS1_PHY_903_DATA 0x00000000 +#define DDRSS1_PHY_904_DATA 0x20202000 +#define DDRSS1_PHY_905_DATA 0x20202020 +#define DDRSS1_PHY_906_DATA 0xF0F02020 +#define DDRSS1_PHY_907_DATA 0x00000000 +#define DDRSS1_PHY_908_DATA 0x00000000 +#define DDRSS1_PHY_909_DATA 0x00000000 +#define DDRSS1_PHY_910_DATA 0x00000000 +#define DDRSS1_PHY_911_DATA 0x00000000 +#define DDRSS1_PHY_912_DATA 0x00000000 +#define DDRSS1_PHY_913_DATA 0x00000000 +#define DDRSS1_PHY_914_DATA 0x00000000 +#define DDRSS1_PHY_915_DATA 0x00000000 +#define DDRSS1_PHY_916_DATA 0x00000000 +#define DDRSS1_PHY_917_DATA 0x00000000 +#define DDRSS1_PHY_918_DATA 0x00000000 +#define DDRSS1_PHY_919_DATA 0x00000000 +#define DDRSS1_PHY_920_DATA 0x00000000 +#define DDRSS1_PHY_921_DATA 0x00000000 +#define DDRSS1_PHY_922_DATA 0x00000000 +#define DDRSS1_PHY_923_DATA 0x00000000 +#define DDRSS1_PHY_924_DATA 0x00000000 +#define DDRSS1_PHY_925_DATA 0x00000000 +#define DDRSS1_PHY_926_DATA 0x00000000 +#define DDRSS1_PHY_927_DATA 0x00000000 +#define DDRSS1_PHY_928_DATA 0x00000000 +#define DDRSS1_PHY_929_DATA 0x00000000 +#define DDRSS1_PHY_930_DATA 0x00000000 +#define DDRSS1_PHY_931_DATA 0x00000000 +#define DDRSS1_PHY_932_DATA 0x00000000 +#define DDRSS1_PHY_933_DATA 0x00000000 +#define DDRSS1_PHY_934_DATA 0x00000000 +#define DDRSS1_PHY_935_DATA 0x00000000 +#define DDRSS1_PHY_936_DATA 0x00000000 +#define DDRSS1_PHY_937_DATA 0x00000000 +#define DDRSS1_PHY_938_DATA 0x00000000 +#define DDRSS1_PHY_939_DATA 0x00000000 +#define DDRSS1_PHY_940_DATA 0x00000000 +#define DDRSS1_PHY_941_DATA 0x00000000 +#define DDRSS1_PHY_942_DATA 0x00000000 +#define DDRSS1_PHY_943_DATA 0x00000000 +#define DDRSS1_PHY_944_DATA 0x00000000 +#define DDRSS1_PHY_945_DATA 0x00000000 +#define DDRSS1_PHY_946_DATA 0x00000000 +#define DDRSS1_PHY_947_DATA 0x00000000 +#define DDRSS1_PHY_948_DATA 0x00000000 +#define DDRSS1_PHY_949_DATA 0x00000000 +#define DDRSS1_PHY_950_DATA 0x00000000 +#define DDRSS1_PHY_951_DATA 0x00000000 +#define DDRSS1_PHY_952_DATA 0x00000000 +#define DDRSS1_PHY_953_DATA 0x00000000 +#define DDRSS1_PHY_954_DATA 0x00000000 +#define DDRSS1_PHY_955_DATA 0x00000000 +#define DDRSS1_PHY_956_DATA 0x00000000 +#define DDRSS1_PHY_957_DATA 0x00000000 +#define DDRSS1_PHY_958_DATA 0x00000000 +#define DDRSS1_PHY_959_DATA 0x00000000 +#define DDRSS1_PHY_960_DATA 0x00000000 +#define DDRSS1_PHY_961_DATA 0x00000000 +#define DDRSS1_PHY_962_DATA 0x00000000 +#define DDRSS1_PHY_963_DATA 0x00000000 +#define DDRSS1_PHY_964_DATA 0x00000000 +#define DDRSS1_PHY_965_DATA 0x00000000 +#define DDRSS1_PHY_966_DATA 0x00000000 +#define DDRSS1_PHY_967_DATA 0x00000000 +#define DDRSS1_PHY_968_DATA 0x00000000 +#define DDRSS1_PHY_969_DATA 0x00000000 +#define DDRSS1_PHY_970_DATA 0x00000000 +#define DDRSS1_PHY_971_DATA 0x00000000 +#define DDRSS1_PHY_972_DATA 0x00000000 +#define DDRSS1_PHY_973_DATA 0x00000000 +#define DDRSS1_PHY_974_DATA 0x00000000 +#define DDRSS1_PHY_975_DATA 0x00000000 +#define DDRSS1_PHY_976_DATA 0x00000000 +#define DDRSS1_PHY_977_DATA 0x00000000 +#define DDRSS1_PHY_978_DATA 0x00000000 +#define DDRSS1_PHY_979_DATA 0x00000000 +#define DDRSS1_PHY_980_DATA 0x00000000 +#define DDRSS1_PHY_981_DATA 0x00000000 +#define DDRSS1_PHY_982_DATA 0x00000000 +#define DDRSS1_PHY_983_DATA 0x00000000 +#define DDRSS1_PHY_984_DATA 0x00000000 +#define DDRSS1_PHY_985_DATA 0x00000000 +#define DDRSS1_PHY_986_DATA 0x00000000 +#define DDRSS1_PHY_987_DATA 0x00000000 +#define DDRSS1_PHY_988_DATA 0x00000000 +#define DDRSS1_PHY_989_DATA 0x00000000 +#define DDRSS1_PHY_990_DATA 0x00000000 +#define DDRSS1_PHY_991_DATA 0x00000000 +#define DDRSS1_PHY_992_DATA 0x00000000 +#define DDRSS1_PHY_993_DATA 0x00000000 +#define DDRSS1_PHY_994_DATA 0x00000000 +#define DDRSS1_PHY_995_DATA 0x00000000 +#define DDRSS1_PHY_996_DATA 0x00000000 +#define DDRSS1_PHY_997_DATA 0x00000000 +#define DDRSS1_PHY_998_DATA 0x00000000 +#define DDRSS1_PHY_999_DATA 0x00000000 +#define DDRSS1_PHY_1000_DATA 0x00000000 +#define DDRSS1_PHY_1001_DATA 0x00000000 +#define DDRSS1_PHY_1002_DATA 0x00000000 +#define DDRSS1_PHY_1003_DATA 0x00000000 +#define DDRSS1_PHY_1004_DATA 0x00000000 +#define DDRSS1_PHY_1005_DATA 0x00000000 +#define DDRSS1_PHY_1006_DATA 0x00000000 +#define DDRSS1_PHY_1007_DATA 0x00000000 +#define DDRSS1_PHY_1008_DATA 0x00000000 +#define DDRSS1_PHY_1009_DATA 0x00000000 +#define DDRSS1_PHY_1010_DATA 0x00000000 +#define DDRSS1_PHY_1011_DATA 0x00000000 +#define DDRSS1_PHY_1012_DATA 0x00000000 +#define DDRSS1_PHY_1013_DATA 0x00000000 +#define DDRSS1_PHY_1014_DATA 0x00000000 +#define DDRSS1_PHY_1015_DATA 0x00000000 +#define DDRSS1_PHY_1016_DATA 0x00000000 +#define DDRSS1_PHY_1017_DATA 0x00000000 +#define DDRSS1_PHY_1018_DATA 0x00000000 +#define DDRSS1_PHY_1019_DATA 0x00000000 +#define DDRSS1_PHY_1020_DATA 0x00000000 +#define DDRSS1_PHY_1021_DATA 0x00000000 +#define DDRSS1_PHY_1022_DATA 0x00000000 +#define DDRSS1_PHY_1023_DATA 0x00000000 +#define DDRSS1_PHY_1024_DATA 0x00000000 +#define DDRSS1_PHY_1025_DATA 0x00000000 +#define DDRSS1_PHY_1026_DATA 0x00000000 +#define DDRSS1_PHY_1027_DATA 0x00000000 +#define DDRSS1_PHY_1028_DATA 0x00000000 +#define DDRSS1_PHY_1029_DATA 0x00000100 +#define DDRSS1_PHY_1030_DATA 0x00000200 +#define DDRSS1_PHY_1031_DATA 0x00000000 +#define DDRSS1_PHY_1032_DATA 0x00000000 +#define DDRSS1_PHY_1033_DATA 0x00000000 +#define DDRSS1_PHY_1034_DATA 0x00000000 +#define DDRSS1_PHY_1035_DATA 0x00400000 +#define DDRSS1_PHY_1036_DATA 0x00000080 +#define DDRSS1_PHY_1037_DATA 0x00DCBA98 +#define DDRSS1_PHY_1038_DATA 0x03000000 +#define DDRSS1_PHY_1039_DATA 0x00200000 +#define DDRSS1_PHY_1040_DATA 0x00000000 +#define DDRSS1_PHY_1041_DATA 0x00000000 +#define DDRSS1_PHY_1042_DATA 0x00000000 +#define DDRSS1_PHY_1043_DATA 0x00000000 +#define DDRSS1_PHY_1044_DATA 0x00000000 +#define DDRSS1_PHY_1045_DATA 0x0000002A +#define DDRSS1_PHY_1046_DATA 0x00000015 +#define DDRSS1_PHY_1047_DATA 0x00000015 +#define DDRSS1_PHY_1048_DATA 0x0000002A +#define DDRSS1_PHY_1049_DATA 0x00000033 +#define DDRSS1_PHY_1050_DATA 0x0000000C +#define DDRSS1_PHY_1051_DATA 0x0000000C +#define DDRSS1_PHY_1052_DATA 0x00000033 +#define DDRSS1_PHY_1053_DATA 0x00543210 +#define DDRSS1_PHY_1054_DATA 0x003F0000 +#define DDRSS1_PHY_1055_DATA 0x000F3F3F +#define DDRSS1_PHY_1056_DATA 0x20202003 +#define DDRSS1_PHY_1057_DATA 0x00202020 +#define DDRSS1_PHY_1058_DATA 0x20008008 +#define DDRSS1_PHY_1059_DATA 0x00000810 +#define DDRSS1_PHY_1060_DATA 0x00000F00 +#define DDRSS1_PHY_1061_DATA 0x00000000 +#define DDRSS1_PHY_1062_DATA 0x00000000 +#define DDRSS1_PHY_1063_DATA 0x00000000 +#define DDRSS1_PHY_1064_DATA 0x000305CC +#define DDRSS1_PHY_1065_DATA 0x00030000 +#define DDRSS1_PHY_1066_DATA 0x00000300 +#define DDRSS1_PHY_1067_DATA 0x00000300 +#define DDRSS1_PHY_1068_DATA 0x00000300 +#define DDRSS1_PHY_1069_DATA 0x00000300 +#define DDRSS1_PHY_1070_DATA 0x00000300 +#define DDRSS1_PHY_1071_DATA 0x42080010 +#define DDRSS1_PHY_1072_DATA 0x0000803E +#define DDRSS1_PHY_1073_DATA 0x00000001 +#define DDRSS1_PHY_1074_DATA 0x01000102 +#define DDRSS1_PHY_1075_DATA 0x00008000 +#define DDRSS1_PHY_1076_DATA 0x00000000 +#define DDRSS1_PHY_1077_DATA 0x00000000 +#define DDRSS1_PHY_1078_DATA 0x00000000 +#define DDRSS1_PHY_1079_DATA 0x00000000 +#define DDRSS1_PHY_1080_DATA 0x00000000 +#define DDRSS1_PHY_1081_DATA 0x00000000 +#define DDRSS1_PHY_1082_DATA 0x00000000 +#define DDRSS1_PHY_1083_DATA 0x00000000 +#define DDRSS1_PHY_1084_DATA 0x00000000 +#define DDRSS1_PHY_1085_DATA 0x00000000 +#define DDRSS1_PHY_1086_DATA 0x00000000 +#define DDRSS1_PHY_1087_DATA 0x00000000 +#define DDRSS1_PHY_1088_DATA 0x00000000 +#define DDRSS1_PHY_1089_DATA 0x00000000 +#define DDRSS1_PHY_1090_DATA 0x00000000 +#define DDRSS1_PHY_1091_DATA 0x00000000 +#define DDRSS1_PHY_1092_DATA 0x00000000 +#define DDRSS1_PHY_1093_DATA 0x00000000 +#define DDRSS1_PHY_1094_DATA 0x00000000 +#define DDRSS1_PHY_1095_DATA 0x00000000 +#define DDRSS1_PHY_1096_DATA 0x00000000 +#define DDRSS1_PHY_1097_DATA 0x00000000 +#define DDRSS1_PHY_1098_DATA 0x00000000 +#define DDRSS1_PHY_1099_DATA 0x00000000 +#define DDRSS1_PHY_1100_DATA 0x00000000 +#define DDRSS1_PHY_1101_DATA 0x00000000 +#define DDRSS1_PHY_1102_DATA 0x00000000 +#define DDRSS1_PHY_1103_DATA 0x00000000 +#define DDRSS1_PHY_1104_DATA 0x00000000 +#define DDRSS1_PHY_1105_DATA 0x00000000 +#define DDRSS1_PHY_1106_DATA 0x00000000 +#define DDRSS1_PHY_1107_DATA 0x00000000 +#define DDRSS1_PHY_1108_DATA 0x00000000 +#define DDRSS1_PHY_1109_DATA 0x00000000 +#define DDRSS1_PHY_1110_DATA 0x00000000 +#define DDRSS1_PHY_1111_DATA 0x00000000 +#define DDRSS1_PHY_1112_DATA 0x00000000 +#define DDRSS1_PHY_1113_DATA 0x00000000 +#define DDRSS1_PHY_1114_DATA 0x00000000 +#define DDRSS1_PHY_1115_DATA 0x00000000 +#define DDRSS1_PHY_1116_DATA 0x00000000 +#define DDRSS1_PHY_1117_DATA 0x00000000 +#define DDRSS1_PHY_1118_DATA 0x00000000 +#define DDRSS1_PHY_1119_DATA 0x00000000 +#define DDRSS1_PHY_1120_DATA 0x00000000 +#define DDRSS1_PHY_1121_DATA 0x00000000 +#define DDRSS1_PHY_1122_DATA 0x00000000 +#define DDRSS1_PHY_1123_DATA 0x00000000 +#define DDRSS1_PHY_1124_DATA 0x00000000 +#define DDRSS1_PHY_1125_DATA 0x00000000 +#define DDRSS1_PHY_1126_DATA 0x00000000 +#define DDRSS1_PHY_1127_DATA 0x00000000 +#define DDRSS1_PHY_1128_DATA 0x00000000 +#define DDRSS1_PHY_1129_DATA 0x00000000 +#define DDRSS1_PHY_1130_DATA 0x00000000 +#define DDRSS1_PHY_1131_DATA 0x00000000 +#define DDRSS1_PHY_1132_DATA 0x00000000 +#define DDRSS1_PHY_1133_DATA 0x00000000 +#define DDRSS1_PHY_1134_DATA 0x00000000 +#define DDRSS1_PHY_1135_DATA 0x00000000 +#define DDRSS1_PHY_1136_DATA 0x00000000 +#define DDRSS1_PHY_1137_DATA 0x00000000 +#define DDRSS1_PHY_1138_DATA 0x00000000 +#define DDRSS1_PHY_1139_DATA 0x00000000 +#define DDRSS1_PHY_1140_DATA 0x00000000 +#define DDRSS1_PHY_1141_DATA 0x00000000 +#define DDRSS1_PHY_1142_DATA 0x00000000 +#define DDRSS1_PHY_1143_DATA 0x00000000 +#define DDRSS1_PHY_1144_DATA 0x00000000 +#define DDRSS1_PHY_1145_DATA 0x00000000 +#define DDRSS1_PHY_1146_DATA 0x00000000 +#define DDRSS1_PHY_1147_DATA 0x00000000 +#define DDRSS1_PHY_1148_DATA 0x00000000 +#define DDRSS1_PHY_1149_DATA 0x00000000 +#define DDRSS1_PHY_1150_DATA 0x00000000 +#define DDRSS1_PHY_1151_DATA 0x00000000 +#define DDRSS1_PHY_1152_DATA 0x00000000 +#define DDRSS1_PHY_1153_DATA 0x00000000 +#define DDRSS1_PHY_1154_DATA 0x00000000 +#define DDRSS1_PHY_1155_DATA 0x00000000 +#define DDRSS1_PHY_1156_DATA 0x00000000 +#define DDRSS1_PHY_1157_DATA 0x00000000 +#define DDRSS1_PHY_1158_DATA 0x00000000 +#define DDRSS1_PHY_1159_DATA 0x00000000 +#define DDRSS1_PHY_1160_DATA 0x00000000 +#define DDRSS1_PHY_1161_DATA 0x00000000 +#define DDRSS1_PHY_1162_DATA 0x00000000 +#define DDRSS1_PHY_1163_DATA 0x00000000 +#define DDRSS1_PHY_1164_DATA 0x00000000 +#define DDRSS1_PHY_1165_DATA 0x00000000 +#define DDRSS1_PHY_1166_DATA 0x00000000 +#define DDRSS1_PHY_1167_DATA 0x00000000 +#define DDRSS1_PHY_1168_DATA 0x00000000 +#define DDRSS1_PHY_1169_DATA 0x00000000 +#define DDRSS1_PHY_1170_DATA 0x00000000 +#define DDRSS1_PHY_1171_DATA 0x00000000 +#define DDRSS1_PHY_1172_DATA 0x00000000 +#define DDRSS1_PHY_1173_DATA 0x00000000 +#define DDRSS1_PHY_1174_DATA 0x00000000 +#define DDRSS1_PHY_1175_DATA 0x00000000 +#define DDRSS1_PHY_1176_DATA 0x00000000 +#define DDRSS1_PHY_1177_DATA 0x00000000 +#define DDRSS1_PHY_1178_DATA 0x00000000 +#define DDRSS1_PHY_1179_DATA 0x00000000 +#define DDRSS1_PHY_1180_DATA 0x00000000 +#define DDRSS1_PHY_1181_DATA 0x00000000 +#define DDRSS1_PHY_1182_DATA 0x00000000 +#define DDRSS1_PHY_1183_DATA 0x00000000 +#define DDRSS1_PHY_1184_DATA 0x00000000 +#define DDRSS1_PHY_1185_DATA 0x00000000 +#define DDRSS1_PHY_1186_DATA 0x00000000 +#define DDRSS1_PHY_1187_DATA 0x00000000 +#define DDRSS1_PHY_1188_DATA 0x00000000 +#define DDRSS1_PHY_1189_DATA 0x00000000 +#define DDRSS1_PHY_1190_DATA 0x00000000 +#define DDRSS1_PHY_1191_DATA 0x00000000 +#define DDRSS1_PHY_1192_DATA 0x00000000 +#define DDRSS1_PHY_1193_DATA 0x00000000 +#define DDRSS1_PHY_1194_DATA 0x00000000 +#define DDRSS1_PHY_1195_DATA 0x00000000 +#define DDRSS1_PHY_1196_DATA 0x00000000 +#define DDRSS1_PHY_1197_DATA 0x00000000 +#define DDRSS1_PHY_1198_DATA 0x00000000 +#define DDRSS1_PHY_1199_DATA 0x00000000 +#define DDRSS1_PHY_1200_DATA 0x00000000 +#define DDRSS1_PHY_1201_DATA 0x00000000 +#define DDRSS1_PHY_1202_DATA 0x00000000 +#define DDRSS1_PHY_1203_DATA 0x00000000 +#define DDRSS1_PHY_1204_DATA 0x00000000 +#define DDRSS1_PHY_1205_DATA 0x00000000 +#define DDRSS1_PHY_1206_DATA 0x00000000 +#define DDRSS1_PHY_1207_DATA 0x00000000 +#define DDRSS1_PHY_1208_DATA 0x00000000 +#define DDRSS1_PHY_1209_DATA 0x00000000 +#define DDRSS1_PHY_1210_DATA 0x00000000 +#define DDRSS1_PHY_1211_DATA 0x00000000 +#define DDRSS1_PHY_1212_DATA 0x00000000 +#define DDRSS1_PHY_1213_DATA 0x00000000 +#define DDRSS1_PHY_1214_DATA 0x00000000 +#define DDRSS1_PHY_1215_DATA 0x00000000 +#define DDRSS1_PHY_1216_DATA 0x00000000 +#define DDRSS1_PHY_1217_DATA 0x00000000 +#define DDRSS1_PHY_1218_DATA 0x00000000 +#define DDRSS1_PHY_1219_DATA 0x00000000 +#define DDRSS1_PHY_1220_DATA 0x00000000 +#define DDRSS1_PHY_1221_DATA 0x00000000 +#define DDRSS1_PHY_1222_DATA 0x00000000 +#define DDRSS1_PHY_1223_DATA 0x00000000 +#define DDRSS1_PHY_1224_DATA 0x00000000 +#define DDRSS1_PHY_1225_DATA 0x00000000 +#define DDRSS1_PHY_1226_DATA 0x00000000 +#define DDRSS1_PHY_1227_DATA 0x00000000 +#define DDRSS1_PHY_1228_DATA 0x00000000 +#define DDRSS1_PHY_1229_DATA 0x00000000 +#define DDRSS1_PHY_1230_DATA 0x00000000 +#define DDRSS1_PHY_1231_DATA 0x00000000 +#define DDRSS1_PHY_1232_DATA 0x00000000 +#define DDRSS1_PHY_1233_DATA 0x00000000 +#define DDRSS1_PHY_1234_DATA 0x00000000 +#define DDRSS1_PHY_1235_DATA 0x00000000 +#define DDRSS1_PHY_1236_DATA 0x00000000 +#define DDRSS1_PHY_1237_DATA 0x00000000 +#define DDRSS1_PHY_1238_DATA 0x00000000 +#define DDRSS1_PHY_1239_DATA 0x00000000 +#define DDRSS1_PHY_1240_DATA 0x00000000 +#define DDRSS1_PHY_1241_DATA 0x00000000 +#define DDRSS1_PHY_1242_DATA 0x00000000 +#define DDRSS1_PHY_1243_DATA 0x00000000 +#define DDRSS1_PHY_1244_DATA 0x00000000 +#define DDRSS1_PHY_1245_DATA 0x00000000 +#define DDRSS1_PHY_1246_DATA 0x00000000 +#define DDRSS1_PHY_1247_DATA 0x00000000 +#define DDRSS1_PHY_1248_DATA 0x00000000 +#define DDRSS1_PHY_1249_DATA 0x00000000 +#define DDRSS1_PHY_1250_DATA 0x00000000 +#define DDRSS1_PHY_1251_DATA 0x00000000 +#define DDRSS1_PHY_1252_DATA 0x00000000 +#define DDRSS1_PHY_1253_DATA 0x00000000 +#define DDRSS1_PHY_1254_DATA 0x00000000 +#define DDRSS1_PHY_1255_DATA 0x00000000 +#define DDRSS1_PHY_1256_DATA 0x00000000 +#define DDRSS1_PHY_1257_DATA 0x00000000 +#define DDRSS1_PHY_1258_DATA 0x00000000 +#define DDRSS1_PHY_1259_DATA 0x00000000 +#define DDRSS1_PHY_1260_DATA 0x00000000 +#define DDRSS1_PHY_1261_DATA 0x00000000 +#define DDRSS1_PHY_1262_DATA 0x00000000 +#define DDRSS1_PHY_1263_DATA 0x00000000 +#define DDRSS1_PHY_1264_DATA 0x00000000 +#define DDRSS1_PHY_1265_DATA 0x00000000 +#define DDRSS1_PHY_1266_DATA 0x00000000 +#define DDRSS1_PHY_1267_DATA 0x00000000 +#define DDRSS1_PHY_1268_DATA 0x00000000 +#define DDRSS1_PHY_1269_DATA 0x00000000 +#define DDRSS1_PHY_1270_DATA 0x00000000 +#define DDRSS1_PHY_1271_DATA 0x00000000 +#define DDRSS1_PHY_1272_DATA 0x00000000 +#define DDRSS1_PHY_1273_DATA 0x00000000 +#define DDRSS1_PHY_1274_DATA 0x00000000 +#define DDRSS1_PHY_1275_DATA 0x00000000 +#define DDRSS1_PHY_1276_DATA 0x00000000 +#define DDRSS1_PHY_1277_DATA 0x00000000 +#define DDRSS1_PHY_1278_DATA 0x00000000 +#define DDRSS1_PHY_1279_DATA 0x00000000 +#define DDRSS1_PHY_1280_DATA 0x00000000 +#define DDRSS1_PHY_1281_DATA 0x00010100 +#define DDRSS1_PHY_1282_DATA 0x00000000 +#define DDRSS1_PHY_1283_DATA 0x00000000 +#define DDRSS1_PHY_1284_DATA 0x00050000 +#define DDRSS1_PHY_1285_DATA 0x04000000 +#define DDRSS1_PHY_1286_DATA 0x00000055 +#define DDRSS1_PHY_1287_DATA 0x00000000 +#define DDRSS1_PHY_1288_DATA 0x00000000 +#define DDRSS1_PHY_1289_DATA 0x00000000 +#define DDRSS1_PHY_1290_DATA 0x00000000 +#define DDRSS1_PHY_1291_DATA 0x00002001 +#define DDRSS1_PHY_1292_DATA 0x0000400F +#define DDRSS1_PHY_1293_DATA 0x50020028 +#define DDRSS1_PHY_1294_DATA 0x01010000 +#define DDRSS1_PHY_1295_DATA 0x80080001 +#define DDRSS1_PHY_1296_DATA 0x10200000 +#define DDRSS1_PHY_1297_DATA 0x00000008 +#define DDRSS1_PHY_1298_DATA 0x00000000 +#define DDRSS1_PHY_1299_DATA 0x01090E00 +#define DDRSS1_PHY_1300_DATA 0x00040101 +#define DDRSS1_PHY_1301_DATA 0x0000010F +#define DDRSS1_PHY_1302_DATA 0x00000000 +#define DDRSS1_PHY_1303_DATA 0x00000064 +#define DDRSS1_PHY_1304_DATA 0x00000000 +#define DDRSS1_PHY_1305_DATA 0x01010000 +#define DDRSS1_PHY_1306_DATA 0x01080402 +#define DDRSS1_PHY_1307_DATA 0x01200F02 +#define DDRSS1_PHY_1308_DATA 0x00194280 +#define DDRSS1_PHY_1309_DATA 0x00000004 +#define DDRSS1_PHY_1310_DATA 0x00042000 +#define DDRSS1_PHY_1311_DATA 0x00000000 +#define DDRSS1_PHY_1312_DATA 0x00000000 +#define DDRSS1_PHY_1313_DATA 0x00000000 +#define DDRSS1_PHY_1314_DATA 0x00000000 +#define DDRSS1_PHY_1315_DATA 0x00000000 +#define DDRSS1_PHY_1316_DATA 0x00000000 +#define DDRSS1_PHY_1317_DATA 0x01000000 +#define DDRSS1_PHY_1318_DATA 0x00000705 +#define DDRSS1_PHY_1319_DATA 0x00000054 +#define DDRSS1_PHY_1320_DATA 0x00030820 +#define DDRSS1_PHY_1321_DATA 0x00010820 +#define DDRSS1_PHY_1322_DATA 0x00010820 +#define DDRSS1_PHY_1323_DATA 0x00010820 +#define DDRSS1_PHY_1324_DATA 0x00010820 +#define DDRSS1_PHY_1325_DATA 0x00010820 +#define DDRSS1_PHY_1326_DATA 0x00010820 +#define DDRSS1_PHY_1327_DATA 0x00010820 +#define DDRSS1_PHY_1328_DATA 0x00010820 +#define DDRSS1_PHY_1329_DATA 0x00000000 +#define DDRSS1_PHY_1330_DATA 0x00000074 +#define DDRSS1_PHY_1331_DATA 0x00000400 +#define DDRSS1_PHY_1332_DATA 0x00000108 +#define DDRSS1_PHY_1333_DATA 0x00000000 +#define DDRSS1_PHY_1334_DATA 0x00000000 +#define DDRSS1_PHY_1335_DATA 0x00000000 +#define DDRSS1_PHY_1336_DATA 0x00000000 +#define DDRSS1_PHY_1337_DATA 0x00000000 +#define DDRSS1_PHY_1338_DATA 0x03000000 +#define DDRSS1_PHY_1339_DATA 0x00000000 +#define DDRSS1_PHY_1340_DATA 0x00000000 +#define DDRSS1_PHY_1341_DATA 0x00000000 +#define DDRSS1_PHY_1342_DATA 0x04102006 +#define DDRSS1_PHY_1343_DATA 0x00041020 +#define DDRSS1_PHY_1344_DATA 0x01C98C98 +#define DDRSS1_PHY_1345_DATA 0x3F400000 +#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS1_PHY_1347_DATA 0x0000001F +#define DDRSS1_PHY_1348_DATA 0x00000000 +#define DDRSS1_PHY_1349_DATA 0x00000000 +#define DDRSS1_PHY_1350_DATA 0x00000000 +#define DDRSS1_PHY_1351_DATA 0x00010000 +#define DDRSS1_PHY_1352_DATA 0x00000000 +#define DDRSS1_PHY_1353_DATA 0x00000000 +#define DDRSS1_PHY_1354_DATA 0x00000000 +#define DDRSS1_PHY_1355_DATA 0x00000000 +#define DDRSS1_PHY_1356_DATA 0x76543210 +#define DDRSS1_PHY_1357_DATA 0x00010198 +#define DDRSS1_PHY_1358_DATA 0x00000000 +#define DDRSS1_PHY_1359_DATA 0x00000000 +#define DDRSS1_PHY_1360_DATA 0x00000000 +#define DDRSS1_PHY_1361_DATA 0x00040700 +#define DDRSS1_PHY_1362_DATA 0x00000000 +#define DDRSS1_PHY_1363_DATA 0x00000000 +#define DDRSS1_PHY_1364_DATA 0x00000000 +#define DDRSS1_PHY_1365_DATA 0x00000000 +#define DDRSS1_PHY_1366_DATA 0x00000000 +#define DDRSS1_PHY_1367_DATA 0x00000002 +#define DDRSS1_PHY_1368_DATA 0x00000000 +#define DDRSS1_PHY_1369_DATA 0x00000000 +#define DDRSS1_PHY_1370_DATA 0x00000000 +#define DDRSS1_PHY_1371_DATA 0x00000000 +#define DDRSS1_PHY_1372_DATA 0x00000000 +#define DDRSS1_PHY_1373_DATA 0x00000000 +#define DDRSS1_PHY_1374_DATA 0x00080000 +#define DDRSS1_PHY_1375_DATA 0x000007FF +#define DDRSS1_PHY_1376_DATA 0x00000000 +#define DDRSS1_PHY_1377_DATA 0x00000000 +#define DDRSS1_PHY_1378_DATA 0x00000000 +#define DDRSS1_PHY_1379_DATA 0x00000000 +#define DDRSS1_PHY_1380_DATA 0x00000000 +#define DDRSS1_PHY_1381_DATA 0x00000000 +#define DDRSS1_PHY_1382_DATA 0x000FFFFF +#define DDRSS1_PHY_1383_DATA 0x000FFFFF +#define DDRSS1_PHY_1384_DATA 0x0000FFFF +#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS1_PHY_1386_DATA 0x030FFFFF +#define DDRSS1_PHY_1387_DATA 0x01FFFFFF +#define DDRSS1_PHY_1388_DATA 0x0000FFFF +#define DDRSS1_PHY_1389_DATA 0x00000000 +#define DDRSS1_PHY_1390_DATA 0x00000000 +#define DDRSS1_PHY_1391_DATA 0x00000000 +#define DDRSS1_PHY_1392_DATA 0x00000000 +#define DDRSS1_PHY_1393_DATA 0x0001F7C0 +#define DDRSS1_PHY_1394_DATA 0x00000003 +#define DDRSS1_PHY_1395_DATA 0x00000000 +#define DDRSS1_PHY_1396_DATA 0x00001142 +#define DDRSS1_PHY_1397_DATA 0x040207AB +#define DDRSS1_PHY_1398_DATA 0x01000080 +#define DDRSS1_PHY_1399_DATA 0x03900390 +#define DDRSS1_PHY_1400_DATA 0x03900390 +#define DDRSS1_PHY_1401_DATA 0x00000390 +#define DDRSS1_PHY_1402_DATA 0x00000390 +#define DDRSS1_PHY_1403_DATA 0x00000390 +#define DDRSS1_PHY_1404_DATA 0x00000390 +#define DDRSS1_PHY_1405_DATA 0x00000005 +#define DDRSS1_PHY_1406_DATA 0x01813FCC +#define DDRSS1_PHY_1407_DATA 0x000000CC +#define DDRSS1_PHY_1408_DATA 0x0C000DFF +#define DDRSS1_PHY_1409_DATA 0x30000DFF +#define DDRSS1_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1411_DATA 0x000100F0 +#define DDRSS1_PHY_1412_DATA 0x780DFFCC +#define DDRSS1_PHY_1413_DATA 0x00007E31 +#define DDRSS1_PHY_1414_DATA 0x000CBF11 +#define DDRSS1_PHY_1415_DATA 0x01990010 +#define DDRSS1_PHY_1416_DATA 0x000CBF11 +#define DDRSS1_PHY_1417_DATA 0x01990010 +#define DDRSS1_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1419_DATA 0x00EF00F0 +#define DDRSS1_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS1_PHY_1421_DATA 0x01FF00F0 +#define DDRSS1_PHY_1422_DATA 0x20040006 + +#define DDRSS2_CTL_00_DATA 0x00000B00 +#define DDRSS2_CTL_01_DATA 0x00000000 +#define DDRSS2_CTL_02_DATA 0x00000000 +#define DDRSS2_CTL_03_DATA 0x00000000 +#define DDRSS2_CTL_04_DATA 0x00000000 +#define DDRSS2_CTL_05_DATA 0x00000000 +#define DDRSS2_CTL_06_DATA 0x00000000 +#define DDRSS2_CTL_07_DATA 0x00002AF8 +#define DDRSS2_CTL_08_DATA 0x0001ADAF +#define DDRSS2_CTL_09_DATA 0x00000005 +#define DDRSS2_CTL_10_DATA 0x0000006E +#define DDRSS2_CTL_11_DATA 0x000681C8 +#define DDRSS2_CTL_12_DATA 0x004111C9 +#define DDRSS2_CTL_13_DATA 0x00000005 +#define DDRSS2_CTL_14_DATA 0x000010A9 +#define DDRSS2_CTL_15_DATA 0x000681C8 +#define DDRSS2_CTL_16_DATA 0x004111C9 +#define DDRSS2_CTL_17_DATA 0x00000005 +#define DDRSS2_CTL_18_DATA 0x000010A9 +#define DDRSS2_CTL_19_DATA 0x01010000 +#define DDRSS2_CTL_20_DATA 0x01011001 +#define DDRSS2_CTL_21_DATA 0x02010000 +#define DDRSS2_CTL_22_DATA 0x00020100 +#define DDRSS2_CTL_23_DATA 0x0000000B +#define DDRSS2_CTL_24_DATA 0x0000001C +#define DDRSS2_CTL_25_DATA 0x00000000 +#define DDRSS2_CTL_26_DATA 0x00000000 +#define DDRSS2_CTL_27_DATA 0x03020200 +#define DDRSS2_CTL_28_DATA 0x00005656 +#define DDRSS2_CTL_29_DATA 0x00100000 +#define DDRSS2_CTL_30_DATA 0x00000000 +#define DDRSS2_CTL_31_DATA 0x00000000 +#define DDRSS2_CTL_32_DATA 0x00000000 +#define DDRSS2_CTL_33_DATA 0x00000000 +#define DDRSS2_CTL_34_DATA 0x040C0000 +#define DDRSS2_CTL_35_DATA 0x12501250 +#define DDRSS2_CTL_36_DATA 0x00050804 +#define DDRSS2_CTL_37_DATA 0x09040008 +#define DDRSS2_CTL_38_DATA 0x15000204 +#define DDRSS2_CTL_39_DATA 0x1760008B +#define DDRSS2_CTL_40_DATA 0x1500422B +#define DDRSS2_CTL_41_DATA 0x1760008B +#define DDRSS2_CTL_42_DATA 0x2000422B +#define DDRSS2_CTL_43_DATA 0x000A0A09 +#define DDRSS2_CTL_44_DATA 0x040003C5 +#define DDRSS2_CTL_45_DATA 0x1E161104 +#define DDRSS2_CTL_46_DATA 0x1000922C +#define DDRSS2_CTL_47_DATA 0x1E161110 +#define DDRSS2_CTL_48_DATA 0x1000922C +#define DDRSS2_CTL_49_DATA 0x02030410 +#define DDRSS2_CTL_50_DATA 0x2C060500 +#define DDRSS2_CTL_51_DATA 0x08292C29 +#define DDRSS2_CTL_52_DATA 0x14000E0A +#define DDRSS2_CTL_53_DATA 0x04010A0A +#define DDRSS2_CTL_54_DATA 0x01010004 +#define DDRSS2_CTL_55_DATA 0x0454540A +#define DDRSS2_CTL_56_DATA 0x04313104 +#define DDRSS2_CTL_57_DATA 0x00003131 +#define DDRSS2_CTL_58_DATA 0x00010100 +#define DDRSS2_CTL_59_DATA 0x03010000 +#define DDRSS2_CTL_60_DATA 0x00001508 +#define DDRSS2_CTL_61_DATA 0x00000068 +#define DDRSS2_CTL_62_DATA 0x0000032B +#define DDRSS2_CTL_63_DATA 0x00001035 +#define DDRSS2_CTL_64_DATA 0x0000032B +#define DDRSS2_CTL_65_DATA 0x00001035 +#define DDRSS2_CTL_66_DATA 0x00000005 +#define DDRSS2_CTL_67_DATA 0x00050000 +#define DDRSS2_CTL_68_DATA 0x00CB0005 +#define DDRSS2_CTL_69_DATA 0x00CB0200 +#define DDRSS2_CTL_70_DATA 0x00400200 +#define DDRSS2_CTL_71_DATA 0x00120103 +#define DDRSS2_CTL_72_DATA 0x00100005 +#define DDRSS2_CTL_73_DATA 0x2F080010 +#define DDRSS2_CTL_74_DATA 0x0505012F +#define DDRSS2_CTL_75_DATA 0x0401030A +#define DDRSS2_CTL_76_DATA 0x041E100B +#define DDRSS2_CTL_77_DATA 0x100B0401 +#define DDRSS2_CTL_78_DATA 0x0001041E +#define DDRSS2_CTL_79_DATA 0x00160016 +#define DDRSS2_CTL_80_DATA 0x033B033B +#define DDRSS2_CTL_81_DATA 0x033B033B +#define DDRSS2_CTL_82_DATA 0x03050505 +#define DDRSS2_CTL_83_DATA 0x03010303 +#define DDRSS2_CTL_84_DATA 0x200B100B +#define DDRSS2_CTL_85_DATA 0x04041004 +#define DDRSS2_CTL_86_DATA 0x200B100B +#define DDRSS2_CTL_87_DATA 0x04041004 +#define DDRSS2_CTL_88_DATA 0x03010000 +#define DDRSS2_CTL_89_DATA 0x00010000 +#define DDRSS2_CTL_90_DATA 0x00000000 +#define DDRSS2_CTL_91_DATA 0x00000000 +#define DDRSS2_CTL_92_DATA 0x01000000 +#define DDRSS2_CTL_93_DATA 0x80104002 +#define DDRSS2_CTL_94_DATA 0x00000000 +#define DDRSS2_CTL_95_DATA 0x00040005 +#define DDRSS2_CTL_96_DATA 0x00000000 +#define DDRSS2_CTL_97_DATA 0x00050000 +#define DDRSS2_CTL_98_DATA 0x00000004 +#define DDRSS2_CTL_99_DATA 0x00000000 +#define DDRSS2_CTL_100_DATA 0x00040005 +#define DDRSS2_CTL_101_DATA 0x00000000 +#define DDRSS2_CTL_102_DATA 0x000018C0 +#define DDRSS2_CTL_103_DATA 0x000018C0 +#define DDRSS2_CTL_104_DATA 0x000018C0 +#define DDRSS2_CTL_105_DATA 0x000018C0 +#define DDRSS2_CTL_106_DATA 0x000018C0 +#define DDRSS2_CTL_107_DATA 0x00000000 +#define DDRSS2_CTL_108_DATA 0x000002B5 +#define DDRSS2_CTL_109_DATA 0x00040D40 +#define DDRSS2_CTL_110_DATA 0x00040D40 +#define DDRSS2_CTL_111_DATA 0x00040D40 +#define DDRSS2_CTL_112_DATA 0x00040D40 +#define DDRSS2_CTL_113_DATA 0x00040D40 +#define DDRSS2_CTL_114_DATA 0x00000000 +#define DDRSS2_CTL_115_DATA 0x00007173 +#define DDRSS2_CTL_116_DATA 0x00040D40 +#define DDRSS2_CTL_117_DATA 0x00040D40 +#define DDRSS2_CTL_118_DATA 0x00040D40 +#define DDRSS2_CTL_119_DATA 0x00040D40 +#define DDRSS2_CTL_120_DATA 0x00040D40 +#define DDRSS2_CTL_121_DATA 0x00000000 +#define DDRSS2_CTL_122_DATA 0x00007173 +#define DDRSS2_CTL_123_DATA 0x00000000 +#define DDRSS2_CTL_124_DATA 0x00000000 +#define DDRSS2_CTL_125_DATA 0x00000000 +#define DDRSS2_CTL_126_DATA 0x00000000 +#define DDRSS2_CTL_127_DATA 0x00000000 +#define DDRSS2_CTL_128_DATA 0x00000000 +#define DDRSS2_CTL_129_DATA 0x00000000 +#define DDRSS2_CTL_130_DATA 0x00000000 +#define DDRSS2_CTL_131_DATA 0x0B030500 +#define DDRSS2_CTL_132_DATA 0x00040B04 +#define DDRSS2_CTL_133_DATA 0x0A090000 +#define DDRSS2_CTL_134_DATA 0x0A090701 +#define DDRSS2_CTL_135_DATA 0x0900000E +#define DDRSS2_CTL_136_DATA 0x0907010A +#define DDRSS2_CTL_137_DATA 0x00000E0A +#define DDRSS2_CTL_138_DATA 0x07010A09 +#define DDRSS2_CTL_139_DATA 0x000E0A09 +#define DDRSS2_CTL_140_DATA 0x07000401 +#define DDRSS2_CTL_141_DATA 0x00000000 +#define DDRSS2_CTL_142_DATA 0x00000000 +#define DDRSS2_CTL_143_DATA 0x00000000 +#define DDRSS2_CTL_144_DATA 0x00000000 +#define DDRSS2_CTL_145_DATA 0x00000000 +#define DDRSS2_CTL_146_DATA 0x00000000 +#define DDRSS2_CTL_147_DATA 0x00000000 +#define DDRSS2_CTL_148_DATA 0x08080000 +#define DDRSS2_CTL_149_DATA 0x01000000 +#define DDRSS2_CTL_150_DATA 0x800000C0 +#define DDRSS2_CTL_151_DATA 0x800000C0 +#define DDRSS2_CTL_152_DATA 0x800000C0 +#define DDRSS2_CTL_153_DATA 0x00000000 +#define DDRSS2_CTL_154_DATA 0x00001500 +#define DDRSS2_CTL_155_DATA 0x00000000 +#define DDRSS2_CTL_156_DATA 0x00000001 +#define DDRSS2_CTL_157_DATA 0x00000002 +#define DDRSS2_CTL_158_DATA 0x0000100E +#define DDRSS2_CTL_159_DATA 0x00000000 +#define DDRSS2_CTL_160_DATA 0x00000000 +#define DDRSS2_CTL_161_DATA 0x00000000 +#define DDRSS2_CTL_162_DATA 0x00000000 +#define DDRSS2_CTL_163_DATA 0x00000000 +#define DDRSS2_CTL_164_DATA 0x000B0000 +#define DDRSS2_CTL_165_DATA 0x000E0006 +#define DDRSS2_CTL_166_DATA 0x000E0404 +#define DDRSS2_CTL_167_DATA 0x00D601AB +#define DDRSS2_CTL_168_DATA 0x10100216 +#define DDRSS2_CTL_169_DATA 0x01AB0216 +#define DDRSS2_CTL_170_DATA 0x021600D6 +#define DDRSS2_CTL_171_DATA 0x02161010 +#define DDRSS2_CTL_172_DATA 0x00000000 +#define DDRSS2_CTL_173_DATA 0x00000000 +#define DDRSS2_CTL_174_DATA 0x00000000 +#define DDRSS2_CTL_175_DATA 0x3FF40084 +#define DDRSS2_CTL_176_DATA 0xF3003FF4 +#define DDRSS2_CTL_177_DATA 0x0000F3F3 +#define DDRSS2_CTL_178_DATA 0x35000000 +#define DDRSS2_CTL_179_DATA 0x27270035 +#define DDRSS2_CTL_180_DATA 0x0F0F0000 +#define DDRSS2_CTL_181_DATA 0x16000000 +#define DDRSS2_CTL_182_DATA 0x00841616 +#define DDRSS2_CTL_183_DATA 0x3FF43FF4 +#define DDRSS2_CTL_184_DATA 0xF3F3F300 +#define DDRSS2_CTL_185_DATA 0x00000000 +#define DDRSS2_CTL_186_DATA 0x00353500 +#define DDRSS2_CTL_187_DATA 0x00002727 +#define DDRSS2_CTL_188_DATA 0x00000F0F +#define DDRSS2_CTL_189_DATA 0x16161600 +#define DDRSS2_CTL_190_DATA 0x00000020 +#define DDRSS2_CTL_191_DATA 0x01000000 +#define DDRSS2_CTL_192_DATA 0x00000001 +#define DDRSS2_CTL_193_DATA 0x00000000 +#define DDRSS2_CTL_194_DATA 0x01000000 +#define DDRSS2_CTL_195_DATA 0x00000001 +#define DDRSS2_CTL_196_DATA 0x00000000 +#define DDRSS2_CTL_197_DATA 0x00000000 +#define DDRSS2_CTL_198_DATA 0x00000000 +#define DDRSS2_CTL_199_DATA 0x00000000 +#define DDRSS2_CTL_200_DATA 0x00000000 +#define DDRSS2_CTL_201_DATA 0x00000000 +#define DDRSS2_CTL_202_DATA 0x00000000 +#define DDRSS2_CTL_203_DATA 0x00000000 +#define DDRSS2_CTL_204_DATA 0x00000000 +#define DDRSS2_CTL_205_DATA 0x00000000 +#define DDRSS2_CTL_206_DATA 0x02000000 +#define DDRSS2_CTL_207_DATA 0x01080101 +#define DDRSS2_CTL_208_DATA 0x00000000 +#define DDRSS2_CTL_209_DATA 0x00000000 +#define DDRSS2_CTL_210_DATA 0x00000000 +#define DDRSS2_CTL_211_DATA 0x00000000 +#define DDRSS2_CTL_212_DATA 0x00000000 +#define DDRSS2_CTL_213_DATA 0x00000000 +#define DDRSS2_CTL_214_DATA 0x00000000 +#define DDRSS2_CTL_215_DATA 0x00000000 +#define DDRSS2_CTL_216_DATA 0x00000000 +#define DDRSS2_CTL_217_DATA 0x00000000 +#define DDRSS2_CTL_218_DATA 0x00000000 +#define DDRSS2_CTL_219_DATA 0x00000000 +#define DDRSS2_CTL_220_DATA 0x00000000 +#define DDRSS2_CTL_221_DATA 0x00000000 +#define DDRSS2_CTL_222_DATA 0x00001000 +#define DDRSS2_CTL_223_DATA 0x006403E8 +#define DDRSS2_CTL_224_DATA 0x00000000 +#define DDRSS2_CTL_225_DATA 0x00000000 +#define DDRSS2_CTL_226_DATA 0x00000000 +#define DDRSS2_CTL_227_DATA 0x15110000 +#define DDRSS2_CTL_228_DATA 0x00040C18 +#define DDRSS2_CTL_229_DATA 0xF000C000 +#define DDRSS2_CTL_230_DATA 0x0000F000 +#define DDRSS2_CTL_231_DATA 0x00000000 +#define DDRSS2_CTL_232_DATA 0x00000000 +#define DDRSS2_CTL_233_DATA 0xC0000000 +#define DDRSS2_CTL_234_DATA 0xF000F000 +#define DDRSS2_CTL_235_DATA 0x00000000 +#define DDRSS2_CTL_236_DATA 0x00000000 +#define DDRSS2_CTL_237_DATA 0x00000000 +#define DDRSS2_CTL_238_DATA 0xF000C000 +#define DDRSS2_CTL_239_DATA 0x0000F000 +#define DDRSS2_CTL_240_DATA 0x00000000 +#define DDRSS2_CTL_241_DATA 0x00000000 +#define DDRSS2_CTL_242_DATA 0x00030000 +#define DDRSS2_CTL_243_DATA 0x00000000 +#define DDRSS2_CTL_244_DATA 0x00000000 +#define DDRSS2_CTL_245_DATA 0x00000000 +#define DDRSS2_CTL_246_DATA 0x00000000 +#define DDRSS2_CTL_247_DATA 0x00000000 +#define DDRSS2_CTL_248_DATA 0x00000000 +#define DDRSS2_CTL_249_DATA 0x00000000 +#define DDRSS2_CTL_250_DATA 0x00000000 +#define DDRSS2_CTL_251_DATA 0x00000000 +#define DDRSS2_CTL_252_DATA 0x00000000 +#define DDRSS2_CTL_253_DATA 0x00000000 +#define DDRSS2_CTL_254_DATA 0x00000000 +#define DDRSS2_CTL_255_DATA 0x00000000 +#define DDRSS2_CTL_256_DATA 0x00000000 +#define DDRSS2_CTL_257_DATA 0x01000200 +#define DDRSS2_CTL_258_DATA 0x00370040 +#define DDRSS2_CTL_259_DATA 0x00020008 +#define DDRSS2_CTL_260_DATA 0x00400100 +#define DDRSS2_CTL_261_DATA 0x00400855 +#define DDRSS2_CTL_262_DATA 0x01000200 +#define DDRSS2_CTL_263_DATA 0x08550040 +#define DDRSS2_CTL_264_DATA 0x00000040 +#define DDRSS2_CTL_265_DATA 0x006B0003 +#define DDRSS2_CTL_266_DATA 0x0100006B +#define DDRSS2_CTL_267_DATA 0x03030303 +#define DDRSS2_CTL_268_DATA 0x00000000 +#define DDRSS2_CTL_269_DATA 0x00000202 +#define DDRSS2_CTL_270_DATA 0x00001FFF +#define DDRSS2_CTL_271_DATA 0x3FFF2000 +#define DDRSS2_CTL_272_DATA 0x03FF0000 +#define DDRSS2_CTL_273_DATA 0x000103FF +#define DDRSS2_CTL_274_DATA 0x0FFF0B00 +#define DDRSS2_CTL_275_DATA 0x01010001 +#define DDRSS2_CTL_276_DATA 0x01010101 +#define DDRSS2_CTL_277_DATA 0x01180101 +#define DDRSS2_CTL_278_DATA 0x00030000 +#define DDRSS2_CTL_279_DATA 0x00000000 +#define DDRSS2_CTL_280_DATA 0x00000000 +#define DDRSS2_CTL_281_DATA 0x00000000 +#define DDRSS2_CTL_282_DATA 0x00000000 +#define DDRSS2_CTL_283_DATA 0x00000000 +#define DDRSS2_CTL_284_DATA 0x00000000 +#define DDRSS2_CTL_285_DATA 0x00000000 +#define DDRSS2_CTL_286_DATA 0x00040101 +#define DDRSS2_CTL_287_DATA 0x04010100 +#define DDRSS2_CTL_288_DATA 0x00000000 +#define DDRSS2_CTL_289_DATA 0x00000000 +#define DDRSS2_CTL_290_DATA 0x03030300 +#define DDRSS2_CTL_291_DATA 0x00010101 +#define DDRSS2_CTL_292_DATA 0x00000000 +#define DDRSS2_CTL_293_DATA 0x00000000 +#define DDRSS2_CTL_294_DATA 0x00000000 +#define DDRSS2_CTL_295_DATA 0x00000000 +#define DDRSS2_CTL_296_DATA 0x00000000 +#define DDRSS2_CTL_297_DATA 0xFFFFFFFF +#define DDRSS2_CTL_298_DATA 0x00000FFF +#define DDRSS2_CTL_299_DATA 0x00000000 +#define DDRSS2_CTL_300_DATA 0x00000000 +#define DDRSS2_CTL_301_DATA 0x00000000 +#define DDRSS2_CTL_302_DATA 0x00000000 +#define DDRSS2_CTL_303_DATA 0x00000000 +#define DDRSS2_CTL_304_DATA 0x00000000 +#define DDRSS2_CTL_305_DATA 0x00000000 +#define DDRSS2_CTL_306_DATA 0x00000000 +#define DDRSS2_CTL_307_DATA 0x00000000 +#define DDRSS2_CTL_308_DATA 0x00000000 +#define DDRSS2_CTL_309_DATA 0x00000000 +#define DDRSS2_CTL_310_DATA 0x00000000 +#define DDRSS2_CTL_311_DATA 0x00000000 +#define DDRSS2_CTL_312_DATA 0x00000000 +#define DDRSS2_CTL_313_DATA 0x01000000 +#define DDRSS2_CTL_314_DATA 0x00020201 +#define DDRSS2_CTL_315_DATA 0x01000101 +#define DDRSS2_CTL_316_DATA 0x01010001 +#define DDRSS2_CTL_317_DATA 0x00010101 +#define DDRSS2_CTL_318_DATA 0x050A0A03 +#define DDRSS2_CTL_319_DATA 0x10082323 +#define DDRSS2_CTL_320_DATA 0x00090310 +#define DDRSS2_CTL_321_DATA 0x0B0C030F +#define DDRSS2_CTL_322_DATA 0x0B0C0306 +#define DDRSS2_CTL_323_DATA 0x0C090006 +#define DDRSS2_CTL_324_DATA 0x0100000C +#define DDRSS2_CTL_325_DATA 0x08040801 +#define DDRSS2_CTL_326_DATA 0x00000004 +#define DDRSS2_CTL_327_DATA 0x00000000 +#define DDRSS2_CTL_328_DATA 0x00010000 +#define DDRSS2_CTL_329_DATA 0x00280D00 +#define DDRSS2_CTL_330_DATA 0x00000001 +#define DDRSS2_CTL_331_DATA 0x00030001 +#define DDRSS2_CTL_332_DATA 0x00000000 +#define DDRSS2_CTL_333_DATA 0x00000000 +#define DDRSS2_CTL_334_DATA 0x00000000 +#define DDRSS2_CTL_335_DATA 0x00000000 +#define DDRSS2_CTL_336_DATA 0x00000000 +#define DDRSS2_CTL_337_DATA 0x00000000 +#define DDRSS2_CTL_338_DATA 0x00000000 +#define DDRSS2_CTL_339_DATA 0x00000000 +#define DDRSS2_CTL_340_DATA 0x01000000 +#define DDRSS2_CTL_341_DATA 0x00000001 +#define DDRSS2_CTL_342_DATA 0x00010100 +#define DDRSS2_CTL_343_DATA 0x03030000 +#define DDRSS2_CTL_344_DATA 0x00000000 +#define DDRSS2_CTL_345_DATA 0x00000000 +#define DDRSS2_CTL_346_DATA 0x00000000 +#define DDRSS2_CTL_347_DATA 0x00000000 +#define DDRSS2_CTL_348_DATA 0x00000000 +#define DDRSS2_CTL_349_DATA 0x00000000 +#define DDRSS2_CTL_350_DATA 0x00000000 +#define DDRSS2_CTL_351_DATA 0x00000000 +#define DDRSS2_CTL_352_DATA 0x00000000 +#define DDRSS2_CTL_353_DATA 0x00000000 +#define DDRSS2_CTL_354_DATA 0x00000000 +#define DDRSS2_CTL_355_DATA 0x00000000 +#define DDRSS2_CTL_356_DATA 0x00000000 +#define DDRSS2_CTL_357_DATA 0x00000000 +#define DDRSS2_CTL_358_DATA 0x00000000 +#define DDRSS2_CTL_359_DATA 0x00000000 +#define DDRSS2_CTL_360_DATA 0x000556AA +#define DDRSS2_CTL_361_DATA 0x000AAAAA +#define DDRSS2_CTL_362_DATA 0x000AA955 +#define DDRSS2_CTL_363_DATA 0x00055555 +#define DDRSS2_CTL_364_DATA 0x000B3133 +#define DDRSS2_CTL_365_DATA 0x0004CD33 +#define DDRSS2_CTL_366_DATA 0x0004CECC +#define DDRSS2_CTL_367_DATA 0x000B32CC +#define DDRSS2_CTL_368_DATA 0x00010300 +#define DDRSS2_CTL_369_DATA 0x03000100 +#define DDRSS2_CTL_370_DATA 0x00000000 +#define DDRSS2_CTL_371_DATA 0x00000000 +#define DDRSS2_CTL_372_DATA 0x00000000 +#define DDRSS2_CTL_373_DATA 0x00000000 +#define DDRSS2_CTL_374_DATA 0x00000000 +#define DDRSS2_CTL_375_DATA 0x00000000 +#define DDRSS2_CTL_376_DATA 0x00000000 +#define DDRSS2_CTL_377_DATA 0x00010000 +#define DDRSS2_CTL_378_DATA 0x00000404 +#define DDRSS2_CTL_379_DATA 0x00000000 +#define DDRSS2_CTL_380_DATA 0x00000000 +#define DDRSS2_CTL_381_DATA 0x00000000 +#define DDRSS2_CTL_382_DATA 0x00000000 +#define DDRSS2_CTL_383_DATA 0x00000000 +#define DDRSS2_CTL_384_DATA 0x00000000 +#define DDRSS2_CTL_385_DATA 0x00000000 +#define DDRSS2_CTL_386_DATA 0x00000000 +#define DDRSS2_CTL_387_DATA 0x3A3A1B00 +#define DDRSS2_CTL_388_DATA 0x000A0000 +#define DDRSS2_CTL_389_DATA 0x000000C6 +#define DDRSS2_CTL_390_DATA 0x00000200 +#define DDRSS2_CTL_391_DATA 0x00000200 +#define DDRSS2_CTL_392_DATA 0x00000200 +#define DDRSS2_CTL_393_DATA 0x00000200 +#define DDRSS2_CTL_394_DATA 0x00000270 +#define DDRSS2_CTL_395_DATA 0x000007BC +#define DDRSS2_CTL_396_DATA 0x00000204 +#define DDRSS2_CTL_397_DATA 0x0000206A +#define DDRSS2_CTL_398_DATA 0x00000200 +#define DDRSS2_CTL_399_DATA 0x00000200 +#define DDRSS2_CTL_400_DATA 0x00000200 +#define DDRSS2_CTL_401_DATA 0x00000200 +#define DDRSS2_CTL_402_DATA 0x0000613E +#define DDRSS2_CTL_403_DATA 0x00014424 +#define DDRSS2_CTL_404_DATA 0x00000E19 +#define DDRSS2_CTL_405_DATA 0x0000206A +#define DDRSS2_CTL_406_DATA 0x00000200 +#define DDRSS2_CTL_407_DATA 0x00000200 +#define DDRSS2_CTL_408_DATA 0x00000200 +#define DDRSS2_CTL_409_DATA 0x00000200 +#define DDRSS2_CTL_410_DATA 0x0000613E +#define DDRSS2_CTL_411_DATA 0x00014424 +#define DDRSS2_CTL_412_DATA 0x02020E19 +#define DDRSS2_CTL_413_DATA 0x03030202 +#define DDRSS2_CTL_414_DATA 0x00000022 +#define DDRSS2_CTL_415_DATA 0x00000000 +#define DDRSS2_CTL_416_DATA 0x00000000 +#define DDRSS2_CTL_417_DATA 0x00001403 +#define DDRSS2_CTL_418_DATA 0x000007D0 +#define DDRSS2_CTL_419_DATA 0x00000000 +#define DDRSS2_CTL_420_DATA 0x00000000 +#define DDRSS2_CTL_421_DATA 0x00030000 +#define DDRSS2_CTL_422_DATA 0x0007001F +#define DDRSS2_CTL_423_DATA 0x001B0033 +#define DDRSS2_CTL_424_DATA 0x001B0033 +#define DDRSS2_CTL_425_DATA 0x00000000 +#define DDRSS2_CTL_426_DATA 0x00000000 +#define DDRSS2_CTL_427_DATA 0x02000000 +#define DDRSS2_CTL_428_DATA 0x01000404 +#define DDRSS2_CTL_429_DATA 0x0B220B22 +#define DDRSS2_CTL_430_DATA 0x00000105 +#define DDRSS2_CTL_431_DATA 0x00010101 +#define DDRSS2_CTL_432_DATA 0x00010101 +#define DDRSS2_CTL_433_DATA 0x00010001 +#define DDRSS2_CTL_434_DATA 0x00000101 +#define DDRSS2_CTL_435_DATA 0x02000201 +#define DDRSS2_CTL_436_DATA 0x02010000 +#define DDRSS2_CTL_437_DATA 0x00000200 +#define DDRSS2_CTL_438_DATA 0x28060000 +#define DDRSS2_CTL_439_DATA 0x00000128 +#define DDRSS2_CTL_440_DATA 0xFFFFFFFF +#define DDRSS2_CTL_441_DATA 0xFFFFFFFF +#define DDRSS2_CTL_442_DATA 0x00000000 +#define DDRSS2_CTL_443_DATA 0x00000000 +#define DDRSS2_CTL_444_DATA 0x00000000 +#define DDRSS2_CTL_445_DATA 0x00000000 +#define DDRSS2_CTL_446_DATA 0x00000000 +#define DDRSS2_CTL_447_DATA 0x00000000 +#define DDRSS2_CTL_448_DATA 0x00000000 +#define DDRSS2_CTL_449_DATA 0x00000000 +#define DDRSS2_CTL_450_DATA 0x00000000 +#define DDRSS2_CTL_451_DATA 0x00000000 +#define DDRSS2_CTL_452_DATA 0x00000000 +#define DDRSS2_CTL_453_DATA 0x00000000 +#define DDRSS2_CTL_454_DATA 0x00000000 +#define DDRSS2_CTL_455_DATA 0x00000000 +#define DDRSS2_CTL_456_DATA 0x00000000 +#define DDRSS2_CTL_457_DATA 0x00000000 +#define DDRSS2_CTL_458_DATA 0x00000000 + +#define DDRSS2_PI_00_DATA 0x00000B00 +#define DDRSS2_PI_01_DATA 0x00000000 +#define DDRSS2_PI_02_DATA 0x00000000 +#define DDRSS2_PI_03_DATA 0x00000000 +#define DDRSS2_PI_04_DATA 0x00000000 +#define DDRSS2_PI_05_DATA 0x00000101 +#define DDRSS2_PI_06_DATA 0x00640000 +#define DDRSS2_PI_07_DATA 0x00000001 +#define DDRSS2_PI_08_DATA 0x00000000 +#define DDRSS2_PI_09_DATA 0x00000000 +#define DDRSS2_PI_10_DATA 0x00000000 +#define DDRSS2_PI_11_DATA 0x00000000 +#define DDRSS2_PI_12_DATA 0x00000003 +#define DDRSS2_PI_13_DATA 0x00010001 +#define DDRSS2_PI_14_DATA 0x0800000F +#define DDRSS2_PI_15_DATA 0x00000103 +#define DDRSS2_PI_16_DATA 0x00000005 +#define DDRSS2_PI_17_DATA 0x00000000 +#define DDRSS2_PI_18_DATA 0x00000000 +#define DDRSS2_PI_19_DATA 0x00000000 +#define DDRSS2_PI_20_DATA 0x00000000 +#define DDRSS2_PI_21_DATA 0x00000000 +#define DDRSS2_PI_22_DATA 0x00000000 +#define DDRSS2_PI_23_DATA 0x00000000 +#define DDRSS2_PI_24_DATA 0x00000000 +#define DDRSS2_PI_25_DATA 0x00000000 +#define DDRSS2_PI_26_DATA 0x00010100 +#define DDRSS2_PI_27_DATA 0x00280A00 +#define DDRSS2_PI_28_DATA 0x00000000 +#define DDRSS2_PI_29_DATA 0x0F000000 +#define DDRSS2_PI_30_DATA 0x00003200 +#define DDRSS2_PI_31_DATA 0x00000000 +#define DDRSS2_PI_32_DATA 0x00000000 +#define DDRSS2_PI_33_DATA 0x01010102 +#define DDRSS2_PI_34_DATA 0x00000000 +#define DDRSS2_PI_35_DATA 0x000000AA +#define DDRSS2_PI_36_DATA 0x00000055 +#define DDRSS2_PI_37_DATA 0x000000B5 +#define DDRSS2_PI_38_DATA 0x0000004A +#define DDRSS2_PI_39_DATA 0x00000056 +#define DDRSS2_PI_40_DATA 0x000000A9 +#define DDRSS2_PI_41_DATA 0x000000A9 +#define DDRSS2_PI_42_DATA 0x000000B5 +#define DDRSS2_PI_43_DATA 0x00000000 +#define DDRSS2_PI_44_DATA 0x00000000 +#define DDRSS2_PI_45_DATA 0x000F0F00 +#define DDRSS2_PI_46_DATA 0x0000001B +#define DDRSS2_PI_47_DATA 0x000007D0 +#define DDRSS2_PI_48_DATA 0x00000300 +#define DDRSS2_PI_49_DATA 0x00000000 +#define DDRSS2_PI_50_DATA 0x00000000 +#define DDRSS2_PI_51_DATA 0x01000000 +#define DDRSS2_PI_52_DATA 0x00010101 +#define DDRSS2_PI_53_DATA 0x00000000 +#define DDRSS2_PI_54_DATA 0x00030000 +#define DDRSS2_PI_55_DATA 0x0F000000 +#define DDRSS2_PI_56_DATA 0x00000017 +#define DDRSS2_PI_57_DATA 0x00000000 +#define DDRSS2_PI_58_DATA 0x00000000 +#define DDRSS2_PI_59_DATA 0x00000000 +#define DDRSS2_PI_60_DATA 0x0A0A140A +#define DDRSS2_PI_61_DATA 0x10020201 +#define DDRSS2_PI_62_DATA 0x00020805 +#define DDRSS2_PI_63_DATA 0x01000404 +#define DDRSS2_PI_64_DATA 0x00000000 +#define DDRSS2_PI_65_DATA 0x00000000 +#define DDRSS2_PI_66_DATA 0x00000100 +#define DDRSS2_PI_67_DATA 0x0002020F +#define DDRSS2_PI_68_DATA 0x00340000 +#define DDRSS2_PI_69_DATA 0x00000000 +#define DDRSS2_PI_70_DATA 0x00000000 +#define DDRSS2_PI_71_DATA 0x0000FFFF +#define DDRSS2_PI_72_DATA 0x01000000 +#define DDRSS2_PI_73_DATA 0x00080000 +#define DDRSS2_PI_74_DATA 0x02000200 +#define DDRSS2_PI_75_DATA 0x01000100 +#define DDRSS2_PI_76_DATA 0x01000000 +#define DDRSS2_PI_77_DATA 0x02000200 +#define DDRSS2_PI_78_DATA 0x00000200 +#define DDRSS2_PI_79_DATA 0x00000000 +#define DDRSS2_PI_80_DATA 0x00000000 +#define DDRSS2_PI_81_DATA 0x00000000 +#define DDRSS2_PI_82_DATA 0x00000000 +#define DDRSS2_PI_83_DATA 0x00000000 +#define DDRSS2_PI_84_DATA 0x00000000 +#define DDRSS2_PI_85_DATA 0x00000000 +#define DDRSS2_PI_86_DATA 0x00000000 +#define DDRSS2_PI_87_DATA 0x00000000 +#define DDRSS2_PI_88_DATA 0x00000000 +#define DDRSS2_PI_89_DATA 0x00000000 +#define DDRSS2_PI_90_DATA 0x00000000 +#define DDRSS2_PI_91_DATA 0x00000400 +#define DDRSS2_PI_92_DATA 0x02010000 +#define DDRSS2_PI_93_DATA 0x00080003 +#define DDRSS2_PI_94_DATA 0x00080000 +#define DDRSS2_PI_95_DATA 0x00000001 +#define DDRSS2_PI_96_DATA 0x00000000 +#define DDRSS2_PI_97_DATA 0x0000AA00 +#define DDRSS2_PI_98_DATA 0x00000000 +#define DDRSS2_PI_99_DATA 0x00000000 +#define DDRSS2_PI_100_DATA 0x00010000 +#define DDRSS2_PI_101_DATA 0x00000000 +#define DDRSS2_PI_102_DATA 0x00000000 +#define DDRSS2_PI_103_DATA 0x00000000 +#define DDRSS2_PI_104_DATA 0x00000000 +#define DDRSS2_PI_105_DATA 0x00000000 +#define DDRSS2_PI_106_DATA 0x00000000 +#define DDRSS2_PI_107_DATA 0x00000000 +#define DDRSS2_PI_108_DATA 0x00000000 +#define DDRSS2_PI_109_DATA 0x00000000 +#define DDRSS2_PI_110_DATA 0x00000000 +#define DDRSS2_PI_111_DATA 0x00000000 +#define DDRSS2_PI_112_DATA 0x00000000 +#define DDRSS2_PI_113_DATA 0x00000000 +#define DDRSS2_PI_114_DATA 0x00000000 +#define DDRSS2_PI_115_DATA 0x00000000 +#define DDRSS2_PI_116_DATA 0x00000000 +#define DDRSS2_PI_117_DATA 0x00000000 +#define DDRSS2_PI_118_DATA 0x00000000 +#define DDRSS2_PI_119_DATA 0x00000000 +#define DDRSS2_PI_120_DATA 0x00000000 +#define DDRSS2_PI_121_DATA 0x00000000 +#define DDRSS2_PI_122_DATA 0x00000000 +#define DDRSS2_PI_123_DATA 0x00000000 +#define DDRSS2_PI_124_DATA 0x00000000 +#define DDRSS2_PI_125_DATA 0x00000008 +#define DDRSS2_PI_126_DATA 0x00000000 +#define DDRSS2_PI_127_DATA 0x00000000 +#define DDRSS2_PI_128_DATA 0x00000000 +#define DDRSS2_PI_129_DATA 0x00000000 +#define DDRSS2_PI_130_DATA 0x00000000 +#define DDRSS2_PI_131_DATA 0x00000000 +#define DDRSS2_PI_132_DATA 0x00000000 +#define DDRSS2_PI_133_DATA 0x00000000 +#define DDRSS2_PI_134_DATA 0x00000002 +#define DDRSS2_PI_135_DATA 0x00000000 +#define DDRSS2_PI_136_DATA 0x00000000 +#define DDRSS2_PI_137_DATA 0x0000000A +#define DDRSS2_PI_138_DATA 0x00000019 +#define DDRSS2_PI_139_DATA 0x00000100 +#define DDRSS2_PI_140_DATA 0x00000000 +#define DDRSS2_PI_141_DATA 0x00000000 +#define DDRSS2_PI_142_DATA 0x00000000 +#define DDRSS2_PI_143_DATA 0x00000000 +#define DDRSS2_PI_144_DATA 0x01000000 +#define DDRSS2_PI_145_DATA 0x00010003 +#define DDRSS2_PI_146_DATA 0x02000101 +#define DDRSS2_PI_147_DATA 0x01030001 +#define DDRSS2_PI_148_DATA 0x00010400 +#define DDRSS2_PI_149_DATA 0x06000105 +#define DDRSS2_PI_150_DATA 0x01070001 +#define DDRSS2_PI_151_DATA 0x00000000 +#define DDRSS2_PI_152_DATA 0x00000000 +#define DDRSS2_PI_153_DATA 0x00000000 +#define DDRSS2_PI_154_DATA 0x00010001 +#define DDRSS2_PI_155_DATA 0x00000000 +#define DDRSS2_PI_156_DATA 0x00000000 +#define DDRSS2_PI_157_DATA 0x00000000 +#define DDRSS2_PI_158_DATA 0x00000000 +#define DDRSS2_PI_159_DATA 0x00000401 +#define DDRSS2_PI_160_DATA 0x00000000 +#define DDRSS2_PI_161_DATA 0x05010000 +#define DDRSS2_PI_162_DATA 0x00000001 +#define DDRSS2_PI_163_DATA 0x2B2B0201 +#define DDRSS2_PI_164_DATA 0x00000034 +#define DDRSS2_PI_165_DATA 0x00000068 +#define DDRSS2_PI_166_DATA 0x00020068 +#define DDRSS2_PI_167_DATA 0x02000200 +#define DDRSS2_PI_168_DATA 0x50120C04 +#define DDRSS2_PI_169_DATA 0x00155012 +#define DDRSS2_PI_170_DATA 0x00000068 +#define DDRSS2_PI_171_DATA 0x0000032B +#define DDRSS2_PI_172_DATA 0x00001035 +#define DDRSS2_PI_173_DATA 0x0000032B +#define DDRSS2_PI_174_DATA 0x04001035 +#define DDRSS2_PI_175_DATA 0x01010404 +#define DDRSS2_PI_176_DATA 0x00001500 +#define DDRSS2_PI_177_DATA 0x00150015 +#define DDRSS2_PI_178_DATA 0x01000100 +#define DDRSS2_PI_179_DATA 0x00000100 +#define DDRSS2_PI_180_DATA 0x00000000 +#define DDRSS2_PI_181_DATA 0x01010101 +#define DDRSS2_PI_182_DATA 0x00000000 +#define DDRSS2_PI_183_DATA 0x00000000 +#define DDRSS2_PI_184_DATA 0x00000000 +#define DDRSS2_PI_185_DATA 0x19040000 +#define DDRSS2_PI_186_DATA 0x0E0E0219 +#define DDRSS2_PI_187_DATA 0x00040402 +#define DDRSS2_PI_188_DATA 0x000D0035 +#define DDRSS2_PI_189_DATA 0x00218049 +#define DDRSS2_PI_190_DATA 0x00218049 +#define DDRSS2_PI_191_DATA 0x01000101 +#define DDRSS2_PI_192_DATA 0x0004000E +#define DDRSS2_PI_193_DATA 0x00040216 +#define DDRSS2_PI_194_DATA 0x01000216 +#define DDRSS2_PI_195_DATA 0x000F000F +#define DDRSS2_PI_196_DATA 0x02170100 +#define DDRSS2_PI_197_DATA 0x01000217 +#define DDRSS2_PI_198_DATA 0x02170217 +#define DDRSS2_PI_199_DATA 0x2F1B3200 +#define DDRSS2_PI_200_DATA 0x01012F1B +#define DDRSS2_PI_201_DATA 0x0A070601 +#define DDRSS2_PI_202_DATA 0x1F130A0D +#define DDRSS2_PI_203_DATA 0x1F130A14 +#define DDRSS2_PI_204_DATA 0x0000C014 +#define DDRSS2_PI_205_DATA 0x00C01000 +#define DDRSS2_PI_206_DATA 0x00C01000 +#define DDRSS2_PI_207_DATA 0x00021000 +#define DDRSS2_PI_208_DATA 0x0024000E +#define DDRSS2_PI_209_DATA 0x00240216 +#define DDRSS2_PI_210_DATA 0x00110216 +#define DDRSS2_PI_211_DATA 0x32000056 +#define DDRSS2_PI_212_DATA 0x00000101 +#define DDRSS2_PI_213_DATA 0x005F0036 +#define DDRSS2_PI_214_DATA 0x03013212 +#define DDRSS2_PI_215_DATA 0x00003600 +#define DDRSS2_PI_216_DATA 0x3212005F +#define DDRSS2_PI_217_DATA 0x09000001 +#define DDRSS2_PI_218_DATA 0x06010504 +#define DDRSS2_PI_219_DATA 0x04000364 +#define DDRSS2_PI_220_DATA 0x0A032001 +#define DDRSS2_PI_221_DATA 0x2C31110A +#define DDRSS2_PI_222_DATA 0x00002918 +#define DDRSS2_PI_223_DATA 0x6000838E +#define DDRSS2_PI_224_DATA 0x1E202008 +#define DDRSS2_PI_225_DATA 0x2C311116 +#define DDRSS2_PI_226_DATA 0x00002918 +#define DDRSS2_PI_227_DATA 0x6000838E +#define DDRSS2_PI_228_DATA 0x1E202008 +#define DDRSS2_PI_229_DATA 0x0000C616 +#define DDRSS2_PI_230_DATA 0x000007BC +#define DDRSS2_PI_231_DATA 0x0000206A +#define DDRSS2_PI_232_DATA 0x00014424 +#define DDRSS2_PI_233_DATA 0x0000206A +#define DDRSS2_PI_234_DATA 0x00014424 +#define DDRSS2_PI_235_DATA 0x033B0016 +#define DDRSS2_PI_236_DATA 0x0303033B +#define DDRSS2_PI_237_DATA 0x002AF803 +#define DDRSS2_PI_238_DATA 0x0001ADAF +#define DDRSS2_PI_239_DATA 0x00000005 +#define DDRSS2_PI_240_DATA 0x0000006E +#define DDRSS2_PI_241_DATA 0x00000016 +#define DDRSS2_PI_242_DATA 0x000681C8 +#define DDRSS2_PI_243_DATA 0x0001ADAF +#define DDRSS2_PI_244_DATA 0x00000005 +#define DDRSS2_PI_245_DATA 0x000010A9 +#define DDRSS2_PI_246_DATA 0x0000033B +#define DDRSS2_PI_247_DATA 0x000681C8 +#define DDRSS2_PI_248_DATA 0x0001ADAF +#define DDRSS2_PI_249_DATA 0x00000005 +#define DDRSS2_PI_250_DATA 0x000010A9 +#define DDRSS2_PI_251_DATA 0x0100033B +#define DDRSS2_PI_252_DATA 0x00370040 +#define DDRSS2_PI_253_DATA 0x00010008 +#define DDRSS2_PI_254_DATA 0x08550040 +#define DDRSS2_PI_255_DATA 0x00010040 +#define DDRSS2_PI_256_DATA 0x08550040 +#define DDRSS2_PI_257_DATA 0x00000340 +#define DDRSS2_PI_258_DATA 0x006B006B +#define DDRSS2_PI_259_DATA 0x08040404 +#define DDRSS2_PI_260_DATA 0x00000055 +#define DDRSS2_PI_261_DATA 0x55083C5A +#define DDRSS2_PI_262_DATA 0x5A000000 +#define DDRSS2_PI_263_DATA 0x0055083C +#define DDRSS2_PI_264_DATA 0x3C5A0000 +#define DDRSS2_PI_265_DATA 0x00005508 +#define DDRSS2_PI_266_DATA 0x0C3C5A00 +#define DDRSS2_PI_267_DATA 0x080F0E0D +#define DDRSS2_PI_268_DATA 0x000B0A09 +#define DDRSS2_PI_269_DATA 0x00030201 +#define DDRSS2_PI_270_DATA 0x01000000 +#define DDRSS2_PI_271_DATA 0x04020201 +#define DDRSS2_PI_272_DATA 0x00080804 +#define DDRSS2_PI_273_DATA 0x00000000 +#define DDRSS2_PI_274_DATA 0x00000000 +#define DDRSS2_PI_275_DATA 0x00F30084 +#define DDRSS2_PI_276_DATA 0x00160000 +#define DDRSS2_PI_277_DATA 0x35F33FF4 +#define DDRSS2_PI_278_DATA 0x00160F27 +#define DDRSS2_PI_279_DATA 0x35F33FF4 +#define DDRSS2_PI_280_DATA 0x00160F27 +#define DDRSS2_PI_281_DATA 0x00F30084 +#define DDRSS2_PI_282_DATA 0x00160000 +#define DDRSS2_PI_283_DATA 0x35F33FF4 +#define DDRSS2_PI_284_DATA 0x00160F27 +#define DDRSS2_PI_285_DATA 0x35F33FF4 +#define DDRSS2_PI_286_DATA 0x00160F27 +#define DDRSS2_PI_287_DATA 0x00F30084 +#define DDRSS2_PI_288_DATA 0x00160000 +#define DDRSS2_PI_289_DATA 0x35F33FF4 +#define DDRSS2_PI_290_DATA 0x00160F27 +#define DDRSS2_PI_291_DATA 0x35F33FF4 +#define DDRSS2_PI_292_DATA 0x00160F27 +#define DDRSS2_PI_293_DATA 0x00F30084 +#define DDRSS2_PI_294_DATA 0x00160000 +#define DDRSS2_PI_295_DATA 0x35F33FF4 +#define DDRSS2_PI_296_DATA 0x00160F27 +#define DDRSS2_PI_297_DATA 0x35F33FF4 +#define DDRSS2_PI_298_DATA 0x00160F27 +#define DDRSS2_PI_299_DATA 0x00000000 + +#define DDRSS2_PHY_00_DATA 0x000004F0 +#define DDRSS2_PHY_01_DATA 0x00000000 +#define DDRSS2_PHY_02_DATA 0x00030200 +#define DDRSS2_PHY_03_DATA 0x00000000 +#define DDRSS2_PHY_04_DATA 0x00000000 +#define DDRSS2_PHY_05_DATA 0x01030000 +#define DDRSS2_PHY_06_DATA 0x00010000 +#define DDRSS2_PHY_07_DATA 0x01030004 +#define DDRSS2_PHY_08_DATA 0x01000000 +#define DDRSS2_PHY_09_DATA 0x00000000 +#define DDRSS2_PHY_10_DATA 0x00000000 +#define DDRSS2_PHY_11_DATA 0x01000001 +#define DDRSS2_PHY_12_DATA 0x00000200 +#define DDRSS2_PHY_13_DATA 0x000800C0 +#define DDRSS2_PHY_14_DATA 0x060100CC +#define DDRSS2_PHY_15_DATA 0x00030066 +#define DDRSS2_PHY_16_DATA 0x00000000 +#define DDRSS2_PHY_17_DATA 0x00000301 +#define DDRSS2_PHY_18_DATA 0x0000AAAA +#define DDRSS2_PHY_19_DATA 0x00005555 +#define DDRSS2_PHY_20_DATA 0x0000B5B5 +#define DDRSS2_PHY_21_DATA 0x00004A4A +#define DDRSS2_PHY_22_DATA 0x00005656 +#define DDRSS2_PHY_23_DATA 0x0000A9A9 +#define DDRSS2_PHY_24_DATA 0x0000A9A9 +#define DDRSS2_PHY_25_DATA 0x0000B5B5 +#define DDRSS2_PHY_26_DATA 0x00000000 +#define DDRSS2_PHY_27_DATA 0x00000000 +#define DDRSS2_PHY_28_DATA 0x2A000000 +#define DDRSS2_PHY_29_DATA 0x00000808 +#define DDRSS2_PHY_30_DATA 0x0F000000 +#define DDRSS2_PHY_31_DATA 0x00000F08 +#define DDRSS2_PHY_32_DATA 0x10400000 +#define DDRSS2_PHY_33_DATA 0x0C002006 +#define DDRSS2_PHY_34_DATA 0x00000000 +#define DDRSS2_PHY_35_DATA 0x00000000 +#define DDRSS2_PHY_36_DATA 0x55555555 +#define DDRSS2_PHY_37_DATA 0xAAAAAAAA +#define DDRSS2_PHY_38_DATA 0x55555555 +#define DDRSS2_PHY_39_DATA 0xAAAAAAAA +#define DDRSS2_PHY_40_DATA 0x00005555 +#define DDRSS2_PHY_41_DATA 0x01000100 +#define DDRSS2_PHY_42_DATA 0x00800180 +#define DDRSS2_PHY_43_DATA 0x00000001 +#define DDRSS2_PHY_44_DATA 0x00000000 +#define DDRSS2_PHY_45_DATA 0x00000000 +#define DDRSS2_PHY_46_DATA 0x00000000 +#define DDRSS2_PHY_47_DATA 0x00000000 +#define DDRSS2_PHY_48_DATA 0x00000000 +#define DDRSS2_PHY_49_DATA 0x00000000 +#define DDRSS2_PHY_50_DATA 0x00000000 +#define DDRSS2_PHY_51_DATA 0x00000000 +#define DDRSS2_PHY_52_DATA 0x00000000 +#define DDRSS2_PHY_53_DATA 0x00000000 +#define DDRSS2_PHY_54_DATA 0x00000000 +#define DDRSS2_PHY_55_DATA 0x00000000 +#define DDRSS2_PHY_56_DATA 0x00000000 +#define DDRSS2_PHY_57_DATA 0x00000000 +#define DDRSS2_PHY_58_DATA 0x00000000 +#define DDRSS2_PHY_59_DATA 0x00000000 +#define DDRSS2_PHY_60_DATA 0x00000000 +#define DDRSS2_PHY_61_DATA 0x00000000 +#define DDRSS2_PHY_62_DATA 0x00000000 +#define DDRSS2_PHY_63_DATA 0x00000000 +#define DDRSS2_PHY_64_DATA 0x00000000 +#define DDRSS2_PHY_65_DATA 0x00000000 +#define DDRSS2_PHY_66_DATA 0x00000104 +#define DDRSS2_PHY_67_DATA 0x00000120 +#define DDRSS2_PHY_68_DATA 0x00000000 +#define DDRSS2_PHY_69_DATA 0x00000000 +#define DDRSS2_PHY_70_DATA 0x00000000 +#define DDRSS2_PHY_71_DATA 0x00000000 +#define DDRSS2_PHY_72_DATA 0x00000000 +#define DDRSS2_PHY_73_DATA 0x00000000 +#define DDRSS2_PHY_74_DATA 0x00000000 +#define DDRSS2_PHY_75_DATA 0x00000001 +#define DDRSS2_PHY_76_DATA 0x07FF0000 +#define DDRSS2_PHY_77_DATA 0x0080081F +#define DDRSS2_PHY_78_DATA 0x00081020 +#define DDRSS2_PHY_79_DATA 0x04010000 +#define DDRSS2_PHY_80_DATA 0x00000000 +#define DDRSS2_PHY_81_DATA 0x00000000 +#define DDRSS2_PHY_82_DATA 0x00000000 +#define DDRSS2_PHY_83_DATA 0x00000100 +#define DDRSS2_PHY_84_DATA 0x01CC0C01 +#define DDRSS2_PHY_85_DATA 0x1003CC0C +#define DDRSS2_PHY_86_DATA 0x20000140 +#define DDRSS2_PHY_87_DATA 0x07FF0200 +#define DDRSS2_PHY_88_DATA 0x0000DD01 +#define DDRSS2_PHY_89_DATA 0x10100303 +#define DDRSS2_PHY_90_DATA 0x10101010 +#define DDRSS2_PHY_91_DATA 0x10101010 +#define DDRSS2_PHY_92_DATA 0x00021010 +#define DDRSS2_PHY_93_DATA 0x00100010 +#define DDRSS2_PHY_94_DATA 0x00100010 +#define DDRSS2_PHY_95_DATA 0x00100010 +#define DDRSS2_PHY_96_DATA 0x00100010 +#define DDRSS2_PHY_97_DATA 0x00050010 +#define DDRSS2_PHY_98_DATA 0x51517041 +#define DDRSS2_PHY_99_DATA 0x31C06001 +#define DDRSS2_PHY_100_DATA 0x07AB01AB +#define DDRSS2_PHY_101_DATA 0x00C0C001 +#define DDRSS2_PHY_102_DATA 0x0E0D0101 +#define DDRSS2_PHY_103_DATA 0x10001000 +#define DDRSS2_PHY_104_DATA 0x0C083E42 +#define DDRSS2_PHY_105_DATA 0x0F0C3701 +#define DDRSS2_PHY_106_DATA 0x01000140 +#define DDRSS2_PHY_107_DATA 0x0C000420 +#define DDRSS2_PHY_108_DATA 0x00000198 +#define DDRSS2_PHY_109_DATA 0x0A0000D0 +#define DDRSS2_PHY_110_DATA 0x00030200 +#define DDRSS2_PHY_111_DATA 0x02800000 +#define DDRSS2_PHY_112_DATA 0x80800000 +#define DDRSS2_PHY_113_DATA 0x000E2010 +#define DDRSS2_PHY_114_DATA 0x76543210 +#define DDRSS2_PHY_115_DATA 0x00000008 +#define DDRSS2_PHY_116_DATA 0x02800280 +#define DDRSS2_PHY_117_DATA 0x02800280 +#define DDRSS2_PHY_118_DATA 0x02800280 +#define DDRSS2_PHY_119_DATA 0x02800280 +#define DDRSS2_PHY_120_DATA 0x00000280 +#define DDRSS2_PHY_121_DATA 0x0000A000 +#define DDRSS2_PHY_122_DATA 0x00A000A0 +#define DDRSS2_PHY_123_DATA 0x00A000A0 +#define DDRSS2_PHY_124_DATA 0x00A000A0 +#define DDRSS2_PHY_125_DATA 0x00A000A0 +#define DDRSS2_PHY_126_DATA 0x00A000A0 +#define DDRSS2_PHY_127_DATA 0x00A000A0 +#define DDRSS2_PHY_128_DATA 0x00A000A0 +#define DDRSS2_PHY_129_DATA 0x00A000A0 +#define DDRSS2_PHY_130_DATA 0x01C200A0 +#define DDRSS2_PHY_131_DATA 0x01A00005 +#define DDRSS2_PHY_132_DATA 0x00000000 +#define DDRSS2_PHY_133_DATA 0x00000000 +#define DDRSS2_PHY_134_DATA 0x00080200 +#define DDRSS2_PHY_135_DATA 0x00000000 +#define DDRSS2_PHY_136_DATA 0x20202000 +#define DDRSS2_PHY_137_DATA 0x20202020 +#define DDRSS2_PHY_138_DATA 0xF0F02020 +#define DDRSS2_PHY_139_DATA 0x00000000 +#define DDRSS2_PHY_140_DATA 0x00000000 +#define DDRSS2_PHY_141_DATA 0x00000000 +#define DDRSS2_PHY_142_DATA 0x00000000 +#define DDRSS2_PHY_143_DATA 0x00000000 +#define DDRSS2_PHY_144_DATA 0x00000000 +#define DDRSS2_PHY_145_DATA 0x00000000 +#define DDRSS2_PHY_146_DATA 0x00000000 +#define DDRSS2_PHY_147_DATA 0x00000000 +#define DDRSS2_PHY_148_DATA 0x00000000 +#define DDRSS2_PHY_149_DATA 0x00000000 +#define DDRSS2_PHY_150_DATA 0x00000000 +#define DDRSS2_PHY_151_DATA 0x00000000 +#define DDRSS2_PHY_152_DATA 0x00000000 +#define DDRSS2_PHY_153_DATA 0x00000000 +#define DDRSS2_PHY_154_DATA 0x00000000 +#define DDRSS2_PHY_155_DATA 0x00000000 +#define DDRSS2_PHY_156_DATA 0x00000000 +#define DDRSS2_PHY_157_DATA 0x00000000 +#define DDRSS2_PHY_158_DATA 0x00000000 +#define DDRSS2_PHY_159_DATA 0x00000000 +#define DDRSS2_PHY_160_DATA 0x00000000 +#define DDRSS2_PHY_161_DATA 0x00000000 +#define DDRSS2_PHY_162_DATA 0x00000000 +#define DDRSS2_PHY_163_DATA 0x00000000 +#define DDRSS2_PHY_164_DATA 0x00000000 +#define DDRSS2_PHY_165_DATA 0x00000000 +#define DDRSS2_PHY_166_DATA 0x00000000 +#define DDRSS2_PHY_167_DATA 0x00000000 +#define DDRSS2_PHY_168_DATA 0x00000000 +#define DDRSS2_PHY_169_DATA 0x00000000 +#define DDRSS2_PHY_170_DATA 0x00000000 +#define DDRSS2_PHY_171_DATA 0x00000000 +#define DDRSS2_PHY_172_DATA 0x00000000 +#define DDRSS2_PHY_173_DATA 0x00000000 +#define DDRSS2_PHY_174_DATA 0x00000000 +#define DDRSS2_PHY_175_DATA 0x00000000 +#define DDRSS2_PHY_176_DATA 0x00000000 +#define DDRSS2_PHY_177_DATA 0x00000000 +#define DDRSS2_PHY_178_DATA 0x00000000 +#define DDRSS2_PHY_179_DATA 0x00000000 +#define DDRSS2_PHY_180_DATA 0x00000000 +#define DDRSS2_PHY_181_DATA 0x00000000 +#define DDRSS2_PHY_182_DATA 0x00000000 +#define DDRSS2_PHY_183_DATA 0x00000000 +#define DDRSS2_PHY_184_DATA 0x00000000 +#define DDRSS2_PHY_185_DATA 0x00000000 +#define DDRSS2_PHY_186_DATA 0x00000000 +#define DDRSS2_PHY_187_DATA 0x00000000 +#define DDRSS2_PHY_188_DATA 0x00000000 +#define DDRSS2_PHY_189_DATA 0x00000000 +#define DDRSS2_PHY_190_DATA 0x00000000 +#define DDRSS2_PHY_191_DATA 0x00000000 +#define DDRSS2_PHY_192_DATA 0x00000000 +#define DDRSS2_PHY_193_DATA 0x00000000 +#define DDRSS2_PHY_194_DATA 0x00000000 +#define DDRSS2_PHY_195_DATA 0x00000000 +#define DDRSS2_PHY_196_DATA 0x00000000 +#define DDRSS2_PHY_197_DATA 0x00000000 +#define DDRSS2_PHY_198_DATA 0x00000000 +#define DDRSS2_PHY_199_DATA 0x00000000 +#define DDRSS2_PHY_200_DATA 0x00000000 +#define DDRSS2_PHY_201_DATA 0x00000000 +#define DDRSS2_PHY_202_DATA 0x00000000 +#define DDRSS2_PHY_203_DATA 0x00000000 +#define DDRSS2_PHY_204_DATA 0x00000000 +#define DDRSS2_PHY_205_DATA 0x00000000 +#define DDRSS2_PHY_206_DATA 0x00000000 +#define DDRSS2_PHY_207_DATA 0x00000000 +#define DDRSS2_PHY_208_DATA 0x00000000 +#define DDRSS2_PHY_209_DATA 0x00000000 +#define DDRSS2_PHY_210_DATA 0x00000000 +#define DDRSS2_PHY_211_DATA 0x00000000 +#define DDRSS2_PHY_212_DATA 0x00000000 +#define DDRSS2_PHY_213_DATA 0x00000000 +#define DDRSS2_PHY_214_DATA 0x00000000 +#define DDRSS2_PHY_215_DATA 0x00000000 +#define DDRSS2_PHY_216_DATA 0x00000000 +#define DDRSS2_PHY_217_DATA 0x00000000 +#define DDRSS2_PHY_218_DATA 0x00000000 +#define DDRSS2_PHY_219_DATA 0x00000000 +#define DDRSS2_PHY_220_DATA 0x00000000 +#define DDRSS2_PHY_221_DATA 0x00000000 +#define DDRSS2_PHY_222_DATA 0x00000000 +#define DDRSS2_PHY_223_DATA 0x00000000 +#define DDRSS2_PHY_224_DATA 0x00000000 +#define DDRSS2_PHY_225_DATA 0x00000000 +#define DDRSS2_PHY_226_DATA 0x00000000 +#define DDRSS2_PHY_227_DATA 0x00000000 +#define DDRSS2_PHY_228_DATA 0x00000000 +#define DDRSS2_PHY_229_DATA 0x00000000 +#define DDRSS2_PHY_230_DATA 0x00000000 +#define DDRSS2_PHY_231_DATA 0x00000000 +#define DDRSS2_PHY_232_DATA 0x00000000 +#define DDRSS2_PHY_233_DATA 0x00000000 +#define DDRSS2_PHY_234_DATA 0x00000000 +#define DDRSS2_PHY_235_DATA 0x00000000 +#define DDRSS2_PHY_236_DATA 0x00000000 +#define DDRSS2_PHY_237_DATA 0x00000000 +#define DDRSS2_PHY_238_DATA 0x00000000 +#define DDRSS2_PHY_239_DATA 0x00000000 +#define DDRSS2_PHY_240_DATA 0x00000000 +#define DDRSS2_PHY_241_DATA 0x00000000 +#define DDRSS2_PHY_242_DATA 0x00000000 +#define DDRSS2_PHY_243_DATA 0x00000000 +#define DDRSS2_PHY_244_DATA 0x00000000 +#define DDRSS2_PHY_245_DATA 0x00000000 +#define DDRSS2_PHY_246_DATA 0x00000000 +#define DDRSS2_PHY_247_DATA 0x00000000 +#define DDRSS2_PHY_248_DATA 0x00000000 +#define DDRSS2_PHY_249_DATA 0x00000000 +#define DDRSS2_PHY_250_DATA 0x00000000 +#define DDRSS2_PHY_251_DATA 0x00000000 +#define DDRSS2_PHY_252_DATA 0x00000000 +#define DDRSS2_PHY_253_DATA 0x00000000 +#define DDRSS2_PHY_254_DATA 0x00000000 +#define DDRSS2_PHY_255_DATA 0x00000000 +#define DDRSS2_PHY_256_DATA 0x000004F0 +#define DDRSS2_PHY_257_DATA 0x00000000 +#define DDRSS2_PHY_258_DATA 0x00030200 +#define DDRSS2_PHY_259_DATA 0x00000000 +#define DDRSS2_PHY_260_DATA 0x00000000 +#define DDRSS2_PHY_261_DATA 0x01030000 +#define DDRSS2_PHY_262_DATA 0x00010000 +#define DDRSS2_PHY_263_DATA 0x01030004 +#define DDRSS2_PHY_264_DATA 0x01000000 +#define DDRSS2_PHY_265_DATA 0x00000000 +#define DDRSS2_PHY_266_DATA 0x00000000 +#define DDRSS2_PHY_267_DATA 0x01000001 +#define DDRSS2_PHY_268_DATA 0x00000200 +#define DDRSS2_PHY_269_DATA 0x000800C0 +#define DDRSS2_PHY_270_DATA 0x060100CC +#define DDRSS2_PHY_271_DATA 0x00030066 +#define DDRSS2_PHY_272_DATA 0x00000000 +#define DDRSS2_PHY_273_DATA 0x00000301 +#define DDRSS2_PHY_274_DATA 0x0000AAAA +#define DDRSS2_PHY_275_DATA 0x00005555 +#define DDRSS2_PHY_276_DATA 0x0000B5B5 +#define DDRSS2_PHY_277_DATA 0x00004A4A +#define DDRSS2_PHY_278_DATA 0x00005656 +#define DDRSS2_PHY_279_DATA 0x0000A9A9 +#define DDRSS2_PHY_280_DATA 0x0000A9A9 +#define DDRSS2_PHY_281_DATA 0x0000B5B5 +#define DDRSS2_PHY_282_DATA 0x00000000 +#define DDRSS2_PHY_283_DATA 0x00000000 +#define DDRSS2_PHY_284_DATA 0x2A000000 +#define DDRSS2_PHY_285_DATA 0x00000808 +#define DDRSS2_PHY_286_DATA 0x0F000000 +#define DDRSS2_PHY_287_DATA 0x00000F08 +#define DDRSS2_PHY_288_DATA 0x10400000 +#define DDRSS2_PHY_289_DATA 0x0C002006 +#define DDRSS2_PHY_290_DATA 0x00000000 +#define DDRSS2_PHY_291_DATA 0x00000000 +#define DDRSS2_PHY_292_DATA 0x55555555 +#define DDRSS2_PHY_293_DATA 0xAAAAAAAA +#define DDRSS2_PHY_294_DATA 0x55555555 +#define DDRSS2_PHY_295_DATA 0xAAAAAAAA +#define DDRSS2_PHY_296_DATA 0x00005555 +#define DDRSS2_PHY_297_DATA 0x01000100 +#define DDRSS2_PHY_298_DATA 0x00800180 +#define DDRSS2_PHY_299_DATA 0x00000000 +#define DDRSS2_PHY_300_DATA 0x00000000 +#define DDRSS2_PHY_301_DATA 0x00000000 +#define DDRSS2_PHY_302_DATA 0x00000000 +#define DDRSS2_PHY_303_DATA 0x00000000 +#define DDRSS2_PHY_304_DATA 0x00000000 +#define DDRSS2_PHY_305_DATA 0x00000000 +#define DDRSS2_PHY_306_DATA 0x00000000 +#define DDRSS2_PHY_307_DATA 0x00000000 +#define DDRSS2_PHY_308_DATA 0x00000000 +#define DDRSS2_PHY_309_DATA 0x00000000 +#define DDRSS2_PHY_310_DATA 0x00000000 +#define DDRSS2_PHY_311_DATA 0x00000000 +#define DDRSS2_PHY_312_DATA 0x00000000 +#define DDRSS2_PHY_313_DATA 0x00000000 +#define DDRSS2_PHY_314_DATA 0x00000000 +#define DDRSS2_PHY_315_DATA 0x00000000 +#define DDRSS2_PHY_316_DATA 0x00000000 +#define DDRSS2_PHY_317_DATA 0x00000000 +#define DDRSS2_PHY_318_DATA 0x00000000 +#define DDRSS2_PHY_319_DATA 0x00000000 +#define DDRSS2_PHY_320_DATA 0x00000000 +#define DDRSS2_PHY_321_DATA 0x00000000 +#define DDRSS2_PHY_322_DATA 0x00000104 +#define DDRSS2_PHY_323_DATA 0x00000120 +#define DDRSS2_PHY_324_DATA 0x00000000 +#define DDRSS2_PHY_325_DATA 0x00000000 +#define DDRSS2_PHY_326_DATA 0x00000000 +#define DDRSS2_PHY_327_DATA 0x00000000 +#define DDRSS2_PHY_328_DATA 0x00000000 +#define DDRSS2_PHY_329_DATA 0x00000000 +#define DDRSS2_PHY_330_DATA 0x00000000 +#define DDRSS2_PHY_331_DATA 0x00000001 +#define DDRSS2_PHY_332_DATA 0x07FF0000 +#define DDRSS2_PHY_333_DATA 0x0080081F +#define DDRSS2_PHY_334_DATA 0x00081020 +#define DDRSS2_PHY_335_DATA 0x04010000 +#define DDRSS2_PHY_336_DATA 0x00000000 +#define DDRSS2_PHY_337_DATA 0x00000000 +#define DDRSS2_PHY_338_DATA 0x00000000 +#define DDRSS2_PHY_339_DATA 0x00000100 +#define DDRSS2_PHY_340_DATA 0x01CC0C01 +#define DDRSS2_PHY_341_DATA 0x1003CC0C +#define DDRSS2_PHY_342_DATA 0x20000140 +#define DDRSS2_PHY_343_DATA 0x07FF0200 +#define DDRSS2_PHY_344_DATA 0x0000DD01 +#define DDRSS2_PHY_345_DATA 0x10100303 +#define DDRSS2_PHY_346_DATA 0x10101010 +#define DDRSS2_PHY_347_DATA 0x10101010 +#define DDRSS2_PHY_348_DATA 0x00021010 +#define DDRSS2_PHY_349_DATA 0x00100010 +#define DDRSS2_PHY_350_DATA 0x00100010 +#define DDRSS2_PHY_351_DATA 0x00100010 +#define DDRSS2_PHY_352_DATA 0x00100010 +#define DDRSS2_PHY_353_DATA 0x00050010 +#define DDRSS2_PHY_354_DATA 0x51517041 +#define DDRSS2_PHY_355_DATA 0x31C06001 +#define DDRSS2_PHY_356_DATA 0x07AB01AB +#define DDRSS2_PHY_357_DATA 0x00C0C001 +#define DDRSS2_PHY_358_DATA 0x0E0D0101 +#define DDRSS2_PHY_359_DATA 0x10001000 +#define DDRSS2_PHY_360_DATA 0x0C083E42 +#define DDRSS2_PHY_361_DATA 0x0F0C3701 +#define DDRSS2_PHY_362_DATA 0x01000140 +#define DDRSS2_PHY_363_DATA 0x0C000420 +#define DDRSS2_PHY_364_DATA 0x00000198 +#define DDRSS2_PHY_365_DATA 0x0A0000D0 +#define DDRSS2_PHY_366_DATA 0x00030200 +#define DDRSS2_PHY_367_DATA 0x02800000 +#define DDRSS2_PHY_368_DATA 0x80800000 +#define DDRSS2_PHY_369_DATA 0x000E2010 +#define DDRSS2_PHY_370_DATA 0x76543210 +#define DDRSS2_PHY_371_DATA 0x00000008 +#define DDRSS2_PHY_372_DATA 0x02800280 +#define DDRSS2_PHY_373_DATA 0x02800280 +#define DDRSS2_PHY_374_DATA 0x02800280 +#define DDRSS2_PHY_375_DATA 0x02800280 +#define DDRSS2_PHY_376_DATA 0x00000280 +#define DDRSS2_PHY_377_DATA 0x0000A000 +#define DDRSS2_PHY_378_DATA 0x00A000A0 +#define DDRSS2_PHY_379_DATA 0x00A000A0 +#define DDRSS2_PHY_380_DATA 0x00A000A0 +#define DDRSS2_PHY_381_DATA 0x00A000A0 +#define DDRSS2_PHY_382_DATA 0x00A000A0 +#define DDRSS2_PHY_383_DATA 0x00A000A0 +#define DDRSS2_PHY_384_DATA 0x00A000A0 +#define DDRSS2_PHY_385_DATA 0x00A000A0 +#define DDRSS2_PHY_386_DATA 0x01C200A0 +#define DDRSS2_PHY_387_DATA 0x01A00005 +#define DDRSS2_PHY_388_DATA 0x00000000 +#define DDRSS2_PHY_389_DATA 0x00000000 +#define DDRSS2_PHY_390_DATA 0x00080200 +#define DDRSS2_PHY_391_DATA 0x00000000 +#define DDRSS2_PHY_392_DATA 0x20202000 +#define DDRSS2_PHY_393_DATA 0x20202020 +#define DDRSS2_PHY_394_DATA 0xF0F02020 +#define DDRSS2_PHY_395_DATA 0x00000000 +#define DDRSS2_PHY_396_DATA 0x00000000 +#define DDRSS2_PHY_397_DATA 0x00000000 +#define DDRSS2_PHY_398_DATA 0x00000000 +#define DDRSS2_PHY_399_DATA 0x00000000 +#define DDRSS2_PHY_400_DATA 0x00000000 +#define DDRSS2_PHY_401_DATA 0x00000000 +#define DDRSS2_PHY_402_DATA 0x00000000 +#define DDRSS2_PHY_403_DATA 0x00000000 +#define DDRSS2_PHY_404_DATA 0x00000000 +#define DDRSS2_PHY_405_DATA 0x00000000 +#define DDRSS2_PHY_406_DATA 0x00000000 +#define DDRSS2_PHY_407_DATA 0x00000000 +#define DDRSS2_PHY_408_DATA 0x00000000 +#define DDRSS2_PHY_409_DATA 0x00000000 +#define DDRSS2_PHY_410_DATA 0x00000000 +#define DDRSS2_PHY_411_DATA 0x00000000 +#define DDRSS2_PHY_412_DATA 0x00000000 +#define DDRSS2_PHY_413_DATA 0x00000000 +#define DDRSS2_PHY_414_DATA 0x00000000 +#define DDRSS2_PHY_415_DATA 0x00000000 +#define DDRSS2_PHY_416_DATA 0x00000000 +#define DDRSS2_PHY_417_DATA 0x00000000 +#define DDRSS2_PHY_418_DATA 0x00000000 +#define DDRSS2_PHY_419_DATA 0x00000000 +#define DDRSS2_PHY_420_DATA 0x00000000 +#define DDRSS2_PHY_421_DATA 0x00000000 +#define DDRSS2_PHY_422_DATA 0x00000000 +#define DDRSS2_PHY_423_DATA 0x00000000 +#define DDRSS2_PHY_424_DATA 0x00000000 +#define DDRSS2_PHY_425_DATA 0x00000000 +#define DDRSS2_PHY_426_DATA 0x00000000 +#define DDRSS2_PHY_427_DATA 0x00000000 +#define DDRSS2_PHY_428_DATA 0x00000000 +#define DDRSS2_PHY_429_DATA 0x00000000 +#define DDRSS2_PHY_430_DATA 0x00000000 +#define DDRSS2_PHY_431_DATA 0x00000000 +#define DDRSS2_PHY_432_DATA 0x00000000 +#define DDRSS2_PHY_433_DATA 0x00000000 +#define DDRSS2_PHY_434_DATA 0x00000000 +#define DDRSS2_PHY_435_DATA 0x00000000 +#define DDRSS2_PHY_436_DATA 0x00000000 +#define DDRSS2_PHY_437_DATA 0x00000000 +#define DDRSS2_PHY_438_DATA 0x00000000 +#define DDRSS2_PHY_439_DATA 0x00000000 +#define DDRSS2_PHY_440_DATA 0x00000000 +#define DDRSS2_PHY_441_DATA 0x00000000 +#define DDRSS2_PHY_442_DATA 0x00000000 +#define DDRSS2_PHY_443_DATA 0x00000000 +#define DDRSS2_PHY_444_DATA 0x00000000 +#define DDRSS2_PHY_445_DATA 0x00000000 +#define DDRSS2_PHY_446_DATA 0x00000000 +#define DDRSS2_PHY_447_DATA 0x00000000 +#define DDRSS2_PHY_448_DATA 0x00000000 +#define DDRSS2_PHY_449_DATA 0x00000000 +#define DDRSS2_PHY_450_DATA 0x00000000 +#define DDRSS2_PHY_451_DATA 0x00000000 +#define DDRSS2_PHY_452_DATA 0x00000000 +#define DDRSS2_PHY_453_DATA 0x00000000 +#define DDRSS2_PHY_454_DATA 0x00000000 +#define DDRSS2_PHY_455_DATA 0x00000000 +#define DDRSS2_PHY_456_DATA 0x00000000 +#define DDRSS2_PHY_457_DATA 0x00000000 +#define DDRSS2_PHY_458_DATA 0x00000000 +#define DDRSS2_PHY_459_DATA 0x00000000 +#define DDRSS2_PHY_460_DATA 0x00000000 +#define DDRSS2_PHY_461_DATA 0x00000000 +#define DDRSS2_PHY_462_DATA 0x00000000 +#define DDRSS2_PHY_463_DATA 0x00000000 +#define DDRSS2_PHY_464_DATA 0x00000000 +#define DDRSS2_PHY_465_DATA 0x00000000 +#define DDRSS2_PHY_466_DATA 0x00000000 +#define DDRSS2_PHY_467_DATA 0x00000000 +#define DDRSS2_PHY_468_DATA 0x00000000 +#define DDRSS2_PHY_469_DATA 0x00000000 +#define DDRSS2_PHY_470_DATA 0x00000000 +#define DDRSS2_PHY_471_DATA 0x00000000 +#define DDRSS2_PHY_472_DATA 0x00000000 +#define DDRSS2_PHY_473_DATA 0x00000000 +#define DDRSS2_PHY_474_DATA 0x00000000 +#define DDRSS2_PHY_475_DATA 0x00000000 +#define DDRSS2_PHY_476_DATA 0x00000000 +#define DDRSS2_PHY_477_DATA 0x00000000 +#define DDRSS2_PHY_478_DATA 0x00000000 +#define DDRSS2_PHY_479_DATA 0x00000000 +#define DDRSS2_PHY_480_DATA 0x00000000 +#define DDRSS2_PHY_481_DATA 0x00000000 +#define DDRSS2_PHY_482_DATA 0x00000000 +#define DDRSS2_PHY_483_DATA 0x00000000 +#define DDRSS2_PHY_484_DATA 0x00000000 +#define DDRSS2_PHY_485_DATA 0x00000000 +#define DDRSS2_PHY_486_DATA 0x00000000 +#define DDRSS2_PHY_487_DATA 0x00000000 +#define DDRSS2_PHY_488_DATA 0x00000000 +#define DDRSS2_PHY_489_DATA 0x00000000 +#define DDRSS2_PHY_490_DATA 0x00000000 +#define DDRSS2_PHY_491_DATA 0x00000000 +#define DDRSS2_PHY_492_DATA 0x00000000 +#define DDRSS2_PHY_493_DATA 0x00000000 +#define DDRSS2_PHY_494_DATA 0x00000000 +#define DDRSS2_PHY_495_DATA 0x00000000 +#define DDRSS2_PHY_496_DATA 0x00000000 +#define DDRSS2_PHY_497_DATA 0x00000000 +#define DDRSS2_PHY_498_DATA 0x00000000 +#define DDRSS2_PHY_499_DATA 0x00000000 +#define DDRSS2_PHY_500_DATA 0x00000000 +#define DDRSS2_PHY_501_DATA 0x00000000 +#define DDRSS2_PHY_502_DATA 0x00000000 +#define DDRSS2_PHY_503_DATA 0x00000000 +#define DDRSS2_PHY_504_DATA 0x00000000 +#define DDRSS2_PHY_505_DATA 0x00000000 +#define DDRSS2_PHY_506_DATA 0x00000000 +#define DDRSS2_PHY_507_DATA 0x00000000 +#define DDRSS2_PHY_508_DATA 0x00000000 +#define DDRSS2_PHY_509_DATA 0x00000000 +#define DDRSS2_PHY_510_DATA 0x00000000 +#define DDRSS2_PHY_511_DATA 0x00000000 +#define DDRSS2_PHY_512_DATA 0x000004F0 +#define DDRSS2_PHY_513_DATA 0x00000000 +#define DDRSS2_PHY_514_DATA 0x00030200 +#define DDRSS2_PHY_515_DATA 0x00000000 +#define DDRSS2_PHY_516_DATA 0x00000000 +#define DDRSS2_PHY_517_DATA 0x01030000 +#define DDRSS2_PHY_518_DATA 0x00010000 +#define DDRSS2_PHY_519_DATA 0x01030004 +#define DDRSS2_PHY_520_DATA 0x01000000 +#define DDRSS2_PHY_521_DATA 0x00000000 +#define DDRSS2_PHY_522_DATA 0x00000000 +#define DDRSS2_PHY_523_DATA 0x01000001 +#define DDRSS2_PHY_524_DATA 0x00000200 +#define DDRSS2_PHY_525_DATA 0x000800C0 +#define DDRSS2_PHY_526_DATA 0x060100CC +#define DDRSS2_PHY_527_DATA 0x00030066 +#define DDRSS2_PHY_528_DATA 0x00000000 +#define DDRSS2_PHY_529_DATA 0x00000301 +#define DDRSS2_PHY_530_DATA 0x0000AAAA +#define DDRSS2_PHY_531_DATA 0x00005555 +#define DDRSS2_PHY_532_DATA 0x0000B5B5 +#define DDRSS2_PHY_533_DATA 0x00004A4A +#define DDRSS2_PHY_534_DATA 0x00005656 +#define DDRSS2_PHY_535_DATA 0x0000A9A9 +#define DDRSS2_PHY_536_DATA 0x0000A9A9 +#define DDRSS2_PHY_537_DATA 0x0000B5B5 +#define DDRSS2_PHY_538_DATA 0x00000000 +#define DDRSS2_PHY_539_DATA 0x00000000 +#define DDRSS2_PHY_540_DATA 0x2A000000 +#define DDRSS2_PHY_541_DATA 0x00000808 +#define DDRSS2_PHY_542_DATA 0x0F000000 +#define DDRSS2_PHY_543_DATA 0x00000F08 +#define DDRSS2_PHY_544_DATA 0x10400000 +#define DDRSS2_PHY_545_DATA 0x0C002006 +#define DDRSS2_PHY_546_DATA 0x00000000 +#define DDRSS2_PHY_547_DATA 0x00000000 +#define DDRSS2_PHY_548_DATA 0x55555555 +#define DDRSS2_PHY_549_DATA 0xAAAAAAAA +#define DDRSS2_PHY_550_DATA 0x55555555 +#define DDRSS2_PHY_551_DATA 0xAAAAAAAA +#define DDRSS2_PHY_552_DATA 0x00005555 +#define DDRSS2_PHY_553_DATA 0x01000100 +#define DDRSS2_PHY_554_DATA 0x00800180 +#define DDRSS2_PHY_555_DATA 0x00000001 +#define DDRSS2_PHY_556_DATA 0x00000000 +#define DDRSS2_PHY_557_DATA 0x00000000 +#define DDRSS2_PHY_558_DATA 0x00000000 +#define DDRSS2_PHY_559_DATA 0x00000000 +#define DDRSS2_PHY_560_DATA 0x00000000 +#define DDRSS2_PHY_561_DATA 0x00000000 +#define DDRSS2_PHY_562_DATA 0x00000000 +#define DDRSS2_PHY_563_DATA 0x00000000 +#define DDRSS2_PHY_564_DATA 0x00000000 +#define DDRSS2_PHY_565_DATA 0x00000000 +#define DDRSS2_PHY_566_DATA 0x00000000 +#define DDRSS2_PHY_567_DATA 0x00000000 +#define DDRSS2_PHY_568_DATA 0x00000000 +#define DDRSS2_PHY_569_DATA 0x00000000 +#define DDRSS2_PHY_570_DATA 0x00000000 +#define DDRSS2_PHY_571_DATA 0x00000000 +#define DDRSS2_PHY_572_DATA 0x00000000 +#define DDRSS2_PHY_573_DATA 0x00000000 +#define DDRSS2_PHY_574_DATA 0x00000000 +#define DDRSS2_PHY_575_DATA 0x00000000 +#define DDRSS2_PHY_576_DATA 0x00000000 +#define DDRSS2_PHY_577_DATA 0x00000000 +#define DDRSS2_PHY_578_DATA 0x00000104 +#define DDRSS2_PHY_579_DATA 0x00000120 +#define DDRSS2_PHY_580_DATA 0x00000000 +#define DDRSS2_PHY_581_DATA 0x00000000 +#define DDRSS2_PHY_582_DATA 0x00000000 +#define DDRSS2_PHY_583_DATA 0x00000000 +#define DDRSS2_PHY_584_DATA 0x00000000 +#define DDRSS2_PHY_585_DATA 0x00000000 +#define DDRSS2_PHY_586_DATA 0x00000000 +#define DDRSS2_PHY_587_DATA 0x00000001 +#define DDRSS2_PHY_588_DATA 0x07FF0000 +#define DDRSS2_PHY_589_DATA 0x0080081F +#define DDRSS2_PHY_590_DATA 0x00081020 +#define DDRSS2_PHY_591_DATA 0x04010000 +#define DDRSS2_PHY_592_DATA 0x00000000 +#define DDRSS2_PHY_593_DATA 0x00000000 +#define DDRSS2_PHY_594_DATA 0x00000000 +#define DDRSS2_PHY_595_DATA 0x00000100 +#define DDRSS2_PHY_596_DATA 0x01CC0C01 +#define DDRSS2_PHY_597_DATA 0x1003CC0C +#define DDRSS2_PHY_598_DATA 0x20000140 +#define DDRSS2_PHY_599_DATA 0x07FF0200 +#define DDRSS2_PHY_600_DATA 0x0000DD01 +#define DDRSS2_PHY_601_DATA 0x10100303 +#define DDRSS2_PHY_602_DATA 0x10101010 +#define DDRSS2_PHY_603_DATA 0x10101010 +#define DDRSS2_PHY_604_DATA 0x00021010 +#define DDRSS2_PHY_605_DATA 0x00100010 +#define DDRSS2_PHY_606_DATA 0x00100010 +#define DDRSS2_PHY_607_DATA 0x00100010 +#define DDRSS2_PHY_608_DATA 0x00100010 +#define DDRSS2_PHY_609_DATA 0x00050010 +#define DDRSS2_PHY_610_DATA 0x51517041 +#define DDRSS2_PHY_611_DATA 0x31C06001 +#define DDRSS2_PHY_612_DATA 0x07AB01AB +#define DDRSS2_PHY_613_DATA 0x00C0C001 +#define DDRSS2_PHY_614_DATA 0x0E0D0101 +#define DDRSS2_PHY_615_DATA 0x10001000 +#define DDRSS2_PHY_616_DATA 0x0C083E42 +#define DDRSS2_PHY_617_DATA 0x0F0C3701 +#define DDRSS2_PHY_618_DATA 0x01000140 +#define DDRSS2_PHY_619_DATA 0x0C000420 +#define DDRSS2_PHY_620_DATA 0x00000198 +#define DDRSS2_PHY_621_DATA 0x0A0000D0 +#define DDRSS2_PHY_622_DATA 0x00030200 +#define DDRSS2_PHY_623_DATA 0x02800000 +#define DDRSS2_PHY_624_DATA 0x80800000 +#define DDRSS2_PHY_625_DATA 0x000E2010 +#define DDRSS2_PHY_626_DATA 0x76543210 +#define DDRSS2_PHY_627_DATA 0x00000008 +#define DDRSS2_PHY_628_DATA 0x02800280 +#define DDRSS2_PHY_629_DATA 0x02800280 +#define DDRSS2_PHY_630_DATA 0x02800280 +#define DDRSS2_PHY_631_DATA 0x02800280 +#define DDRSS2_PHY_632_DATA 0x00000280 +#define DDRSS2_PHY_633_DATA 0x0000A000 +#define DDRSS2_PHY_634_DATA 0x00A000A0 +#define DDRSS2_PHY_635_DATA 0x00A000A0 +#define DDRSS2_PHY_636_DATA 0x00A000A0 +#define DDRSS2_PHY_637_DATA 0x00A000A0 +#define DDRSS2_PHY_638_DATA 0x00A000A0 +#define DDRSS2_PHY_639_DATA 0x00A000A0 +#define DDRSS2_PHY_640_DATA 0x00A000A0 +#define DDRSS2_PHY_641_DATA 0x00A000A0 +#define DDRSS2_PHY_642_DATA 0x01C200A0 +#define DDRSS2_PHY_643_DATA 0x01A00005 +#define DDRSS2_PHY_644_DATA 0x00000000 +#define DDRSS2_PHY_645_DATA 0x00000000 +#define DDRSS2_PHY_646_DATA 0x00080200 +#define DDRSS2_PHY_647_DATA 0x00000000 +#define DDRSS2_PHY_648_DATA 0x20202000 +#define DDRSS2_PHY_649_DATA 0x20202020 +#define DDRSS2_PHY_650_DATA 0xF0F02020 +#define DDRSS2_PHY_651_DATA 0x00000000 +#define DDRSS2_PHY_652_DATA 0x00000000 +#define DDRSS2_PHY_653_DATA 0x00000000 +#define DDRSS2_PHY_654_DATA 0x00000000 +#define DDRSS2_PHY_655_DATA 0x00000000 +#define DDRSS2_PHY_656_DATA 0x00000000 +#define DDRSS2_PHY_657_DATA 0x00000000 +#define DDRSS2_PHY_658_DATA 0x00000000 +#define DDRSS2_PHY_659_DATA 0x00000000 +#define DDRSS2_PHY_660_DATA 0x00000000 +#define DDRSS2_PHY_661_DATA 0x00000000 +#define DDRSS2_PHY_662_DATA 0x00000000 +#define DDRSS2_PHY_663_DATA 0x00000000 +#define DDRSS2_PHY_664_DATA 0x00000000 +#define DDRSS2_PHY_665_DATA 0x00000000 +#define DDRSS2_PHY_666_DATA 0x00000000 +#define DDRSS2_PHY_667_DATA 0x00000000 +#define DDRSS2_PHY_668_DATA 0x00000000 +#define DDRSS2_PHY_669_DATA 0x00000000 +#define DDRSS2_PHY_670_DATA 0x00000000 +#define DDRSS2_PHY_671_DATA 0x00000000 +#define DDRSS2_PHY_672_DATA 0x00000000 +#define DDRSS2_PHY_673_DATA 0x00000000 +#define DDRSS2_PHY_674_DATA 0x00000000 +#define DDRSS2_PHY_675_DATA 0x00000000 +#define DDRSS2_PHY_676_DATA 0x00000000 +#define DDRSS2_PHY_677_DATA 0x00000000 +#define DDRSS2_PHY_678_DATA 0x00000000 +#define DDRSS2_PHY_679_DATA 0x00000000 +#define DDRSS2_PHY_680_DATA 0x00000000 +#define DDRSS2_PHY_681_DATA 0x00000000 +#define DDRSS2_PHY_682_DATA 0x00000000 +#define DDRSS2_PHY_683_DATA 0x00000000 +#define DDRSS2_PHY_684_DATA 0x00000000 +#define DDRSS2_PHY_685_DATA 0x00000000 +#define DDRSS2_PHY_686_DATA 0x00000000 +#define DDRSS2_PHY_687_DATA 0x00000000 +#define DDRSS2_PHY_688_DATA 0x00000000 +#define DDRSS2_PHY_689_DATA 0x00000000 +#define DDRSS2_PHY_690_DATA 0x00000000 +#define DDRSS2_PHY_691_DATA 0x00000000 +#define DDRSS2_PHY_692_DATA 0x00000000 +#define DDRSS2_PHY_693_DATA 0x00000000 +#define DDRSS2_PHY_694_DATA 0x00000000 +#define DDRSS2_PHY_695_DATA 0x00000000 +#define DDRSS2_PHY_696_DATA 0x00000000 +#define DDRSS2_PHY_697_DATA 0x00000000 +#define DDRSS2_PHY_698_DATA 0x00000000 +#define DDRSS2_PHY_699_DATA 0x00000000 +#define DDRSS2_PHY_700_DATA 0x00000000 +#define DDRSS2_PHY_701_DATA 0x00000000 +#define DDRSS2_PHY_702_DATA 0x00000000 +#define DDRSS2_PHY_703_DATA 0x00000000 +#define DDRSS2_PHY_704_DATA 0x00000000 +#define DDRSS2_PHY_705_DATA 0x00000000 +#define DDRSS2_PHY_706_DATA 0x00000000 +#define DDRSS2_PHY_707_DATA 0x00000000 +#define DDRSS2_PHY_708_DATA 0x00000000 +#define DDRSS2_PHY_709_DATA 0x00000000 +#define DDRSS2_PHY_710_DATA 0x00000000 +#define DDRSS2_PHY_711_DATA 0x00000000 +#define DDRSS2_PHY_712_DATA 0x00000000 +#define DDRSS2_PHY_713_DATA 0x00000000 +#define DDRSS2_PHY_714_DATA 0x00000000 +#define DDRSS2_PHY_715_DATA 0x00000000 +#define DDRSS2_PHY_716_DATA 0x00000000 +#define DDRSS2_PHY_717_DATA 0x00000000 +#define DDRSS2_PHY_718_DATA 0x00000000 +#define DDRSS2_PHY_719_DATA 0x00000000 +#define DDRSS2_PHY_720_DATA 0x00000000 +#define DDRSS2_PHY_721_DATA 0x00000000 +#define DDRSS2_PHY_722_DATA 0x00000000 +#define DDRSS2_PHY_723_DATA 0x00000000 +#define DDRSS2_PHY_724_DATA 0x00000000 +#define DDRSS2_PHY_725_DATA 0x00000000 +#define DDRSS2_PHY_726_DATA 0x00000000 +#define DDRSS2_PHY_727_DATA 0x00000000 +#define DDRSS2_PHY_728_DATA 0x00000000 +#define DDRSS2_PHY_729_DATA 0x00000000 +#define DDRSS2_PHY_730_DATA 0x00000000 +#define DDRSS2_PHY_731_DATA 0x00000000 +#define DDRSS2_PHY_732_DATA 0x00000000 +#define DDRSS2_PHY_733_DATA 0x00000000 +#define DDRSS2_PHY_734_DATA 0x00000000 +#define DDRSS2_PHY_735_DATA 0x00000000 +#define DDRSS2_PHY_736_DATA 0x00000000 +#define DDRSS2_PHY_737_DATA 0x00000000 +#define DDRSS2_PHY_738_DATA 0x00000000 +#define DDRSS2_PHY_739_DATA 0x00000000 +#define DDRSS2_PHY_740_DATA 0x00000000 +#define DDRSS2_PHY_741_DATA 0x00000000 +#define DDRSS2_PHY_742_DATA 0x00000000 +#define DDRSS2_PHY_743_DATA 0x00000000 +#define DDRSS2_PHY_744_DATA 0x00000000 +#define DDRSS2_PHY_745_DATA 0x00000000 +#define DDRSS2_PHY_746_DATA 0x00000000 +#define DDRSS2_PHY_747_DATA 0x00000000 +#define DDRSS2_PHY_748_DATA 0x00000000 +#define DDRSS2_PHY_749_DATA 0x00000000 +#define DDRSS2_PHY_750_DATA 0x00000000 +#define DDRSS2_PHY_751_DATA 0x00000000 +#define DDRSS2_PHY_752_DATA 0x00000000 +#define DDRSS2_PHY_753_DATA 0x00000000 +#define DDRSS2_PHY_754_DATA 0x00000000 +#define DDRSS2_PHY_755_DATA 0x00000000 +#define DDRSS2_PHY_756_DATA 0x00000000 +#define DDRSS2_PHY_757_DATA 0x00000000 +#define DDRSS2_PHY_758_DATA 0x00000000 +#define DDRSS2_PHY_759_DATA 0x00000000 +#define DDRSS2_PHY_760_DATA 0x00000000 +#define DDRSS2_PHY_761_DATA 0x00000000 +#define DDRSS2_PHY_762_DATA 0x00000000 +#define DDRSS2_PHY_763_DATA 0x00000000 +#define DDRSS2_PHY_764_DATA 0x00000000 +#define DDRSS2_PHY_765_DATA 0x00000000 +#define DDRSS2_PHY_766_DATA 0x00000000 +#define DDRSS2_PHY_767_DATA 0x00000000 +#define DDRSS2_PHY_768_DATA 0x000004F0 +#define DDRSS2_PHY_769_DATA 0x00000000 +#define DDRSS2_PHY_770_DATA 0x00030200 +#define DDRSS2_PHY_771_DATA 0x00000000 +#define DDRSS2_PHY_772_DATA 0x00000000 +#define DDRSS2_PHY_773_DATA 0x01030000 +#define DDRSS2_PHY_774_DATA 0x00010000 +#define DDRSS2_PHY_775_DATA 0x01030004 +#define DDRSS2_PHY_776_DATA 0x01000000 +#define DDRSS2_PHY_777_DATA 0x00000000 +#define DDRSS2_PHY_778_DATA 0x00000000 +#define DDRSS2_PHY_779_DATA 0x01000001 +#define DDRSS2_PHY_780_DATA 0x00000200 +#define DDRSS2_PHY_781_DATA 0x000800C0 +#define DDRSS2_PHY_782_DATA 0x060100CC +#define DDRSS2_PHY_783_DATA 0x00030066 +#define DDRSS2_PHY_784_DATA 0x00000000 +#define DDRSS2_PHY_785_DATA 0x00000301 +#define DDRSS2_PHY_786_DATA 0x0000AAAA +#define DDRSS2_PHY_787_DATA 0x00005555 +#define DDRSS2_PHY_788_DATA 0x0000B5B5 +#define DDRSS2_PHY_789_DATA 0x00004A4A +#define DDRSS2_PHY_790_DATA 0x00005656 +#define DDRSS2_PHY_791_DATA 0x0000A9A9 +#define DDRSS2_PHY_792_DATA 0x0000A9A9 +#define DDRSS2_PHY_793_DATA 0x0000B5B5 +#define DDRSS2_PHY_794_DATA 0x00000000 +#define DDRSS2_PHY_795_DATA 0x00000000 +#define DDRSS2_PHY_796_DATA 0x2A000000 +#define DDRSS2_PHY_797_DATA 0x00000808 +#define DDRSS2_PHY_798_DATA 0x0F000000 +#define DDRSS2_PHY_799_DATA 0x00000F08 +#define DDRSS2_PHY_800_DATA 0x10400000 +#define DDRSS2_PHY_801_DATA 0x0C002006 +#define DDRSS2_PHY_802_DATA 0x00000000 +#define DDRSS2_PHY_803_DATA 0x00000000 +#define DDRSS2_PHY_804_DATA 0x55555555 +#define DDRSS2_PHY_805_DATA 0xAAAAAAAA +#define DDRSS2_PHY_806_DATA 0x55555555 +#define DDRSS2_PHY_807_DATA 0xAAAAAAAA +#define DDRSS2_PHY_808_DATA 0x00005555 +#define DDRSS2_PHY_809_DATA 0x01000100 +#define DDRSS2_PHY_810_DATA 0x00800180 +#define DDRSS2_PHY_811_DATA 0x00000000 +#define DDRSS2_PHY_812_DATA 0x00000000 +#define DDRSS2_PHY_813_DATA 0x00000000 +#define DDRSS2_PHY_814_DATA 0x00000000 +#define DDRSS2_PHY_815_DATA 0x00000000 +#define DDRSS2_PHY_816_DATA 0x00000000 +#define DDRSS2_PHY_817_DATA 0x00000000 +#define DDRSS2_PHY_818_DATA 0x00000000 +#define DDRSS2_PHY_819_DATA 0x00000000 +#define DDRSS2_PHY_820_DATA 0x00000000 +#define DDRSS2_PHY_821_DATA 0x00000000 +#define DDRSS2_PHY_822_DATA 0x00000000 +#define DDRSS2_PHY_823_DATA 0x00000000 +#define DDRSS2_PHY_824_DATA 0x00000000 +#define DDRSS2_PHY_825_DATA 0x00000000 +#define DDRSS2_PHY_826_DATA 0x00000000 +#define DDRSS2_PHY_827_DATA 0x00000000 +#define DDRSS2_PHY_828_DATA 0x00000000 +#define DDRSS2_PHY_829_DATA 0x00000000 +#define DDRSS2_PHY_830_DATA 0x00000000 +#define DDRSS2_PHY_831_DATA 0x00000000 +#define DDRSS2_PHY_832_DATA 0x00000000 +#define DDRSS2_PHY_833_DATA 0x00000000 +#define DDRSS2_PHY_834_DATA 0x00000104 +#define DDRSS2_PHY_835_DATA 0x00000120 +#define DDRSS2_PHY_836_DATA 0x00000000 +#define DDRSS2_PHY_837_DATA 0x00000000 +#define DDRSS2_PHY_838_DATA 0x00000000 +#define DDRSS2_PHY_839_DATA 0x00000000 +#define DDRSS2_PHY_840_DATA 0x00000000 +#define DDRSS2_PHY_841_DATA 0x00000000 +#define DDRSS2_PHY_842_DATA 0x00000000 +#define DDRSS2_PHY_843_DATA 0x00000001 +#define DDRSS2_PHY_844_DATA 0x07FF0000 +#define DDRSS2_PHY_845_DATA 0x0080081F +#define DDRSS2_PHY_846_DATA 0x00081020 +#define DDRSS2_PHY_847_DATA 0x04010000 +#define DDRSS2_PHY_848_DATA 0x00000000 +#define DDRSS2_PHY_849_DATA 0x00000000 +#define DDRSS2_PHY_850_DATA 0x00000000 +#define DDRSS2_PHY_851_DATA 0x00000100 +#define DDRSS2_PHY_852_DATA 0x01CC0C01 +#define DDRSS2_PHY_853_DATA 0x1003CC0C +#define DDRSS2_PHY_854_DATA 0x20000140 +#define DDRSS2_PHY_855_DATA 0x07FF0200 +#define DDRSS2_PHY_856_DATA 0x0000DD01 +#define DDRSS2_PHY_857_DATA 0x10100303 +#define DDRSS2_PHY_858_DATA 0x10101010 +#define DDRSS2_PHY_859_DATA 0x10101010 +#define DDRSS2_PHY_860_DATA 0x00021010 +#define DDRSS2_PHY_861_DATA 0x00100010 +#define DDRSS2_PHY_862_DATA 0x00100010 +#define DDRSS2_PHY_863_DATA 0x00100010 +#define DDRSS2_PHY_864_DATA 0x00100010 +#define DDRSS2_PHY_865_DATA 0x00050010 +#define DDRSS2_PHY_866_DATA 0x51517041 +#define DDRSS2_PHY_867_DATA 0x31C06001 +#define DDRSS2_PHY_868_DATA 0x07AB01AB +#define DDRSS2_PHY_869_DATA 0x00C0C001 +#define DDRSS2_PHY_870_DATA 0x0E0D0101 +#define DDRSS2_PHY_871_DATA 0x10001000 +#define DDRSS2_PHY_872_DATA 0x0C083E42 +#define DDRSS2_PHY_873_DATA 0x0F0C3701 +#define DDRSS2_PHY_874_DATA 0x01000140 +#define DDRSS2_PHY_875_DATA 0x0C000420 +#define DDRSS2_PHY_876_DATA 0x00000198 +#define DDRSS2_PHY_877_DATA 0x0A0000D0 +#define DDRSS2_PHY_878_DATA 0x00030200 +#define DDRSS2_PHY_879_DATA 0x02800000 +#define DDRSS2_PHY_880_DATA 0x80800000 +#define DDRSS2_PHY_881_DATA 0x000E2010 +#define DDRSS2_PHY_882_DATA 0x76543210 +#define DDRSS2_PHY_883_DATA 0x00000008 +#define DDRSS2_PHY_884_DATA 0x02800280 +#define DDRSS2_PHY_885_DATA 0x02800280 +#define DDRSS2_PHY_886_DATA 0x02800280 +#define DDRSS2_PHY_887_DATA 0x02800280 +#define DDRSS2_PHY_888_DATA 0x00000280 +#define DDRSS2_PHY_889_DATA 0x0000A000 +#define DDRSS2_PHY_890_DATA 0x00A000A0 +#define DDRSS2_PHY_891_DATA 0x00A000A0 +#define DDRSS2_PHY_892_DATA 0x00A000A0 +#define DDRSS2_PHY_893_DATA 0x00A000A0 +#define DDRSS2_PHY_894_DATA 0x00A000A0 +#define DDRSS2_PHY_895_DATA 0x00A000A0 +#define DDRSS2_PHY_896_DATA 0x00A000A0 +#define DDRSS2_PHY_897_DATA 0x00A000A0 +#define DDRSS2_PHY_898_DATA 0x01C200A0 +#define DDRSS2_PHY_899_DATA 0x01A00005 +#define DDRSS2_PHY_900_DATA 0x00000000 +#define DDRSS2_PHY_901_DATA 0x00000000 +#define DDRSS2_PHY_902_DATA 0x00080200 +#define DDRSS2_PHY_903_DATA 0x00000000 +#define DDRSS2_PHY_904_DATA 0x20202000 +#define DDRSS2_PHY_905_DATA 0x20202020 +#define DDRSS2_PHY_906_DATA 0xF0F02020 +#define DDRSS2_PHY_907_DATA 0x00000000 +#define DDRSS2_PHY_908_DATA 0x00000000 +#define DDRSS2_PHY_909_DATA 0x00000000 +#define DDRSS2_PHY_910_DATA 0x00000000 +#define DDRSS2_PHY_911_DATA 0x00000000 +#define DDRSS2_PHY_912_DATA 0x00000000 +#define DDRSS2_PHY_913_DATA 0x00000000 +#define DDRSS2_PHY_914_DATA 0x00000000 +#define DDRSS2_PHY_915_DATA 0x00000000 +#define DDRSS2_PHY_916_DATA 0x00000000 +#define DDRSS2_PHY_917_DATA 0x00000000 +#define DDRSS2_PHY_918_DATA 0x00000000 +#define DDRSS2_PHY_919_DATA 0x00000000 +#define DDRSS2_PHY_920_DATA 0x00000000 +#define DDRSS2_PHY_921_DATA 0x00000000 +#define DDRSS2_PHY_922_DATA 0x00000000 +#define DDRSS2_PHY_923_DATA 0x00000000 +#define DDRSS2_PHY_924_DATA 0x00000000 +#define DDRSS2_PHY_925_DATA 0x00000000 +#define DDRSS2_PHY_926_DATA 0x00000000 +#define DDRSS2_PHY_927_DATA 0x00000000 +#define DDRSS2_PHY_928_DATA 0x00000000 +#define DDRSS2_PHY_929_DATA 0x00000000 +#define DDRSS2_PHY_930_DATA 0x00000000 +#define DDRSS2_PHY_931_DATA 0x00000000 +#define DDRSS2_PHY_932_DATA 0x00000000 +#define DDRSS2_PHY_933_DATA 0x00000000 +#define DDRSS2_PHY_934_DATA 0x00000000 +#define DDRSS2_PHY_935_DATA 0x00000000 +#define DDRSS2_PHY_936_DATA 0x00000000 +#define DDRSS2_PHY_937_DATA 0x00000000 +#define DDRSS2_PHY_938_DATA 0x00000000 +#define DDRSS2_PHY_939_DATA 0x00000000 +#define DDRSS2_PHY_940_DATA 0x00000000 +#define DDRSS2_PHY_941_DATA 0x00000000 +#define DDRSS2_PHY_942_DATA 0x00000000 +#define DDRSS2_PHY_943_DATA 0x00000000 +#define DDRSS2_PHY_944_DATA 0x00000000 +#define DDRSS2_PHY_945_DATA 0x00000000 +#define DDRSS2_PHY_946_DATA 0x00000000 +#define DDRSS2_PHY_947_DATA 0x00000000 +#define DDRSS2_PHY_948_DATA 0x00000000 +#define DDRSS2_PHY_949_DATA 0x00000000 +#define DDRSS2_PHY_950_DATA 0x00000000 +#define DDRSS2_PHY_951_DATA 0x00000000 +#define DDRSS2_PHY_952_DATA 0x00000000 +#define DDRSS2_PHY_953_DATA 0x00000000 +#define DDRSS2_PHY_954_DATA 0x00000000 +#define DDRSS2_PHY_955_DATA 0x00000000 +#define DDRSS2_PHY_956_DATA 0x00000000 +#define DDRSS2_PHY_957_DATA 0x00000000 +#define DDRSS2_PHY_958_DATA 0x00000000 +#define DDRSS2_PHY_959_DATA 0x00000000 +#define DDRSS2_PHY_960_DATA 0x00000000 +#define DDRSS2_PHY_961_DATA 0x00000000 +#define DDRSS2_PHY_962_DATA 0x00000000 +#define DDRSS2_PHY_963_DATA 0x00000000 +#define DDRSS2_PHY_964_DATA 0x00000000 +#define DDRSS2_PHY_965_DATA 0x00000000 +#define DDRSS2_PHY_966_DATA 0x00000000 +#define DDRSS2_PHY_967_DATA 0x00000000 +#define DDRSS2_PHY_968_DATA 0x00000000 +#define DDRSS2_PHY_969_DATA 0x00000000 +#define DDRSS2_PHY_970_DATA 0x00000000 +#define DDRSS2_PHY_971_DATA 0x00000000 +#define DDRSS2_PHY_972_DATA 0x00000000 +#define DDRSS2_PHY_973_DATA 0x00000000 +#define DDRSS2_PHY_974_DATA 0x00000000 +#define DDRSS2_PHY_975_DATA 0x00000000 +#define DDRSS2_PHY_976_DATA 0x00000000 +#define DDRSS2_PHY_977_DATA 0x00000000 +#define DDRSS2_PHY_978_DATA 0x00000000 +#define DDRSS2_PHY_979_DATA 0x00000000 +#define DDRSS2_PHY_980_DATA 0x00000000 +#define DDRSS2_PHY_981_DATA 0x00000000 +#define DDRSS2_PHY_982_DATA 0x00000000 +#define DDRSS2_PHY_983_DATA 0x00000000 +#define DDRSS2_PHY_984_DATA 0x00000000 +#define DDRSS2_PHY_985_DATA 0x00000000 +#define DDRSS2_PHY_986_DATA 0x00000000 +#define DDRSS2_PHY_987_DATA 0x00000000 +#define DDRSS2_PHY_988_DATA 0x00000000 +#define DDRSS2_PHY_989_DATA 0x00000000 +#define DDRSS2_PHY_990_DATA 0x00000000 +#define DDRSS2_PHY_991_DATA 0x00000000 +#define DDRSS2_PHY_992_DATA 0x00000000 +#define DDRSS2_PHY_993_DATA 0x00000000 +#define DDRSS2_PHY_994_DATA 0x00000000 +#define DDRSS2_PHY_995_DATA 0x00000000 +#define DDRSS2_PHY_996_DATA 0x00000000 +#define DDRSS2_PHY_997_DATA 0x00000000 +#define DDRSS2_PHY_998_DATA 0x00000000 +#define DDRSS2_PHY_999_DATA 0x00000000 +#define DDRSS2_PHY_1000_DATA 0x00000000 +#define DDRSS2_PHY_1001_DATA 0x00000000 +#define DDRSS2_PHY_1002_DATA 0x00000000 +#define DDRSS2_PHY_1003_DATA 0x00000000 +#define DDRSS2_PHY_1004_DATA 0x00000000 +#define DDRSS2_PHY_1005_DATA 0x00000000 +#define DDRSS2_PHY_1006_DATA 0x00000000 +#define DDRSS2_PHY_1007_DATA 0x00000000 +#define DDRSS2_PHY_1008_DATA 0x00000000 +#define DDRSS2_PHY_1009_DATA 0x00000000 +#define DDRSS2_PHY_1010_DATA 0x00000000 +#define DDRSS2_PHY_1011_DATA 0x00000000 +#define DDRSS2_PHY_1012_DATA 0x00000000 +#define DDRSS2_PHY_1013_DATA 0x00000000 +#define DDRSS2_PHY_1014_DATA 0x00000000 +#define DDRSS2_PHY_1015_DATA 0x00000000 +#define DDRSS2_PHY_1016_DATA 0x00000000 +#define DDRSS2_PHY_1017_DATA 0x00000000 +#define DDRSS2_PHY_1018_DATA 0x00000000 +#define DDRSS2_PHY_1019_DATA 0x00000000 +#define DDRSS2_PHY_1020_DATA 0x00000000 +#define DDRSS2_PHY_1021_DATA 0x00000000 +#define DDRSS2_PHY_1022_DATA 0x00000000 +#define DDRSS2_PHY_1023_DATA 0x00000000 +#define DDRSS2_PHY_1024_DATA 0x00000000 +#define DDRSS2_PHY_1025_DATA 0x00000000 +#define DDRSS2_PHY_1026_DATA 0x00000000 +#define DDRSS2_PHY_1027_DATA 0x00000000 +#define DDRSS2_PHY_1028_DATA 0x00000000 +#define DDRSS2_PHY_1029_DATA 0x00000100 +#define DDRSS2_PHY_1030_DATA 0x00000200 +#define DDRSS2_PHY_1031_DATA 0x00000000 +#define DDRSS2_PHY_1032_DATA 0x00000000 +#define DDRSS2_PHY_1033_DATA 0x00000000 +#define DDRSS2_PHY_1034_DATA 0x00000000 +#define DDRSS2_PHY_1035_DATA 0x00400000 +#define DDRSS2_PHY_1036_DATA 0x00000080 +#define DDRSS2_PHY_1037_DATA 0x00DCBA98 +#define DDRSS2_PHY_1038_DATA 0x03000000 +#define DDRSS2_PHY_1039_DATA 0x00200000 +#define DDRSS2_PHY_1040_DATA 0x00000000 +#define DDRSS2_PHY_1041_DATA 0x00000000 +#define DDRSS2_PHY_1042_DATA 0x00000000 +#define DDRSS2_PHY_1043_DATA 0x00000000 +#define DDRSS2_PHY_1044_DATA 0x00000000 +#define DDRSS2_PHY_1045_DATA 0x0000002A +#define DDRSS2_PHY_1046_DATA 0x00000015 +#define DDRSS2_PHY_1047_DATA 0x00000015 +#define DDRSS2_PHY_1048_DATA 0x0000002A +#define DDRSS2_PHY_1049_DATA 0x00000033 +#define DDRSS2_PHY_1050_DATA 0x0000000C +#define DDRSS2_PHY_1051_DATA 0x0000000C +#define DDRSS2_PHY_1052_DATA 0x00000033 +#define DDRSS2_PHY_1053_DATA 0x00543210 +#define DDRSS2_PHY_1054_DATA 0x003F0000 +#define DDRSS2_PHY_1055_DATA 0x000F3F3F +#define DDRSS2_PHY_1056_DATA 0x20202003 +#define DDRSS2_PHY_1057_DATA 0x00202020 +#define DDRSS2_PHY_1058_DATA 0x20008008 +#define DDRSS2_PHY_1059_DATA 0x00000810 +#define DDRSS2_PHY_1060_DATA 0x00000F00 +#define DDRSS2_PHY_1061_DATA 0x00000000 +#define DDRSS2_PHY_1062_DATA 0x00000000 +#define DDRSS2_PHY_1063_DATA 0x00000000 +#define DDRSS2_PHY_1064_DATA 0x000305CC +#define DDRSS2_PHY_1065_DATA 0x00030000 +#define DDRSS2_PHY_1066_DATA 0x00000300 +#define DDRSS2_PHY_1067_DATA 0x00000300 +#define DDRSS2_PHY_1068_DATA 0x00000300 +#define DDRSS2_PHY_1069_DATA 0x00000300 +#define DDRSS2_PHY_1070_DATA 0x00000300 +#define DDRSS2_PHY_1071_DATA 0x42080010 +#define DDRSS2_PHY_1072_DATA 0x0000803E +#define DDRSS2_PHY_1073_DATA 0x00000001 +#define DDRSS2_PHY_1074_DATA 0x01000102 +#define DDRSS2_PHY_1075_DATA 0x00008000 +#define DDRSS2_PHY_1076_DATA 0x00000000 +#define DDRSS2_PHY_1077_DATA 0x00000000 +#define DDRSS2_PHY_1078_DATA 0x00000000 +#define DDRSS2_PHY_1079_DATA 0x00000000 +#define DDRSS2_PHY_1080_DATA 0x00000000 +#define DDRSS2_PHY_1081_DATA 0x00000000 +#define DDRSS2_PHY_1082_DATA 0x00000000 +#define DDRSS2_PHY_1083_DATA 0x00000000 +#define DDRSS2_PHY_1084_DATA 0x00000000 +#define DDRSS2_PHY_1085_DATA 0x00000000 +#define DDRSS2_PHY_1086_DATA 0x00000000 +#define DDRSS2_PHY_1087_DATA 0x00000000 +#define DDRSS2_PHY_1088_DATA 0x00000000 +#define DDRSS2_PHY_1089_DATA 0x00000000 +#define DDRSS2_PHY_1090_DATA 0x00000000 +#define DDRSS2_PHY_1091_DATA 0x00000000 +#define DDRSS2_PHY_1092_DATA 0x00000000 +#define DDRSS2_PHY_1093_DATA 0x00000000 +#define DDRSS2_PHY_1094_DATA 0x00000000 +#define DDRSS2_PHY_1095_DATA 0x00000000 +#define DDRSS2_PHY_1096_DATA 0x00000000 +#define DDRSS2_PHY_1097_DATA 0x00000000 +#define DDRSS2_PHY_1098_DATA 0x00000000 +#define DDRSS2_PHY_1099_DATA 0x00000000 +#define DDRSS2_PHY_1100_DATA 0x00000000 +#define DDRSS2_PHY_1101_DATA 0x00000000 +#define DDRSS2_PHY_1102_DATA 0x00000000 +#define DDRSS2_PHY_1103_DATA 0x00000000 +#define DDRSS2_PHY_1104_DATA 0x00000000 +#define DDRSS2_PHY_1105_DATA 0x00000000 +#define DDRSS2_PHY_1106_DATA 0x00000000 +#define DDRSS2_PHY_1107_DATA 0x00000000 +#define DDRSS2_PHY_1108_DATA 0x00000000 +#define DDRSS2_PHY_1109_DATA 0x00000000 +#define DDRSS2_PHY_1110_DATA 0x00000000 +#define DDRSS2_PHY_1111_DATA 0x00000000 +#define DDRSS2_PHY_1112_DATA 0x00000000 +#define DDRSS2_PHY_1113_DATA 0x00000000 +#define DDRSS2_PHY_1114_DATA 0x00000000 +#define DDRSS2_PHY_1115_DATA 0x00000000 +#define DDRSS2_PHY_1116_DATA 0x00000000 +#define DDRSS2_PHY_1117_DATA 0x00000000 +#define DDRSS2_PHY_1118_DATA 0x00000000 +#define DDRSS2_PHY_1119_DATA 0x00000000 +#define DDRSS2_PHY_1120_DATA 0x00000000 +#define DDRSS2_PHY_1121_DATA 0x00000000 +#define DDRSS2_PHY_1122_DATA 0x00000000 +#define DDRSS2_PHY_1123_DATA 0x00000000 +#define DDRSS2_PHY_1124_DATA 0x00000000 +#define DDRSS2_PHY_1125_DATA 0x00000000 +#define DDRSS2_PHY_1126_DATA 0x00000000 +#define DDRSS2_PHY_1127_DATA 0x00000000 +#define DDRSS2_PHY_1128_DATA 0x00000000 +#define DDRSS2_PHY_1129_DATA 0x00000000 +#define DDRSS2_PHY_1130_DATA 0x00000000 +#define DDRSS2_PHY_1131_DATA 0x00000000 +#define DDRSS2_PHY_1132_DATA 0x00000000 +#define DDRSS2_PHY_1133_DATA 0x00000000 +#define DDRSS2_PHY_1134_DATA 0x00000000 +#define DDRSS2_PHY_1135_DATA 0x00000000 +#define DDRSS2_PHY_1136_DATA 0x00000000 +#define DDRSS2_PHY_1137_DATA 0x00000000 +#define DDRSS2_PHY_1138_DATA 0x00000000 +#define DDRSS2_PHY_1139_DATA 0x00000000 +#define DDRSS2_PHY_1140_DATA 0x00000000 +#define DDRSS2_PHY_1141_DATA 0x00000000 +#define DDRSS2_PHY_1142_DATA 0x00000000 +#define DDRSS2_PHY_1143_DATA 0x00000000 +#define DDRSS2_PHY_1144_DATA 0x00000000 +#define DDRSS2_PHY_1145_DATA 0x00000000 +#define DDRSS2_PHY_1146_DATA 0x00000000 +#define DDRSS2_PHY_1147_DATA 0x00000000 +#define DDRSS2_PHY_1148_DATA 0x00000000 +#define DDRSS2_PHY_1149_DATA 0x00000000 +#define DDRSS2_PHY_1150_DATA 0x00000000 +#define DDRSS2_PHY_1151_DATA 0x00000000 +#define DDRSS2_PHY_1152_DATA 0x00000000 +#define DDRSS2_PHY_1153_DATA 0x00000000 +#define DDRSS2_PHY_1154_DATA 0x00000000 +#define DDRSS2_PHY_1155_DATA 0x00000000 +#define DDRSS2_PHY_1156_DATA 0x00000000 +#define DDRSS2_PHY_1157_DATA 0x00000000 +#define DDRSS2_PHY_1158_DATA 0x00000000 +#define DDRSS2_PHY_1159_DATA 0x00000000 +#define DDRSS2_PHY_1160_DATA 0x00000000 +#define DDRSS2_PHY_1161_DATA 0x00000000 +#define DDRSS2_PHY_1162_DATA 0x00000000 +#define DDRSS2_PHY_1163_DATA 0x00000000 +#define DDRSS2_PHY_1164_DATA 0x00000000 +#define DDRSS2_PHY_1165_DATA 0x00000000 +#define DDRSS2_PHY_1166_DATA 0x00000000 +#define DDRSS2_PHY_1167_DATA 0x00000000 +#define DDRSS2_PHY_1168_DATA 0x00000000 +#define DDRSS2_PHY_1169_DATA 0x00000000 +#define DDRSS2_PHY_1170_DATA 0x00000000 +#define DDRSS2_PHY_1171_DATA 0x00000000 +#define DDRSS2_PHY_1172_DATA 0x00000000 +#define DDRSS2_PHY_1173_DATA 0x00000000 +#define DDRSS2_PHY_1174_DATA 0x00000000 +#define DDRSS2_PHY_1175_DATA 0x00000000 +#define DDRSS2_PHY_1176_DATA 0x00000000 +#define DDRSS2_PHY_1177_DATA 0x00000000 +#define DDRSS2_PHY_1178_DATA 0x00000000 +#define DDRSS2_PHY_1179_DATA 0x00000000 +#define DDRSS2_PHY_1180_DATA 0x00000000 +#define DDRSS2_PHY_1181_DATA 0x00000000 +#define DDRSS2_PHY_1182_DATA 0x00000000 +#define DDRSS2_PHY_1183_DATA 0x00000000 +#define DDRSS2_PHY_1184_DATA 0x00000000 +#define DDRSS2_PHY_1185_DATA 0x00000000 +#define DDRSS2_PHY_1186_DATA 0x00000000 +#define DDRSS2_PHY_1187_DATA 0x00000000 +#define DDRSS2_PHY_1188_DATA 0x00000000 +#define DDRSS2_PHY_1189_DATA 0x00000000 +#define DDRSS2_PHY_1190_DATA 0x00000000 +#define DDRSS2_PHY_1191_DATA 0x00000000 +#define DDRSS2_PHY_1192_DATA 0x00000000 +#define DDRSS2_PHY_1193_DATA 0x00000000 +#define DDRSS2_PHY_1194_DATA 0x00000000 +#define DDRSS2_PHY_1195_DATA 0x00000000 +#define DDRSS2_PHY_1196_DATA 0x00000000 +#define DDRSS2_PHY_1197_DATA 0x00000000 +#define DDRSS2_PHY_1198_DATA 0x00000000 +#define DDRSS2_PHY_1199_DATA 0x00000000 +#define DDRSS2_PHY_1200_DATA 0x00000000 +#define DDRSS2_PHY_1201_DATA 0x00000000 +#define DDRSS2_PHY_1202_DATA 0x00000000 +#define DDRSS2_PHY_1203_DATA 0x00000000 +#define DDRSS2_PHY_1204_DATA 0x00000000 +#define DDRSS2_PHY_1205_DATA 0x00000000 +#define DDRSS2_PHY_1206_DATA 0x00000000 +#define DDRSS2_PHY_1207_DATA 0x00000000 +#define DDRSS2_PHY_1208_DATA 0x00000000 +#define DDRSS2_PHY_1209_DATA 0x00000000 +#define DDRSS2_PHY_1210_DATA 0x00000000 +#define DDRSS2_PHY_1211_DATA 0x00000000 +#define DDRSS2_PHY_1212_DATA 0x00000000 +#define DDRSS2_PHY_1213_DATA 0x00000000 +#define DDRSS2_PHY_1214_DATA 0x00000000 +#define DDRSS2_PHY_1215_DATA 0x00000000 +#define DDRSS2_PHY_1216_DATA 0x00000000 +#define DDRSS2_PHY_1217_DATA 0x00000000 +#define DDRSS2_PHY_1218_DATA 0x00000000 +#define DDRSS2_PHY_1219_DATA 0x00000000 +#define DDRSS2_PHY_1220_DATA 0x00000000 +#define DDRSS2_PHY_1221_DATA 0x00000000 +#define DDRSS2_PHY_1222_DATA 0x00000000 +#define DDRSS2_PHY_1223_DATA 0x00000000 +#define DDRSS2_PHY_1224_DATA 0x00000000 +#define DDRSS2_PHY_1225_DATA 0x00000000 +#define DDRSS2_PHY_1226_DATA 0x00000000 +#define DDRSS2_PHY_1227_DATA 0x00000000 +#define DDRSS2_PHY_1228_DATA 0x00000000 +#define DDRSS2_PHY_1229_DATA 0x00000000 +#define DDRSS2_PHY_1230_DATA 0x00000000 +#define DDRSS2_PHY_1231_DATA 0x00000000 +#define DDRSS2_PHY_1232_DATA 0x00000000 +#define DDRSS2_PHY_1233_DATA 0x00000000 +#define DDRSS2_PHY_1234_DATA 0x00000000 +#define DDRSS2_PHY_1235_DATA 0x00000000 +#define DDRSS2_PHY_1236_DATA 0x00000000 +#define DDRSS2_PHY_1237_DATA 0x00000000 +#define DDRSS2_PHY_1238_DATA 0x00000000 +#define DDRSS2_PHY_1239_DATA 0x00000000 +#define DDRSS2_PHY_1240_DATA 0x00000000 +#define DDRSS2_PHY_1241_DATA 0x00000000 +#define DDRSS2_PHY_1242_DATA 0x00000000 +#define DDRSS2_PHY_1243_DATA 0x00000000 +#define DDRSS2_PHY_1244_DATA 0x00000000 +#define DDRSS2_PHY_1245_DATA 0x00000000 +#define DDRSS2_PHY_1246_DATA 0x00000000 +#define DDRSS2_PHY_1247_DATA 0x00000000 +#define DDRSS2_PHY_1248_DATA 0x00000000 +#define DDRSS2_PHY_1249_DATA 0x00000000 +#define DDRSS2_PHY_1250_DATA 0x00000000 +#define DDRSS2_PHY_1251_DATA 0x00000000 +#define DDRSS2_PHY_1252_DATA 0x00000000 +#define DDRSS2_PHY_1253_DATA 0x00000000 +#define DDRSS2_PHY_1254_DATA 0x00000000 +#define DDRSS2_PHY_1255_DATA 0x00000000 +#define DDRSS2_PHY_1256_DATA 0x00000000 +#define DDRSS2_PHY_1257_DATA 0x00000000 +#define DDRSS2_PHY_1258_DATA 0x00000000 +#define DDRSS2_PHY_1259_DATA 0x00000000 +#define DDRSS2_PHY_1260_DATA 0x00000000 +#define DDRSS2_PHY_1261_DATA 0x00000000 +#define DDRSS2_PHY_1262_DATA 0x00000000 +#define DDRSS2_PHY_1263_DATA 0x00000000 +#define DDRSS2_PHY_1264_DATA 0x00000000 +#define DDRSS2_PHY_1265_DATA 0x00000000 +#define DDRSS2_PHY_1266_DATA 0x00000000 +#define DDRSS2_PHY_1267_DATA 0x00000000 +#define DDRSS2_PHY_1268_DATA 0x00000000 +#define DDRSS2_PHY_1269_DATA 0x00000000 +#define DDRSS2_PHY_1270_DATA 0x00000000 +#define DDRSS2_PHY_1271_DATA 0x00000000 +#define DDRSS2_PHY_1272_DATA 0x00000000 +#define DDRSS2_PHY_1273_DATA 0x00000000 +#define DDRSS2_PHY_1274_DATA 0x00000000 +#define DDRSS2_PHY_1275_DATA 0x00000000 +#define DDRSS2_PHY_1276_DATA 0x00000000 +#define DDRSS2_PHY_1277_DATA 0x00000000 +#define DDRSS2_PHY_1278_DATA 0x00000000 +#define DDRSS2_PHY_1279_DATA 0x00000000 +#define DDRSS2_PHY_1280_DATA 0x00000000 +#define DDRSS2_PHY_1281_DATA 0x00010100 +#define DDRSS2_PHY_1282_DATA 0x00000000 +#define DDRSS2_PHY_1283_DATA 0x00000000 +#define DDRSS2_PHY_1284_DATA 0x00050000 +#define DDRSS2_PHY_1285_DATA 0x04000000 +#define DDRSS2_PHY_1286_DATA 0x00000055 +#define DDRSS2_PHY_1287_DATA 0x00000000 +#define DDRSS2_PHY_1288_DATA 0x00000000 +#define DDRSS2_PHY_1289_DATA 0x00000000 +#define DDRSS2_PHY_1290_DATA 0x00000000 +#define DDRSS2_PHY_1291_DATA 0x00002001 +#define DDRSS2_PHY_1292_DATA 0x0000400F +#define DDRSS2_PHY_1293_DATA 0x50020028 +#define DDRSS2_PHY_1294_DATA 0x01010000 +#define DDRSS2_PHY_1295_DATA 0x80080001 +#define DDRSS2_PHY_1296_DATA 0x10200000 +#define DDRSS2_PHY_1297_DATA 0x00000008 +#define DDRSS2_PHY_1298_DATA 0x00000000 +#define DDRSS2_PHY_1299_DATA 0x01090E00 +#define DDRSS2_PHY_1300_DATA 0x00040101 +#define DDRSS2_PHY_1301_DATA 0x0000010F +#define DDRSS2_PHY_1302_DATA 0x00000000 +#define DDRSS2_PHY_1303_DATA 0x00000064 +#define DDRSS2_PHY_1304_DATA 0x00000000 +#define DDRSS2_PHY_1305_DATA 0x01010000 +#define DDRSS2_PHY_1306_DATA 0x01080402 +#define DDRSS2_PHY_1307_DATA 0x01200F02 +#define DDRSS2_PHY_1308_DATA 0x00194280 +#define DDRSS2_PHY_1309_DATA 0x00000004 +#define DDRSS2_PHY_1310_DATA 0x00042000 +#define DDRSS2_PHY_1311_DATA 0x00000000 +#define DDRSS2_PHY_1312_DATA 0x00000000 +#define DDRSS2_PHY_1313_DATA 0x00000000 +#define DDRSS2_PHY_1314_DATA 0x00000000 +#define DDRSS2_PHY_1315_DATA 0x00000000 +#define DDRSS2_PHY_1316_DATA 0x00000000 +#define DDRSS2_PHY_1317_DATA 0x01000000 +#define DDRSS2_PHY_1318_DATA 0x00000705 +#define DDRSS2_PHY_1319_DATA 0x00000054 +#define DDRSS2_PHY_1320_DATA 0x00030820 +#define DDRSS2_PHY_1321_DATA 0x00010820 +#define DDRSS2_PHY_1322_DATA 0x00010820 +#define DDRSS2_PHY_1323_DATA 0x00010820 +#define DDRSS2_PHY_1324_DATA 0x00010820 +#define DDRSS2_PHY_1325_DATA 0x00010820 +#define DDRSS2_PHY_1326_DATA 0x00010820 +#define DDRSS2_PHY_1327_DATA 0x00010820 +#define DDRSS2_PHY_1328_DATA 0x00010820 +#define DDRSS2_PHY_1329_DATA 0x00000000 +#define DDRSS2_PHY_1330_DATA 0x00000074 +#define DDRSS2_PHY_1331_DATA 0x00000400 +#define DDRSS2_PHY_1332_DATA 0x00000108 +#define DDRSS2_PHY_1333_DATA 0x00000000 +#define DDRSS2_PHY_1334_DATA 0x00000000 +#define DDRSS2_PHY_1335_DATA 0x00000000 +#define DDRSS2_PHY_1336_DATA 0x00000000 +#define DDRSS2_PHY_1337_DATA 0x00000000 +#define DDRSS2_PHY_1338_DATA 0x03000000 +#define DDRSS2_PHY_1339_DATA 0x00000000 +#define DDRSS2_PHY_1340_DATA 0x00000000 +#define DDRSS2_PHY_1341_DATA 0x00000000 +#define DDRSS2_PHY_1342_DATA 0x04102006 +#define DDRSS2_PHY_1343_DATA 0x00041020 +#define DDRSS2_PHY_1344_DATA 0x01C98C98 +#define DDRSS2_PHY_1345_DATA 0x3F400000 +#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS2_PHY_1347_DATA 0x0000001F +#define DDRSS2_PHY_1348_DATA 0x00000000 +#define DDRSS2_PHY_1349_DATA 0x00000000 +#define DDRSS2_PHY_1350_DATA 0x00000000 +#define DDRSS2_PHY_1351_DATA 0x00010000 +#define DDRSS2_PHY_1352_DATA 0x00000000 +#define DDRSS2_PHY_1353_DATA 0x00000000 +#define DDRSS2_PHY_1354_DATA 0x00000000 +#define DDRSS2_PHY_1355_DATA 0x00000000 +#define DDRSS2_PHY_1356_DATA 0x76543210 +#define DDRSS2_PHY_1357_DATA 0x00010198 +#define DDRSS2_PHY_1358_DATA 0x00000000 +#define DDRSS2_PHY_1359_DATA 0x00000000 +#define DDRSS2_PHY_1360_DATA 0x00000000 +#define DDRSS2_PHY_1361_DATA 0x00040700 +#define DDRSS2_PHY_1362_DATA 0x00000000 +#define DDRSS2_PHY_1363_DATA 0x00000000 +#define DDRSS2_PHY_1364_DATA 0x00000000 +#define DDRSS2_PHY_1365_DATA 0x00000000 +#define DDRSS2_PHY_1366_DATA 0x00000000 +#define DDRSS2_PHY_1367_DATA 0x00000002 +#define DDRSS2_PHY_1368_DATA 0x00000000 +#define DDRSS2_PHY_1369_DATA 0x00000000 +#define DDRSS2_PHY_1370_DATA 0x00000000 +#define DDRSS2_PHY_1371_DATA 0x00000000 +#define DDRSS2_PHY_1372_DATA 0x00000000 +#define DDRSS2_PHY_1373_DATA 0x00000000 +#define DDRSS2_PHY_1374_DATA 0x00080000 +#define DDRSS2_PHY_1375_DATA 0x000007FF +#define DDRSS2_PHY_1376_DATA 0x00000000 +#define DDRSS2_PHY_1377_DATA 0x00000000 +#define DDRSS2_PHY_1378_DATA 0x00000000 +#define DDRSS2_PHY_1379_DATA 0x00000000 +#define DDRSS2_PHY_1380_DATA 0x00000000 +#define DDRSS2_PHY_1381_DATA 0x00000000 +#define DDRSS2_PHY_1382_DATA 0x000FFFFF +#define DDRSS2_PHY_1383_DATA 0x000FFFFF +#define DDRSS2_PHY_1384_DATA 0x0000FFFF +#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS2_PHY_1386_DATA 0x030FFFFF +#define DDRSS2_PHY_1387_DATA 0x01FFFFFF +#define DDRSS2_PHY_1388_DATA 0x0000FFFF +#define DDRSS2_PHY_1389_DATA 0x00000000 +#define DDRSS2_PHY_1390_DATA 0x00000000 +#define DDRSS2_PHY_1391_DATA 0x00000000 +#define DDRSS2_PHY_1392_DATA 0x00000000 +#define DDRSS2_PHY_1393_DATA 0x0001F7C0 +#define DDRSS2_PHY_1394_DATA 0x00000003 +#define DDRSS2_PHY_1395_DATA 0x00000000 +#define DDRSS2_PHY_1396_DATA 0x00001142 +#define DDRSS2_PHY_1397_DATA 0x040207AB +#define DDRSS2_PHY_1398_DATA 0x01000080 +#define DDRSS2_PHY_1399_DATA 0x03900390 +#define DDRSS2_PHY_1400_DATA 0x03900390 +#define DDRSS2_PHY_1401_DATA 0x00000390 +#define DDRSS2_PHY_1402_DATA 0x00000390 +#define DDRSS2_PHY_1403_DATA 0x00000390 +#define DDRSS2_PHY_1404_DATA 0x00000390 +#define DDRSS2_PHY_1405_DATA 0x00000005 +#define DDRSS2_PHY_1406_DATA 0x01813FCC +#define DDRSS2_PHY_1407_DATA 0x000000CC +#define DDRSS2_PHY_1408_DATA 0x0C000DFF +#define DDRSS2_PHY_1409_DATA 0x30000DFF +#define DDRSS2_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1411_DATA 0x000100F0 +#define DDRSS2_PHY_1412_DATA 0x780DFFCC +#define DDRSS2_PHY_1413_DATA 0x00007E31 +#define DDRSS2_PHY_1414_DATA 0x000CBF11 +#define DDRSS2_PHY_1415_DATA 0x01990010 +#define DDRSS2_PHY_1416_DATA 0x000CBF11 +#define DDRSS2_PHY_1417_DATA 0x01990010 +#define DDRSS2_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1419_DATA 0x00EF00F0 +#define DDRSS2_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS2_PHY_1421_DATA 0x01FF00F0 +#define DDRSS2_PHY_1422_DATA 0x20040006 + +#define DDRSS3_CTL_00_DATA 0x00000B00 +#define DDRSS3_CTL_01_DATA 0x00000000 +#define DDRSS3_CTL_02_DATA 0x00000000 +#define DDRSS3_CTL_03_DATA 0x00000000 +#define DDRSS3_CTL_04_DATA 0x00000000 +#define DDRSS3_CTL_05_DATA 0x00000000 +#define DDRSS3_CTL_06_DATA 0x00000000 +#define DDRSS3_CTL_07_DATA 0x00002AF8 +#define DDRSS3_CTL_08_DATA 0x0001ADAF +#define DDRSS3_CTL_09_DATA 0x00000005 +#define DDRSS3_CTL_10_DATA 0x0000006E +#define DDRSS3_CTL_11_DATA 0x000681C8 +#define DDRSS3_CTL_12_DATA 0x004111C9 +#define DDRSS3_CTL_13_DATA 0x00000005 +#define DDRSS3_CTL_14_DATA 0x000010A9 +#define DDRSS3_CTL_15_DATA 0x000681C8 +#define DDRSS3_CTL_16_DATA 0x004111C9 +#define DDRSS3_CTL_17_DATA 0x00000005 +#define DDRSS3_CTL_18_DATA 0x000010A9 +#define DDRSS3_CTL_19_DATA 0x01010000 +#define DDRSS3_CTL_20_DATA 0x01011001 +#define DDRSS3_CTL_21_DATA 0x02010000 +#define DDRSS3_CTL_22_DATA 0x00020100 +#define DDRSS3_CTL_23_DATA 0x0000000B +#define DDRSS3_CTL_24_DATA 0x0000001C +#define DDRSS3_CTL_25_DATA 0x00000000 +#define DDRSS3_CTL_26_DATA 0x00000000 +#define DDRSS3_CTL_27_DATA 0x03020200 +#define DDRSS3_CTL_28_DATA 0x00005656 +#define DDRSS3_CTL_29_DATA 0x00100000 +#define DDRSS3_CTL_30_DATA 0x00000000 +#define DDRSS3_CTL_31_DATA 0x00000000 +#define DDRSS3_CTL_32_DATA 0x00000000 +#define DDRSS3_CTL_33_DATA 0x00000000 +#define DDRSS3_CTL_34_DATA 0x040C0000 +#define DDRSS3_CTL_35_DATA 0x12501250 +#define DDRSS3_CTL_36_DATA 0x00050804 +#define DDRSS3_CTL_37_DATA 0x09040008 +#define DDRSS3_CTL_38_DATA 0x15000204 +#define DDRSS3_CTL_39_DATA 0x1760008B +#define DDRSS3_CTL_40_DATA 0x1500422B +#define DDRSS3_CTL_41_DATA 0x1760008B +#define DDRSS3_CTL_42_DATA 0x2000422B +#define DDRSS3_CTL_43_DATA 0x000A0A09 +#define DDRSS3_CTL_44_DATA 0x040003C5 +#define DDRSS3_CTL_45_DATA 0x1E161104 +#define DDRSS3_CTL_46_DATA 0x1000922C +#define DDRSS3_CTL_47_DATA 0x1E161110 +#define DDRSS3_CTL_48_DATA 0x1000922C +#define DDRSS3_CTL_49_DATA 0x02030410 +#define DDRSS3_CTL_50_DATA 0x2C060500 +#define DDRSS3_CTL_51_DATA 0x08292C29 +#define DDRSS3_CTL_52_DATA 0x14000E0A +#define DDRSS3_CTL_53_DATA 0x04010A0A +#define DDRSS3_CTL_54_DATA 0x01010004 +#define DDRSS3_CTL_55_DATA 0x0454540A +#define DDRSS3_CTL_56_DATA 0x04313104 +#define DDRSS3_CTL_57_DATA 0x00003131 +#define DDRSS3_CTL_58_DATA 0x00010100 +#define DDRSS3_CTL_59_DATA 0x03010000 +#define DDRSS3_CTL_60_DATA 0x00001508 +#define DDRSS3_CTL_61_DATA 0x00000068 +#define DDRSS3_CTL_62_DATA 0x0000032B +#define DDRSS3_CTL_63_DATA 0x00001035 +#define DDRSS3_CTL_64_DATA 0x0000032B +#define DDRSS3_CTL_65_DATA 0x00001035 +#define DDRSS3_CTL_66_DATA 0x00000005 +#define DDRSS3_CTL_67_DATA 0x00050000 +#define DDRSS3_CTL_68_DATA 0x00CB0005 +#define DDRSS3_CTL_69_DATA 0x00CB0200 +#define DDRSS3_CTL_70_DATA 0x00400200 +#define DDRSS3_CTL_71_DATA 0x00120103 +#define DDRSS3_CTL_72_DATA 0x00100005 +#define DDRSS3_CTL_73_DATA 0x2F080010 +#define DDRSS3_CTL_74_DATA 0x0505012F +#define DDRSS3_CTL_75_DATA 0x0401030A +#define DDRSS3_CTL_76_DATA 0x041E100B +#define DDRSS3_CTL_77_DATA 0x100B0401 +#define DDRSS3_CTL_78_DATA 0x0001041E +#define DDRSS3_CTL_79_DATA 0x00160016 +#define DDRSS3_CTL_80_DATA 0x033B033B +#define DDRSS3_CTL_81_DATA 0x033B033B +#define DDRSS3_CTL_82_DATA 0x03050505 +#define DDRSS3_CTL_83_DATA 0x03010303 +#define DDRSS3_CTL_84_DATA 0x200B100B +#define DDRSS3_CTL_85_DATA 0x04041004 +#define DDRSS3_CTL_86_DATA 0x200B100B +#define DDRSS3_CTL_87_DATA 0x04041004 +#define DDRSS3_CTL_88_DATA 0x03010000 +#define DDRSS3_CTL_89_DATA 0x00010000 +#define DDRSS3_CTL_90_DATA 0x00000000 +#define DDRSS3_CTL_91_DATA 0x00000000 +#define DDRSS3_CTL_92_DATA 0x01000000 +#define DDRSS3_CTL_93_DATA 0x80104002 +#define DDRSS3_CTL_94_DATA 0x00000000 +#define DDRSS3_CTL_95_DATA 0x00040005 +#define DDRSS3_CTL_96_DATA 0x00000000 +#define DDRSS3_CTL_97_DATA 0x00050000 +#define DDRSS3_CTL_98_DATA 0x00000004 +#define DDRSS3_CTL_99_DATA 0x00000000 +#define DDRSS3_CTL_100_DATA 0x00040005 +#define DDRSS3_CTL_101_DATA 0x00000000 +#define DDRSS3_CTL_102_DATA 0x000018C0 +#define DDRSS3_CTL_103_DATA 0x000018C0 +#define DDRSS3_CTL_104_DATA 0x000018C0 +#define DDRSS3_CTL_105_DATA 0x000018C0 +#define DDRSS3_CTL_106_DATA 0x000018C0 +#define DDRSS3_CTL_107_DATA 0x00000000 +#define DDRSS3_CTL_108_DATA 0x000002B5 +#define DDRSS3_CTL_109_DATA 0x00040D40 +#define DDRSS3_CTL_110_DATA 0x00040D40 +#define DDRSS3_CTL_111_DATA 0x00040D40 +#define DDRSS3_CTL_112_DATA 0x00040D40 +#define DDRSS3_CTL_113_DATA 0x00040D40 +#define DDRSS3_CTL_114_DATA 0x00000000 +#define DDRSS3_CTL_115_DATA 0x00007173 +#define DDRSS3_CTL_116_DATA 0x00040D40 +#define DDRSS3_CTL_117_DATA 0x00040D40 +#define DDRSS3_CTL_118_DATA 0x00040D40 +#define DDRSS3_CTL_119_DATA 0x00040D40 +#define DDRSS3_CTL_120_DATA 0x00040D40 +#define DDRSS3_CTL_121_DATA 0x00000000 +#define DDRSS3_CTL_122_DATA 0x00007173 +#define DDRSS3_CTL_123_DATA 0x00000000 +#define DDRSS3_CTL_124_DATA 0x00000000 +#define DDRSS3_CTL_125_DATA 0x00000000 +#define DDRSS3_CTL_126_DATA 0x00000000 +#define DDRSS3_CTL_127_DATA 0x00000000 +#define DDRSS3_CTL_128_DATA 0x00000000 +#define DDRSS3_CTL_129_DATA 0x00000000 +#define DDRSS3_CTL_130_DATA 0x00000000 +#define DDRSS3_CTL_131_DATA 0x0B030500 +#define DDRSS3_CTL_132_DATA 0x00040B04 +#define DDRSS3_CTL_133_DATA 0x0A090000 +#define DDRSS3_CTL_134_DATA 0x0A090701 +#define DDRSS3_CTL_135_DATA 0x0900000E +#define DDRSS3_CTL_136_DATA 0x0907010A +#define DDRSS3_CTL_137_DATA 0x00000E0A +#define DDRSS3_CTL_138_DATA 0x07010A09 +#define DDRSS3_CTL_139_DATA 0x000E0A09 +#define DDRSS3_CTL_140_DATA 0x07000401 +#define DDRSS3_CTL_141_DATA 0x00000000 +#define DDRSS3_CTL_142_DATA 0x00000000 +#define DDRSS3_CTL_143_DATA 0x00000000 +#define DDRSS3_CTL_144_DATA 0x00000000 +#define DDRSS3_CTL_145_DATA 0x00000000 +#define DDRSS3_CTL_146_DATA 0x00000000 +#define DDRSS3_CTL_147_DATA 0x00000000 +#define DDRSS3_CTL_148_DATA 0x08080000 +#define DDRSS3_CTL_149_DATA 0x01000000 +#define DDRSS3_CTL_150_DATA 0x800000C0 +#define DDRSS3_CTL_151_DATA 0x800000C0 +#define DDRSS3_CTL_152_DATA 0x800000C0 +#define DDRSS3_CTL_153_DATA 0x00000000 +#define DDRSS3_CTL_154_DATA 0x00001500 +#define DDRSS3_CTL_155_DATA 0x00000000 +#define DDRSS3_CTL_156_DATA 0x00000001 +#define DDRSS3_CTL_157_DATA 0x00000002 +#define DDRSS3_CTL_158_DATA 0x0000100E +#define DDRSS3_CTL_159_DATA 0x00000000 +#define DDRSS3_CTL_160_DATA 0x00000000 +#define DDRSS3_CTL_161_DATA 0x00000000 +#define DDRSS3_CTL_162_DATA 0x00000000 +#define DDRSS3_CTL_163_DATA 0x00000000 +#define DDRSS3_CTL_164_DATA 0x000B0000 +#define DDRSS3_CTL_165_DATA 0x000E0006 +#define DDRSS3_CTL_166_DATA 0x000E0404 +#define DDRSS3_CTL_167_DATA 0x00D601AB +#define DDRSS3_CTL_168_DATA 0x10100216 +#define DDRSS3_CTL_169_DATA 0x01AB0216 +#define DDRSS3_CTL_170_DATA 0x021600D6 +#define DDRSS3_CTL_171_DATA 0x02161010 +#define DDRSS3_CTL_172_DATA 0x00000000 +#define DDRSS3_CTL_173_DATA 0x00000000 +#define DDRSS3_CTL_174_DATA 0x00000000 +#define DDRSS3_CTL_175_DATA 0x3FF40084 +#define DDRSS3_CTL_176_DATA 0xF3003FF4 +#define DDRSS3_CTL_177_DATA 0x0000F3F3 +#define DDRSS3_CTL_178_DATA 0x35350000 +#define DDRSS3_CTL_179_DATA 0x27270035 +#define DDRSS3_CTL_180_DATA 0x0F0F0000 +#define DDRSS3_CTL_181_DATA 0x16000000 +#define DDRSS3_CTL_182_DATA 0x00841616 +#define DDRSS3_CTL_183_DATA 0x3FF43FF4 +#define DDRSS3_CTL_184_DATA 0xF3F3F300 +#define DDRSS3_CTL_185_DATA 0x00000000 +#define DDRSS3_CTL_186_DATA 0x00353535 +#define DDRSS3_CTL_187_DATA 0x00002727 +#define DDRSS3_CTL_188_DATA 0x00000F0F +#define DDRSS3_CTL_189_DATA 0x16161600 +#define DDRSS3_CTL_190_DATA 0x00000020 +#define DDRSS3_CTL_191_DATA 0x01000000 +#define DDRSS3_CTL_192_DATA 0x00000001 +#define DDRSS3_CTL_193_DATA 0x00000000 +#define DDRSS3_CTL_194_DATA 0x01000000 +#define DDRSS3_CTL_195_DATA 0x00000001 +#define DDRSS3_CTL_196_DATA 0x00000000 +#define DDRSS3_CTL_197_DATA 0x00000000 +#define DDRSS3_CTL_198_DATA 0x00000000 +#define DDRSS3_CTL_199_DATA 0x00000000 +#define DDRSS3_CTL_200_DATA 0x00000000 +#define DDRSS3_CTL_201_DATA 0x00000000 +#define DDRSS3_CTL_202_DATA 0x00000000 +#define DDRSS3_CTL_203_DATA 0x00000000 +#define DDRSS3_CTL_204_DATA 0x00000000 +#define DDRSS3_CTL_205_DATA 0x00000000 +#define DDRSS3_CTL_206_DATA 0x02000000 +#define DDRSS3_CTL_207_DATA 0x01080101 +#define DDRSS3_CTL_208_DATA 0x00000000 +#define DDRSS3_CTL_209_DATA 0x00000000 +#define DDRSS3_CTL_210_DATA 0x00000000 +#define DDRSS3_CTL_211_DATA 0x00000000 +#define DDRSS3_CTL_212_DATA 0x00000000 +#define DDRSS3_CTL_213_DATA 0x00000000 +#define DDRSS3_CTL_214_DATA 0x00000000 +#define DDRSS3_CTL_215_DATA 0x00000000 +#define DDRSS3_CTL_216_DATA 0x00000000 +#define DDRSS3_CTL_217_DATA 0x00000000 +#define DDRSS3_CTL_218_DATA 0x00000000 +#define DDRSS3_CTL_219_DATA 0x00000000 +#define DDRSS3_CTL_220_DATA 0x00000000 +#define DDRSS3_CTL_221_DATA 0x00000000 +#define DDRSS3_CTL_222_DATA 0x00001000 +#define DDRSS3_CTL_223_DATA 0x006403E8 +#define DDRSS3_CTL_224_DATA 0x00000000 +#define DDRSS3_CTL_225_DATA 0x00000000 +#define DDRSS3_CTL_226_DATA 0x00000000 +#define DDRSS3_CTL_227_DATA 0x15110000 +#define DDRSS3_CTL_228_DATA 0x00040C18 +#define DDRSS3_CTL_229_DATA 0xF000C000 +#define DDRSS3_CTL_230_DATA 0x0000F000 +#define DDRSS3_CTL_231_DATA 0x00000000 +#define DDRSS3_CTL_232_DATA 0x00000000 +#define DDRSS3_CTL_233_DATA 0xC0000000 +#define DDRSS3_CTL_234_DATA 0xF000F000 +#define DDRSS3_CTL_235_DATA 0x00000000 +#define DDRSS3_CTL_236_DATA 0x00000000 +#define DDRSS3_CTL_237_DATA 0x00000000 +#define DDRSS3_CTL_238_DATA 0xF000C000 +#define DDRSS3_CTL_239_DATA 0x0000F000 +#define DDRSS3_CTL_240_DATA 0x00000000 +#define DDRSS3_CTL_241_DATA 0x00000000 +#define DDRSS3_CTL_242_DATA 0x00030000 +#define DDRSS3_CTL_243_DATA 0x00000000 +#define DDRSS3_CTL_244_DATA 0x00000000 +#define DDRSS3_CTL_245_DATA 0x00000000 +#define DDRSS3_CTL_246_DATA 0x00000000 +#define DDRSS3_CTL_247_DATA 0x00000000 +#define DDRSS3_CTL_248_DATA 0x00000000 +#define DDRSS3_CTL_249_DATA 0x00000000 +#define DDRSS3_CTL_250_DATA 0x00000000 +#define DDRSS3_CTL_251_DATA 0x00000000 +#define DDRSS3_CTL_252_DATA 0x00000000 +#define DDRSS3_CTL_253_DATA 0x00000000 +#define DDRSS3_CTL_254_DATA 0x00000000 +#define DDRSS3_CTL_255_DATA 0x00000000 +#define DDRSS3_CTL_256_DATA 0x00000000 +#define DDRSS3_CTL_257_DATA 0x01000200 +#define DDRSS3_CTL_258_DATA 0x00370040 +#define DDRSS3_CTL_259_DATA 0x00020008 +#define DDRSS3_CTL_260_DATA 0x00400100 +#define DDRSS3_CTL_261_DATA 0x00400855 +#define DDRSS3_CTL_262_DATA 0x01000200 +#define DDRSS3_CTL_263_DATA 0x08550040 +#define DDRSS3_CTL_264_DATA 0x00000040 +#define DDRSS3_CTL_265_DATA 0x006B0003 +#define DDRSS3_CTL_266_DATA 0x0100006B +#define DDRSS3_CTL_267_DATA 0x03030303 +#define DDRSS3_CTL_268_DATA 0x00000000 +#define DDRSS3_CTL_269_DATA 0x00000202 +#define DDRSS3_CTL_270_DATA 0x00001FFF +#define DDRSS3_CTL_271_DATA 0x3FFF2000 +#define DDRSS3_CTL_272_DATA 0x03FF0000 +#define DDRSS3_CTL_273_DATA 0x000103FF +#define DDRSS3_CTL_274_DATA 0x0FFF0B00 +#define DDRSS3_CTL_275_DATA 0x01010001 +#define DDRSS3_CTL_276_DATA 0x01010101 +#define DDRSS3_CTL_277_DATA 0x01180101 +#define DDRSS3_CTL_278_DATA 0x00030000 +#define DDRSS3_CTL_279_DATA 0x00000000 +#define DDRSS3_CTL_280_DATA 0x00000000 +#define DDRSS3_CTL_281_DATA 0x00000000 +#define DDRSS3_CTL_282_DATA 0x00000000 +#define DDRSS3_CTL_283_DATA 0x00000000 +#define DDRSS3_CTL_284_DATA 0x00000000 +#define DDRSS3_CTL_285_DATA 0x00000000 +#define DDRSS3_CTL_286_DATA 0x00040101 +#define DDRSS3_CTL_287_DATA 0x04010100 +#define DDRSS3_CTL_288_DATA 0x00000000 +#define DDRSS3_CTL_289_DATA 0x00000000 +#define DDRSS3_CTL_290_DATA 0x03030300 +#define DDRSS3_CTL_291_DATA 0x00010101 +#define DDRSS3_CTL_292_DATA 0x00000000 +#define DDRSS3_CTL_293_DATA 0x00000000 +#define DDRSS3_CTL_294_DATA 0x00000000 +#define DDRSS3_CTL_295_DATA 0x00000000 +#define DDRSS3_CTL_296_DATA 0x00000000 +#define DDRSS3_CTL_297_DATA 0xFFFFFFFF +#define DDRSS3_CTL_298_DATA 0x00000FFF +#define DDRSS3_CTL_299_DATA 0x00000000 +#define DDRSS3_CTL_300_DATA 0x00000000 +#define DDRSS3_CTL_301_DATA 0x00000000 +#define DDRSS3_CTL_302_DATA 0x00000000 +#define DDRSS3_CTL_303_DATA 0x00000000 +#define DDRSS3_CTL_304_DATA 0x00000000 +#define DDRSS3_CTL_305_DATA 0x00000000 +#define DDRSS3_CTL_306_DATA 0x00000000 +#define DDRSS3_CTL_307_DATA 0x00000000 +#define DDRSS3_CTL_308_DATA 0x00000000 +#define DDRSS3_CTL_309_DATA 0x00000000 +#define DDRSS3_CTL_310_DATA 0x00000000 +#define DDRSS3_CTL_311_DATA 0x00000000 +#define DDRSS3_CTL_312_DATA 0x00000000 +#define DDRSS3_CTL_313_DATA 0x01000000 +#define DDRSS3_CTL_314_DATA 0x00020201 +#define DDRSS3_CTL_315_DATA 0x01000101 +#define DDRSS3_CTL_316_DATA 0x01010001 +#define DDRSS3_CTL_317_DATA 0x00010101 +#define DDRSS3_CTL_318_DATA 0x050A0A03 +#define DDRSS3_CTL_319_DATA 0x10082323 +#define DDRSS3_CTL_320_DATA 0x00090310 +#define DDRSS3_CTL_321_DATA 0x0B0C030F +#define DDRSS3_CTL_322_DATA 0x0B0C0306 +#define DDRSS3_CTL_323_DATA 0x0C090006 +#define DDRSS3_CTL_324_DATA 0x0100000C +#define DDRSS3_CTL_325_DATA 0x08040801 +#define DDRSS3_CTL_326_DATA 0x00000004 +#define DDRSS3_CTL_327_DATA 0x00000000 +#define DDRSS3_CTL_328_DATA 0x00010000 +#define DDRSS3_CTL_329_DATA 0x00280D00 +#define DDRSS3_CTL_330_DATA 0x00000001 +#define DDRSS3_CTL_331_DATA 0x00030001 +#define DDRSS3_CTL_332_DATA 0x00000000 +#define DDRSS3_CTL_333_DATA 0x00000000 +#define DDRSS3_CTL_334_DATA 0x00000000 +#define DDRSS3_CTL_335_DATA 0x00000000 +#define DDRSS3_CTL_336_DATA 0x00000000 +#define DDRSS3_CTL_337_DATA 0x00000000 +#define DDRSS3_CTL_338_DATA 0x00000000 +#define DDRSS3_CTL_339_DATA 0x00000000 +#define DDRSS3_CTL_340_DATA 0x01000000 +#define DDRSS3_CTL_341_DATA 0x00000001 +#define DDRSS3_CTL_342_DATA 0x00010100 +#define DDRSS3_CTL_343_DATA 0x03030000 +#define DDRSS3_CTL_344_DATA 0x00000000 +#define DDRSS3_CTL_345_DATA 0x00000000 +#define DDRSS3_CTL_346_DATA 0x00000000 +#define DDRSS3_CTL_347_DATA 0x00000000 +#define DDRSS3_CTL_348_DATA 0x00000000 +#define DDRSS3_CTL_349_DATA 0x00000000 +#define DDRSS3_CTL_350_DATA 0x00000000 +#define DDRSS3_CTL_351_DATA 0x00000000 +#define DDRSS3_CTL_352_DATA 0x00000000 +#define DDRSS3_CTL_353_DATA 0x00000000 +#define DDRSS3_CTL_354_DATA 0x00000000 +#define DDRSS3_CTL_355_DATA 0x00000000 +#define DDRSS3_CTL_356_DATA 0x00000000 +#define DDRSS3_CTL_357_DATA 0x00000000 +#define DDRSS3_CTL_358_DATA 0x00000000 +#define DDRSS3_CTL_359_DATA 0x00000000 +#define DDRSS3_CTL_360_DATA 0x000556AA +#define DDRSS3_CTL_361_DATA 0x000AAAAA +#define DDRSS3_CTL_362_DATA 0x000AA955 +#define DDRSS3_CTL_363_DATA 0x00055555 +#define DDRSS3_CTL_364_DATA 0x000B3133 +#define DDRSS3_CTL_365_DATA 0x0004CD33 +#define DDRSS3_CTL_366_DATA 0x0004CECC +#define DDRSS3_CTL_367_DATA 0x000B32CC +#define DDRSS3_CTL_368_DATA 0x00010300 +#define DDRSS3_CTL_369_DATA 0x03000100 +#define DDRSS3_CTL_370_DATA 0x00000000 +#define DDRSS3_CTL_371_DATA 0x00000000 +#define DDRSS3_CTL_372_DATA 0x00000000 +#define DDRSS3_CTL_373_DATA 0x00000000 +#define DDRSS3_CTL_374_DATA 0x00000000 +#define DDRSS3_CTL_375_DATA 0x00000000 +#define DDRSS3_CTL_376_DATA 0x00000000 +#define DDRSS3_CTL_377_DATA 0x00010000 +#define DDRSS3_CTL_378_DATA 0x00000404 +#define DDRSS3_CTL_379_DATA 0x00000000 +#define DDRSS3_CTL_380_DATA 0x00000000 +#define DDRSS3_CTL_381_DATA 0x00000000 +#define DDRSS3_CTL_382_DATA 0x00000000 +#define DDRSS3_CTL_383_DATA 0x00000000 +#define DDRSS3_CTL_384_DATA 0x00000000 +#define DDRSS3_CTL_385_DATA 0x00000000 +#define DDRSS3_CTL_386_DATA 0x00000000 +#define DDRSS3_CTL_387_DATA 0x3A3A1B00 +#define DDRSS3_CTL_388_DATA 0x000A0000 +#define DDRSS3_CTL_389_DATA 0x000000C6 +#define DDRSS3_CTL_390_DATA 0x00000200 +#define DDRSS3_CTL_391_DATA 0x00000200 +#define DDRSS3_CTL_392_DATA 0x00000200 +#define DDRSS3_CTL_393_DATA 0x00000200 +#define DDRSS3_CTL_394_DATA 0x00000270 +#define DDRSS3_CTL_395_DATA 0x000007BC +#define DDRSS3_CTL_396_DATA 0x00000204 +#define DDRSS3_CTL_397_DATA 0x0000206A +#define DDRSS3_CTL_398_DATA 0x00000200 +#define DDRSS3_CTL_399_DATA 0x00000200 +#define DDRSS3_CTL_400_DATA 0x00000200 +#define DDRSS3_CTL_401_DATA 0x00000200 +#define DDRSS3_CTL_402_DATA 0x0000613E +#define DDRSS3_CTL_403_DATA 0x00014424 +#define DDRSS3_CTL_404_DATA 0x00000E19 +#define DDRSS3_CTL_405_DATA 0x0000206A +#define DDRSS3_CTL_406_DATA 0x00000200 +#define DDRSS3_CTL_407_DATA 0x00000200 +#define DDRSS3_CTL_408_DATA 0x00000200 +#define DDRSS3_CTL_409_DATA 0x00000200 +#define DDRSS3_CTL_410_DATA 0x0000613E +#define DDRSS3_CTL_411_DATA 0x00014424 +#define DDRSS3_CTL_412_DATA 0x02020E19 +#define DDRSS3_CTL_413_DATA 0x03030202 +#define DDRSS3_CTL_414_DATA 0x00000022 +#define DDRSS3_CTL_415_DATA 0x00000000 +#define DDRSS3_CTL_416_DATA 0x00000000 +#define DDRSS3_CTL_417_DATA 0x00001403 +#define DDRSS3_CTL_418_DATA 0x000007D0 +#define DDRSS3_CTL_419_DATA 0x00000000 +#define DDRSS3_CTL_420_DATA 0x00000000 +#define DDRSS3_CTL_421_DATA 0x00030000 +#define DDRSS3_CTL_422_DATA 0x0007001F +#define DDRSS3_CTL_423_DATA 0x001B0033 +#define DDRSS3_CTL_424_DATA 0x001B0033 +#define DDRSS3_CTL_425_DATA 0x00000000 +#define DDRSS3_CTL_426_DATA 0x00000000 +#define DDRSS3_CTL_427_DATA 0x02000000 +#define DDRSS3_CTL_428_DATA 0x01000404 +#define DDRSS3_CTL_429_DATA 0x0B220B22 +#define DDRSS3_CTL_430_DATA 0x00000105 +#define DDRSS3_CTL_431_DATA 0x00010101 +#define DDRSS3_CTL_432_DATA 0x00010101 +#define DDRSS3_CTL_433_DATA 0x00010001 +#define DDRSS3_CTL_434_DATA 0x00000101 +#define DDRSS3_CTL_435_DATA 0x02000201 +#define DDRSS3_CTL_436_DATA 0x02010000 +#define DDRSS3_CTL_437_DATA 0x00000200 +#define DDRSS3_CTL_438_DATA 0x28060000 +#define DDRSS3_CTL_439_DATA 0x00000128 +#define DDRSS3_CTL_440_DATA 0xFFFFFFFF +#define DDRSS3_CTL_441_DATA 0xFFFFFFFF +#define DDRSS3_CTL_442_DATA 0x00000000 +#define DDRSS3_CTL_443_DATA 0x00000000 +#define DDRSS3_CTL_444_DATA 0x00000000 +#define DDRSS3_CTL_445_DATA 0x00000000 +#define DDRSS3_CTL_446_DATA 0x00000000 +#define DDRSS3_CTL_447_DATA 0x00000000 +#define DDRSS3_CTL_448_DATA 0x00000000 +#define DDRSS3_CTL_449_DATA 0x00000000 +#define DDRSS3_CTL_450_DATA 0x00000000 +#define DDRSS3_CTL_451_DATA 0x00000000 +#define DDRSS3_CTL_452_DATA 0x00000000 +#define DDRSS3_CTL_453_DATA 0x00000000 +#define DDRSS3_CTL_454_DATA 0x00000000 +#define DDRSS3_CTL_455_DATA 0x00000000 +#define DDRSS3_CTL_456_DATA 0x00000000 +#define DDRSS3_CTL_457_DATA 0x00000000 +#define DDRSS3_CTL_458_DATA 0x00000000 + +#define DDRSS3_PI_00_DATA 0x00000B00 +#define DDRSS3_PI_01_DATA 0x00000000 +#define DDRSS3_PI_02_DATA 0x00000000 +#define DDRSS3_PI_03_DATA 0x00000000 +#define DDRSS3_PI_04_DATA 0x00000000 +#define DDRSS3_PI_05_DATA 0x00000101 +#define DDRSS3_PI_06_DATA 0x00640000 +#define DDRSS3_PI_07_DATA 0x00000001 +#define DDRSS3_PI_08_DATA 0x00000000 +#define DDRSS3_PI_09_DATA 0x00000000 +#define DDRSS3_PI_10_DATA 0x00000000 +#define DDRSS3_PI_11_DATA 0x00000000 +#define DDRSS3_PI_12_DATA 0x00000003 +#define DDRSS3_PI_13_DATA 0x00010001 +#define DDRSS3_PI_14_DATA 0x0800000F +#define DDRSS3_PI_15_DATA 0x00000103 +#define DDRSS3_PI_16_DATA 0x00000005 +#define DDRSS3_PI_17_DATA 0x00000000 +#define DDRSS3_PI_18_DATA 0x00000000 +#define DDRSS3_PI_19_DATA 0x00000000 +#define DDRSS3_PI_20_DATA 0x00000000 +#define DDRSS3_PI_21_DATA 0x00000000 +#define DDRSS3_PI_22_DATA 0x00000000 +#define DDRSS3_PI_23_DATA 0x00000000 +#define DDRSS3_PI_24_DATA 0x00000000 +#define DDRSS3_PI_25_DATA 0x00000000 +#define DDRSS3_PI_26_DATA 0x00010100 +#define DDRSS3_PI_27_DATA 0x00280A00 +#define DDRSS3_PI_28_DATA 0x00000000 +#define DDRSS3_PI_29_DATA 0x0F000000 +#define DDRSS3_PI_30_DATA 0x00003200 +#define DDRSS3_PI_31_DATA 0x00000000 +#define DDRSS3_PI_32_DATA 0x00000000 +#define DDRSS3_PI_33_DATA 0x01010102 +#define DDRSS3_PI_34_DATA 0x00000000 +#define DDRSS3_PI_35_DATA 0x000000AA +#define DDRSS3_PI_36_DATA 0x00000055 +#define DDRSS3_PI_37_DATA 0x000000B5 +#define DDRSS3_PI_38_DATA 0x0000004A +#define DDRSS3_PI_39_DATA 0x00000056 +#define DDRSS3_PI_40_DATA 0x000000A9 +#define DDRSS3_PI_41_DATA 0x000000A9 +#define DDRSS3_PI_42_DATA 0x000000B5 +#define DDRSS3_PI_43_DATA 0x00000000 +#define DDRSS3_PI_44_DATA 0x00000000 +#define DDRSS3_PI_45_DATA 0x000F0F00 +#define DDRSS3_PI_46_DATA 0x0000001B +#define DDRSS3_PI_47_DATA 0x000007D0 +#define DDRSS3_PI_48_DATA 0x00000300 +#define DDRSS3_PI_49_DATA 0x00000000 +#define DDRSS3_PI_50_DATA 0x00000000 +#define DDRSS3_PI_51_DATA 0x01000000 +#define DDRSS3_PI_52_DATA 0x00010101 +#define DDRSS3_PI_53_DATA 0x00000000 +#define DDRSS3_PI_54_DATA 0x00030000 +#define DDRSS3_PI_55_DATA 0x0F000000 +#define DDRSS3_PI_56_DATA 0x00000017 +#define DDRSS3_PI_57_DATA 0x00000000 +#define DDRSS3_PI_58_DATA 0x00000000 +#define DDRSS3_PI_59_DATA 0x00000000 +#define DDRSS3_PI_60_DATA 0x0A0A140A +#define DDRSS3_PI_61_DATA 0x10020201 +#define DDRSS3_PI_62_DATA 0x00020805 +#define DDRSS3_PI_63_DATA 0x01000404 +#define DDRSS3_PI_64_DATA 0x00000000 +#define DDRSS3_PI_65_DATA 0x00000000 +#define DDRSS3_PI_66_DATA 0x00000100 +#define DDRSS3_PI_67_DATA 0x0002020F +#define DDRSS3_PI_68_DATA 0x00340000 +#define DDRSS3_PI_69_DATA 0x00000000 +#define DDRSS3_PI_70_DATA 0x00000000 +#define DDRSS3_PI_71_DATA 0x0000FFFF +#define DDRSS3_PI_72_DATA 0x01000000 +#define DDRSS3_PI_73_DATA 0x00080000 +#define DDRSS3_PI_74_DATA 0x02000200 +#define DDRSS3_PI_75_DATA 0x01000100 +#define DDRSS3_PI_76_DATA 0x01000000 +#define DDRSS3_PI_77_DATA 0x02000200 +#define DDRSS3_PI_78_DATA 0x00000200 +#define DDRSS3_PI_79_DATA 0x00000000 +#define DDRSS3_PI_80_DATA 0x00000000 +#define DDRSS3_PI_81_DATA 0x00000000 +#define DDRSS3_PI_82_DATA 0x00000000 +#define DDRSS3_PI_83_DATA 0x00000000 +#define DDRSS3_PI_84_DATA 0x00000000 +#define DDRSS3_PI_85_DATA 0x00000000 +#define DDRSS3_PI_86_DATA 0x00000000 +#define DDRSS3_PI_87_DATA 0x00000000 +#define DDRSS3_PI_88_DATA 0x00000000 +#define DDRSS3_PI_89_DATA 0x00000000 +#define DDRSS3_PI_90_DATA 0x00000000 +#define DDRSS3_PI_91_DATA 0x00000400 +#define DDRSS3_PI_92_DATA 0x02010000 +#define DDRSS3_PI_93_DATA 0x00080003 +#define DDRSS3_PI_94_DATA 0x00080000 +#define DDRSS3_PI_95_DATA 0x00000001 +#define DDRSS3_PI_96_DATA 0x00000000 +#define DDRSS3_PI_97_DATA 0x0000AA00 +#define DDRSS3_PI_98_DATA 0x00000000 +#define DDRSS3_PI_99_DATA 0x00000000 +#define DDRSS3_PI_100_DATA 0x00010000 +#define DDRSS3_PI_101_DATA 0x00000000 +#define DDRSS3_PI_102_DATA 0x00000000 +#define DDRSS3_PI_103_DATA 0x00000000 +#define DDRSS3_PI_104_DATA 0x00000000 +#define DDRSS3_PI_105_DATA 0x00000000 +#define DDRSS3_PI_106_DATA 0x00000000 +#define DDRSS3_PI_107_DATA 0x00000000 +#define DDRSS3_PI_108_DATA 0x00000000 +#define DDRSS3_PI_109_DATA 0x00000000 +#define DDRSS3_PI_110_DATA 0x00000000 +#define DDRSS3_PI_111_DATA 0x00000000 +#define DDRSS3_PI_112_DATA 0x00000000 +#define DDRSS3_PI_113_DATA 0x00000000 +#define DDRSS3_PI_114_DATA 0x00000000 +#define DDRSS3_PI_115_DATA 0x00000000 +#define DDRSS3_PI_116_DATA 0x00000000 +#define DDRSS3_PI_117_DATA 0x00000000 +#define DDRSS3_PI_118_DATA 0x00000000 +#define DDRSS3_PI_119_DATA 0x00000000 +#define DDRSS3_PI_120_DATA 0x00000000 +#define DDRSS3_PI_121_DATA 0x00000000 +#define DDRSS3_PI_122_DATA 0x00000000 +#define DDRSS3_PI_123_DATA 0x00000000 +#define DDRSS3_PI_124_DATA 0x00000000 +#define DDRSS3_PI_125_DATA 0x00000008 +#define DDRSS3_PI_126_DATA 0x00000000 +#define DDRSS3_PI_127_DATA 0x00000000 +#define DDRSS3_PI_128_DATA 0x00000000 +#define DDRSS3_PI_129_DATA 0x00000000 +#define DDRSS3_PI_130_DATA 0x00000000 +#define DDRSS3_PI_131_DATA 0x00000000 +#define DDRSS3_PI_132_DATA 0x00000000 +#define DDRSS3_PI_133_DATA 0x00000000 +#define DDRSS3_PI_134_DATA 0x00000002 +#define DDRSS3_PI_135_DATA 0x00000000 +#define DDRSS3_PI_136_DATA 0x00000000 +#define DDRSS3_PI_137_DATA 0x0000000A +#define DDRSS3_PI_138_DATA 0x00000019 +#define DDRSS3_PI_139_DATA 0x00000100 +#define DDRSS3_PI_140_DATA 0x00000000 +#define DDRSS3_PI_141_DATA 0x00000000 +#define DDRSS3_PI_142_DATA 0x00000000 +#define DDRSS3_PI_143_DATA 0x00000000 +#define DDRSS3_PI_144_DATA 0x01000000 +#define DDRSS3_PI_145_DATA 0x00010003 +#define DDRSS3_PI_146_DATA 0x02000101 +#define DDRSS3_PI_147_DATA 0x01030001 +#define DDRSS3_PI_148_DATA 0x00010400 +#define DDRSS3_PI_149_DATA 0x06000105 +#define DDRSS3_PI_150_DATA 0x01070001 +#define DDRSS3_PI_151_DATA 0x00000000 +#define DDRSS3_PI_152_DATA 0x00000000 +#define DDRSS3_PI_153_DATA 0x00000000 +#define DDRSS3_PI_154_DATA 0x00010001 +#define DDRSS3_PI_155_DATA 0x00000000 +#define DDRSS3_PI_156_DATA 0x00000000 +#define DDRSS3_PI_157_DATA 0x00000000 +#define DDRSS3_PI_158_DATA 0x00000000 +#define DDRSS3_PI_159_DATA 0x00000401 +#define DDRSS3_PI_160_DATA 0x00000000 +#define DDRSS3_PI_161_DATA 0x05010000 +#define DDRSS3_PI_162_DATA 0x00000001 +#define DDRSS3_PI_163_DATA 0x2B2B0201 +#define DDRSS3_PI_164_DATA 0x00000034 +#define DDRSS3_PI_165_DATA 0x00000068 +#define DDRSS3_PI_166_DATA 0x00020068 +#define DDRSS3_PI_167_DATA 0x02000200 +#define DDRSS3_PI_168_DATA 0x50120C04 +#define DDRSS3_PI_169_DATA 0x00155012 +#define DDRSS3_PI_170_DATA 0x00000068 +#define DDRSS3_PI_171_DATA 0x0000032B +#define DDRSS3_PI_172_DATA 0x00001035 +#define DDRSS3_PI_173_DATA 0x0000032B +#define DDRSS3_PI_174_DATA 0x04001035 +#define DDRSS3_PI_175_DATA 0x01010404 +#define DDRSS3_PI_176_DATA 0x00001500 +#define DDRSS3_PI_177_DATA 0x00150015 +#define DDRSS3_PI_178_DATA 0x01000100 +#define DDRSS3_PI_179_DATA 0x00000100 +#define DDRSS3_PI_180_DATA 0x00000000 +#define DDRSS3_PI_181_DATA 0x01010101 +#define DDRSS3_PI_182_DATA 0x00000000 +#define DDRSS3_PI_183_DATA 0x00000000 +#define DDRSS3_PI_184_DATA 0x00000000 +#define DDRSS3_PI_185_DATA 0x19040000 +#define DDRSS3_PI_186_DATA 0x0E0E0219 +#define DDRSS3_PI_187_DATA 0x00040402 +#define DDRSS3_PI_188_DATA 0x000D0035 +#define DDRSS3_PI_189_DATA 0x00218049 +#define DDRSS3_PI_190_DATA 0x00218049 +#define DDRSS3_PI_191_DATA 0x01000101 +#define DDRSS3_PI_192_DATA 0x0004000E +#define DDRSS3_PI_193_DATA 0x00040216 +#define DDRSS3_PI_194_DATA 0x01000216 +#define DDRSS3_PI_195_DATA 0x000F000F +#define DDRSS3_PI_196_DATA 0x02170100 +#define DDRSS3_PI_197_DATA 0x01000217 +#define DDRSS3_PI_198_DATA 0x02170217 +#define DDRSS3_PI_199_DATA 0x2F1B3200 +#define DDRSS3_PI_200_DATA 0x01012F1B +#define DDRSS3_PI_201_DATA 0x0A070601 +#define DDRSS3_PI_202_DATA 0x1F130A0D +#define DDRSS3_PI_203_DATA 0x1F130A14 +#define DDRSS3_PI_204_DATA 0x0000C014 +#define DDRSS3_PI_205_DATA 0x00C01000 +#define DDRSS3_PI_206_DATA 0x00C01000 +#define DDRSS3_PI_207_DATA 0x00021000 +#define DDRSS3_PI_208_DATA 0x0024000E +#define DDRSS3_PI_209_DATA 0x00240216 +#define DDRSS3_PI_210_DATA 0x00110216 +#define DDRSS3_PI_211_DATA 0x32000056 +#define DDRSS3_PI_212_DATA 0x00000101 +#define DDRSS3_PI_213_DATA 0x005F0036 +#define DDRSS3_PI_214_DATA 0x03013212 +#define DDRSS3_PI_215_DATA 0x00003600 +#define DDRSS3_PI_216_DATA 0x3212005F +#define DDRSS3_PI_217_DATA 0x09000001 +#define DDRSS3_PI_218_DATA 0x06010504 +#define DDRSS3_PI_219_DATA 0x04000364 +#define DDRSS3_PI_220_DATA 0x0A032001 +#define DDRSS3_PI_221_DATA 0x2C31110A +#define DDRSS3_PI_222_DATA 0x00002918 +#define DDRSS3_PI_223_DATA 0x6000838E +#define DDRSS3_PI_224_DATA 0x1E202008 +#define DDRSS3_PI_225_DATA 0x2C311116 +#define DDRSS3_PI_226_DATA 0x00002918 +#define DDRSS3_PI_227_DATA 0x6000838E +#define DDRSS3_PI_228_DATA 0x1E202008 +#define DDRSS3_PI_229_DATA 0x0000C616 +#define DDRSS3_PI_230_DATA 0x000007BC +#define DDRSS3_PI_231_DATA 0x0000206A +#define DDRSS3_PI_232_DATA 0x00014424 +#define DDRSS3_PI_233_DATA 0x0000206A +#define DDRSS3_PI_234_DATA 0x00014424 +#define DDRSS3_PI_235_DATA 0x033B0016 +#define DDRSS3_PI_236_DATA 0x0303033B +#define DDRSS3_PI_237_DATA 0x002AF803 +#define DDRSS3_PI_238_DATA 0x0001ADAF +#define DDRSS3_PI_239_DATA 0x00000005 +#define DDRSS3_PI_240_DATA 0x0000006E +#define DDRSS3_PI_241_DATA 0x00000016 +#define DDRSS3_PI_242_DATA 0x000681C8 +#define DDRSS3_PI_243_DATA 0x0001ADAF +#define DDRSS3_PI_244_DATA 0x00000005 +#define DDRSS3_PI_245_DATA 0x000010A9 +#define DDRSS3_PI_246_DATA 0x0000033B +#define DDRSS3_PI_247_DATA 0x000681C8 +#define DDRSS3_PI_248_DATA 0x0001ADAF +#define DDRSS3_PI_249_DATA 0x00000005 +#define DDRSS3_PI_250_DATA 0x000010A9 +#define DDRSS3_PI_251_DATA 0x0100033B +#define DDRSS3_PI_252_DATA 0x00370040 +#define DDRSS3_PI_253_DATA 0x00010008 +#define DDRSS3_PI_254_DATA 0x08550040 +#define DDRSS3_PI_255_DATA 0x00010040 +#define DDRSS3_PI_256_DATA 0x08550040 +#define DDRSS3_PI_257_DATA 0x00000340 +#define DDRSS3_PI_258_DATA 0x006B006B +#define DDRSS3_PI_259_DATA 0x08040404 +#define DDRSS3_PI_260_DATA 0x00000055 +#define DDRSS3_PI_261_DATA 0x55083C5A +#define DDRSS3_PI_262_DATA 0x5A000000 +#define DDRSS3_PI_263_DATA 0x0055083C +#define DDRSS3_PI_264_DATA 0x3C5A0000 +#define DDRSS3_PI_265_DATA 0x00005508 +#define DDRSS3_PI_266_DATA 0x0C3C5A00 +#define DDRSS3_PI_267_DATA 0x080F0E0D +#define DDRSS3_PI_268_DATA 0x000B0A09 +#define DDRSS3_PI_269_DATA 0x00030201 +#define DDRSS3_PI_270_DATA 0x01000000 +#define DDRSS3_PI_271_DATA 0x04020201 +#define DDRSS3_PI_272_DATA 0x00080804 +#define DDRSS3_PI_273_DATA 0x00000000 +#define DDRSS3_PI_274_DATA 0x00000000 +#define DDRSS3_PI_275_DATA 0x35F30084 +#define DDRSS3_PI_276_DATA 0x00160000 +#define DDRSS3_PI_277_DATA 0x35F33FF4 +#define DDRSS3_PI_278_DATA 0x00160F27 +#define DDRSS3_PI_279_DATA 0x35F33FF4 +#define DDRSS3_PI_280_DATA 0x00160F27 +#define DDRSS3_PI_281_DATA 0x35F30084 +#define DDRSS3_PI_282_DATA 0x00160000 +#define DDRSS3_PI_283_DATA 0x35F33FF4 +#define DDRSS3_PI_284_DATA 0x00160F27 +#define DDRSS3_PI_285_DATA 0x35F33FF4 +#define DDRSS3_PI_286_DATA 0x00160F27 +#define DDRSS3_PI_287_DATA 0x35F30084 +#define DDRSS3_PI_288_DATA 0x00160000 +#define DDRSS3_PI_289_DATA 0x35F33FF4 +#define DDRSS3_PI_290_DATA 0x00160F27 +#define DDRSS3_PI_291_DATA 0x35F33FF4 +#define DDRSS3_PI_292_DATA 0x00160F27 +#define DDRSS3_PI_293_DATA 0x35F30084 +#define DDRSS3_PI_294_DATA 0x00160000 +#define DDRSS3_PI_295_DATA 0x35F33FF4 +#define DDRSS3_PI_296_DATA 0x00160F27 +#define DDRSS3_PI_297_DATA 0x35F33FF4 +#define DDRSS3_PI_298_DATA 0x00160F27 +#define DDRSS3_PI_299_DATA 0x00000000 + +#define DDRSS3_PHY_00_DATA 0x000004F0 +#define DDRSS3_PHY_01_DATA 0x00000000 +#define DDRSS3_PHY_02_DATA 0x00030200 +#define DDRSS3_PHY_03_DATA 0x00000000 +#define DDRSS3_PHY_04_DATA 0x00000000 +#define DDRSS3_PHY_05_DATA 0x01030000 +#define DDRSS3_PHY_06_DATA 0x00010000 +#define DDRSS3_PHY_07_DATA 0x01030004 +#define DDRSS3_PHY_08_DATA 0x01000000 +#define DDRSS3_PHY_09_DATA 0x00000000 +#define DDRSS3_PHY_10_DATA 0x00000000 +#define DDRSS3_PHY_11_DATA 0x01000001 +#define DDRSS3_PHY_12_DATA 0x00000200 +#define DDRSS3_PHY_13_DATA 0x000800C0 +#define DDRSS3_PHY_14_DATA 0x060100CC +#define DDRSS3_PHY_15_DATA 0x00030066 +#define DDRSS3_PHY_16_DATA 0x00000000 +#define DDRSS3_PHY_17_DATA 0x00000301 +#define DDRSS3_PHY_18_DATA 0x0000AAAA +#define DDRSS3_PHY_19_DATA 0x00005555 +#define DDRSS3_PHY_20_DATA 0x0000B5B5 +#define DDRSS3_PHY_21_DATA 0x00004A4A +#define DDRSS3_PHY_22_DATA 0x00005656 +#define DDRSS3_PHY_23_DATA 0x0000A9A9 +#define DDRSS3_PHY_24_DATA 0x0000A9A9 +#define DDRSS3_PHY_25_DATA 0x0000B5B5 +#define DDRSS3_PHY_26_DATA 0x00000000 +#define DDRSS3_PHY_27_DATA 0x00000000 +#define DDRSS3_PHY_28_DATA 0x2A000000 +#define DDRSS3_PHY_29_DATA 0x00000808 +#define DDRSS3_PHY_30_DATA 0x0F000000 +#define DDRSS3_PHY_31_DATA 0x00000F08 +#define DDRSS3_PHY_32_DATA 0x10400000 +#define DDRSS3_PHY_33_DATA 0x0C002006 +#define DDRSS3_PHY_34_DATA 0x00000000 +#define DDRSS3_PHY_35_DATA 0x00000000 +#define DDRSS3_PHY_36_DATA 0x55555555 +#define DDRSS3_PHY_37_DATA 0xAAAAAAAA +#define DDRSS3_PHY_38_DATA 0x55555555 +#define DDRSS3_PHY_39_DATA 0xAAAAAAAA +#define DDRSS3_PHY_40_DATA 0x00005555 +#define DDRSS3_PHY_41_DATA 0x01000100 +#define DDRSS3_PHY_42_DATA 0x00800180 +#define DDRSS3_PHY_43_DATA 0x00000001 +#define DDRSS3_PHY_44_DATA 0x00000000 +#define DDRSS3_PHY_45_DATA 0x00000000 +#define DDRSS3_PHY_46_DATA 0x00000000 +#define DDRSS3_PHY_47_DATA 0x00000000 +#define DDRSS3_PHY_48_DATA 0x00000000 +#define DDRSS3_PHY_49_DATA 0x00000000 +#define DDRSS3_PHY_50_DATA 0x00000000 +#define DDRSS3_PHY_51_DATA 0x00000000 +#define DDRSS3_PHY_52_DATA 0x00000000 +#define DDRSS3_PHY_53_DATA 0x00000000 +#define DDRSS3_PHY_54_DATA 0x00000000 +#define DDRSS3_PHY_55_DATA 0x00000000 +#define DDRSS3_PHY_56_DATA 0x00000000 +#define DDRSS3_PHY_57_DATA 0x00000000 +#define DDRSS3_PHY_58_DATA 0x00000000 +#define DDRSS3_PHY_59_DATA 0x00000000 +#define DDRSS3_PHY_60_DATA 0x00000000 +#define DDRSS3_PHY_61_DATA 0x00000000 +#define DDRSS3_PHY_62_DATA 0x00000000 +#define DDRSS3_PHY_63_DATA 0x00000000 +#define DDRSS3_PHY_64_DATA 0x00000000 +#define DDRSS3_PHY_65_DATA 0x00000000 +#define DDRSS3_PHY_66_DATA 0x00000104 +#define DDRSS3_PHY_67_DATA 0x00000120 +#define DDRSS3_PHY_68_DATA 0x00000000 +#define DDRSS3_PHY_69_DATA 0x00000000 +#define DDRSS3_PHY_70_DATA 0x00000000 +#define DDRSS3_PHY_71_DATA 0x00000000 +#define DDRSS3_PHY_72_DATA 0x00000000 +#define DDRSS3_PHY_73_DATA 0x00000000 +#define DDRSS3_PHY_74_DATA 0x00000000 +#define DDRSS3_PHY_75_DATA 0x00000001 +#define DDRSS3_PHY_76_DATA 0x07FF0000 +#define DDRSS3_PHY_77_DATA 0x0080081F +#define DDRSS3_PHY_78_DATA 0x00081020 +#define DDRSS3_PHY_79_DATA 0x04010000 +#define DDRSS3_PHY_80_DATA 0x00000000 +#define DDRSS3_PHY_81_DATA 0x00000000 +#define DDRSS3_PHY_82_DATA 0x00000000 +#define DDRSS3_PHY_83_DATA 0x00000100 +#define DDRSS3_PHY_84_DATA 0x01CC0C01 +#define DDRSS3_PHY_85_DATA 0x1003CC0C +#define DDRSS3_PHY_86_DATA 0x20000140 +#define DDRSS3_PHY_87_DATA 0x07FF0200 +#define DDRSS3_PHY_88_DATA 0x0000DD01 +#define DDRSS3_PHY_89_DATA 0x10100303 +#define DDRSS3_PHY_90_DATA 0x10101010 +#define DDRSS3_PHY_91_DATA 0x10101010 +#define DDRSS3_PHY_92_DATA 0x00021010 +#define DDRSS3_PHY_93_DATA 0x00100010 +#define DDRSS3_PHY_94_DATA 0x00100010 +#define DDRSS3_PHY_95_DATA 0x00100010 +#define DDRSS3_PHY_96_DATA 0x00100010 +#define DDRSS3_PHY_97_DATA 0x00050010 +#define DDRSS3_PHY_98_DATA 0x51517041 +#define DDRSS3_PHY_99_DATA 0x31C06001 +#define DDRSS3_PHY_100_DATA 0x07AB01AB +#define DDRSS3_PHY_101_DATA 0x00C0C001 +#define DDRSS3_PHY_102_DATA 0x0E0D0101 +#define DDRSS3_PHY_103_DATA 0x10001000 +#define DDRSS3_PHY_104_DATA 0x0C083E42 +#define DDRSS3_PHY_105_DATA 0x0F0C3701 +#define DDRSS3_PHY_106_DATA 0x01000140 +#define DDRSS3_PHY_107_DATA 0x0C000420 +#define DDRSS3_PHY_108_DATA 0x00000198 +#define DDRSS3_PHY_109_DATA 0x0A0000D0 +#define DDRSS3_PHY_110_DATA 0x00030200 +#define DDRSS3_PHY_111_DATA 0x02800000 +#define DDRSS3_PHY_112_DATA 0x80800000 +#define DDRSS3_PHY_113_DATA 0x000E2010 +#define DDRSS3_PHY_114_DATA 0x76543210 +#define DDRSS3_PHY_115_DATA 0x00000008 +#define DDRSS3_PHY_116_DATA 0x02800280 +#define DDRSS3_PHY_117_DATA 0x02800280 +#define DDRSS3_PHY_118_DATA 0x02800280 +#define DDRSS3_PHY_119_DATA 0x02800280 +#define DDRSS3_PHY_120_DATA 0x00000280 +#define DDRSS3_PHY_121_DATA 0x0000A000 +#define DDRSS3_PHY_122_DATA 0x00A000A0 +#define DDRSS3_PHY_123_DATA 0x00A000A0 +#define DDRSS3_PHY_124_DATA 0x00A000A0 +#define DDRSS3_PHY_125_DATA 0x00A000A0 +#define DDRSS3_PHY_126_DATA 0x00A000A0 +#define DDRSS3_PHY_127_DATA 0x00A000A0 +#define DDRSS3_PHY_128_DATA 0x00A000A0 +#define DDRSS3_PHY_129_DATA 0x00A000A0 +#define DDRSS3_PHY_130_DATA 0x01C200A0 +#define DDRSS3_PHY_131_DATA 0x01A00005 +#define DDRSS3_PHY_132_DATA 0x00000000 +#define DDRSS3_PHY_133_DATA 0x00000000 +#define DDRSS3_PHY_134_DATA 0x00080200 +#define DDRSS3_PHY_135_DATA 0x00000000 +#define DDRSS3_PHY_136_DATA 0x20202000 +#define DDRSS3_PHY_137_DATA 0x20202020 +#define DDRSS3_PHY_138_DATA 0xF0F02020 +#define DDRSS3_PHY_139_DATA 0x00000000 +#define DDRSS3_PHY_140_DATA 0x00000000 +#define DDRSS3_PHY_141_DATA 0x00000000 +#define DDRSS3_PHY_142_DATA 0x00000000 +#define DDRSS3_PHY_143_DATA 0x00000000 +#define DDRSS3_PHY_144_DATA 0x00000000 +#define DDRSS3_PHY_145_DATA 0x00000000 +#define DDRSS3_PHY_146_DATA 0x00000000 +#define DDRSS3_PHY_147_DATA 0x00000000 +#define DDRSS3_PHY_148_DATA 0x00000000 +#define DDRSS3_PHY_149_DATA 0x00000000 +#define DDRSS3_PHY_150_DATA 0x00000000 +#define DDRSS3_PHY_151_DATA 0x00000000 +#define DDRSS3_PHY_152_DATA 0x00000000 +#define DDRSS3_PHY_153_DATA 0x00000000 +#define DDRSS3_PHY_154_DATA 0x00000000 +#define DDRSS3_PHY_155_DATA 0x00000000 +#define DDRSS3_PHY_156_DATA 0x00000000 +#define DDRSS3_PHY_157_DATA 0x00000000 +#define DDRSS3_PHY_158_DATA 0x00000000 +#define DDRSS3_PHY_159_DATA 0x00000000 +#define DDRSS3_PHY_160_DATA 0x00000000 +#define DDRSS3_PHY_161_DATA 0x00000000 +#define DDRSS3_PHY_162_DATA 0x00000000 +#define DDRSS3_PHY_163_DATA 0x00000000 +#define DDRSS3_PHY_164_DATA 0x00000000 +#define DDRSS3_PHY_165_DATA 0x00000000 +#define DDRSS3_PHY_166_DATA 0x00000000 +#define DDRSS3_PHY_167_DATA 0x00000000 +#define DDRSS3_PHY_168_DATA 0x00000000 +#define DDRSS3_PHY_169_DATA 0x00000000 +#define DDRSS3_PHY_170_DATA 0x00000000 +#define DDRSS3_PHY_171_DATA 0x00000000 +#define DDRSS3_PHY_172_DATA 0x00000000 +#define DDRSS3_PHY_173_DATA 0x00000000 +#define DDRSS3_PHY_174_DATA 0x00000000 +#define DDRSS3_PHY_175_DATA 0x00000000 +#define DDRSS3_PHY_176_DATA 0x00000000 +#define DDRSS3_PHY_177_DATA 0x00000000 +#define DDRSS3_PHY_178_DATA 0x00000000 +#define DDRSS3_PHY_179_DATA 0x00000000 +#define DDRSS3_PHY_180_DATA 0x00000000 +#define DDRSS3_PHY_181_DATA 0x00000000 +#define DDRSS3_PHY_182_DATA 0x00000000 +#define DDRSS3_PHY_183_DATA 0x00000000 +#define DDRSS3_PHY_184_DATA 0x00000000 +#define DDRSS3_PHY_185_DATA 0x00000000 +#define DDRSS3_PHY_186_DATA 0x00000000 +#define DDRSS3_PHY_187_DATA 0x00000000 +#define DDRSS3_PHY_188_DATA 0x00000000 +#define DDRSS3_PHY_189_DATA 0x00000000 +#define DDRSS3_PHY_190_DATA 0x00000000 +#define DDRSS3_PHY_191_DATA 0x00000000 +#define DDRSS3_PHY_192_DATA 0x00000000 +#define DDRSS3_PHY_193_DATA 0x00000000 +#define DDRSS3_PHY_194_DATA 0x00000000 +#define DDRSS3_PHY_195_DATA 0x00000000 +#define DDRSS3_PHY_196_DATA 0x00000000 +#define DDRSS3_PHY_197_DATA 0x00000000 +#define DDRSS3_PHY_198_DATA 0x00000000 +#define DDRSS3_PHY_199_DATA 0x00000000 +#define DDRSS3_PHY_200_DATA 0x00000000 +#define DDRSS3_PHY_201_DATA 0x00000000 +#define DDRSS3_PHY_202_DATA 0x00000000 +#define DDRSS3_PHY_203_DATA 0x00000000 +#define DDRSS3_PHY_204_DATA 0x00000000 +#define DDRSS3_PHY_205_DATA 0x00000000 +#define DDRSS3_PHY_206_DATA 0x00000000 +#define DDRSS3_PHY_207_DATA 0x00000000 +#define DDRSS3_PHY_208_DATA 0x00000000 +#define DDRSS3_PHY_209_DATA 0x00000000 +#define DDRSS3_PHY_210_DATA 0x00000000 +#define DDRSS3_PHY_211_DATA 0x00000000 +#define DDRSS3_PHY_212_DATA 0x00000000 +#define DDRSS3_PHY_213_DATA 0x00000000 +#define DDRSS3_PHY_214_DATA 0x00000000 +#define DDRSS3_PHY_215_DATA 0x00000000 +#define DDRSS3_PHY_216_DATA 0x00000000 +#define DDRSS3_PHY_217_DATA 0x00000000 +#define DDRSS3_PHY_218_DATA 0x00000000 +#define DDRSS3_PHY_219_DATA 0x00000000 +#define DDRSS3_PHY_220_DATA 0x00000000 +#define DDRSS3_PHY_221_DATA 0x00000000 +#define DDRSS3_PHY_222_DATA 0x00000000 +#define DDRSS3_PHY_223_DATA 0x00000000 +#define DDRSS3_PHY_224_DATA 0x00000000 +#define DDRSS3_PHY_225_DATA 0x00000000 +#define DDRSS3_PHY_226_DATA 0x00000000 +#define DDRSS3_PHY_227_DATA 0x00000000 +#define DDRSS3_PHY_228_DATA 0x00000000 +#define DDRSS3_PHY_229_DATA 0x00000000 +#define DDRSS3_PHY_230_DATA 0x00000000 +#define DDRSS3_PHY_231_DATA 0x00000000 +#define DDRSS3_PHY_232_DATA 0x00000000 +#define DDRSS3_PHY_233_DATA 0x00000000 +#define DDRSS3_PHY_234_DATA 0x00000000 +#define DDRSS3_PHY_235_DATA 0x00000000 +#define DDRSS3_PHY_236_DATA 0x00000000 +#define DDRSS3_PHY_237_DATA 0x00000000 +#define DDRSS3_PHY_238_DATA 0x00000000 +#define DDRSS3_PHY_239_DATA 0x00000000 +#define DDRSS3_PHY_240_DATA 0x00000000 +#define DDRSS3_PHY_241_DATA 0x00000000 +#define DDRSS3_PHY_242_DATA 0x00000000 +#define DDRSS3_PHY_243_DATA 0x00000000 +#define DDRSS3_PHY_244_DATA 0x00000000 +#define DDRSS3_PHY_245_DATA 0x00000000 +#define DDRSS3_PHY_246_DATA 0x00000000 +#define DDRSS3_PHY_247_DATA 0x00000000 +#define DDRSS3_PHY_248_DATA 0x00000000 +#define DDRSS3_PHY_249_DATA 0x00000000 +#define DDRSS3_PHY_250_DATA 0x00000000 +#define DDRSS3_PHY_251_DATA 0x00000000 +#define DDRSS3_PHY_252_DATA 0x00000000 +#define DDRSS3_PHY_253_DATA 0x00000000 +#define DDRSS3_PHY_254_DATA 0x00000000 +#define DDRSS3_PHY_255_DATA 0x00000000 +#define DDRSS3_PHY_256_DATA 0x000004F0 +#define DDRSS3_PHY_257_DATA 0x00000000 +#define DDRSS3_PHY_258_DATA 0x00030200 +#define DDRSS3_PHY_259_DATA 0x00000000 +#define DDRSS3_PHY_260_DATA 0x00000000 +#define DDRSS3_PHY_261_DATA 0x01030000 +#define DDRSS3_PHY_262_DATA 0x00010000 +#define DDRSS3_PHY_263_DATA 0x01030004 +#define DDRSS3_PHY_264_DATA 0x01000000 +#define DDRSS3_PHY_265_DATA 0x00000000 +#define DDRSS3_PHY_266_DATA 0x00000000 +#define DDRSS3_PHY_267_DATA 0x01000001 +#define DDRSS3_PHY_268_DATA 0x00000200 +#define DDRSS3_PHY_269_DATA 0x000800C0 +#define DDRSS3_PHY_270_DATA 0x060100CC +#define DDRSS3_PHY_271_DATA 0x00030066 +#define DDRSS3_PHY_272_DATA 0x00000000 +#define DDRSS3_PHY_273_DATA 0x00000301 +#define DDRSS3_PHY_274_DATA 0x0000AAAA +#define DDRSS3_PHY_275_DATA 0x00005555 +#define DDRSS3_PHY_276_DATA 0x0000B5B5 +#define DDRSS3_PHY_277_DATA 0x00004A4A +#define DDRSS3_PHY_278_DATA 0x00005656 +#define DDRSS3_PHY_279_DATA 0x0000A9A9 +#define DDRSS3_PHY_280_DATA 0x0000A9A9 +#define DDRSS3_PHY_281_DATA 0x0000B5B5 +#define DDRSS3_PHY_282_DATA 0x00000000 +#define DDRSS3_PHY_283_DATA 0x00000000 +#define DDRSS3_PHY_284_DATA 0x2A000000 +#define DDRSS3_PHY_285_DATA 0x00000808 +#define DDRSS3_PHY_286_DATA 0x0F000000 +#define DDRSS3_PHY_287_DATA 0x00000F08 +#define DDRSS3_PHY_288_DATA 0x10400000 +#define DDRSS3_PHY_289_DATA 0x0C002006 +#define DDRSS3_PHY_290_DATA 0x00000000 +#define DDRSS3_PHY_291_DATA 0x00000000 +#define DDRSS3_PHY_292_DATA 0x55555555 +#define DDRSS3_PHY_293_DATA 0xAAAAAAAA +#define DDRSS3_PHY_294_DATA 0x55555555 +#define DDRSS3_PHY_295_DATA 0xAAAAAAAA +#define DDRSS3_PHY_296_DATA 0x00005555 +#define DDRSS3_PHY_297_DATA 0x01000100 +#define DDRSS3_PHY_298_DATA 0x00800180 +#define DDRSS3_PHY_299_DATA 0x00000000 +#define DDRSS3_PHY_300_DATA 0x00000000 +#define DDRSS3_PHY_301_DATA 0x00000000 +#define DDRSS3_PHY_302_DATA 0x00000000 +#define DDRSS3_PHY_303_DATA 0x00000000 +#define DDRSS3_PHY_304_DATA 0x00000000 +#define DDRSS3_PHY_305_DATA 0x00000000 +#define DDRSS3_PHY_306_DATA 0x00000000 +#define DDRSS3_PHY_307_DATA 0x00000000 +#define DDRSS3_PHY_308_DATA 0x00000000 +#define DDRSS3_PHY_309_DATA 0x00000000 +#define DDRSS3_PHY_310_DATA 0x00000000 +#define DDRSS3_PHY_311_DATA 0x00000000 +#define DDRSS3_PHY_312_DATA 0x00000000 +#define DDRSS3_PHY_313_DATA 0x00000000 +#define DDRSS3_PHY_314_DATA 0x00000000 +#define DDRSS3_PHY_315_DATA 0x00000000 +#define DDRSS3_PHY_316_DATA 0x00000000 +#define DDRSS3_PHY_317_DATA 0x00000000 +#define DDRSS3_PHY_318_DATA 0x00000000 +#define DDRSS3_PHY_319_DATA 0x00000000 +#define DDRSS3_PHY_320_DATA 0x00000000 +#define DDRSS3_PHY_321_DATA 0x00000000 +#define DDRSS3_PHY_322_DATA 0x00000104 +#define DDRSS3_PHY_323_DATA 0x00000120 +#define DDRSS3_PHY_324_DATA 0x00000000 +#define DDRSS3_PHY_325_DATA 0x00000000 +#define DDRSS3_PHY_326_DATA 0x00000000 +#define DDRSS3_PHY_327_DATA 0x00000000 +#define DDRSS3_PHY_328_DATA 0x00000000 +#define DDRSS3_PHY_329_DATA 0x00000000 +#define DDRSS3_PHY_330_DATA 0x00000000 +#define DDRSS3_PHY_331_DATA 0x00000001 +#define DDRSS3_PHY_332_DATA 0x07FF0000 +#define DDRSS3_PHY_333_DATA 0x0080081F +#define DDRSS3_PHY_334_DATA 0x00081020 +#define DDRSS3_PHY_335_DATA 0x04010000 +#define DDRSS3_PHY_336_DATA 0x00000000 +#define DDRSS3_PHY_337_DATA 0x00000000 +#define DDRSS3_PHY_338_DATA 0x00000000 +#define DDRSS3_PHY_339_DATA 0x00000100 +#define DDRSS3_PHY_340_DATA 0x01CC0C01 +#define DDRSS3_PHY_341_DATA 0x1003CC0C +#define DDRSS3_PHY_342_DATA 0x20000140 +#define DDRSS3_PHY_343_DATA 0x07FF0200 +#define DDRSS3_PHY_344_DATA 0x0000DD01 +#define DDRSS3_PHY_345_DATA 0x10100303 +#define DDRSS3_PHY_346_DATA 0x10101010 +#define DDRSS3_PHY_347_DATA 0x10101010 +#define DDRSS3_PHY_348_DATA 0x00021010 +#define DDRSS3_PHY_349_DATA 0x00100010 +#define DDRSS3_PHY_350_DATA 0x00100010 +#define DDRSS3_PHY_351_DATA 0x00100010 +#define DDRSS3_PHY_352_DATA 0x00100010 +#define DDRSS3_PHY_353_DATA 0x00050010 +#define DDRSS3_PHY_354_DATA 0x51517041 +#define DDRSS3_PHY_355_DATA 0x31C06001 +#define DDRSS3_PHY_356_DATA 0x07AB01AB +#define DDRSS3_PHY_357_DATA 0x00C0C001 +#define DDRSS3_PHY_358_DATA 0x0E0D0101 +#define DDRSS3_PHY_359_DATA 0x10001000 +#define DDRSS3_PHY_360_DATA 0x0C083E42 +#define DDRSS3_PHY_361_DATA 0x0F0C3701 +#define DDRSS3_PHY_362_DATA 0x01000140 +#define DDRSS3_PHY_363_DATA 0x0C000420 +#define DDRSS3_PHY_364_DATA 0x00000198 +#define DDRSS3_PHY_365_DATA 0x0A0000D0 +#define DDRSS3_PHY_366_DATA 0x00030200 +#define DDRSS3_PHY_367_DATA 0x02800000 +#define DDRSS3_PHY_368_DATA 0x80800000 +#define DDRSS3_PHY_369_DATA 0x000E2010 +#define DDRSS3_PHY_370_DATA 0x76543210 +#define DDRSS3_PHY_371_DATA 0x00000008 +#define DDRSS3_PHY_372_DATA 0x02800280 +#define DDRSS3_PHY_373_DATA 0x02800280 +#define DDRSS3_PHY_374_DATA 0x02800280 +#define DDRSS3_PHY_375_DATA 0x02800280 +#define DDRSS3_PHY_376_DATA 0x00000280 +#define DDRSS3_PHY_377_DATA 0x0000A000 +#define DDRSS3_PHY_378_DATA 0x00A000A0 +#define DDRSS3_PHY_379_DATA 0x00A000A0 +#define DDRSS3_PHY_380_DATA 0x00A000A0 +#define DDRSS3_PHY_381_DATA 0x00A000A0 +#define DDRSS3_PHY_382_DATA 0x00A000A0 +#define DDRSS3_PHY_383_DATA 0x00A000A0 +#define DDRSS3_PHY_384_DATA 0x00A000A0 +#define DDRSS3_PHY_385_DATA 0x00A000A0 +#define DDRSS3_PHY_386_DATA 0x01C200A0 +#define DDRSS3_PHY_387_DATA 0x01A00005 +#define DDRSS3_PHY_388_DATA 0x00000000 +#define DDRSS3_PHY_389_DATA 0x00000000 +#define DDRSS3_PHY_390_DATA 0x00080200 +#define DDRSS3_PHY_391_DATA 0x00000000 +#define DDRSS3_PHY_392_DATA 0x20202000 +#define DDRSS3_PHY_393_DATA 0x20202020 +#define DDRSS3_PHY_394_DATA 0xF0F02020 +#define DDRSS3_PHY_395_DATA 0x00000000 +#define DDRSS3_PHY_396_DATA 0x00000000 +#define DDRSS3_PHY_397_DATA 0x00000000 +#define DDRSS3_PHY_398_DATA 0x00000000 +#define DDRSS3_PHY_399_DATA 0x00000000 +#define DDRSS3_PHY_400_DATA 0x00000000 +#define DDRSS3_PHY_401_DATA 0x00000000 +#define DDRSS3_PHY_402_DATA 0x00000000 +#define DDRSS3_PHY_403_DATA 0x00000000 +#define DDRSS3_PHY_404_DATA 0x00000000 +#define DDRSS3_PHY_405_DATA 0x00000000 +#define DDRSS3_PHY_406_DATA 0x00000000 +#define DDRSS3_PHY_407_DATA 0x00000000 +#define DDRSS3_PHY_408_DATA 0x00000000 +#define DDRSS3_PHY_409_DATA 0x00000000 +#define DDRSS3_PHY_410_DATA 0x00000000 +#define DDRSS3_PHY_411_DATA 0x00000000 +#define DDRSS3_PHY_412_DATA 0x00000000 +#define DDRSS3_PHY_413_DATA 0x00000000 +#define DDRSS3_PHY_414_DATA 0x00000000 +#define DDRSS3_PHY_415_DATA 0x00000000 +#define DDRSS3_PHY_416_DATA 0x00000000 +#define DDRSS3_PHY_417_DATA 0x00000000 +#define DDRSS3_PHY_418_DATA 0x00000000 +#define DDRSS3_PHY_419_DATA 0x00000000 +#define DDRSS3_PHY_420_DATA 0x00000000 +#define DDRSS3_PHY_421_DATA 0x00000000 +#define DDRSS3_PHY_422_DATA 0x00000000 +#define DDRSS3_PHY_423_DATA 0x00000000 +#define DDRSS3_PHY_424_DATA 0x00000000 +#define DDRSS3_PHY_425_DATA 0x00000000 +#define DDRSS3_PHY_426_DATA 0x00000000 +#define DDRSS3_PHY_427_DATA 0x00000000 +#define DDRSS3_PHY_428_DATA 0x00000000 +#define DDRSS3_PHY_429_DATA 0x00000000 +#define DDRSS3_PHY_430_DATA 0x00000000 +#define DDRSS3_PHY_431_DATA 0x00000000 +#define DDRSS3_PHY_432_DATA 0x00000000 +#define DDRSS3_PHY_433_DATA 0x00000000 +#define DDRSS3_PHY_434_DATA 0x00000000 +#define DDRSS3_PHY_435_DATA 0x00000000 +#define DDRSS3_PHY_436_DATA 0x00000000 +#define DDRSS3_PHY_437_DATA 0x00000000 +#define DDRSS3_PHY_438_DATA 0x00000000 +#define DDRSS3_PHY_439_DATA 0x00000000 +#define DDRSS3_PHY_440_DATA 0x00000000 +#define DDRSS3_PHY_441_DATA 0x00000000 +#define DDRSS3_PHY_442_DATA 0x00000000 +#define DDRSS3_PHY_443_DATA 0x00000000 +#define DDRSS3_PHY_444_DATA 0x00000000 +#define DDRSS3_PHY_445_DATA 0x00000000 +#define DDRSS3_PHY_446_DATA 0x00000000 +#define DDRSS3_PHY_447_DATA 0x00000000 +#define DDRSS3_PHY_448_DATA 0x00000000 +#define DDRSS3_PHY_449_DATA 0x00000000 +#define DDRSS3_PHY_450_DATA 0x00000000 +#define DDRSS3_PHY_451_DATA 0x00000000 +#define DDRSS3_PHY_452_DATA 0x00000000 +#define DDRSS3_PHY_453_DATA 0x00000000 +#define DDRSS3_PHY_454_DATA 0x00000000 +#define DDRSS3_PHY_455_DATA 0x00000000 +#define DDRSS3_PHY_456_DATA 0x00000000 +#define DDRSS3_PHY_457_DATA 0x00000000 +#define DDRSS3_PHY_458_DATA 0x00000000 +#define DDRSS3_PHY_459_DATA 0x00000000 +#define DDRSS3_PHY_460_DATA 0x00000000 +#define DDRSS3_PHY_461_DATA 0x00000000 +#define DDRSS3_PHY_462_DATA 0x00000000 +#define DDRSS3_PHY_463_DATA 0x00000000 +#define DDRSS3_PHY_464_DATA 0x00000000 +#define DDRSS3_PHY_465_DATA 0x00000000 +#define DDRSS3_PHY_466_DATA 0x00000000 +#define DDRSS3_PHY_467_DATA 0x00000000 +#define DDRSS3_PHY_468_DATA 0x00000000 +#define DDRSS3_PHY_469_DATA 0x00000000 +#define DDRSS3_PHY_470_DATA 0x00000000 +#define DDRSS3_PHY_471_DATA 0x00000000 +#define DDRSS3_PHY_472_DATA 0x00000000 +#define DDRSS3_PHY_473_DATA 0x00000000 +#define DDRSS3_PHY_474_DATA 0x00000000 +#define DDRSS3_PHY_475_DATA 0x00000000 +#define DDRSS3_PHY_476_DATA 0x00000000 +#define DDRSS3_PHY_477_DATA 0x00000000 +#define DDRSS3_PHY_478_DATA 0x00000000 +#define DDRSS3_PHY_479_DATA 0x00000000 +#define DDRSS3_PHY_480_DATA 0x00000000 +#define DDRSS3_PHY_481_DATA 0x00000000 +#define DDRSS3_PHY_482_DATA 0x00000000 +#define DDRSS3_PHY_483_DATA 0x00000000 +#define DDRSS3_PHY_484_DATA 0x00000000 +#define DDRSS3_PHY_485_DATA 0x00000000 +#define DDRSS3_PHY_486_DATA 0x00000000 +#define DDRSS3_PHY_487_DATA 0x00000000 +#define DDRSS3_PHY_488_DATA 0x00000000 +#define DDRSS3_PHY_489_DATA 0x00000000 +#define DDRSS3_PHY_490_DATA 0x00000000 +#define DDRSS3_PHY_491_DATA 0x00000000 +#define DDRSS3_PHY_492_DATA 0x00000000 +#define DDRSS3_PHY_493_DATA 0x00000000 +#define DDRSS3_PHY_494_DATA 0x00000000 +#define DDRSS3_PHY_495_DATA 0x00000000 +#define DDRSS3_PHY_496_DATA 0x00000000 +#define DDRSS3_PHY_497_DATA 0x00000000 +#define DDRSS3_PHY_498_DATA 0x00000000 +#define DDRSS3_PHY_499_DATA 0x00000000 +#define DDRSS3_PHY_500_DATA 0x00000000 +#define DDRSS3_PHY_501_DATA 0x00000000 +#define DDRSS3_PHY_502_DATA 0x00000000 +#define DDRSS3_PHY_503_DATA 0x00000000 +#define DDRSS3_PHY_504_DATA 0x00000000 +#define DDRSS3_PHY_505_DATA 0x00000000 +#define DDRSS3_PHY_506_DATA 0x00000000 +#define DDRSS3_PHY_507_DATA 0x00000000 +#define DDRSS3_PHY_508_DATA 0x00000000 +#define DDRSS3_PHY_509_DATA 0x00000000 +#define DDRSS3_PHY_510_DATA 0x00000000 +#define DDRSS3_PHY_511_DATA 0x00000000 +#define DDRSS3_PHY_512_DATA 0x000004F0 +#define DDRSS3_PHY_513_DATA 0x00000000 +#define DDRSS3_PHY_514_DATA 0x00030200 +#define DDRSS3_PHY_515_DATA 0x00000000 +#define DDRSS3_PHY_516_DATA 0x00000000 +#define DDRSS3_PHY_517_DATA 0x01030000 +#define DDRSS3_PHY_518_DATA 0x00010000 +#define DDRSS3_PHY_519_DATA 0x01030004 +#define DDRSS3_PHY_520_DATA 0x01000000 +#define DDRSS3_PHY_521_DATA 0x00000000 +#define DDRSS3_PHY_522_DATA 0x00000000 +#define DDRSS3_PHY_523_DATA 0x01000001 +#define DDRSS3_PHY_524_DATA 0x00000200 +#define DDRSS3_PHY_525_DATA 0x000800C0 +#define DDRSS3_PHY_526_DATA 0x060100CC +#define DDRSS3_PHY_527_DATA 0x00030066 +#define DDRSS3_PHY_528_DATA 0x00000000 +#define DDRSS3_PHY_529_DATA 0x00000301 +#define DDRSS3_PHY_530_DATA 0x0000AAAA +#define DDRSS3_PHY_531_DATA 0x00005555 +#define DDRSS3_PHY_532_DATA 0x0000B5B5 +#define DDRSS3_PHY_533_DATA 0x00004A4A +#define DDRSS3_PHY_534_DATA 0x00005656 +#define DDRSS3_PHY_535_DATA 0x0000A9A9 +#define DDRSS3_PHY_536_DATA 0x0000A9A9 +#define DDRSS3_PHY_537_DATA 0x0000B5B5 +#define DDRSS3_PHY_538_DATA 0x00000000 +#define DDRSS3_PHY_539_DATA 0x00000000 +#define DDRSS3_PHY_540_DATA 0x2A000000 +#define DDRSS3_PHY_541_DATA 0x00000808 +#define DDRSS3_PHY_542_DATA 0x0F000000 +#define DDRSS3_PHY_543_DATA 0x00000F08 +#define DDRSS3_PHY_544_DATA 0x10400000 +#define DDRSS3_PHY_545_DATA 0x0C002006 +#define DDRSS3_PHY_546_DATA 0x00000000 +#define DDRSS3_PHY_547_DATA 0x00000000 +#define DDRSS3_PHY_548_DATA 0x55555555 +#define DDRSS3_PHY_549_DATA 0xAAAAAAAA +#define DDRSS3_PHY_550_DATA 0x55555555 +#define DDRSS3_PHY_551_DATA 0xAAAAAAAA +#define DDRSS3_PHY_552_DATA 0x00005555 +#define DDRSS3_PHY_553_DATA 0x01000100 +#define DDRSS3_PHY_554_DATA 0x00800180 +#define DDRSS3_PHY_555_DATA 0x00000001 +#define DDRSS3_PHY_556_DATA 0x00000000 +#define DDRSS3_PHY_557_DATA 0x00000000 +#define DDRSS3_PHY_558_DATA 0x00000000 +#define DDRSS3_PHY_559_DATA 0x00000000 +#define DDRSS3_PHY_560_DATA 0x00000000 +#define DDRSS3_PHY_561_DATA 0x00000000 +#define DDRSS3_PHY_562_DATA 0x00000000 +#define DDRSS3_PHY_563_DATA 0x00000000 +#define DDRSS3_PHY_564_DATA 0x00000000 +#define DDRSS3_PHY_565_DATA 0x00000000 +#define DDRSS3_PHY_566_DATA 0x00000000 +#define DDRSS3_PHY_567_DATA 0x00000000 +#define DDRSS3_PHY_568_DATA 0x00000000 +#define DDRSS3_PHY_569_DATA 0x00000000 +#define DDRSS3_PHY_570_DATA 0x00000000 +#define DDRSS3_PHY_571_DATA 0x00000000 +#define DDRSS3_PHY_572_DATA 0x00000000 +#define DDRSS3_PHY_573_DATA 0x00000000 +#define DDRSS3_PHY_574_DATA 0x00000000 +#define DDRSS3_PHY_575_DATA 0x00000000 +#define DDRSS3_PHY_576_DATA 0x00000000 +#define DDRSS3_PHY_577_DATA 0x00000000 +#define DDRSS3_PHY_578_DATA 0x00000104 +#define DDRSS3_PHY_579_DATA 0x00000120 +#define DDRSS3_PHY_580_DATA 0x00000000 +#define DDRSS3_PHY_581_DATA 0x00000000 +#define DDRSS3_PHY_582_DATA 0x00000000 +#define DDRSS3_PHY_583_DATA 0x00000000 +#define DDRSS3_PHY_584_DATA 0x00000000 +#define DDRSS3_PHY_585_DATA 0x00000000 +#define DDRSS3_PHY_586_DATA 0x00000000 +#define DDRSS3_PHY_587_DATA 0x00000001 +#define DDRSS3_PHY_588_DATA 0x07FF0000 +#define DDRSS3_PHY_589_DATA 0x0080081F +#define DDRSS3_PHY_590_DATA 0x00081020 +#define DDRSS3_PHY_591_DATA 0x04010000 +#define DDRSS3_PHY_592_DATA 0x00000000 +#define DDRSS3_PHY_593_DATA 0x00000000 +#define DDRSS3_PHY_594_DATA 0x00000000 +#define DDRSS3_PHY_595_DATA 0x00000100 +#define DDRSS3_PHY_596_DATA 0x01CC0C01 +#define DDRSS3_PHY_597_DATA 0x1003CC0C +#define DDRSS3_PHY_598_DATA 0x20000140 +#define DDRSS3_PHY_599_DATA 0x07FF0200 +#define DDRSS3_PHY_600_DATA 0x0000DD01 +#define DDRSS3_PHY_601_DATA 0x10100303 +#define DDRSS3_PHY_602_DATA 0x10101010 +#define DDRSS3_PHY_603_DATA 0x10101010 +#define DDRSS3_PHY_604_DATA 0x00021010 +#define DDRSS3_PHY_605_DATA 0x00100010 +#define DDRSS3_PHY_606_DATA 0x00100010 +#define DDRSS3_PHY_607_DATA 0x00100010 +#define DDRSS3_PHY_608_DATA 0x00100010 +#define DDRSS3_PHY_609_DATA 0x00050010 +#define DDRSS3_PHY_610_DATA 0x51517041 +#define DDRSS3_PHY_611_DATA 0x31C06001 +#define DDRSS3_PHY_612_DATA 0x07AB01AB +#define DDRSS3_PHY_613_DATA 0x00C0C001 +#define DDRSS3_PHY_614_DATA 0x0E0D0101 +#define DDRSS3_PHY_615_DATA 0x10001000 +#define DDRSS3_PHY_616_DATA 0x0C083E42 +#define DDRSS3_PHY_617_DATA 0x0F0C3701 +#define DDRSS3_PHY_618_DATA 0x01000140 +#define DDRSS3_PHY_619_DATA 0x0C000420 +#define DDRSS3_PHY_620_DATA 0x00000198 +#define DDRSS3_PHY_621_DATA 0x0A0000D0 +#define DDRSS3_PHY_622_DATA 0x00030200 +#define DDRSS3_PHY_623_DATA 0x02800000 +#define DDRSS3_PHY_624_DATA 0x80800000 +#define DDRSS3_PHY_625_DATA 0x000E2010 +#define DDRSS3_PHY_626_DATA 0x76543210 +#define DDRSS3_PHY_627_DATA 0x00000008 +#define DDRSS3_PHY_628_DATA 0x02800280 +#define DDRSS3_PHY_629_DATA 0x02800280 +#define DDRSS3_PHY_630_DATA 0x02800280 +#define DDRSS3_PHY_631_DATA 0x02800280 +#define DDRSS3_PHY_632_DATA 0x00000280 +#define DDRSS3_PHY_633_DATA 0x0000A000 +#define DDRSS3_PHY_634_DATA 0x00A000A0 +#define DDRSS3_PHY_635_DATA 0x00A000A0 +#define DDRSS3_PHY_636_DATA 0x00A000A0 +#define DDRSS3_PHY_637_DATA 0x00A000A0 +#define DDRSS3_PHY_638_DATA 0x00A000A0 +#define DDRSS3_PHY_639_DATA 0x00A000A0 +#define DDRSS3_PHY_640_DATA 0x00A000A0 +#define DDRSS3_PHY_641_DATA 0x00A000A0 +#define DDRSS3_PHY_642_DATA 0x01C200A0 +#define DDRSS3_PHY_643_DATA 0x01A00005 +#define DDRSS3_PHY_644_DATA 0x00000000 +#define DDRSS3_PHY_645_DATA 0x00000000 +#define DDRSS3_PHY_646_DATA 0x00080200 +#define DDRSS3_PHY_647_DATA 0x00000000 +#define DDRSS3_PHY_648_DATA 0x20202000 +#define DDRSS3_PHY_649_DATA 0x20202020 +#define DDRSS3_PHY_650_DATA 0xF0F02020 +#define DDRSS3_PHY_651_DATA 0x00000000 +#define DDRSS3_PHY_652_DATA 0x00000000 +#define DDRSS3_PHY_653_DATA 0x00000000 +#define DDRSS3_PHY_654_DATA 0x00000000 +#define DDRSS3_PHY_655_DATA 0x00000000 +#define DDRSS3_PHY_656_DATA 0x00000000 +#define DDRSS3_PHY_657_DATA 0x00000000 +#define DDRSS3_PHY_658_DATA 0x00000000 +#define DDRSS3_PHY_659_DATA 0x00000000 +#define DDRSS3_PHY_660_DATA 0x00000000 +#define DDRSS3_PHY_661_DATA 0x00000000 +#define DDRSS3_PHY_662_DATA 0x00000000 +#define DDRSS3_PHY_663_DATA 0x00000000 +#define DDRSS3_PHY_664_DATA 0x00000000 +#define DDRSS3_PHY_665_DATA 0x00000000 +#define DDRSS3_PHY_666_DATA 0x00000000 +#define DDRSS3_PHY_667_DATA 0x00000000 +#define DDRSS3_PHY_668_DATA 0x00000000 +#define DDRSS3_PHY_669_DATA 0x00000000 +#define DDRSS3_PHY_670_DATA 0x00000000 +#define DDRSS3_PHY_671_DATA 0x00000000 +#define DDRSS3_PHY_672_DATA 0x00000000 +#define DDRSS3_PHY_673_DATA 0x00000000 +#define DDRSS3_PHY_674_DATA 0x00000000 +#define DDRSS3_PHY_675_DATA 0x00000000 +#define DDRSS3_PHY_676_DATA 0x00000000 +#define DDRSS3_PHY_677_DATA 0x00000000 +#define DDRSS3_PHY_678_DATA 0x00000000 +#define DDRSS3_PHY_679_DATA 0x00000000 +#define DDRSS3_PHY_680_DATA 0x00000000 +#define DDRSS3_PHY_681_DATA 0x00000000 +#define DDRSS3_PHY_682_DATA 0x00000000 +#define DDRSS3_PHY_683_DATA 0x00000000 +#define DDRSS3_PHY_684_DATA 0x00000000 +#define DDRSS3_PHY_685_DATA 0x00000000 +#define DDRSS3_PHY_686_DATA 0x00000000 +#define DDRSS3_PHY_687_DATA 0x00000000 +#define DDRSS3_PHY_688_DATA 0x00000000 +#define DDRSS3_PHY_689_DATA 0x00000000 +#define DDRSS3_PHY_690_DATA 0x00000000 +#define DDRSS3_PHY_691_DATA 0x00000000 +#define DDRSS3_PHY_692_DATA 0x00000000 +#define DDRSS3_PHY_693_DATA 0x00000000 +#define DDRSS3_PHY_694_DATA 0x00000000 +#define DDRSS3_PHY_695_DATA 0x00000000 +#define DDRSS3_PHY_696_DATA 0x00000000 +#define DDRSS3_PHY_697_DATA 0x00000000 +#define DDRSS3_PHY_698_DATA 0x00000000 +#define DDRSS3_PHY_699_DATA 0x00000000 +#define DDRSS3_PHY_700_DATA 0x00000000 +#define DDRSS3_PHY_701_DATA 0x00000000 +#define DDRSS3_PHY_702_DATA 0x00000000 +#define DDRSS3_PHY_703_DATA 0x00000000 +#define DDRSS3_PHY_704_DATA 0x00000000 +#define DDRSS3_PHY_705_DATA 0x00000000 +#define DDRSS3_PHY_706_DATA 0x00000000 +#define DDRSS3_PHY_707_DATA 0x00000000 +#define DDRSS3_PHY_708_DATA 0x00000000 +#define DDRSS3_PHY_709_DATA 0x00000000 +#define DDRSS3_PHY_710_DATA 0x00000000 +#define DDRSS3_PHY_711_DATA 0x00000000 +#define DDRSS3_PHY_712_DATA 0x00000000 +#define DDRSS3_PHY_713_DATA 0x00000000 +#define DDRSS3_PHY_714_DATA 0x00000000 +#define DDRSS3_PHY_715_DATA 0x00000000 +#define DDRSS3_PHY_716_DATA 0x00000000 +#define DDRSS3_PHY_717_DATA 0x00000000 +#define DDRSS3_PHY_718_DATA 0x00000000 +#define DDRSS3_PHY_719_DATA 0x00000000 +#define DDRSS3_PHY_720_DATA 0x00000000 +#define DDRSS3_PHY_721_DATA 0x00000000 +#define DDRSS3_PHY_722_DATA 0x00000000 +#define DDRSS3_PHY_723_DATA 0x00000000 +#define DDRSS3_PHY_724_DATA 0x00000000 +#define DDRSS3_PHY_725_DATA 0x00000000 +#define DDRSS3_PHY_726_DATA 0x00000000 +#define DDRSS3_PHY_727_DATA 0x00000000 +#define DDRSS3_PHY_728_DATA 0x00000000 +#define DDRSS3_PHY_729_DATA 0x00000000 +#define DDRSS3_PHY_730_DATA 0x00000000 +#define DDRSS3_PHY_731_DATA 0x00000000 +#define DDRSS3_PHY_732_DATA 0x00000000 +#define DDRSS3_PHY_733_DATA 0x00000000 +#define DDRSS3_PHY_734_DATA 0x00000000 +#define DDRSS3_PHY_735_DATA 0x00000000 +#define DDRSS3_PHY_736_DATA 0x00000000 +#define DDRSS3_PHY_737_DATA 0x00000000 +#define DDRSS3_PHY_738_DATA 0x00000000 +#define DDRSS3_PHY_739_DATA 0x00000000 +#define DDRSS3_PHY_740_DATA 0x00000000 +#define DDRSS3_PHY_741_DATA 0x00000000 +#define DDRSS3_PHY_742_DATA 0x00000000 +#define DDRSS3_PHY_743_DATA 0x00000000 +#define DDRSS3_PHY_744_DATA 0x00000000 +#define DDRSS3_PHY_745_DATA 0x00000000 +#define DDRSS3_PHY_746_DATA 0x00000000 +#define DDRSS3_PHY_747_DATA 0x00000000 +#define DDRSS3_PHY_748_DATA 0x00000000 +#define DDRSS3_PHY_749_DATA 0x00000000 +#define DDRSS3_PHY_750_DATA 0x00000000 +#define DDRSS3_PHY_751_DATA 0x00000000 +#define DDRSS3_PHY_752_DATA 0x00000000 +#define DDRSS3_PHY_753_DATA 0x00000000 +#define DDRSS3_PHY_754_DATA 0x00000000 +#define DDRSS3_PHY_755_DATA 0x00000000 +#define DDRSS3_PHY_756_DATA 0x00000000 +#define DDRSS3_PHY_757_DATA 0x00000000 +#define DDRSS3_PHY_758_DATA 0x00000000 +#define DDRSS3_PHY_759_DATA 0x00000000 +#define DDRSS3_PHY_760_DATA 0x00000000 +#define DDRSS3_PHY_761_DATA 0x00000000 +#define DDRSS3_PHY_762_DATA 0x00000000 +#define DDRSS3_PHY_763_DATA 0x00000000 +#define DDRSS3_PHY_764_DATA 0x00000000 +#define DDRSS3_PHY_765_DATA 0x00000000 +#define DDRSS3_PHY_766_DATA 0x00000000 +#define DDRSS3_PHY_767_DATA 0x00000000 +#define DDRSS3_PHY_768_DATA 0x000004F0 +#define DDRSS3_PHY_769_DATA 0x00000000 +#define DDRSS3_PHY_770_DATA 0x00030200 +#define DDRSS3_PHY_771_DATA 0x00000000 +#define DDRSS3_PHY_772_DATA 0x00000000 +#define DDRSS3_PHY_773_DATA 0x01030000 +#define DDRSS3_PHY_774_DATA 0x00010000 +#define DDRSS3_PHY_775_DATA 0x01030004 +#define DDRSS3_PHY_776_DATA 0x01000000 +#define DDRSS3_PHY_777_DATA 0x00000000 +#define DDRSS3_PHY_778_DATA 0x00000000 +#define DDRSS3_PHY_779_DATA 0x01000001 +#define DDRSS3_PHY_780_DATA 0x00000200 +#define DDRSS3_PHY_781_DATA 0x000800C0 +#define DDRSS3_PHY_782_DATA 0x060100CC +#define DDRSS3_PHY_783_DATA 0x00030066 +#define DDRSS3_PHY_784_DATA 0x00000000 +#define DDRSS3_PHY_785_DATA 0x00000301 +#define DDRSS3_PHY_786_DATA 0x0000AAAA +#define DDRSS3_PHY_787_DATA 0x00005555 +#define DDRSS3_PHY_788_DATA 0x0000B5B5 +#define DDRSS3_PHY_789_DATA 0x00004A4A +#define DDRSS3_PHY_790_DATA 0x00005656 +#define DDRSS3_PHY_791_DATA 0x0000A9A9 +#define DDRSS3_PHY_792_DATA 0x0000A9A9 +#define DDRSS3_PHY_793_DATA 0x0000B5B5 +#define DDRSS3_PHY_794_DATA 0x00000000 +#define DDRSS3_PHY_795_DATA 0x00000000 +#define DDRSS3_PHY_796_DATA 0x2A000000 +#define DDRSS3_PHY_797_DATA 0x00000808 +#define DDRSS3_PHY_798_DATA 0x0F000000 +#define DDRSS3_PHY_799_DATA 0x00000F08 +#define DDRSS3_PHY_800_DATA 0x10400000 +#define DDRSS3_PHY_801_DATA 0x0C002006 +#define DDRSS3_PHY_802_DATA 0x00000000 +#define DDRSS3_PHY_803_DATA 0x00000000 +#define DDRSS3_PHY_804_DATA 0x55555555 +#define DDRSS3_PHY_805_DATA 0xAAAAAAAA +#define DDRSS3_PHY_806_DATA 0x55555555 +#define DDRSS3_PHY_807_DATA 0xAAAAAAAA +#define DDRSS3_PHY_808_DATA 0x00005555 +#define DDRSS3_PHY_809_DATA 0x01000100 +#define DDRSS3_PHY_810_DATA 0x00800180 +#define DDRSS3_PHY_811_DATA 0x00000000 +#define DDRSS3_PHY_812_DATA 0x00000000 +#define DDRSS3_PHY_813_DATA 0x00000000 +#define DDRSS3_PHY_814_DATA 0x00000000 +#define DDRSS3_PHY_815_DATA 0x00000000 +#define DDRSS3_PHY_816_DATA 0x00000000 +#define DDRSS3_PHY_817_DATA 0x00000000 +#define DDRSS3_PHY_818_DATA 0x00000000 +#define DDRSS3_PHY_819_DATA 0x00000000 +#define DDRSS3_PHY_820_DATA 0x00000000 +#define DDRSS3_PHY_821_DATA 0x00000000 +#define DDRSS3_PHY_822_DATA 0x00000000 +#define DDRSS3_PHY_823_DATA 0x00000000 +#define DDRSS3_PHY_824_DATA 0x00000000 +#define DDRSS3_PHY_825_DATA 0x00000000 +#define DDRSS3_PHY_826_DATA 0x00000000 +#define DDRSS3_PHY_827_DATA 0x00000000 +#define DDRSS3_PHY_828_DATA 0x00000000 +#define DDRSS3_PHY_829_DATA 0x00000000 +#define DDRSS3_PHY_830_DATA 0x00000000 +#define DDRSS3_PHY_831_DATA 0x00000000 +#define DDRSS3_PHY_832_DATA 0x00000000 +#define DDRSS3_PHY_833_DATA 0x00000000 +#define DDRSS3_PHY_834_DATA 0x00000104 +#define DDRSS3_PHY_835_DATA 0x00000120 +#define DDRSS3_PHY_836_DATA 0x00000000 +#define DDRSS3_PHY_837_DATA 0x00000000 +#define DDRSS3_PHY_838_DATA 0x00000000 +#define DDRSS3_PHY_839_DATA 0x00000000 +#define DDRSS3_PHY_840_DATA 0x00000000 +#define DDRSS3_PHY_841_DATA 0x00000000 +#define DDRSS3_PHY_842_DATA 0x00000000 +#define DDRSS3_PHY_843_DATA 0x00000001 +#define DDRSS3_PHY_844_DATA 0x07FF0000 +#define DDRSS3_PHY_845_DATA 0x0080081F +#define DDRSS3_PHY_846_DATA 0x00081020 +#define DDRSS3_PHY_847_DATA 0x04010000 +#define DDRSS3_PHY_848_DATA 0x00000000 +#define DDRSS3_PHY_849_DATA 0x00000000 +#define DDRSS3_PHY_850_DATA 0x00000000 +#define DDRSS3_PHY_851_DATA 0x00000100 +#define DDRSS3_PHY_852_DATA 0x01CC0C01 +#define DDRSS3_PHY_853_DATA 0x1003CC0C +#define DDRSS3_PHY_854_DATA 0x20000140 +#define DDRSS3_PHY_855_DATA 0x07FF0200 +#define DDRSS3_PHY_856_DATA 0x0000DD01 +#define DDRSS3_PHY_857_DATA 0x10100303 +#define DDRSS3_PHY_858_DATA 0x10101010 +#define DDRSS3_PHY_859_DATA 0x10101010 +#define DDRSS3_PHY_860_DATA 0x00021010 +#define DDRSS3_PHY_861_DATA 0x00100010 +#define DDRSS3_PHY_862_DATA 0x00100010 +#define DDRSS3_PHY_863_DATA 0x00100010 +#define DDRSS3_PHY_864_DATA 0x00100010 +#define DDRSS3_PHY_865_DATA 0x00050010 +#define DDRSS3_PHY_866_DATA 0x51517041 +#define DDRSS3_PHY_867_DATA 0x31C06001 +#define DDRSS3_PHY_868_DATA 0x07AB01AB +#define DDRSS3_PHY_869_DATA 0x00C0C001 +#define DDRSS3_PHY_870_DATA 0x0E0D0101 +#define DDRSS3_PHY_871_DATA 0x10001000 +#define DDRSS3_PHY_872_DATA 0x0C083E42 +#define DDRSS3_PHY_873_DATA 0x0F0C3701 +#define DDRSS3_PHY_874_DATA 0x01000140 +#define DDRSS3_PHY_875_DATA 0x0C000420 +#define DDRSS3_PHY_876_DATA 0x00000198 +#define DDRSS3_PHY_877_DATA 0x0A0000D0 +#define DDRSS3_PHY_878_DATA 0x00030200 +#define DDRSS3_PHY_879_DATA 0x02800000 +#define DDRSS3_PHY_880_DATA 0x80800000 +#define DDRSS3_PHY_881_DATA 0x000E2010 +#define DDRSS3_PHY_882_DATA 0x76543210 +#define DDRSS3_PHY_883_DATA 0x00000008 +#define DDRSS3_PHY_884_DATA 0x02800280 +#define DDRSS3_PHY_885_DATA 0x02800280 +#define DDRSS3_PHY_886_DATA 0x02800280 +#define DDRSS3_PHY_887_DATA 0x02800280 +#define DDRSS3_PHY_888_DATA 0x00000280 +#define DDRSS3_PHY_889_DATA 0x0000A000 +#define DDRSS3_PHY_890_DATA 0x00A000A0 +#define DDRSS3_PHY_891_DATA 0x00A000A0 +#define DDRSS3_PHY_892_DATA 0x00A000A0 +#define DDRSS3_PHY_893_DATA 0x00A000A0 +#define DDRSS3_PHY_894_DATA 0x00A000A0 +#define DDRSS3_PHY_895_DATA 0x00A000A0 +#define DDRSS3_PHY_896_DATA 0x00A000A0 +#define DDRSS3_PHY_897_DATA 0x00A000A0 +#define DDRSS3_PHY_898_DATA 0x01C200A0 +#define DDRSS3_PHY_899_DATA 0x01A00005 +#define DDRSS3_PHY_900_DATA 0x00000000 +#define DDRSS3_PHY_901_DATA 0x00000000 +#define DDRSS3_PHY_902_DATA 0x00080200 +#define DDRSS3_PHY_903_DATA 0x00000000 +#define DDRSS3_PHY_904_DATA 0x20202000 +#define DDRSS3_PHY_905_DATA 0x20202020 +#define DDRSS3_PHY_906_DATA 0xF0F02020 +#define DDRSS3_PHY_907_DATA 0x00000000 +#define DDRSS3_PHY_908_DATA 0x00000000 +#define DDRSS3_PHY_909_DATA 0x00000000 +#define DDRSS3_PHY_910_DATA 0x00000000 +#define DDRSS3_PHY_911_DATA 0x00000000 +#define DDRSS3_PHY_912_DATA 0x00000000 +#define DDRSS3_PHY_913_DATA 0x00000000 +#define DDRSS3_PHY_914_DATA 0x00000000 +#define DDRSS3_PHY_915_DATA 0x00000000 +#define DDRSS3_PHY_916_DATA 0x00000000 +#define DDRSS3_PHY_917_DATA 0x00000000 +#define DDRSS3_PHY_918_DATA 0x00000000 +#define DDRSS3_PHY_919_DATA 0x00000000 +#define DDRSS3_PHY_920_DATA 0x00000000 +#define DDRSS3_PHY_921_DATA 0x00000000 +#define DDRSS3_PHY_922_DATA 0x00000000 +#define DDRSS3_PHY_923_DATA 0x00000000 +#define DDRSS3_PHY_924_DATA 0x00000000 +#define DDRSS3_PHY_925_DATA 0x00000000 +#define DDRSS3_PHY_926_DATA 0x00000000 +#define DDRSS3_PHY_927_DATA 0x00000000 +#define DDRSS3_PHY_928_DATA 0x00000000 +#define DDRSS3_PHY_929_DATA 0x00000000 +#define DDRSS3_PHY_930_DATA 0x00000000 +#define DDRSS3_PHY_931_DATA 0x00000000 +#define DDRSS3_PHY_932_DATA 0x00000000 +#define DDRSS3_PHY_933_DATA 0x00000000 +#define DDRSS3_PHY_934_DATA 0x00000000 +#define DDRSS3_PHY_935_DATA 0x00000000 +#define DDRSS3_PHY_936_DATA 0x00000000 +#define DDRSS3_PHY_937_DATA 0x00000000 +#define DDRSS3_PHY_938_DATA 0x00000000 +#define DDRSS3_PHY_939_DATA 0x00000000 +#define DDRSS3_PHY_940_DATA 0x00000000 +#define DDRSS3_PHY_941_DATA 0x00000000 +#define DDRSS3_PHY_942_DATA 0x00000000 +#define DDRSS3_PHY_943_DATA 0x00000000 +#define DDRSS3_PHY_944_DATA 0x00000000 +#define DDRSS3_PHY_945_DATA 0x00000000 +#define DDRSS3_PHY_946_DATA 0x00000000 +#define DDRSS3_PHY_947_DATA 0x00000000 +#define DDRSS3_PHY_948_DATA 0x00000000 +#define DDRSS3_PHY_949_DATA 0x00000000 +#define DDRSS3_PHY_950_DATA 0x00000000 +#define DDRSS3_PHY_951_DATA 0x00000000 +#define DDRSS3_PHY_952_DATA 0x00000000 +#define DDRSS3_PHY_953_DATA 0x00000000 +#define DDRSS3_PHY_954_DATA 0x00000000 +#define DDRSS3_PHY_955_DATA 0x00000000 +#define DDRSS3_PHY_956_DATA 0x00000000 +#define DDRSS3_PHY_957_DATA 0x00000000 +#define DDRSS3_PHY_958_DATA 0x00000000 +#define DDRSS3_PHY_959_DATA 0x00000000 +#define DDRSS3_PHY_960_DATA 0x00000000 +#define DDRSS3_PHY_961_DATA 0x00000000 +#define DDRSS3_PHY_962_DATA 0x00000000 +#define DDRSS3_PHY_963_DATA 0x00000000 +#define DDRSS3_PHY_964_DATA 0x00000000 +#define DDRSS3_PHY_965_DATA 0x00000000 +#define DDRSS3_PHY_966_DATA 0x00000000 +#define DDRSS3_PHY_967_DATA 0x00000000 +#define DDRSS3_PHY_968_DATA 0x00000000 +#define DDRSS3_PHY_969_DATA 0x00000000 +#define DDRSS3_PHY_970_DATA 0x00000000 +#define DDRSS3_PHY_971_DATA 0x00000000 +#define DDRSS3_PHY_972_DATA 0x00000000 +#define DDRSS3_PHY_973_DATA 0x00000000 +#define DDRSS3_PHY_974_DATA 0x00000000 +#define DDRSS3_PHY_975_DATA 0x00000000 +#define DDRSS3_PHY_976_DATA 0x00000000 +#define DDRSS3_PHY_977_DATA 0x00000000 +#define DDRSS3_PHY_978_DATA 0x00000000 +#define DDRSS3_PHY_979_DATA 0x00000000 +#define DDRSS3_PHY_980_DATA 0x00000000 +#define DDRSS3_PHY_981_DATA 0x00000000 +#define DDRSS3_PHY_982_DATA 0x00000000 +#define DDRSS3_PHY_983_DATA 0x00000000 +#define DDRSS3_PHY_984_DATA 0x00000000 +#define DDRSS3_PHY_985_DATA 0x00000000 +#define DDRSS3_PHY_986_DATA 0x00000000 +#define DDRSS3_PHY_987_DATA 0x00000000 +#define DDRSS3_PHY_988_DATA 0x00000000 +#define DDRSS3_PHY_989_DATA 0x00000000 +#define DDRSS3_PHY_990_DATA 0x00000000 +#define DDRSS3_PHY_991_DATA 0x00000000 +#define DDRSS3_PHY_992_DATA 0x00000000 +#define DDRSS3_PHY_993_DATA 0x00000000 +#define DDRSS3_PHY_994_DATA 0x00000000 +#define DDRSS3_PHY_995_DATA 0x00000000 +#define DDRSS3_PHY_996_DATA 0x00000000 +#define DDRSS3_PHY_997_DATA 0x00000000 +#define DDRSS3_PHY_998_DATA 0x00000000 +#define DDRSS3_PHY_999_DATA 0x00000000 +#define DDRSS3_PHY_1000_DATA 0x00000000 +#define DDRSS3_PHY_1001_DATA 0x00000000 +#define DDRSS3_PHY_1002_DATA 0x00000000 +#define DDRSS3_PHY_1003_DATA 0x00000000 +#define DDRSS3_PHY_1004_DATA 0x00000000 +#define DDRSS3_PHY_1005_DATA 0x00000000 +#define DDRSS3_PHY_1006_DATA 0x00000000 +#define DDRSS3_PHY_1007_DATA 0x00000000 +#define DDRSS3_PHY_1008_DATA 0x00000000 +#define DDRSS3_PHY_1009_DATA 0x00000000 +#define DDRSS3_PHY_1010_DATA 0x00000000 +#define DDRSS3_PHY_1011_DATA 0x00000000 +#define DDRSS3_PHY_1012_DATA 0x00000000 +#define DDRSS3_PHY_1013_DATA 0x00000000 +#define DDRSS3_PHY_1014_DATA 0x00000000 +#define DDRSS3_PHY_1015_DATA 0x00000000 +#define DDRSS3_PHY_1016_DATA 0x00000000 +#define DDRSS3_PHY_1017_DATA 0x00000000 +#define DDRSS3_PHY_1018_DATA 0x00000000 +#define DDRSS3_PHY_1019_DATA 0x00000000 +#define DDRSS3_PHY_1020_DATA 0x00000000 +#define DDRSS3_PHY_1021_DATA 0x00000000 +#define DDRSS3_PHY_1022_DATA 0x00000000 +#define DDRSS3_PHY_1023_DATA 0x00000000 +#define DDRSS3_PHY_1024_DATA 0x00000000 +#define DDRSS3_PHY_1025_DATA 0x00000000 +#define DDRSS3_PHY_1026_DATA 0x00000000 +#define DDRSS3_PHY_1027_DATA 0x00000000 +#define DDRSS3_PHY_1028_DATA 0x00000000 +#define DDRSS3_PHY_1029_DATA 0x00000100 +#define DDRSS3_PHY_1030_DATA 0x00000200 +#define DDRSS3_PHY_1031_DATA 0x00000000 +#define DDRSS3_PHY_1032_DATA 0x00000000 +#define DDRSS3_PHY_1033_DATA 0x00000000 +#define DDRSS3_PHY_1034_DATA 0x00000000 +#define DDRSS3_PHY_1035_DATA 0x00400000 +#define DDRSS3_PHY_1036_DATA 0x00000080 +#define DDRSS3_PHY_1037_DATA 0x00DCBA98 +#define DDRSS3_PHY_1038_DATA 0x03000000 +#define DDRSS3_PHY_1039_DATA 0x00200000 +#define DDRSS3_PHY_1040_DATA 0x00000000 +#define DDRSS3_PHY_1041_DATA 0x00000000 +#define DDRSS3_PHY_1042_DATA 0x00000000 +#define DDRSS3_PHY_1043_DATA 0x00000000 +#define DDRSS3_PHY_1044_DATA 0x00000000 +#define DDRSS3_PHY_1045_DATA 0x0000002A +#define DDRSS3_PHY_1046_DATA 0x00000015 +#define DDRSS3_PHY_1047_DATA 0x00000015 +#define DDRSS3_PHY_1048_DATA 0x0000002A +#define DDRSS3_PHY_1049_DATA 0x00000033 +#define DDRSS3_PHY_1050_DATA 0x0000000C +#define DDRSS3_PHY_1051_DATA 0x0000000C +#define DDRSS3_PHY_1052_DATA 0x00000033 +#define DDRSS3_PHY_1053_DATA 0x00543210 +#define DDRSS3_PHY_1054_DATA 0x003F0000 +#define DDRSS3_PHY_1055_DATA 0x000F3F3F +#define DDRSS3_PHY_1056_DATA 0x20202003 +#define DDRSS3_PHY_1057_DATA 0x00202020 +#define DDRSS3_PHY_1058_DATA 0x20008008 +#define DDRSS3_PHY_1059_DATA 0x00000810 +#define DDRSS3_PHY_1060_DATA 0x00000F00 +#define DDRSS3_PHY_1061_DATA 0x00000000 +#define DDRSS3_PHY_1062_DATA 0x00000000 +#define DDRSS3_PHY_1063_DATA 0x00000000 +#define DDRSS3_PHY_1064_DATA 0x000305CC +#define DDRSS3_PHY_1065_DATA 0x00030000 +#define DDRSS3_PHY_1066_DATA 0x00000300 +#define DDRSS3_PHY_1067_DATA 0x00000300 +#define DDRSS3_PHY_1068_DATA 0x00000300 +#define DDRSS3_PHY_1069_DATA 0x00000300 +#define DDRSS3_PHY_1070_DATA 0x00000300 +#define DDRSS3_PHY_1071_DATA 0x42080010 +#define DDRSS3_PHY_1072_DATA 0x0000803E +#define DDRSS3_PHY_1073_DATA 0x00000001 +#define DDRSS3_PHY_1074_DATA 0x01000102 +#define DDRSS3_PHY_1075_DATA 0x00008000 +#define DDRSS3_PHY_1076_DATA 0x00000000 +#define DDRSS3_PHY_1077_DATA 0x00000000 +#define DDRSS3_PHY_1078_DATA 0x00000000 +#define DDRSS3_PHY_1079_DATA 0x00000000 +#define DDRSS3_PHY_1080_DATA 0x00000000 +#define DDRSS3_PHY_1081_DATA 0x00000000 +#define DDRSS3_PHY_1082_DATA 0x00000000 +#define DDRSS3_PHY_1083_DATA 0x00000000 +#define DDRSS3_PHY_1084_DATA 0x00000000 +#define DDRSS3_PHY_1085_DATA 0x00000000 +#define DDRSS3_PHY_1086_DATA 0x00000000 +#define DDRSS3_PHY_1087_DATA 0x00000000 +#define DDRSS3_PHY_1088_DATA 0x00000000 +#define DDRSS3_PHY_1089_DATA 0x00000000 +#define DDRSS3_PHY_1090_DATA 0x00000000 +#define DDRSS3_PHY_1091_DATA 0x00000000 +#define DDRSS3_PHY_1092_DATA 0x00000000 +#define DDRSS3_PHY_1093_DATA 0x00000000 +#define DDRSS3_PHY_1094_DATA 0x00000000 +#define DDRSS3_PHY_1095_DATA 0x00000000 +#define DDRSS3_PHY_1096_DATA 0x00000000 +#define DDRSS3_PHY_1097_DATA 0x00000000 +#define DDRSS3_PHY_1098_DATA 0x00000000 +#define DDRSS3_PHY_1099_DATA 0x00000000 +#define DDRSS3_PHY_1100_DATA 0x00000000 +#define DDRSS3_PHY_1101_DATA 0x00000000 +#define DDRSS3_PHY_1102_DATA 0x00000000 +#define DDRSS3_PHY_1103_DATA 0x00000000 +#define DDRSS3_PHY_1104_DATA 0x00000000 +#define DDRSS3_PHY_1105_DATA 0x00000000 +#define DDRSS3_PHY_1106_DATA 0x00000000 +#define DDRSS3_PHY_1107_DATA 0x00000000 +#define DDRSS3_PHY_1108_DATA 0x00000000 +#define DDRSS3_PHY_1109_DATA 0x00000000 +#define DDRSS3_PHY_1110_DATA 0x00000000 +#define DDRSS3_PHY_1111_DATA 0x00000000 +#define DDRSS3_PHY_1112_DATA 0x00000000 +#define DDRSS3_PHY_1113_DATA 0x00000000 +#define DDRSS3_PHY_1114_DATA 0x00000000 +#define DDRSS3_PHY_1115_DATA 0x00000000 +#define DDRSS3_PHY_1116_DATA 0x00000000 +#define DDRSS3_PHY_1117_DATA 0x00000000 +#define DDRSS3_PHY_1118_DATA 0x00000000 +#define DDRSS3_PHY_1119_DATA 0x00000000 +#define DDRSS3_PHY_1120_DATA 0x00000000 +#define DDRSS3_PHY_1121_DATA 0x00000000 +#define DDRSS3_PHY_1122_DATA 0x00000000 +#define DDRSS3_PHY_1123_DATA 0x00000000 +#define DDRSS3_PHY_1124_DATA 0x00000000 +#define DDRSS3_PHY_1125_DATA 0x00000000 +#define DDRSS3_PHY_1126_DATA 0x00000000 +#define DDRSS3_PHY_1127_DATA 0x00000000 +#define DDRSS3_PHY_1128_DATA 0x00000000 +#define DDRSS3_PHY_1129_DATA 0x00000000 +#define DDRSS3_PHY_1130_DATA 0x00000000 +#define DDRSS3_PHY_1131_DATA 0x00000000 +#define DDRSS3_PHY_1132_DATA 0x00000000 +#define DDRSS3_PHY_1133_DATA 0x00000000 +#define DDRSS3_PHY_1134_DATA 0x00000000 +#define DDRSS3_PHY_1135_DATA 0x00000000 +#define DDRSS3_PHY_1136_DATA 0x00000000 +#define DDRSS3_PHY_1137_DATA 0x00000000 +#define DDRSS3_PHY_1138_DATA 0x00000000 +#define DDRSS3_PHY_1139_DATA 0x00000000 +#define DDRSS3_PHY_1140_DATA 0x00000000 +#define DDRSS3_PHY_1141_DATA 0x00000000 +#define DDRSS3_PHY_1142_DATA 0x00000000 +#define DDRSS3_PHY_1143_DATA 0x00000000 +#define DDRSS3_PHY_1144_DATA 0x00000000 +#define DDRSS3_PHY_1145_DATA 0x00000000 +#define DDRSS3_PHY_1146_DATA 0x00000000 +#define DDRSS3_PHY_1147_DATA 0x00000000 +#define DDRSS3_PHY_1148_DATA 0x00000000 +#define DDRSS3_PHY_1149_DATA 0x00000000 +#define DDRSS3_PHY_1150_DATA 0x00000000 +#define DDRSS3_PHY_1151_DATA 0x00000000 +#define DDRSS3_PHY_1152_DATA 0x00000000 +#define DDRSS3_PHY_1153_DATA 0x00000000 +#define DDRSS3_PHY_1154_DATA 0x00000000 +#define DDRSS3_PHY_1155_DATA 0x00000000 +#define DDRSS3_PHY_1156_DATA 0x00000000 +#define DDRSS3_PHY_1157_DATA 0x00000000 +#define DDRSS3_PHY_1158_DATA 0x00000000 +#define DDRSS3_PHY_1159_DATA 0x00000000 +#define DDRSS3_PHY_1160_DATA 0x00000000 +#define DDRSS3_PHY_1161_DATA 0x00000000 +#define DDRSS3_PHY_1162_DATA 0x00000000 +#define DDRSS3_PHY_1163_DATA 0x00000000 +#define DDRSS3_PHY_1164_DATA 0x00000000 +#define DDRSS3_PHY_1165_DATA 0x00000000 +#define DDRSS3_PHY_1166_DATA 0x00000000 +#define DDRSS3_PHY_1167_DATA 0x00000000 +#define DDRSS3_PHY_1168_DATA 0x00000000 +#define DDRSS3_PHY_1169_DATA 0x00000000 +#define DDRSS3_PHY_1170_DATA 0x00000000 +#define DDRSS3_PHY_1171_DATA 0x00000000 +#define DDRSS3_PHY_1172_DATA 0x00000000 +#define DDRSS3_PHY_1173_DATA 0x00000000 +#define DDRSS3_PHY_1174_DATA 0x00000000 +#define DDRSS3_PHY_1175_DATA 0x00000000 +#define DDRSS3_PHY_1176_DATA 0x00000000 +#define DDRSS3_PHY_1177_DATA 0x00000000 +#define DDRSS3_PHY_1178_DATA 0x00000000 +#define DDRSS3_PHY_1179_DATA 0x00000000 +#define DDRSS3_PHY_1180_DATA 0x00000000 +#define DDRSS3_PHY_1181_DATA 0x00000000 +#define DDRSS3_PHY_1182_DATA 0x00000000 +#define DDRSS3_PHY_1183_DATA 0x00000000 +#define DDRSS3_PHY_1184_DATA 0x00000000 +#define DDRSS3_PHY_1185_DATA 0x00000000 +#define DDRSS3_PHY_1186_DATA 0x00000000 +#define DDRSS3_PHY_1187_DATA 0x00000000 +#define DDRSS3_PHY_1188_DATA 0x00000000 +#define DDRSS3_PHY_1189_DATA 0x00000000 +#define DDRSS3_PHY_1190_DATA 0x00000000 +#define DDRSS3_PHY_1191_DATA 0x00000000 +#define DDRSS3_PHY_1192_DATA 0x00000000 +#define DDRSS3_PHY_1193_DATA 0x00000000 +#define DDRSS3_PHY_1194_DATA 0x00000000 +#define DDRSS3_PHY_1195_DATA 0x00000000 +#define DDRSS3_PHY_1196_DATA 0x00000000 +#define DDRSS3_PHY_1197_DATA 0x00000000 +#define DDRSS3_PHY_1198_DATA 0x00000000 +#define DDRSS3_PHY_1199_DATA 0x00000000 +#define DDRSS3_PHY_1200_DATA 0x00000000 +#define DDRSS3_PHY_1201_DATA 0x00000000 +#define DDRSS3_PHY_1202_DATA 0x00000000 +#define DDRSS3_PHY_1203_DATA 0x00000000 +#define DDRSS3_PHY_1204_DATA 0x00000000 +#define DDRSS3_PHY_1205_DATA 0x00000000 +#define DDRSS3_PHY_1206_DATA 0x00000000 +#define DDRSS3_PHY_1207_DATA 0x00000000 +#define DDRSS3_PHY_1208_DATA 0x00000000 +#define DDRSS3_PHY_1209_DATA 0x00000000 +#define DDRSS3_PHY_1210_DATA 0x00000000 +#define DDRSS3_PHY_1211_DATA 0x00000000 +#define DDRSS3_PHY_1212_DATA 0x00000000 +#define DDRSS3_PHY_1213_DATA 0x00000000 +#define DDRSS3_PHY_1214_DATA 0x00000000 +#define DDRSS3_PHY_1215_DATA 0x00000000 +#define DDRSS3_PHY_1216_DATA 0x00000000 +#define DDRSS3_PHY_1217_DATA 0x00000000 +#define DDRSS3_PHY_1218_DATA 0x00000000 +#define DDRSS3_PHY_1219_DATA 0x00000000 +#define DDRSS3_PHY_1220_DATA 0x00000000 +#define DDRSS3_PHY_1221_DATA 0x00000000 +#define DDRSS3_PHY_1222_DATA 0x00000000 +#define DDRSS3_PHY_1223_DATA 0x00000000 +#define DDRSS3_PHY_1224_DATA 0x00000000 +#define DDRSS3_PHY_1225_DATA 0x00000000 +#define DDRSS3_PHY_1226_DATA 0x00000000 +#define DDRSS3_PHY_1227_DATA 0x00000000 +#define DDRSS3_PHY_1228_DATA 0x00000000 +#define DDRSS3_PHY_1229_DATA 0x00000000 +#define DDRSS3_PHY_1230_DATA 0x00000000 +#define DDRSS3_PHY_1231_DATA 0x00000000 +#define DDRSS3_PHY_1232_DATA 0x00000000 +#define DDRSS3_PHY_1233_DATA 0x00000000 +#define DDRSS3_PHY_1234_DATA 0x00000000 +#define DDRSS3_PHY_1235_DATA 0x00000000 +#define DDRSS3_PHY_1236_DATA 0x00000000 +#define DDRSS3_PHY_1237_DATA 0x00000000 +#define DDRSS3_PHY_1238_DATA 0x00000000 +#define DDRSS3_PHY_1239_DATA 0x00000000 +#define DDRSS3_PHY_1240_DATA 0x00000000 +#define DDRSS3_PHY_1241_DATA 0x00000000 +#define DDRSS3_PHY_1242_DATA 0x00000000 +#define DDRSS3_PHY_1243_DATA 0x00000000 +#define DDRSS3_PHY_1244_DATA 0x00000000 +#define DDRSS3_PHY_1245_DATA 0x00000000 +#define DDRSS3_PHY_1246_DATA 0x00000000 +#define DDRSS3_PHY_1247_DATA 0x00000000 +#define DDRSS3_PHY_1248_DATA 0x00000000 +#define DDRSS3_PHY_1249_DATA 0x00000000 +#define DDRSS3_PHY_1250_DATA 0x00000000 +#define DDRSS3_PHY_1251_DATA 0x00000000 +#define DDRSS3_PHY_1252_DATA 0x00000000 +#define DDRSS3_PHY_1253_DATA 0x00000000 +#define DDRSS3_PHY_1254_DATA 0x00000000 +#define DDRSS3_PHY_1255_DATA 0x00000000 +#define DDRSS3_PHY_1256_DATA 0x00000000 +#define DDRSS3_PHY_1257_DATA 0x00000000 +#define DDRSS3_PHY_1258_DATA 0x00000000 +#define DDRSS3_PHY_1259_DATA 0x00000000 +#define DDRSS3_PHY_1260_DATA 0x00000000 +#define DDRSS3_PHY_1261_DATA 0x00000000 +#define DDRSS3_PHY_1262_DATA 0x00000000 +#define DDRSS3_PHY_1263_DATA 0x00000000 +#define DDRSS3_PHY_1264_DATA 0x00000000 +#define DDRSS3_PHY_1265_DATA 0x00000000 +#define DDRSS3_PHY_1266_DATA 0x00000000 +#define DDRSS3_PHY_1267_DATA 0x00000000 +#define DDRSS3_PHY_1268_DATA 0x00000000 +#define DDRSS3_PHY_1269_DATA 0x00000000 +#define DDRSS3_PHY_1270_DATA 0x00000000 +#define DDRSS3_PHY_1271_DATA 0x00000000 +#define DDRSS3_PHY_1272_DATA 0x00000000 +#define DDRSS3_PHY_1273_DATA 0x00000000 +#define DDRSS3_PHY_1274_DATA 0x00000000 +#define DDRSS3_PHY_1275_DATA 0x00000000 +#define DDRSS3_PHY_1276_DATA 0x00000000 +#define DDRSS3_PHY_1277_DATA 0x00000000 +#define DDRSS3_PHY_1278_DATA 0x00000000 +#define DDRSS3_PHY_1279_DATA 0x00000000 +#define DDRSS3_PHY_1280_DATA 0x00000000 +#define DDRSS3_PHY_1281_DATA 0x00010100 +#define DDRSS3_PHY_1282_DATA 0x00000000 +#define DDRSS3_PHY_1283_DATA 0x00000000 +#define DDRSS3_PHY_1284_DATA 0x00050000 +#define DDRSS3_PHY_1285_DATA 0x04000000 +#define DDRSS3_PHY_1286_DATA 0x00000055 +#define DDRSS3_PHY_1287_DATA 0x00000000 +#define DDRSS3_PHY_1288_DATA 0x00000000 +#define DDRSS3_PHY_1289_DATA 0x00000000 +#define DDRSS3_PHY_1290_DATA 0x00000000 +#define DDRSS3_PHY_1291_DATA 0x00002001 +#define DDRSS3_PHY_1292_DATA 0x0000400F +#define DDRSS3_PHY_1293_DATA 0x50020028 +#define DDRSS3_PHY_1294_DATA 0x01010000 +#define DDRSS3_PHY_1295_DATA 0x80080001 +#define DDRSS3_PHY_1296_DATA 0x10200000 +#define DDRSS3_PHY_1297_DATA 0x00000008 +#define DDRSS3_PHY_1298_DATA 0x00000000 +#define DDRSS3_PHY_1299_DATA 0x01090E00 +#define DDRSS3_PHY_1300_DATA 0x00040101 +#define DDRSS3_PHY_1301_DATA 0x0000010F +#define DDRSS3_PHY_1302_DATA 0x00000000 +#define DDRSS3_PHY_1303_DATA 0x00000064 +#define DDRSS3_PHY_1304_DATA 0x00000000 +#define DDRSS3_PHY_1305_DATA 0x01010000 +#define DDRSS3_PHY_1306_DATA 0x01080402 +#define DDRSS3_PHY_1307_DATA 0x01200F02 +#define DDRSS3_PHY_1308_DATA 0x00194280 +#define DDRSS3_PHY_1309_DATA 0x00000004 +#define DDRSS3_PHY_1310_DATA 0x00042000 +#define DDRSS3_PHY_1311_DATA 0x00000000 +#define DDRSS3_PHY_1312_DATA 0x00000000 +#define DDRSS3_PHY_1313_DATA 0x00000000 +#define DDRSS3_PHY_1314_DATA 0x00000000 +#define DDRSS3_PHY_1315_DATA 0x00000000 +#define DDRSS3_PHY_1316_DATA 0x00000000 +#define DDRSS3_PHY_1317_DATA 0x01000000 +#define DDRSS3_PHY_1318_DATA 0x00000705 +#define DDRSS3_PHY_1319_DATA 0x00000054 +#define DDRSS3_PHY_1320_DATA 0x00030820 +#define DDRSS3_PHY_1321_DATA 0x00010820 +#define DDRSS3_PHY_1322_DATA 0x00010820 +#define DDRSS3_PHY_1323_DATA 0x00010820 +#define DDRSS3_PHY_1324_DATA 0x00010820 +#define DDRSS3_PHY_1325_DATA 0x00010820 +#define DDRSS3_PHY_1326_DATA 0x00010820 +#define DDRSS3_PHY_1327_DATA 0x00010820 +#define DDRSS3_PHY_1328_DATA 0x00010820 +#define DDRSS3_PHY_1329_DATA 0x00000000 +#define DDRSS3_PHY_1330_DATA 0x00000074 +#define DDRSS3_PHY_1331_DATA 0x00000400 +#define DDRSS3_PHY_1332_DATA 0x00000108 +#define DDRSS3_PHY_1333_DATA 0x00000000 +#define DDRSS3_PHY_1334_DATA 0x00000000 +#define DDRSS3_PHY_1335_DATA 0x00000000 +#define DDRSS3_PHY_1336_DATA 0x00000000 +#define DDRSS3_PHY_1337_DATA 0x00000000 +#define DDRSS3_PHY_1338_DATA 0x03000000 +#define DDRSS3_PHY_1339_DATA 0x00000000 +#define DDRSS3_PHY_1340_DATA 0x00000000 +#define DDRSS3_PHY_1341_DATA 0x00000000 +#define DDRSS3_PHY_1342_DATA 0x04102006 +#define DDRSS3_PHY_1343_DATA 0x00041020 +#define DDRSS3_PHY_1344_DATA 0x01C98C98 +#define DDRSS3_PHY_1345_DATA 0x3F400000 +#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F +#define DDRSS3_PHY_1347_DATA 0x0000001F +#define DDRSS3_PHY_1348_DATA 0x00000000 +#define DDRSS3_PHY_1349_DATA 0x00000000 +#define DDRSS3_PHY_1350_DATA 0x00000000 +#define DDRSS3_PHY_1351_DATA 0x00010000 +#define DDRSS3_PHY_1352_DATA 0x00000000 +#define DDRSS3_PHY_1353_DATA 0x00000000 +#define DDRSS3_PHY_1354_DATA 0x00000000 +#define DDRSS3_PHY_1355_DATA 0x00000000 +#define DDRSS3_PHY_1356_DATA 0x76543210 +#define DDRSS3_PHY_1357_DATA 0x00010198 +#define DDRSS3_PHY_1358_DATA 0x00000000 +#define DDRSS3_PHY_1359_DATA 0x00000000 +#define DDRSS3_PHY_1360_DATA 0x00000000 +#define DDRSS3_PHY_1361_DATA 0x00040700 +#define DDRSS3_PHY_1362_DATA 0x00000000 +#define DDRSS3_PHY_1363_DATA 0x00000000 +#define DDRSS3_PHY_1364_DATA 0x00000000 +#define DDRSS3_PHY_1365_DATA 0x00000000 +#define DDRSS3_PHY_1366_DATA 0x00000000 +#define DDRSS3_PHY_1367_DATA 0x00000002 +#define DDRSS3_PHY_1368_DATA 0x00000000 +#define DDRSS3_PHY_1369_DATA 0x00000000 +#define DDRSS3_PHY_1370_DATA 0x00000000 +#define DDRSS3_PHY_1371_DATA 0x00000000 +#define DDRSS3_PHY_1372_DATA 0x00000000 +#define DDRSS3_PHY_1373_DATA 0x00000000 +#define DDRSS3_PHY_1374_DATA 0x00080000 +#define DDRSS3_PHY_1375_DATA 0x000007FF +#define DDRSS3_PHY_1376_DATA 0x00000000 +#define DDRSS3_PHY_1377_DATA 0x00000000 +#define DDRSS3_PHY_1378_DATA 0x00000000 +#define DDRSS3_PHY_1379_DATA 0x00000000 +#define DDRSS3_PHY_1380_DATA 0x00000000 +#define DDRSS3_PHY_1381_DATA 0x00000000 +#define DDRSS3_PHY_1382_DATA 0x000FFFFF +#define DDRSS3_PHY_1383_DATA 0x000FFFFF +#define DDRSS3_PHY_1384_DATA 0x0000FFFF +#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0 +#define DDRSS3_PHY_1386_DATA 0x030FFFFF +#define DDRSS3_PHY_1387_DATA 0x01FFFFFF +#define DDRSS3_PHY_1388_DATA 0x0000FFFF +#define DDRSS3_PHY_1389_DATA 0x00000000 +#define DDRSS3_PHY_1390_DATA 0x00000000 +#define DDRSS3_PHY_1391_DATA 0x00000000 +#define DDRSS3_PHY_1392_DATA 0x00000000 +#define DDRSS3_PHY_1393_DATA 0x0001F7C0 +#define DDRSS3_PHY_1394_DATA 0x00000003 +#define DDRSS3_PHY_1395_DATA 0x00000000 +#define DDRSS3_PHY_1396_DATA 0x00001142 +#define DDRSS3_PHY_1397_DATA 0x040207AB +#define DDRSS3_PHY_1398_DATA 0x01000080 +#define DDRSS3_PHY_1399_DATA 0x03900390 +#define DDRSS3_PHY_1400_DATA 0x03900390 +#define DDRSS3_PHY_1401_DATA 0x00000390 +#define DDRSS3_PHY_1402_DATA 0x00000390 +#define DDRSS3_PHY_1403_DATA 0x00000390 +#define DDRSS3_PHY_1404_DATA 0x00000390 +#define DDRSS3_PHY_1405_DATA 0x00000005 +#define DDRSS3_PHY_1406_DATA 0x01813FCC +#define DDRSS3_PHY_1407_DATA 0x000000CC +#define DDRSS3_PHY_1408_DATA 0x0C000DFF +#define DDRSS3_PHY_1409_DATA 0x30000DFF +#define DDRSS3_PHY_1410_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1411_DATA 0x000100F0 +#define DDRSS3_PHY_1412_DATA 0x780DFFCC +#define DDRSS3_PHY_1413_DATA 0x00007E31 +#define DDRSS3_PHY_1414_DATA 0x000CBF11 +#define DDRSS3_PHY_1415_DATA 0x01990010 +#define DDRSS3_PHY_1416_DATA 0x000CBF11 +#define DDRSS3_PHY_1417_DATA 0x01990010 +#define DDRSS3_PHY_1418_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1419_DATA 0x00EF00F0 +#define DDRSS3_PHY_1420_DATA 0x3F0DFF11 +#define DDRSS3_PHY_1421_DATA 0x01FF00F0 +#define DDRSS3_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts index e8362647c5d..036d3d9d250 100644 --- a/arch/arm/dts/k3-am69-r5-sk.dts +++ b/arch/arm/dts/k3-am69-r5-sk.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-am69-sk.dts" -#include "k3-j784s4-ddr-evm-lp4-4266.dtsi" +#include "k3-am69-ddr-sk-lp4-4266.dtsi" #include "k3-j784s4-ddr.dtsi" #include "k3-am69-sk-u-boot.dtsi" #include "k3-j784s4-r5.dtsi" diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi index f0683088cf6..810415494ce 100644 --- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi +++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi @@ -1,14 +1,22 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0 - * This file was generated on 06/01/2021 + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 13:11:41 GMT+0530 (India Standard Time) */ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 -#define DDRSS_PLL_FREQUENCY_1 666500000 -#define DDRSS_PLL_FREQUENCY_2 666500000 +#define DDRSS_PLL_FREQUENCY_1 800000000 +#define DDRSS_PLL_FREQUENCY_2 800000000 + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000000 +#define DDR_REG1_SIZE_LSB 0x80000000 + #define DDRSS_CTL_00_DATA 0x00000B00 #define DDRSS_CTL_01_DATA 0x00000000 @@ -21,16 +29,16 @@ #define DDRSS_CTL_08_DATA 0x0001ADAF #define DDRSS_CTL_09_DATA 0x00000005 #define DDRSS_CTL_10_DATA 0x0000006E -#define DDRSS_CTL_11_DATA 0x000411AB -#define DDRSS_CTL_12_DATA 0x0028B0AB +#define DDRSS_CTL_11_DATA 0x0004E200 +#define DDRSS_CTL_12_DATA 0x0030D400 #define DDRSS_CTL_13_DATA 0x00000005 -#define DDRSS_CTL_14_DATA 0x00000A6B -#define DDRSS_CTL_15_DATA 0x000411AB -#define DDRSS_CTL_16_DATA 0x0028B0AB +#define DDRSS_CTL_14_DATA 0x00000C80 +#define DDRSS_CTL_15_DATA 0x0004E200 +#define DDRSS_CTL_16_DATA 0x0030D400 #define DDRSS_CTL_17_DATA 0x00000005 -#define DDRSS_CTL_18_DATA 0x00000A6B +#define DDRSS_CTL_18_DATA 0x00000C80 #define DDRSS_CTL_19_DATA 0x01010000 -#define DDRSS_CTL_20_DATA 0x02011001 +#define DDRSS_CTL_20_DATA 0x01011001 #define DDRSS_CTL_21_DATA 0x02010000 #define DDRSS_CTL_22_DATA 0x00020100 #define DDRSS_CTL_23_DATA 0x0000000B @@ -38,66 +46,66 @@ #define DDRSS_CTL_25_DATA 0x00000000 #define DDRSS_CTL_26_DATA 0x00000000 #define DDRSS_CTL_27_DATA 0x03020200 -#define DDRSS_CTL_28_DATA 0x00003636 +#define DDRSS_CTL_28_DATA 0x00004040 #define DDRSS_CTL_29_DATA 0x00100000 #define DDRSS_CTL_30_DATA 0x00000000 #define DDRSS_CTL_31_DATA 0x00000000 #define DDRSS_CTL_32_DATA 0x00000000 #define DDRSS_CTL_33_DATA 0x00000000 #define DDRSS_CTL_34_DATA 0x040C0000 -#define DDRSS_CTL_35_DATA 0x0C300C30 +#define DDRSS_CTL_35_DATA 0x0E400E40 #define DDRSS_CTL_36_DATA 0x00050804 #define DDRSS_CTL_37_DATA 0x09040008 -#define DDRSS_CTL_38_DATA 0x0D000204 -#define DDRSS_CTL_39_DATA 0x113C0057 -#define DDRSS_CTL_40_DATA 0x0D00291B -#define DDRSS_CTL_41_DATA 0x113C0057 -#define DDRSS_CTL_42_DATA 0x2000291B +#define DDRSS_CTL_38_DATA 0x14000304 +#define DDRSS_CTL_39_DATA 0x15480068 +#define DDRSS_CTL_40_DATA 0x14004220 +#define DDRSS_CTL_41_DATA 0x15480068 +#define DDRSS_CTL_42_DATA 0x20004220 #define DDRSS_CTL_43_DATA 0x000A0A09 -#define DDRSS_CTL_44_DATA 0x0400078A -#define DDRSS_CTL_45_DATA 0x130E0B04 -#define DDRSS_CTL_46_DATA 0x0A00B6D0 -#define DDRSS_CTL_47_DATA 0x130E0B0A -#define DDRSS_CTL_48_DATA 0x0A00B6D0 -#define DDRSS_CTL_49_DATA 0x0203040A -#define DDRSS_CTL_50_DATA 0x1C040500 -#define DDRSS_CTL_51_DATA 0x081D1C1D +#define DDRSS_CTL_44_DATA 0x040003C5 +#define DDRSS_CTL_45_DATA 0x17100D04 +#define DDRSS_CTL_46_DATA 0x0C006DB0 +#define DDRSS_CTL_47_DATA 0x17100D0C +#define DDRSS_CTL_48_DATA 0x0C006DB0 +#define DDRSS_CTL_49_DATA 0x0203040C +#define DDRSS_CTL_50_DATA 0x21060500 +#define DDRSS_CTL_51_DATA 0x08222122 #define DDRSS_CTL_52_DATA 0x14000E0A -#define DDRSS_CTL_53_DATA 0x02010A0A -#define DDRSS_CTL_54_DATA 0x01010002 -#define DDRSS_CTL_55_DATA 0x04383808 -#define DDRSS_CTL_56_DATA 0x041F1F04 -#define DDRSS_CTL_57_DATA 0x00001F1F +#define DDRSS_CTL_53_DATA 0x03010A0A +#define DDRSS_CTL_54_DATA 0x01010003 +#define DDRSS_CTL_55_DATA 0x0442420A +#define DDRSS_CTL_56_DATA 0x04252504 +#define DDRSS_CTL_57_DATA 0x00002525 #define DDRSS_CTL_58_DATA 0x00010100 #define DDRSS_CTL_59_DATA 0x03010000 #define DDRSS_CTL_60_DATA 0x00001008 -#define DDRSS_CTL_61_DATA 0x000000CE -#define DDRSS_CTL_62_DATA 0x00000176 -#define DDRSS_CTL_63_DATA 0x00001448 -#define DDRSS_CTL_64_DATA 0x00000176 -#define DDRSS_CTL_65_DATA 0x00001448 +#define DDRSS_CTL_61_DATA 0x00000068 +#define DDRSS_CTL_62_DATA 0x000001C0 +#define DDRSS_CTL_63_DATA 0x00000C28 +#define DDRSS_CTL_64_DATA 0x000001C0 +#define DDRSS_CTL_65_DATA 0x00000C28 #define DDRSS_CTL_66_DATA 0x00000005 #define DDRSS_CTL_67_DATA 0x00040000 -#define DDRSS_CTL_68_DATA 0x005D0012 -#define DDRSS_CTL_69_DATA 0x005D0282 -#define DDRSS_CTL_70_DATA 0x00400282 +#define DDRSS_CTL_68_DATA 0x00700005 +#define DDRSS_CTL_69_DATA 0x0070017E +#define DDRSS_CTL_70_DATA 0x0040017E #define DDRSS_CTL_71_DATA 0x00120103 -#define DDRSS_CTL_72_DATA 0x000A0005 -#define DDRSS_CTL_73_DATA 0x1F08000A -#define DDRSS_CTL_74_DATA 0x0505011F +#define DDRSS_CTL_72_DATA 0x000C0005 +#define DDRSS_CTL_73_DATA 0x2408000C +#define DDRSS_CTL_74_DATA 0x05050124 #define DDRSS_CTL_75_DATA 0x0301030A -#define DDRSS_CTL_76_DATA 0x03130A07 -#define DDRSS_CTL_77_DATA 0x0A070301 -#define DDRSS_CTL_78_DATA 0x00010313 +#define DDRSS_CTL_76_DATA 0x03170C08 +#define DDRSS_CTL_77_DATA 0x0C080301 +#define DDRSS_CTL_78_DATA 0x00010317 #define DDRSS_CTL_79_DATA 0x00100010 -#define DDRSS_CTL_80_DATA 0x01800180 -#define DDRSS_CTL_81_DATA 0x01800180 +#define DDRSS_CTL_80_DATA 0x01CC01CC +#define DDRSS_CTL_81_DATA 0x01CC01CC #define DDRSS_CTL_82_DATA 0x03050505 #define DDRSS_CTL_83_DATA 0x03010303 -#define DDRSS_CTL_84_DATA 0x14070A07 -#define DDRSS_CTL_85_DATA 0x03030A03 -#define DDRSS_CTL_86_DATA 0x14070A07 -#define DDRSS_CTL_87_DATA 0x03030A03 +#define DDRSS_CTL_84_DATA 0x18080C08 +#define DDRSS_CTL_85_DATA 0x03030C03 +#define DDRSS_CTL_86_DATA 0x18080C08 +#define DDRSS_CTL_87_DATA 0x03030C03 #define DDRSS_CTL_88_DATA 0x03010000 #define DDRSS_CTL_89_DATA 0x00010000 #define DDRSS_CTL_90_DATA 0x00000000 @@ -112,27 +120,27 @@ #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x00040005 #define DDRSS_CTL_101_DATA 0x00000000 -#define DDRSS_CTL_102_DATA 0x00003380 -#define DDRSS_CTL_103_DATA 0x00003380 -#define DDRSS_CTL_104_DATA 0x00003380 -#define DDRSS_CTL_105_DATA 0x00003380 -#define DDRSS_CTL_106_DATA 0x00003380 +#define DDRSS_CTL_102_DATA 0x000018C0 +#define DDRSS_CTL_103_DATA 0x000018C0 +#define DDRSS_CTL_104_DATA 0x000018C0 +#define DDRSS_CTL_105_DATA 0x000018C0 +#define DDRSS_CTL_106_DATA 0x000018C0 #define DDRSS_CTL_107_DATA 0x00000000 -#define DDRSS_CTL_108_DATA 0x000005A2 -#define DDRSS_CTL_109_DATA 0x00051200 -#define DDRSS_CTL_110_DATA 0x00051200 -#define DDRSS_CTL_111_DATA 0x00051200 -#define DDRSS_CTL_112_DATA 0x00051200 -#define DDRSS_CTL_113_DATA 0x00051200 +#define DDRSS_CTL_108_DATA 0x000002B5 +#define DDRSS_CTL_109_DATA 0x00030A00 +#define DDRSS_CTL_110_DATA 0x00030A00 +#define DDRSS_CTL_111_DATA 0x00030A00 +#define DDRSS_CTL_112_DATA 0x00030A00 +#define DDRSS_CTL_113_DATA 0x00030A00 #define DDRSS_CTL_114_DATA 0x00000000 -#define DDRSS_CTL_115_DATA 0x00008DF8 -#define DDRSS_CTL_116_DATA 0x00051200 -#define DDRSS_CTL_117_DATA 0x00051200 -#define DDRSS_CTL_118_DATA 0x00051200 -#define DDRSS_CTL_119_DATA 0x00051200 -#define DDRSS_CTL_120_DATA 0x00051200 +#define DDRSS_CTL_115_DATA 0x00005518 +#define DDRSS_CTL_116_DATA 0x00030A00 +#define DDRSS_CTL_117_DATA 0x00030A00 +#define DDRSS_CTL_118_DATA 0x00030A00 +#define DDRSS_CTL_119_DATA 0x00030A00 +#define DDRSS_CTL_120_DATA 0x00030A00 #define DDRSS_CTL_121_DATA 0x00000000 -#define DDRSS_CTL_122_DATA 0x00008DF8 +#define DDRSS_CTL_122_DATA 0x00005518 #define DDRSS_CTL_123_DATA 0x00000000 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x00000000 @@ -141,8 +149,8 @@ #define DDRSS_CTL_128_DATA 0x00000000 #define DDRSS_CTL_129_DATA 0x00000000 #define DDRSS_CTL_130_DATA 0x00000000 -#define DDRSS_CTL_131_DATA 0x07030500 -#define DDRSS_CTL_132_DATA 0x00030703 +#define DDRSS_CTL_131_DATA 0x08030500 +#define DDRSS_CTL_132_DATA 0x00030803 #define DDRSS_CTL_133_DATA 0x0A090000 #define DDRSS_CTL_134_DATA 0x0A090701 #define DDRSS_CTL_135_DATA 0x0900000E @@ -177,31 +185,31 @@ #define DDRSS_CTL_164_DATA 0x000B0000 #define DDRSS_CTL_165_DATA 0x000E0006 #define DDRSS_CTL_166_DATA 0x000E0404 -#define DDRSS_CTL_167_DATA 0x0086010B -#define DDRSS_CTL_168_DATA 0x0A0A014E -#define DDRSS_CTL_169_DATA 0x010B014E -#define DDRSS_CTL_170_DATA 0x014E0086 -#define DDRSS_CTL_171_DATA 0x014E0A0A +#define DDRSS_CTL_167_DATA 0x00A00140 +#define DDRSS_CTL_168_DATA 0x0C0C0190 +#define DDRSS_CTL_169_DATA 0x01400190 +#define DDRSS_CTL_170_DATA 0x019000A0 +#define DDRSS_CTL_171_DATA 0x01900C0C #define DDRSS_CTL_172_DATA 0x00000000 #define DDRSS_CTL_173_DATA 0x00000000 #define DDRSS_CTL_174_DATA 0x00000000 -#define DDRSS_CTL_175_DATA 0x24C40084 -#define DDRSS_CTL_176_DATA 0x2B0024C4 -#define DDRSS_CTL_177_DATA 0x00002B2B +#define DDRSS_CTL_175_DATA 0x2DD40084 +#define DDRSS_CTL_176_DATA 0xEB002DD4 +#define DDRSS_CTL_177_DATA 0x0000EBEB #define DDRSS_CTL_178_DATA 0x36000000 #define DDRSS_CTL_179_DATA 0x27270036 #define DDRSS_CTL_180_DATA 0x0F0F0000 #define DDRSS_CTL_181_DATA 0x15000000 #define DDRSS_CTL_182_DATA 0x00841515 -#define DDRSS_CTL_183_DATA 0x24C424C4 -#define DDRSS_CTL_184_DATA 0x2B2B2B00 +#define DDRSS_CTL_183_DATA 0x2DD42DD4 +#define DDRSS_CTL_184_DATA 0xEBEBEB00 #define DDRSS_CTL_185_DATA 0x00000000 #define DDRSS_CTL_186_DATA 0x00363600 #define DDRSS_CTL_187_DATA 0x00002727 #define DDRSS_CTL_188_DATA 0x00000F0F #define DDRSS_CTL_189_DATA 0x15151500 #define DDRSS_CTL_190_DATA 0x00000020 -#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x01000000 #define DDRSS_CTL_192_DATA 0x00000001 #define DDRSS_CTL_193_DATA 0x00000000 #define DDRSS_CTL_194_DATA 0x01000000 @@ -239,17 +247,17 @@ #define DDRSS_CTL_226_DATA 0x00000000 #define DDRSS_CTL_227_DATA 0x15110000 #define DDRSS_CTL_228_DATA 0x00040C18 -#define DDRSS_CTL_229_DATA 0x00000000 -#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_229_DATA 0xF000C000 +#define DDRSS_CTL_230_DATA 0x0000F000 #define DDRSS_CTL_231_DATA 0x00000000 #define DDRSS_CTL_232_DATA 0x00000000 -#define DDRSS_CTL_233_DATA 0x00000000 -#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0xC0000000 +#define DDRSS_CTL_234_DATA 0xF000F000 #define DDRSS_CTL_235_DATA 0x00000000 #define DDRSS_CTL_236_DATA 0x00000000 #define DDRSS_CTL_237_DATA 0x00000000 -#define DDRSS_CTL_238_DATA 0x00000000 -#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0xF000C000 +#define DDRSS_CTL_239_DATA 0x0000F000 #define DDRSS_CTL_240_DATA 0x00000000 #define DDRSS_CTL_241_DATA 0x00000000 #define DDRSS_CTL_242_DATA 0x00030000 @@ -271,13 +279,13 @@ #define DDRSS_CTL_258_DATA 0x00370040 #define DDRSS_CTL_259_DATA 0x00020008 #define DDRSS_CTL_260_DATA 0x00400100 -#define DDRSS_CTL_261_DATA 0x00280536 +#define DDRSS_CTL_261_DATA 0x00300640 #define DDRSS_CTL_262_DATA 0x01000200 -#define DDRSS_CTL_263_DATA 0x05360040 -#define DDRSS_CTL_264_DATA 0x00000028 -#define DDRSS_CTL_265_DATA 0x00430003 -#define DDRSS_CTL_266_DATA 0x01000043 -#define DDRSS_CTL_267_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x06400040 +#define DDRSS_CTL_264_DATA 0x00000030 +#define DDRSS_CTL_265_DATA 0x00500003 +#define DDRSS_CTL_266_DATA 0x01000050 +#define DDRSS_CTL_267_DATA 0x03030303 #define DDRSS_CTL_268_DATA 0x01010000 #define DDRSS_CTL_269_DATA 0x00000202 #define DDRSS_CTL_270_DATA 0x00000FFF @@ -301,14 +309,14 @@ #define DDRSS_CTL_288_DATA 0x00000000 #define DDRSS_CTL_289_DATA 0x00000000 #define DDRSS_CTL_290_DATA 0x03030300 -#define DDRSS_CTL_291_DATA 0x00000001 +#define DDRSS_CTL_291_DATA 0x00010101 #define DDRSS_CTL_292_DATA 0x00000000 #define DDRSS_CTL_293_DATA 0x00000000 #define DDRSS_CTL_294_DATA 0x00000000 #define DDRSS_CTL_295_DATA 0x00000000 #define DDRSS_CTL_296_DATA 0x00000000 -#define DDRSS_CTL_297_DATA 0x00000000 -#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0xFFFFFFFF +#define DDRSS_CTL_298_DATA 0x00000FFF #define DDRSS_CTL_299_DATA 0x00000000 #define DDRSS_CTL_300_DATA 0x00000000 #define DDRSS_CTL_301_DATA 0x00000000 @@ -328,15 +336,15 @@ #define DDRSS_CTL_315_DATA 0x01000101 #define DDRSS_CTL_316_DATA 0x01010001 #define DDRSS_CTL_317_DATA 0x00010101 -#define DDRSS_CTL_318_DATA 0x05070703 -#define DDRSS_CTL_319_DATA 0x0A081414 -#define DDRSS_CTL_320_DATA 0x0009030A -#define DDRSS_CTL_321_DATA 0x080C030F -#define DDRSS_CTL_322_DATA 0x080C0306 -#define DDRSS_CTL_323_DATA 0x0C090006 -#define DDRSS_CTL_324_DATA 0x0100000C -#define DDRSS_CTL_325_DATA 0x05020501 -#define DDRSS_CTL_326_DATA 0x00000002 +#define DDRSS_CTL_318_DATA 0x05080803 +#define DDRSS_CTL_319_DATA 0x0C081C1C +#define DDRSS_CTL_320_DATA 0x0009030C +#define DDRSS_CTL_321_DATA 0x090B030F +#define DDRSS_CTL_322_DATA 0x090B0306 +#define DDRSS_CTL_323_DATA 0x0B090006 +#define DDRSS_CTL_324_DATA 0x0100000B +#define DDRSS_CTL_325_DATA 0x06030601 +#define DDRSS_CTL_326_DATA 0x00000003 #define DDRSS_CTL_327_DATA 0x00000000 #define DDRSS_CTL_328_DATA 0x00010000 #define DDRSS_CTL_329_DATA 0x00280D00 @@ -397,32 +405,32 @@ #define DDRSS_CTL_384_DATA 0x00000000 #define DDRSS_CTL_385_DATA 0x00000000 #define DDRSS_CTL_386_DATA 0x00000000 -#define DDRSS_CTL_387_DATA 0x2E2E1B00 +#define DDRSS_CTL_387_DATA 0x33331B00 #define DDRSS_CTL_388_DATA 0x000A0000 -#define DDRSS_CTL_389_DATA 0x0000019C +#define DDRSS_CTL_389_DATA 0x000000C6 #define DDRSS_CTL_390_DATA 0x00000200 #define DDRSS_CTL_391_DATA 0x00000200 #define DDRSS_CTL_392_DATA 0x00000200 #define DDRSS_CTL_393_DATA 0x00000200 -#define DDRSS_CTL_394_DATA 0x000004D4 -#define DDRSS_CTL_395_DATA 0x00001018 +#define DDRSS_CTL_394_DATA 0x00000270 +#define DDRSS_CTL_395_DATA 0x000007BC #define DDRSS_CTL_396_DATA 0x00000204 -#define DDRSS_CTL_397_DATA 0x00002890 +#define DDRSS_CTL_397_DATA 0x00001850 #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x00000200 #define DDRSS_CTL_400_DATA 0x00000200 #define DDRSS_CTL_401_DATA 0x00000200 -#define DDRSS_CTL_402_DATA 0x000079B0 -#define DDRSS_CTL_403_DATA 0x000195A0 -#define DDRSS_CTL_404_DATA 0x0000080E -#define DDRSS_CTL_405_DATA 0x00002890 +#define DDRSS_CTL_402_DATA 0x000048F0 +#define DDRSS_CTL_403_DATA 0x0000F320 +#define DDRSS_CTL_404_DATA 0x00000A14 +#define DDRSS_CTL_405_DATA 0x00001850 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x00000200 #define DDRSS_CTL_409_DATA 0x00000200 -#define DDRSS_CTL_410_DATA 0x000079B0 -#define DDRSS_CTL_411_DATA 0x000195A0 -#define DDRSS_CTL_412_DATA 0x0202080E +#define DDRSS_CTL_410_DATA 0x000048F0 +#define DDRSS_CTL_411_DATA 0x0000F320 +#define DDRSS_CTL_412_DATA 0x02020A14 #define DDRSS_CTL_413_DATA 0x03030202 #define DDRSS_CTL_414_DATA 0x00000022 #define DDRSS_CTL_415_DATA 0x00000000 @@ -433,13 +441,13 @@ #define DDRSS_CTL_420_DATA 0x00000000 #define DDRSS_CTL_421_DATA 0x00030000 #define DDRSS_CTL_422_DATA 0x0007001F -#define DDRSS_CTL_423_DATA 0x0013002B -#define DDRSS_CTL_424_DATA 0x0013002B +#define DDRSS_CTL_423_DATA 0x0016002E +#define DDRSS_CTL_424_DATA 0x0016002E #define DDRSS_CTL_425_DATA 0x00000000 #define DDRSS_CTL_426_DATA 0x00000000 #define DDRSS_CTL_427_DATA 0x02000000 #define DDRSS_CTL_428_DATA 0x01000404 -#define DDRSS_CTL_429_DATA 0x05120512 +#define DDRSS_CTL_429_DATA 0x071A071A #define DDRSS_CTL_430_DATA 0x00000105 #define DDRSS_CTL_431_DATA 0x00010101 #define DDRSS_CTL_432_DATA 0x00010101 @@ -448,8 +456,8 @@ #define DDRSS_CTL_435_DATA 0x02000201 #define DDRSS_CTL_436_DATA 0x02010000 #define DDRSS_CTL_437_DATA 0x00000200 -#define DDRSS_CTL_438_DATA 0x18060000 -#define DDRSS_CTL_439_DATA 0x00000118 +#define DDRSS_CTL_438_DATA 0x1E060000 +#define DDRSS_CTL_439_DATA 0x0000011E #define DDRSS_CTL_440_DATA 0xFFFFFFFF #define DDRSS_CTL_441_DATA 0xFFFFFFFF #define DDRSS_CTL_442_DATA 0x00000000 @@ -482,8 +490,8 @@ #define DDRSS_PI_09_DATA 0x00000000 #define DDRSS_PI_10_DATA 0x00000000 #define DDRSS_PI_11_DATA 0x00000000 -#define DDRSS_PI_12_DATA 0x00000007 -#define DDRSS_PI_13_DATA 0x00010002 +#define DDRSS_PI_12_DATA 0x00000003 +#define DDRSS_PI_13_DATA 0x00010001 #define DDRSS_PI_14_DATA 0x0800000F #define DDRSS_PI_15_DATA 0x00000103 #define DDRSS_PI_16_DATA 0x00000005 @@ -516,7 +524,7 @@ #define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x000F0F00 -#define DDRSS_PI_46_DATA 0x00000017 +#define DDRSS_PI_46_DATA 0x00000019 #define DDRSS_PI_47_DATA 0x000007D0 #define DDRSS_PI_48_DATA 0x00000300 #define DDRSS_PI_49_DATA 0x00000000 @@ -531,18 +539,18 @@ #define DDRSS_PI_58_DATA 0x00000000 #define DDRSS_PI_59_DATA 0x00000000 #define DDRSS_PI_60_DATA 0x0A0A140A -#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_61_DATA 0x10020201 #define DDRSS_PI_62_DATA 0x00020805 #define DDRSS_PI_63_DATA 0x01000404 #define DDRSS_PI_64_DATA 0x00000000 #define DDRSS_PI_65_DATA 0x00000000 -#define DDRSS_PI_66_DATA 0x00000100 -#define DDRSS_PI_67_DATA 0x0001010F +#define DDRSS_PI_66_DATA 0x01000100 +#define DDRSS_PI_67_DATA 0x0102020F #define DDRSS_PI_68_DATA 0x00340000 #define DDRSS_PI_69_DATA 0x00000000 #define DDRSS_PI_70_DATA 0x00000000 #define DDRSS_PI_71_DATA 0x0000FFFF -#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_72_DATA 0x01000000 #define DDRSS_PI_73_DATA 0x00080100 #define DDRSS_PI_74_DATA 0x02000200 #define DDRSS_PI_75_DATA 0x01000100 @@ -631,104 +639,104 @@ #define DDRSS_PI_158_DATA 0x00000000 #define DDRSS_PI_159_DATA 0x00000401 #define DDRSS_PI_160_DATA 0x00000000 -#define DDRSS_PI_161_DATA 0x00010000 -#define DDRSS_PI_162_DATA 0x00000000 -#define DDRSS_PI_163_DATA 0x1B1B0200 +#define DDRSS_PI_161_DATA 0x05010000 +#define DDRSS_PI_162_DATA 0x00000001 +#define DDRSS_PI_163_DATA 0x20200201 #define DDRSS_PI_164_DATA 0x00000034 -#define DDRSS_PI_165_DATA 0x00000051 -#define DDRSS_PI_166_DATA 0x00020051 +#define DDRSS_PI_165_DATA 0x0000005C +#define DDRSS_PI_166_DATA 0x0002005C #define DDRSS_PI_167_DATA 0x02000200 -#define DDRSS_PI_168_DATA 0x300C0C04 -#define DDRSS_PI_169_DATA 0x0010300C -#define DDRSS_PI_170_DATA 0x000000CE -#define DDRSS_PI_171_DATA 0x00000176 -#define DDRSS_PI_172_DATA 0x00001448 -#define DDRSS_PI_173_DATA 0x00000176 -#define DDRSS_PI_174_DATA 0x04001448 +#define DDRSS_PI_168_DATA 0x400E0C04 +#define DDRSS_PI_169_DATA 0x0010400E +#define DDRSS_PI_170_DATA 0x00000068 +#define DDRSS_PI_171_DATA 0x000001C0 +#define DDRSS_PI_172_DATA 0x00000C28 +#define DDRSS_PI_173_DATA 0x000001C0 +#define DDRSS_PI_174_DATA 0x04000C28 #define DDRSS_PI_175_DATA 0x01010404 -#define DDRSS_PI_176_DATA 0x00001501 +#define DDRSS_PI_176_DATA 0x00001500 #define DDRSS_PI_177_DATA 0x00150015 #define DDRSS_PI_178_DATA 0x01000100 #define DDRSS_PI_179_DATA 0x00000100 #define DDRSS_PI_180_DATA 0x00000000 #define DDRSS_PI_181_DATA 0x01010101 -#define DDRSS_PI_182_DATA 0x00000101 -#define DDRSS_PI_183_DATA 0x00000100 -#define DDRSS_PI_184_DATA 0x00000100 -#define DDRSS_PI_185_DATA 0x0E040100 -#define DDRSS_PI_186_DATA 0x0808020E +#define DDRSS_PI_182_DATA 0x00010000 +#define DDRSS_PI_183_DATA 0x00010100 +#define DDRSS_PI_184_DATA 0x00010100 +#define DDRSS_PI_185_DATA 0x14040100 +#define DDRSS_PI_186_DATA 0x0A0A0214 #define DDRSS_PI_187_DATA 0x00040402 #define DDRSS_PI_188_DATA 0x000D0035 -#define DDRSS_PI_189_DATA 0x00198041 -#define DDRSS_PI_190_DATA 0x00198041 -#define DDRSS_PI_191_DATA 0x01010101 -#define DDRSS_PI_192_DATA 0x0002000E -#define DDRSS_PI_193_DATA 0x0002014E -#define DDRSS_PI_194_DATA 0x0100014E +#define DDRSS_PI_189_DATA 0x001C0044 +#define DDRSS_PI_190_DATA 0x001C0044 +#define DDRSS_PI_191_DATA 0x01000101 +#define DDRSS_PI_192_DATA 0x0003000E +#define DDRSS_PI_193_DATA 0x00030190 +#define DDRSS_PI_194_DATA 0x01000190 #define DDRSS_PI_195_DATA 0x000F000F -#define DDRSS_PI_196_DATA 0x014F0100 -#define DDRSS_PI_197_DATA 0x0100014F -#define DDRSS_PI_198_DATA 0x014F014F -#define DDRSS_PI_199_DATA 0x32103200 -#define DDRSS_PI_200_DATA 0x01013210 +#define DDRSS_PI_196_DATA 0x01910100 +#define DDRSS_PI_197_DATA 0x01000191 +#define DDRSS_PI_198_DATA 0x01910191 +#define DDRSS_PI_199_DATA 0x2F1B3200 +#define DDRSS_PI_200_DATA 0x01012F1B #define DDRSS_PI_201_DATA 0x0A070601 -#define DDRSS_PI_202_DATA 0x140D080D -#define DDRSS_PI_203_DATA 0x140D0810 -#define DDRSS_PI_204_DATA 0x0000C010 +#define DDRSS_PI_202_DATA 0x180F090D +#define DDRSS_PI_203_DATA 0x180F0911 +#define DDRSS_PI_204_DATA 0x0000C011 #define DDRSS_PI_205_DATA 0x00C01000 #define DDRSS_PI_206_DATA 0x00C01000 #define DDRSS_PI_207_DATA 0x00021000 -#define DDRSS_PI_208_DATA 0x001C000E -#define DDRSS_PI_209_DATA 0x001C014E -#define DDRSS_PI_210_DATA 0x0011014E +#define DDRSS_PI_208_DATA 0x001E000E +#define DDRSS_PI_209_DATA 0x001E0190 +#define DDRSS_PI_210_DATA 0x00110190 #define DDRSS_PI_211_DATA 0x32000056 -#define DDRSS_PI_212_DATA 0x00000301 -#define DDRSS_PI_213_DATA 0x005A002A +#define DDRSS_PI_212_DATA 0x00000101 +#define DDRSS_PI_213_DATA 0x005E0030 #define DDRSS_PI_214_DATA 0x03013212 -#define DDRSS_PI_215_DATA 0x00002A00 -#define DDRSS_PI_216_DATA 0x3212005A -#define DDRSS_PI_217_DATA 0x09000301 -#define DDRSS_PI_218_DATA 0x04010504 -#define DDRSS_PI_219_DATA 0x040006C9 +#define DDRSS_PI_215_DATA 0x00003000 +#define DDRSS_PI_216_DATA 0x3212005E +#define DDRSS_PI_217_DATA 0x09000001 +#define DDRSS_PI_218_DATA 0x06010504 +#define DDRSS_PI_219_DATA 0x04000364 #define DDRSS_PI_220_DATA 0x0A032001 -#define DDRSS_PI_221_DATA 0x1C1F0B0A -#define DDRSS_PI_222_DATA 0x00001D12 -#define DDRSS_PI_223_DATA 0x3C00A488 -#define DDRSS_PI_224_DATA 0x13142005 -#define DDRSS_PI_225_DATA 0x1C1F0B0E -#define DDRSS_PI_226_DATA 0x00001D12 -#define DDRSS_PI_227_DATA 0x3C00A488 -#define DDRSS_PI_228_DATA 0x13142005 -#define DDRSS_PI_229_DATA 0x00019C0E -#define DDRSS_PI_230_DATA 0x00001018 -#define DDRSS_PI_231_DATA 0x00002890 -#define DDRSS_PI_232_DATA 0x000195A0 -#define DDRSS_PI_233_DATA 0x00002890 -#define DDRSS_PI_234_DATA 0x000195A0 -#define DDRSS_PI_235_DATA 0x01800010 -#define DDRSS_PI_236_DATA 0x03030180 +#define DDRSS_PI_221_DATA 0x21250D0A +#define DDRSS_PI_222_DATA 0x00002216 +#define DDRSS_PI_223_DATA 0x480062B8 +#define DDRSS_PI_224_DATA 0x17182006 +#define DDRSS_PI_225_DATA 0x21250D10 +#define DDRSS_PI_226_DATA 0x00002216 +#define DDRSS_PI_227_DATA 0x480062B8 +#define DDRSS_PI_228_DATA 0x17182006 +#define DDRSS_PI_229_DATA 0x0000C610 +#define DDRSS_PI_230_DATA 0x000007BC +#define DDRSS_PI_231_DATA 0x00001850 +#define DDRSS_PI_232_DATA 0x0000F320 +#define DDRSS_PI_233_DATA 0x00001850 +#define DDRSS_PI_234_DATA 0x0000F320 +#define DDRSS_PI_235_DATA 0x01CC0010 +#define DDRSS_PI_236_DATA 0x030301CC #define DDRSS_PI_237_DATA 0x002AF803 #define DDRSS_PI_238_DATA 0x0001ADAF #define DDRSS_PI_239_DATA 0x00000005 #define DDRSS_PI_240_DATA 0x0000006E #define DDRSS_PI_241_DATA 0x00000010 -#define DDRSS_PI_242_DATA 0x000411AB +#define DDRSS_PI_242_DATA 0x0004E200 #define DDRSS_PI_243_DATA 0x0001ADAF #define DDRSS_PI_244_DATA 0x00000005 -#define DDRSS_PI_245_DATA 0x00000A6B -#define DDRSS_PI_246_DATA 0x00000180 -#define DDRSS_PI_247_DATA 0x000411AB +#define DDRSS_PI_245_DATA 0x00000C80 +#define DDRSS_PI_246_DATA 0x000001CC +#define DDRSS_PI_247_DATA 0x0004E200 #define DDRSS_PI_248_DATA 0x0001ADAF #define DDRSS_PI_249_DATA 0x00000005 -#define DDRSS_PI_250_DATA 0x00000A6B -#define DDRSS_PI_251_DATA 0x01000180 +#define DDRSS_PI_250_DATA 0x00000C80 +#define DDRSS_PI_251_DATA 0x010001CC #define DDRSS_PI_252_DATA 0x00370040 #define DDRSS_PI_253_DATA 0x00010008 -#define DDRSS_PI_254_DATA 0x05360040 -#define DDRSS_PI_255_DATA 0x00010028 -#define DDRSS_PI_256_DATA 0x05360040 -#define DDRSS_PI_257_DATA 0x00000328 -#define DDRSS_PI_258_DATA 0x00430043 +#define DDRSS_PI_254_DATA 0x06400040 +#define DDRSS_PI_255_DATA 0x00010030 +#define DDRSS_PI_256_DATA 0x06400040 +#define DDRSS_PI_257_DATA 0x00000330 +#define DDRSS_PI_258_DATA 0x00500050 #define DDRSS_PI_259_DATA 0x08040404 #define DDRSS_PI_260_DATA 0x00000055 #define DDRSS_PI_261_DATA 0x55083C5A @@ -745,29 +753,29 @@ #define DDRSS_PI_272_DATA 0x00080804 #define DDRSS_PI_273_DATA 0x00000000 #define DDRSS_PI_274_DATA 0x00000000 -#define DDRSS_PI_275_DATA 0x002B0084 +#define DDRSS_PI_275_DATA 0x00EB0084 #define DDRSS_PI_276_DATA 0x00150000 -#define DDRSS_PI_277_DATA 0x362B24C4 +#define DDRSS_PI_277_DATA 0x36EB2DD4 #define DDRSS_PI_278_DATA 0x00150F27 -#define DDRSS_PI_279_DATA 0x362B24C4 +#define DDRSS_PI_279_DATA 0x36EB2DD4 #define DDRSS_PI_280_DATA 0x00150F27 -#define DDRSS_PI_281_DATA 0x002B0084 +#define DDRSS_PI_281_DATA 0x00EB0084 #define DDRSS_PI_282_DATA 0x00150000 -#define DDRSS_PI_283_DATA 0x362B24C4 +#define DDRSS_PI_283_DATA 0x36EB2DD4 #define DDRSS_PI_284_DATA 0x00150F27 -#define DDRSS_PI_285_DATA 0x362B24C4 +#define DDRSS_PI_285_DATA 0x36EB2DD4 #define DDRSS_PI_286_DATA 0x00150F27 -#define DDRSS_PI_287_DATA 0x002B0084 +#define DDRSS_PI_287_DATA 0x00EB0084 #define DDRSS_PI_288_DATA 0x00150000 -#define DDRSS_PI_289_DATA 0x362B24C4 +#define DDRSS_PI_289_DATA 0x36EB2DD4 #define DDRSS_PI_290_DATA 0x00150F27 -#define DDRSS_PI_291_DATA 0x362B24C4 +#define DDRSS_PI_291_DATA 0x36EB2DD4 #define DDRSS_PI_292_DATA 0x00150F27 -#define DDRSS_PI_293_DATA 0x002B0084 +#define DDRSS_PI_293_DATA 0x00EB0084 #define DDRSS_PI_294_DATA 0x00150000 -#define DDRSS_PI_295_DATA 0x362B24C4 +#define DDRSS_PI_295_DATA 0x36EB2DD4 #define DDRSS_PI_296_DATA 0x00150F27 -#define DDRSS_PI_297_DATA 0x362B24C4 +#define DDRSS_PI_297_DATA 0x36EB2DD4 #define DDRSS_PI_298_DATA 0x00150F27 #define DDRSS_PI_299_DATA 0x00000000 @@ -783,7 +791,7 @@ #define DDRSS_PHY_09_DATA 0x00000000 #define DDRSS_PHY_10_DATA 0x00000000 #define DDRSS_PHY_11_DATA 0x01000001 -#define DDRSS_PHY_12_DATA 0x00000100 +#define DDRSS_PHY_12_DATA 0x00000200 #define DDRSS_PHY_13_DATA 0x000800C0 #define DDRSS_PHY_14_DATA 0x060100CC #define DDRSS_PHY_15_DATA 0x00030066 @@ -802,9 +810,9 @@ #define DDRSS_PHY_28_DATA 0x2A000000 #define DDRSS_PHY_29_DATA 0x00000808 #define DDRSS_PHY_30_DATA 0x0F000000 -#define DDRSS_PHY_31_DATA 0x00000F0F -#define DDRSS_PHY_32_DATA 0x10200000 -#define DDRSS_PHY_33_DATA 0x0C002007 +#define DDRSS_PHY_31_DATA 0x00000F08 +#define DDRSS_PHY_32_DATA 0x10400000 +#define DDRSS_PHY_33_DATA 0x0C002006 #define DDRSS_PHY_34_DATA 0x00000000 #define DDRSS_PHY_35_DATA 0x00000000 #define DDRSS_PHY_36_DATA 0x55555555 @@ -871,20 +879,20 @@ #define DDRSS_PHY_97_DATA 0x00050010 #define DDRSS_PHY_98_DATA 0x51517041 #define DDRSS_PHY_99_DATA 0x31C06000 -#define DDRSS_PHY_100_DATA 0x07AB0340 +#define DDRSS_PHY_100_DATA 0x07AB01AB #define DDRSS_PHY_101_DATA 0x00C0C001 -#define DDRSS_PHY_102_DATA 0x09080001 +#define DDRSS_PHY_102_DATA 0x0B0A0101 #define DDRSS_PHY_103_DATA 0x10001000 -#define DDRSS_PHY_104_DATA 0x0C063E42 -#define DDRSS_PHY_105_DATA 0x0F0C2701 +#define DDRSS_PHY_104_DATA 0x0C073E42 +#define DDRSS_PHY_105_DATA 0x0F0C2D01 #define DDRSS_PHY_106_DATA 0x01000140 -#define DDRSS_PHY_107_DATA 0x04000420 +#define DDRSS_PHY_107_DATA 0x0C000420 #define DDRSS_PHY_108_DATA 0x00000198 #define DDRSS_PHY_109_DATA 0x0A0000D0 #define DDRSS_PHY_110_DATA 0x00030200 #define DDRSS_PHY_111_DATA 0x02800000 #define DDRSS_PHY_112_DATA 0x80800000 -#define DDRSS_PHY_113_DATA 0x00092010 +#define DDRSS_PHY_113_DATA 0x000B2010 #define DDRSS_PHY_114_DATA 0x76543210 #define DDRSS_PHY_115_DATA 0x00000008 #define DDRSS_PHY_116_DATA 0x02800280 @@ -901,8 +909,8 @@ #define DDRSS_PHY_127_DATA 0x00A000A0 #define DDRSS_PHY_128_DATA 0x00A000A0 #define DDRSS_PHY_129_DATA 0x00A000A0 -#define DDRSS_PHY_130_DATA 0x01C400A0 -#define DDRSS_PHY_131_DATA 0x01A00003 +#define DDRSS_PHY_130_DATA 0x011900A0 +#define DDRSS_PHY_131_DATA 0x01A00004 #define DDRSS_PHY_132_DATA 0x00000000 #define DDRSS_PHY_133_DATA 0x00000000 #define DDRSS_PHY_134_DATA 0x00080200 @@ -1039,7 +1047,7 @@ #define DDRSS_PHY_265_DATA 0x00000000 #define DDRSS_PHY_266_DATA 0x00000000 #define DDRSS_PHY_267_DATA 0x01000001 -#define DDRSS_PHY_268_DATA 0x00000100 +#define DDRSS_PHY_268_DATA 0x00000200 #define DDRSS_PHY_269_DATA 0x000800C0 #define DDRSS_PHY_270_DATA 0x060100CC #define DDRSS_PHY_271_DATA 0x00030066 @@ -1058,9 +1066,9 @@ #define DDRSS_PHY_284_DATA 0x2A000000 #define DDRSS_PHY_285_DATA 0x00000808 #define DDRSS_PHY_286_DATA 0x0F000000 -#define DDRSS_PHY_287_DATA 0x00000F0F -#define DDRSS_PHY_288_DATA 0x10200000 -#define DDRSS_PHY_289_DATA 0x0C002007 +#define DDRSS_PHY_287_DATA 0x00000F08 +#define DDRSS_PHY_288_DATA 0x10400000 +#define DDRSS_PHY_289_DATA 0x0C002006 #define DDRSS_PHY_290_DATA 0x00000000 #define DDRSS_PHY_291_DATA 0x00000000 #define DDRSS_PHY_292_DATA 0x55555555 @@ -1127,20 +1135,20 @@ #define DDRSS_PHY_353_DATA 0x00050010 #define DDRSS_PHY_354_DATA 0x51517041 #define DDRSS_PHY_355_DATA 0x31C06000 -#define DDRSS_PHY_356_DATA 0x07AB0340 +#define DDRSS_PHY_356_DATA 0x07AB01AB #define DDRSS_PHY_357_DATA 0x00C0C001 -#define DDRSS_PHY_358_DATA 0x09080001 +#define DDRSS_PHY_358_DATA 0x0B0A0101 #define DDRSS_PHY_359_DATA 0x10001000 -#define DDRSS_PHY_360_DATA 0x0C063E42 -#define DDRSS_PHY_361_DATA 0x0F0C2701 +#define DDRSS_PHY_360_DATA 0x0C073E42 +#define DDRSS_PHY_361_DATA 0x0F0C2D01 #define DDRSS_PHY_362_DATA 0x01000140 -#define DDRSS_PHY_363_DATA 0x04000420 +#define DDRSS_PHY_363_DATA 0x0C000420 #define DDRSS_PHY_364_DATA 0x00000198 #define DDRSS_PHY_365_DATA 0x0A0000D0 #define DDRSS_PHY_366_DATA 0x00030200 #define DDRSS_PHY_367_DATA 0x02800000 #define DDRSS_PHY_368_DATA 0x80800000 -#define DDRSS_PHY_369_DATA 0x00092010 +#define DDRSS_PHY_369_DATA 0x000B2010 #define DDRSS_PHY_370_DATA 0x76543210 #define DDRSS_PHY_371_DATA 0x00000008 #define DDRSS_PHY_372_DATA 0x02800280 @@ -1157,8 +1165,8 @@ #define DDRSS_PHY_383_DATA 0x00A000A0 #define DDRSS_PHY_384_DATA 0x00A000A0 #define DDRSS_PHY_385_DATA 0x00A000A0 -#define DDRSS_PHY_386_DATA 0x01C400A0 -#define DDRSS_PHY_387_DATA 0x01A00003 +#define DDRSS_PHY_386_DATA 0x011900A0 +#define DDRSS_PHY_387_DATA 0x01A00004 #define DDRSS_PHY_388_DATA 0x00000000 #define DDRSS_PHY_389_DATA 0x00000000 #define DDRSS_PHY_390_DATA 0x00080200 @@ -1295,7 +1303,7 @@ #define DDRSS_PHY_521_DATA 0x00000000 #define DDRSS_PHY_522_DATA 0x00000000 #define DDRSS_PHY_523_DATA 0x01000001 -#define DDRSS_PHY_524_DATA 0x00000100 +#define DDRSS_PHY_524_DATA 0x00000200 #define DDRSS_PHY_525_DATA 0x000800C0 #define DDRSS_PHY_526_DATA 0x060100CC #define DDRSS_PHY_527_DATA 0x00030066 @@ -1314,9 +1322,9 @@ #define DDRSS_PHY_540_DATA 0x2A000000 #define DDRSS_PHY_541_DATA 0x00000808 #define DDRSS_PHY_542_DATA 0x0F000000 -#define DDRSS_PHY_543_DATA 0x00000F0F -#define DDRSS_PHY_544_DATA 0x10200000 -#define DDRSS_PHY_545_DATA 0x0C002007 +#define DDRSS_PHY_543_DATA 0x00000F08 +#define DDRSS_PHY_544_DATA 0x10400000 +#define DDRSS_PHY_545_DATA 0x0C002006 #define DDRSS_PHY_546_DATA 0x00000000 #define DDRSS_PHY_547_DATA 0x00000000 #define DDRSS_PHY_548_DATA 0x55555555 @@ -1383,20 +1391,20 @@ #define DDRSS_PHY_609_DATA 0x00050010 #define DDRSS_PHY_610_DATA 0x51517041 #define DDRSS_PHY_611_DATA 0x31C06000 -#define DDRSS_PHY_612_DATA 0x07AB0340 +#define DDRSS_PHY_612_DATA 0x07AB01AB #define DDRSS_PHY_613_DATA 0x00C0C001 -#define DDRSS_PHY_614_DATA 0x09080001 +#define DDRSS_PHY_614_DATA 0x0B0A0101 #define DDRSS_PHY_615_DATA 0x10001000 -#define DDRSS_PHY_616_DATA 0x0C063E42 -#define DDRSS_PHY_617_DATA 0x0F0C2701 +#define DDRSS_PHY_616_DATA 0x0C073E42 +#define DDRSS_PHY_617_DATA 0x0F0C2D01 #define DDRSS_PHY_618_DATA 0x01000140 -#define DDRSS_PHY_619_DATA 0x04000420 +#define DDRSS_PHY_619_DATA 0x0C000420 #define DDRSS_PHY_620_DATA 0x00000198 #define DDRSS_PHY_621_DATA 0x0A0000D0 #define DDRSS_PHY_622_DATA 0x00030200 #define DDRSS_PHY_623_DATA 0x02800000 #define DDRSS_PHY_624_DATA 0x80800000 -#define DDRSS_PHY_625_DATA 0x00092010 +#define DDRSS_PHY_625_DATA 0x000B2010 #define DDRSS_PHY_626_DATA 0x76543210 #define DDRSS_PHY_627_DATA 0x00000008 #define DDRSS_PHY_628_DATA 0x02800280 @@ -1413,8 +1421,8 @@ #define DDRSS_PHY_639_DATA 0x00A000A0 #define DDRSS_PHY_640_DATA 0x00A000A0 #define DDRSS_PHY_641_DATA 0x00A000A0 -#define DDRSS_PHY_642_DATA 0x01C400A0 -#define DDRSS_PHY_643_DATA 0x01A00003 +#define DDRSS_PHY_642_DATA 0x011900A0 +#define DDRSS_PHY_643_DATA 0x01A00004 #define DDRSS_PHY_644_DATA 0x00000000 #define DDRSS_PHY_645_DATA 0x00000000 #define DDRSS_PHY_646_DATA 0x00080200 @@ -1551,7 +1559,7 @@ #define DDRSS_PHY_777_DATA 0x00000000 #define DDRSS_PHY_778_DATA 0x00000000 #define DDRSS_PHY_779_DATA 0x01000001 -#define DDRSS_PHY_780_DATA 0x00000100 +#define DDRSS_PHY_780_DATA 0x00000200 #define DDRSS_PHY_781_DATA 0x000800C0 #define DDRSS_PHY_782_DATA 0x060100CC #define DDRSS_PHY_783_DATA 0x00030066 @@ -1570,9 +1578,9 @@ #define DDRSS_PHY_796_DATA 0x2A000000 #define DDRSS_PHY_797_DATA 0x00000808 #define DDRSS_PHY_798_DATA 0x0F000000 -#define DDRSS_PHY_799_DATA 0x00000F0F -#define DDRSS_PHY_800_DATA 0x10200000 -#define DDRSS_PHY_801_DATA 0x0C002007 +#define DDRSS_PHY_799_DATA 0x00000F08 +#define DDRSS_PHY_800_DATA 0x10400000 +#define DDRSS_PHY_801_DATA 0x0C002006 #define DDRSS_PHY_802_DATA 0x00000000 #define DDRSS_PHY_803_DATA 0x00000000 #define DDRSS_PHY_804_DATA 0x55555555 @@ -1639,20 +1647,20 @@ #define DDRSS_PHY_865_DATA 0x00050010 #define DDRSS_PHY_866_DATA 0x51517041 #define DDRSS_PHY_867_DATA 0x31C06000 -#define DDRSS_PHY_868_DATA 0x07AB0340 +#define DDRSS_PHY_868_DATA 0x07AB01AB #define DDRSS_PHY_869_DATA 0x00C0C001 -#define DDRSS_PHY_870_DATA 0x09080001 +#define DDRSS_PHY_870_DATA 0x0B0A0101 #define DDRSS_PHY_871_DATA 0x10001000 -#define DDRSS_PHY_872_DATA 0x0C063E42 -#define DDRSS_PHY_873_DATA 0x0F0C2701 +#define DDRSS_PHY_872_DATA 0x0C073E42 +#define DDRSS_PHY_873_DATA 0x0F0C2D01 #define DDRSS_PHY_874_DATA 0x01000140 -#define DDRSS_PHY_875_DATA 0x04000420 +#define DDRSS_PHY_875_DATA 0x0C000420 #define DDRSS_PHY_876_DATA 0x00000198 #define DDRSS_PHY_877_DATA 0x0A0000D0 #define DDRSS_PHY_878_DATA 0x00030200 #define DDRSS_PHY_879_DATA 0x02800000 #define DDRSS_PHY_880_DATA 0x80800000 -#define DDRSS_PHY_881_DATA 0x00092010 +#define DDRSS_PHY_881_DATA 0x000B2010 #define DDRSS_PHY_882_DATA 0x76543210 #define DDRSS_PHY_883_DATA 0x00000008 #define DDRSS_PHY_884_DATA 0x02800280 @@ -1669,8 +1677,8 @@ #define DDRSS_PHY_895_DATA 0x00A000A0 #define DDRSS_PHY_896_DATA 0x00A000A0 #define DDRSS_PHY_897_DATA 0x00A000A0 -#define DDRSS_PHY_898_DATA 0x01C400A0 -#define DDRSS_PHY_899_DATA 0x01A00003 +#define DDRSS_PHY_898_DATA 0x011900A0 +#define DDRSS_PHY_899_DATA 0x01A00004 #define DDRSS_PHY_900_DATA 0x00000000 #define DDRSS_PHY_901_DATA 0x00000000 #define DDRSS_PHY_902_DATA 0x00080200 @@ -1810,7 +1818,7 @@ #define DDRSS_PHY_1036_DATA 0x00000080 #define DDRSS_PHY_1037_DATA 0x00DCBA98 #define DDRSS_PHY_1038_DATA 0x03000000 -#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1039_DATA 0x00200001 #define DDRSS_PHY_1040_DATA 0x00000000 #define DDRSS_PHY_1041_DATA 0x00000000 #define DDRSS_PHY_1042_DATA 0x00000000 @@ -1826,7 +1834,7 @@ #define DDRSS_PHY_1052_DATA 0x00000033 #define DDRSS_PHY_1053_DATA 0x00543210 #define DDRSS_PHY_1054_DATA 0x003F0000 -#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1055_DATA 0x000F3F3F #define DDRSS_PHY_1056_DATA 0x20202003 #define DDRSS_PHY_1057_DATA 0x00202020 #define DDRSS_PHY_1058_DATA 0x20008008 @@ -1835,7 +1843,7 @@ #define DDRSS_PHY_1061_DATA 0x00000000 #define DDRSS_PHY_1062_DATA 0x00000000 #define DDRSS_PHY_1063_DATA 0x00000000 -#define DDRSS_PHY_1064_DATA 0x000205BB +#define DDRSS_PHY_1064_DATA 0x000305CC #define DDRSS_PHY_1065_DATA 0x00030000 #define DDRSS_PHY_1066_DATA 0x00000300 #define DDRSS_PHY_1067_DATA 0x00000300 @@ -1844,8 +1852,8 @@ #define DDRSS_PHY_1070_DATA 0x00000300 #define DDRSS_PHY_1071_DATA 0x42080010 #define DDRSS_PHY_1072_DATA 0x0000803E -#define DDRSS_PHY_1073_DATA 0x00000001 -#define DDRSS_PHY_1074_DATA 0x01000102 +#define DDRSS_PHY_1073_DATA 0x00000004 +#define DDRSS_PHY_1074_DATA 0x01000002 #define DDRSS_PHY_1075_DATA 0x00008000 #define DDRSS_PHY_1076_DATA 0x00000000 #define DDRSS_PHY_1077_DATA 0x00000000 @@ -2074,14 +2082,14 @@ #define DDRSS_PHY_1300_DATA 0x00040101 #define DDRSS_PHY_1301_DATA 0x0000010F #define DDRSS_PHY_1302_DATA 0x00000000 -#define DDRSS_PHY_1303_DATA 0x0000FFFF +#define DDRSS_PHY_1303_DATA 0x00000064 #define DDRSS_PHY_1304_DATA 0x00000000 #define DDRSS_PHY_1305_DATA 0x01010000 #define DDRSS_PHY_1306_DATA 0x01080402 #define DDRSS_PHY_1307_DATA 0x01200F02 #define DDRSS_PHY_1308_DATA 0x00194280 #define DDRSS_PHY_1309_DATA 0x00000004 -#define DDRSS_PHY_1310_DATA 0x00052000 +#define DDRSS_PHY_1310_DATA 0x00042000 #define DDRSS_PHY_1311_DATA 0x00000000 #define DDRSS_PHY_1312_DATA 0x00000000 #define DDRSS_PHY_1313_DATA 0x00000000 @@ -2165,10 +2173,10 @@ #define DDRSS_PHY_1391_DATA 0x00000000 #define DDRSS_PHY_1392_DATA 0x00000000 #define DDRSS_PHY_1393_DATA 0x0001F7C0 -#define DDRSS_PHY_1394_DATA 0x00000002 +#define DDRSS_PHY_1394_DATA 0x00000003 #define DDRSS_PHY_1395_DATA 0x00000000 #define DDRSS_PHY_1396_DATA 0x00001142 -#define DDRSS_PHY_1397_DATA 0x010207AB +#define DDRSS_PHY_1397_DATA 0x040207AB #define DDRSS_PHY_1398_DATA 0x01000080 #define DDRSS_PHY_1399_DATA 0x03900390 #define DDRSS_PHY_1400_DATA 0x03900390 @@ -2177,20 +2185,23 @@ #define DDRSS_PHY_1403_DATA 0x00000390 #define DDRSS_PHY_1404_DATA 0x00000390 #define DDRSS_PHY_1405_DATA 0x00000005 -#define DDRSS_PHY_1406_DATA 0x01813FBB -#define DDRSS_PHY_1407_DATA 0x000000BB +#define DDRSS_PHY_1406_DATA 0x01813FCC +#define DDRSS_PHY_1407_DATA 0x000000CC #define DDRSS_PHY_1408_DATA 0x0C000DFF #define DDRSS_PHY_1409_DATA 0x30000DFF #define DDRSS_PHY_1410_DATA 0x3F0DFF11 #define DDRSS_PHY_1411_DATA 0x000100F0 -#define DDRSS_PHY_1412_DATA 0x780DFFBB +#define DDRSS_PHY_1412_DATA 0x780DFFCC #define DDRSS_PHY_1413_DATA 0x00007E31 #define DDRSS_PHY_1414_DATA 0x000CBF11 -#define DDRSS_PHY_1415_DATA 0x01770010 +#define DDRSS_PHY_1415_DATA 0x01990010 #define DDRSS_PHY_1416_DATA 0x000CBF11 -#define DDRSS_PHY_1417_DATA 0x01770010 +#define DDRSS_PHY_1417_DATA 0x01990010 #define DDRSS_PHY_1418_DATA 0x3F0DFF11 -#define DDRSS_PHY_1419_DATA 0x017700F0 +#define DDRSS_PHY_1419_DATA 0x00EF00F0 #define DDRSS_PHY_1420_DATA 0x3F0DFF11 #define DDRSS_PHY_1421_DATA 0x01FF00F0 #define DDRSS_PHY_1422_DATA 0x20040006 + + + diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index b0e73fe72c4..8de96ad5c9e 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "k3-j7200-common-proc-board.dts" -#include "k3-j7200-ddr-evm-lp4-2666.dtsi" +#include "k3-j7200-ddr-evm-lp4-3200.dtsi" #include "k3-j721e-ddr.dtsi" #include "k3-j7200-common-proc-board-u-boot.dtsi" #include "k3-j7200-r5.dtsi" diff --git a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi index c91576bf093..ecd42b1cf4d 100644 --- a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.7.0 - * This file was generated on 10/14/2021 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:46:29 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -16,6 +28,15 @@ #define MULTI_DDR_CFG_HYBRID_SELECT 0 #define MULTI_DDR_CFG_EMIFS_ACTIVE 3 +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000003 +#define DDR_REG1_SIZE_LSB 0x80000000 + + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -36,7 +57,7 @@ #define DDRSS0_CTL_17_DATA 0x00000005 #define DDRSS0_CTL_18_DATA 0x000010A9 #define DDRSS0_CTL_19_DATA 0x01010000 -#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_20_DATA 0x01011001 #define DDRSS0_CTL_21_DATA 0x02010000 #define DDRSS0_CTL_22_DATA 0x00020100 #define DDRSS0_CTL_23_DATA 0x0000000B @@ -51,7 +72,7 @@ #define DDRSS0_CTL_32_DATA 0x00000000 #define DDRSS0_CTL_33_DATA 0x00000000 #define DDRSS0_CTL_34_DATA 0x040C0000 -#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_35_DATA 0x12501250 #define DDRSS0_CTL_36_DATA 0x00050804 #define DDRSS0_CTL_37_DATA 0x09040008 #define DDRSS0_CTL_38_DATA 0x15000204 @@ -60,33 +81,33 @@ #define DDRSS0_CTL_41_DATA 0x1760008B #define DDRSS0_CTL_42_DATA 0x2000422B #define DDRSS0_CTL_43_DATA 0x000A0A09 -#define DDRSS0_CTL_44_DATA 0x0400078A +#define DDRSS0_CTL_44_DATA 0x040003C5 #define DDRSS0_CTL_45_DATA 0x1E161104 -#define DDRSS0_CTL_46_DATA 0x10012458 +#define DDRSS0_CTL_46_DATA 0x1000922C #define DDRSS0_CTL_47_DATA 0x1E161110 -#define DDRSS0_CTL_48_DATA 0x10012458 +#define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 -#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_50_DATA 0x2C060500 #define DDRSS0_CTL_51_DATA 0x08292C29 #define DDRSS0_CTL_52_DATA 0x14000E0A #define DDRSS0_CTL_53_DATA 0x04010A0A #define DDRSS0_CTL_54_DATA 0x01010004 -#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_55_DATA 0x0454540A #define DDRSS0_CTL_56_DATA 0x04313104 #define DDRSS0_CTL_57_DATA 0x00003131 #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x000000CE +#define DDRSS0_CTL_61_DATA 0x00000068 #define DDRSS0_CTL_62_DATA 0x0000032B -#define DDRSS0_CTL_63_DATA 0x00002073 +#define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B -#define DDRSS0_CTL_65_DATA 0x00002073 +#define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 -#define DDRSS0_CTL_68_DATA 0x00CB0012 -#define DDRSS0_CTL_69_DATA 0x00CB0408 -#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 #define DDRSS0_CTL_71_DATA 0x00120103 #define DDRSS0_CTL_72_DATA 0x00100005 #define DDRSS0_CTL_73_DATA 0x2F080010 @@ -118,27 +139,27 @@ #define DDRSS0_CTL_99_DATA 0x00000000 #define DDRSS0_CTL_100_DATA 0x00040005 #define DDRSS0_CTL_101_DATA 0x00000000 -#define DDRSS0_CTL_102_DATA 0x00003380 -#define DDRSS0_CTL_103_DATA 0x00003380 -#define DDRSS0_CTL_104_DATA 0x00003380 -#define DDRSS0_CTL_105_DATA 0x00003380 -#define DDRSS0_CTL_106_DATA 0x00003380 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 #define DDRSS0_CTL_107_DATA 0x00000000 -#define DDRSS0_CTL_108_DATA 0x000005A2 -#define DDRSS0_CTL_109_DATA 0x00081CC0 -#define DDRSS0_CTL_110_DATA 0x00081CC0 -#define DDRSS0_CTL_111_DATA 0x00081CC0 -#define DDRSS0_CTL_112_DATA 0x00081CC0 -#define DDRSS0_CTL_113_DATA 0x00081CC0 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 #define DDRSS0_CTL_114_DATA 0x00000000 -#define DDRSS0_CTL_115_DATA 0x0000E325 -#define DDRSS0_CTL_116_DATA 0x00081CC0 -#define DDRSS0_CTL_117_DATA 0x00081CC0 -#define DDRSS0_CTL_118_DATA 0x00081CC0 -#define DDRSS0_CTL_119_DATA 0x00081CC0 -#define DDRSS0_CTL_120_DATA 0x00081CC0 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 #define DDRSS0_CTL_121_DATA 0x00000000 -#define DDRSS0_CTL_122_DATA 0x0000E325 +#define DDRSS0_CTL_122_DATA 0x00007173 #define DDRSS0_CTL_123_DATA 0x00000000 #define DDRSS0_CTL_124_DATA 0x00000000 #define DDRSS0_CTL_125_DATA 0x00000000 @@ -192,22 +213,22 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 -#define DDRSS0_CTL_178_DATA 0x56000000 -#define DDRSS0_CTL_179_DATA 0x27270056 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 +#define DDRSS0_CTL_178_DATA 0x36000000 +#define DDRSS0_CTL_179_DATA 0x27270036 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 #define DDRSS0_CTL_185_DATA 0x00000000 -#define DDRSS0_CTL_186_DATA 0x00565600 +#define DDRSS0_CTL_186_DATA 0x00363600 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 #define DDRSS0_CTL_190_DATA 0x00000020 -#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_191_DATA 0x01000000 #define DDRSS0_CTL_192_DATA 0x00000001 #define DDRSS0_CTL_193_DATA 0x00000000 #define DDRSS0_CTL_194_DATA 0x01000000 @@ -245,17 +266,17 @@ #define DDRSS0_CTL_226_DATA 0x00000000 #define DDRSS0_CTL_227_DATA 0x15110000 #define DDRSS0_CTL_228_DATA 0x00040C18 -#define DDRSS0_CTL_229_DATA 0x00000000 -#define DDRSS0_CTL_230_DATA 0x00000000 +#define DDRSS0_CTL_229_DATA 0xF000C000 +#define DDRSS0_CTL_230_DATA 0x0000F000 #define DDRSS0_CTL_231_DATA 0x00000000 #define DDRSS0_CTL_232_DATA 0x00000000 -#define DDRSS0_CTL_233_DATA 0x00000000 -#define DDRSS0_CTL_234_DATA 0x00000000 +#define DDRSS0_CTL_233_DATA 0xC0000000 +#define DDRSS0_CTL_234_DATA 0xF000F000 #define DDRSS0_CTL_235_DATA 0x00000000 #define DDRSS0_CTL_236_DATA 0x00000000 #define DDRSS0_CTL_237_DATA 0x00000000 -#define DDRSS0_CTL_238_DATA 0x00000000 -#define DDRSS0_CTL_239_DATA 0x00000000 +#define DDRSS0_CTL_238_DATA 0xF000C000 +#define DDRSS0_CTL_239_DATA 0x0000F000 #define DDRSS0_CTL_240_DATA 0x00000000 #define DDRSS0_CTL_241_DATA 0x00000000 #define DDRSS0_CTL_242_DATA 0x00030000 @@ -283,7 +304,7 @@ #define DDRSS0_CTL_264_DATA 0x00000040 #define DDRSS0_CTL_265_DATA 0x006B0003 #define DDRSS0_CTL_266_DATA 0x0100006B -#define DDRSS0_CTL_267_DATA 0x00000000 +#define DDRSS0_CTL_267_DATA 0x03030303 #define DDRSS0_CTL_268_DATA 0x00000000 #define DDRSS0_CTL_269_DATA 0x00000202 #define DDRSS0_CTL_270_DATA 0x00001FFF @@ -307,14 +328,14 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00010101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 #define DDRSS0_CTL_295_DATA 0x00000000 #define DDRSS0_CTL_296_DATA 0x00000000 -#define DDRSS0_CTL_297_DATA 0x00000000 -#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF #define DDRSS0_CTL_299_DATA 0x00000000 #define DDRSS0_CTL_300_DATA 0x00000000 #define DDRSS0_CTL_301_DATA 0x00000000 @@ -335,7 +356,7 @@ #define DDRSS0_CTL_316_DATA 0x01010001 #define DDRSS0_CTL_317_DATA 0x00010101 #define DDRSS0_CTL_318_DATA 0x050A0A03 -#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_319_DATA 0x10082323 #define DDRSS0_CTL_320_DATA 0x00090310 #define DDRSS0_CTL_321_DATA 0x0B0C030F #define DDRSS0_CTL_322_DATA 0x0B0C0306 @@ -405,30 +426,30 @@ #define DDRSS0_CTL_386_DATA 0x00000000 #define DDRSS0_CTL_387_DATA 0x3A3A1B00 #define DDRSS0_CTL_388_DATA 0x000A0000 -#define DDRSS0_CTL_389_DATA 0x0000019C +#define DDRSS0_CTL_389_DATA 0x000000C6 #define DDRSS0_CTL_390_DATA 0x00000200 #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x000004D4 -#define DDRSS0_CTL_395_DATA 0x00001018 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 -#define DDRSS0_CTL_397_DATA 0x000040E6 +#define DDRSS0_CTL_397_DATA 0x0000206A #define DDRSS0_CTL_398_DATA 0x00000200 #define DDRSS0_CTL_399_DATA 0x00000200 #define DDRSS0_CTL_400_DATA 0x00000200 #define DDRSS0_CTL_401_DATA 0x00000200 -#define DDRSS0_CTL_402_DATA 0x0000C2B2 -#define DDRSS0_CTL_403_DATA 0x000288FC -#define DDRSS0_CTL_404_DATA 0x00000E15 -#define DDRSS0_CTL_405_DATA 0x000040E6 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 #define DDRSS0_CTL_408_DATA 0x00000200 #define DDRSS0_CTL_409_DATA 0x00000200 -#define DDRSS0_CTL_410_DATA 0x0000C2B2 -#define DDRSS0_CTL_411_DATA 0x000288FC -#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 #define DDRSS0_CTL_415_DATA 0x00000000 @@ -445,7 +466,7 @@ #define DDRSS0_CTL_426_DATA 0x00000000 #define DDRSS0_CTL_427_DATA 0x02000000 #define DDRSS0_CTL_428_DATA 0x01000404 -#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_429_DATA 0x0B220B22 #define DDRSS0_CTL_430_DATA 0x00000105 #define DDRSS0_CTL_431_DATA 0x00010101 #define DDRSS0_CTL_432_DATA 0x00010101 @@ -488,8 +509,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -537,18 +558,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 -#define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_66_DATA 0x01000100 +#define DDRSS0_PI_67_DATA 0x0102020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -637,37 +658,37 @@ #define DDRSS0_PI_158_DATA 0x00000000 #define DDRSS0_PI_159_DATA 0x00000401 #define DDRSS0_PI_160_DATA 0x00000000 -#define DDRSS0_PI_161_DATA 0x00010000 -#define DDRSS0_PI_162_DATA 0x00000000 -#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 #define DDRSS0_PI_164_DATA 0x00000034 -#define DDRSS0_PI_165_DATA 0x00000064 -#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 #define DDRSS0_PI_167_DATA 0x02000200 -#define DDRSS0_PI_168_DATA 0x48120C04 -#define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x000000CE +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 #define DDRSS0_PI_171_DATA 0x0000032B -#define DDRSS0_PI_172_DATA 0x00002073 +#define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B -#define DDRSS0_PI_174_DATA 0x04002073 +#define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 -#define DDRSS0_PI_185_DATA 0x15040000 -#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 #define DDRSS0_PI_187_DATA 0x00040402 #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -675,8 +696,8 @@ #define DDRSS0_PI_196_DATA 0x02170100 #define DDRSS0_PI_197_DATA 0x01000217 #define DDRSS0_PI_198_DATA 0x02170217 -#define DDRSS0_PI_199_DATA 0x32103200 -#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B #define DDRSS0_PI_201_DATA 0x0A070601 #define DDRSS0_PI_202_DATA 0x1F130A0D #define DDRSS0_PI_203_DATA 0x1F130A14 @@ -688,29 +709,29 @@ #define DDRSS0_PI_209_DATA 0x00240216 #define DDRSS0_PI_210_DATA 0x00110216 #define DDRSS0_PI_211_DATA 0x32000056 -#define DDRSS0_PI_212_DATA 0x00000301 -#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 -#define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 -#define DDRSS0_PI_218_DATA 0x04010504 -#define DDRSS0_PI_219_DATA 0x040006C9 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A #define DDRSS0_PI_222_DATA 0x00002918 -#define DDRSS0_PI_223_DATA 0x6001071C +#define DDRSS0_PI_223_DATA 0x6000838E #define DDRSS0_PI_224_DATA 0x1E202008 #define DDRSS0_PI_225_DATA 0x2C311116 #define DDRSS0_PI_226_DATA 0x00002918 -#define DDRSS0_PI_227_DATA 0x6001071C +#define DDRSS0_PI_227_DATA 0x6000838E #define DDRSS0_PI_228_DATA 0x1E202008 -#define DDRSS0_PI_229_DATA 0x00019C16 -#define DDRSS0_PI_230_DATA 0x00001018 -#define DDRSS0_PI_231_DATA 0x000040E6 -#define DDRSS0_PI_232_DATA 0x000288FC -#define DDRSS0_PI_233_DATA 0x000040E6 -#define DDRSS0_PI_234_DATA 0x000288FC +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 #define DDRSS0_PI_235_DATA 0x033B0016 #define DDRSS0_PI_236_DATA 0x0303033B #define DDRSS0_PI_237_DATA 0x002AF803 @@ -751,29 +772,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00F30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x56333FF4 +#define DDRSS0_PI_277_DATA 0x36F33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x56333FF4 +#define DDRSS0_PI_279_DATA 0x36F33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00F30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x56333FF4 +#define DDRSS0_PI_283_DATA 0x36F33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x56333FF4 +#define DDRSS0_PI_285_DATA 0x36F33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00F30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x56333FF4 +#define DDRSS0_PI_289_DATA 0x36F33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x56333FF4 +#define DDRSS0_PI_291_DATA 0x36F33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00F30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x56333FF4 +#define DDRSS0_PI_295_DATA 0x36F33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x56333FF4 +#define DDRSS0_PI_297_DATA 0x36F33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -789,7 +810,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -808,9 +829,9 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F -#define DDRSS0_PHY_32_DATA 0x10200000 -#define DDRSS0_PHY_33_DATA 0x0C002006 +#define DDRSS0_PHY_31_DATA 0x00000F08 +#define DDRSS0_PHY_32_DATA 0x10400000 +#define DDRSS0_PHY_33_DATA 0x0C002002 #define DDRSS0_PHY_34_DATA 0x00000000 #define DDRSS0_PHY_35_DATA 0x00000000 #define DDRSS0_PHY_36_DATA 0x55555555 @@ -877,9 +898,9 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 -#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 #define DDRSS0_PHY_103_DATA 0x10001000 #define DDRSS0_PHY_104_DATA 0x0C083E42 #define DDRSS0_PHY_105_DATA 0x0F0C3701 @@ -913,7 +934,7 @@ #define DDRSS0_PHY_133_DATA 0x00000000 #define DDRSS0_PHY_134_DATA 0x00080200 #define DDRSS0_PHY_135_DATA 0x00000000 -#define DDRSS0_PHY_136_DATA 0x20202000 +#define DDRSS0_PHY_136_DATA 0x20202020 #define DDRSS0_PHY_137_DATA 0x20202020 #define DDRSS0_PHY_138_DATA 0xF0F02020 #define DDRSS0_PHY_139_DATA 0x00000000 @@ -1045,7 +1066,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1064,9 +1085,9 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F -#define DDRSS0_PHY_288_DATA 0x10200000 -#define DDRSS0_PHY_289_DATA 0x0C002006 +#define DDRSS0_PHY_287_DATA 0x00000F08 +#define DDRSS0_PHY_288_DATA 0x10400000 +#define DDRSS0_PHY_289_DATA 0x0C002002 #define DDRSS0_PHY_290_DATA 0x00000000 #define DDRSS0_PHY_291_DATA 0x00000000 #define DDRSS0_PHY_292_DATA 0x55555555 @@ -1133,9 +1154,9 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 -#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 #define DDRSS0_PHY_359_DATA 0x10001000 #define DDRSS0_PHY_360_DATA 0x0C083E42 #define DDRSS0_PHY_361_DATA 0x0F0C3701 @@ -1169,7 +1190,7 @@ #define DDRSS0_PHY_389_DATA 0x00000000 #define DDRSS0_PHY_390_DATA 0x00080200 #define DDRSS0_PHY_391_DATA 0x00000000 -#define DDRSS0_PHY_392_DATA 0x20202000 +#define DDRSS0_PHY_392_DATA 0x20202020 #define DDRSS0_PHY_393_DATA 0x20202020 #define DDRSS0_PHY_394_DATA 0xF0F02020 #define DDRSS0_PHY_395_DATA 0x00000000 @@ -1301,7 +1322,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1320,9 +1341,9 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F -#define DDRSS0_PHY_544_DATA 0x10200000 -#define DDRSS0_PHY_545_DATA 0x0C002006 +#define DDRSS0_PHY_543_DATA 0x00000F08 +#define DDRSS0_PHY_544_DATA 0x10400000 +#define DDRSS0_PHY_545_DATA 0x0C002002 #define DDRSS0_PHY_546_DATA 0x00000000 #define DDRSS0_PHY_547_DATA 0x00000000 #define DDRSS0_PHY_548_DATA 0x55555555 @@ -1389,9 +1410,9 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 -#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 #define DDRSS0_PHY_615_DATA 0x10001000 #define DDRSS0_PHY_616_DATA 0x0C083E42 #define DDRSS0_PHY_617_DATA 0x0F0C3701 @@ -1425,7 +1446,7 @@ #define DDRSS0_PHY_645_DATA 0x00000000 #define DDRSS0_PHY_646_DATA 0x00080200 #define DDRSS0_PHY_647_DATA 0x00000000 -#define DDRSS0_PHY_648_DATA 0x20202000 +#define DDRSS0_PHY_648_DATA 0x20202020 #define DDRSS0_PHY_649_DATA 0x20202020 #define DDRSS0_PHY_650_DATA 0xF0F02020 #define DDRSS0_PHY_651_DATA 0x00000000 @@ -1557,7 +1578,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1576,9 +1597,9 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F -#define DDRSS0_PHY_800_DATA 0x10200000 -#define DDRSS0_PHY_801_DATA 0x0C002006 +#define DDRSS0_PHY_799_DATA 0x00000F08 +#define DDRSS0_PHY_800_DATA 0x10400000 +#define DDRSS0_PHY_801_DATA 0x0C002002 #define DDRSS0_PHY_802_DATA 0x00000000 #define DDRSS0_PHY_803_DATA 0x00000000 #define DDRSS0_PHY_804_DATA 0x55555555 @@ -1645,9 +1666,9 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 -#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 #define DDRSS0_PHY_871_DATA 0x10001000 #define DDRSS0_PHY_872_DATA 0x0C083E42 #define DDRSS0_PHY_873_DATA 0x0F0C3701 @@ -1681,7 +1702,7 @@ #define DDRSS0_PHY_901_DATA 0x00000000 #define DDRSS0_PHY_902_DATA 0x00080200 #define DDRSS0_PHY_903_DATA 0x00000000 -#define DDRSS0_PHY_904_DATA 0x20202000 +#define DDRSS0_PHY_904_DATA 0x20202020 #define DDRSS0_PHY_905_DATA 0x20202020 #define DDRSS0_PHY_906_DATA 0xF0F02020 #define DDRSS0_PHY_907_DATA 0x00000000 @@ -1832,7 +1853,7 @@ #define DDRSS0_PHY_1052_DATA 0x00000033 #define DDRSS0_PHY_1053_DATA 0x00543210 #define DDRSS0_PHY_1054_DATA 0x003F0000 -#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1055_DATA 0x000F3F3F #define DDRSS0_PHY_1056_DATA 0x20202003 #define DDRSS0_PHY_1057_DATA 0x00202020 #define DDRSS0_PHY_1058_DATA 0x20008008 @@ -2080,14 +2101,14 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 #define DDRSS0_PHY_1307_DATA 0x01200F02 #define DDRSS0_PHY_1308_DATA 0x00194280 #define DDRSS0_PHY_1309_DATA 0x00000004 -#define DDRSS0_PHY_1310_DATA 0x00052000 +#define DDRSS0_PHY_1310_DATA 0x00042000 #define DDRSS0_PHY_1311_DATA 0x00000000 #define DDRSS0_PHY_1312_DATA 0x00000000 #define DDRSS0_PHY_1313_DATA 0x00000000 @@ -2174,7 +2195,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2221,7 +2242,7 @@ #define DDRSS1_CTL_17_DATA 0x00000005 #define DDRSS1_CTL_18_DATA 0x000010A9 #define DDRSS1_CTL_19_DATA 0x01010000 -#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_20_DATA 0x01011001 #define DDRSS1_CTL_21_DATA 0x02010000 #define DDRSS1_CTL_22_DATA 0x00020100 #define DDRSS1_CTL_23_DATA 0x0000000B @@ -2236,7 +2257,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2245,33 +2266,33 @@ #define DDRSS1_CTL_41_DATA 0x1760008B #define DDRSS1_CTL_42_DATA 0x2000422B #define DDRSS1_CTL_43_DATA 0x000A0A09 -#define DDRSS1_CTL_44_DATA 0x0400078A +#define DDRSS1_CTL_44_DATA 0x040003C5 #define DDRSS1_CTL_45_DATA 0x1E161104 -#define DDRSS1_CTL_46_DATA 0x10012458 +#define DDRSS1_CTL_46_DATA 0x1000922C #define DDRSS1_CTL_47_DATA 0x1E161110 -#define DDRSS1_CTL_48_DATA 0x10012458 +#define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 -#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_50_DATA 0x2C060500 #define DDRSS1_CTL_51_DATA 0x08292C29 #define DDRSS1_CTL_52_DATA 0x14000E0A #define DDRSS1_CTL_53_DATA 0x04010A0A #define DDRSS1_CTL_54_DATA 0x01010004 -#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_55_DATA 0x0454540A #define DDRSS1_CTL_56_DATA 0x04313104 #define DDRSS1_CTL_57_DATA 0x00003131 #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x000000CE +#define DDRSS1_CTL_61_DATA 0x00000068 #define DDRSS1_CTL_62_DATA 0x0000032B -#define DDRSS1_CTL_63_DATA 0x00002073 +#define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B -#define DDRSS1_CTL_65_DATA 0x00002073 +#define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 -#define DDRSS1_CTL_68_DATA 0x00CB0012 -#define DDRSS1_CTL_69_DATA 0x00CB0408 -#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 #define DDRSS1_CTL_71_DATA 0x00120103 #define DDRSS1_CTL_72_DATA 0x00100005 #define DDRSS1_CTL_73_DATA 0x2F080010 @@ -2303,27 +2324,27 @@ #define DDRSS1_CTL_99_DATA 0x00000000 #define DDRSS1_CTL_100_DATA 0x00040005 #define DDRSS1_CTL_101_DATA 0x00000000 -#define DDRSS1_CTL_102_DATA 0x00003380 -#define DDRSS1_CTL_103_DATA 0x00003380 -#define DDRSS1_CTL_104_DATA 0x00003380 -#define DDRSS1_CTL_105_DATA 0x00003380 -#define DDRSS1_CTL_106_DATA 0x00003380 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 #define DDRSS1_CTL_107_DATA 0x00000000 -#define DDRSS1_CTL_108_DATA 0x000005A2 -#define DDRSS1_CTL_109_DATA 0x00081CC0 -#define DDRSS1_CTL_110_DATA 0x00081CC0 -#define DDRSS1_CTL_111_DATA 0x00081CC0 -#define DDRSS1_CTL_112_DATA 0x00081CC0 -#define DDRSS1_CTL_113_DATA 0x00081CC0 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 #define DDRSS1_CTL_114_DATA 0x00000000 -#define DDRSS1_CTL_115_DATA 0x0000E325 -#define DDRSS1_CTL_116_DATA 0x00081CC0 -#define DDRSS1_CTL_117_DATA 0x00081CC0 -#define DDRSS1_CTL_118_DATA 0x00081CC0 -#define DDRSS1_CTL_119_DATA 0x00081CC0 -#define DDRSS1_CTL_120_DATA 0x00081CC0 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 #define DDRSS1_CTL_121_DATA 0x00000000 -#define DDRSS1_CTL_122_DATA 0x0000E325 +#define DDRSS1_CTL_122_DATA 0x00007173 #define DDRSS1_CTL_123_DATA 0x00000000 #define DDRSS1_CTL_124_DATA 0x00000000 #define DDRSS1_CTL_125_DATA 0x00000000 @@ -2377,22 +2398,22 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 -#define DDRSS1_CTL_178_DATA 0x56000000 -#define DDRSS1_CTL_179_DATA 0x27270056 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 +#define DDRSS1_CTL_178_DATA 0x36000000 +#define DDRSS1_CTL_179_DATA 0x27270036 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 -#define DDRSS1_CTL_186_DATA 0x00565600 +#define DDRSS1_CTL_186_DATA 0x00363600 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 #define DDRSS1_CTL_190_DATA 0x00000020 -#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_191_DATA 0x01000000 #define DDRSS1_CTL_192_DATA 0x00000001 #define DDRSS1_CTL_193_DATA 0x00000000 #define DDRSS1_CTL_194_DATA 0x01000000 @@ -2430,17 +2451,17 @@ #define DDRSS1_CTL_226_DATA 0x00000000 #define DDRSS1_CTL_227_DATA 0x15110000 #define DDRSS1_CTL_228_DATA 0x00040C18 -#define DDRSS1_CTL_229_DATA 0x00000000 -#define DDRSS1_CTL_230_DATA 0x00000000 +#define DDRSS1_CTL_229_DATA 0xF000C000 +#define DDRSS1_CTL_230_DATA 0x0000F000 #define DDRSS1_CTL_231_DATA 0x00000000 #define DDRSS1_CTL_232_DATA 0x00000000 -#define DDRSS1_CTL_233_DATA 0x00000000 -#define DDRSS1_CTL_234_DATA 0x00000000 +#define DDRSS1_CTL_233_DATA 0xC0000000 +#define DDRSS1_CTL_234_DATA 0xF000F000 #define DDRSS1_CTL_235_DATA 0x00000000 #define DDRSS1_CTL_236_DATA 0x00000000 #define DDRSS1_CTL_237_DATA 0x00000000 -#define DDRSS1_CTL_238_DATA 0x00000000 -#define DDRSS1_CTL_239_DATA 0x00000000 +#define DDRSS1_CTL_238_DATA 0xF000C000 +#define DDRSS1_CTL_239_DATA 0x0000F000 #define DDRSS1_CTL_240_DATA 0x00000000 #define DDRSS1_CTL_241_DATA 0x00000000 #define DDRSS1_CTL_242_DATA 0x00030000 @@ -2468,7 +2489,7 @@ #define DDRSS1_CTL_264_DATA 0x00000040 #define DDRSS1_CTL_265_DATA 0x006B0003 #define DDRSS1_CTL_266_DATA 0x0100006B -#define DDRSS1_CTL_267_DATA 0x00000000 +#define DDRSS1_CTL_267_DATA 0x03030303 #define DDRSS1_CTL_268_DATA 0x00000000 #define DDRSS1_CTL_269_DATA 0x00000202 #define DDRSS1_CTL_270_DATA 0x00001FFF @@ -2492,14 +2513,14 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 #define DDRSS1_CTL_295_DATA 0x00000000 #define DDRSS1_CTL_296_DATA 0x00000000 -#define DDRSS1_CTL_297_DATA 0x00000000 -#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF #define DDRSS1_CTL_299_DATA 0x00000000 #define DDRSS1_CTL_300_DATA 0x00000000 #define DDRSS1_CTL_301_DATA 0x00000000 @@ -2520,7 +2541,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2590,30 +2611,30 @@ #define DDRSS1_CTL_386_DATA 0x00000000 #define DDRSS1_CTL_387_DATA 0x3A3A1B00 #define DDRSS1_CTL_388_DATA 0x000A0000 -#define DDRSS1_CTL_389_DATA 0x0000019C +#define DDRSS1_CTL_389_DATA 0x000000C6 #define DDRSS1_CTL_390_DATA 0x00000200 #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x000004D4 -#define DDRSS1_CTL_395_DATA 0x00001018 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 -#define DDRSS1_CTL_397_DATA 0x000040E6 +#define DDRSS1_CTL_397_DATA 0x0000206A #define DDRSS1_CTL_398_DATA 0x00000200 #define DDRSS1_CTL_399_DATA 0x00000200 #define DDRSS1_CTL_400_DATA 0x00000200 #define DDRSS1_CTL_401_DATA 0x00000200 -#define DDRSS1_CTL_402_DATA 0x0000C2B2 -#define DDRSS1_CTL_403_DATA 0x000288FC -#define DDRSS1_CTL_404_DATA 0x00000E15 -#define DDRSS1_CTL_405_DATA 0x000040E6 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 #define DDRSS1_CTL_408_DATA 0x00000200 #define DDRSS1_CTL_409_DATA 0x00000200 -#define DDRSS1_CTL_410_DATA 0x0000C2B2 -#define DDRSS1_CTL_411_DATA 0x000288FC -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2630,7 +2651,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2673,8 +2694,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2722,18 +2743,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2822,37 +2843,37 @@ #define DDRSS1_PI_158_DATA 0x00000000 #define DDRSS1_PI_159_DATA 0x00000401 #define DDRSS1_PI_160_DATA 0x00000000 -#define DDRSS1_PI_161_DATA 0x00010000 -#define DDRSS1_PI_162_DATA 0x00000000 -#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x000000CE +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 #define DDRSS1_PI_171_DATA 0x0000032B -#define DDRSS1_PI_172_DATA 0x00002073 +#define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B -#define DDRSS1_PI_174_DATA 0x04002073 +#define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2860,8 +2881,8 @@ #define DDRSS1_PI_196_DATA 0x02170100 #define DDRSS1_PI_197_DATA 0x01000217 #define DDRSS1_PI_198_DATA 0x02170217 -#define DDRSS1_PI_199_DATA 0x32103200 -#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B #define DDRSS1_PI_201_DATA 0x0A070601 #define DDRSS1_PI_202_DATA 0x1F130A0D #define DDRSS1_PI_203_DATA 0x1F130A14 @@ -2873,29 +2894,29 @@ #define DDRSS1_PI_209_DATA 0x00240216 #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 -#define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 -#define DDRSS1_PI_218_DATA 0x04010504 -#define DDRSS1_PI_219_DATA 0x040006C9 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A #define DDRSS1_PI_222_DATA 0x00002918 -#define DDRSS1_PI_223_DATA 0x6001071C +#define DDRSS1_PI_223_DATA 0x6000838E #define DDRSS1_PI_224_DATA 0x1E202008 #define DDRSS1_PI_225_DATA 0x2C311116 #define DDRSS1_PI_226_DATA 0x00002918 -#define DDRSS1_PI_227_DATA 0x6001071C +#define DDRSS1_PI_227_DATA 0x6000838E #define DDRSS1_PI_228_DATA 0x1E202008 -#define DDRSS1_PI_229_DATA 0x00019C16 -#define DDRSS1_PI_230_DATA 0x00001018 -#define DDRSS1_PI_231_DATA 0x000040E6 -#define DDRSS1_PI_232_DATA 0x000288FC -#define DDRSS1_PI_233_DATA 0x000040E6 -#define DDRSS1_PI_234_DATA 0x000288FC +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 #define DDRSS1_PI_235_DATA 0x033B0016 #define DDRSS1_PI_236_DATA 0x0303033B #define DDRSS1_PI_237_DATA 0x002AF803 @@ -2936,29 +2957,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x56333FF4 +#define DDRSS1_PI_277_DATA 0x36F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x56333FF4 +#define DDRSS1_PI_279_DATA 0x36F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x56333FF4 +#define DDRSS1_PI_283_DATA 0x36F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x56333FF4 +#define DDRSS1_PI_285_DATA 0x36F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x56333FF4 +#define DDRSS1_PI_289_DATA 0x36F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x56333FF4 +#define DDRSS1_PI_291_DATA 0x36F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x56333FF4 +#define DDRSS1_PI_295_DATA 0x36F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x56333FF4 +#define DDRSS1_PI_297_DATA 0x36F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2974,7 +2995,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2993,8 +3014,8 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F -#define DDRSS1_PHY_32_DATA 0x10200000 +#define DDRSS1_PHY_31_DATA 0x00000F08 +#define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 #define DDRSS1_PHY_35_DATA 0x00000000 @@ -3062,9 +3083,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3098,7 +3119,7 @@ #define DDRSS1_PHY_133_DATA 0x00000000 #define DDRSS1_PHY_134_DATA 0x00080200 #define DDRSS1_PHY_135_DATA 0x00000000 -#define DDRSS1_PHY_136_DATA 0x20202000 +#define DDRSS1_PHY_136_DATA 0x20202020 #define DDRSS1_PHY_137_DATA 0x20202020 #define DDRSS1_PHY_138_DATA 0xF0F02020 #define DDRSS1_PHY_139_DATA 0x00000000 @@ -3230,7 +3251,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3249,8 +3270,8 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F -#define DDRSS1_PHY_288_DATA 0x10200000 +#define DDRSS1_PHY_287_DATA 0x00000F08 +#define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 #define DDRSS1_PHY_291_DATA 0x00000000 @@ -3318,9 +3339,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3354,7 +3375,7 @@ #define DDRSS1_PHY_389_DATA 0x00000000 #define DDRSS1_PHY_390_DATA 0x00080200 #define DDRSS1_PHY_391_DATA 0x00000000 -#define DDRSS1_PHY_392_DATA 0x20202000 +#define DDRSS1_PHY_392_DATA 0x20202020 #define DDRSS1_PHY_393_DATA 0x20202020 #define DDRSS1_PHY_394_DATA 0xF0F02020 #define DDRSS1_PHY_395_DATA 0x00000000 @@ -3486,7 +3507,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3505,8 +3526,8 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F -#define DDRSS1_PHY_544_DATA 0x10200000 +#define DDRSS1_PHY_543_DATA 0x00000F08 +#define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 #define DDRSS1_PHY_547_DATA 0x00000000 @@ -3574,9 +3595,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3610,7 +3631,7 @@ #define DDRSS1_PHY_645_DATA 0x00000000 #define DDRSS1_PHY_646_DATA 0x00080200 #define DDRSS1_PHY_647_DATA 0x00000000 -#define DDRSS1_PHY_648_DATA 0x20202000 +#define DDRSS1_PHY_648_DATA 0x20202020 #define DDRSS1_PHY_649_DATA 0x20202020 #define DDRSS1_PHY_650_DATA 0xF0F02020 #define DDRSS1_PHY_651_DATA 0x00000000 @@ -3742,7 +3763,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3761,8 +3782,8 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F -#define DDRSS1_PHY_800_DATA 0x10200000 +#define DDRSS1_PHY_799_DATA 0x00000F08 +#define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 #define DDRSS1_PHY_803_DATA 0x00000000 @@ -3830,9 +3851,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -3866,7 +3887,7 @@ #define DDRSS1_PHY_901_DATA 0x00000000 #define DDRSS1_PHY_902_DATA 0x00080200 #define DDRSS1_PHY_903_DATA 0x00000000 -#define DDRSS1_PHY_904_DATA 0x20202000 +#define DDRSS1_PHY_904_DATA 0x20202020 #define DDRSS1_PHY_905_DATA 0x20202020 #define DDRSS1_PHY_906_DATA 0xF0F02020 #define DDRSS1_PHY_907_DATA 0x00000000 @@ -4017,7 +4038,7 @@ #define DDRSS1_PHY_1052_DATA 0x00000033 #define DDRSS1_PHY_1053_DATA 0x00543210 #define DDRSS1_PHY_1054_DATA 0x003F0000 -#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1055_DATA 0x000F3F3F #define DDRSS1_PHY_1056_DATA 0x20202003 #define DDRSS1_PHY_1057_DATA 0x00202020 #define DDRSS1_PHY_1058_DATA 0x20008008 @@ -4265,14 +4286,14 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 #define DDRSS1_PHY_1307_DATA 0x01200F02 #define DDRSS1_PHY_1308_DATA 0x00194280 #define DDRSS1_PHY_1309_DATA 0x00000004 -#define DDRSS1_PHY_1310_DATA 0x00052000 +#define DDRSS1_PHY_1310_DATA 0x00042000 #define DDRSS1_PHY_1311_DATA 0x00000000 #define DDRSS1_PHY_1312_DATA 0x00000000 #define DDRSS1_PHY_1313_DATA 0x00000000 @@ -4359,7 +4380,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4385,3 +4406,5 @@ #define DDRSS1_PHY_1420_DATA 0x3F0DFF11 #define DDRSS1_PHY_1421_DATA 0x01FF00F0 #define DDRSS1_PHY_1422_DATA 0x20040006 + + diff --git a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi index a64d19b05f3..2cd21efbf93 100644 --- a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi @@ -1,10 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 15:02:20 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -12,9 +25,18 @@ #define MULTI_DDR_CFG_INTRLV_GRAN 0 #define MULTI_DDR_CFG_INTRLV_SIZE 11 #define MULTI_DDR_CFG_ECC_ENABLE 0 -#define MULTI_DDR_CFG_HYBRID_SELECT 0 +#define MULTI_DDR_CFG_HYBRID_SELECT 2 #define MULTI_DDR_CFG_EMIFS_ACTIVE 3 +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000003 +#define DDR_REG1_SIZE_LSB 0x80000000 + + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -35,7 +57,7 @@ #define DDRSS0_CTL_17_DATA 0x00000005 #define DDRSS0_CTL_18_DATA 0x000010A9 #define DDRSS0_CTL_19_DATA 0x01010000 -#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_20_DATA 0x01011001 #define DDRSS0_CTL_21_DATA 0x02010000 #define DDRSS0_CTL_22_DATA 0x00020100 #define DDRSS0_CTL_23_DATA 0x0000000B @@ -50,7 +72,7 @@ #define DDRSS0_CTL_32_DATA 0x00000000 #define DDRSS0_CTL_33_DATA 0x00000000 #define DDRSS0_CTL_34_DATA 0x040C0000 -#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_35_DATA 0x12501250 #define DDRSS0_CTL_36_DATA 0x00050804 #define DDRSS0_CTL_37_DATA 0x09040008 #define DDRSS0_CTL_38_DATA 0x15000204 @@ -59,33 +81,33 @@ #define DDRSS0_CTL_41_DATA 0x1760008B #define DDRSS0_CTL_42_DATA 0x2000422B #define DDRSS0_CTL_43_DATA 0x000A0A09 -#define DDRSS0_CTL_44_DATA 0x0400078A +#define DDRSS0_CTL_44_DATA 0x040003C5 #define DDRSS0_CTL_45_DATA 0x1E161104 -#define DDRSS0_CTL_46_DATA 0x10012458 +#define DDRSS0_CTL_46_DATA 0x1000922C #define DDRSS0_CTL_47_DATA 0x1E161110 -#define DDRSS0_CTL_48_DATA 0x10012458 +#define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 -#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_50_DATA 0x2C060500 #define DDRSS0_CTL_51_DATA 0x08292C29 #define DDRSS0_CTL_52_DATA 0x14000E0A #define DDRSS0_CTL_53_DATA 0x04010A0A #define DDRSS0_CTL_54_DATA 0x01010004 -#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_55_DATA 0x0454540A #define DDRSS0_CTL_56_DATA 0x04313104 #define DDRSS0_CTL_57_DATA 0x00003131 #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x000000CE +#define DDRSS0_CTL_61_DATA 0x00000068 #define DDRSS0_CTL_62_DATA 0x0000032B -#define DDRSS0_CTL_63_DATA 0x00002073 +#define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B -#define DDRSS0_CTL_65_DATA 0x00002073 +#define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 -#define DDRSS0_CTL_68_DATA 0x00CB0012 -#define DDRSS0_CTL_69_DATA 0x00CB0408 -#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 #define DDRSS0_CTL_71_DATA 0x00120103 #define DDRSS0_CTL_72_DATA 0x00100005 #define DDRSS0_CTL_73_DATA 0x2F080010 @@ -117,27 +139,27 @@ #define DDRSS0_CTL_99_DATA 0x00000000 #define DDRSS0_CTL_100_DATA 0x00040005 #define DDRSS0_CTL_101_DATA 0x00000000 -#define DDRSS0_CTL_102_DATA 0x00003380 -#define DDRSS0_CTL_103_DATA 0x00003380 -#define DDRSS0_CTL_104_DATA 0x00003380 -#define DDRSS0_CTL_105_DATA 0x00003380 -#define DDRSS0_CTL_106_DATA 0x00003380 +#define DDRSS0_CTL_102_DATA 0x000018C0 +#define DDRSS0_CTL_103_DATA 0x000018C0 +#define DDRSS0_CTL_104_DATA 0x000018C0 +#define DDRSS0_CTL_105_DATA 0x000018C0 +#define DDRSS0_CTL_106_DATA 0x000018C0 #define DDRSS0_CTL_107_DATA 0x00000000 -#define DDRSS0_CTL_108_DATA 0x000005A2 -#define DDRSS0_CTL_109_DATA 0x00081CC0 -#define DDRSS0_CTL_110_DATA 0x00081CC0 -#define DDRSS0_CTL_111_DATA 0x00081CC0 -#define DDRSS0_CTL_112_DATA 0x00081CC0 -#define DDRSS0_CTL_113_DATA 0x00081CC0 +#define DDRSS0_CTL_108_DATA 0x000002B5 +#define DDRSS0_CTL_109_DATA 0x00040D40 +#define DDRSS0_CTL_110_DATA 0x00040D40 +#define DDRSS0_CTL_111_DATA 0x00040D40 +#define DDRSS0_CTL_112_DATA 0x00040D40 +#define DDRSS0_CTL_113_DATA 0x00040D40 #define DDRSS0_CTL_114_DATA 0x00000000 -#define DDRSS0_CTL_115_DATA 0x0000E325 -#define DDRSS0_CTL_116_DATA 0x00081CC0 -#define DDRSS0_CTL_117_DATA 0x00081CC0 -#define DDRSS0_CTL_118_DATA 0x00081CC0 -#define DDRSS0_CTL_119_DATA 0x00081CC0 -#define DDRSS0_CTL_120_DATA 0x00081CC0 +#define DDRSS0_CTL_115_DATA 0x00007173 +#define DDRSS0_CTL_116_DATA 0x00040D40 +#define DDRSS0_CTL_117_DATA 0x00040D40 +#define DDRSS0_CTL_118_DATA 0x00040D40 +#define DDRSS0_CTL_119_DATA 0x00040D40 +#define DDRSS0_CTL_120_DATA 0x00040D40 #define DDRSS0_CTL_121_DATA 0x00000000 -#define DDRSS0_CTL_122_DATA 0x0000E325 +#define DDRSS0_CTL_122_DATA 0x00007173 #define DDRSS0_CTL_123_DATA 0x00000000 #define DDRSS0_CTL_124_DATA 0x00000000 #define DDRSS0_CTL_125_DATA 0x00000000 @@ -191,22 +213,22 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 #define DDRSS0_CTL_178_DATA 0x35000000 #define DDRSS0_CTL_179_DATA 0x27270035 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 #define DDRSS0_CTL_185_DATA 0x00000000 #define DDRSS0_CTL_186_DATA 0x00353500 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 #define DDRSS0_CTL_190_DATA 0x00000020 -#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_191_DATA 0x01000000 #define DDRSS0_CTL_192_DATA 0x00000001 #define DDRSS0_CTL_193_DATA 0x00000000 #define DDRSS0_CTL_194_DATA 0x01000000 @@ -306,14 +328,14 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00010101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 #define DDRSS0_CTL_295_DATA 0x00000000 #define DDRSS0_CTL_296_DATA 0x00000000 -#define DDRSS0_CTL_297_DATA 0x00000000 -#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF #define DDRSS0_CTL_299_DATA 0x00000000 #define DDRSS0_CTL_300_DATA 0x00000000 #define DDRSS0_CTL_301_DATA 0x00000000 @@ -334,7 +356,7 @@ #define DDRSS0_CTL_316_DATA 0x01010001 #define DDRSS0_CTL_317_DATA 0x00010101 #define DDRSS0_CTL_318_DATA 0x050A0A03 -#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_319_DATA 0x10082323 #define DDRSS0_CTL_320_DATA 0x00090310 #define DDRSS0_CTL_321_DATA 0x0B0C030F #define DDRSS0_CTL_322_DATA 0x0B0C0306 @@ -404,30 +426,30 @@ #define DDRSS0_CTL_386_DATA 0x00000000 #define DDRSS0_CTL_387_DATA 0x3A3A1B00 #define DDRSS0_CTL_388_DATA 0x000A0000 -#define DDRSS0_CTL_389_DATA 0x0000019C +#define DDRSS0_CTL_389_DATA 0x000000C6 #define DDRSS0_CTL_390_DATA 0x00000200 #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x000004D4 -#define DDRSS0_CTL_395_DATA 0x00001018 +#define DDRSS0_CTL_394_DATA 0x00000270 +#define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 -#define DDRSS0_CTL_397_DATA 0x000040E6 +#define DDRSS0_CTL_397_DATA 0x0000206A #define DDRSS0_CTL_398_DATA 0x00000200 #define DDRSS0_CTL_399_DATA 0x00000200 #define DDRSS0_CTL_400_DATA 0x00000200 #define DDRSS0_CTL_401_DATA 0x00000200 -#define DDRSS0_CTL_402_DATA 0x0000C2B2 -#define DDRSS0_CTL_403_DATA 0x000288FC -#define DDRSS0_CTL_404_DATA 0x00000E15 -#define DDRSS0_CTL_405_DATA 0x000040E6 +#define DDRSS0_CTL_402_DATA 0x0000613E +#define DDRSS0_CTL_403_DATA 0x00014424 +#define DDRSS0_CTL_404_DATA 0x00000E19 +#define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 #define DDRSS0_CTL_408_DATA 0x00000200 #define DDRSS0_CTL_409_DATA 0x00000200 -#define DDRSS0_CTL_410_DATA 0x0000C2B2 -#define DDRSS0_CTL_411_DATA 0x000288FC -#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_410_DATA 0x0000613E +#define DDRSS0_CTL_411_DATA 0x00014424 +#define DDRSS0_CTL_412_DATA 0x02020E19 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 #define DDRSS0_CTL_415_DATA 0x00000000 @@ -444,7 +466,7 @@ #define DDRSS0_CTL_426_DATA 0x00000000 #define DDRSS0_CTL_427_DATA 0x02000000 #define DDRSS0_CTL_428_DATA 0x01000404 -#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_429_DATA 0x0B220B22 #define DDRSS0_CTL_430_DATA 0x00000105 #define DDRSS0_CTL_431_DATA 0x00010101 #define DDRSS0_CTL_432_DATA 0x00010101 @@ -487,8 +509,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -536,18 +558,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 #define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_67_DATA 0x0002020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -636,37 +658,37 @@ #define DDRSS0_PI_158_DATA 0x00000000 #define DDRSS0_PI_159_DATA 0x00000401 #define DDRSS0_PI_160_DATA 0x00000000 -#define DDRSS0_PI_161_DATA 0x00010000 -#define DDRSS0_PI_162_DATA 0x00000000 -#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 #define DDRSS0_PI_164_DATA 0x00000034 -#define DDRSS0_PI_165_DATA 0x00000064 -#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 #define DDRSS0_PI_167_DATA 0x02000200 -#define DDRSS0_PI_168_DATA 0x48120C04 -#define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x000000CE +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 #define DDRSS0_PI_171_DATA 0x0000032B -#define DDRSS0_PI_172_DATA 0x00002073 +#define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B -#define DDRSS0_PI_174_DATA 0x04002073 +#define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 -#define DDRSS0_PI_185_DATA 0x15040000 -#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 #define DDRSS0_PI_187_DATA 0x00040402 #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -674,8 +696,8 @@ #define DDRSS0_PI_196_DATA 0x02170100 #define DDRSS0_PI_197_DATA 0x01000217 #define DDRSS0_PI_198_DATA 0x02170217 -#define DDRSS0_PI_199_DATA 0x32103200 -#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B #define DDRSS0_PI_201_DATA 0x0A070601 #define DDRSS0_PI_202_DATA 0x1F130A0D #define DDRSS0_PI_203_DATA 0x1F130A14 @@ -687,29 +709,29 @@ #define DDRSS0_PI_209_DATA 0x00240216 #define DDRSS0_PI_210_DATA 0x00110216 #define DDRSS0_PI_211_DATA 0x32000056 -#define DDRSS0_PI_212_DATA 0x00000301 -#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 -#define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 -#define DDRSS0_PI_218_DATA 0x04010504 -#define DDRSS0_PI_219_DATA 0x040006C9 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 +#define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A #define DDRSS0_PI_222_DATA 0x00002918 -#define DDRSS0_PI_223_DATA 0x6001071C +#define DDRSS0_PI_223_DATA 0x6000838E #define DDRSS0_PI_224_DATA 0x1E202008 #define DDRSS0_PI_225_DATA 0x2C311116 #define DDRSS0_PI_226_DATA 0x00002918 -#define DDRSS0_PI_227_DATA 0x6001071C +#define DDRSS0_PI_227_DATA 0x6000838E #define DDRSS0_PI_228_DATA 0x1E202008 -#define DDRSS0_PI_229_DATA 0x00019C16 -#define DDRSS0_PI_230_DATA 0x00001018 -#define DDRSS0_PI_231_DATA 0x000040E6 -#define DDRSS0_PI_232_DATA 0x000288FC -#define DDRSS0_PI_233_DATA 0x000040E6 -#define DDRSS0_PI_234_DATA 0x000288FC +#define DDRSS0_PI_229_DATA 0x0000C616 +#define DDRSS0_PI_230_DATA 0x000007BC +#define DDRSS0_PI_231_DATA 0x0000206A +#define DDRSS0_PI_232_DATA 0x00014424 +#define DDRSS0_PI_233_DATA 0x0000206A +#define DDRSS0_PI_234_DATA 0x00014424 #define DDRSS0_PI_235_DATA 0x033B0016 #define DDRSS0_PI_236_DATA 0x0303033B #define DDRSS0_PI_237_DATA 0x002AF803 @@ -750,29 +772,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00F30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x35333FF4 +#define DDRSS0_PI_277_DATA 0x35F33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x35333FF4 +#define DDRSS0_PI_279_DATA 0x35F33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00F30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x35333FF4 +#define DDRSS0_PI_283_DATA 0x35F33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x35333FF4 +#define DDRSS0_PI_285_DATA 0x35F33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00F30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x35333FF4 +#define DDRSS0_PI_289_DATA 0x35F33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x35333FF4 +#define DDRSS0_PI_291_DATA 0x35F33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00F30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x35333FF4 +#define DDRSS0_PI_295_DATA 0x35F33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x35333FF4 +#define DDRSS0_PI_297_DATA 0x35F33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -788,7 +810,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -807,7 +829,7 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_31_DATA 0x00000F08 #define DDRSS0_PHY_32_DATA 0x10400000 #define DDRSS0_PHY_33_DATA 0x0C002006 #define DDRSS0_PHY_34_DATA 0x00000000 @@ -876,9 +898,9 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 -#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 #define DDRSS0_PHY_103_DATA 0x10001000 #define DDRSS0_PHY_104_DATA 0x0C083E42 #define DDRSS0_PHY_105_DATA 0x0F0C3701 @@ -1044,7 +1066,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1063,7 +1085,7 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_287_DATA 0x00000F08 #define DDRSS0_PHY_288_DATA 0x10400000 #define DDRSS0_PHY_289_DATA 0x0C002006 #define DDRSS0_PHY_290_DATA 0x00000000 @@ -1132,9 +1154,9 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 -#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 #define DDRSS0_PHY_359_DATA 0x10001000 #define DDRSS0_PHY_360_DATA 0x0C083E42 #define DDRSS0_PHY_361_DATA 0x0F0C3701 @@ -1300,7 +1322,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1319,7 +1341,7 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_543_DATA 0x00000F08 #define DDRSS0_PHY_544_DATA 0x10400000 #define DDRSS0_PHY_545_DATA 0x0C002006 #define DDRSS0_PHY_546_DATA 0x00000000 @@ -1388,9 +1410,9 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 -#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 #define DDRSS0_PHY_615_DATA 0x10001000 #define DDRSS0_PHY_616_DATA 0x0C083E42 #define DDRSS0_PHY_617_DATA 0x0F0C3701 @@ -1556,7 +1578,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1575,7 +1597,7 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_799_DATA 0x00000F08 #define DDRSS0_PHY_800_DATA 0x10400000 #define DDRSS0_PHY_801_DATA 0x0C002006 #define DDRSS0_PHY_802_DATA 0x00000000 @@ -1644,9 +1666,9 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 -#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 #define DDRSS0_PHY_871_DATA 0x10001000 #define DDRSS0_PHY_872_DATA 0x0C083E42 #define DDRSS0_PHY_873_DATA 0x0F0C3701 @@ -1831,7 +1853,7 @@ #define DDRSS0_PHY_1052_DATA 0x00000033 #define DDRSS0_PHY_1053_DATA 0x00543210 #define DDRSS0_PHY_1054_DATA 0x003F0000 -#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1055_DATA 0x000F3F3F #define DDRSS0_PHY_1056_DATA 0x20202003 #define DDRSS0_PHY_1057_DATA 0x00202020 #define DDRSS0_PHY_1058_DATA 0x20008008 @@ -2079,7 +2101,7 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 @@ -2173,7 +2195,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2220,7 +2242,7 @@ #define DDRSS1_CTL_17_DATA 0x00000005 #define DDRSS1_CTL_18_DATA 0x000010A9 #define DDRSS1_CTL_19_DATA 0x01010000 -#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_20_DATA 0x01011001 #define DDRSS1_CTL_21_DATA 0x02010000 #define DDRSS1_CTL_22_DATA 0x00020100 #define DDRSS1_CTL_23_DATA 0x0000000B @@ -2235,7 +2257,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2244,33 +2266,33 @@ #define DDRSS1_CTL_41_DATA 0x1760008B #define DDRSS1_CTL_42_DATA 0x2000422B #define DDRSS1_CTL_43_DATA 0x000A0A09 -#define DDRSS1_CTL_44_DATA 0x0400078A +#define DDRSS1_CTL_44_DATA 0x040003C5 #define DDRSS1_CTL_45_DATA 0x1E161104 -#define DDRSS1_CTL_46_DATA 0x10012458 +#define DDRSS1_CTL_46_DATA 0x1000922C #define DDRSS1_CTL_47_DATA 0x1E161110 -#define DDRSS1_CTL_48_DATA 0x10012458 +#define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 -#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_50_DATA 0x2C060500 #define DDRSS1_CTL_51_DATA 0x08292C29 #define DDRSS1_CTL_52_DATA 0x14000E0A #define DDRSS1_CTL_53_DATA 0x04010A0A #define DDRSS1_CTL_54_DATA 0x01010004 -#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_55_DATA 0x0454540A #define DDRSS1_CTL_56_DATA 0x04313104 #define DDRSS1_CTL_57_DATA 0x00003131 #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x000000CE +#define DDRSS1_CTL_61_DATA 0x00000068 #define DDRSS1_CTL_62_DATA 0x0000032B -#define DDRSS1_CTL_63_DATA 0x00002073 +#define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B -#define DDRSS1_CTL_65_DATA 0x00002073 +#define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 -#define DDRSS1_CTL_68_DATA 0x00CB0012 -#define DDRSS1_CTL_69_DATA 0x00CB0408 -#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 #define DDRSS1_CTL_71_DATA 0x00120103 #define DDRSS1_CTL_72_DATA 0x00100005 #define DDRSS1_CTL_73_DATA 0x2F080010 @@ -2302,27 +2324,27 @@ #define DDRSS1_CTL_99_DATA 0x00000000 #define DDRSS1_CTL_100_DATA 0x00040005 #define DDRSS1_CTL_101_DATA 0x00000000 -#define DDRSS1_CTL_102_DATA 0x00003380 -#define DDRSS1_CTL_103_DATA 0x00003380 -#define DDRSS1_CTL_104_DATA 0x00003380 -#define DDRSS1_CTL_105_DATA 0x00003380 -#define DDRSS1_CTL_106_DATA 0x00003380 +#define DDRSS1_CTL_102_DATA 0x000018C0 +#define DDRSS1_CTL_103_DATA 0x000018C0 +#define DDRSS1_CTL_104_DATA 0x000018C0 +#define DDRSS1_CTL_105_DATA 0x000018C0 +#define DDRSS1_CTL_106_DATA 0x000018C0 #define DDRSS1_CTL_107_DATA 0x00000000 -#define DDRSS1_CTL_108_DATA 0x000005A2 -#define DDRSS1_CTL_109_DATA 0x00081CC0 -#define DDRSS1_CTL_110_DATA 0x00081CC0 -#define DDRSS1_CTL_111_DATA 0x00081CC0 -#define DDRSS1_CTL_112_DATA 0x00081CC0 -#define DDRSS1_CTL_113_DATA 0x00081CC0 +#define DDRSS1_CTL_108_DATA 0x000002B5 +#define DDRSS1_CTL_109_DATA 0x00040D40 +#define DDRSS1_CTL_110_DATA 0x00040D40 +#define DDRSS1_CTL_111_DATA 0x00040D40 +#define DDRSS1_CTL_112_DATA 0x00040D40 +#define DDRSS1_CTL_113_DATA 0x00040D40 #define DDRSS1_CTL_114_DATA 0x00000000 -#define DDRSS1_CTL_115_DATA 0x0000E325 -#define DDRSS1_CTL_116_DATA 0x00081CC0 -#define DDRSS1_CTL_117_DATA 0x00081CC0 -#define DDRSS1_CTL_118_DATA 0x00081CC0 -#define DDRSS1_CTL_119_DATA 0x00081CC0 -#define DDRSS1_CTL_120_DATA 0x00081CC0 +#define DDRSS1_CTL_115_DATA 0x00007173 +#define DDRSS1_CTL_116_DATA 0x00040D40 +#define DDRSS1_CTL_117_DATA 0x00040D40 +#define DDRSS1_CTL_118_DATA 0x00040D40 +#define DDRSS1_CTL_119_DATA 0x00040D40 +#define DDRSS1_CTL_120_DATA 0x00040D40 #define DDRSS1_CTL_121_DATA 0x00000000 -#define DDRSS1_CTL_122_DATA 0x0000E325 +#define DDRSS1_CTL_122_DATA 0x00007173 #define DDRSS1_CTL_123_DATA 0x00000000 #define DDRSS1_CTL_124_DATA 0x00000000 #define DDRSS1_CTL_125_DATA 0x00000000 @@ -2376,22 +2398,22 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 #define DDRSS1_CTL_178_DATA 0x35000000 #define DDRSS1_CTL_179_DATA 0x27270035 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 #define DDRSS1_CTL_186_DATA 0x00353500 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 #define DDRSS1_CTL_190_DATA 0x00000020 -#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_191_DATA 0x01000000 #define DDRSS1_CTL_192_DATA 0x00000001 #define DDRSS1_CTL_193_DATA 0x00000000 #define DDRSS1_CTL_194_DATA 0x01000000 @@ -2491,14 +2513,14 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 #define DDRSS1_CTL_295_DATA 0x00000000 #define DDRSS1_CTL_296_DATA 0x00000000 -#define DDRSS1_CTL_297_DATA 0x00000000 -#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF #define DDRSS1_CTL_299_DATA 0x00000000 #define DDRSS1_CTL_300_DATA 0x00000000 #define DDRSS1_CTL_301_DATA 0x00000000 @@ -2519,7 +2541,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2589,30 +2611,30 @@ #define DDRSS1_CTL_386_DATA 0x00000000 #define DDRSS1_CTL_387_DATA 0x3A3A1B00 #define DDRSS1_CTL_388_DATA 0x000A0000 -#define DDRSS1_CTL_389_DATA 0x0000019C +#define DDRSS1_CTL_389_DATA 0x000000C6 #define DDRSS1_CTL_390_DATA 0x00000200 #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x000004D4 -#define DDRSS1_CTL_395_DATA 0x00001018 +#define DDRSS1_CTL_394_DATA 0x00000270 +#define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 -#define DDRSS1_CTL_397_DATA 0x000040E6 +#define DDRSS1_CTL_397_DATA 0x0000206A #define DDRSS1_CTL_398_DATA 0x00000200 #define DDRSS1_CTL_399_DATA 0x00000200 #define DDRSS1_CTL_400_DATA 0x00000200 #define DDRSS1_CTL_401_DATA 0x00000200 -#define DDRSS1_CTL_402_DATA 0x0000C2B2 -#define DDRSS1_CTL_403_DATA 0x000288FC -#define DDRSS1_CTL_404_DATA 0x00000E15 -#define DDRSS1_CTL_405_DATA 0x000040E6 +#define DDRSS1_CTL_402_DATA 0x0000613E +#define DDRSS1_CTL_403_DATA 0x00014424 +#define DDRSS1_CTL_404_DATA 0x00000E19 +#define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 #define DDRSS1_CTL_408_DATA 0x00000200 #define DDRSS1_CTL_409_DATA 0x00000200 -#define DDRSS1_CTL_410_DATA 0x0000C2B2 -#define DDRSS1_CTL_411_DATA 0x000288FC -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_410_DATA 0x0000613E +#define DDRSS1_CTL_411_DATA 0x00014424 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2629,7 +2651,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2672,8 +2694,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2721,18 +2743,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2821,37 +2843,37 @@ #define DDRSS1_PI_158_DATA 0x00000000 #define DDRSS1_PI_159_DATA 0x00000401 #define DDRSS1_PI_160_DATA 0x00000000 -#define DDRSS1_PI_161_DATA 0x00010000 -#define DDRSS1_PI_162_DATA 0x00000000 -#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x000000CE +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 #define DDRSS1_PI_171_DATA 0x0000032B -#define DDRSS1_PI_172_DATA 0x00002073 +#define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B -#define DDRSS1_PI_174_DATA 0x04002073 +#define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2859,8 +2881,8 @@ #define DDRSS1_PI_196_DATA 0x02170100 #define DDRSS1_PI_197_DATA 0x01000217 #define DDRSS1_PI_198_DATA 0x02170217 -#define DDRSS1_PI_199_DATA 0x32103200 -#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B #define DDRSS1_PI_201_DATA 0x0A070601 #define DDRSS1_PI_202_DATA 0x1F130A0D #define DDRSS1_PI_203_DATA 0x1F130A14 @@ -2872,29 +2894,29 @@ #define DDRSS1_PI_209_DATA 0x00240216 #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 -#define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 -#define DDRSS1_PI_218_DATA 0x04010504 -#define DDRSS1_PI_219_DATA 0x040006C9 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 +#define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A #define DDRSS1_PI_222_DATA 0x00002918 -#define DDRSS1_PI_223_DATA 0x6001071C +#define DDRSS1_PI_223_DATA 0x6000838E #define DDRSS1_PI_224_DATA 0x1E202008 #define DDRSS1_PI_225_DATA 0x2C311116 #define DDRSS1_PI_226_DATA 0x00002918 -#define DDRSS1_PI_227_DATA 0x6001071C +#define DDRSS1_PI_227_DATA 0x6000838E #define DDRSS1_PI_228_DATA 0x1E202008 -#define DDRSS1_PI_229_DATA 0x00019C16 -#define DDRSS1_PI_230_DATA 0x00001018 -#define DDRSS1_PI_231_DATA 0x000040E6 -#define DDRSS1_PI_232_DATA 0x000288FC -#define DDRSS1_PI_233_DATA 0x000040E6 -#define DDRSS1_PI_234_DATA 0x000288FC +#define DDRSS1_PI_229_DATA 0x0000C616 +#define DDRSS1_PI_230_DATA 0x000007BC +#define DDRSS1_PI_231_DATA 0x0000206A +#define DDRSS1_PI_232_DATA 0x00014424 +#define DDRSS1_PI_233_DATA 0x0000206A +#define DDRSS1_PI_234_DATA 0x00014424 #define DDRSS1_PI_235_DATA 0x033B0016 #define DDRSS1_PI_236_DATA 0x0303033B #define DDRSS1_PI_237_DATA 0x002AF803 @@ -2935,29 +2957,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x35333FF4 +#define DDRSS1_PI_277_DATA 0x35F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x35333FF4 +#define DDRSS1_PI_279_DATA 0x35F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x35333FF4 +#define DDRSS1_PI_283_DATA 0x35F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x35333FF4 +#define DDRSS1_PI_285_DATA 0x35F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x35333FF4 +#define DDRSS1_PI_289_DATA 0x35F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x35333FF4 +#define DDRSS1_PI_291_DATA 0x35F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x35333FF4 +#define DDRSS1_PI_295_DATA 0x35F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x35333FF4 +#define DDRSS1_PI_297_DATA 0x35F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2973,7 +2995,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2992,7 +3014,7 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_31_DATA 0x00000F08 #define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 @@ -3061,9 +3083,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3229,7 +3251,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3248,7 +3270,7 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_287_DATA 0x00000F08 #define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 @@ -3317,9 +3339,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3485,7 +3507,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3504,7 +3526,7 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_543_DATA 0x00000F08 #define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 @@ -3573,9 +3595,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3741,7 +3763,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3760,7 +3782,7 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_799_DATA 0x00000F08 #define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 @@ -3829,9 +3851,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -4016,7 +4038,7 @@ #define DDRSS1_PHY_1052_DATA 0x00000033 #define DDRSS1_PHY_1053_DATA 0x00543210 #define DDRSS1_PHY_1054_DATA 0x003F0000 -#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1055_DATA 0x000F3F3F #define DDRSS1_PHY_1056_DATA 0x20202003 #define DDRSS1_PHY_1057_DATA 0x00202020 #define DDRSS1_PHY_1058_DATA 0x20008008 @@ -4264,7 +4286,7 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 @@ -4358,7 +4380,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4385,4372 +4407,4 @@ #define DDRSS1_PHY_1421_DATA 0x01FF00F0 #define DDRSS1_PHY_1422_DATA 0x20040006 -#define DDRSS2_CTL_00_DATA 0x00000B00 -#define DDRSS2_CTL_01_DATA 0x00000000 -#define DDRSS2_CTL_02_DATA 0x00000000 -#define DDRSS2_CTL_03_DATA 0x00000000 -#define DDRSS2_CTL_04_DATA 0x00000000 -#define DDRSS2_CTL_05_DATA 0x00000000 -#define DDRSS2_CTL_06_DATA 0x00000000 -#define DDRSS2_CTL_07_DATA 0x00002AF8 -#define DDRSS2_CTL_08_DATA 0x0001ADAF -#define DDRSS2_CTL_09_DATA 0x00000005 -#define DDRSS2_CTL_10_DATA 0x0000006E -#define DDRSS2_CTL_11_DATA 0x000681C8 -#define DDRSS2_CTL_12_DATA 0x004111C9 -#define DDRSS2_CTL_13_DATA 0x00000005 -#define DDRSS2_CTL_14_DATA 0x000010A9 -#define DDRSS2_CTL_15_DATA 0x000681C8 -#define DDRSS2_CTL_16_DATA 0x004111C9 -#define DDRSS2_CTL_17_DATA 0x00000005 -#define DDRSS2_CTL_18_DATA 0x000010A9 -#define DDRSS2_CTL_19_DATA 0x01010000 -#define DDRSS2_CTL_20_DATA 0x02011001 -#define DDRSS2_CTL_21_DATA 0x02010000 -#define DDRSS2_CTL_22_DATA 0x00020100 -#define DDRSS2_CTL_23_DATA 0x0000000B -#define DDRSS2_CTL_24_DATA 0x0000001C -#define DDRSS2_CTL_25_DATA 0x00000000 -#define DDRSS2_CTL_26_DATA 0x00000000 -#define DDRSS2_CTL_27_DATA 0x03020200 -#define DDRSS2_CTL_28_DATA 0x00005656 -#define DDRSS2_CTL_29_DATA 0x00100000 -#define DDRSS2_CTL_30_DATA 0x00000000 -#define DDRSS2_CTL_31_DATA 0x00000000 -#define DDRSS2_CTL_32_DATA 0x00000000 -#define DDRSS2_CTL_33_DATA 0x00000000 -#define DDRSS2_CTL_34_DATA 0x040C0000 -#define DDRSS2_CTL_35_DATA 0x12481248 -#define DDRSS2_CTL_36_DATA 0x00050804 -#define DDRSS2_CTL_37_DATA 0x09040008 -#define DDRSS2_CTL_38_DATA 0x15000204 -#define DDRSS2_CTL_39_DATA 0x1760008B -#define DDRSS2_CTL_40_DATA 0x1500422B -#define DDRSS2_CTL_41_DATA 0x1760008B -#define DDRSS2_CTL_42_DATA 0x2000422B -#define DDRSS2_CTL_43_DATA 0x000A0A09 -#define DDRSS2_CTL_44_DATA 0x0400078A -#define DDRSS2_CTL_45_DATA 0x1E161104 -#define DDRSS2_CTL_46_DATA 0x10012458 -#define DDRSS2_CTL_47_DATA 0x1E161110 -#define DDRSS2_CTL_48_DATA 0x10012458 -#define DDRSS2_CTL_49_DATA 0x02030410 -#define DDRSS2_CTL_50_DATA 0x2C040500 -#define DDRSS2_CTL_51_DATA 0x08292C29 -#define DDRSS2_CTL_52_DATA 0x14000E0A -#define DDRSS2_CTL_53_DATA 0x04010A0A -#define DDRSS2_CTL_54_DATA 0x01010004 -#define DDRSS2_CTL_55_DATA 0x04545408 -#define DDRSS2_CTL_56_DATA 0x04313104 -#define DDRSS2_CTL_57_DATA 0x00003131 -#define DDRSS2_CTL_58_DATA 0x00010100 -#define DDRSS2_CTL_59_DATA 0x03010000 -#define DDRSS2_CTL_60_DATA 0x00001508 -#define DDRSS2_CTL_61_DATA 0x000000CE -#define DDRSS2_CTL_62_DATA 0x0000032B -#define DDRSS2_CTL_63_DATA 0x00002073 -#define DDRSS2_CTL_64_DATA 0x0000032B -#define DDRSS2_CTL_65_DATA 0x00002073 -#define DDRSS2_CTL_66_DATA 0x00000005 -#define DDRSS2_CTL_67_DATA 0x00050000 -#define DDRSS2_CTL_68_DATA 0x00CB0012 -#define DDRSS2_CTL_69_DATA 0x00CB0408 -#define DDRSS2_CTL_70_DATA 0x00400408 -#define DDRSS2_CTL_71_DATA 0x00120103 -#define DDRSS2_CTL_72_DATA 0x00100005 -#define DDRSS2_CTL_73_DATA 0x2F080010 -#define DDRSS2_CTL_74_DATA 0x0505012F -#define DDRSS2_CTL_75_DATA 0x0401030A -#define DDRSS2_CTL_76_DATA 0x041E100B -#define DDRSS2_CTL_77_DATA 0x100B0401 -#define DDRSS2_CTL_78_DATA 0x0001041E -#define DDRSS2_CTL_79_DATA 0x00160016 -#define DDRSS2_CTL_80_DATA 0x033B033B -#define DDRSS2_CTL_81_DATA 0x033B033B -#define DDRSS2_CTL_82_DATA 0x03050505 -#define DDRSS2_CTL_83_DATA 0x03010303 -#define DDRSS2_CTL_84_DATA 0x200B100B -#define DDRSS2_CTL_85_DATA 0x04041004 -#define DDRSS2_CTL_86_DATA 0x200B100B -#define DDRSS2_CTL_87_DATA 0x04041004 -#define DDRSS2_CTL_88_DATA 0x03010000 -#define DDRSS2_CTL_89_DATA 0x00010000 -#define DDRSS2_CTL_90_DATA 0x00000000 -#define DDRSS2_CTL_91_DATA 0x00000000 -#define DDRSS2_CTL_92_DATA 0x01000000 -#define DDRSS2_CTL_93_DATA 0x80104002 -#define DDRSS2_CTL_94_DATA 0x00000000 -#define DDRSS2_CTL_95_DATA 0x00040005 -#define DDRSS2_CTL_96_DATA 0x00000000 -#define DDRSS2_CTL_97_DATA 0x00050000 -#define DDRSS2_CTL_98_DATA 0x00000004 -#define DDRSS2_CTL_99_DATA 0x00000000 -#define DDRSS2_CTL_100_DATA 0x00040005 -#define DDRSS2_CTL_101_DATA 0x00000000 -#define DDRSS2_CTL_102_DATA 0x00003380 -#define DDRSS2_CTL_103_DATA 0x00003380 -#define DDRSS2_CTL_104_DATA 0x00003380 -#define DDRSS2_CTL_105_DATA 0x00003380 -#define DDRSS2_CTL_106_DATA 0x00003380 -#define DDRSS2_CTL_107_DATA 0x00000000 -#define DDRSS2_CTL_108_DATA 0x000005A2 -#define DDRSS2_CTL_109_DATA 0x00081CC0 -#define DDRSS2_CTL_110_DATA 0x00081CC0 -#define DDRSS2_CTL_111_DATA 0x00081CC0 -#define DDRSS2_CTL_112_DATA 0x00081CC0 -#define DDRSS2_CTL_113_DATA 0x00081CC0 -#define DDRSS2_CTL_114_DATA 0x00000000 -#define DDRSS2_CTL_115_DATA 0x0000E325 -#define DDRSS2_CTL_116_DATA 0x00081CC0 -#define DDRSS2_CTL_117_DATA 0x00081CC0 -#define DDRSS2_CTL_118_DATA 0x00081CC0 -#define DDRSS2_CTL_119_DATA 0x00081CC0 -#define DDRSS2_CTL_120_DATA 0x00081CC0 -#define DDRSS2_CTL_121_DATA 0x00000000 -#define DDRSS2_CTL_122_DATA 0x0000E325 -#define DDRSS2_CTL_123_DATA 0x00000000 -#define DDRSS2_CTL_124_DATA 0x00000000 -#define DDRSS2_CTL_125_DATA 0x00000000 -#define DDRSS2_CTL_126_DATA 0x00000000 -#define DDRSS2_CTL_127_DATA 0x00000000 -#define DDRSS2_CTL_128_DATA 0x00000000 -#define DDRSS2_CTL_129_DATA 0x00000000 -#define DDRSS2_CTL_130_DATA 0x00000000 -#define DDRSS2_CTL_131_DATA 0x0B030500 -#define DDRSS2_CTL_132_DATA 0x00040B04 -#define DDRSS2_CTL_133_DATA 0x0A090000 -#define DDRSS2_CTL_134_DATA 0x0A090701 -#define DDRSS2_CTL_135_DATA 0x0900000E -#define DDRSS2_CTL_136_DATA 0x0907010A -#define DDRSS2_CTL_137_DATA 0x00000E0A -#define DDRSS2_CTL_138_DATA 0x07010A09 -#define DDRSS2_CTL_139_DATA 0x000E0A09 -#define DDRSS2_CTL_140_DATA 0x07000401 -#define DDRSS2_CTL_141_DATA 0x00000000 -#define DDRSS2_CTL_142_DATA 0x00000000 -#define DDRSS2_CTL_143_DATA 0x00000000 -#define DDRSS2_CTL_144_DATA 0x00000000 -#define DDRSS2_CTL_145_DATA 0x00000000 -#define DDRSS2_CTL_146_DATA 0x00000000 -#define DDRSS2_CTL_147_DATA 0x00000000 -#define DDRSS2_CTL_148_DATA 0x08080000 -#define DDRSS2_CTL_149_DATA 0x01000000 -#define DDRSS2_CTL_150_DATA 0x800000C0 -#define DDRSS2_CTL_151_DATA 0x800000C0 -#define DDRSS2_CTL_152_DATA 0x800000C0 -#define DDRSS2_CTL_153_DATA 0x00000000 -#define DDRSS2_CTL_154_DATA 0x00001500 -#define DDRSS2_CTL_155_DATA 0x00000000 -#define DDRSS2_CTL_156_DATA 0x00000001 -#define DDRSS2_CTL_157_DATA 0x00000002 -#define DDRSS2_CTL_158_DATA 0x0000100E -#define DDRSS2_CTL_159_DATA 0x00000000 -#define DDRSS2_CTL_160_DATA 0x00000000 -#define DDRSS2_CTL_161_DATA 0x00000000 -#define DDRSS2_CTL_162_DATA 0x00000000 -#define DDRSS2_CTL_163_DATA 0x00000000 -#define DDRSS2_CTL_164_DATA 0x000B0000 -#define DDRSS2_CTL_165_DATA 0x000E0006 -#define DDRSS2_CTL_166_DATA 0x000E0404 -#define DDRSS2_CTL_167_DATA 0x00D601AB -#define DDRSS2_CTL_168_DATA 0x10100216 -#define DDRSS2_CTL_169_DATA 0x01AB0216 -#define DDRSS2_CTL_170_DATA 0x021600D6 -#define DDRSS2_CTL_171_DATA 0x02161010 -#define DDRSS2_CTL_172_DATA 0x00000000 -#define DDRSS2_CTL_173_DATA 0x00000000 -#define DDRSS2_CTL_174_DATA 0x00000000 -#define DDRSS2_CTL_175_DATA 0x3FF40084 -#define DDRSS2_CTL_176_DATA 0x33003FF4 -#define DDRSS2_CTL_177_DATA 0x00003333 -#define DDRSS2_CTL_178_DATA 0x35000000 -#define DDRSS2_CTL_179_DATA 0x27270035 -#define DDRSS2_CTL_180_DATA 0x0F0F0000 -#define DDRSS2_CTL_181_DATA 0x16000000 -#define DDRSS2_CTL_182_DATA 0x00841616 -#define DDRSS2_CTL_183_DATA 0x3FF43FF4 -#define DDRSS2_CTL_184_DATA 0x33333300 -#define DDRSS2_CTL_185_DATA 0x00000000 -#define DDRSS2_CTL_186_DATA 0x00353500 -#define DDRSS2_CTL_187_DATA 0x00002727 -#define DDRSS2_CTL_188_DATA 0x00000F0F -#define DDRSS2_CTL_189_DATA 0x16161600 -#define DDRSS2_CTL_190_DATA 0x00000020 -#define DDRSS2_CTL_191_DATA 0x00000000 -#define DDRSS2_CTL_192_DATA 0x00000001 -#define DDRSS2_CTL_193_DATA 0x00000000 -#define DDRSS2_CTL_194_DATA 0x01000000 -#define DDRSS2_CTL_195_DATA 0x00000001 -#define DDRSS2_CTL_196_DATA 0x00000000 -#define DDRSS2_CTL_197_DATA 0x00000000 -#define DDRSS2_CTL_198_DATA 0x00000000 -#define DDRSS2_CTL_199_DATA 0x00000000 -#define DDRSS2_CTL_200_DATA 0x00000000 -#define DDRSS2_CTL_201_DATA 0x00000000 -#define DDRSS2_CTL_202_DATA 0x00000000 -#define DDRSS2_CTL_203_DATA 0x00000000 -#define DDRSS2_CTL_204_DATA 0x00000000 -#define DDRSS2_CTL_205_DATA 0x00000000 -#define DDRSS2_CTL_206_DATA 0x02000000 -#define DDRSS2_CTL_207_DATA 0x01080101 -#define DDRSS2_CTL_208_DATA 0x00000000 -#define DDRSS2_CTL_209_DATA 0x00000000 -#define DDRSS2_CTL_210_DATA 0x00000000 -#define DDRSS2_CTL_211_DATA 0x00000000 -#define DDRSS2_CTL_212_DATA 0x00000000 -#define DDRSS2_CTL_213_DATA 0x00000000 -#define DDRSS2_CTL_214_DATA 0x00000000 -#define DDRSS2_CTL_215_DATA 0x00000000 -#define DDRSS2_CTL_216_DATA 0x00000000 -#define DDRSS2_CTL_217_DATA 0x00000000 -#define DDRSS2_CTL_218_DATA 0x00000000 -#define DDRSS2_CTL_219_DATA 0x00000000 -#define DDRSS2_CTL_220_DATA 0x00000000 -#define DDRSS2_CTL_221_DATA 0x00000000 -#define DDRSS2_CTL_222_DATA 0x00001000 -#define DDRSS2_CTL_223_DATA 0x006403E8 -#define DDRSS2_CTL_224_DATA 0x00000000 -#define DDRSS2_CTL_225_DATA 0x00000000 -#define DDRSS2_CTL_226_DATA 0x00000000 -#define DDRSS2_CTL_227_DATA 0x15110000 -#define DDRSS2_CTL_228_DATA 0x00040C18 -#define DDRSS2_CTL_229_DATA 0xF000C000 -#define DDRSS2_CTL_230_DATA 0x0000F000 -#define DDRSS2_CTL_231_DATA 0x00000000 -#define DDRSS2_CTL_232_DATA 0x00000000 -#define DDRSS2_CTL_233_DATA 0xC0000000 -#define DDRSS2_CTL_234_DATA 0xF000F000 -#define DDRSS2_CTL_235_DATA 0x00000000 -#define DDRSS2_CTL_236_DATA 0x00000000 -#define DDRSS2_CTL_237_DATA 0x00000000 -#define DDRSS2_CTL_238_DATA 0xF000C000 -#define DDRSS2_CTL_239_DATA 0x0000F000 -#define DDRSS2_CTL_240_DATA 0x00000000 -#define DDRSS2_CTL_241_DATA 0x00000000 -#define DDRSS2_CTL_242_DATA 0x00030000 -#define DDRSS2_CTL_243_DATA 0x00000000 -#define DDRSS2_CTL_244_DATA 0x00000000 -#define DDRSS2_CTL_245_DATA 0x00000000 -#define DDRSS2_CTL_246_DATA 0x00000000 -#define DDRSS2_CTL_247_DATA 0x00000000 -#define DDRSS2_CTL_248_DATA 0x00000000 -#define DDRSS2_CTL_249_DATA 0x00000000 -#define DDRSS2_CTL_250_DATA 0x00000000 -#define DDRSS2_CTL_251_DATA 0x00000000 -#define DDRSS2_CTL_252_DATA 0x00000000 -#define DDRSS2_CTL_253_DATA 0x00000000 -#define DDRSS2_CTL_254_DATA 0x00000000 -#define DDRSS2_CTL_255_DATA 0x00000000 -#define DDRSS2_CTL_256_DATA 0x00000000 -#define DDRSS2_CTL_257_DATA 0x01000200 -#define DDRSS2_CTL_258_DATA 0x00370040 -#define DDRSS2_CTL_259_DATA 0x00020008 -#define DDRSS2_CTL_260_DATA 0x00400100 -#define DDRSS2_CTL_261_DATA 0x00400855 -#define DDRSS2_CTL_262_DATA 0x01000200 -#define DDRSS2_CTL_263_DATA 0x08550040 -#define DDRSS2_CTL_264_DATA 0x00000040 -#define DDRSS2_CTL_265_DATA 0x006B0003 -#define DDRSS2_CTL_266_DATA 0x0100006B -#define DDRSS2_CTL_267_DATA 0x03030303 -#define DDRSS2_CTL_268_DATA 0x00000000 -#define DDRSS2_CTL_269_DATA 0x00000202 -#define DDRSS2_CTL_270_DATA 0x00001FFF -#define DDRSS2_CTL_271_DATA 0x3FFF2000 -#define DDRSS2_CTL_272_DATA 0x03FF0000 -#define DDRSS2_CTL_273_DATA 0x000103FF -#define DDRSS2_CTL_274_DATA 0x0FFF0B00 -#define DDRSS2_CTL_275_DATA 0x01010001 -#define DDRSS2_CTL_276_DATA 0x01010101 -#define DDRSS2_CTL_277_DATA 0x01180101 -#define DDRSS2_CTL_278_DATA 0x00030000 -#define DDRSS2_CTL_279_DATA 0x00000000 -#define DDRSS2_CTL_280_DATA 0x00000000 -#define DDRSS2_CTL_281_DATA 0x00000000 -#define DDRSS2_CTL_282_DATA 0x00000000 -#define DDRSS2_CTL_283_DATA 0x00000000 -#define DDRSS2_CTL_284_DATA 0x00000000 -#define DDRSS2_CTL_285_DATA 0x00000000 -#define DDRSS2_CTL_286_DATA 0x00040101 -#define DDRSS2_CTL_287_DATA 0x04010100 -#define DDRSS2_CTL_288_DATA 0x00000000 -#define DDRSS2_CTL_289_DATA 0x00000000 -#define DDRSS2_CTL_290_DATA 0x03030300 -#define DDRSS2_CTL_291_DATA 0x00000001 -#define DDRSS2_CTL_292_DATA 0x00000000 -#define DDRSS2_CTL_293_DATA 0x00000000 -#define DDRSS2_CTL_294_DATA 0x00000000 -#define DDRSS2_CTL_295_DATA 0x00000000 -#define DDRSS2_CTL_296_DATA 0x00000000 -#define DDRSS2_CTL_297_DATA 0x00000000 -#define DDRSS2_CTL_298_DATA 0x00000000 -#define DDRSS2_CTL_299_DATA 0x00000000 -#define DDRSS2_CTL_300_DATA 0x00000000 -#define DDRSS2_CTL_301_DATA 0x00000000 -#define DDRSS2_CTL_302_DATA 0x00000000 -#define DDRSS2_CTL_303_DATA 0x00000000 -#define DDRSS2_CTL_304_DATA 0x00000000 -#define DDRSS2_CTL_305_DATA 0x00000000 -#define DDRSS2_CTL_306_DATA 0x00000000 -#define DDRSS2_CTL_307_DATA 0x00000000 -#define DDRSS2_CTL_308_DATA 0x00000000 -#define DDRSS2_CTL_309_DATA 0x00000000 -#define DDRSS2_CTL_310_DATA 0x00000000 -#define DDRSS2_CTL_311_DATA 0x00000000 -#define DDRSS2_CTL_312_DATA 0x00000000 -#define DDRSS2_CTL_313_DATA 0x01000000 -#define DDRSS2_CTL_314_DATA 0x00020201 -#define DDRSS2_CTL_315_DATA 0x01000101 -#define DDRSS2_CTL_316_DATA 0x01010001 -#define DDRSS2_CTL_317_DATA 0x00010101 -#define DDRSS2_CTL_318_DATA 0x050A0A03 -#define DDRSS2_CTL_319_DATA 0x10081F1F -#define DDRSS2_CTL_320_DATA 0x00090310 -#define DDRSS2_CTL_321_DATA 0x0B0C030F -#define DDRSS2_CTL_322_DATA 0x0B0C0306 -#define DDRSS2_CTL_323_DATA 0x0C090006 -#define DDRSS2_CTL_324_DATA 0x0100000C -#define DDRSS2_CTL_325_DATA 0x08040801 -#define DDRSS2_CTL_326_DATA 0x00000004 -#define DDRSS2_CTL_327_DATA 0x00000000 -#define DDRSS2_CTL_328_DATA 0x00010000 -#define DDRSS2_CTL_329_DATA 0x00280D00 -#define DDRSS2_CTL_330_DATA 0x00000001 -#define DDRSS2_CTL_331_DATA 0x00030001 -#define DDRSS2_CTL_332_DATA 0x00000000 -#define DDRSS2_CTL_333_DATA 0x00000000 -#define DDRSS2_CTL_334_DATA 0x00000000 -#define DDRSS2_CTL_335_DATA 0x00000000 -#define DDRSS2_CTL_336_DATA 0x00000000 -#define DDRSS2_CTL_337_DATA 0x00000000 -#define DDRSS2_CTL_338_DATA 0x00000000 -#define DDRSS2_CTL_339_DATA 0x00000000 -#define DDRSS2_CTL_340_DATA 0x01000000 -#define DDRSS2_CTL_341_DATA 0x00000001 -#define DDRSS2_CTL_342_DATA 0x00010100 -#define DDRSS2_CTL_343_DATA 0x03030000 -#define DDRSS2_CTL_344_DATA 0x00000000 -#define DDRSS2_CTL_345_DATA 0x00000000 -#define DDRSS2_CTL_346_DATA 0x00000000 -#define DDRSS2_CTL_347_DATA 0x00000000 -#define DDRSS2_CTL_348_DATA 0x00000000 -#define DDRSS2_CTL_349_DATA 0x00000000 -#define DDRSS2_CTL_350_DATA 0x00000000 -#define DDRSS2_CTL_351_DATA 0x00000000 -#define DDRSS2_CTL_352_DATA 0x00000000 -#define DDRSS2_CTL_353_DATA 0x00000000 -#define DDRSS2_CTL_354_DATA 0x00000000 -#define DDRSS2_CTL_355_DATA 0x00000000 -#define DDRSS2_CTL_356_DATA 0x00000000 -#define DDRSS2_CTL_357_DATA 0x00000000 -#define DDRSS2_CTL_358_DATA 0x00000000 -#define DDRSS2_CTL_359_DATA 0x00000000 -#define DDRSS2_CTL_360_DATA 0x000556AA -#define DDRSS2_CTL_361_DATA 0x000AAAAA -#define DDRSS2_CTL_362_DATA 0x000AA955 -#define DDRSS2_CTL_363_DATA 0x00055555 -#define DDRSS2_CTL_364_DATA 0x000B3133 -#define DDRSS2_CTL_365_DATA 0x0004CD33 -#define DDRSS2_CTL_366_DATA 0x0004CECC -#define DDRSS2_CTL_367_DATA 0x000B32CC -#define DDRSS2_CTL_368_DATA 0x00010300 -#define DDRSS2_CTL_369_DATA 0x03000100 -#define DDRSS2_CTL_370_DATA 0x00000000 -#define DDRSS2_CTL_371_DATA 0x00000000 -#define DDRSS2_CTL_372_DATA 0x00000000 -#define DDRSS2_CTL_373_DATA 0x00000000 -#define DDRSS2_CTL_374_DATA 0x00000000 -#define DDRSS2_CTL_375_DATA 0x00000000 -#define DDRSS2_CTL_376_DATA 0x00000000 -#define DDRSS2_CTL_377_DATA 0x00010000 -#define DDRSS2_CTL_378_DATA 0x00000404 -#define DDRSS2_CTL_379_DATA 0x00000000 -#define DDRSS2_CTL_380_DATA 0x00000000 -#define DDRSS2_CTL_381_DATA 0x00000000 -#define DDRSS2_CTL_382_DATA 0x00000000 -#define DDRSS2_CTL_383_DATA 0x00000000 -#define DDRSS2_CTL_384_DATA 0x00000000 -#define DDRSS2_CTL_385_DATA 0x00000000 -#define DDRSS2_CTL_386_DATA 0x00000000 -#define DDRSS2_CTL_387_DATA 0x3A3A1B00 -#define DDRSS2_CTL_388_DATA 0x000A0000 -#define DDRSS2_CTL_389_DATA 0x0000019C -#define DDRSS2_CTL_390_DATA 0x00000200 -#define DDRSS2_CTL_391_DATA 0x00000200 -#define DDRSS2_CTL_392_DATA 0x00000200 -#define DDRSS2_CTL_393_DATA 0x00000200 -#define DDRSS2_CTL_394_DATA 0x000004D4 -#define DDRSS2_CTL_395_DATA 0x00001018 -#define DDRSS2_CTL_396_DATA 0x00000204 -#define DDRSS2_CTL_397_DATA 0x000040E6 -#define DDRSS2_CTL_398_DATA 0x00000200 -#define DDRSS2_CTL_399_DATA 0x00000200 -#define DDRSS2_CTL_400_DATA 0x00000200 -#define DDRSS2_CTL_401_DATA 0x00000200 -#define DDRSS2_CTL_402_DATA 0x0000C2B2 -#define DDRSS2_CTL_403_DATA 0x000288FC -#define DDRSS2_CTL_404_DATA 0x00000E15 -#define DDRSS2_CTL_405_DATA 0x000040E6 -#define DDRSS2_CTL_406_DATA 0x00000200 -#define DDRSS2_CTL_407_DATA 0x00000200 -#define DDRSS2_CTL_408_DATA 0x00000200 -#define DDRSS2_CTL_409_DATA 0x00000200 -#define DDRSS2_CTL_410_DATA 0x0000C2B2 -#define DDRSS2_CTL_411_DATA 0x000288FC -#define DDRSS2_CTL_412_DATA 0x02020E15 -#define DDRSS2_CTL_413_DATA 0x03030202 -#define DDRSS2_CTL_414_DATA 0x00000022 -#define DDRSS2_CTL_415_DATA 0x00000000 -#define DDRSS2_CTL_416_DATA 0x00000000 -#define DDRSS2_CTL_417_DATA 0x00001403 -#define DDRSS2_CTL_418_DATA 0x000007D0 -#define DDRSS2_CTL_419_DATA 0x00000000 -#define DDRSS2_CTL_420_DATA 0x00000000 -#define DDRSS2_CTL_421_DATA 0x00030000 -#define DDRSS2_CTL_422_DATA 0x0007001F -#define DDRSS2_CTL_423_DATA 0x001B0033 -#define DDRSS2_CTL_424_DATA 0x001B0033 -#define DDRSS2_CTL_425_DATA 0x00000000 -#define DDRSS2_CTL_426_DATA 0x00000000 -#define DDRSS2_CTL_427_DATA 0x02000000 -#define DDRSS2_CTL_428_DATA 0x01000404 -#define DDRSS2_CTL_429_DATA 0x0B1E0B1E -#define DDRSS2_CTL_430_DATA 0x00000105 -#define DDRSS2_CTL_431_DATA 0x00010101 -#define DDRSS2_CTL_432_DATA 0x00010101 -#define DDRSS2_CTL_433_DATA 0x00010001 -#define DDRSS2_CTL_434_DATA 0x00000101 -#define DDRSS2_CTL_435_DATA 0x02000201 -#define DDRSS2_CTL_436_DATA 0x02010000 -#define DDRSS2_CTL_437_DATA 0x00000200 -#define DDRSS2_CTL_438_DATA 0x28060000 -#define DDRSS2_CTL_439_DATA 0x00000128 -#define DDRSS2_CTL_440_DATA 0xFFFFFFFF -#define DDRSS2_CTL_441_DATA 0xFFFFFFFF -#define DDRSS2_CTL_442_DATA 0x00000000 -#define DDRSS2_CTL_443_DATA 0x00000000 -#define DDRSS2_CTL_444_DATA 0x00000000 -#define DDRSS2_CTL_445_DATA 0x00000000 -#define DDRSS2_CTL_446_DATA 0x00000000 -#define DDRSS2_CTL_447_DATA 0x00000000 -#define DDRSS2_CTL_448_DATA 0x00000000 -#define DDRSS2_CTL_449_DATA 0x00000000 -#define DDRSS2_CTL_450_DATA 0x00000000 -#define DDRSS2_CTL_451_DATA 0x00000000 -#define DDRSS2_CTL_452_DATA 0x00000000 -#define DDRSS2_CTL_453_DATA 0x00000000 -#define DDRSS2_CTL_454_DATA 0x00000000 -#define DDRSS2_CTL_455_DATA 0x00000000 -#define DDRSS2_CTL_456_DATA 0x00000000 -#define DDRSS2_CTL_457_DATA 0x00000000 -#define DDRSS2_CTL_458_DATA 0x00000000 - -#define DDRSS2_PI_00_DATA 0x00000B00 -#define DDRSS2_PI_01_DATA 0x00000000 -#define DDRSS2_PI_02_DATA 0x00000000 -#define DDRSS2_PI_03_DATA 0x00000000 -#define DDRSS2_PI_04_DATA 0x00000000 -#define DDRSS2_PI_05_DATA 0x00000101 -#define DDRSS2_PI_06_DATA 0x00640000 -#define DDRSS2_PI_07_DATA 0x00000001 -#define DDRSS2_PI_08_DATA 0x00000000 -#define DDRSS2_PI_09_DATA 0x00000000 -#define DDRSS2_PI_10_DATA 0x00000000 -#define DDRSS2_PI_11_DATA 0x00000000 -#define DDRSS2_PI_12_DATA 0x00000007 -#define DDRSS2_PI_13_DATA 0x00010002 -#define DDRSS2_PI_14_DATA 0x0800000F -#define DDRSS2_PI_15_DATA 0x00000103 -#define DDRSS2_PI_16_DATA 0x00000005 -#define DDRSS2_PI_17_DATA 0x00000000 -#define DDRSS2_PI_18_DATA 0x00000000 -#define DDRSS2_PI_19_DATA 0x00000000 -#define DDRSS2_PI_20_DATA 0x00000000 -#define DDRSS2_PI_21_DATA 0x00000000 -#define DDRSS2_PI_22_DATA 0x00000000 -#define DDRSS2_PI_23_DATA 0x00000000 -#define DDRSS2_PI_24_DATA 0x00000000 -#define DDRSS2_PI_25_DATA 0x00000000 -#define DDRSS2_PI_26_DATA 0x00010100 -#define DDRSS2_PI_27_DATA 0x00280A00 -#define DDRSS2_PI_28_DATA 0x00000000 -#define DDRSS2_PI_29_DATA 0x0F000000 -#define DDRSS2_PI_30_DATA 0x00003200 -#define DDRSS2_PI_31_DATA 0x00000000 -#define DDRSS2_PI_32_DATA 0x00000000 -#define DDRSS2_PI_33_DATA 0x01010102 -#define DDRSS2_PI_34_DATA 0x00000000 -#define DDRSS2_PI_35_DATA 0x000000AA -#define DDRSS2_PI_36_DATA 0x00000055 -#define DDRSS2_PI_37_DATA 0x000000B5 -#define DDRSS2_PI_38_DATA 0x0000004A -#define DDRSS2_PI_39_DATA 0x00000056 -#define DDRSS2_PI_40_DATA 0x000000A9 -#define DDRSS2_PI_41_DATA 0x000000A9 -#define DDRSS2_PI_42_DATA 0x000000B5 -#define DDRSS2_PI_43_DATA 0x00000000 -#define DDRSS2_PI_44_DATA 0x00000000 -#define DDRSS2_PI_45_DATA 0x000F0F00 -#define DDRSS2_PI_46_DATA 0x0000001B -#define DDRSS2_PI_47_DATA 0x000007D0 -#define DDRSS2_PI_48_DATA 0x00000300 -#define DDRSS2_PI_49_DATA 0x00000000 -#define DDRSS2_PI_50_DATA 0x00000000 -#define DDRSS2_PI_51_DATA 0x01000000 -#define DDRSS2_PI_52_DATA 0x00010101 -#define DDRSS2_PI_53_DATA 0x00000000 -#define DDRSS2_PI_54_DATA 0x00030000 -#define DDRSS2_PI_55_DATA 0x0F000000 -#define DDRSS2_PI_56_DATA 0x00000017 -#define DDRSS2_PI_57_DATA 0x00000000 -#define DDRSS2_PI_58_DATA 0x00000000 -#define DDRSS2_PI_59_DATA 0x00000000 -#define DDRSS2_PI_60_DATA 0x0A0A140A -#define DDRSS2_PI_61_DATA 0x10020101 -#define DDRSS2_PI_62_DATA 0x00020805 -#define DDRSS2_PI_63_DATA 0x01000404 -#define DDRSS2_PI_64_DATA 0x00000000 -#define DDRSS2_PI_65_DATA 0x00000000 -#define DDRSS2_PI_66_DATA 0x00000100 -#define DDRSS2_PI_67_DATA 0x0001010F -#define DDRSS2_PI_68_DATA 0x00340000 -#define DDRSS2_PI_69_DATA 0x00000000 -#define DDRSS2_PI_70_DATA 0x00000000 -#define DDRSS2_PI_71_DATA 0x0000FFFF -#define DDRSS2_PI_72_DATA 0x00000000 -#define DDRSS2_PI_73_DATA 0x00080000 -#define DDRSS2_PI_74_DATA 0x02000200 -#define DDRSS2_PI_75_DATA 0x01000100 -#define DDRSS2_PI_76_DATA 0x01000000 -#define DDRSS2_PI_77_DATA 0x02000200 -#define DDRSS2_PI_78_DATA 0x00000200 -#define DDRSS2_PI_79_DATA 0x00000000 -#define DDRSS2_PI_80_DATA 0x00000000 -#define DDRSS2_PI_81_DATA 0x00000000 -#define DDRSS2_PI_82_DATA 0x00000000 -#define DDRSS2_PI_83_DATA 0x00000000 -#define DDRSS2_PI_84_DATA 0x00000000 -#define DDRSS2_PI_85_DATA 0x00000000 -#define DDRSS2_PI_86_DATA 0x00000000 -#define DDRSS2_PI_87_DATA 0x00000000 -#define DDRSS2_PI_88_DATA 0x00000000 -#define DDRSS2_PI_89_DATA 0x00000000 -#define DDRSS2_PI_90_DATA 0x00000000 -#define DDRSS2_PI_91_DATA 0x00000400 -#define DDRSS2_PI_92_DATA 0x02010000 -#define DDRSS2_PI_93_DATA 0x00080003 -#define DDRSS2_PI_94_DATA 0x00080000 -#define DDRSS2_PI_95_DATA 0x00000001 -#define DDRSS2_PI_96_DATA 0x00000000 -#define DDRSS2_PI_97_DATA 0x0000AA00 -#define DDRSS2_PI_98_DATA 0x00000000 -#define DDRSS2_PI_99_DATA 0x00000000 -#define DDRSS2_PI_100_DATA 0x00010000 -#define DDRSS2_PI_101_DATA 0x00000000 -#define DDRSS2_PI_102_DATA 0x00000000 -#define DDRSS2_PI_103_DATA 0x00000000 -#define DDRSS2_PI_104_DATA 0x00000000 -#define DDRSS2_PI_105_DATA 0x00000000 -#define DDRSS2_PI_106_DATA 0x00000000 -#define DDRSS2_PI_107_DATA 0x00000000 -#define DDRSS2_PI_108_DATA 0x00000000 -#define DDRSS2_PI_109_DATA 0x00000000 -#define DDRSS2_PI_110_DATA 0x00000000 -#define DDRSS2_PI_111_DATA 0x00000000 -#define DDRSS2_PI_112_DATA 0x00000000 -#define DDRSS2_PI_113_DATA 0x00000000 -#define DDRSS2_PI_114_DATA 0x00000000 -#define DDRSS2_PI_115_DATA 0x00000000 -#define DDRSS2_PI_116_DATA 0x00000000 -#define DDRSS2_PI_117_DATA 0x00000000 -#define DDRSS2_PI_118_DATA 0x00000000 -#define DDRSS2_PI_119_DATA 0x00000000 -#define DDRSS2_PI_120_DATA 0x00000000 -#define DDRSS2_PI_121_DATA 0x00000000 -#define DDRSS2_PI_122_DATA 0x00000000 -#define DDRSS2_PI_123_DATA 0x00000000 -#define DDRSS2_PI_124_DATA 0x00000000 -#define DDRSS2_PI_125_DATA 0x00000008 -#define DDRSS2_PI_126_DATA 0x00000000 -#define DDRSS2_PI_127_DATA 0x00000000 -#define DDRSS2_PI_128_DATA 0x00000000 -#define DDRSS2_PI_129_DATA 0x00000000 -#define DDRSS2_PI_130_DATA 0x00000000 -#define DDRSS2_PI_131_DATA 0x00000000 -#define DDRSS2_PI_132_DATA 0x00000000 -#define DDRSS2_PI_133_DATA 0x00000000 -#define DDRSS2_PI_134_DATA 0x00000002 -#define DDRSS2_PI_135_DATA 0x00000000 -#define DDRSS2_PI_136_DATA 0x00000000 -#define DDRSS2_PI_137_DATA 0x0000000A -#define DDRSS2_PI_138_DATA 0x00000019 -#define DDRSS2_PI_139_DATA 0x00000100 -#define DDRSS2_PI_140_DATA 0x00000000 -#define DDRSS2_PI_141_DATA 0x00000000 -#define DDRSS2_PI_142_DATA 0x00000000 -#define DDRSS2_PI_143_DATA 0x00000000 -#define DDRSS2_PI_144_DATA 0x01000000 -#define DDRSS2_PI_145_DATA 0x00010003 -#define DDRSS2_PI_146_DATA 0x02000101 -#define DDRSS2_PI_147_DATA 0x01030001 -#define DDRSS2_PI_148_DATA 0x00010400 -#define DDRSS2_PI_149_DATA 0x06000105 -#define DDRSS2_PI_150_DATA 0x01070001 -#define DDRSS2_PI_151_DATA 0x00000000 -#define DDRSS2_PI_152_DATA 0x00000000 -#define DDRSS2_PI_153_DATA 0x00000000 -#define DDRSS2_PI_154_DATA 0x00010001 -#define DDRSS2_PI_155_DATA 0x00000000 -#define DDRSS2_PI_156_DATA 0x00000000 -#define DDRSS2_PI_157_DATA 0x00000000 -#define DDRSS2_PI_158_DATA 0x00000000 -#define DDRSS2_PI_159_DATA 0x00000401 -#define DDRSS2_PI_160_DATA 0x00000000 -#define DDRSS2_PI_161_DATA 0x00010000 -#define DDRSS2_PI_162_DATA 0x00000000 -#define DDRSS2_PI_163_DATA 0x2B2B0200 -#define DDRSS2_PI_164_DATA 0x00000034 -#define DDRSS2_PI_165_DATA 0x00000064 -#define DDRSS2_PI_166_DATA 0x00020064 -#define DDRSS2_PI_167_DATA 0x02000200 -#define DDRSS2_PI_168_DATA 0x48120C04 -#define DDRSS2_PI_169_DATA 0x00154812 -#define DDRSS2_PI_170_DATA 0x000000CE -#define DDRSS2_PI_171_DATA 0x0000032B -#define DDRSS2_PI_172_DATA 0x00002073 -#define DDRSS2_PI_173_DATA 0x0000032B -#define DDRSS2_PI_174_DATA 0x04002073 -#define DDRSS2_PI_175_DATA 0x01010404 -#define DDRSS2_PI_176_DATA 0x00001501 -#define DDRSS2_PI_177_DATA 0x00150015 -#define DDRSS2_PI_178_DATA 0x01000100 -#define DDRSS2_PI_179_DATA 0x00000100 -#define DDRSS2_PI_180_DATA 0x00000000 -#define DDRSS2_PI_181_DATA 0x01010101 -#define DDRSS2_PI_182_DATA 0x00000101 -#define DDRSS2_PI_183_DATA 0x00000000 -#define DDRSS2_PI_184_DATA 0x00000000 -#define DDRSS2_PI_185_DATA 0x15040000 -#define DDRSS2_PI_186_DATA 0x0E0E0215 -#define DDRSS2_PI_187_DATA 0x00040402 -#define DDRSS2_PI_188_DATA 0x000D0035 -#define DDRSS2_PI_189_DATA 0x00218049 -#define DDRSS2_PI_190_DATA 0x00218049 -#define DDRSS2_PI_191_DATA 0x01010101 -#define DDRSS2_PI_192_DATA 0x0004000E -#define DDRSS2_PI_193_DATA 0x00040216 -#define DDRSS2_PI_194_DATA 0x01000216 -#define DDRSS2_PI_195_DATA 0x000F000F -#define DDRSS2_PI_196_DATA 0x02170100 -#define DDRSS2_PI_197_DATA 0x01000217 -#define DDRSS2_PI_198_DATA 0x02170217 -#define DDRSS2_PI_199_DATA 0x32103200 -#define DDRSS2_PI_200_DATA 0x01013210 -#define DDRSS2_PI_201_DATA 0x0A070601 -#define DDRSS2_PI_202_DATA 0x1F130A0D -#define DDRSS2_PI_203_DATA 0x1F130A14 -#define DDRSS2_PI_204_DATA 0x0000C014 -#define DDRSS2_PI_205_DATA 0x00C01000 -#define DDRSS2_PI_206_DATA 0x00C01000 -#define DDRSS2_PI_207_DATA 0x00021000 -#define DDRSS2_PI_208_DATA 0x0024000E -#define DDRSS2_PI_209_DATA 0x00240216 -#define DDRSS2_PI_210_DATA 0x00110216 -#define DDRSS2_PI_211_DATA 0x32000056 -#define DDRSS2_PI_212_DATA 0x00000301 -#define DDRSS2_PI_213_DATA 0x005B0036 -#define DDRSS2_PI_214_DATA 0x03013212 -#define DDRSS2_PI_215_DATA 0x00003600 -#define DDRSS2_PI_216_DATA 0x3212005B -#define DDRSS2_PI_217_DATA 0x09000301 -#define DDRSS2_PI_218_DATA 0x04010504 -#define DDRSS2_PI_219_DATA 0x040006C9 -#define DDRSS2_PI_220_DATA 0x0A032001 -#define DDRSS2_PI_221_DATA 0x2C31110A -#define DDRSS2_PI_222_DATA 0x00002918 -#define DDRSS2_PI_223_DATA 0x6001071C -#define DDRSS2_PI_224_DATA 0x1E202008 -#define DDRSS2_PI_225_DATA 0x2C311116 -#define DDRSS2_PI_226_DATA 0x00002918 -#define DDRSS2_PI_227_DATA 0x6001071C -#define DDRSS2_PI_228_DATA 0x1E202008 -#define DDRSS2_PI_229_DATA 0x00019C16 -#define DDRSS2_PI_230_DATA 0x00001018 -#define DDRSS2_PI_231_DATA 0x000040E6 -#define DDRSS2_PI_232_DATA 0x000288FC -#define DDRSS2_PI_233_DATA 0x000040E6 -#define DDRSS2_PI_234_DATA 0x000288FC -#define DDRSS2_PI_235_DATA 0x033B0016 -#define DDRSS2_PI_236_DATA 0x0303033B -#define DDRSS2_PI_237_DATA 0x002AF803 -#define DDRSS2_PI_238_DATA 0x0001ADAF -#define DDRSS2_PI_239_DATA 0x00000005 -#define DDRSS2_PI_240_DATA 0x0000006E -#define DDRSS2_PI_241_DATA 0x00000016 -#define DDRSS2_PI_242_DATA 0x000681C8 -#define DDRSS2_PI_243_DATA 0x0001ADAF -#define DDRSS2_PI_244_DATA 0x00000005 -#define DDRSS2_PI_245_DATA 0x000010A9 -#define DDRSS2_PI_246_DATA 0x0000033B -#define DDRSS2_PI_247_DATA 0x000681C8 -#define DDRSS2_PI_248_DATA 0x0001ADAF -#define DDRSS2_PI_249_DATA 0x00000005 -#define DDRSS2_PI_250_DATA 0x000010A9 -#define DDRSS2_PI_251_DATA 0x0100033B -#define DDRSS2_PI_252_DATA 0x00370040 -#define DDRSS2_PI_253_DATA 0x00010008 -#define DDRSS2_PI_254_DATA 0x08550040 -#define DDRSS2_PI_255_DATA 0x00010040 -#define DDRSS2_PI_256_DATA 0x08550040 -#define DDRSS2_PI_257_DATA 0x00000340 -#define DDRSS2_PI_258_DATA 0x006B006B -#define DDRSS2_PI_259_DATA 0x08040404 -#define DDRSS2_PI_260_DATA 0x00000055 -#define DDRSS2_PI_261_DATA 0x55083C5A -#define DDRSS2_PI_262_DATA 0x5A000000 -#define DDRSS2_PI_263_DATA 0x0055083C -#define DDRSS2_PI_264_DATA 0x3C5A0000 -#define DDRSS2_PI_265_DATA 0x00005508 -#define DDRSS2_PI_266_DATA 0x0C3C5A00 -#define DDRSS2_PI_267_DATA 0x080F0E0D -#define DDRSS2_PI_268_DATA 0x000B0A09 -#define DDRSS2_PI_269_DATA 0x00030201 -#define DDRSS2_PI_270_DATA 0x01000000 -#define DDRSS2_PI_271_DATA 0x04020201 -#define DDRSS2_PI_272_DATA 0x00080804 -#define DDRSS2_PI_273_DATA 0x00000000 -#define DDRSS2_PI_274_DATA 0x00000000 -#define DDRSS2_PI_275_DATA 0x00330084 -#define DDRSS2_PI_276_DATA 0x00160000 -#define DDRSS2_PI_277_DATA 0x35333FF4 -#define DDRSS2_PI_278_DATA 0x00160F27 -#define DDRSS2_PI_279_DATA 0x35333FF4 -#define DDRSS2_PI_280_DATA 0x00160F27 -#define DDRSS2_PI_281_DATA 0x00330084 -#define DDRSS2_PI_282_DATA 0x00160000 -#define DDRSS2_PI_283_DATA 0x35333FF4 -#define DDRSS2_PI_284_DATA 0x00160F27 -#define DDRSS2_PI_285_DATA 0x35333FF4 -#define DDRSS2_PI_286_DATA 0x00160F27 -#define DDRSS2_PI_287_DATA 0x00330084 -#define DDRSS2_PI_288_DATA 0x00160000 -#define DDRSS2_PI_289_DATA 0x35333FF4 -#define DDRSS2_PI_290_DATA 0x00160F27 -#define DDRSS2_PI_291_DATA 0x35333FF4 -#define DDRSS2_PI_292_DATA 0x00160F27 -#define DDRSS2_PI_293_DATA 0x00330084 -#define DDRSS2_PI_294_DATA 0x00160000 -#define DDRSS2_PI_295_DATA 0x35333FF4 -#define DDRSS2_PI_296_DATA 0x00160F27 -#define DDRSS2_PI_297_DATA 0x35333FF4 -#define DDRSS2_PI_298_DATA 0x00160F27 -#define DDRSS2_PI_299_DATA 0x00000000 - -#define DDRSS2_PHY_00_DATA 0x000004F0 -#define DDRSS2_PHY_01_DATA 0x00000000 -#define DDRSS2_PHY_02_DATA 0x00030200 -#define DDRSS2_PHY_03_DATA 0x00000000 -#define DDRSS2_PHY_04_DATA 0x00000000 -#define DDRSS2_PHY_05_DATA 0x01030000 -#define DDRSS2_PHY_06_DATA 0x00010000 -#define DDRSS2_PHY_07_DATA 0x01030004 -#define DDRSS2_PHY_08_DATA 0x01000000 -#define DDRSS2_PHY_09_DATA 0x00000000 -#define DDRSS2_PHY_10_DATA 0x00000000 -#define DDRSS2_PHY_11_DATA 0x01000001 -#define DDRSS2_PHY_12_DATA 0x00000100 -#define DDRSS2_PHY_13_DATA 0x000800C0 -#define DDRSS2_PHY_14_DATA 0x060100CC -#define DDRSS2_PHY_15_DATA 0x00030066 -#define DDRSS2_PHY_16_DATA 0x00000000 -#define DDRSS2_PHY_17_DATA 0x00000301 -#define DDRSS2_PHY_18_DATA 0x0000AAAA -#define DDRSS2_PHY_19_DATA 0x00005555 -#define DDRSS2_PHY_20_DATA 0x0000B5B5 -#define DDRSS2_PHY_21_DATA 0x00004A4A -#define DDRSS2_PHY_22_DATA 0x00005656 -#define DDRSS2_PHY_23_DATA 0x0000A9A9 -#define DDRSS2_PHY_24_DATA 0x0000A9A9 -#define DDRSS2_PHY_25_DATA 0x0000B5B5 -#define DDRSS2_PHY_26_DATA 0x00000000 -#define DDRSS2_PHY_27_DATA 0x00000000 -#define DDRSS2_PHY_28_DATA 0x2A000000 -#define DDRSS2_PHY_29_DATA 0x00000808 -#define DDRSS2_PHY_30_DATA 0x0F000000 -#define DDRSS2_PHY_31_DATA 0x00000F0F -#define DDRSS2_PHY_32_DATA 0x10400000 -#define DDRSS2_PHY_33_DATA 0x0C002006 -#define DDRSS2_PHY_34_DATA 0x00000000 -#define DDRSS2_PHY_35_DATA 0x00000000 -#define DDRSS2_PHY_36_DATA 0x55555555 -#define DDRSS2_PHY_37_DATA 0xAAAAAAAA -#define DDRSS2_PHY_38_DATA 0x55555555 -#define DDRSS2_PHY_39_DATA 0xAAAAAAAA -#define DDRSS2_PHY_40_DATA 0x00005555 -#define DDRSS2_PHY_41_DATA 0x01000100 -#define DDRSS2_PHY_42_DATA 0x00800180 -#define DDRSS2_PHY_43_DATA 0x00000001 -#define DDRSS2_PHY_44_DATA 0x00000000 -#define DDRSS2_PHY_45_DATA 0x00000000 -#define DDRSS2_PHY_46_DATA 0x00000000 -#define DDRSS2_PHY_47_DATA 0x00000000 -#define DDRSS2_PHY_48_DATA 0x00000000 -#define DDRSS2_PHY_49_DATA 0x00000000 -#define DDRSS2_PHY_50_DATA 0x00000000 -#define DDRSS2_PHY_51_DATA 0x00000000 -#define DDRSS2_PHY_52_DATA 0x00000000 -#define DDRSS2_PHY_53_DATA 0x00000000 -#define DDRSS2_PHY_54_DATA 0x00000000 -#define DDRSS2_PHY_55_DATA 0x00000000 -#define DDRSS2_PHY_56_DATA 0x00000000 -#define DDRSS2_PHY_57_DATA 0x00000000 -#define DDRSS2_PHY_58_DATA 0x00000000 -#define DDRSS2_PHY_59_DATA 0x00000000 -#define DDRSS2_PHY_60_DATA 0x00000000 -#define DDRSS2_PHY_61_DATA 0x00000000 -#define DDRSS2_PHY_62_DATA 0x00000000 -#define DDRSS2_PHY_63_DATA 0x00000000 -#define DDRSS2_PHY_64_DATA 0x00000000 -#define DDRSS2_PHY_65_DATA 0x00000000 -#define DDRSS2_PHY_66_DATA 0x00000104 -#define DDRSS2_PHY_67_DATA 0x00000120 -#define DDRSS2_PHY_68_DATA 0x00000000 -#define DDRSS2_PHY_69_DATA 0x00000000 -#define DDRSS2_PHY_70_DATA 0x00000000 -#define DDRSS2_PHY_71_DATA 0x00000000 -#define DDRSS2_PHY_72_DATA 0x00000000 -#define DDRSS2_PHY_73_DATA 0x00000000 -#define DDRSS2_PHY_74_DATA 0x00000000 -#define DDRSS2_PHY_75_DATA 0x00000001 -#define DDRSS2_PHY_76_DATA 0x07FF0000 -#define DDRSS2_PHY_77_DATA 0x0080081F -#define DDRSS2_PHY_78_DATA 0x00081020 -#define DDRSS2_PHY_79_DATA 0x04010000 -#define DDRSS2_PHY_80_DATA 0x00000000 -#define DDRSS2_PHY_81_DATA 0x00000000 -#define DDRSS2_PHY_82_DATA 0x00000000 -#define DDRSS2_PHY_83_DATA 0x00000100 -#define DDRSS2_PHY_84_DATA 0x01CC0C01 -#define DDRSS2_PHY_85_DATA 0x1003CC0C -#define DDRSS2_PHY_86_DATA 0x20000140 -#define DDRSS2_PHY_87_DATA 0x07FF0200 -#define DDRSS2_PHY_88_DATA 0x0000DD01 -#define DDRSS2_PHY_89_DATA 0x10100303 -#define DDRSS2_PHY_90_DATA 0x10101010 -#define DDRSS2_PHY_91_DATA 0x10101010 -#define DDRSS2_PHY_92_DATA 0x00021010 -#define DDRSS2_PHY_93_DATA 0x00100010 -#define DDRSS2_PHY_94_DATA 0x00100010 -#define DDRSS2_PHY_95_DATA 0x00100010 -#define DDRSS2_PHY_96_DATA 0x00100010 -#define DDRSS2_PHY_97_DATA 0x00050010 -#define DDRSS2_PHY_98_DATA 0x51517041 -#define DDRSS2_PHY_99_DATA 0x31C06001 -#define DDRSS2_PHY_100_DATA 0x07AB0340 -#define DDRSS2_PHY_101_DATA 0x00C0C001 -#define DDRSS2_PHY_102_DATA 0x0E0D0001 -#define DDRSS2_PHY_103_DATA 0x10001000 -#define DDRSS2_PHY_104_DATA 0x0C083E42 -#define DDRSS2_PHY_105_DATA 0x0F0C3701 -#define DDRSS2_PHY_106_DATA 0x01000140 -#define DDRSS2_PHY_107_DATA 0x0C000420 -#define DDRSS2_PHY_108_DATA 0x00000198 -#define DDRSS2_PHY_109_DATA 0x0A0000D0 -#define DDRSS2_PHY_110_DATA 0x00030200 -#define DDRSS2_PHY_111_DATA 0x02800000 -#define DDRSS2_PHY_112_DATA 0x80800000 -#define DDRSS2_PHY_113_DATA 0x000E2010 -#define DDRSS2_PHY_114_DATA 0x76543210 -#define DDRSS2_PHY_115_DATA 0x00000008 -#define DDRSS2_PHY_116_DATA 0x02800280 -#define DDRSS2_PHY_117_DATA 0x02800280 -#define DDRSS2_PHY_118_DATA 0x02800280 -#define DDRSS2_PHY_119_DATA 0x02800280 -#define DDRSS2_PHY_120_DATA 0x00000280 -#define DDRSS2_PHY_121_DATA 0x0000A000 -#define DDRSS2_PHY_122_DATA 0x00A000A0 -#define DDRSS2_PHY_123_DATA 0x00A000A0 -#define DDRSS2_PHY_124_DATA 0x00A000A0 -#define DDRSS2_PHY_125_DATA 0x00A000A0 -#define DDRSS2_PHY_126_DATA 0x00A000A0 -#define DDRSS2_PHY_127_DATA 0x00A000A0 -#define DDRSS2_PHY_128_DATA 0x00A000A0 -#define DDRSS2_PHY_129_DATA 0x00A000A0 -#define DDRSS2_PHY_130_DATA 0x01C200A0 -#define DDRSS2_PHY_131_DATA 0x01A00005 -#define DDRSS2_PHY_132_DATA 0x00000000 -#define DDRSS2_PHY_133_DATA 0x00000000 -#define DDRSS2_PHY_134_DATA 0x00080200 -#define DDRSS2_PHY_135_DATA 0x00000000 -#define DDRSS2_PHY_136_DATA 0x20202000 -#define DDRSS2_PHY_137_DATA 0x20202020 -#define DDRSS2_PHY_138_DATA 0xF0F02020 -#define DDRSS2_PHY_139_DATA 0x00000000 -#define DDRSS2_PHY_140_DATA 0x00000000 -#define DDRSS2_PHY_141_DATA 0x00000000 -#define DDRSS2_PHY_142_DATA 0x00000000 -#define DDRSS2_PHY_143_DATA 0x00000000 -#define DDRSS2_PHY_144_DATA 0x00000000 -#define DDRSS2_PHY_145_DATA 0x00000000 -#define DDRSS2_PHY_146_DATA 0x00000000 -#define DDRSS2_PHY_147_DATA 0x00000000 -#define DDRSS2_PHY_148_DATA 0x00000000 -#define DDRSS2_PHY_149_DATA 0x00000000 -#define DDRSS2_PHY_150_DATA 0x00000000 -#define DDRSS2_PHY_151_DATA 0x00000000 -#define DDRSS2_PHY_152_DATA 0x00000000 -#define DDRSS2_PHY_153_DATA 0x00000000 -#define DDRSS2_PHY_154_DATA 0x00000000 -#define DDRSS2_PHY_155_DATA 0x00000000 -#define DDRSS2_PHY_156_DATA 0x00000000 -#define DDRSS2_PHY_157_DATA 0x00000000 -#define DDRSS2_PHY_158_DATA 0x00000000 -#define DDRSS2_PHY_159_DATA 0x00000000 -#define DDRSS2_PHY_160_DATA 0x00000000 -#define DDRSS2_PHY_161_DATA 0x00000000 -#define DDRSS2_PHY_162_DATA 0x00000000 -#define DDRSS2_PHY_163_DATA 0x00000000 -#define DDRSS2_PHY_164_DATA 0x00000000 -#define DDRSS2_PHY_165_DATA 0x00000000 -#define DDRSS2_PHY_166_DATA 0x00000000 -#define DDRSS2_PHY_167_DATA 0x00000000 -#define DDRSS2_PHY_168_DATA 0x00000000 -#define DDRSS2_PHY_169_DATA 0x00000000 -#define DDRSS2_PHY_170_DATA 0x00000000 -#define DDRSS2_PHY_171_DATA 0x00000000 -#define DDRSS2_PHY_172_DATA 0x00000000 -#define DDRSS2_PHY_173_DATA 0x00000000 -#define DDRSS2_PHY_174_DATA 0x00000000 -#define DDRSS2_PHY_175_DATA 0x00000000 -#define DDRSS2_PHY_176_DATA 0x00000000 -#define DDRSS2_PHY_177_DATA 0x00000000 -#define DDRSS2_PHY_178_DATA 0x00000000 -#define DDRSS2_PHY_179_DATA 0x00000000 -#define DDRSS2_PHY_180_DATA 0x00000000 -#define DDRSS2_PHY_181_DATA 0x00000000 -#define DDRSS2_PHY_182_DATA 0x00000000 -#define DDRSS2_PHY_183_DATA 0x00000000 -#define DDRSS2_PHY_184_DATA 0x00000000 -#define DDRSS2_PHY_185_DATA 0x00000000 -#define DDRSS2_PHY_186_DATA 0x00000000 -#define DDRSS2_PHY_187_DATA 0x00000000 -#define DDRSS2_PHY_188_DATA 0x00000000 -#define DDRSS2_PHY_189_DATA 0x00000000 -#define DDRSS2_PHY_190_DATA 0x00000000 -#define DDRSS2_PHY_191_DATA 0x00000000 -#define DDRSS2_PHY_192_DATA 0x00000000 -#define DDRSS2_PHY_193_DATA 0x00000000 -#define DDRSS2_PHY_194_DATA 0x00000000 -#define DDRSS2_PHY_195_DATA 0x00000000 -#define DDRSS2_PHY_196_DATA 0x00000000 -#define DDRSS2_PHY_197_DATA 0x00000000 -#define DDRSS2_PHY_198_DATA 0x00000000 -#define DDRSS2_PHY_199_DATA 0x00000000 -#define DDRSS2_PHY_200_DATA 0x00000000 -#define DDRSS2_PHY_201_DATA 0x00000000 -#define DDRSS2_PHY_202_DATA 0x00000000 -#define DDRSS2_PHY_203_DATA 0x00000000 -#define DDRSS2_PHY_204_DATA 0x00000000 -#define DDRSS2_PHY_205_DATA 0x00000000 -#define DDRSS2_PHY_206_DATA 0x00000000 -#define DDRSS2_PHY_207_DATA 0x00000000 -#define DDRSS2_PHY_208_DATA 0x00000000 -#define DDRSS2_PHY_209_DATA 0x00000000 -#define DDRSS2_PHY_210_DATA 0x00000000 -#define DDRSS2_PHY_211_DATA 0x00000000 -#define DDRSS2_PHY_212_DATA 0x00000000 -#define DDRSS2_PHY_213_DATA 0x00000000 -#define DDRSS2_PHY_214_DATA 0x00000000 -#define DDRSS2_PHY_215_DATA 0x00000000 -#define DDRSS2_PHY_216_DATA 0x00000000 -#define DDRSS2_PHY_217_DATA 0x00000000 -#define DDRSS2_PHY_218_DATA 0x00000000 -#define DDRSS2_PHY_219_DATA 0x00000000 -#define DDRSS2_PHY_220_DATA 0x00000000 -#define DDRSS2_PHY_221_DATA 0x00000000 -#define DDRSS2_PHY_222_DATA 0x00000000 -#define DDRSS2_PHY_223_DATA 0x00000000 -#define DDRSS2_PHY_224_DATA 0x00000000 -#define DDRSS2_PHY_225_DATA 0x00000000 -#define DDRSS2_PHY_226_DATA 0x00000000 -#define DDRSS2_PHY_227_DATA 0x00000000 -#define DDRSS2_PHY_228_DATA 0x00000000 -#define DDRSS2_PHY_229_DATA 0x00000000 -#define DDRSS2_PHY_230_DATA 0x00000000 -#define DDRSS2_PHY_231_DATA 0x00000000 -#define DDRSS2_PHY_232_DATA 0x00000000 -#define DDRSS2_PHY_233_DATA 0x00000000 -#define DDRSS2_PHY_234_DATA 0x00000000 -#define DDRSS2_PHY_235_DATA 0x00000000 -#define DDRSS2_PHY_236_DATA 0x00000000 -#define DDRSS2_PHY_237_DATA 0x00000000 -#define DDRSS2_PHY_238_DATA 0x00000000 -#define DDRSS2_PHY_239_DATA 0x00000000 -#define DDRSS2_PHY_240_DATA 0x00000000 -#define DDRSS2_PHY_241_DATA 0x00000000 -#define DDRSS2_PHY_242_DATA 0x00000000 -#define DDRSS2_PHY_243_DATA 0x00000000 -#define DDRSS2_PHY_244_DATA 0x00000000 -#define DDRSS2_PHY_245_DATA 0x00000000 -#define DDRSS2_PHY_246_DATA 0x00000000 -#define DDRSS2_PHY_247_DATA 0x00000000 -#define DDRSS2_PHY_248_DATA 0x00000000 -#define DDRSS2_PHY_249_DATA 0x00000000 -#define DDRSS2_PHY_250_DATA 0x00000000 -#define DDRSS2_PHY_251_DATA 0x00000000 -#define DDRSS2_PHY_252_DATA 0x00000000 -#define DDRSS2_PHY_253_DATA 0x00000000 -#define DDRSS2_PHY_254_DATA 0x00000000 -#define DDRSS2_PHY_255_DATA 0x00000000 -#define DDRSS2_PHY_256_DATA 0x000004F0 -#define DDRSS2_PHY_257_DATA 0x00000000 -#define DDRSS2_PHY_258_DATA 0x00030200 -#define DDRSS2_PHY_259_DATA 0x00000000 -#define DDRSS2_PHY_260_DATA 0x00000000 -#define DDRSS2_PHY_261_DATA 0x01030000 -#define DDRSS2_PHY_262_DATA 0x00010000 -#define DDRSS2_PHY_263_DATA 0x01030004 -#define DDRSS2_PHY_264_DATA 0x01000000 -#define DDRSS2_PHY_265_DATA 0x00000000 -#define DDRSS2_PHY_266_DATA 0x00000000 -#define DDRSS2_PHY_267_DATA 0x01000001 -#define DDRSS2_PHY_268_DATA 0x00000100 -#define DDRSS2_PHY_269_DATA 0x000800C0 -#define DDRSS2_PHY_270_DATA 0x060100CC -#define DDRSS2_PHY_271_DATA 0x00030066 -#define DDRSS2_PHY_272_DATA 0x00000000 -#define DDRSS2_PHY_273_DATA 0x00000301 -#define DDRSS2_PHY_274_DATA 0x0000AAAA -#define DDRSS2_PHY_275_DATA 0x00005555 -#define DDRSS2_PHY_276_DATA 0x0000B5B5 -#define DDRSS2_PHY_277_DATA 0x00004A4A -#define DDRSS2_PHY_278_DATA 0x00005656 -#define DDRSS2_PHY_279_DATA 0x0000A9A9 -#define DDRSS2_PHY_280_DATA 0x0000A9A9 -#define DDRSS2_PHY_281_DATA 0x0000B5B5 -#define DDRSS2_PHY_282_DATA 0x00000000 -#define DDRSS2_PHY_283_DATA 0x00000000 -#define DDRSS2_PHY_284_DATA 0x2A000000 -#define DDRSS2_PHY_285_DATA 0x00000808 -#define DDRSS2_PHY_286_DATA 0x0F000000 -#define DDRSS2_PHY_287_DATA 0x00000F0F -#define DDRSS2_PHY_288_DATA 0x10400000 -#define DDRSS2_PHY_289_DATA 0x0C002006 -#define DDRSS2_PHY_290_DATA 0x00000000 -#define DDRSS2_PHY_291_DATA 0x00000000 -#define DDRSS2_PHY_292_DATA 0x55555555 -#define DDRSS2_PHY_293_DATA 0xAAAAAAAA -#define DDRSS2_PHY_294_DATA 0x55555555 -#define DDRSS2_PHY_295_DATA 0xAAAAAAAA -#define DDRSS2_PHY_296_DATA 0x00005555 -#define DDRSS2_PHY_297_DATA 0x01000100 -#define DDRSS2_PHY_298_DATA 0x00800180 -#define DDRSS2_PHY_299_DATA 0x00000000 -#define DDRSS2_PHY_300_DATA 0x00000000 -#define DDRSS2_PHY_301_DATA 0x00000000 -#define DDRSS2_PHY_302_DATA 0x00000000 -#define DDRSS2_PHY_303_DATA 0x00000000 -#define DDRSS2_PHY_304_DATA 0x00000000 -#define DDRSS2_PHY_305_DATA 0x00000000 -#define DDRSS2_PHY_306_DATA 0x00000000 -#define DDRSS2_PHY_307_DATA 0x00000000 -#define DDRSS2_PHY_308_DATA 0x00000000 -#define DDRSS2_PHY_309_DATA 0x00000000 -#define DDRSS2_PHY_310_DATA 0x00000000 -#define DDRSS2_PHY_311_DATA 0x00000000 -#define DDRSS2_PHY_312_DATA 0x00000000 -#define DDRSS2_PHY_313_DATA 0x00000000 -#define DDRSS2_PHY_314_DATA 0x00000000 -#define DDRSS2_PHY_315_DATA 0x00000000 -#define DDRSS2_PHY_316_DATA 0x00000000 -#define DDRSS2_PHY_317_DATA 0x00000000 -#define DDRSS2_PHY_318_DATA 0x00000000 -#define DDRSS2_PHY_319_DATA 0x00000000 -#define DDRSS2_PHY_320_DATA 0x00000000 -#define DDRSS2_PHY_321_DATA 0x00000000 -#define DDRSS2_PHY_322_DATA 0x00000104 -#define DDRSS2_PHY_323_DATA 0x00000120 -#define DDRSS2_PHY_324_DATA 0x00000000 -#define DDRSS2_PHY_325_DATA 0x00000000 -#define DDRSS2_PHY_326_DATA 0x00000000 -#define DDRSS2_PHY_327_DATA 0x00000000 -#define DDRSS2_PHY_328_DATA 0x00000000 -#define DDRSS2_PHY_329_DATA 0x00000000 -#define DDRSS2_PHY_330_DATA 0x00000000 -#define DDRSS2_PHY_331_DATA 0x00000001 -#define DDRSS2_PHY_332_DATA 0x07FF0000 -#define DDRSS2_PHY_333_DATA 0x0080081F -#define DDRSS2_PHY_334_DATA 0x00081020 -#define DDRSS2_PHY_335_DATA 0x04010000 -#define DDRSS2_PHY_336_DATA 0x00000000 -#define DDRSS2_PHY_337_DATA 0x00000000 -#define DDRSS2_PHY_338_DATA 0x00000000 -#define DDRSS2_PHY_339_DATA 0x00000100 -#define DDRSS2_PHY_340_DATA 0x01CC0C01 -#define DDRSS2_PHY_341_DATA 0x1003CC0C -#define DDRSS2_PHY_342_DATA 0x20000140 -#define DDRSS2_PHY_343_DATA 0x07FF0200 -#define DDRSS2_PHY_344_DATA 0x0000DD01 -#define DDRSS2_PHY_345_DATA 0x10100303 -#define DDRSS2_PHY_346_DATA 0x10101010 -#define DDRSS2_PHY_347_DATA 0x10101010 -#define DDRSS2_PHY_348_DATA 0x00021010 -#define DDRSS2_PHY_349_DATA 0x00100010 -#define DDRSS2_PHY_350_DATA 0x00100010 -#define DDRSS2_PHY_351_DATA 0x00100010 -#define DDRSS2_PHY_352_DATA 0x00100010 -#define DDRSS2_PHY_353_DATA 0x00050010 -#define DDRSS2_PHY_354_DATA 0x51517041 -#define DDRSS2_PHY_355_DATA 0x31C06001 -#define DDRSS2_PHY_356_DATA 0x07AB0340 -#define DDRSS2_PHY_357_DATA 0x00C0C001 -#define DDRSS2_PHY_358_DATA 0x0E0D0001 -#define DDRSS2_PHY_359_DATA 0x10001000 -#define DDRSS2_PHY_360_DATA 0x0C083E42 -#define DDRSS2_PHY_361_DATA 0x0F0C3701 -#define DDRSS2_PHY_362_DATA 0x01000140 -#define DDRSS2_PHY_363_DATA 0x0C000420 -#define DDRSS2_PHY_364_DATA 0x00000198 -#define DDRSS2_PHY_365_DATA 0x0A0000D0 -#define DDRSS2_PHY_366_DATA 0x00030200 -#define DDRSS2_PHY_367_DATA 0x02800000 -#define DDRSS2_PHY_368_DATA 0x80800000 -#define DDRSS2_PHY_369_DATA 0x000E2010 -#define DDRSS2_PHY_370_DATA 0x76543210 -#define DDRSS2_PHY_371_DATA 0x00000008 -#define DDRSS2_PHY_372_DATA 0x02800280 -#define DDRSS2_PHY_373_DATA 0x02800280 -#define DDRSS2_PHY_374_DATA 0x02800280 -#define DDRSS2_PHY_375_DATA 0x02800280 -#define DDRSS2_PHY_376_DATA 0x00000280 -#define DDRSS2_PHY_377_DATA 0x0000A000 -#define DDRSS2_PHY_378_DATA 0x00A000A0 -#define DDRSS2_PHY_379_DATA 0x00A000A0 -#define DDRSS2_PHY_380_DATA 0x00A000A0 -#define DDRSS2_PHY_381_DATA 0x00A000A0 -#define DDRSS2_PHY_382_DATA 0x00A000A0 -#define DDRSS2_PHY_383_DATA 0x00A000A0 -#define DDRSS2_PHY_384_DATA 0x00A000A0 -#define DDRSS2_PHY_385_DATA 0x00A000A0 -#define DDRSS2_PHY_386_DATA 0x01C200A0 -#define DDRSS2_PHY_387_DATA 0x01A00005 -#define DDRSS2_PHY_388_DATA 0x00000000 -#define DDRSS2_PHY_389_DATA 0x00000000 -#define DDRSS2_PHY_390_DATA 0x00080200 -#define DDRSS2_PHY_391_DATA 0x00000000 -#define DDRSS2_PHY_392_DATA 0x20202000 -#define DDRSS2_PHY_393_DATA 0x20202020 -#define DDRSS2_PHY_394_DATA 0xF0F02020 -#define DDRSS2_PHY_395_DATA 0x00000000 -#define DDRSS2_PHY_396_DATA 0x00000000 -#define DDRSS2_PHY_397_DATA 0x00000000 -#define DDRSS2_PHY_398_DATA 0x00000000 -#define DDRSS2_PHY_399_DATA 0x00000000 -#define DDRSS2_PHY_400_DATA 0x00000000 -#define DDRSS2_PHY_401_DATA 0x00000000 -#define DDRSS2_PHY_402_DATA 0x00000000 -#define DDRSS2_PHY_403_DATA 0x00000000 -#define DDRSS2_PHY_404_DATA 0x00000000 -#define DDRSS2_PHY_405_DATA 0x00000000 -#define DDRSS2_PHY_406_DATA 0x00000000 -#define DDRSS2_PHY_407_DATA 0x00000000 -#define DDRSS2_PHY_408_DATA 0x00000000 -#define DDRSS2_PHY_409_DATA 0x00000000 -#define DDRSS2_PHY_410_DATA 0x00000000 -#define DDRSS2_PHY_411_DATA 0x00000000 -#define DDRSS2_PHY_412_DATA 0x00000000 -#define DDRSS2_PHY_413_DATA 0x00000000 -#define DDRSS2_PHY_414_DATA 0x00000000 -#define DDRSS2_PHY_415_DATA 0x00000000 -#define DDRSS2_PHY_416_DATA 0x00000000 -#define DDRSS2_PHY_417_DATA 0x00000000 -#define DDRSS2_PHY_418_DATA 0x00000000 -#define DDRSS2_PHY_419_DATA 0x00000000 -#define DDRSS2_PHY_420_DATA 0x00000000 -#define DDRSS2_PHY_421_DATA 0x00000000 -#define DDRSS2_PHY_422_DATA 0x00000000 -#define DDRSS2_PHY_423_DATA 0x00000000 -#define DDRSS2_PHY_424_DATA 0x00000000 -#define DDRSS2_PHY_425_DATA 0x00000000 -#define DDRSS2_PHY_426_DATA 0x00000000 -#define DDRSS2_PHY_427_DATA 0x00000000 -#define DDRSS2_PHY_428_DATA 0x00000000 -#define DDRSS2_PHY_429_DATA 0x00000000 -#define DDRSS2_PHY_430_DATA 0x00000000 -#define DDRSS2_PHY_431_DATA 0x00000000 -#define DDRSS2_PHY_432_DATA 0x00000000 -#define DDRSS2_PHY_433_DATA 0x00000000 -#define DDRSS2_PHY_434_DATA 0x00000000 -#define DDRSS2_PHY_435_DATA 0x00000000 -#define DDRSS2_PHY_436_DATA 0x00000000 -#define DDRSS2_PHY_437_DATA 0x00000000 -#define DDRSS2_PHY_438_DATA 0x00000000 -#define DDRSS2_PHY_439_DATA 0x00000000 -#define DDRSS2_PHY_440_DATA 0x00000000 -#define DDRSS2_PHY_441_DATA 0x00000000 -#define DDRSS2_PHY_442_DATA 0x00000000 -#define DDRSS2_PHY_443_DATA 0x00000000 -#define DDRSS2_PHY_444_DATA 0x00000000 -#define DDRSS2_PHY_445_DATA 0x00000000 -#define DDRSS2_PHY_446_DATA 0x00000000 -#define DDRSS2_PHY_447_DATA 0x00000000 -#define DDRSS2_PHY_448_DATA 0x00000000 -#define DDRSS2_PHY_449_DATA 0x00000000 -#define DDRSS2_PHY_450_DATA 0x00000000 -#define DDRSS2_PHY_451_DATA 0x00000000 -#define DDRSS2_PHY_452_DATA 0x00000000 -#define DDRSS2_PHY_453_DATA 0x00000000 -#define DDRSS2_PHY_454_DATA 0x00000000 -#define DDRSS2_PHY_455_DATA 0x00000000 -#define DDRSS2_PHY_456_DATA 0x00000000 -#define DDRSS2_PHY_457_DATA 0x00000000 -#define DDRSS2_PHY_458_DATA 0x00000000 -#define DDRSS2_PHY_459_DATA 0x00000000 -#define DDRSS2_PHY_460_DATA 0x00000000 -#define DDRSS2_PHY_461_DATA 0x00000000 -#define DDRSS2_PHY_462_DATA 0x00000000 -#define DDRSS2_PHY_463_DATA 0x00000000 -#define DDRSS2_PHY_464_DATA 0x00000000 -#define DDRSS2_PHY_465_DATA 0x00000000 -#define DDRSS2_PHY_466_DATA 0x00000000 -#define DDRSS2_PHY_467_DATA 0x00000000 -#define DDRSS2_PHY_468_DATA 0x00000000 -#define DDRSS2_PHY_469_DATA 0x00000000 -#define DDRSS2_PHY_470_DATA 0x00000000 -#define DDRSS2_PHY_471_DATA 0x00000000 -#define DDRSS2_PHY_472_DATA 0x00000000 -#define DDRSS2_PHY_473_DATA 0x00000000 -#define DDRSS2_PHY_474_DATA 0x00000000 -#define DDRSS2_PHY_475_DATA 0x00000000 -#define DDRSS2_PHY_476_DATA 0x00000000 -#define DDRSS2_PHY_477_DATA 0x00000000 -#define DDRSS2_PHY_478_DATA 0x00000000 -#define DDRSS2_PHY_479_DATA 0x00000000 -#define DDRSS2_PHY_480_DATA 0x00000000 -#define DDRSS2_PHY_481_DATA 0x00000000 -#define DDRSS2_PHY_482_DATA 0x00000000 -#define DDRSS2_PHY_483_DATA 0x00000000 -#define DDRSS2_PHY_484_DATA 0x00000000 -#define DDRSS2_PHY_485_DATA 0x00000000 -#define DDRSS2_PHY_486_DATA 0x00000000 -#define DDRSS2_PHY_487_DATA 0x00000000 -#define DDRSS2_PHY_488_DATA 0x00000000 -#define DDRSS2_PHY_489_DATA 0x00000000 -#define DDRSS2_PHY_490_DATA 0x00000000 -#define DDRSS2_PHY_491_DATA 0x00000000 -#define DDRSS2_PHY_492_DATA 0x00000000 -#define DDRSS2_PHY_493_DATA 0x00000000 -#define DDRSS2_PHY_494_DATA 0x00000000 -#define DDRSS2_PHY_495_DATA 0x00000000 -#define DDRSS2_PHY_496_DATA 0x00000000 -#define DDRSS2_PHY_497_DATA 0x00000000 -#define DDRSS2_PHY_498_DATA 0x00000000 -#define DDRSS2_PHY_499_DATA 0x00000000 -#define DDRSS2_PHY_500_DATA 0x00000000 -#define DDRSS2_PHY_501_DATA 0x00000000 -#define DDRSS2_PHY_502_DATA 0x00000000 -#define DDRSS2_PHY_503_DATA 0x00000000 -#define DDRSS2_PHY_504_DATA 0x00000000 -#define DDRSS2_PHY_505_DATA 0x00000000 -#define DDRSS2_PHY_506_DATA 0x00000000 -#define DDRSS2_PHY_507_DATA 0x00000000 -#define DDRSS2_PHY_508_DATA 0x00000000 -#define DDRSS2_PHY_509_DATA 0x00000000 -#define DDRSS2_PHY_510_DATA 0x00000000 -#define DDRSS2_PHY_511_DATA 0x00000000 -#define DDRSS2_PHY_512_DATA 0x000004F0 -#define DDRSS2_PHY_513_DATA 0x00000000 -#define DDRSS2_PHY_514_DATA 0x00030200 -#define DDRSS2_PHY_515_DATA 0x00000000 -#define DDRSS2_PHY_516_DATA 0x00000000 -#define DDRSS2_PHY_517_DATA 0x01030000 -#define DDRSS2_PHY_518_DATA 0x00010000 -#define DDRSS2_PHY_519_DATA 0x01030004 -#define DDRSS2_PHY_520_DATA 0x01000000 -#define DDRSS2_PHY_521_DATA 0x00000000 -#define DDRSS2_PHY_522_DATA 0x00000000 -#define DDRSS2_PHY_523_DATA 0x01000001 -#define DDRSS2_PHY_524_DATA 0x00000100 -#define DDRSS2_PHY_525_DATA 0x000800C0 -#define DDRSS2_PHY_526_DATA 0x060100CC -#define DDRSS2_PHY_527_DATA 0x00030066 -#define DDRSS2_PHY_528_DATA 0x00000000 -#define DDRSS2_PHY_529_DATA 0x00000301 -#define DDRSS2_PHY_530_DATA 0x0000AAAA -#define DDRSS2_PHY_531_DATA 0x00005555 -#define DDRSS2_PHY_532_DATA 0x0000B5B5 -#define DDRSS2_PHY_533_DATA 0x00004A4A -#define DDRSS2_PHY_534_DATA 0x00005656 -#define DDRSS2_PHY_535_DATA 0x0000A9A9 -#define DDRSS2_PHY_536_DATA 0x0000A9A9 -#define DDRSS2_PHY_537_DATA 0x0000B5B5 -#define DDRSS2_PHY_538_DATA 0x00000000 -#define DDRSS2_PHY_539_DATA 0x00000000 -#define DDRSS2_PHY_540_DATA 0x2A000000 -#define DDRSS2_PHY_541_DATA 0x00000808 -#define DDRSS2_PHY_542_DATA 0x0F000000 -#define DDRSS2_PHY_543_DATA 0x00000F0F -#define DDRSS2_PHY_544_DATA 0x10400000 -#define DDRSS2_PHY_545_DATA 0x0C002006 -#define DDRSS2_PHY_546_DATA 0x00000000 -#define DDRSS2_PHY_547_DATA 0x00000000 -#define DDRSS2_PHY_548_DATA 0x55555555 -#define DDRSS2_PHY_549_DATA 0xAAAAAAAA -#define DDRSS2_PHY_550_DATA 0x55555555 -#define DDRSS2_PHY_551_DATA 0xAAAAAAAA -#define DDRSS2_PHY_552_DATA 0x00005555 -#define DDRSS2_PHY_553_DATA 0x01000100 -#define DDRSS2_PHY_554_DATA 0x00800180 -#define DDRSS2_PHY_555_DATA 0x00000001 -#define DDRSS2_PHY_556_DATA 0x00000000 -#define DDRSS2_PHY_557_DATA 0x00000000 -#define DDRSS2_PHY_558_DATA 0x00000000 -#define DDRSS2_PHY_559_DATA 0x00000000 -#define DDRSS2_PHY_560_DATA 0x00000000 -#define DDRSS2_PHY_561_DATA 0x00000000 -#define DDRSS2_PHY_562_DATA 0x00000000 -#define DDRSS2_PHY_563_DATA 0x00000000 -#define DDRSS2_PHY_564_DATA 0x00000000 -#define DDRSS2_PHY_565_DATA 0x00000000 -#define DDRSS2_PHY_566_DATA 0x00000000 -#define DDRSS2_PHY_567_DATA 0x00000000 -#define DDRSS2_PHY_568_DATA 0x00000000 -#define DDRSS2_PHY_569_DATA 0x00000000 -#define DDRSS2_PHY_570_DATA 0x00000000 -#define DDRSS2_PHY_571_DATA 0x00000000 -#define DDRSS2_PHY_572_DATA 0x00000000 -#define DDRSS2_PHY_573_DATA 0x00000000 -#define DDRSS2_PHY_574_DATA 0x00000000 -#define DDRSS2_PHY_575_DATA 0x00000000 -#define DDRSS2_PHY_576_DATA 0x00000000 -#define DDRSS2_PHY_577_DATA 0x00000000 -#define DDRSS2_PHY_578_DATA 0x00000104 -#define DDRSS2_PHY_579_DATA 0x00000120 -#define DDRSS2_PHY_580_DATA 0x00000000 -#define DDRSS2_PHY_581_DATA 0x00000000 -#define DDRSS2_PHY_582_DATA 0x00000000 -#define DDRSS2_PHY_583_DATA 0x00000000 -#define DDRSS2_PHY_584_DATA 0x00000000 -#define DDRSS2_PHY_585_DATA 0x00000000 -#define DDRSS2_PHY_586_DATA 0x00000000 -#define DDRSS2_PHY_587_DATA 0x00000001 -#define DDRSS2_PHY_588_DATA 0x07FF0000 -#define DDRSS2_PHY_589_DATA 0x0080081F -#define DDRSS2_PHY_590_DATA 0x00081020 -#define DDRSS2_PHY_591_DATA 0x04010000 -#define DDRSS2_PHY_592_DATA 0x00000000 -#define DDRSS2_PHY_593_DATA 0x00000000 -#define DDRSS2_PHY_594_DATA 0x00000000 -#define DDRSS2_PHY_595_DATA 0x00000100 -#define DDRSS2_PHY_596_DATA 0x01CC0C01 -#define DDRSS2_PHY_597_DATA 0x1003CC0C -#define DDRSS2_PHY_598_DATA 0x20000140 -#define DDRSS2_PHY_599_DATA 0x07FF0200 -#define DDRSS2_PHY_600_DATA 0x0000DD01 -#define DDRSS2_PHY_601_DATA 0x10100303 -#define DDRSS2_PHY_602_DATA 0x10101010 -#define DDRSS2_PHY_603_DATA 0x10101010 -#define DDRSS2_PHY_604_DATA 0x00021010 -#define DDRSS2_PHY_605_DATA 0x00100010 -#define DDRSS2_PHY_606_DATA 0x00100010 -#define DDRSS2_PHY_607_DATA 0x00100010 -#define DDRSS2_PHY_608_DATA 0x00100010 -#define DDRSS2_PHY_609_DATA 0x00050010 -#define DDRSS2_PHY_610_DATA 0x51517041 -#define DDRSS2_PHY_611_DATA 0x31C06001 -#define DDRSS2_PHY_612_DATA 0x07AB0340 -#define DDRSS2_PHY_613_DATA 0x00C0C001 -#define DDRSS2_PHY_614_DATA 0x0E0D0001 -#define DDRSS2_PHY_615_DATA 0x10001000 -#define DDRSS2_PHY_616_DATA 0x0C083E42 -#define DDRSS2_PHY_617_DATA 0x0F0C3701 -#define DDRSS2_PHY_618_DATA 0x01000140 -#define DDRSS2_PHY_619_DATA 0x0C000420 -#define DDRSS2_PHY_620_DATA 0x00000198 -#define DDRSS2_PHY_621_DATA 0x0A0000D0 -#define DDRSS2_PHY_622_DATA 0x00030200 -#define DDRSS2_PHY_623_DATA 0x02800000 -#define DDRSS2_PHY_624_DATA 0x80800000 -#define DDRSS2_PHY_625_DATA 0x000E2010 -#define DDRSS2_PHY_626_DATA 0x76543210 -#define DDRSS2_PHY_627_DATA 0x00000008 -#define DDRSS2_PHY_628_DATA 0x02800280 -#define DDRSS2_PHY_629_DATA 0x02800280 -#define DDRSS2_PHY_630_DATA 0x02800280 -#define DDRSS2_PHY_631_DATA 0x02800280 -#define DDRSS2_PHY_632_DATA 0x00000280 -#define DDRSS2_PHY_633_DATA 0x0000A000 -#define DDRSS2_PHY_634_DATA 0x00A000A0 -#define DDRSS2_PHY_635_DATA 0x00A000A0 -#define DDRSS2_PHY_636_DATA 0x00A000A0 -#define DDRSS2_PHY_637_DATA 0x00A000A0 -#define DDRSS2_PHY_638_DATA 0x00A000A0 -#define DDRSS2_PHY_639_DATA 0x00A000A0 -#define DDRSS2_PHY_640_DATA 0x00A000A0 -#define DDRSS2_PHY_641_DATA 0x00A000A0 -#define DDRSS2_PHY_642_DATA 0x01C200A0 -#define DDRSS2_PHY_643_DATA 0x01A00005 -#define DDRSS2_PHY_644_DATA 0x00000000 -#define DDRSS2_PHY_645_DATA 0x00000000 -#define DDRSS2_PHY_646_DATA 0x00080200 -#define DDRSS2_PHY_647_DATA 0x00000000 -#define DDRSS2_PHY_648_DATA 0x20202000 -#define DDRSS2_PHY_649_DATA 0x20202020 -#define DDRSS2_PHY_650_DATA 0xF0F02020 -#define DDRSS2_PHY_651_DATA 0x00000000 -#define DDRSS2_PHY_652_DATA 0x00000000 -#define DDRSS2_PHY_653_DATA 0x00000000 -#define DDRSS2_PHY_654_DATA 0x00000000 -#define DDRSS2_PHY_655_DATA 0x00000000 -#define DDRSS2_PHY_656_DATA 0x00000000 -#define DDRSS2_PHY_657_DATA 0x00000000 -#define DDRSS2_PHY_658_DATA 0x00000000 -#define DDRSS2_PHY_659_DATA 0x00000000 -#define DDRSS2_PHY_660_DATA 0x00000000 -#define DDRSS2_PHY_661_DATA 0x00000000 -#define DDRSS2_PHY_662_DATA 0x00000000 -#define DDRSS2_PHY_663_DATA 0x00000000 -#define DDRSS2_PHY_664_DATA 0x00000000 -#define DDRSS2_PHY_665_DATA 0x00000000 -#define DDRSS2_PHY_666_DATA 0x00000000 -#define DDRSS2_PHY_667_DATA 0x00000000 -#define DDRSS2_PHY_668_DATA 0x00000000 -#define DDRSS2_PHY_669_DATA 0x00000000 -#define DDRSS2_PHY_670_DATA 0x00000000 -#define DDRSS2_PHY_671_DATA 0x00000000 -#define DDRSS2_PHY_672_DATA 0x00000000 -#define DDRSS2_PHY_673_DATA 0x00000000 -#define DDRSS2_PHY_674_DATA 0x00000000 -#define DDRSS2_PHY_675_DATA 0x00000000 -#define DDRSS2_PHY_676_DATA 0x00000000 -#define DDRSS2_PHY_677_DATA 0x00000000 -#define DDRSS2_PHY_678_DATA 0x00000000 -#define DDRSS2_PHY_679_DATA 0x00000000 -#define DDRSS2_PHY_680_DATA 0x00000000 -#define DDRSS2_PHY_681_DATA 0x00000000 -#define DDRSS2_PHY_682_DATA 0x00000000 -#define DDRSS2_PHY_683_DATA 0x00000000 -#define DDRSS2_PHY_684_DATA 0x00000000 -#define DDRSS2_PHY_685_DATA 0x00000000 -#define DDRSS2_PHY_686_DATA 0x00000000 -#define DDRSS2_PHY_687_DATA 0x00000000 -#define DDRSS2_PHY_688_DATA 0x00000000 -#define DDRSS2_PHY_689_DATA 0x00000000 -#define DDRSS2_PHY_690_DATA 0x00000000 -#define DDRSS2_PHY_691_DATA 0x00000000 -#define DDRSS2_PHY_692_DATA 0x00000000 -#define DDRSS2_PHY_693_DATA 0x00000000 -#define DDRSS2_PHY_694_DATA 0x00000000 -#define DDRSS2_PHY_695_DATA 0x00000000 -#define DDRSS2_PHY_696_DATA 0x00000000 -#define DDRSS2_PHY_697_DATA 0x00000000 -#define DDRSS2_PHY_698_DATA 0x00000000 -#define DDRSS2_PHY_699_DATA 0x00000000 -#define DDRSS2_PHY_700_DATA 0x00000000 -#define DDRSS2_PHY_701_DATA 0x00000000 -#define DDRSS2_PHY_702_DATA 0x00000000 -#define DDRSS2_PHY_703_DATA 0x00000000 -#define DDRSS2_PHY_704_DATA 0x00000000 -#define DDRSS2_PHY_705_DATA 0x00000000 -#define DDRSS2_PHY_706_DATA 0x00000000 -#define DDRSS2_PHY_707_DATA 0x00000000 -#define DDRSS2_PHY_708_DATA 0x00000000 -#define DDRSS2_PHY_709_DATA 0x00000000 -#define DDRSS2_PHY_710_DATA 0x00000000 -#define DDRSS2_PHY_711_DATA 0x00000000 -#define DDRSS2_PHY_712_DATA 0x00000000 -#define DDRSS2_PHY_713_DATA 0x00000000 -#define DDRSS2_PHY_714_DATA 0x00000000 -#define DDRSS2_PHY_715_DATA 0x00000000 -#define DDRSS2_PHY_716_DATA 0x00000000 -#define DDRSS2_PHY_717_DATA 0x00000000 -#define DDRSS2_PHY_718_DATA 0x00000000 -#define DDRSS2_PHY_719_DATA 0x00000000 -#define DDRSS2_PHY_720_DATA 0x00000000 -#define DDRSS2_PHY_721_DATA 0x00000000 -#define DDRSS2_PHY_722_DATA 0x00000000 -#define DDRSS2_PHY_723_DATA 0x00000000 -#define DDRSS2_PHY_724_DATA 0x00000000 -#define DDRSS2_PHY_725_DATA 0x00000000 -#define DDRSS2_PHY_726_DATA 0x00000000 -#define DDRSS2_PHY_727_DATA 0x00000000 -#define DDRSS2_PHY_728_DATA 0x00000000 -#define DDRSS2_PHY_729_DATA 0x00000000 -#define DDRSS2_PHY_730_DATA 0x00000000 -#define DDRSS2_PHY_731_DATA 0x00000000 -#define DDRSS2_PHY_732_DATA 0x00000000 -#define DDRSS2_PHY_733_DATA 0x00000000 -#define DDRSS2_PHY_734_DATA 0x00000000 -#define DDRSS2_PHY_735_DATA 0x00000000 -#define DDRSS2_PHY_736_DATA 0x00000000 -#define DDRSS2_PHY_737_DATA 0x00000000 -#define DDRSS2_PHY_738_DATA 0x00000000 -#define DDRSS2_PHY_739_DATA 0x00000000 -#define DDRSS2_PHY_740_DATA 0x00000000 -#define DDRSS2_PHY_741_DATA 0x00000000 -#define DDRSS2_PHY_742_DATA 0x00000000 -#define DDRSS2_PHY_743_DATA 0x00000000 -#define DDRSS2_PHY_744_DATA 0x00000000 -#define DDRSS2_PHY_745_DATA 0x00000000 -#define DDRSS2_PHY_746_DATA 0x00000000 -#define DDRSS2_PHY_747_DATA 0x00000000 -#define DDRSS2_PHY_748_DATA 0x00000000 -#define DDRSS2_PHY_749_DATA 0x00000000 -#define DDRSS2_PHY_750_DATA 0x00000000 -#define DDRSS2_PHY_751_DATA 0x00000000 -#define DDRSS2_PHY_752_DATA 0x00000000 -#define DDRSS2_PHY_753_DATA 0x00000000 -#define DDRSS2_PHY_754_DATA 0x00000000 -#define DDRSS2_PHY_755_DATA 0x00000000 -#define DDRSS2_PHY_756_DATA 0x00000000 -#define DDRSS2_PHY_757_DATA 0x00000000 -#define DDRSS2_PHY_758_DATA 0x00000000 -#define DDRSS2_PHY_759_DATA 0x00000000 -#define DDRSS2_PHY_760_DATA 0x00000000 -#define DDRSS2_PHY_761_DATA 0x00000000 -#define DDRSS2_PHY_762_DATA 0x00000000 -#define DDRSS2_PHY_763_DATA 0x00000000 -#define DDRSS2_PHY_764_DATA 0x00000000 -#define DDRSS2_PHY_765_DATA 0x00000000 -#define DDRSS2_PHY_766_DATA 0x00000000 -#define DDRSS2_PHY_767_DATA 0x00000000 -#define DDRSS2_PHY_768_DATA 0x000004F0 -#define DDRSS2_PHY_769_DATA 0x00000000 -#define DDRSS2_PHY_770_DATA 0x00030200 -#define DDRSS2_PHY_771_DATA 0x00000000 -#define DDRSS2_PHY_772_DATA 0x00000000 -#define DDRSS2_PHY_773_DATA 0x01030000 -#define DDRSS2_PHY_774_DATA 0x00010000 -#define DDRSS2_PHY_775_DATA 0x01030004 -#define DDRSS2_PHY_776_DATA 0x01000000 -#define DDRSS2_PHY_777_DATA 0x00000000 -#define DDRSS2_PHY_778_DATA 0x00000000 -#define DDRSS2_PHY_779_DATA 0x01000001 -#define DDRSS2_PHY_780_DATA 0x00000100 -#define DDRSS2_PHY_781_DATA 0x000800C0 -#define DDRSS2_PHY_782_DATA 0x060100CC -#define DDRSS2_PHY_783_DATA 0x00030066 -#define DDRSS2_PHY_784_DATA 0x00000000 -#define DDRSS2_PHY_785_DATA 0x00000301 -#define DDRSS2_PHY_786_DATA 0x0000AAAA -#define DDRSS2_PHY_787_DATA 0x00005555 -#define DDRSS2_PHY_788_DATA 0x0000B5B5 -#define DDRSS2_PHY_789_DATA 0x00004A4A -#define DDRSS2_PHY_790_DATA 0x00005656 -#define DDRSS2_PHY_791_DATA 0x0000A9A9 -#define DDRSS2_PHY_792_DATA 0x0000A9A9 -#define DDRSS2_PHY_793_DATA 0x0000B5B5 -#define DDRSS2_PHY_794_DATA 0x00000000 -#define DDRSS2_PHY_795_DATA 0x00000000 -#define DDRSS2_PHY_796_DATA 0x2A000000 -#define DDRSS2_PHY_797_DATA 0x00000808 -#define DDRSS2_PHY_798_DATA 0x0F000000 -#define DDRSS2_PHY_799_DATA 0x00000F0F -#define DDRSS2_PHY_800_DATA 0x10400000 -#define DDRSS2_PHY_801_DATA 0x0C002006 -#define DDRSS2_PHY_802_DATA 0x00000000 -#define DDRSS2_PHY_803_DATA 0x00000000 -#define DDRSS2_PHY_804_DATA 0x55555555 -#define DDRSS2_PHY_805_DATA 0xAAAAAAAA -#define DDRSS2_PHY_806_DATA 0x55555555 -#define DDRSS2_PHY_807_DATA 0xAAAAAAAA -#define DDRSS2_PHY_808_DATA 0x00005555 -#define DDRSS2_PHY_809_DATA 0x01000100 -#define DDRSS2_PHY_810_DATA 0x00800180 -#define DDRSS2_PHY_811_DATA 0x00000000 -#define DDRSS2_PHY_812_DATA 0x00000000 -#define DDRSS2_PHY_813_DATA 0x00000000 -#define DDRSS2_PHY_814_DATA 0x00000000 -#define DDRSS2_PHY_815_DATA 0x00000000 -#define DDRSS2_PHY_816_DATA 0x00000000 -#define DDRSS2_PHY_817_DATA 0x00000000 -#define DDRSS2_PHY_818_DATA 0x00000000 -#define DDRSS2_PHY_819_DATA 0x00000000 -#define DDRSS2_PHY_820_DATA 0x00000000 -#define DDRSS2_PHY_821_DATA 0x00000000 -#define DDRSS2_PHY_822_DATA 0x00000000 -#define DDRSS2_PHY_823_DATA 0x00000000 -#define DDRSS2_PHY_824_DATA 0x00000000 -#define DDRSS2_PHY_825_DATA 0x00000000 -#define DDRSS2_PHY_826_DATA 0x00000000 -#define DDRSS2_PHY_827_DATA 0x00000000 -#define DDRSS2_PHY_828_DATA 0x00000000 -#define DDRSS2_PHY_829_DATA 0x00000000 -#define DDRSS2_PHY_830_DATA 0x00000000 -#define DDRSS2_PHY_831_DATA 0x00000000 -#define DDRSS2_PHY_832_DATA 0x00000000 -#define DDRSS2_PHY_833_DATA 0x00000000 -#define DDRSS2_PHY_834_DATA 0x00000104 -#define DDRSS2_PHY_835_DATA 0x00000120 -#define DDRSS2_PHY_836_DATA 0x00000000 -#define DDRSS2_PHY_837_DATA 0x00000000 -#define DDRSS2_PHY_838_DATA 0x00000000 -#define DDRSS2_PHY_839_DATA 0x00000000 -#define DDRSS2_PHY_840_DATA 0x00000000 -#define DDRSS2_PHY_841_DATA 0x00000000 -#define DDRSS2_PHY_842_DATA 0x00000000 -#define DDRSS2_PHY_843_DATA 0x00000001 -#define DDRSS2_PHY_844_DATA 0x07FF0000 -#define DDRSS2_PHY_845_DATA 0x0080081F -#define DDRSS2_PHY_846_DATA 0x00081020 -#define DDRSS2_PHY_847_DATA 0x04010000 -#define DDRSS2_PHY_848_DATA 0x00000000 -#define DDRSS2_PHY_849_DATA 0x00000000 -#define DDRSS2_PHY_850_DATA 0x00000000 -#define DDRSS2_PHY_851_DATA 0x00000100 -#define DDRSS2_PHY_852_DATA 0x01CC0C01 -#define DDRSS2_PHY_853_DATA 0x1003CC0C -#define DDRSS2_PHY_854_DATA 0x20000140 -#define DDRSS2_PHY_855_DATA 0x07FF0200 -#define DDRSS2_PHY_856_DATA 0x0000DD01 -#define DDRSS2_PHY_857_DATA 0x10100303 -#define DDRSS2_PHY_858_DATA 0x10101010 -#define DDRSS2_PHY_859_DATA 0x10101010 -#define DDRSS2_PHY_860_DATA 0x00021010 -#define DDRSS2_PHY_861_DATA 0x00100010 -#define DDRSS2_PHY_862_DATA 0x00100010 -#define DDRSS2_PHY_863_DATA 0x00100010 -#define DDRSS2_PHY_864_DATA 0x00100010 -#define DDRSS2_PHY_865_DATA 0x00050010 -#define DDRSS2_PHY_866_DATA 0x51517041 -#define DDRSS2_PHY_867_DATA 0x31C06001 -#define DDRSS2_PHY_868_DATA 0x07AB0340 -#define DDRSS2_PHY_869_DATA 0x00C0C001 -#define DDRSS2_PHY_870_DATA 0x0E0D0001 -#define DDRSS2_PHY_871_DATA 0x10001000 -#define DDRSS2_PHY_872_DATA 0x0C083E42 -#define DDRSS2_PHY_873_DATA 0x0F0C3701 -#define DDRSS2_PHY_874_DATA 0x01000140 -#define DDRSS2_PHY_875_DATA 0x0C000420 -#define DDRSS2_PHY_876_DATA 0x00000198 -#define DDRSS2_PHY_877_DATA 0x0A0000D0 -#define DDRSS2_PHY_878_DATA 0x00030200 -#define DDRSS2_PHY_879_DATA 0x02800000 -#define DDRSS2_PHY_880_DATA 0x80800000 -#define DDRSS2_PHY_881_DATA 0x000E2010 -#define DDRSS2_PHY_882_DATA 0x76543210 -#define DDRSS2_PHY_883_DATA 0x00000008 -#define DDRSS2_PHY_884_DATA 0x02800280 -#define DDRSS2_PHY_885_DATA 0x02800280 -#define DDRSS2_PHY_886_DATA 0x02800280 -#define DDRSS2_PHY_887_DATA 0x02800280 -#define DDRSS2_PHY_888_DATA 0x00000280 -#define DDRSS2_PHY_889_DATA 0x0000A000 -#define DDRSS2_PHY_890_DATA 0x00A000A0 -#define DDRSS2_PHY_891_DATA 0x00A000A0 -#define DDRSS2_PHY_892_DATA 0x00A000A0 -#define DDRSS2_PHY_893_DATA 0x00A000A0 -#define DDRSS2_PHY_894_DATA 0x00A000A0 -#define DDRSS2_PHY_895_DATA 0x00A000A0 -#define DDRSS2_PHY_896_DATA 0x00A000A0 -#define DDRSS2_PHY_897_DATA 0x00A000A0 -#define DDRSS2_PHY_898_DATA 0x01C200A0 -#define DDRSS2_PHY_899_DATA 0x01A00005 -#define DDRSS2_PHY_900_DATA 0x00000000 -#define DDRSS2_PHY_901_DATA 0x00000000 -#define DDRSS2_PHY_902_DATA 0x00080200 -#define DDRSS2_PHY_903_DATA 0x00000000 -#define DDRSS2_PHY_904_DATA 0x20202000 -#define DDRSS2_PHY_905_DATA 0x20202020 -#define DDRSS2_PHY_906_DATA 0xF0F02020 -#define DDRSS2_PHY_907_DATA 0x00000000 -#define DDRSS2_PHY_908_DATA 0x00000000 -#define DDRSS2_PHY_909_DATA 0x00000000 -#define DDRSS2_PHY_910_DATA 0x00000000 -#define DDRSS2_PHY_911_DATA 0x00000000 -#define DDRSS2_PHY_912_DATA 0x00000000 -#define DDRSS2_PHY_913_DATA 0x00000000 -#define DDRSS2_PHY_914_DATA 0x00000000 -#define DDRSS2_PHY_915_DATA 0x00000000 -#define DDRSS2_PHY_916_DATA 0x00000000 -#define DDRSS2_PHY_917_DATA 0x00000000 -#define DDRSS2_PHY_918_DATA 0x00000000 -#define DDRSS2_PHY_919_DATA 0x00000000 -#define DDRSS2_PHY_920_DATA 0x00000000 -#define DDRSS2_PHY_921_DATA 0x00000000 -#define DDRSS2_PHY_922_DATA 0x00000000 -#define DDRSS2_PHY_923_DATA 0x00000000 -#define DDRSS2_PHY_924_DATA 0x00000000 -#define DDRSS2_PHY_925_DATA 0x00000000 -#define DDRSS2_PHY_926_DATA 0x00000000 -#define DDRSS2_PHY_927_DATA 0x00000000 -#define DDRSS2_PHY_928_DATA 0x00000000 -#define DDRSS2_PHY_929_DATA 0x00000000 -#define DDRSS2_PHY_930_DATA 0x00000000 -#define DDRSS2_PHY_931_DATA 0x00000000 -#define DDRSS2_PHY_932_DATA 0x00000000 -#define DDRSS2_PHY_933_DATA 0x00000000 -#define DDRSS2_PHY_934_DATA 0x00000000 -#define DDRSS2_PHY_935_DATA 0x00000000 -#define DDRSS2_PHY_936_DATA 0x00000000 -#define DDRSS2_PHY_937_DATA 0x00000000 -#define DDRSS2_PHY_938_DATA 0x00000000 -#define DDRSS2_PHY_939_DATA 0x00000000 -#define DDRSS2_PHY_940_DATA 0x00000000 -#define DDRSS2_PHY_941_DATA 0x00000000 -#define DDRSS2_PHY_942_DATA 0x00000000 -#define DDRSS2_PHY_943_DATA 0x00000000 -#define DDRSS2_PHY_944_DATA 0x00000000 -#define DDRSS2_PHY_945_DATA 0x00000000 -#define DDRSS2_PHY_946_DATA 0x00000000 -#define DDRSS2_PHY_947_DATA 0x00000000 -#define DDRSS2_PHY_948_DATA 0x00000000 -#define DDRSS2_PHY_949_DATA 0x00000000 -#define DDRSS2_PHY_950_DATA 0x00000000 -#define DDRSS2_PHY_951_DATA 0x00000000 -#define DDRSS2_PHY_952_DATA 0x00000000 -#define DDRSS2_PHY_953_DATA 0x00000000 -#define DDRSS2_PHY_954_DATA 0x00000000 -#define DDRSS2_PHY_955_DATA 0x00000000 -#define DDRSS2_PHY_956_DATA 0x00000000 -#define DDRSS2_PHY_957_DATA 0x00000000 -#define DDRSS2_PHY_958_DATA 0x00000000 -#define DDRSS2_PHY_959_DATA 0x00000000 -#define DDRSS2_PHY_960_DATA 0x00000000 -#define DDRSS2_PHY_961_DATA 0x00000000 -#define DDRSS2_PHY_962_DATA 0x00000000 -#define DDRSS2_PHY_963_DATA 0x00000000 -#define DDRSS2_PHY_964_DATA 0x00000000 -#define DDRSS2_PHY_965_DATA 0x00000000 -#define DDRSS2_PHY_966_DATA 0x00000000 -#define DDRSS2_PHY_967_DATA 0x00000000 -#define DDRSS2_PHY_968_DATA 0x00000000 -#define DDRSS2_PHY_969_DATA 0x00000000 -#define DDRSS2_PHY_970_DATA 0x00000000 -#define DDRSS2_PHY_971_DATA 0x00000000 -#define DDRSS2_PHY_972_DATA 0x00000000 -#define DDRSS2_PHY_973_DATA 0x00000000 -#define DDRSS2_PHY_974_DATA 0x00000000 -#define DDRSS2_PHY_975_DATA 0x00000000 -#define DDRSS2_PHY_976_DATA 0x00000000 -#define DDRSS2_PHY_977_DATA 0x00000000 -#define DDRSS2_PHY_978_DATA 0x00000000 -#define DDRSS2_PHY_979_DATA 0x00000000 -#define DDRSS2_PHY_980_DATA 0x00000000 -#define DDRSS2_PHY_981_DATA 0x00000000 -#define DDRSS2_PHY_982_DATA 0x00000000 -#define DDRSS2_PHY_983_DATA 0x00000000 -#define DDRSS2_PHY_984_DATA 0x00000000 -#define DDRSS2_PHY_985_DATA 0x00000000 -#define DDRSS2_PHY_986_DATA 0x00000000 -#define DDRSS2_PHY_987_DATA 0x00000000 -#define DDRSS2_PHY_988_DATA 0x00000000 -#define DDRSS2_PHY_989_DATA 0x00000000 -#define DDRSS2_PHY_990_DATA 0x00000000 -#define DDRSS2_PHY_991_DATA 0x00000000 -#define DDRSS2_PHY_992_DATA 0x00000000 -#define DDRSS2_PHY_993_DATA 0x00000000 -#define DDRSS2_PHY_994_DATA 0x00000000 -#define DDRSS2_PHY_995_DATA 0x00000000 -#define DDRSS2_PHY_996_DATA 0x00000000 -#define DDRSS2_PHY_997_DATA 0x00000000 -#define DDRSS2_PHY_998_DATA 0x00000000 -#define DDRSS2_PHY_999_DATA 0x00000000 -#define DDRSS2_PHY_1000_DATA 0x00000000 -#define DDRSS2_PHY_1001_DATA 0x00000000 -#define DDRSS2_PHY_1002_DATA 0x00000000 -#define DDRSS2_PHY_1003_DATA 0x00000000 -#define DDRSS2_PHY_1004_DATA 0x00000000 -#define DDRSS2_PHY_1005_DATA 0x00000000 -#define DDRSS2_PHY_1006_DATA 0x00000000 -#define DDRSS2_PHY_1007_DATA 0x00000000 -#define DDRSS2_PHY_1008_DATA 0x00000000 -#define DDRSS2_PHY_1009_DATA 0x00000000 -#define DDRSS2_PHY_1010_DATA 0x00000000 -#define DDRSS2_PHY_1011_DATA 0x00000000 -#define DDRSS2_PHY_1012_DATA 0x00000000 -#define DDRSS2_PHY_1013_DATA 0x00000000 -#define DDRSS2_PHY_1014_DATA 0x00000000 -#define DDRSS2_PHY_1015_DATA 0x00000000 -#define DDRSS2_PHY_1016_DATA 0x00000000 -#define DDRSS2_PHY_1017_DATA 0x00000000 -#define DDRSS2_PHY_1018_DATA 0x00000000 -#define DDRSS2_PHY_1019_DATA 0x00000000 -#define DDRSS2_PHY_1020_DATA 0x00000000 -#define DDRSS2_PHY_1021_DATA 0x00000000 -#define DDRSS2_PHY_1022_DATA 0x00000000 -#define DDRSS2_PHY_1023_DATA 0x00000000 -#define DDRSS2_PHY_1024_DATA 0x00000000 -#define DDRSS2_PHY_1025_DATA 0x00000000 -#define DDRSS2_PHY_1026_DATA 0x00000000 -#define DDRSS2_PHY_1027_DATA 0x00000000 -#define DDRSS2_PHY_1028_DATA 0x00000000 -#define DDRSS2_PHY_1029_DATA 0x00000100 -#define DDRSS2_PHY_1030_DATA 0x00000200 -#define DDRSS2_PHY_1031_DATA 0x00000000 -#define DDRSS2_PHY_1032_DATA 0x00000000 -#define DDRSS2_PHY_1033_DATA 0x00000000 -#define DDRSS2_PHY_1034_DATA 0x00000000 -#define DDRSS2_PHY_1035_DATA 0x00400000 -#define DDRSS2_PHY_1036_DATA 0x00000080 -#define DDRSS2_PHY_1037_DATA 0x00DCBA98 -#define DDRSS2_PHY_1038_DATA 0x03000000 -#define DDRSS2_PHY_1039_DATA 0x00200000 -#define DDRSS2_PHY_1040_DATA 0x00000000 -#define DDRSS2_PHY_1041_DATA 0x00000000 -#define DDRSS2_PHY_1042_DATA 0x00000000 -#define DDRSS2_PHY_1043_DATA 0x00000000 -#define DDRSS2_PHY_1044_DATA 0x00000000 -#define DDRSS2_PHY_1045_DATA 0x0000002A -#define DDRSS2_PHY_1046_DATA 0x00000015 -#define DDRSS2_PHY_1047_DATA 0x00000015 -#define DDRSS2_PHY_1048_DATA 0x0000002A -#define DDRSS2_PHY_1049_DATA 0x00000033 -#define DDRSS2_PHY_1050_DATA 0x0000000C -#define DDRSS2_PHY_1051_DATA 0x0000000C -#define DDRSS2_PHY_1052_DATA 0x00000033 -#define DDRSS2_PHY_1053_DATA 0x00543210 -#define DDRSS2_PHY_1054_DATA 0x003F0000 -#define DDRSS2_PHY_1055_DATA 0x000F013F -#define DDRSS2_PHY_1056_DATA 0x20202003 -#define DDRSS2_PHY_1057_DATA 0x00202020 -#define DDRSS2_PHY_1058_DATA 0x20008008 -#define DDRSS2_PHY_1059_DATA 0x00000810 -#define DDRSS2_PHY_1060_DATA 0x00000F00 -#define DDRSS2_PHY_1061_DATA 0x00000000 -#define DDRSS2_PHY_1062_DATA 0x00000000 -#define DDRSS2_PHY_1063_DATA 0x00000000 -#define DDRSS2_PHY_1064_DATA 0x000305CC -#define DDRSS2_PHY_1065_DATA 0x00030000 -#define DDRSS2_PHY_1066_DATA 0x00000300 -#define DDRSS2_PHY_1067_DATA 0x00000300 -#define DDRSS2_PHY_1068_DATA 0x00000300 -#define DDRSS2_PHY_1069_DATA 0x00000300 -#define DDRSS2_PHY_1070_DATA 0x00000300 -#define DDRSS2_PHY_1071_DATA 0x42080010 -#define DDRSS2_PHY_1072_DATA 0x0000803E -#define DDRSS2_PHY_1073_DATA 0x00000001 -#define DDRSS2_PHY_1074_DATA 0x01000102 -#define DDRSS2_PHY_1075_DATA 0x00008000 -#define DDRSS2_PHY_1076_DATA 0x00000000 -#define DDRSS2_PHY_1077_DATA 0x00000000 -#define DDRSS2_PHY_1078_DATA 0x00000000 -#define DDRSS2_PHY_1079_DATA 0x00000000 -#define DDRSS2_PHY_1080_DATA 0x00000000 -#define DDRSS2_PHY_1081_DATA 0x00000000 -#define DDRSS2_PHY_1082_DATA 0x00000000 -#define DDRSS2_PHY_1083_DATA 0x00000000 -#define DDRSS2_PHY_1084_DATA 0x00000000 -#define DDRSS2_PHY_1085_DATA 0x00000000 -#define DDRSS2_PHY_1086_DATA 0x00000000 -#define DDRSS2_PHY_1087_DATA 0x00000000 -#define DDRSS2_PHY_1088_DATA 0x00000000 -#define DDRSS2_PHY_1089_DATA 0x00000000 -#define DDRSS2_PHY_1090_DATA 0x00000000 -#define DDRSS2_PHY_1091_DATA 0x00000000 -#define DDRSS2_PHY_1092_DATA 0x00000000 -#define DDRSS2_PHY_1093_DATA 0x00000000 -#define DDRSS2_PHY_1094_DATA 0x00000000 -#define DDRSS2_PHY_1095_DATA 0x00000000 -#define DDRSS2_PHY_1096_DATA 0x00000000 -#define DDRSS2_PHY_1097_DATA 0x00000000 -#define DDRSS2_PHY_1098_DATA 0x00000000 -#define DDRSS2_PHY_1099_DATA 0x00000000 -#define DDRSS2_PHY_1100_DATA 0x00000000 -#define DDRSS2_PHY_1101_DATA 0x00000000 -#define DDRSS2_PHY_1102_DATA 0x00000000 -#define DDRSS2_PHY_1103_DATA 0x00000000 -#define DDRSS2_PHY_1104_DATA 0x00000000 -#define DDRSS2_PHY_1105_DATA 0x00000000 -#define DDRSS2_PHY_1106_DATA 0x00000000 -#define DDRSS2_PHY_1107_DATA 0x00000000 -#define DDRSS2_PHY_1108_DATA 0x00000000 -#define DDRSS2_PHY_1109_DATA 0x00000000 -#define DDRSS2_PHY_1110_DATA 0x00000000 -#define DDRSS2_PHY_1111_DATA 0x00000000 -#define DDRSS2_PHY_1112_DATA 0x00000000 -#define DDRSS2_PHY_1113_DATA 0x00000000 -#define DDRSS2_PHY_1114_DATA 0x00000000 -#define DDRSS2_PHY_1115_DATA 0x00000000 -#define DDRSS2_PHY_1116_DATA 0x00000000 -#define DDRSS2_PHY_1117_DATA 0x00000000 -#define DDRSS2_PHY_1118_DATA 0x00000000 -#define DDRSS2_PHY_1119_DATA 0x00000000 -#define DDRSS2_PHY_1120_DATA 0x00000000 -#define DDRSS2_PHY_1121_DATA 0x00000000 -#define DDRSS2_PHY_1122_DATA 0x00000000 -#define DDRSS2_PHY_1123_DATA 0x00000000 -#define DDRSS2_PHY_1124_DATA 0x00000000 -#define DDRSS2_PHY_1125_DATA 0x00000000 -#define DDRSS2_PHY_1126_DATA 0x00000000 -#define DDRSS2_PHY_1127_DATA 0x00000000 -#define DDRSS2_PHY_1128_DATA 0x00000000 -#define DDRSS2_PHY_1129_DATA 0x00000000 -#define DDRSS2_PHY_1130_DATA 0x00000000 -#define DDRSS2_PHY_1131_DATA 0x00000000 -#define DDRSS2_PHY_1132_DATA 0x00000000 -#define DDRSS2_PHY_1133_DATA 0x00000000 -#define DDRSS2_PHY_1134_DATA 0x00000000 -#define DDRSS2_PHY_1135_DATA 0x00000000 -#define DDRSS2_PHY_1136_DATA 0x00000000 -#define DDRSS2_PHY_1137_DATA 0x00000000 -#define DDRSS2_PHY_1138_DATA 0x00000000 -#define DDRSS2_PHY_1139_DATA 0x00000000 -#define DDRSS2_PHY_1140_DATA 0x00000000 -#define DDRSS2_PHY_1141_DATA 0x00000000 -#define DDRSS2_PHY_1142_DATA 0x00000000 -#define DDRSS2_PHY_1143_DATA 0x00000000 -#define DDRSS2_PHY_1144_DATA 0x00000000 -#define DDRSS2_PHY_1145_DATA 0x00000000 -#define DDRSS2_PHY_1146_DATA 0x00000000 -#define DDRSS2_PHY_1147_DATA 0x00000000 -#define DDRSS2_PHY_1148_DATA 0x00000000 -#define DDRSS2_PHY_1149_DATA 0x00000000 -#define DDRSS2_PHY_1150_DATA 0x00000000 -#define DDRSS2_PHY_1151_DATA 0x00000000 -#define DDRSS2_PHY_1152_DATA 0x00000000 -#define DDRSS2_PHY_1153_DATA 0x00000000 -#define DDRSS2_PHY_1154_DATA 0x00000000 -#define DDRSS2_PHY_1155_DATA 0x00000000 -#define DDRSS2_PHY_1156_DATA 0x00000000 -#define DDRSS2_PHY_1157_DATA 0x00000000 -#define DDRSS2_PHY_1158_DATA 0x00000000 -#define DDRSS2_PHY_1159_DATA 0x00000000 -#define DDRSS2_PHY_1160_DATA 0x00000000 -#define DDRSS2_PHY_1161_DATA 0x00000000 -#define DDRSS2_PHY_1162_DATA 0x00000000 -#define DDRSS2_PHY_1163_DATA 0x00000000 -#define DDRSS2_PHY_1164_DATA 0x00000000 -#define DDRSS2_PHY_1165_DATA 0x00000000 -#define DDRSS2_PHY_1166_DATA 0x00000000 -#define DDRSS2_PHY_1167_DATA 0x00000000 -#define DDRSS2_PHY_1168_DATA 0x00000000 -#define DDRSS2_PHY_1169_DATA 0x00000000 -#define DDRSS2_PHY_1170_DATA 0x00000000 -#define DDRSS2_PHY_1171_DATA 0x00000000 -#define DDRSS2_PHY_1172_DATA 0x00000000 -#define DDRSS2_PHY_1173_DATA 0x00000000 -#define DDRSS2_PHY_1174_DATA 0x00000000 -#define DDRSS2_PHY_1175_DATA 0x00000000 -#define DDRSS2_PHY_1176_DATA 0x00000000 -#define DDRSS2_PHY_1177_DATA 0x00000000 -#define DDRSS2_PHY_1178_DATA 0x00000000 -#define DDRSS2_PHY_1179_DATA 0x00000000 -#define DDRSS2_PHY_1180_DATA 0x00000000 -#define DDRSS2_PHY_1181_DATA 0x00000000 -#define DDRSS2_PHY_1182_DATA 0x00000000 -#define DDRSS2_PHY_1183_DATA 0x00000000 -#define DDRSS2_PHY_1184_DATA 0x00000000 -#define DDRSS2_PHY_1185_DATA 0x00000000 -#define DDRSS2_PHY_1186_DATA 0x00000000 -#define DDRSS2_PHY_1187_DATA 0x00000000 -#define DDRSS2_PHY_1188_DATA 0x00000000 -#define DDRSS2_PHY_1189_DATA 0x00000000 -#define DDRSS2_PHY_1190_DATA 0x00000000 -#define DDRSS2_PHY_1191_DATA 0x00000000 -#define DDRSS2_PHY_1192_DATA 0x00000000 -#define DDRSS2_PHY_1193_DATA 0x00000000 -#define DDRSS2_PHY_1194_DATA 0x00000000 -#define DDRSS2_PHY_1195_DATA 0x00000000 -#define DDRSS2_PHY_1196_DATA 0x00000000 -#define DDRSS2_PHY_1197_DATA 0x00000000 -#define DDRSS2_PHY_1198_DATA 0x00000000 -#define DDRSS2_PHY_1199_DATA 0x00000000 -#define DDRSS2_PHY_1200_DATA 0x00000000 -#define DDRSS2_PHY_1201_DATA 0x00000000 -#define DDRSS2_PHY_1202_DATA 0x00000000 -#define DDRSS2_PHY_1203_DATA 0x00000000 -#define DDRSS2_PHY_1204_DATA 0x00000000 -#define DDRSS2_PHY_1205_DATA 0x00000000 -#define DDRSS2_PHY_1206_DATA 0x00000000 -#define DDRSS2_PHY_1207_DATA 0x00000000 -#define DDRSS2_PHY_1208_DATA 0x00000000 -#define DDRSS2_PHY_1209_DATA 0x00000000 -#define DDRSS2_PHY_1210_DATA 0x00000000 -#define DDRSS2_PHY_1211_DATA 0x00000000 -#define DDRSS2_PHY_1212_DATA 0x00000000 -#define DDRSS2_PHY_1213_DATA 0x00000000 -#define DDRSS2_PHY_1214_DATA 0x00000000 -#define DDRSS2_PHY_1215_DATA 0x00000000 -#define DDRSS2_PHY_1216_DATA 0x00000000 -#define DDRSS2_PHY_1217_DATA 0x00000000 -#define DDRSS2_PHY_1218_DATA 0x00000000 -#define DDRSS2_PHY_1219_DATA 0x00000000 -#define DDRSS2_PHY_1220_DATA 0x00000000 -#define DDRSS2_PHY_1221_DATA 0x00000000 -#define DDRSS2_PHY_1222_DATA 0x00000000 -#define DDRSS2_PHY_1223_DATA 0x00000000 -#define DDRSS2_PHY_1224_DATA 0x00000000 -#define DDRSS2_PHY_1225_DATA 0x00000000 -#define DDRSS2_PHY_1226_DATA 0x00000000 -#define DDRSS2_PHY_1227_DATA 0x00000000 -#define DDRSS2_PHY_1228_DATA 0x00000000 -#define DDRSS2_PHY_1229_DATA 0x00000000 -#define DDRSS2_PHY_1230_DATA 0x00000000 -#define DDRSS2_PHY_1231_DATA 0x00000000 -#define DDRSS2_PHY_1232_DATA 0x00000000 -#define DDRSS2_PHY_1233_DATA 0x00000000 -#define DDRSS2_PHY_1234_DATA 0x00000000 -#define DDRSS2_PHY_1235_DATA 0x00000000 -#define DDRSS2_PHY_1236_DATA 0x00000000 -#define DDRSS2_PHY_1237_DATA 0x00000000 -#define DDRSS2_PHY_1238_DATA 0x00000000 -#define DDRSS2_PHY_1239_DATA 0x00000000 -#define DDRSS2_PHY_1240_DATA 0x00000000 -#define DDRSS2_PHY_1241_DATA 0x00000000 -#define DDRSS2_PHY_1242_DATA 0x00000000 -#define DDRSS2_PHY_1243_DATA 0x00000000 -#define DDRSS2_PHY_1244_DATA 0x00000000 -#define DDRSS2_PHY_1245_DATA 0x00000000 -#define DDRSS2_PHY_1246_DATA 0x00000000 -#define DDRSS2_PHY_1247_DATA 0x00000000 -#define DDRSS2_PHY_1248_DATA 0x00000000 -#define DDRSS2_PHY_1249_DATA 0x00000000 -#define DDRSS2_PHY_1250_DATA 0x00000000 -#define DDRSS2_PHY_1251_DATA 0x00000000 -#define DDRSS2_PHY_1252_DATA 0x00000000 -#define DDRSS2_PHY_1253_DATA 0x00000000 -#define DDRSS2_PHY_1254_DATA 0x00000000 -#define DDRSS2_PHY_1255_DATA 0x00000000 -#define DDRSS2_PHY_1256_DATA 0x00000000 -#define DDRSS2_PHY_1257_DATA 0x00000000 -#define DDRSS2_PHY_1258_DATA 0x00000000 -#define DDRSS2_PHY_1259_DATA 0x00000000 -#define DDRSS2_PHY_1260_DATA 0x00000000 -#define DDRSS2_PHY_1261_DATA 0x00000000 -#define DDRSS2_PHY_1262_DATA 0x00000000 -#define DDRSS2_PHY_1263_DATA 0x00000000 -#define DDRSS2_PHY_1264_DATA 0x00000000 -#define DDRSS2_PHY_1265_DATA 0x00000000 -#define DDRSS2_PHY_1266_DATA 0x00000000 -#define DDRSS2_PHY_1267_DATA 0x00000000 -#define DDRSS2_PHY_1268_DATA 0x00000000 -#define DDRSS2_PHY_1269_DATA 0x00000000 -#define DDRSS2_PHY_1270_DATA 0x00000000 -#define DDRSS2_PHY_1271_DATA 0x00000000 -#define DDRSS2_PHY_1272_DATA 0x00000000 -#define DDRSS2_PHY_1273_DATA 0x00000000 -#define DDRSS2_PHY_1274_DATA 0x00000000 -#define DDRSS2_PHY_1275_DATA 0x00000000 -#define DDRSS2_PHY_1276_DATA 0x00000000 -#define DDRSS2_PHY_1277_DATA 0x00000000 -#define DDRSS2_PHY_1278_DATA 0x00000000 -#define DDRSS2_PHY_1279_DATA 0x00000000 -#define DDRSS2_PHY_1280_DATA 0x00000000 -#define DDRSS2_PHY_1281_DATA 0x00010100 -#define DDRSS2_PHY_1282_DATA 0x00000000 -#define DDRSS2_PHY_1283_DATA 0x00000000 -#define DDRSS2_PHY_1284_DATA 0x00050000 -#define DDRSS2_PHY_1285_DATA 0x04000000 -#define DDRSS2_PHY_1286_DATA 0x00000055 -#define DDRSS2_PHY_1287_DATA 0x00000000 -#define DDRSS2_PHY_1288_DATA 0x00000000 -#define DDRSS2_PHY_1289_DATA 0x00000000 -#define DDRSS2_PHY_1290_DATA 0x00000000 -#define DDRSS2_PHY_1291_DATA 0x00002001 -#define DDRSS2_PHY_1292_DATA 0x0000400F -#define DDRSS2_PHY_1293_DATA 0x50020028 -#define DDRSS2_PHY_1294_DATA 0x01010000 -#define DDRSS2_PHY_1295_DATA 0x80080001 -#define DDRSS2_PHY_1296_DATA 0x10200000 -#define DDRSS2_PHY_1297_DATA 0x00000008 -#define DDRSS2_PHY_1298_DATA 0x00000000 -#define DDRSS2_PHY_1299_DATA 0x01090E00 -#define DDRSS2_PHY_1300_DATA 0x00040101 -#define DDRSS2_PHY_1301_DATA 0x0000010F -#define DDRSS2_PHY_1302_DATA 0x00000000 -#define DDRSS2_PHY_1303_DATA 0x0000FFFF -#define DDRSS2_PHY_1304_DATA 0x00000000 -#define DDRSS2_PHY_1305_DATA 0x01010000 -#define DDRSS2_PHY_1306_DATA 0x01080402 -#define DDRSS2_PHY_1307_DATA 0x01200F02 -#define DDRSS2_PHY_1308_DATA 0x00194280 -#define DDRSS2_PHY_1309_DATA 0x00000004 -#define DDRSS2_PHY_1310_DATA 0x00042000 -#define DDRSS2_PHY_1311_DATA 0x00000000 -#define DDRSS2_PHY_1312_DATA 0x00000000 -#define DDRSS2_PHY_1313_DATA 0x00000000 -#define DDRSS2_PHY_1314_DATA 0x00000000 -#define DDRSS2_PHY_1315_DATA 0x00000000 -#define DDRSS2_PHY_1316_DATA 0x00000000 -#define DDRSS2_PHY_1317_DATA 0x01000000 -#define DDRSS2_PHY_1318_DATA 0x00000705 -#define DDRSS2_PHY_1319_DATA 0x00000054 -#define DDRSS2_PHY_1320_DATA 0x00030820 -#define DDRSS2_PHY_1321_DATA 0x00010820 -#define DDRSS2_PHY_1322_DATA 0x00010820 -#define DDRSS2_PHY_1323_DATA 0x00010820 -#define DDRSS2_PHY_1324_DATA 0x00010820 -#define DDRSS2_PHY_1325_DATA 0x00010820 -#define DDRSS2_PHY_1326_DATA 0x00010820 -#define DDRSS2_PHY_1327_DATA 0x00010820 -#define DDRSS2_PHY_1328_DATA 0x00010820 -#define DDRSS2_PHY_1329_DATA 0x00000000 -#define DDRSS2_PHY_1330_DATA 0x00000074 -#define DDRSS2_PHY_1331_DATA 0x00000400 -#define DDRSS2_PHY_1332_DATA 0x00000108 -#define DDRSS2_PHY_1333_DATA 0x00000000 -#define DDRSS2_PHY_1334_DATA 0x00000000 -#define DDRSS2_PHY_1335_DATA 0x00000000 -#define DDRSS2_PHY_1336_DATA 0x00000000 -#define DDRSS2_PHY_1337_DATA 0x00000000 -#define DDRSS2_PHY_1338_DATA 0x03000000 -#define DDRSS2_PHY_1339_DATA 0x00000000 -#define DDRSS2_PHY_1340_DATA 0x00000000 -#define DDRSS2_PHY_1341_DATA 0x00000000 -#define DDRSS2_PHY_1342_DATA 0x04102006 -#define DDRSS2_PHY_1343_DATA 0x00041020 -#define DDRSS2_PHY_1344_DATA 0x01C98C98 -#define DDRSS2_PHY_1345_DATA 0x3F400000 -#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F -#define DDRSS2_PHY_1347_DATA 0x0000001F -#define DDRSS2_PHY_1348_DATA 0x00000000 -#define DDRSS2_PHY_1349_DATA 0x00000000 -#define DDRSS2_PHY_1350_DATA 0x00000000 -#define DDRSS2_PHY_1351_DATA 0x00010000 -#define DDRSS2_PHY_1352_DATA 0x00000000 -#define DDRSS2_PHY_1353_DATA 0x00000000 -#define DDRSS2_PHY_1354_DATA 0x00000000 -#define DDRSS2_PHY_1355_DATA 0x00000000 -#define DDRSS2_PHY_1356_DATA 0x76543210 -#define DDRSS2_PHY_1357_DATA 0x00010198 -#define DDRSS2_PHY_1358_DATA 0x00000000 -#define DDRSS2_PHY_1359_DATA 0x00000000 -#define DDRSS2_PHY_1360_DATA 0x00000000 -#define DDRSS2_PHY_1361_DATA 0x00040700 -#define DDRSS2_PHY_1362_DATA 0x00000000 -#define DDRSS2_PHY_1363_DATA 0x00000000 -#define DDRSS2_PHY_1364_DATA 0x00000000 -#define DDRSS2_PHY_1365_DATA 0x00000000 -#define DDRSS2_PHY_1366_DATA 0x00000000 -#define DDRSS2_PHY_1367_DATA 0x00000002 -#define DDRSS2_PHY_1368_DATA 0x00000000 -#define DDRSS2_PHY_1369_DATA 0x00000000 -#define DDRSS2_PHY_1370_DATA 0x00000000 -#define DDRSS2_PHY_1371_DATA 0x00000000 -#define DDRSS2_PHY_1372_DATA 0x00000000 -#define DDRSS2_PHY_1373_DATA 0x00000000 -#define DDRSS2_PHY_1374_DATA 0x00080000 -#define DDRSS2_PHY_1375_DATA 0x000007FF -#define DDRSS2_PHY_1376_DATA 0x00000000 -#define DDRSS2_PHY_1377_DATA 0x00000000 -#define DDRSS2_PHY_1378_DATA 0x00000000 -#define DDRSS2_PHY_1379_DATA 0x00000000 -#define DDRSS2_PHY_1380_DATA 0x00000000 -#define DDRSS2_PHY_1381_DATA 0x00000000 -#define DDRSS2_PHY_1382_DATA 0x000FFFFF -#define DDRSS2_PHY_1383_DATA 0x000FFFFF -#define DDRSS2_PHY_1384_DATA 0x0000FFFF -#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0 -#define DDRSS2_PHY_1386_DATA 0x030FFFFF -#define DDRSS2_PHY_1387_DATA 0x01FFFFFF -#define DDRSS2_PHY_1388_DATA 0x0000FFFF -#define DDRSS2_PHY_1389_DATA 0x00000000 -#define DDRSS2_PHY_1390_DATA 0x00000000 -#define DDRSS2_PHY_1391_DATA 0x00000000 -#define DDRSS2_PHY_1392_DATA 0x00000000 -#define DDRSS2_PHY_1393_DATA 0x0001F7C0 -#define DDRSS2_PHY_1394_DATA 0x00000003 -#define DDRSS2_PHY_1395_DATA 0x00000000 -#define DDRSS2_PHY_1396_DATA 0x00001142 -#define DDRSS2_PHY_1397_DATA 0x010207AB -#define DDRSS2_PHY_1398_DATA 0x01000080 -#define DDRSS2_PHY_1399_DATA 0x03900390 -#define DDRSS2_PHY_1400_DATA 0x03900390 -#define DDRSS2_PHY_1401_DATA 0x00000390 -#define DDRSS2_PHY_1402_DATA 0x00000390 -#define DDRSS2_PHY_1403_DATA 0x00000390 -#define DDRSS2_PHY_1404_DATA 0x00000390 -#define DDRSS2_PHY_1405_DATA 0x00000005 -#define DDRSS2_PHY_1406_DATA 0x01813FCC -#define DDRSS2_PHY_1407_DATA 0x000000CC -#define DDRSS2_PHY_1408_DATA 0x0C000DFF -#define DDRSS2_PHY_1409_DATA 0x30000DFF -#define DDRSS2_PHY_1410_DATA 0x3F0DFF11 -#define DDRSS2_PHY_1411_DATA 0x000100F0 -#define DDRSS2_PHY_1412_DATA 0x780DFFCC -#define DDRSS2_PHY_1413_DATA 0x00007E31 -#define DDRSS2_PHY_1414_DATA 0x000CBF11 -#define DDRSS2_PHY_1415_DATA 0x01990010 -#define DDRSS2_PHY_1416_DATA 0x000CBF11 -#define DDRSS2_PHY_1417_DATA 0x01990010 -#define DDRSS2_PHY_1418_DATA 0x3F0DFF11 -#define DDRSS2_PHY_1419_DATA 0x00EF00F0 -#define DDRSS2_PHY_1420_DATA 0x3F0DFF11 -#define DDRSS2_PHY_1421_DATA 0x01FF00F0 -#define DDRSS2_PHY_1422_DATA 0x20040006 - -#define DDRSS3_CTL_00_DATA 0x00000B00 -#define DDRSS3_CTL_01_DATA 0x00000000 -#define DDRSS3_CTL_02_DATA 0x00000000 -#define DDRSS3_CTL_03_DATA 0x00000000 -#define DDRSS3_CTL_04_DATA 0x00000000 -#define DDRSS3_CTL_05_DATA 0x00000000 -#define DDRSS3_CTL_06_DATA 0x00000000 -#define DDRSS3_CTL_07_DATA 0x00002AF8 -#define DDRSS3_CTL_08_DATA 0x0001ADAF -#define DDRSS3_CTL_09_DATA 0x00000005 -#define DDRSS3_CTL_10_DATA 0x0000006E -#define DDRSS3_CTL_11_DATA 0x000681C8 -#define DDRSS3_CTL_12_DATA 0x004111C9 -#define DDRSS3_CTL_13_DATA 0x00000005 -#define DDRSS3_CTL_14_DATA 0x000010A9 -#define DDRSS3_CTL_15_DATA 0x000681C8 -#define DDRSS3_CTL_16_DATA 0x004111C9 -#define DDRSS3_CTL_17_DATA 0x00000005 -#define DDRSS3_CTL_18_DATA 0x000010A9 -#define DDRSS3_CTL_19_DATA 0x01010000 -#define DDRSS3_CTL_20_DATA 0x02011001 -#define DDRSS3_CTL_21_DATA 0x02010000 -#define DDRSS3_CTL_22_DATA 0x00020100 -#define DDRSS3_CTL_23_DATA 0x0000000B -#define DDRSS3_CTL_24_DATA 0x0000001C -#define DDRSS3_CTL_25_DATA 0x00000000 -#define DDRSS3_CTL_26_DATA 0x00000000 -#define DDRSS3_CTL_27_DATA 0x03020200 -#define DDRSS3_CTL_28_DATA 0x00005656 -#define DDRSS3_CTL_29_DATA 0x00100000 -#define DDRSS3_CTL_30_DATA 0x00000000 -#define DDRSS3_CTL_31_DATA 0x00000000 -#define DDRSS3_CTL_32_DATA 0x00000000 -#define DDRSS3_CTL_33_DATA 0x00000000 -#define DDRSS3_CTL_34_DATA 0x040C0000 -#define DDRSS3_CTL_35_DATA 0x12481248 -#define DDRSS3_CTL_36_DATA 0x00050804 -#define DDRSS3_CTL_37_DATA 0x09040008 -#define DDRSS3_CTL_38_DATA 0x15000204 -#define DDRSS3_CTL_39_DATA 0x1760008B -#define DDRSS3_CTL_40_DATA 0x1500422B -#define DDRSS3_CTL_41_DATA 0x1760008B -#define DDRSS3_CTL_42_DATA 0x2000422B -#define DDRSS3_CTL_43_DATA 0x000A0A09 -#define DDRSS3_CTL_44_DATA 0x0400078A -#define DDRSS3_CTL_45_DATA 0x1E161104 -#define DDRSS3_CTL_46_DATA 0x10012458 -#define DDRSS3_CTL_47_DATA 0x1E161110 -#define DDRSS3_CTL_48_DATA 0x10012458 -#define DDRSS3_CTL_49_DATA 0x02030410 -#define DDRSS3_CTL_50_DATA 0x2C040500 -#define DDRSS3_CTL_51_DATA 0x08292C29 -#define DDRSS3_CTL_52_DATA 0x14000E0A -#define DDRSS3_CTL_53_DATA 0x04010A0A -#define DDRSS3_CTL_54_DATA 0x01010004 -#define DDRSS3_CTL_55_DATA 0x04545408 -#define DDRSS3_CTL_56_DATA 0x04313104 -#define DDRSS3_CTL_57_DATA 0x00003131 -#define DDRSS3_CTL_58_DATA 0x00010100 -#define DDRSS3_CTL_59_DATA 0x03010000 -#define DDRSS3_CTL_60_DATA 0x00001508 -#define DDRSS3_CTL_61_DATA 0x000000CE -#define DDRSS3_CTL_62_DATA 0x0000032B -#define DDRSS3_CTL_63_DATA 0x00002073 -#define DDRSS3_CTL_64_DATA 0x0000032B -#define DDRSS3_CTL_65_DATA 0x00002073 -#define DDRSS3_CTL_66_DATA 0x00000005 -#define DDRSS3_CTL_67_DATA 0x00050000 -#define DDRSS3_CTL_68_DATA 0x00CB0012 -#define DDRSS3_CTL_69_DATA 0x00CB0408 -#define DDRSS3_CTL_70_DATA 0x00400408 -#define DDRSS3_CTL_71_DATA 0x00120103 -#define DDRSS3_CTL_72_DATA 0x00100005 -#define DDRSS3_CTL_73_DATA 0x2F080010 -#define DDRSS3_CTL_74_DATA 0x0505012F -#define DDRSS3_CTL_75_DATA 0x0401030A -#define DDRSS3_CTL_76_DATA 0x041E100B -#define DDRSS3_CTL_77_DATA 0x100B0401 -#define DDRSS3_CTL_78_DATA 0x0001041E -#define DDRSS3_CTL_79_DATA 0x00160016 -#define DDRSS3_CTL_80_DATA 0x033B033B -#define DDRSS3_CTL_81_DATA 0x033B033B -#define DDRSS3_CTL_82_DATA 0x03050505 -#define DDRSS3_CTL_83_DATA 0x03010303 -#define DDRSS3_CTL_84_DATA 0x200B100B -#define DDRSS3_CTL_85_DATA 0x04041004 -#define DDRSS3_CTL_86_DATA 0x200B100B -#define DDRSS3_CTL_87_DATA 0x04041004 -#define DDRSS3_CTL_88_DATA 0x03010000 -#define DDRSS3_CTL_89_DATA 0x00010000 -#define DDRSS3_CTL_90_DATA 0x00000000 -#define DDRSS3_CTL_91_DATA 0x00000000 -#define DDRSS3_CTL_92_DATA 0x01000000 -#define DDRSS3_CTL_93_DATA 0x80104002 -#define DDRSS3_CTL_94_DATA 0x00000000 -#define DDRSS3_CTL_95_DATA 0x00040005 -#define DDRSS3_CTL_96_DATA 0x00000000 -#define DDRSS3_CTL_97_DATA 0x00050000 -#define DDRSS3_CTL_98_DATA 0x00000004 -#define DDRSS3_CTL_99_DATA 0x00000000 -#define DDRSS3_CTL_100_DATA 0x00040005 -#define DDRSS3_CTL_101_DATA 0x00000000 -#define DDRSS3_CTL_102_DATA 0x00003380 -#define DDRSS3_CTL_103_DATA 0x00003380 -#define DDRSS3_CTL_104_DATA 0x00003380 -#define DDRSS3_CTL_105_DATA 0x00003380 -#define DDRSS3_CTL_106_DATA 0x00003380 -#define DDRSS3_CTL_107_DATA 0x00000000 -#define DDRSS3_CTL_108_DATA 0x000005A2 -#define DDRSS3_CTL_109_DATA 0x00081CC0 -#define DDRSS3_CTL_110_DATA 0x00081CC0 -#define DDRSS3_CTL_111_DATA 0x00081CC0 -#define DDRSS3_CTL_112_DATA 0x00081CC0 -#define DDRSS3_CTL_113_DATA 0x00081CC0 -#define DDRSS3_CTL_114_DATA 0x00000000 -#define DDRSS3_CTL_115_DATA 0x0000E325 -#define DDRSS3_CTL_116_DATA 0x00081CC0 -#define DDRSS3_CTL_117_DATA 0x00081CC0 -#define DDRSS3_CTL_118_DATA 0x00081CC0 -#define DDRSS3_CTL_119_DATA 0x00081CC0 -#define DDRSS3_CTL_120_DATA 0x00081CC0 -#define DDRSS3_CTL_121_DATA 0x00000000 -#define DDRSS3_CTL_122_DATA 0x0000E325 -#define DDRSS3_CTL_123_DATA 0x00000000 -#define DDRSS3_CTL_124_DATA 0x00000000 -#define DDRSS3_CTL_125_DATA 0x00000000 -#define DDRSS3_CTL_126_DATA 0x00000000 -#define DDRSS3_CTL_127_DATA 0x00000000 -#define DDRSS3_CTL_128_DATA 0x00000000 -#define DDRSS3_CTL_129_DATA 0x00000000 -#define DDRSS3_CTL_130_DATA 0x00000000 -#define DDRSS3_CTL_131_DATA 0x0B030500 -#define DDRSS3_CTL_132_DATA 0x00040B04 -#define DDRSS3_CTL_133_DATA 0x0A090000 -#define DDRSS3_CTL_134_DATA 0x0A090701 -#define DDRSS3_CTL_135_DATA 0x0900000E -#define DDRSS3_CTL_136_DATA 0x0907010A -#define DDRSS3_CTL_137_DATA 0x00000E0A -#define DDRSS3_CTL_138_DATA 0x07010A09 -#define DDRSS3_CTL_139_DATA 0x000E0A09 -#define DDRSS3_CTL_140_DATA 0x07000401 -#define DDRSS3_CTL_141_DATA 0x00000000 -#define DDRSS3_CTL_142_DATA 0x00000000 -#define DDRSS3_CTL_143_DATA 0x00000000 -#define DDRSS3_CTL_144_DATA 0x00000000 -#define DDRSS3_CTL_145_DATA 0x00000000 -#define DDRSS3_CTL_146_DATA 0x00000000 -#define DDRSS3_CTL_147_DATA 0x00000000 -#define DDRSS3_CTL_148_DATA 0x08080000 -#define DDRSS3_CTL_149_DATA 0x01000000 -#define DDRSS3_CTL_150_DATA 0x800000C0 -#define DDRSS3_CTL_151_DATA 0x800000C0 -#define DDRSS3_CTL_152_DATA 0x800000C0 -#define DDRSS3_CTL_153_DATA 0x00000000 -#define DDRSS3_CTL_154_DATA 0x00001500 -#define DDRSS3_CTL_155_DATA 0x00000000 -#define DDRSS3_CTL_156_DATA 0x00000001 -#define DDRSS3_CTL_157_DATA 0x00000002 -#define DDRSS3_CTL_158_DATA 0x0000100E -#define DDRSS3_CTL_159_DATA 0x00000000 -#define DDRSS3_CTL_160_DATA 0x00000000 -#define DDRSS3_CTL_161_DATA 0x00000000 -#define DDRSS3_CTL_162_DATA 0x00000000 -#define DDRSS3_CTL_163_DATA 0x00000000 -#define DDRSS3_CTL_164_DATA 0x000B0000 -#define DDRSS3_CTL_165_DATA 0x000E0006 -#define DDRSS3_CTL_166_DATA 0x000E0404 -#define DDRSS3_CTL_167_DATA 0x00D601AB -#define DDRSS3_CTL_168_DATA 0x10100216 -#define DDRSS3_CTL_169_DATA 0x01AB0216 -#define DDRSS3_CTL_170_DATA 0x021600D6 -#define DDRSS3_CTL_171_DATA 0x02161010 -#define DDRSS3_CTL_172_DATA 0x00000000 -#define DDRSS3_CTL_173_DATA 0x00000000 -#define DDRSS3_CTL_174_DATA 0x00000000 -#define DDRSS3_CTL_175_DATA 0x3FF40084 -#define DDRSS3_CTL_176_DATA 0x33003FF4 -#define DDRSS3_CTL_177_DATA 0x00003333 -#define DDRSS3_CTL_178_DATA 0x35000000 -#define DDRSS3_CTL_179_DATA 0x27270035 -#define DDRSS3_CTL_180_DATA 0x0F0F0000 -#define DDRSS3_CTL_181_DATA 0x16000000 -#define DDRSS3_CTL_182_DATA 0x00841616 -#define DDRSS3_CTL_183_DATA 0x3FF43FF4 -#define DDRSS3_CTL_184_DATA 0x33333300 -#define DDRSS3_CTL_185_DATA 0x00000000 -#define DDRSS3_CTL_186_DATA 0x00353500 -#define DDRSS3_CTL_187_DATA 0x00002727 -#define DDRSS3_CTL_188_DATA 0x00000F0F -#define DDRSS3_CTL_189_DATA 0x16161600 -#define DDRSS3_CTL_190_DATA 0x00000020 -#define DDRSS3_CTL_191_DATA 0x00000000 -#define DDRSS3_CTL_192_DATA 0x00000001 -#define DDRSS3_CTL_193_DATA 0x00000000 -#define DDRSS3_CTL_194_DATA 0x01000000 -#define DDRSS3_CTL_195_DATA 0x00000001 -#define DDRSS3_CTL_196_DATA 0x00000000 -#define DDRSS3_CTL_197_DATA 0x00000000 -#define DDRSS3_CTL_198_DATA 0x00000000 -#define DDRSS3_CTL_199_DATA 0x00000000 -#define DDRSS3_CTL_200_DATA 0x00000000 -#define DDRSS3_CTL_201_DATA 0x00000000 -#define DDRSS3_CTL_202_DATA 0x00000000 -#define DDRSS3_CTL_203_DATA 0x00000000 -#define DDRSS3_CTL_204_DATA 0x00000000 -#define DDRSS3_CTL_205_DATA 0x00000000 -#define DDRSS3_CTL_206_DATA 0x02000000 -#define DDRSS3_CTL_207_DATA 0x01080101 -#define DDRSS3_CTL_208_DATA 0x00000000 -#define DDRSS3_CTL_209_DATA 0x00000000 -#define DDRSS3_CTL_210_DATA 0x00000000 -#define DDRSS3_CTL_211_DATA 0x00000000 -#define DDRSS3_CTL_212_DATA 0x00000000 -#define DDRSS3_CTL_213_DATA 0x00000000 -#define DDRSS3_CTL_214_DATA 0x00000000 -#define DDRSS3_CTL_215_DATA 0x00000000 -#define DDRSS3_CTL_216_DATA 0x00000000 -#define DDRSS3_CTL_217_DATA 0x00000000 -#define DDRSS3_CTL_218_DATA 0x00000000 -#define DDRSS3_CTL_219_DATA 0x00000000 -#define DDRSS3_CTL_220_DATA 0x00000000 -#define DDRSS3_CTL_221_DATA 0x00000000 -#define DDRSS3_CTL_222_DATA 0x00001000 -#define DDRSS3_CTL_223_DATA 0x006403E8 -#define DDRSS3_CTL_224_DATA 0x00000000 -#define DDRSS3_CTL_225_DATA 0x00000000 -#define DDRSS3_CTL_226_DATA 0x00000000 -#define DDRSS3_CTL_227_DATA 0x15110000 -#define DDRSS3_CTL_228_DATA 0x00040C18 -#define DDRSS3_CTL_229_DATA 0xF000C000 -#define DDRSS3_CTL_230_DATA 0x0000F000 -#define DDRSS3_CTL_231_DATA 0x00000000 -#define DDRSS3_CTL_232_DATA 0x00000000 -#define DDRSS3_CTL_233_DATA 0xC0000000 -#define DDRSS3_CTL_234_DATA 0xF000F000 -#define DDRSS3_CTL_235_DATA 0x00000000 -#define DDRSS3_CTL_236_DATA 0x00000000 -#define DDRSS3_CTL_237_DATA 0x00000000 -#define DDRSS3_CTL_238_DATA 0xF000C000 -#define DDRSS3_CTL_239_DATA 0x0000F000 -#define DDRSS3_CTL_240_DATA 0x00000000 -#define DDRSS3_CTL_241_DATA 0x00000000 -#define DDRSS3_CTL_242_DATA 0x00030000 -#define DDRSS3_CTL_243_DATA 0x00000000 -#define DDRSS3_CTL_244_DATA 0x00000000 -#define DDRSS3_CTL_245_DATA 0x00000000 -#define DDRSS3_CTL_246_DATA 0x00000000 -#define DDRSS3_CTL_247_DATA 0x00000000 -#define DDRSS3_CTL_248_DATA 0x00000000 -#define DDRSS3_CTL_249_DATA 0x00000000 -#define DDRSS3_CTL_250_DATA 0x00000000 -#define DDRSS3_CTL_251_DATA 0x00000000 -#define DDRSS3_CTL_252_DATA 0x00000000 -#define DDRSS3_CTL_253_DATA 0x00000000 -#define DDRSS3_CTL_254_DATA 0x00000000 -#define DDRSS3_CTL_255_DATA 0x00000000 -#define DDRSS3_CTL_256_DATA 0x00000000 -#define DDRSS3_CTL_257_DATA 0x01000200 -#define DDRSS3_CTL_258_DATA 0x00370040 -#define DDRSS3_CTL_259_DATA 0x00020008 -#define DDRSS3_CTL_260_DATA 0x00400100 -#define DDRSS3_CTL_261_DATA 0x00400855 -#define DDRSS3_CTL_262_DATA 0x01000200 -#define DDRSS3_CTL_263_DATA 0x08550040 -#define DDRSS3_CTL_264_DATA 0x00000040 -#define DDRSS3_CTL_265_DATA 0x006B0003 -#define DDRSS3_CTL_266_DATA 0x0100006B -#define DDRSS3_CTL_267_DATA 0x03030303 -#define DDRSS3_CTL_268_DATA 0x00000000 -#define DDRSS3_CTL_269_DATA 0x00000202 -#define DDRSS3_CTL_270_DATA 0x00001FFF -#define DDRSS3_CTL_271_DATA 0x3FFF2000 -#define DDRSS3_CTL_272_DATA 0x03FF0000 -#define DDRSS3_CTL_273_DATA 0x000103FF -#define DDRSS3_CTL_274_DATA 0x0FFF0B00 -#define DDRSS3_CTL_275_DATA 0x01010001 -#define DDRSS3_CTL_276_DATA 0x01010101 -#define DDRSS3_CTL_277_DATA 0x01180101 -#define DDRSS3_CTL_278_DATA 0x00030000 -#define DDRSS3_CTL_279_DATA 0x00000000 -#define DDRSS3_CTL_280_DATA 0x00000000 -#define DDRSS3_CTL_281_DATA 0x00000000 -#define DDRSS3_CTL_282_DATA 0x00000000 -#define DDRSS3_CTL_283_DATA 0x00000000 -#define DDRSS3_CTL_284_DATA 0x00000000 -#define DDRSS3_CTL_285_DATA 0x00000000 -#define DDRSS3_CTL_286_DATA 0x00040101 -#define DDRSS3_CTL_287_DATA 0x04010100 -#define DDRSS3_CTL_288_DATA 0x00000000 -#define DDRSS3_CTL_289_DATA 0x00000000 -#define DDRSS3_CTL_290_DATA 0x03030300 -#define DDRSS3_CTL_291_DATA 0x00000001 -#define DDRSS3_CTL_292_DATA 0x00000000 -#define DDRSS3_CTL_293_DATA 0x00000000 -#define DDRSS3_CTL_294_DATA 0x00000000 -#define DDRSS3_CTL_295_DATA 0x00000000 -#define DDRSS3_CTL_296_DATA 0x00000000 -#define DDRSS3_CTL_297_DATA 0x00000000 -#define DDRSS3_CTL_298_DATA 0x00000000 -#define DDRSS3_CTL_299_DATA 0x00000000 -#define DDRSS3_CTL_300_DATA 0x00000000 -#define DDRSS3_CTL_301_DATA 0x00000000 -#define DDRSS3_CTL_302_DATA 0x00000000 -#define DDRSS3_CTL_303_DATA 0x00000000 -#define DDRSS3_CTL_304_DATA 0x00000000 -#define DDRSS3_CTL_305_DATA 0x00000000 -#define DDRSS3_CTL_306_DATA 0x00000000 -#define DDRSS3_CTL_307_DATA 0x00000000 -#define DDRSS3_CTL_308_DATA 0x00000000 -#define DDRSS3_CTL_309_DATA 0x00000000 -#define DDRSS3_CTL_310_DATA 0x00000000 -#define DDRSS3_CTL_311_DATA 0x00000000 -#define DDRSS3_CTL_312_DATA 0x00000000 -#define DDRSS3_CTL_313_DATA 0x01000000 -#define DDRSS3_CTL_314_DATA 0x00020201 -#define DDRSS3_CTL_315_DATA 0x01000101 -#define DDRSS3_CTL_316_DATA 0x01010001 -#define DDRSS3_CTL_317_DATA 0x00010101 -#define DDRSS3_CTL_318_DATA 0x050A0A03 -#define DDRSS3_CTL_319_DATA 0x10081F1F -#define DDRSS3_CTL_320_DATA 0x00090310 -#define DDRSS3_CTL_321_DATA 0x0B0C030F -#define DDRSS3_CTL_322_DATA 0x0B0C0306 -#define DDRSS3_CTL_323_DATA 0x0C090006 -#define DDRSS3_CTL_324_DATA 0x0100000C -#define DDRSS3_CTL_325_DATA 0x08040801 -#define DDRSS3_CTL_326_DATA 0x00000004 -#define DDRSS3_CTL_327_DATA 0x00000000 -#define DDRSS3_CTL_328_DATA 0x00010000 -#define DDRSS3_CTL_329_DATA 0x00280D00 -#define DDRSS3_CTL_330_DATA 0x00000001 -#define DDRSS3_CTL_331_DATA 0x00030001 -#define DDRSS3_CTL_332_DATA 0x00000000 -#define DDRSS3_CTL_333_DATA 0x00000000 -#define DDRSS3_CTL_334_DATA 0x00000000 -#define DDRSS3_CTL_335_DATA 0x00000000 -#define DDRSS3_CTL_336_DATA 0x00000000 -#define DDRSS3_CTL_337_DATA 0x00000000 -#define DDRSS3_CTL_338_DATA 0x00000000 -#define DDRSS3_CTL_339_DATA 0x00000000 -#define DDRSS3_CTL_340_DATA 0x01000000 -#define DDRSS3_CTL_341_DATA 0x00000001 -#define DDRSS3_CTL_342_DATA 0x00010100 -#define DDRSS3_CTL_343_DATA 0x03030000 -#define DDRSS3_CTL_344_DATA 0x00000000 -#define DDRSS3_CTL_345_DATA 0x00000000 -#define DDRSS3_CTL_346_DATA 0x00000000 -#define DDRSS3_CTL_347_DATA 0x00000000 -#define DDRSS3_CTL_348_DATA 0x00000000 -#define DDRSS3_CTL_349_DATA 0x00000000 -#define DDRSS3_CTL_350_DATA 0x00000000 -#define DDRSS3_CTL_351_DATA 0x00000000 -#define DDRSS3_CTL_352_DATA 0x00000000 -#define DDRSS3_CTL_353_DATA 0x00000000 -#define DDRSS3_CTL_354_DATA 0x00000000 -#define DDRSS3_CTL_355_DATA 0x00000000 -#define DDRSS3_CTL_356_DATA 0x00000000 -#define DDRSS3_CTL_357_DATA 0x00000000 -#define DDRSS3_CTL_358_DATA 0x00000000 -#define DDRSS3_CTL_359_DATA 0x00000000 -#define DDRSS3_CTL_360_DATA 0x000556AA -#define DDRSS3_CTL_361_DATA 0x000AAAAA -#define DDRSS3_CTL_362_DATA 0x000AA955 -#define DDRSS3_CTL_363_DATA 0x00055555 -#define DDRSS3_CTL_364_DATA 0x000B3133 -#define DDRSS3_CTL_365_DATA 0x0004CD33 -#define DDRSS3_CTL_366_DATA 0x0004CECC -#define DDRSS3_CTL_367_DATA 0x000B32CC -#define DDRSS3_CTL_368_DATA 0x00010300 -#define DDRSS3_CTL_369_DATA 0x03000100 -#define DDRSS3_CTL_370_DATA 0x00000000 -#define DDRSS3_CTL_371_DATA 0x00000000 -#define DDRSS3_CTL_372_DATA 0x00000000 -#define DDRSS3_CTL_373_DATA 0x00000000 -#define DDRSS3_CTL_374_DATA 0x00000000 -#define DDRSS3_CTL_375_DATA 0x00000000 -#define DDRSS3_CTL_376_DATA 0x00000000 -#define DDRSS3_CTL_377_DATA 0x00010000 -#define DDRSS3_CTL_378_DATA 0x00000404 -#define DDRSS3_CTL_379_DATA 0x00000000 -#define DDRSS3_CTL_380_DATA 0x00000000 -#define DDRSS3_CTL_381_DATA 0x00000000 -#define DDRSS3_CTL_382_DATA 0x00000000 -#define DDRSS3_CTL_383_DATA 0x00000000 -#define DDRSS3_CTL_384_DATA 0x00000000 -#define DDRSS3_CTL_385_DATA 0x00000000 -#define DDRSS3_CTL_386_DATA 0x00000000 -#define DDRSS3_CTL_387_DATA 0x3A3A1B00 -#define DDRSS3_CTL_388_DATA 0x000A0000 -#define DDRSS3_CTL_389_DATA 0x0000019C -#define DDRSS3_CTL_390_DATA 0x00000200 -#define DDRSS3_CTL_391_DATA 0x00000200 -#define DDRSS3_CTL_392_DATA 0x00000200 -#define DDRSS3_CTL_393_DATA 0x00000200 -#define DDRSS3_CTL_394_DATA 0x000004D4 -#define DDRSS3_CTL_395_DATA 0x00001018 -#define DDRSS3_CTL_396_DATA 0x00000204 -#define DDRSS3_CTL_397_DATA 0x000040E6 -#define DDRSS3_CTL_398_DATA 0x00000200 -#define DDRSS3_CTL_399_DATA 0x00000200 -#define DDRSS3_CTL_400_DATA 0x00000200 -#define DDRSS3_CTL_401_DATA 0x00000200 -#define DDRSS3_CTL_402_DATA 0x0000C2B2 -#define DDRSS3_CTL_403_DATA 0x000288FC -#define DDRSS3_CTL_404_DATA 0x00000E15 -#define DDRSS3_CTL_405_DATA 0x000040E6 -#define DDRSS3_CTL_406_DATA 0x00000200 -#define DDRSS3_CTL_407_DATA 0x00000200 -#define DDRSS3_CTL_408_DATA 0x00000200 -#define DDRSS3_CTL_409_DATA 0x00000200 -#define DDRSS3_CTL_410_DATA 0x0000C2B2 -#define DDRSS3_CTL_411_DATA 0x000288FC -#define DDRSS3_CTL_412_DATA 0x02020E15 -#define DDRSS3_CTL_413_DATA 0x03030202 -#define DDRSS3_CTL_414_DATA 0x00000022 -#define DDRSS3_CTL_415_DATA 0x00000000 -#define DDRSS3_CTL_416_DATA 0x00000000 -#define DDRSS3_CTL_417_DATA 0x00001403 -#define DDRSS3_CTL_418_DATA 0x000007D0 -#define DDRSS3_CTL_419_DATA 0x00000000 -#define DDRSS3_CTL_420_DATA 0x00000000 -#define DDRSS3_CTL_421_DATA 0x00030000 -#define DDRSS3_CTL_422_DATA 0x0007001F -#define DDRSS3_CTL_423_DATA 0x001B0033 -#define DDRSS3_CTL_424_DATA 0x001B0033 -#define DDRSS3_CTL_425_DATA 0x00000000 -#define DDRSS3_CTL_426_DATA 0x00000000 -#define DDRSS3_CTL_427_DATA 0x02000000 -#define DDRSS3_CTL_428_DATA 0x01000404 -#define DDRSS3_CTL_429_DATA 0x0B1E0B1E -#define DDRSS3_CTL_430_DATA 0x00000105 -#define DDRSS3_CTL_431_DATA 0x00010101 -#define DDRSS3_CTL_432_DATA 0x00010101 -#define DDRSS3_CTL_433_DATA 0x00010001 -#define DDRSS3_CTL_434_DATA 0x00000101 -#define DDRSS3_CTL_435_DATA 0x02000201 -#define DDRSS3_CTL_436_DATA 0x02010000 -#define DDRSS3_CTL_437_DATA 0x00000200 -#define DDRSS3_CTL_438_DATA 0x28060000 -#define DDRSS3_CTL_439_DATA 0x00000128 -#define DDRSS3_CTL_440_DATA 0xFFFFFFFF -#define DDRSS3_CTL_441_DATA 0xFFFFFFFF -#define DDRSS3_CTL_442_DATA 0x00000000 -#define DDRSS3_CTL_443_DATA 0x00000000 -#define DDRSS3_CTL_444_DATA 0x00000000 -#define DDRSS3_CTL_445_DATA 0x00000000 -#define DDRSS3_CTL_446_DATA 0x00000000 -#define DDRSS3_CTL_447_DATA 0x00000000 -#define DDRSS3_CTL_448_DATA 0x00000000 -#define DDRSS3_CTL_449_DATA 0x00000000 -#define DDRSS3_CTL_450_DATA 0x00000000 -#define DDRSS3_CTL_451_DATA 0x00000000 -#define DDRSS3_CTL_452_DATA 0x00000000 -#define DDRSS3_CTL_453_DATA 0x00000000 -#define DDRSS3_CTL_454_DATA 0x00000000 -#define DDRSS3_CTL_455_DATA 0x00000000 -#define DDRSS3_CTL_456_DATA 0x00000000 -#define DDRSS3_CTL_457_DATA 0x00000000 -#define DDRSS3_CTL_458_DATA 0x00000000 - -#define DDRSS3_PI_00_DATA 0x00000B00 -#define DDRSS3_PI_01_DATA 0x00000000 -#define DDRSS3_PI_02_DATA 0x00000000 -#define DDRSS3_PI_03_DATA 0x00000000 -#define DDRSS3_PI_04_DATA 0x00000000 -#define DDRSS3_PI_05_DATA 0x00000101 -#define DDRSS3_PI_06_DATA 0x00640000 -#define DDRSS3_PI_07_DATA 0x00000001 -#define DDRSS3_PI_08_DATA 0x00000000 -#define DDRSS3_PI_09_DATA 0x00000000 -#define DDRSS3_PI_10_DATA 0x00000000 -#define DDRSS3_PI_11_DATA 0x00000000 -#define DDRSS3_PI_12_DATA 0x00000007 -#define DDRSS3_PI_13_DATA 0x00010002 -#define DDRSS3_PI_14_DATA 0x0800000F -#define DDRSS3_PI_15_DATA 0x00000103 -#define DDRSS3_PI_16_DATA 0x00000005 -#define DDRSS3_PI_17_DATA 0x00000000 -#define DDRSS3_PI_18_DATA 0x00000000 -#define DDRSS3_PI_19_DATA 0x00000000 -#define DDRSS3_PI_20_DATA 0x00000000 -#define DDRSS3_PI_21_DATA 0x00000000 -#define DDRSS3_PI_22_DATA 0x00000000 -#define DDRSS3_PI_23_DATA 0x00000000 -#define DDRSS3_PI_24_DATA 0x00000000 -#define DDRSS3_PI_25_DATA 0x00000000 -#define DDRSS3_PI_26_DATA 0x00010100 -#define DDRSS3_PI_27_DATA 0x00280A00 -#define DDRSS3_PI_28_DATA 0x00000000 -#define DDRSS3_PI_29_DATA 0x0F000000 -#define DDRSS3_PI_30_DATA 0x00003200 -#define DDRSS3_PI_31_DATA 0x00000000 -#define DDRSS3_PI_32_DATA 0x00000000 -#define DDRSS3_PI_33_DATA 0x01010102 -#define DDRSS3_PI_34_DATA 0x00000000 -#define DDRSS3_PI_35_DATA 0x000000AA -#define DDRSS3_PI_36_DATA 0x00000055 -#define DDRSS3_PI_37_DATA 0x000000B5 -#define DDRSS3_PI_38_DATA 0x0000004A -#define DDRSS3_PI_39_DATA 0x00000056 -#define DDRSS3_PI_40_DATA 0x000000A9 -#define DDRSS3_PI_41_DATA 0x000000A9 -#define DDRSS3_PI_42_DATA 0x000000B5 -#define DDRSS3_PI_43_DATA 0x00000000 -#define DDRSS3_PI_44_DATA 0x00000000 -#define DDRSS3_PI_45_DATA 0x000F0F00 -#define DDRSS3_PI_46_DATA 0x0000001B -#define DDRSS3_PI_47_DATA 0x000007D0 -#define DDRSS3_PI_48_DATA 0x00000300 -#define DDRSS3_PI_49_DATA 0x00000000 -#define DDRSS3_PI_50_DATA 0x00000000 -#define DDRSS3_PI_51_DATA 0x01000000 -#define DDRSS3_PI_52_DATA 0x00010101 -#define DDRSS3_PI_53_DATA 0x00000000 -#define DDRSS3_PI_54_DATA 0x00030000 -#define DDRSS3_PI_55_DATA 0x0F000000 -#define DDRSS3_PI_56_DATA 0x00000017 -#define DDRSS3_PI_57_DATA 0x00000000 -#define DDRSS3_PI_58_DATA 0x00000000 -#define DDRSS3_PI_59_DATA 0x00000000 -#define DDRSS3_PI_60_DATA 0x0A0A140A -#define DDRSS3_PI_61_DATA 0x10020101 -#define DDRSS3_PI_62_DATA 0x00020805 -#define DDRSS3_PI_63_DATA 0x01000404 -#define DDRSS3_PI_64_DATA 0x00000000 -#define DDRSS3_PI_65_DATA 0x00000000 -#define DDRSS3_PI_66_DATA 0x00000100 -#define DDRSS3_PI_67_DATA 0x0001010F -#define DDRSS3_PI_68_DATA 0x00340000 -#define DDRSS3_PI_69_DATA 0x00000000 -#define DDRSS3_PI_70_DATA 0x00000000 -#define DDRSS3_PI_71_DATA 0x0000FFFF -#define DDRSS3_PI_72_DATA 0x00000000 -#define DDRSS3_PI_73_DATA 0x00080000 -#define DDRSS3_PI_74_DATA 0x02000200 -#define DDRSS3_PI_75_DATA 0x01000100 -#define DDRSS3_PI_76_DATA 0x01000000 -#define DDRSS3_PI_77_DATA 0x02000200 -#define DDRSS3_PI_78_DATA 0x00000200 -#define DDRSS3_PI_79_DATA 0x00000000 -#define DDRSS3_PI_80_DATA 0x00000000 -#define DDRSS3_PI_81_DATA 0x00000000 -#define DDRSS3_PI_82_DATA 0x00000000 -#define DDRSS3_PI_83_DATA 0x00000000 -#define DDRSS3_PI_84_DATA 0x00000000 -#define DDRSS3_PI_85_DATA 0x00000000 -#define DDRSS3_PI_86_DATA 0x00000000 -#define DDRSS3_PI_87_DATA 0x00000000 -#define DDRSS3_PI_88_DATA 0x00000000 -#define DDRSS3_PI_89_DATA 0x00000000 -#define DDRSS3_PI_90_DATA 0x00000000 -#define DDRSS3_PI_91_DATA 0x00000400 -#define DDRSS3_PI_92_DATA 0x02010000 -#define DDRSS3_PI_93_DATA 0x00080003 -#define DDRSS3_PI_94_DATA 0x00080000 -#define DDRSS3_PI_95_DATA 0x00000001 -#define DDRSS3_PI_96_DATA 0x00000000 -#define DDRSS3_PI_97_DATA 0x0000AA00 -#define DDRSS3_PI_98_DATA 0x00000000 -#define DDRSS3_PI_99_DATA 0x00000000 -#define DDRSS3_PI_100_DATA 0x00010000 -#define DDRSS3_PI_101_DATA 0x00000000 -#define DDRSS3_PI_102_DATA 0x00000000 -#define DDRSS3_PI_103_DATA 0x00000000 -#define DDRSS3_PI_104_DATA 0x00000000 -#define DDRSS3_PI_105_DATA 0x00000000 -#define DDRSS3_PI_106_DATA 0x00000000 -#define DDRSS3_PI_107_DATA 0x00000000 -#define DDRSS3_PI_108_DATA 0x00000000 -#define DDRSS3_PI_109_DATA 0x00000000 -#define DDRSS3_PI_110_DATA 0x00000000 -#define DDRSS3_PI_111_DATA 0x00000000 -#define DDRSS3_PI_112_DATA 0x00000000 -#define DDRSS3_PI_113_DATA 0x00000000 -#define DDRSS3_PI_114_DATA 0x00000000 -#define DDRSS3_PI_115_DATA 0x00000000 -#define DDRSS3_PI_116_DATA 0x00000000 -#define DDRSS3_PI_117_DATA 0x00000000 -#define DDRSS3_PI_118_DATA 0x00000000 -#define DDRSS3_PI_119_DATA 0x00000000 -#define DDRSS3_PI_120_DATA 0x00000000 -#define DDRSS3_PI_121_DATA 0x00000000 -#define DDRSS3_PI_122_DATA 0x00000000 -#define DDRSS3_PI_123_DATA 0x00000000 -#define DDRSS3_PI_124_DATA 0x00000000 -#define DDRSS3_PI_125_DATA 0x00000008 -#define DDRSS3_PI_126_DATA 0x00000000 -#define DDRSS3_PI_127_DATA 0x00000000 -#define DDRSS3_PI_128_DATA 0x00000000 -#define DDRSS3_PI_129_DATA 0x00000000 -#define DDRSS3_PI_130_DATA 0x00000000 -#define DDRSS3_PI_131_DATA 0x00000000 -#define DDRSS3_PI_132_DATA 0x00000000 -#define DDRSS3_PI_133_DATA 0x00000000 -#define DDRSS3_PI_134_DATA 0x00000002 -#define DDRSS3_PI_135_DATA 0x00000000 -#define DDRSS3_PI_136_DATA 0x00000000 -#define DDRSS3_PI_137_DATA 0x0000000A -#define DDRSS3_PI_138_DATA 0x00000019 -#define DDRSS3_PI_139_DATA 0x00000100 -#define DDRSS3_PI_140_DATA 0x00000000 -#define DDRSS3_PI_141_DATA 0x00000000 -#define DDRSS3_PI_142_DATA 0x00000000 -#define DDRSS3_PI_143_DATA 0x00000000 -#define DDRSS3_PI_144_DATA 0x01000000 -#define DDRSS3_PI_145_DATA 0x00010003 -#define DDRSS3_PI_146_DATA 0x02000101 -#define DDRSS3_PI_147_DATA 0x01030001 -#define DDRSS3_PI_148_DATA 0x00010400 -#define DDRSS3_PI_149_DATA 0x06000105 -#define DDRSS3_PI_150_DATA 0x01070001 -#define DDRSS3_PI_151_DATA 0x00000000 -#define DDRSS3_PI_152_DATA 0x00000000 -#define DDRSS3_PI_153_DATA 0x00000000 -#define DDRSS3_PI_154_DATA 0x00010001 -#define DDRSS3_PI_155_DATA 0x00000000 -#define DDRSS3_PI_156_DATA 0x00000000 -#define DDRSS3_PI_157_DATA 0x00000000 -#define DDRSS3_PI_158_DATA 0x00000000 -#define DDRSS3_PI_159_DATA 0x00000401 -#define DDRSS3_PI_160_DATA 0x00000000 -#define DDRSS3_PI_161_DATA 0x00010000 -#define DDRSS3_PI_162_DATA 0x00000000 -#define DDRSS3_PI_163_DATA 0x2B2B0200 -#define DDRSS3_PI_164_DATA 0x00000034 -#define DDRSS3_PI_165_DATA 0x00000064 -#define DDRSS3_PI_166_DATA 0x00020064 -#define DDRSS3_PI_167_DATA 0x02000200 -#define DDRSS3_PI_168_DATA 0x48120C04 -#define DDRSS3_PI_169_DATA 0x00154812 -#define DDRSS3_PI_170_DATA 0x000000CE -#define DDRSS3_PI_171_DATA 0x0000032B -#define DDRSS3_PI_172_DATA 0x00002073 -#define DDRSS3_PI_173_DATA 0x0000032B -#define DDRSS3_PI_174_DATA 0x04002073 -#define DDRSS3_PI_175_DATA 0x01010404 -#define DDRSS3_PI_176_DATA 0x00001501 -#define DDRSS3_PI_177_DATA 0x00150015 -#define DDRSS3_PI_178_DATA 0x01000100 -#define DDRSS3_PI_179_DATA 0x00000100 -#define DDRSS3_PI_180_DATA 0x00000000 -#define DDRSS3_PI_181_DATA 0x01010101 -#define DDRSS3_PI_182_DATA 0x00000101 -#define DDRSS3_PI_183_DATA 0x00000000 -#define DDRSS3_PI_184_DATA 0x00000000 -#define DDRSS3_PI_185_DATA 0x15040000 -#define DDRSS3_PI_186_DATA 0x0E0E0215 -#define DDRSS3_PI_187_DATA 0x00040402 -#define DDRSS3_PI_188_DATA 0x000D0035 -#define DDRSS3_PI_189_DATA 0x00218049 -#define DDRSS3_PI_190_DATA 0x00218049 -#define DDRSS3_PI_191_DATA 0x01010101 -#define DDRSS3_PI_192_DATA 0x0004000E -#define DDRSS3_PI_193_DATA 0x00040216 -#define DDRSS3_PI_194_DATA 0x01000216 -#define DDRSS3_PI_195_DATA 0x000F000F -#define DDRSS3_PI_196_DATA 0x02170100 -#define DDRSS3_PI_197_DATA 0x01000217 -#define DDRSS3_PI_198_DATA 0x02170217 -#define DDRSS3_PI_199_DATA 0x32103200 -#define DDRSS3_PI_200_DATA 0x01013210 -#define DDRSS3_PI_201_DATA 0x0A070601 -#define DDRSS3_PI_202_DATA 0x1F130A0D -#define DDRSS3_PI_203_DATA 0x1F130A14 -#define DDRSS3_PI_204_DATA 0x0000C014 -#define DDRSS3_PI_205_DATA 0x00C01000 -#define DDRSS3_PI_206_DATA 0x00C01000 -#define DDRSS3_PI_207_DATA 0x00021000 -#define DDRSS3_PI_208_DATA 0x0024000E -#define DDRSS3_PI_209_DATA 0x00240216 -#define DDRSS3_PI_210_DATA 0x00110216 -#define DDRSS3_PI_211_DATA 0x32000056 -#define DDRSS3_PI_212_DATA 0x00000301 -#define DDRSS3_PI_213_DATA 0x005B0036 -#define DDRSS3_PI_214_DATA 0x03013212 -#define DDRSS3_PI_215_DATA 0x00003600 -#define DDRSS3_PI_216_DATA 0x3212005B -#define DDRSS3_PI_217_DATA 0x09000301 -#define DDRSS3_PI_218_DATA 0x04010504 -#define DDRSS3_PI_219_DATA 0x040006C9 -#define DDRSS3_PI_220_DATA 0x0A032001 -#define DDRSS3_PI_221_DATA 0x2C31110A -#define DDRSS3_PI_222_DATA 0x00002918 -#define DDRSS3_PI_223_DATA 0x6001071C -#define DDRSS3_PI_224_DATA 0x1E202008 -#define DDRSS3_PI_225_DATA 0x2C311116 -#define DDRSS3_PI_226_DATA 0x00002918 -#define DDRSS3_PI_227_DATA 0x6001071C -#define DDRSS3_PI_228_DATA 0x1E202008 -#define DDRSS3_PI_229_DATA 0x00019C16 -#define DDRSS3_PI_230_DATA 0x00001018 -#define DDRSS3_PI_231_DATA 0x000040E6 -#define DDRSS3_PI_232_DATA 0x000288FC -#define DDRSS3_PI_233_DATA 0x000040E6 -#define DDRSS3_PI_234_DATA 0x000288FC -#define DDRSS3_PI_235_DATA 0x033B0016 -#define DDRSS3_PI_236_DATA 0x0303033B -#define DDRSS3_PI_237_DATA 0x002AF803 -#define DDRSS3_PI_238_DATA 0x0001ADAF -#define DDRSS3_PI_239_DATA 0x00000005 -#define DDRSS3_PI_240_DATA 0x0000006E -#define DDRSS3_PI_241_DATA 0x00000016 -#define DDRSS3_PI_242_DATA 0x000681C8 -#define DDRSS3_PI_243_DATA 0x0001ADAF -#define DDRSS3_PI_244_DATA 0x00000005 -#define DDRSS3_PI_245_DATA 0x000010A9 -#define DDRSS3_PI_246_DATA 0x0000033B -#define DDRSS3_PI_247_DATA 0x000681C8 -#define DDRSS3_PI_248_DATA 0x0001ADAF -#define DDRSS3_PI_249_DATA 0x00000005 -#define DDRSS3_PI_250_DATA 0x000010A9 -#define DDRSS3_PI_251_DATA 0x0100033B -#define DDRSS3_PI_252_DATA 0x00370040 -#define DDRSS3_PI_253_DATA 0x00010008 -#define DDRSS3_PI_254_DATA 0x08550040 -#define DDRSS3_PI_255_DATA 0x00010040 -#define DDRSS3_PI_256_DATA 0x08550040 -#define DDRSS3_PI_257_DATA 0x00000340 -#define DDRSS3_PI_258_DATA 0x006B006B -#define DDRSS3_PI_259_DATA 0x08040404 -#define DDRSS3_PI_260_DATA 0x00000055 -#define DDRSS3_PI_261_DATA 0x55083C5A -#define DDRSS3_PI_262_DATA 0x5A000000 -#define DDRSS3_PI_263_DATA 0x0055083C -#define DDRSS3_PI_264_DATA 0x3C5A0000 -#define DDRSS3_PI_265_DATA 0x00005508 -#define DDRSS3_PI_266_DATA 0x0C3C5A00 -#define DDRSS3_PI_267_DATA 0x080F0E0D -#define DDRSS3_PI_268_DATA 0x000B0A09 -#define DDRSS3_PI_269_DATA 0x00030201 -#define DDRSS3_PI_270_DATA 0x01000000 -#define DDRSS3_PI_271_DATA 0x04020201 -#define DDRSS3_PI_272_DATA 0x00080804 -#define DDRSS3_PI_273_DATA 0x00000000 -#define DDRSS3_PI_274_DATA 0x00000000 -#define DDRSS3_PI_275_DATA 0x00330084 -#define DDRSS3_PI_276_DATA 0x00160000 -#define DDRSS3_PI_277_DATA 0x35333FF4 -#define DDRSS3_PI_278_DATA 0x00160F27 -#define DDRSS3_PI_279_DATA 0x35333FF4 -#define DDRSS3_PI_280_DATA 0x00160F27 -#define DDRSS3_PI_281_DATA 0x00330084 -#define DDRSS3_PI_282_DATA 0x00160000 -#define DDRSS3_PI_283_DATA 0x35333FF4 -#define DDRSS3_PI_284_DATA 0x00160F27 -#define DDRSS3_PI_285_DATA 0x35333FF4 -#define DDRSS3_PI_286_DATA 0x00160F27 -#define DDRSS3_PI_287_DATA 0x00330084 -#define DDRSS3_PI_288_DATA 0x00160000 -#define DDRSS3_PI_289_DATA 0x35333FF4 -#define DDRSS3_PI_290_DATA 0x00160F27 -#define DDRSS3_PI_291_DATA 0x35333FF4 -#define DDRSS3_PI_292_DATA 0x00160F27 -#define DDRSS3_PI_293_DATA 0x00330084 -#define DDRSS3_PI_294_DATA 0x00160000 -#define DDRSS3_PI_295_DATA 0x35333FF4 -#define DDRSS3_PI_296_DATA 0x00160F27 -#define DDRSS3_PI_297_DATA 0x35333FF4 -#define DDRSS3_PI_298_DATA 0x00160F27 -#define DDRSS3_PI_299_DATA 0x00000000 -#define DDRSS3_PHY_00_DATA 0x000004F0 -#define DDRSS3_PHY_01_DATA 0x00000000 -#define DDRSS3_PHY_02_DATA 0x00030200 -#define DDRSS3_PHY_03_DATA 0x00000000 -#define DDRSS3_PHY_04_DATA 0x00000000 -#define DDRSS3_PHY_05_DATA 0x01030000 -#define DDRSS3_PHY_06_DATA 0x00010000 -#define DDRSS3_PHY_07_DATA 0x01030004 -#define DDRSS3_PHY_08_DATA 0x01000000 -#define DDRSS3_PHY_09_DATA 0x00000000 -#define DDRSS3_PHY_10_DATA 0x00000000 -#define DDRSS3_PHY_11_DATA 0x01000001 -#define DDRSS3_PHY_12_DATA 0x00000100 -#define DDRSS3_PHY_13_DATA 0x000800C0 -#define DDRSS3_PHY_14_DATA 0x060100CC -#define DDRSS3_PHY_15_DATA 0x00030066 -#define DDRSS3_PHY_16_DATA 0x00000000 -#define DDRSS3_PHY_17_DATA 0x00000301 -#define DDRSS3_PHY_18_DATA 0x0000AAAA -#define DDRSS3_PHY_19_DATA 0x00005555 -#define DDRSS3_PHY_20_DATA 0x0000B5B5 -#define DDRSS3_PHY_21_DATA 0x00004A4A -#define DDRSS3_PHY_22_DATA 0x00005656 -#define DDRSS3_PHY_23_DATA 0x0000A9A9 -#define DDRSS3_PHY_24_DATA 0x0000A9A9 -#define DDRSS3_PHY_25_DATA 0x0000B5B5 -#define DDRSS3_PHY_26_DATA 0x00000000 -#define DDRSS3_PHY_27_DATA 0x00000000 -#define DDRSS3_PHY_28_DATA 0x2A000000 -#define DDRSS3_PHY_29_DATA 0x00000808 -#define DDRSS3_PHY_30_DATA 0x0F000000 -#define DDRSS3_PHY_31_DATA 0x00000F0F -#define DDRSS3_PHY_32_DATA 0x10400000 -#define DDRSS3_PHY_33_DATA 0x0C002006 -#define DDRSS3_PHY_34_DATA 0x00000000 -#define DDRSS3_PHY_35_DATA 0x00000000 -#define DDRSS3_PHY_36_DATA 0x55555555 -#define DDRSS3_PHY_37_DATA 0xAAAAAAAA -#define DDRSS3_PHY_38_DATA 0x55555555 -#define DDRSS3_PHY_39_DATA 0xAAAAAAAA -#define DDRSS3_PHY_40_DATA 0x00005555 -#define DDRSS3_PHY_41_DATA 0x01000100 -#define DDRSS3_PHY_42_DATA 0x00800180 -#define DDRSS3_PHY_43_DATA 0x00000001 -#define DDRSS3_PHY_44_DATA 0x00000000 -#define DDRSS3_PHY_45_DATA 0x00000000 -#define DDRSS3_PHY_46_DATA 0x00000000 -#define DDRSS3_PHY_47_DATA 0x00000000 -#define DDRSS3_PHY_48_DATA 0x00000000 -#define DDRSS3_PHY_49_DATA 0x00000000 -#define DDRSS3_PHY_50_DATA 0x00000000 -#define DDRSS3_PHY_51_DATA 0x00000000 -#define DDRSS3_PHY_52_DATA 0x00000000 -#define DDRSS3_PHY_53_DATA 0x00000000 -#define DDRSS3_PHY_54_DATA 0x00000000 -#define DDRSS3_PHY_55_DATA 0x00000000 -#define DDRSS3_PHY_56_DATA 0x00000000 -#define DDRSS3_PHY_57_DATA 0x00000000 -#define DDRSS3_PHY_58_DATA 0x00000000 -#define DDRSS3_PHY_59_DATA 0x00000000 -#define DDRSS3_PHY_60_DATA 0x00000000 -#define DDRSS3_PHY_61_DATA 0x00000000 -#define DDRSS3_PHY_62_DATA 0x00000000 -#define DDRSS3_PHY_63_DATA 0x00000000 -#define DDRSS3_PHY_64_DATA 0x00000000 -#define DDRSS3_PHY_65_DATA 0x00000000 -#define DDRSS3_PHY_66_DATA 0x00000104 -#define DDRSS3_PHY_67_DATA 0x00000120 -#define DDRSS3_PHY_68_DATA 0x00000000 -#define DDRSS3_PHY_69_DATA 0x00000000 -#define DDRSS3_PHY_70_DATA 0x00000000 -#define DDRSS3_PHY_71_DATA 0x00000000 -#define DDRSS3_PHY_72_DATA 0x00000000 -#define DDRSS3_PHY_73_DATA 0x00000000 -#define DDRSS3_PHY_74_DATA 0x00000000 -#define DDRSS3_PHY_75_DATA 0x00000001 -#define DDRSS3_PHY_76_DATA 0x07FF0000 -#define DDRSS3_PHY_77_DATA 0x0080081F -#define DDRSS3_PHY_78_DATA 0x00081020 -#define DDRSS3_PHY_79_DATA 0x04010000 -#define DDRSS3_PHY_80_DATA 0x00000000 -#define DDRSS3_PHY_81_DATA 0x00000000 -#define DDRSS3_PHY_82_DATA 0x00000000 -#define DDRSS3_PHY_83_DATA 0x00000100 -#define DDRSS3_PHY_84_DATA 0x01CC0C01 -#define DDRSS3_PHY_85_DATA 0x1003CC0C -#define DDRSS3_PHY_86_DATA 0x20000140 -#define DDRSS3_PHY_87_DATA 0x07FF0200 -#define DDRSS3_PHY_88_DATA 0x0000DD01 -#define DDRSS3_PHY_89_DATA 0x10100303 -#define DDRSS3_PHY_90_DATA 0x10101010 -#define DDRSS3_PHY_91_DATA 0x10101010 -#define DDRSS3_PHY_92_DATA 0x00021010 -#define DDRSS3_PHY_93_DATA 0x00100010 -#define DDRSS3_PHY_94_DATA 0x00100010 -#define DDRSS3_PHY_95_DATA 0x00100010 -#define DDRSS3_PHY_96_DATA 0x00100010 -#define DDRSS3_PHY_97_DATA 0x00050010 -#define DDRSS3_PHY_98_DATA 0x51517041 -#define DDRSS3_PHY_99_DATA 0x31C06001 -#define DDRSS3_PHY_100_DATA 0x07AB0340 -#define DDRSS3_PHY_101_DATA 0x00C0C001 -#define DDRSS3_PHY_102_DATA 0x0E0D0001 -#define DDRSS3_PHY_103_DATA 0x10001000 -#define DDRSS3_PHY_104_DATA 0x0C083E42 -#define DDRSS3_PHY_105_DATA 0x0F0C3701 -#define DDRSS3_PHY_106_DATA 0x01000140 -#define DDRSS3_PHY_107_DATA 0x0C000420 -#define DDRSS3_PHY_108_DATA 0x00000198 -#define DDRSS3_PHY_109_DATA 0x0A0000D0 -#define DDRSS3_PHY_110_DATA 0x00030200 -#define DDRSS3_PHY_111_DATA 0x02800000 -#define DDRSS3_PHY_112_DATA 0x80800000 -#define DDRSS3_PHY_113_DATA 0x000E2010 -#define DDRSS3_PHY_114_DATA 0x76543210 -#define DDRSS3_PHY_115_DATA 0x00000008 -#define DDRSS3_PHY_116_DATA 0x02800280 -#define DDRSS3_PHY_117_DATA 0x02800280 -#define DDRSS3_PHY_118_DATA 0x02800280 -#define DDRSS3_PHY_119_DATA 0x02800280 -#define DDRSS3_PHY_120_DATA 0x00000280 -#define DDRSS3_PHY_121_DATA 0x0000A000 -#define DDRSS3_PHY_122_DATA 0x00A000A0 -#define DDRSS3_PHY_123_DATA 0x00A000A0 -#define DDRSS3_PHY_124_DATA 0x00A000A0 -#define DDRSS3_PHY_125_DATA 0x00A000A0 -#define DDRSS3_PHY_126_DATA 0x00A000A0 -#define DDRSS3_PHY_127_DATA 0x00A000A0 -#define DDRSS3_PHY_128_DATA 0x00A000A0 -#define DDRSS3_PHY_129_DATA 0x00A000A0 -#define DDRSS3_PHY_130_DATA 0x01C200A0 -#define DDRSS3_PHY_131_DATA 0x01A00005 -#define DDRSS3_PHY_132_DATA 0x00000000 -#define DDRSS3_PHY_133_DATA 0x00000000 -#define DDRSS3_PHY_134_DATA 0x00080200 -#define DDRSS3_PHY_135_DATA 0x00000000 -#define DDRSS3_PHY_136_DATA 0x20202000 -#define DDRSS3_PHY_137_DATA 0x20202020 -#define DDRSS3_PHY_138_DATA 0xF0F02020 -#define DDRSS3_PHY_139_DATA 0x00000000 -#define DDRSS3_PHY_140_DATA 0x00000000 -#define DDRSS3_PHY_141_DATA 0x00000000 -#define DDRSS3_PHY_142_DATA 0x00000000 -#define DDRSS3_PHY_143_DATA 0x00000000 -#define DDRSS3_PHY_144_DATA 0x00000000 -#define DDRSS3_PHY_145_DATA 0x00000000 -#define DDRSS3_PHY_146_DATA 0x00000000 -#define DDRSS3_PHY_147_DATA 0x00000000 -#define DDRSS3_PHY_148_DATA 0x00000000 -#define DDRSS3_PHY_149_DATA 0x00000000 -#define DDRSS3_PHY_150_DATA 0x00000000 -#define DDRSS3_PHY_151_DATA 0x00000000 -#define DDRSS3_PHY_152_DATA 0x00000000 -#define DDRSS3_PHY_153_DATA 0x00000000 -#define DDRSS3_PHY_154_DATA 0x00000000 -#define DDRSS3_PHY_155_DATA 0x00000000 -#define DDRSS3_PHY_156_DATA 0x00000000 -#define DDRSS3_PHY_157_DATA 0x00000000 -#define DDRSS3_PHY_158_DATA 0x00000000 -#define DDRSS3_PHY_159_DATA 0x00000000 -#define DDRSS3_PHY_160_DATA 0x00000000 -#define DDRSS3_PHY_161_DATA 0x00000000 -#define DDRSS3_PHY_162_DATA 0x00000000 -#define DDRSS3_PHY_163_DATA 0x00000000 -#define DDRSS3_PHY_164_DATA 0x00000000 -#define DDRSS3_PHY_165_DATA 0x00000000 -#define DDRSS3_PHY_166_DATA 0x00000000 -#define DDRSS3_PHY_167_DATA 0x00000000 -#define DDRSS3_PHY_168_DATA 0x00000000 -#define DDRSS3_PHY_169_DATA 0x00000000 -#define DDRSS3_PHY_170_DATA 0x00000000 -#define DDRSS3_PHY_171_DATA 0x00000000 -#define DDRSS3_PHY_172_DATA 0x00000000 -#define DDRSS3_PHY_173_DATA 0x00000000 -#define DDRSS3_PHY_174_DATA 0x00000000 -#define DDRSS3_PHY_175_DATA 0x00000000 -#define DDRSS3_PHY_176_DATA 0x00000000 -#define DDRSS3_PHY_177_DATA 0x00000000 -#define DDRSS3_PHY_178_DATA 0x00000000 -#define DDRSS3_PHY_179_DATA 0x00000000 -#define DDRSS3_PHY_180_DATA 0x00000000 -#define DDRSS3_PHY_181_DATA 0x00000000 -#define DDRSS3_PHY_182_DATA 0x00000000 -#define DDRSS3_PHY_183_DATA 0x00000000 -#define DDRSS3_PHY_184_DATA 0x00000000 -#define DDRSS3_PHY_185_DATA 0x00000000 -#define DDRSS3_PHY_186_DATA 0x00000000 -#define DDRSS3_PHY_187_DATA 0x00000000 -#define DDRSS3_PHY_188_DATA 0x00000000 -#define DDRSS3_PHY_189_DATA 0x00000000 -#define DDRSS3_PHY_190_DATA 0x00000000 -#define DDRSS3_PHY_191_DATA 0x00000000 -#define DDRSS3_PHY_192_DATA 0x00000000 -#define DDRSS3_PHY_193_DATA 0x00000000 -#define DDRSS3_PHY_194_DATA 0x00000000 -#define DDRSS3_PHY_195_DATA 0x00000000 -#define DDRSS3_PHY_196_DATA 0x00000000 -#define DDRSS3_PHY_197_DATA 0x00000000 -#define DDRSS3_PHY_198_DATA 0x00000000 -#define DDRSS3_PHY_199_DATA 0x00000000 -#define DDRSS3_PHY_200_DATA 0x00000000 -#define DDRSS3_PHY_201_DATA 0x00000000 -#define DDRSS3_PHY_202_DATA 0x00000000 -#define DDRSS3_PHY_203_DATA 0x00000000 -#define DDRSS3_PHY_204_DATA 0x00000000 -#define DDRSS3_PHY_205_DATA 0x00000000 -#define DDRSS3_PHY_206_DATA 0x00000000 -#define DDRSS3_PHY_207_DATA 0x00000000 -#define DDRSS3_PHY_208_DATA 0x00000000 -#define DDRSS3_PHY_209_DATA 0x00000000 -#define DDRSS3_PHY_210_DATA 0x00000000 -#define DDRSS3_PHY_211_DATA 0x00000000 -#define DDRSS3_PHY_212_DATA 0x00000000 -#define DDRSS3_PHY_213_DATA 0x00000000 -#define DDRSS3_PHY_214_DATA 0x00000000 -#define DDRSS3_PHY_215_DATA 0x00000000 -#define DDRSS3_PHY_216_DATA 0x00000000 -#define DDRSS3_PHY_217_DATA 0x00000000 -#define DDRSS3_PHY_218_DATA 0x00000000 -#define DDRSS3_PHY_219_DATA 0x00000000 -#define DDRSS3_PHY_220_DATA 0x00000000 -#define DDRSS3_PHY_221_DATA 0x00000000 -#define DDRSS3_PHY_222_DATA 0x00000000 -#define DDRSS3_PHY_223_DATA 0x00000000 -#define DDRSS3_PHY_224_DATA 0x00000000 -#define DDRSS3_PHY_225_DATA 0x00000000 -#define DDRSS3_PHY_226_DATA 0x00000000 -#define DDRSS3_PHY_227_DATA 0x00000000 -#define DDRSS3_PHY_228_DATA 0x00000000 -#define DDRSS3_PHY_229_DATA 0x00000000 -#define DDRSS3_PHY_230_DATA 0x00000000 -#define DDRSS3_PHY_231_DATA 0x00000000 -#define DDRSS3_PHY_232_DATA 0x00000000 -#define DDRSS3_PHY_233_DATA 0x00000000 -#define DDRSS3_PHY_234_DATA 0x00000000 -#define DDRSS3_PHY_235_DATA 0x00000000 -#define DDRSS3_PHY_236_DATA 0x00000000 -#define DDRSS3_PHY_237_DATA 0x00000000 -#define DDRSS3_PHY_238_DATA 0x00000000 -#define DDRSS3_PHY_239_DATA 0x00000000 -#define DDRSS3_PHY_240_DATA 0x00000000 -#define DDRSS3_PHY_241_DATA 0x00000000 -#define DDRSS3_PHY_242_DATA 0x00000000 -#define DDRSS3_PHY_243_DATA 0x00000000 -#define DDRSS3_PHY_244_DATA 0x00000000 -#define DDRSS3_PHY_245_DATA 0x00000000 -#define DDRSS3_PHY_246_DATA 0x00000000 -#define DDRSS3_PHY_247_DATA 0x00000000 -#define DDRSS3_PHY_248_DATA 0x00000000 -#define DDRSS3_PHY_249_DATA 0x00000000 -#define DDRSS3_PHY_250_DATA 0x00000000 -#define DDRSS3_PHY_251_DATA 0x00000000 -#define DDRSS3_PHY_252_DATA 0x00000000 -#define DDRSS3_PHY_253_DATA 0x00000000 -#define DDRSS3_PHY_254_DATA 0x00000000 -#define DDRSS3_PHY_255_DATA 0x00000000 -#define DDRSS3_PHY_256_DATA 0x000004F0 -#define DDRSS3_PHY_257_DATA 0x00000000 -#define DDRSS3_PHY_258_DATA 0x00030200 -#define DDRSS3_PHY_259_DATA 0x00000000 -#define DDRSS3_PHY_260_DATA 0x00000000 -#define DDRSS3_PHY_261_DATA 0x01030000 -#define DDRSS3_PHY_262_DATA 0x00010000 -#define DDRSS3_PHY_263_DATA 0x01030004 -#define DDRSS3_PHY_264_DATA 0x01000000 -#define DDRSS3_PHY_265_DATA 0x00000000 -#define DDRSS3_PHY_266_DATA 0x00000000 -#define DDRSS3_PHY_267_DATA 0x01000001 -#define DDRSS3_PHY_268_DATA 0x00000100 -#define DDRSS3_PHY_269_DATA 0x000800C0 -#define DDRSS3_PHY_270_DATA 0x060100CC -#define DDRSS3_PHY_271_DATA 0x00030066 -#define DDRSS3_PHY_272_DATA 0x00000000 -#define DDRSS3_PHY_273_DATA 0x00000301 -#define DDRSS3_PHY_274_DATA 0x0000AAAA -#define DDRSS3_PHY_275_DATA 0x00005555 -#define DDRSS3_PHY_276_DATA 0x0000B5B5 -#define DDRSS3_PHY_277_DATA 0x00004A4A -#define DDRSS3_PHY_278_DATA 0x00005656 -#define DDRSS3_PHY_279_DATA 0x0000A9A9 -#define DDRSS3_PHY_280_DATA 0x0000A9A9 -#define DDRSS3_PHY_281_DATA 0x0000B5B5 -#define DDRSS3_PHY_282_DATA 0x00000000 -#define DDRSS3_PHY_283_DATA 0x00000000 -#define DDRSS3_PHY_284_DATA 0x2A000000 -#define DDRSS3_PHY_285_DATA 0x00000808 -#define DDRSS3_PHY_286_DATA 0x0F000000 -#define DDRSS3_PHY_287_DATA 0x00000F0F -#define DDRSS3_PHY_288_DATA 0x10400000 -#define DDRSS3_PHY_289_DATA 0x0C002006 -#define DDRSS3_PHY_290_DATA 0x00000000 -#define DDRSS3_PHY_291_DATA 0x00000000 -#define DDRSS3_PHY_292_DATA 0x55555555 -#define DDRSS3_PHY_293_DATA 0xAAAAAAAA -#define DDRSS3_PHY_294_DATA 0x55555555 -#define DDRSS3_PHY_295_DATA 0xAAAAAAAA -#define DDRSS3_PHY_296_DATA 0x00005555 -#define DDRSS3_PHY_297_DATA 0x01000100 -#define DDRSS3_PHY_298_DATA 0x00800180 -#define DDRSS3_PHY_299_DATA 0x00000000 -#define DDRSS3_PHY_300_DATA 0x00000000 -#define DDRSS3_PHY_301_DATA 0x00000000 -#define DDRSS3_PHY_302_DATA 0x00000000 -#define DDRSS3_PHY_303_DATA 0x00000000 -#define DDRSS3_PHY_304_DATA 0x00000000 -#define DDRSS3_PHY_305_DATA 0x00000000 -#define DDRSS3_PHY_306_DATA 0x00000000 -#define DDRSS3_PHY_307_DATA 0x00000000 -#define DDRSS3_PHY_308_DATA 0x00000000 -#define DDRSS3_PHY_309_DATA 0x00000000 -#define DDRSS3_PHY_310_DATA 0x00000000 -#define DDRSS3_PHY_311_DATA 0x00000000 -#define DDRSS3_PHY_312_DATA 0x00000000 -#define DDRSS3_PHY_313_DATA 0x00000000 -#define DDRSS3_PHY_314_DATA 0x00000000 -#define DDRSS3_PHY_315_DATA 0x00000000 -#define DDRSS3_PHY_316_DATA 0x00000000 -#define DDRSS3_PHY_317_DATA 0x00000000 -#define DDRSS3_PHY_318_DATA 0x00000000 -#define DDRSS3_PHY_319_DATA 0x00000000 -#define DDRSS3_PHY_320_DATA 0x00000000 -#define DDRSS3_PHY_321_DATA 0x00000000 -#define DDRSS3_PHY_322_DATA 0x00000104 -#define DDRSS3_PHY_323_DATA 0x00000120 -#define DDRSS3_PHY_324_DATA 0x00000000 -#define DDRSS3_PHY_325_DATA 0x00000000 -#define DDRSS3_PHY_326_DATA 0x00000000 -#define DDRSS3_PHY_327_DATA 0x00000000 -#define DDRSS3_PHY_328_DATA 0x00000000 -#define DDRSS3_PHY_329_DATA 0x00000000 -#define DDRSS3_PHY_330_DATA 0x00000000 -#define DDRSS3_PHY_331_DATA 0x00000001 -#define DDRSS3_PHY_332_DATA 0x07FF0000 -#define DDRSS3_PHY_333_DATA 0x0080081F -#define DDRSS3_PHY_334_DATA 0x00081020 -#define DDRSS3_PHY_335_DATA 0x04010000 -#define DDRSS3_PHY_336_DATA 0x00000000 -#define DDRSS3_PHY_337_DATA 0x00000000 -#define DDRSS3_PHY_338_DATA 0x00000000 -#define DDRSS3_PHY_339_DATA 0x00000100 -#define DDRSS3_PHY_340_DATA 0x01CC0C01 -#define DDRSS3_PHY_341_DATA 0x1003CC0C -#define DDRSS3_PHY_342_DATA 0x20000140 -#define DDRSS3_PHY_343_DATA 0x07FF0200 -#define DDRSS3_PHY_344_DATA 0x0000DD01 -#define DDRSS3_PHY_345_DATA 0x10100303 -#define DDRSS3_PHY_346_DATA 0x10101010 -#define DDRSS3_PHY_347_DATA 0x10101010 -#define DDRSS3_PHY_348_DATA 0x00021010 -#define DDRSS3_PHY_349_DATA 0x00100010 -#define DDRSS3_PHY_350_DATA 0x00100010 -#define DDRSS3_PHY_351_DATA 0x00100010 -#define DDRSS3_PHY_352_DATA 0x00100010 -#define DDRSS3_PHY_353_DATA 0x00050010 -#define DDRSS3_PHY_354_DATA 0x51517041 -#define DDRSS3_PHY_355_DATA 0x31C06001 -#define DDRSS3_PHY_356_DATA 0x07AB0340 -#define DDRSS3_PHY_357_DATA 0x00C0C001 -#define DDRSS3_PHY_358_DATA 0x0E0D0001 -#define DDRSS3_PHY_359_DATA 0x10001000 -#define DDRSS3_PHY_360_DATA 0x0C083E42 -#define DDRSS3_PHY_361_DATA 0x0F0C3701 -#define DDRSS3_PHY_362_DATA 0x01000140 -#define DDRSS3_PHY_363_DATA 0x0C000420 -#define DDRSS3_PHY_364_DATA 0x00000198 -#define DDRSS3_PHY_365_DATA 0x0A0000D0 -#define DDRSS3_PHY_366_DATA 0x00030200 -#define DDRSS3_PHY_367_DATA 0x02800000 -#define DDRSS3_PHY_368_DATA 0x80800000 -#define DDRSS3_PHY_369_DATA 0x000E2010 -#define DDRSS3_PHY_370_DATA 0x76543210 -#define DDRSS3_PHY_371_DATA 0x00000008 -#define DDRSS3_PHY_372_DATA 0x02800280 -#define DDRSS3_PHY_373_DATA 0x02800280 -#define DDRSS3_PHY_374_DATA 0x02800280 -#define DDRSS3_PHY_375_DATA 0x02800280 -#define DDRSS3_PHY_376_DATA 0x00000280 -#define DDRSS3_PHY_377_DATA 0x0000A000 -#define DDRSS3_PHY_378_DATA 0x00A000A0 -#define DDRSS3_PHY_379_DATA 0x00A000A0 -#define DDRSS3_PHY_380_DATA 0x00A000A0 -#define DDRSS3_PHY_381_DATA 0x00A000A0 -#define DDRSS3_PHY_382_DATA 0x00A000A0 -#define DDRSS3_PHY_383_DATA 0x00A000A0 -#define DDRSS3_PHY_384_DATA 0x00A000A0 -#define DDRSS3_PHY_385_DATA 0x00A000A0 -#define DDRSS3_PHY_386_DATA 0x01C200A0 -#define DDRSS3_PHY_387_DATA 0x01A00005 -#define DDRSS3_PHY_388_DATA 0x00000000 -#define DDRSS3_PHY_389_DATA 0x00000000 -#define DDRSS3_PHY_390_DATA 0x00080200 -#define DDRSS3_PHY_391_DATA 0x00000000 -#define DDRSS3_PHY_392_DATA 0x20202000 -#define DDRSS3_PHY_393_DATA 0x20202020 -#define DDRSS3_PHY_394_DATA 0xF0F02020 -#define DDRSS3_PHY_395_DATA 0x00000000 -#define DDRSS3_PHY_396_DATA 0x00000000 -#define DDRSS3_PHY_397_DATA 0x00000000 -#define DDRSS3_PHY_398_DATA 0x00000000 -#define DDRSS3_PHY_399_DATA 0x00000000 -#define DDRSS3_PHY_400_DATA 0x00000000 -#define DDRSS3_PHY_401_DATA 0x00000000 -#define DDRSS3_PHY_402_DATA 0x00000000 -#define DDRSS3_PHY_403_DATA 0x00000000 -#define DDRSS3_PHY_404_DATA 0x00000000 -#define DDRSS3_PHY_405_DATA 0x00000000 -#define DDRSS3_PHY_406_DATA 0x00000000 -#define DDRSS3_PHY_407_DATA 0x00000000 -#define DDRSS3_PHY_408_DATA 0x00000000 -#define DDRSS3_PHY_409_DATA 0x00000000 -#define DDRSS3_PHY_410_DATA 0x00000000 -#define DDRSS3_PHY_411_DATA 0x00000000 -#define DDRSS3_PHY_412_DATA 0x00000000 -#define DDRSS3_PHY_413_DATA 0x00000000 -#define DDRSS3_PHY_414_DATA 0x00000000 -#define DDRSS3_PHY_415_DATA 0x00000000 -#define DDRSS3_PHY_416_DATA 0x00000000 -#define DDRSS3_PHY_417_DATA 0x00000000 -#define DDRSS3_PHY_418_DATA 0x00000000 -#define DDRSS3_PHY_419_DATA 0x00000000 -#define DDRSS3_PHY_420_DATA 0x00000000 -#define DDRSS3_PHY_421_DATA 0x00000000 -#define DDRSS3_PHY_422_DATA 0x00000000 -#define DDRSS3_PHY_423_DATA 0x00000000 -#define DDRSS3_PHY_424_DATA 0x00000000 -#define DDRSS3_PHY_425_DATA 0x00000000 -#define DDRSS3_PHY_426_DATA 0x00000000 -#define DDRSS3_PHY_427_DATA 0x00000000 -#define DDRSS3_PHY_428_DATA 0x00000000 -#define DDRSS3_PHY_429_DATA 0x00000000 -#define DDRSS3_PHY_430_DATA 0x00000000 -#define DDRSS3_PHY_431_DATA 0x00000000 -#define DDRSS3_PHY_432_DATA 0x00000000 -#define DDRSS3_PHY_433_DATA 0x00000000 -#define DDRSS3_PHY_434_DATA 0x00000000 -#define DDRSS3_PHY_435_DATA 0x00000000 -#define DDRSS3_PHY_436_DATA 0x00000000 -#define DDRSS3_PHY_437_DATA 0x00000000 -#define DDRSS3_PHY_438_DATA 0x00000000 -#define DDRSS3_PHY_439_DATA 0x00000000 -#define DDRSS3_PHY_440_DATA 0x00000000 -#define DDRSS3_PHY_441_DATA 0x00000000 -#define DDRSS3_PHY_442_DATA 0x00000000 -#define DDRSS3_PHY_443_DATA 0x00000000 -#define DDRSS3_PHY_444_DATA 0x00000000 -#define DDRSS3_PHY_445_DATA 0x00000000 -#define DDRSS3_PHY_446_DATA 0x00000000 -#define DDRSS3_PHY_447_DATA 0x00000000 -#define DDRSS3_PHY_448_DATA 0x00000000 -#define DDRSS3_PHY_449_DATA 0x00000000 -#define DDRSS3_PHY_450_DATA 0x00000000 -#define DDRSS3_PHY_451_DATA 0x00000000 -#define DDRSS3_PHY_452_DATA 0x00000000 -#define DDRSS3_PHY_453_DATA 0x00000000 -#define DDRSS3_PHY_454_DATA 0x00000000 -#define DDRSS3_PHY_455_DATA 0x00000000 -#define DDRSS3_PHY_456_DATA 0x00000000 -#define DDRSS3_PHY_457_DATA 0x00000000 -#define DDRSS3_PHY_458_DATA 0x00000000 -#define DDRSS3_PHY_459_DATA 0x00000000 -#define DDRSS3_PHY_460_DATA 0x00000000 -#define DDRSS3_PHY_461_DATA 0x00000000 -#define DDRSS3_PHY_462_DATA 0x00000000 -#define DDRSS3_PHY_463_DATA 0x00000000 -#define DDRSS3_PHY_464_DATA 0x00000000 -#define DDRSS3_PHY_465_DATA 0x00000000 -#define DDRSS3_PHY_466_DATA 0x00000000 -#define DDRSS3_PHY_467_DATA 0x00000000 -#define DDRSS3_PHY_468_DATA 0x00000000 -#define DDRSS3_PHY_469_DATA 0x00000000 -#define DDRSS3_PHY_470_DATA 0x00000000 -#define DDRSS3_PHY_471_DATA 0x00000000 -#define DDRSS3_PHY_472_DATA 0x00000000 -#define DDRSS3_PHY_473_DATA 0x00000000 -#define DDRSS3_PHY_474_DATA 0x00000000 -#define DDRSS3_PHY_475_DATA 0x00000000 -#define DDRSS3_PHY_476_DATA 0x00000000 -#define DDRSS3_PHY_477_DATA 0x00000000 -#define DDRSS3_PHY_478_DATA 0x00000000 -#define DDRSS3_PHY_479_DATA 0x00000000 -#define DDRSS3_PHY_480_DATA 0x00000000 -#define DDRSS3_PHY_481_DATA 0x00000000 -#define DDRSS3_PHY_482_DATA 0x00000000 -#define DDRSS3_PHY_483_DATA 0x00000000 -#define DDRSS3_PHY_484_DATA 0x00000000 -#define DDRSS3_PHY_485_DATA 0x00000000 -#define DDRSS3_PHY_486_DATA 0x00000000 -#define DDRSS3_PHY_487_DATA 0x00000000 -#define DDRSS3_PHY_488_DATA 0x00000000 -#define DDRSS3_PHY_489_DATA 0x00000000 -#define DDRSS3_PHY_490_DATA 0x00000000 -#define DDRSS3_PHY_491_DATA 0x00000000 -#define DDRSS3_PHY_492_DATA 0x00000000 -#define DDRSS3_PHY_493_DATA 0x00000000 -#define DDRSS3_PHY_494_DATA 0x00000000 -#define DDRSS3_PHY_495_DATA 0x00000000 -#define DDRSS3_PHY_496_DATA 0x00000000 -#define DDRSS3_PHY_497_DATA 0x00000000 -#define DDRSS3_PHY_498_DATA 0x00000000 -#define DDRSS3_PHY_499_DATA 0x00000000 -#define DDRSS3_PHY_500_DATA 0x00000000 -#define DDRSS3_PHY_501_DATA 0x00000000 -#define DDRSS3_PHY_502_DATA 0x00000000 -#define DDRSS3_PHY_503_DATA 0x00000000 -#define DDRSS3_PHY_504_DATA 0x00000000 -#define DDRSS3_PHY_505_DATA 0x00000000 -#define DDRSS3_PHY_506_DATA 0x00000000 -#define DDRSS3_PHY_507_DATA 0x00000000 -#define DDRSS3_PHY_508_DATA 0x00000000 -#define DDRSS3_PHY_509_DATA 0x00000000 -#define DDRSS3_PHY_510_DATA 0x00000000 -#define DDRSS3_PHY_511_DATA 0x00000000 -#define DDRSS3_PHY_512_DATA 0x000004F0 -#define DDRSS3_PHY_513_DATA 0x00000000 -#define DDRSS3_PHY_514_DATA 0x00030200 -#define DDRSS3_PHY_515_DATA 0x00000000 -#define DDRSS3_PHY_516_DATA 0x00000000 -#define DDRSS3_PHY_517_DATA 0x01030000 -#define DDRSS3_PHY_518_DATA 0x00010000 -#define DDRSS3_PHY_519_DATA 0x01030004 -#define DDRSS3_PHY_520_DATA 0x01000000 -#define DDRSS3_PHY_521_DATA 0x00000000 -#define DDRSS3_PHY_522_DATA 0x00000000 -#define DDRSS3_PHY_523_DATA 0x01000001 -#define DDRSS3_PHY_524_DATA 0x00000100 -#define DDRSS3_PHY_525_DATA 0x000800C0 -#define DDRSS3_PHY_526_DATA 0x060100CC -#define DDRSS3_PHY_527_DATA 0x00030066 -#define DDRSS3_PHY_528_DATA 0x00000000 -#define DDRSS3_PHY_529_DATA 0x00000301 -#define DDRSS3_PHY_530_DATA 0x0000AAAA -#define DDRSS3_PHY_531_DATA 0x00005555 -#define DDRSS3_PHY_532_DATA 0x0000B5B5 -#define DDRSS3_PHY_533_DATA 0x00004A4A -#define DDRSS3_PHY_534_DATA 0x00005656 -#define DDRSS3_PHY_535_DATA 0x0000A9A9 -#define DDRSS3_PHY_536_DATA 0x0000A9A9 -#define DDRSS3_PHY_537_DATA 0x0000B5B5 -#define DDRSS3_PHY_538_DATA 0x00000000 -#define DDRSS3_PHY_539_DATA 0x00000000 -#define DDRSS3_PHY_540_DATA 0x2A000000 -#define DDRSS3_PHY_541_DATA 0x00000808 -#define DDRSS3_PHY_542_DATA 0x0F000000 -#define DDRSS3_PHY_543_DATA 0x00000F0F -#define DDRSS3_PHY_544_DATA 0x10400000 -#define DDRSS3_PHY_545_DATA 0x0C002006 -#define DDRSS3_PHY_546_DATA 0x00000000 -#define DDRSS3_PHY_547_DATA 0x00000000 -#define DDRSS3_PHY_548_DATA 0x55555555 -#define DDRSS3_PHY_549_DATA 0xAAAAAAAA -#define DDRSS3_PHY_550_DATA 0x55555555 -#define DDRSS3_PHY_551_DATA 0xAAAAAAAA -#define DDRSS3_PHY_552_DATA 0x00005555 -#define DDRSS3_PHY_553_DATA 0x01000100 -#define DDRSS3_PHY_554_DATA 0x00800180 -#define DDRSS3_PHY_555_DATA 0x00000001 -#define DDRSS3_PHY_556_DATA 0x00000000 -#define DDRSS3_PHY_557_DATA 0x00000000 -#define DDRSS3_PHY_558_DATA 0x00000000 -#define DDRSS3_PHY_559_DATA 0x00000000 -#define DDRSS3_PHY_560_DATA 0x00000000 -#define DDRSS3_PHY_561_DATA 0x00000000 -#define DDRSS3_PHY_562_DATA 0x00000000 -#define DDRSS3_PHY_563_DATA 0x00000000 -#define DDRSS3_PHY_564_DATA 0x00000000 -#define DDRSS3_PHY_565_DATA 0x00000000 -#define DDRSS3_PHY_566_DATA 0x00000000 -#define DDRSS3_PHY_567_DATA 0x00000000 -#define DDRSS3_PHY_568_DATA 0x00000000 -#define DDRSS3_PHY_569_DATA 0x00000000 -#define DDRSS3_PHY_570_DATA 0x00000000 -#define DDRSS3_PHY_571_DATA 0x00000000 -#define DDRSS3_PHY_572_DATA 0x00000000 -#define DDRSS3_PHY_573_DATA 0x00000000 -#define DDRSS3_PHY_574_DATA 0x00000000 -#define DDRSS3_PHY_575_DATA 0x00000000 -#define DDRSS3_PHY_576_DATA 0x00000000 -#define DDRSS3_PHY_577_DATA 0x00000000 -#define DDRSS3_PHY_578_DATA 0x00000104 -#define DDRSS3_PHY_579_DATA 0x00000120 -#define DDRSS3_PHY_580_DATA 0x00000000 -#define DDRSS3_PHY_581_DATA 0x00000000 -#define DDRSS3_PHY_582_DATA 0x00000000 -#define DDRSS3_PHY_583_DATA 0x00000000 -#define DDRSS3_PHY_584_DATA 0x00000000 -#define DDRSS3_PHY_585_DATA 0x00000000 -#define DDRSS3_PHY_586_DATA 0x00000000 -#define DDRSS3_PHY_587_DATA 0x00000001 -#define DDRSS3_PHY_588_DATA 0x07FF0000 -#define DDRSS3_PHY_589_DATA 0x0080081F -#define DDRSS3_PHY_590_DATA 0x00081020 -#define DDRSS3_PHY_591_DATA 0x04010000 -#define DDRSS3_PHY_592_DATA 0x00000000 -#define DDRSS3_PHY_593_DATA 0x00000000 -#define DDRSS3_PHY_594_DATA 0x00000000 -#define DDRSS3_PHY_595_DATA 0x00000100 -#define DDRSS3_PHY_596_DATA 0x01CC0C01 -#define DDRSS3_PHY_597_DATA 0x1003CC0C -#define DDRSS3_PHY_598_DATA 0x20000140 -#define DDRSS3_PHY_599_DATA 0x07FF0200 -#define DDRSS3_PHY_600_DATA 0x0000DD01 -#define DDRSS3_PHY_601_DATA 0x10100303 -#define DDRSS3_PHY_602_DATA 0x10101010 -#define DDRSS3_PHY_603_DATA 0x10101010 -#define DDRSS3_PHY_604_DATA 0x00021010 -#define DDRSS3_PHY_605_DATA 0x00100010 -#define DDRSS3_PHY_606_DATA 0x00100010 -#define DDRSS3_PHY_607_DATA 0x00100010 -#define DDRSS3_PHY_608_DATA 0x00100010 -#define DDRSS3_PHY_609_DATA 0x00050010 -#define DDRSS3_PHY_610_DATA 0x51517041 -#define DDRSS3_PHY_611_DATA 0x31C06001 -#define DDRSS3_PHY_612_DATA 0x07AB0340 -#define DDRSS3_PHY_613_DATA 0x00C0C001 -#define DDRSS3_PHY_614_DATA 0x0E0D0001 -#define DDRSS3_PHY_615_DATA 0x10001000 -#define DDRSS3_PHY_616_DATA 0x0C083E42 -#define DDRSS3_PHY_617_DATA 0x0F0C3701 -#define DDRSS3_PHY_618_DATA 0x01000140 -#define DDRSS3_PHY_619_DATA 0x0C000420 -#define DDRSS3_PHY_620_DATA 0x00000198 -#define DDRSS3_PHY_621_DATA 0x0A0000D0 -#define DDRSS3_PHY_622_DATA 0x00030200 -#define DDRSS3_PHY_623_DATA 0x02800000 -#define DDRSS3_PHY_624_DATA 0x80800000 -#define DDRSS3_PHY_625_DATA 0x000E2010 -#define DDRSS3_PHY_626_DATA 0x76543210 -#define DDRSS3_PHY_627_DATA 0x00000008 -#define DDRSS3_PHY_628_DATA 0x02800280 -#define DDRSS3_PHY_629_DATA 0x02800280 -#define DDRSS3_PHY_630_DATA 0x02800280 -#define DDRSS3_PHY_631_DATA 0x02800280 -#define DDRSS3_PHY_632_DATA 0x00000280 -#define DDRSS3_PHY_633_DATA 0x0000A000 -#define DDRSS3_PHY_634_DATA 0x00A000A0 -#define DDRSS3_PHY_635_DATA 0x00A000A0 -#define DDRSS3_PHY_636_DATA 0x00A000A0 -#define DDRSS3_PHY_637_DATA 0x00A000A0 -#define DDRSS3_PHY_638_DATA 0x00A000A0 -#define DDRSS3_PHY_639_DATA 0x00A000A0 -#define DDRSS3_PHY_640_DATA 0x00A000A0 -#define DDRSS3_PHY_641_DATA 0x00A000A0 -#define DDRSS3_PHY_642_DATA 0x01C200A0 -#define DDRSS3_PHY_643_DATA 0x01A00005 -#define DDRSS3_PHY_644_DATA 0x00000000 -#define DDRSS3_PHY_645_DATA 0x00000000 -#define DDRSS3_PHY_646_DATA 0x00080200 -#define DDRSS3_PHY_647_DATA 0x00000000 -#define DDRSS3_PHY_648_DATA 0x20202000 -#define DDRSS3_PHY_649_DATA 0x20202020 -#define DDRSS3_PHY_650_DATA 0xF0F02020 -#define DDRSS3_PHY_651_DATA 0x00000000 -#define DDRSS3_PHY_652_DATA 0x00000000 -#define DDRSS3_PHY_653_DATA 0x00000000 -#define DDRSS3_PHY_654_DATA 0x00000000 -#define DDRSS3_PHY_655_DATA 0x00000000 -#define DDRSS3_PHY_656_DATA 0x00000000 -#define DDRSS3_PHY_657_DATA 0x00000000 -#define DDRSS3_PHY_658_DATA 0x00000000 -#define DDRSS3_PHY_659_DATA 0x00000000 -#define DDRSS3_PHY_660_DATA 0x00000000 -#define DDRSS3_PHY_661_DATA 0x00000000 -#define DDRSS3_PHY_662_DATA 0x00000000 -#define DDRSS3_PHY_663_DATA 0x00000000 -#define DDRSS3_PHY_664_DATA 0x00000000 -#define DDRSS3_PHY_665_DATA 0x00000000 -#define DDRSS3_PHY_666_DATA 0x00000000 -#define DDRSS3_PHY_667_DATA 0x00000000 -#define DDRSS3_PHY_668_DATA 0x00000000 -#define DDRSS3_PHY_669_DATA 0x00000000 -#define DDRSS3_PHY_670_DATA 0x00000000 -#define DDRSS3_PHY_671_DATA 0x00000000 -#define DDRSS3_PHY_672_DATA 0x00000000 -#define DDRSS3_PHY_673_DATA 0x00000000 -#define DDRSS3_PHY_674_DATA 0x00000000 -#define DDRSS3_PHY_675_DATA 0x00000000 -#define DDRSS3_PHY_676_DATA 0x00000000 -#define DDRSS3_PHY_677_DATA 0x00000000 -#define DDRSS3_PHY_678_DATA 0x00000000 -#define DDRSS3_PHY_679_DATA 0x00000000 -#define DDRSS3_PHY_680_DATA 0x00000000 -#define DDRSS3_PHY_681_DATA 0x00000000 -#define DDRSS3_PHY_682_DATA 0x00000000 -#define DDRSS3_PHY_683_DATA 0x00000000 -#define DDRSS3_PHY_684_DATA 0x00000000 -#define DDRSS3_PHY_685_DATA 0x00000000 -#define DDRSS3_PHY_686_DATA 0x00000000 -#define DDRSS3_PHY_687_DATA 0x00000000 -#define DDRSS3_PHY_688_DATA 0x00000000 -#define DDRSS3_PHY_689_DATA 0x00000000 -#define DDRSS3_PHY_690_DATA 0x00000000 -#define DDRSS3_PHY_691_DATA 0x00000000 -#define DDRSS3_PHY_692_DATA 0x00000000 -#define DDRSS3_PHY_693_DATA 0x00000000 -#define DDRSS3_PHY_694_DATA 0x00000000 -#define DDRSS3_PHY_695_DATA 0x00000000 -#define DDRSS3_PHY_696_DATA 0x00000000 -#define DDRSS3_PHY_697_DATA 0x00000000 -#define DDRSS3_PHY_698_DATA 0x00000000 -#define DDRSS3_PHY_699_DATA 0x00000000 -#define DDRSS3_PHY_700_DATA 0x00000000 -#define DDRSS3_PHY_701_DATA 0x00000000 -#define DDRSS3_PHY_702_DATA 0x00000000 -#define DDRSS3_PHY_703_DATA 0x00000000 -#define DDRSS3_PHY_704_DATA 0x00000000 -#define DDRSS3_PHY_705_DATA 0x00000000 -#define DDRSS3_PHY_706_DATA 0x00000000 -#define DDRSS3_PHY_707_DATA 0x00000000 -#define DDRSS3_PHY_708_DATA 0x00000000 -#define DDRSS3_PHY_709_DATA 0x00000000 -#define DDRSS3_PHY_710_DATA 0x00000000 -#define DDRSS3_PHY_711_DATA 0x00000000 -#define DDRSS3_PHY_712_DATA 0x00000000 -#define DDRSS3_PHY_713_DATA 0x00000000 -#define DDRSS3_PHY_714_DATA 0x00000000 -#define DDRSS3_PHY_715_DATA 0x00000000 -#define DDRSS3_PHY_716_DATA 0x00000000 -#define DDRSS3_PHY_717_DATA 0x00000000 -#define DDRSS3_PHY_718_DATA 0x00000000 -#define DDRSS3_PHY_719_DATA 0x00000000 -#define DDRSS3_PHY_720_DATA 0x00000000 -#define DDRSS3_PHY_721_DATA 0x00000000 -#define DDRSS3_PHY_722_DATA 0x00000000 -#define DDRSS3_PHY_723_DATA 0x00000000 -#define DDRSS3_PHY_724_DATA 0x00000000 -#define DDRSS3_PHY_725_DATA 0x00000000 -#define DDRSS3_PHY_726_DATA 0x00000000 -#define DDRSS3_PHY_727_DATA 0x00000000 -#define DDRSS3_PHY_728_DATA 0x00000000 -#define DDRSS3_PHY_729_DATA 0x00000000 -#define DDRSS3_PHY_730_DATA 0x00000000 -#define DDRSS3_PHY_731_DATA 0x00000000 -#define DDRSS3_PHY_732_DATA 0x00000000 -#define DDRSS3_PHY_733_DATA 0x00000000 -#define DDRSS3_PHY_734_DATA 0x00000000 -#define DDRSS3_PHY_735_DATA 0x00000000 -#define DDRSS3_PHY_736_DATA 0x00000000 -#define DDRSS3_PHY_737_DATA 0x00000000 -#define DDRSS3_PHY_738_DATA 0x00000000 -#define DDRSS3_PHY_739_DATA 0x00000000 -#define DDRSS3_PHY_740_DATA 0x00000000 -#define DDRSS3_PHY_741_DATA 0x00000000 -#define DDRSS3_PHY_742_DATA 0x00000000 -#define DDRSS3_PHY_743_DATA 0x00000000 -#define DDRSS3_PHY_744_DATA 0x00000000 -#define DDRSS3_PHY_745_DATA 0x00000000 -#define DDRSS3_PHY_746_DATA 0x00000000 -#define DDRSS3_PHY_747_DATA 0x00000000 -#define DDRSS3_PHY_748_DATA 0x00000000 -#define DDRSS3_PHY_749_DATA 0x00000000 -#define DDRSS3_PHY_750_DATA 0x00000000 -#define DDRSS3_PHY_751_DATA 0x00000000 -#define DDRSS3_PHY_752_DATA 0x00000000 -#define DDRSS3_PHY_753_DATA 0x00000000 -#define DDRSS3_PHY_754_DATA 0x00000000 -#define DDRSS3_PHY_755_DATA 0x00000000 -#define DDRSS3_PHY_756_DATA 0x00000000 -#define DDRSS3_PHY_757_DATA 0x00000000 -#define DDRSS3_PHY_758_DATA 0x00000000 -#define DDRSS3_PHY_759_DATA 0x00000000 -#define DDRSS3_PHY_760_DATA 0x00000000 -#define DDRSS3_PHY_761_DATA 0x00000000 -#define DDRSS3_PHY_762_DATA 0x00000000 -#define DDRSS3_PHY_763_DATA 0x00000000 -#define DDRSS3_PHY_764_DATA 0x00000000 -#define DDRSS3_PHY_765_DATA 0x00000000 -#define DDRSS3_PHY_766_DATA 0x00000000 -#define DDRSS3_PHY_767_DATA 0x00000000 -#define DDRSS3_PHY_768_DATA 0x000004F0 -#define DDRSS3_PHY_769_DATA 0x00000000 -#define DDRSS3_PHY_770_DATA 0x00030200 -#define DDRSS3_PHY_771_DATA 0x00000000 -#define DDRSS3_PHY_772_DATA 0x00000000 -#define DDRSS3_PHY_773_DATA 0x01030000 -#define DDRSS3_PHY_774_DATA 0x00010000 -#define DDRSS3_PHY_775_DATA 0x01030004 -#define DDRSS3_PHY_776_DATA 0x01000000 -#define DDRSS3_PHY_777_DATA 0x00000000 -#define DDRSS3_PHY_778_DATA 0x00000000 -#define DDRSS3_PHY_779_DATA 0x01000001 -#define DDRSS3_PHY_780_DATA 0x00000100 -#define DDRSS3_PHY_781_DATA 0x000800C0 -#define DDRSS3_PHY_782_DATA 0x060100CC -#define DDRSS3_PHY_783_DATA 0x00030066 -#define DDRSS3_PHY_784_DATA 0x00000000 -#define DDRSS3_PHY_785_DATA 0x00000301 -#define DDRSS3_PHY_786_DATA 0x0000AAAA -#define DDRSS3_PHY_787_DATA 0x00005555 -#define DDRSS3_PHY_788_DATA 0x0000B5B5 -#define DDRSS3_PHY_789_DATA 0x00004A4A -#define DDRSS3_PHY_790_DATA 0x00005656 -#define DDRSS3_PHY_791_DATA 0x0000A9A9 -#define DDRSS3_PHY_792_DATA 0x0000A9A9 -#define DDRSS3_PHY_793_DATA 0x0000B5B5 -#define DDRSS3_PHY_794_DATA 0x00000000 -#define DDRSS3_PHY_795_DATA 0x00000000 -#define DDRSS3_PHY_796_DATA 0x2A000000 -#define DDRSS3_PHY_797_DATA 0x00000808 -#define DDRSS3_PHY_798_DATA 0x0F000000 -#define DDRSS3_PHY_799_DATA 0x00000F0F -#define DDRSS3_PHY_800_DATA 0x10400000 -#define DDRSS3_PHY_801_DATA 0x0C002006 -#define DDRSS3_PHY_802_DATA 0x00000000 -#define DDRSS3_PHY_803_DATA 0x00000000 -#define DDRSS3_PHY_804_DATA 0x55555555 -#define DDRSS3_PHY_805_DATA 0xAAAAAAAA -#define DDRSS3_PHY_806_DATA 0x55555555 -#define DDRSS3_PHY_807_DATA 0xAAAAAAAA -#define DDRSS3_PHY_808_DATA 0x00005555 -#define DDRSS3_PHY_809_DATA 0x01000100 -#define DDRSS3_PHY_810_DATA 0x00800180 -#define DDRSS3_PHY_811_DATA 0x00000000 -#define DDRSS3_PHY_812_DATA 0x00000000 -#define DDRSS3_PHY_813_DATA 0x00000000 -#define DDRSS3_PHY_814_DATA 0x00000000 -#define DDRSS3_PHY_815_DATA 0x00000000 -#define DDRSS3_PHY_816_DATA 0x00000000 -#define DDRSS3_PHY_817_DATA 0x00000000 -#define DDRSS3_PHY_818_DATA 0x00000000 -#define DDRSS3_PHY_819_DATA 0x00000000 -#define DDRSS3_PHY_820_DATA 0x00000000 -#define DDRSS3_PHY_821_DATA 0x00000000 -#define DDRSS3_PHY_822_DATA 0x00000000 -#define DDRSS3_PHY_823_DATA 0x00000000 -#define DDRSS3_PHY_824_DATA 0x00000000 -#define DDRSS3_PHY_825_DATA 0x00000000 -#define DDRSS3_PHY_826_DATA 0x00000000 -#define DDRSS3_PHY_827_DATA 0x00000000 -#define DDRSS3_PHY_828_DATA 0x00000000 -#define DDRSS3_PHY_829_DATA 0x00000000 -#define DDRSS3_PHY_830_DATA 0x00000000 -#define DDRSS3_PHY_831_DATA 0x00000000 -#define DDRSS3_PHY_832_DATA 0x00000000 -#define DDRSS3_PHY_833_DATA 0x00000000 -#define DDRSS3_PHY_834_DATA 0x00000104 -#define DDRSS3_PHY_835_DATA 0x00000120 -#define DDRSS3_PHY_836_DATA 0x00000000 -#define DDRSS3_PHY_837_DATA 0x00000000 -#define DDRSS3_PHY_838_DATA 0x00000000 -#define DDRSS3_PHY_839_DATA 0x00000000 -#define DDRSS3_PHY_840_DATA 0x00000000 -#define DDRSS3_PHY_841_DATA 0x00000000 -#define DDRSS3_PHY_842_DATA 0x00000000 -#define DDRSS3_PHY_843_DATA 0x00000001 -#define DDRSS3_PHY_844_DATA 0x07FF0000 -#define DDRSS3_PHY_845_DATA 0x0080081F -#define DDRSS3_PHY_846_DATA 0x00081020 -#define DDRSS3_PHY_847_DATA 0x04010000 -#define DDRSS3_PHY_848_DATA 0x00000000 -#define DDRSS3_PHY_849_DATA 0x00000000 -#define DDRSS3_PHY_850_DATA 0x00000000 -#define DDRSS3_PHY_851_DATA 0x00000100 -#define DDRSS3_PHY_852_DATA 0x01CC0C01 -#define DDRSS3_PHY_853_DATA 0x1003CC0C -#define DDRSS3_PHY_854_DATA 0x20000140 -#define DDRSS3_PHY_855_DATA 0x07FF0200 -#define DDRSS3_PHY_856_DATA 0x0000DD01 -#define DDRSS3_PHY_857_DATA 0x10100303 -#define DDRSS3_PHY_858_DATA 0x10101010 -#define DDRSS3_PHY_859_DATA 0x10101010 -#define DDRSS3_PHY_860_DATA 0x00021010 -#define DDRSS3_PHY_861_DATA 0x00100010 -#define DDRSS3_PHY_862_DATA 0x00100010 -#define DDRSS3_PHY_863_DATA 0x00100010 -#define DDRSS3_PHY_864_DATA 0x00100010 -#define DDRSS3_PHY_865_DATA 0x00050010 -#define DDRSS3_PHY_866_DATA 0x51517041 -#define DDRSS3_PHY_867_DATA 0x31C06001 -#define DDRSS3_PHY_868_DATA 0x07AB0340 -#define DDRSS3_PHY_869_DATA 0x00C0C001 -#define DDRSS3_PHY_870_DATA 0x0E0D0001 -#define DDRSS3_PHY_871_DATA 0x10001000 -#define DDRSS3_PHY_872_DATA 0x0C083E42 -#define DDRSS3_PHY_873_DATA 0x0F0C3701 -#define DDRSS3_PHY_874_DATA 0x01000140 -#define DDRSS3_PHY_875_DATA 0x0C000420 -#define DDRSS3_PHY_876_DATA 0x00000198 -#define DDRSS3_PHY_877_DATA 0x0A0000D0 -#define DDRSS3_PHY_878_DATA 0x00030200 -#define DDRSS3_PHY_879_DATA 0x02800000 -#define DDRSS3_PHY_880_DATA 0x80800000 -#define DDRSS3_PHY_881_DATA 0x000E2010 -#define DDRSS3_PHY_882_DATA 0x76543210 -#define DDRSS3_PHY_883_DATA 0x00000008 -#define DDRSS3_PHY_884_DATA 0x02800280 -#define DDRSS3_PHY_885_DATA 0x02800280 -#define DDRSS3_PHY_886_DATA 0x02800280 -#define DDRSS3_PHY_887_DATA 0x02800280 -#define DDRSS3_PHY_888_DATA 0x00000280 -#define DDRSS3_PHY_889_DATA 0x0000A000 -#define DDRSS3_PHY_890_DATA 0x00A000A0 -#define DDRSS3_PHY_891_DATA 0x00A000A0 -#define DDRSS3_PHY_892_DATA 0x00A000A0 -#define DDRSS3_PHY_893_DATA 0x00A000A0 -#define DDRSS3_PHY_894_DATA 0x00A000A0 -#define DDRSS3_PHY_895_DATA 0x00A000A0 -#define DDRSS3_PHY_896_DATA 0x00A000A0 -#define DDRSS3_PHY_897_DATA 0x00A000A0 -#define DDRSS3_PHY_898_DATA 0x01C200A0 -#define DDRSS3_PHY_899_DATA 0x01A00005 -#define DDRSS3_PHY_900_DATA 0x00000000 -#define DDRSS3_PHY_901_DATA 0x00000000 -#define DDRSS3_PHY_902_DATA 0x00080200 -#define DDRSS3_PHY_903_DATA 0x00000000 -#define DDRSS3_PHY_904_DATA 0x20202000 -#define DDRSS3_PHY_905_DATA 0x20202020 -#define DDRSS3_PHY_906_DATA 0xF0F02020 -#define DDRSS3_PHY_907_DATA 0x00000000 -#define DDRSS3_PHY_908_DATA 0x00000000 -#define DDRSS3_PHY_909_DATA 0x00000000 -#define DDRSS3_PHY_910_DATA 0x00000000 -#define DDRSS3_PHY_911_DATA 0x00000000 -#define DDRSS3_PHY_912_DATA 0x00000000 -#define DDRSS3_PHY_913_DATA 0x00000000 -#define DDRSS3_PHY_914_DATA 0x00000000 -#define DDRSS3_PHY_915_DATA 0x00000000 -#define DDRSS3_PHY_916_DATA 0x00000000 -#define DDRSS3_PHY_917_DATA 0x00000000 -#define DDRSS3_PHY_918_DATA 0x00000000 -#define DDRSS3_PHY_919_DATA 0x00000000 -#define DDRSS3_PHY_920_DATA 0x00000000 -#define DDRSS3_PHY_921_DATA 0x00000000 -#define DDRSS3_PHY_922_DATA 0x00000000 -#define DDRSS3_PHY_923_DATA 0x00000000 -#define DDRSS3_PHY_924_DATA 0x00000000 -#define DDRSS3_PHY_925_DATA 0x00000000 -#define DDRSS3_PHY_926_DATA 0x00000000 -#define DDRSS3_PHY_927_DATA 0x00000000 -#define DDRSS3_PHY_928_DATA 0x00000000 -#define DDRSS3_PHY_929_DATA 0x00000000 -#define DDRSS3_PHY_930_DATA 0x00000000 -#define DDRSS3_PHY_931_DATA 0x00000000 -#define DDRSS3_PHY_932_DATA 0x00000000 -#define DDRSS3_PHY_933_DATA 0x00000000 -#define DDRSS3_PHY_934_DATA 0x00000000 -#define DDRSS3_PHY_935_DATA 0x00000000 -#define DDRSS3_PHY_936_DATA 0x00000000 -#define DDRSS3_PHY_937_DATA 0x00000000 -#define DDRSS3_PHY_938_DATA 0x00000000 -#define DDRSS3_PHY_939_DATA 0x00000000 -#define DDRSS3_PHY_940_DATA 0x00000000 -#define DDRSS3_PHY_941_DATA 0x00000000 -#define DDRSS3_PHY_942_DATA 0x00000000 -#define DDRSS3_PHY_943_DATA 0x00000000 -#define DDRSS3_PHY_944_DATA 0x00000000 -#define DDRSS3_PHY_945_DATA 0x00000000 -#define DDRSS3_PHY_946_DATA 0x00000000 -#define DDRSS3_PHY_947_DATA 0x00000000 -#define DDRSS3_PHY_948_DATA 0x00000000 -#define DDRSS3_PHY_949_DATA 0x00000000 -#define DDRSS3_PHY_950_DATA 0x00000000 -#define DDRSS3_PHY_951_DATA 0x00000000 -#define DDRSS3_PHY_952_DATA 0x00000000 -#define DDRSS3_PHY_953_DATA 0x00000000 -#define DDRSS3_PHY_954_DATA 0x00000000 -#define DDRSS3_PHY_955_DATA 0x00000000 -#define DDRSS3_PHY_956_DATA 0x00000000 -#define DDRSS3_PHY_957_DATA 0x00000000 -#define DDRSS3_PHY_958_DATA 0x00000000 -#define DDRSS3_PHY_959_DATA 0x00000000 -#define DDRSS3_PHY_960_DATA 0x00000000 -#define DDRSS3_PHY_961_DATA 0x00000000 -#define DDRSS3_PHY_962_DATA 0x00000000 -#define DDRSS3_PHY_963_DATA 0x00000000 -#define DDRSS3_PHY_964_DATA 0x00000000 -#define DDRSS3_PHY_965_DATA 0x00000000 -#define DDRSS3_PHY_966_DATA 0x00000000 -#define DDRSS3_PHY_967_DATA 0x00000000 -#define DDRSS3_PHY_968_DATA 0x00000000 -#define DDRSS3_PHY_969_DATA 0x00000000 -#define DDRSS3_PHY_970_DATA 0x00000000 -#define DDRSS3_PHY_971_DATA 0x00000000 -#define DDRSS3_PHY_972_DATA 0x00000000 -#define DDRSS3_PHY_973_DATA 0x00000000 -#define DDRSS3_PHY_974_DATA 0x00000000 -#define DDRSS3_PHY_975_DATA 0x00000000 -#define DDRSS3_PHY_976_DATA 0x00000000 -#define DDRSS3_PHY_977_DATA 0x00000000 -#define DDRSS3_PHY_978_DATA 0x00000000 -#define DDRSS3_PHY_979_DATA 0x00000000 -#define DDRSS3_PHY_980_DATA 0x00000000 -#define DDRSS3_PHY_981_DATA 0x00000000 -#define DDRSS3_PHY_982_DATA 0x00000000 -#define DDRSS3_PHY_983_DATA 0x00000000 -#define DDRSS3_PHY_984_DATA 0x00000000 -#define DDRSS3_PHY_985_DATA 0x00000000 -#define DDRSS3_PHY_986_DATA 0x00000000 -#define DDRSS3_PHY_987_DATA 0x00000000 -#define DDRSS3_PHY_988_DATA 0x00000000 -#define DDRSS3_PHY_989_DATA 0x00000000 -#define DDRSS3_PHY_990_DATA 0x00000000 -#define DDRSS3_PHY_991_DATA 0x00000000 -#define DDRSS3_PHY_992_DATA 0x00000000 -#define DDRSS3_PHY_993_DATA 0x00000000 -#define DDRSS3_PHY_994_DATA 0x00000000 -#define DDRSS3_PHY_995_DATA 0x00000000 -#define DDRSS3_PHY_996_DATA 0x00000000 -#define DDRSS3_PHY_997_DATA 0x00000000 -#define DDRSS3_PHY_998_DATA 0x00000000 -#define DDRSS3_PHY_999_DATA 0x00000000 -#define DDRSS3_PHY_1000_DATA 0x00000000 -#define DDRSS3_PHY_1001_DATA 0x00000000 -#define DDRSS3_PHY_1002_DATA 0x00000000 -#define DDRSS3_PHY_1003_DATA 0x00000000 -#define DDRSS3_PHY_1004_DATA 0x00000000 -#define DDRSS3_PHY_1005_DATA 0x00000000 -#define DDRSS3_PHY_1006_DATA 0x00000000 -#define DDRSS3_PHY_1007_DATA 0x00000000 -#define DDRSS3_PHY_1008_DATA 0x00000000 -#define DDRSS3_PHY_1009_DATA 0x00000000 -#define DDRSS3_PHY_1010_DATA 0x00000000 -#define DDRSS3_PHY_1011_DATA 0x00000000 -#define DDRSS3_PHY_1012_DATA 0x00000000 -#define DDRSS3_PHY_1013_DATA 0x00000000 -#define DDRSS3_PHY_1014_DATA 0x00000000 -#define DDRSS3_PHY_1015_DATA 0x00000000 -#define DDRSS3_PHY_1016_DATA 0x00000000 -#define DDRSS3_PHY_1017_DATA 0x00000000 -#define DDRSS3_PHY_1018_DATA 0x00000000 -#define DDRSS3_PHY_1019_DATA 0x00000000 -#define DDRSS3_PHY_1020_DATA 0x00000000 -#define DDRSS3_PHY_1021_DATA 0x00000000 -#define DDRSS3_PHY_1022_DATA 0x00000000 -#define DDRSS3_PHY_1023_DATA 0x00000000 -#define DDRSS3_PHY_1024_DATA 0x00000000 -#define DDRSS3_PHY_1025_DATA 0x00000000 -#define DDRSS3_PHY_1026_DATA 0x00000000 -#define DDRSS3_PHY_1027_DATA 0x00000000 -#define DDRSS3_PHY_1028_DATA 0x00000000 -#define DDRSS3_PHY_1029_DATA 0x00000100 -#define DDRSS3_PHY_1030_DATA 0x00000200 -#define DDRSS3_PHY_1031_DATA 0x00000000 -#define DDRSS3_PHY_1032_DATA 0x00000000 -#define DDRSS3_PHY_1033_DATA 0x00000000 -#define DDRSS3_PHY_1034_DATA 0x00000000 -#define DDRSS3_PHY_1035_DATA 0x00400000 -#define DDRSS3_PHY_1036_DATA 0x00000080 -#define DDRSS3_PHY_1037_DATA 0x00DCBA98 -#define DDRSS3_PHY_1038_DATA 0x03000000 -#define DDRSS3_PHY_1039_DATA 0x00200000 -#define DDRSS3_PHY_1040_DATA 0x00000000 -#define DDRSS3_PHY_1041_DATA 0x00000000 -#define DDRSS3_PHY_1042_DATA 0x00000000 -#define DDRSS3_PHY_1043_DATA 0x00000000 -#define DDRSS3_PHY_1044_DATA 0x00000000 -#define DDRSS3_PHY_1045_DATA 0x0000002A -#define DDRSS3_PHY_1046_DATA 0x00000015 -#define DDRSS3_PHY_1047_DATA 0x00000015 -#define DDRSS3_PHY_1048_DATA 0x0000002A -#define DDRSS3_PHY_1049_DATA 0x00000033 -#define DDRSS3_PHY_1050_DATA 0x0000000C -#define DDRSS3_PHY_1051_DATA 0x0000000C -#define DDRSS3_PHY_1052_DATA 0x00000033 -#define DDRSS3_PHY_1053_DATA 0x00543210 -#define DDRSS3_PHY_1054_DATA 0x003F0000 -#define DDRSS3_PHY_1055_DATA 0x000F013F -#define DDRSS3_PHY_1056_DATA 0x20202003 -#define DDRSS3_PHY_1057_DATA 0x00202020 -#define DDRSS3_PHY_1058_DATA 0x20008008 -#define DDRSS3_PHY_1059_DATA 0x00000810 -#define DDRSS3_PHY_1060_DATA 0x00000F00 -#define DDRSS3_PHY_1061_DATA 0x00000000 -#define DDRSS3_PHY_1062_DATA 0x00000000 -#define DDRSS3_PHY_1063_DATA 0x00000000 -#define DDRSS3_PHY_1064_DATA 0x000305CC -#define DDRSS3_PHY_1065_DATA 0x00030000 -#define DDRSS3_PHY_1066_DATA 0x00000300 -#define DDRSS3_PHY_1067_DATA 0x00000300 -#define DDRSS3_PHY_1068_DATA 0x00000300 -#define DDRSS3_PHY_1069_DATA 0x00000300 -#define DDRSS3_PHY_1070_DATA 0x00000300 -#define DDRSS3_PHY_1071_DATA 0x42080010 -#define DDRSS3_PHY_1072_DATA 0x0000803E -#define DDRSS3_PHY_1073_DATA 0x00000001 -#define DDRSS3_PHY_1074_DATA 0x01000102 -#define DDRSS3_PHY_1075_DATA 0x00008000 -#define DDRSS3_PHY_1076_DATA 0x00000000 -#define DDRSS3_PHY_1077_DATA 0x00000000 -#define DDRSS3_PHY_1078_DATA 0x00000000 -#define DDRSS3_PHY_1079_DATA 0x00000000 -#define DDRSS3_PHY_1080_DATA 0x00000000 -#define DDRSS3_PHY_1081_DATA 0x00000000 -#define DDRSS3_PHY_1082_DATA 0x00000000 -#define DDRSS3_PHY_1083_DATA 0x00000000 -#define DDRSS3_PHY_1084_DATA 0x00000000 -#define DDRSS3_PHY_1085_DATA 0x00000000 -#define DDRSS3_PHY_1086_DATA 0x00000000 -#define DDRSS3_PHY_1087_DATA 0x00000000 -#define DDRSS3_PHY_1088_DATA 0x00000000 -#define DDRSS3_PHY_1089_DATA 0x00000000 -#define DDRSS3_PHY_1090_DATA 0x00000000 -#define DDRSS3_PHY_1091_DATA 0x00000000 -#define DDRSS3_PHY_1092_DATA 0x00000000 -#define DDRSS3_PHY_1093_DATA 0x00000000 -#define DDRSS3_PHY_1094_DATA 0x00000000 -#define DDRSS3_PHY_1095_DATA 0x00000000 -#define DDRSS3_PHY_1096_DATA 0x00000000 -#define DDRSS3_PHY_1097_DATA 0x00000000 -#define DDRSS3_PHY_1098_DATA 0x00000000 -#define DDRSS3_PHY_1099_DATA 0x00000000 -#define DDRSS3_PHY_1100_DATA 0x00000000 -#define DDRSS3_PHY_1101_DATA 0x00000000 -#define DDRSS3_PHY_1102_DATA 0x00000000 -#define DDRSS3_PHY_1103_DATA 0x00000000 -#define DDRSS3_PHY_1104_DATA 0x00000000 -#define DDRSS3_PHY_1105_DATA 0x00000000 -#define DDRSS3_PHY_1106_DATA 0x00000000 -#define DDRSS3_PHY_1107_DATA 0x00000000 -#define DDRSS3_PHY_1108_DATA 0x00000000 -#define DDRSS3_PHY_1109_DATA 0x00000000 -#define DDRSS3_PHY_1110_DATA 0x00000000 -#define DDRSS3_PHY_1111_DATA 0x00000000 -#define DDRSS3_PHY_1112_DATA 0x00000000 -#define DDRSS3_PHY_1113_DATA 0x00000000 -#define DDRSS3_PHY_1114_DATA 0x00000000 -#define DDRSS3_PHY_1115_DATA 0x00000000 -#define DDRSS3_PHY_1116_DATA 0x00000000 -#define DDRSS3_PHY_1117_DATA 0x00000000 -#define DDRSS3_PHY_1118_DATA 0x00000000 -#define DDRSS3_PHY_1119_DATA 0x00000000 -#define DDRSS3_PHY_1120_DATA 0x00000000 -#define DDRSS3_PHY_1121_DATA 0x00000000 -#define DDRSS3_PHY_1122_DATA 0x00000000 -#define DDRSS3_PHY_1123_DATA 0x00000000 -#define DDRSS3_PHY_1124_DATA 0x00000000 -#define DDRSS3_PHY_1125_DATA 0x00000000 -#define DDRSS3_PHY_1126_DATA 0x00000000 -#define DDRSS3_PHY_1127_DATA 0x00000000 -#define DDRSS3_PHY_1128_DATA 0x00000000 -#define DDRSS3_PHY_1129_DATA 0x00000000 -#define DDRSS3_PHY_1130_DATA 0x00000000 -#define DDRSS3_PHY_1131_DATA 0x00000000 -#define DDRSS3_PHY_1132_DATA 0x00000000 -#define DDRSS3_PHY_1133_DATA 0x00000000 -#define DDRSS3_PHY_1134_DATA 0x00000000 -#define DDRSS3_PHY_1135_DATA 0x00000000 -#define DDRSS3_PHY_1136_DATA 0x00000000 -#define DDRSS3_PHY_1137_DATA 0x00000000 -#define DDRSS3_PHY_1138_DATA 0x00000000 -#define DDRSS3_PHY_1139_DATA 0x00000000 -#define DDRSS3_PHY_1140_DATA 0x00000000 -#define DDRSS3_PHY_1141_DATA 0x00000000 -#define DDRSS3_PHY_1142_DATA 0x00000000 -#define DDRSS3_PHY_1143_DATA 0x00000000 -#define DDRSS3_PHY_1144_DATA 0x00000000 -#define DDRSS3_PHY_1145_DATA 0x00000000 -#define DDRSS3_PHY_1146_DATA 0x00000000 -#define DDRSS3_PHY_1147_DATA 0x00000000 -#define DDRSS3_PHY_1148_DATA 0x00000000 -#define DDRSS3_PHY_1149_DATA 0x00000000 -#define DDRSS3_PHY_1150_DATA 0x00000000 -#define DDRSS3_PHY_1151_DATA 0x00000000 -#define DDRSS3_PHY_1152_DATA 0x00000000 -#define DDRSS3_PHY_1153_DATA 0x00000000 -#define DDRSS3_PHY_1154_DATA 0x00000000 -#define DDRSS3_PHY_1155_DATA 0x00000000 -#define DDRSS3_PHY_1156_DATA 0x00000000 -#define DDRSS3_PHY_1157_DATA 0x00000000 -#define DDRSS3_PHY_1158_DATA 0x00000000 -#define DDRSS3_PHY_1159_DATA 0x00000000 -#define DDRSS3_PHY_1160_DATA 0x00000000 -#define DDRSS3_PHY_1161_DATA 0x00000000 -#define DDRSS3_PHY_1162_DATA 0x00000000 -#define DDRSS3_PHY_1163_DATA 0x00000000 -#define DDRSS3_PHY_1164_DATA 0x00000000 -#define DDRSS3_PHY_1165_DATA 0x00000000 -#define DDRSS3_PHY_1166_DATA 0x00000000 -#define DDRSS3_PHY_1167_DATA 0x00000000 -#define DDRSS3_PHY_1168_DATA 0x00000000 -#define DDRSS3_PHY_1169_DATA 0x00000000 -#define DDRSS3_PHY_1170_DATA 0x00000000 -#define DDRSS3_PHY_1171_DATA 0x00000000 -#define DDRSS3_PHY_1172_DATA 0x00000000 -#define DDRSS3_PHY_1173_DATA 0x00000000 -#define DDRSS3_PHY_1174_DATA 0x00000000 -#define DDRSS3_PHY_1175_DATA 0x00000000 -#define DDRSS3_PHY_1176_DATA 0x00000000 -#define DDRSS3_PHY_1177_DATA 0x00000000 -#define DDRSS3_PHY_1178_DATA 0x00000000 -#define DDRSS3_PHY_1179_DATA 0x00000000 -#define DDRSS3_PHY_1180_DATA 0x00000000 -#define DDRSS3_PHY_1181_DATA 0x00000000 -#define DDRSS3_PHY_1182_DATA 0x00000000 -#define DDRSS3_PHY_1183_DATA 0x00000000 -#define DDRSS3_PHY_1184_DATA 0x00000000 -#define DDRSS3_PHY_1185_DATA 0x00000000 -#define DDRSS3_PHY_1186_DATA 0x00000000 -#define DDRSS3_PHY_1187_DATA 0x00000000 -#define DDRSS3_PHY_1188_DATA 0x00000000 -#define DDRSS3_PHY_1189_DATA 0x00000000 -#define DDRSS3_PHY_1190_DATA 0x00000000 -#define DDRSS3_PHY_1191_DATA 0x00000000 -#define DDRSS3_PHY_1192_DATA 0x00000000 -#define DDRSS3_PHY_1193_DATA 0x00000000 -#define DDRSS3_PHY_1194_DATA 0x00000000 -#define DDRSS3_PHY_1195_DATA 0x00000000 -#define DDRSS3_PHY_1196_DATA 0x00000000 -#define DDRSS3_PHY_1197_DATA 0x00000000 -#define DDRSS3_PHY_1198_DATA 0x00000000 -#define DDRSS3_PHY_1199_DATA 0x00000000 -#define DDRSS3_PHY_1200_DATA 0x00000000 -#define DDRSS3_PHY_1201_DATA 0x00000000 -#define DDRSS3_PHY_1202_DATA 0x00000000 -#define DDRSS3_PHY_1203_DATA 0x00000000 -#define DDRSS3_PHY_1204_DATA 0x00000000 -#define DDRSS3_PHY_1205_DATA 0x00000000 -#define DDRSS3_PHY_1206_DATA 0x00000000 -#define DDRSS3_PHY_1207_DATA 0x00000000 -#define DDRSS3_PHY_1208_DATA 0x00000000 -#define DDRSS3_PHY_1209_DATA 0x00000000 -#define DDRSS3_PHY_1210_DATA 0x00000000 -#define DDRSS3_PHY_1211_DATA 0x00000000 -#define DDRSS3_PHY_1212_DATA 0x00000000 -#define DDRSS3_PHY_1213_DATA 0x00000000 -#define DDRSS3_PHY_1214_DATA 0x00000000 -#define DDRSS3_PHY_1215_DATA 0x00000000 -#define DDRSS3_PHY_1216_DATA 0x00000000 -#define DDRSS3_PHY_1217_DATA 0x00000000 -#define DDRSS3_PHY_1218_DATA 0x00000000 -#define DDRSS3_PHY_1219_DATA 0x00000000 -#define DDRSS3_PHY_1220_DATA 0x00000000 -#define DDRSS3_PHY_1221_DATA 0x00000000 -#define DDRSS3_PHY_1222_DATA 0x00000000 -#define DDRSS3_PHY_1223_DATA 0x00000000 -#define DDRSS3_PHY_1224_DATA 0x00000000 -#define DDRSS3_PHY_1225_DATA 0x00000000 -#define DDRSS3_PHY_1226_DATA 0x00000000 -#define DDRSS3_PHY_1227_DATA 0x00000000 -#define DDRSS3_PHY_1228_DATA 0x00000000 -#define DDRSS3_PHY_1229_DATA 0x00000000 -#define DDRSS3_PHY_1230_DATA 0x00000000 -#define DDRSS3_PHY_1231_DATA 0x00000000 -#define DDRSS3_PHY_1232_DATA 0x00000000 -#define DDRSS3_PHY_1233_DATA 0x00000000 -#define DDRSS3_PHY_1234_DATA 0x00000000 -#define DDRSS3_PHY_1235_DATA 0x00000000 -#define DDRSS3_PHY_1236_DATA 0x00000000 -#define DDRSS3_PHY_1237_DATA 0x00000000 -#define DDRSS3_PHY_1238_DATA 0x00000000 -#define DDRSS3_PHY_1239_DATA 0x00000000 -#define DDRSS3_PHY_1240_DATA 0x00000000 -#define DDRSS3_PHY_1241_DATA 0x00000000 -#define DDRSS3_PHY_1242_DATA 0x00000000 -#define DDRSS3_PHY_1243_DATA 0x00000000 -#define DDRSS3_PHY_1244_DATA 0x00000000 -#define DDRSS3_PHY_1245_DATA 0x00000000 -#define DDRSS3_PHY_1246_DATA 0x00000000 -#define DDRSS3_PHY_1247_DATA 0x00000000 -#define DDRSS3_PHY_1248_DATA 0x00000000 -#define DDRSS3_PHY_1249_DATA 0x00000000 -#define DDRSS3_PHY_1250_DATA 0x00000000 -#define DDRSS3_PHY_1251_DATA 0x00000000 -#define DDRSS3_PHY_1252_DATA 0x00000000 -#define DDRSS3_PHY_1253_DATA 0x00000000 -#define DDRSS3_PHY_1254_DATA 0x00000000 -#define DDRSS3_PHY_1255_DATA 0x00000000 -#define DDRSS3_PHY_1256_DATA 0x00000000 -#define DDRSS3_PHY_1257_DATA 0x00000000 -#define DDRSS3_PHY_1258_DATA 0x00000000 -#define DDRSS3_PHY_1259_DATA 0x00000000 -#define DDRSS3_PHY_1260_DATA 0x00000000 -#define DDRSS3_PHY_1261_DATA 0x00000000 -#define DDRSS3_PHY_1262_DATA 0x00000000 -#define DDRSS3_PHY_1263_DATA 0x00000000 -#define DDRSS3_PHY_1264_DATA 0x00000000 -#define DDRSS3_PHY_1265_DATA 0x00000000 -#define DDRSS3_PHY_1266_DATA 0x00000000 -#define DDRSS3_PHY_1267_DATA 0x00000000 -#define DDRSS3_PHY_1268_DATA 0x00000000 -#define DDRSS3_PHY_1269_DATA 0x00000000 -#define DDRSS3_PHY_1270_DATA 0x00000000 -#define DDRSS3_PHY_1271_DATA 0x00000000 -#define DDRSS3_PHY_1272_DATA 0x00000000 -#define DDRSS3_PHY_1273_DATA 0x00000000 -#define DDRSS3_PHY_1274_DATA 0x00000000 -#define DDRSS3_PHY_1275_DATA 0x00000000 -#define DDRSS3_PHY_1276_DATA 0x00000000 -#define DDRSS3_PHY_1277_DATA 0x00000000 -#define DDRSS3_PHY_1278_DATA 0x00000000 -#define DDRSS3_PHY_1279_DATA 0x00000000 -#define DDRSS3_PHY_1280_DATA 0x00000000 -#define DDRSS3_PHY_1281_DATA 0x00010100 -#define DDRSS3_PHY_1282_DATA 0x00000000 -#define DDRSS3_PHY_1283_DATA 0x00000000 -#define DDRSS3_PHY_1284_DATA 0x00050000 -#define DDRSS3_PHY_1285_DATA 0x04000000 -#define DDRSS3_PHY_1286_DATA 0x00000055 -#define DDRSS3_PHY_1287_DATA 0x00000000 -#define DDRSS3_PHY_1288_DATA 0x00000000 -#define DDRSS3_PHY_1289_DATA 0x00000000 -#define DDRSS3_PHY_1290_DATA 0x00000000 -#define DDRSS3_PHY_1291_DATA 0x00002001 -#define DDRSS3_PHY_1292_DATA 0x0000400F -#define DDRSS3_PHY_1293_DATA 0x50020028 -#define DDRSS3_PHY_1294_DATA 0x01010000 -#define DDRSS3_PHY_1295_DATA 0x80080001 -#define DDRSS3_PHY_1296_DATA 0x10200000 -#define DDRSS3_PHY_1297_DATA 0x00000008 -#define DDRSS3_PHY_1298_DATA 0x00000000 -#define DDRSS3_PHY_1299_DATA 0x01090E00 -#define DDRSS3_PHY_1300_DATA 0x00040101 -#define DDRSS3_PHY_1301_DATA 0x0000010F -#define DDRSS3_PHY_1302_DATA 0x00000000 -#define DDRSS3_PHY_1303_DATA 0x0000FFFF -#define DDRSS3_PHY_1304_DATA 0x00000000 -#define DDRSS3_PHY_1305_DATA 0x01010000 -#define DDRSS3_PHY_1306_DATA 0x01080402 -#define DDRSS3_PHY_1307_DATA 0x01200F02 -#define DDRSS3_PHY_1308_DATA 0x00194280 -#define DDRSS3_PHY_1309_DATA 0x00000004 -#define DDRSS3_PHY_1310_DATA 0x00042000 -#define DDRSS3_PHY_1311_DATA 0x00000000 -#define DDRSS3_PHY_1312_DATA 0x00000000 -#define DDRSS3_PHY_1313_DATA 0x00000000 -#define DDRSS3_PHY_1314_DATA 0x00000000 -#define DDRSS3_PHY_1315_DATA 0x00000000 -#define DDRSS3_PHY_1316_DATA 0x00000000 -#define DDRSS3_PHY_1317_DATA 0x01000000 -#define DDRSS3_PHY_1318_DATA 0x00000705 -#define DDRSS3_PHY_1319_DATA 0x00000054 -#define DDRSS3_PHY_1320_DATA 0x00030820 -#define DDRSS3_PHY_1321_DATA 0x00010820 -#define DDRSS3_PHY_1322_DATA 0x00010820 -#define DDRSS3_PHY_1323_DATA 0x00010820 -#define DDRSS3_PHY_1324_DATA 0x00010820 -#define DDRSS3_PHY_1325_DATA 0x00010820 -#define DDRSS3_PHY_1326_DATA 0x00010820 -#define DDRSS3_PHY_1327_DATA 0x00010820 -#define DDRSS3_PHY_1328_DATA 0x00010820 -#define DDRSS3_PHY_1329_DATA 0x00000000 -#define DDRSS3_PHY_1330_DATA 0x00000074 -#define DDRSS3_PHY_1331_DATA 0x00000400 -#define DDRSS3_PHY_1332_DATA 0x00000108 -#define DDRSS3_PHY_1333_DATA 0x00000000 -#define DDRSS3_PHY_1334_DATA 0x00000000 -#define DDRSS3_PHY_1335_DATA 0x00000000 -#define DDRSS3_PHY_1336_DATA 0x00000000 -#define DDRSS3_PHY_1337_DATA 0x00000000 -#define DDRSS3_PHY_1338_DATA 0x03000000 -#define DDRSS3_PHY_1339_DATA 0x00000000 -#define DDRSS3_PHY_1340_DATA 0x00000000 -#define DDRSS3_PHY_1341_DATA 0x00000000 -#define DDRSS3_PHY_1342_DATA 0x04102006 -#define DDRSS3_PHY_1343_DATA 0x00041020 -#define DDRSS3_PHY_1344_DATA 0x01C98C98 -#define DDRSS3_PHY_1345_DATA 0x3F400000 -#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F -#define DDRSS3_PHY_1347_DATA 0x0000001F -#define DDRSS3_PHY_1348_DATA 0x00000000 -#define DDRSS3_PHY_1349_DATA 0x00000000 -#define DDRSS3_PHY_1350_DATA 0x00000000 -#define DDRSS3_PHY_1351_DATA 0x00010000 -#define DDRSS3_PHY_1352_DATA 0x00000000 -#define DDRSS3_PHY_1353_DATA 0x00000000 -#define DDRSS3_PHY_1354_DATA 0x00000000 -#define DDRSS3_PHY_1355_DATA 0x00000000 -#define DDRSS3_PHY_1356_DATA 0x76543210 -#define DDRSS3_PHY_1357_DATA 0x00010198 -#define DDRSS3_PHY_1358_DATA 0x00000000 -#define DDRSS3_PHY_1359_DATA 0x00000000 -#define DDRSS3_PHY_1360_DATA 0x00000000 -#define DDRSS3_PHY_1361_DATA 0x00040700 -#define DDRSS3_PHY_1362_DATA 0x00000000 -#define DDRSS3_PHY_1363_DATA 0x00000000 -#define DDRSS3_PHY_1364_DATA 0x00000000 -#define DDRSS3_PHY_1365_DATA 0x00000000 -#define DDRSS3_PHY_1366_DATA 0x00000000 -#define DDRSS3_PHY_1367_DATA 0x00000002 -#define DDRSS3_PHY_1368_DATA 0x00000000 -#define DDRSS3_PHY_1369_DATA 0x00000000 -#define DDRSS3_PHY_1370_DATA 0x00000000 -#define DDRSS3_PHY_1371_DATA 0x00000000 -#define DDRSS3_PHY_1372_DATA 0x00000000 -#define DDRSS3_PHY_1373_DATA 0x00000000 -#define DDRSS3_PHY_1374_DATA 0x00080000 -#define DDRSS3_PHY_1375_DATA 0x000007FF -#define DDRSS3_PHY_1376_DATA 0x00000000 -#define DDRSS3_PHY_1377_DATA 0x00000000 -#define DDRSS3_PHY_1378_DATA 0x00000000 -#define DDRSS3_PHY_1379_DATA 0x00000000 -#define DDRSS3_PHY_1380_DATA 0x00000000 -#define DDRSS3_PHY_1381_DATA 0x00000000 -#define DDRSS3_PHY_1382_DATA 0x000FFFFF -#define DDRSS3_PHY_1383_DATA 0x000FFFFF -#define DDRSS3_PHY_1384_DATA 0x0000FFFF -#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0 -#define DDRSS3_PHY_1386_DATA 0x030FFFFF -#define DDRSS3_PHY_1387_DATA 0x01FFFFFF -#define DDRSS3_PHY_1388_DATA 0x0000FFFF -#define DDRSS3_PHY_1389_DATA 0x00000000 -#define DDRSS3_PHY_1390_DATA 0x00000000 -#define DDRSS3_PHY_1391_DATA 0x00000000 -#define DDRSS3_PHY_1392_DATA 0x00000000 -#define DDRSS3_PHY_1393_DATA 0x0001F7C0 -#define DDRSS3_PHY_1394_DATA 0x00000003 -#define DDRSS3_PHY_1395_DATA 0x00000000 -#define DDRSS3_PHY_1396_DATA 0x00001142 -#define DDRSS3_PHY_1397_DATA 0x010207AB -#define DDRSS3_PHY_1398_DATA 0x01000080 -#define DDRSS3_PHY_1399_DATA 0x03900390 -#define DDRSS3_PHY_1400_DATA 0x03900390 -#define DDRSS3_PHY_1401_DATA 0x00000390 -#define DDRSS3_PHY_1402_DATA 0x00000390 -#define DDRSS3_PHY_1403_DATA 0x00000390 -#define DDRSS3_PHY_1404_DATA 0x00000390 -#define DDRSS3_PHY_1405_DATA 0x00000005 -#define DDRSS3_PHY_1406_DATA 0x01813FCC -#define DDRSS3_PHY_1407_DATA 0x000000CC -#define DDRSS3_PHY_1408_DATA 0x0C000DFF -#define DDRSS3_PHY_1409_DATA 0x30000DFF -#define DDRSS3_PHY_1410_DATA 0x3F0DFF11 -#define DDRSS3_PHY_1411_DATA 0x000100F0 -#define DDRSS3_PHY_1412_DATA 0x780DFFCC -#define DDRSS3_PHY_1413_DATA 0x00007E31 -#define DDRSS3_PHY_1414_DATA 0x000CBF11 -#define DDRSS3_PHY_1415_DATA 0x01990010 -#define DDRSS3_PHY_1416_DATA 0x000CBF11 -#define DDRSS3_PHY_1417_DATA 0x01990010 -#define DDRSS3_PHY_1418_DATA 0x3F0DFF11 -#define DDRSS3_PHY_1419_DATA 0x00EF00F0 -#define DDRSS3_PHY_1420_DATA 0x3F0DFF11 -#define DDRSS3_PHY_1421_DATA 0x01FF00F0 -#define DDRSS3_PHY_1422_DATA 0x20040006 diff --git a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi index 0e16d2f201d..521464e2264 100644 --- a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi +++ b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi @@ -1,11 +1,29 @@ -// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ - * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0 - * This file was generated on 04/12/2023 - */ + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + * This file was generated with the following tool revisions: + * - SysConfig: Revision 1.25.0+4268 + * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0 + * This file was generated on Thu Oct 30 2025 14:55:08 GMT+0530 (India Standard Time) + * + * Multi DDR Configuration (table based on register configuration tool inputs): + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 0 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 1 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 2 | 8 GB | 8 GB | + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~| + * | 3 | 8 GB | 8 GB | + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| +*/ -#define DDRSS_PLL_FHS_CNT 10 +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS1_PLL_FHS_CNT 5 +#define DDRSS2_PLL_FHS_CNT 5 +#define DDRSS3_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_0 27500000 #define DDRSS_PLL_FREQUENCY_1 1066500000 #define DDRSS_PLL_FREQUENCY_2 1066500000 @@ -16,6 +34,17 @@ #define MULTI_DDR_CFG_HYBRID_SELECT 24 #define MULTI_DDR_CFG_EMIFS_ACTIVE 15 +#define DDR0_CTL_NODE_STAT okay +#define DDR1_CTL_NODE_STAT okay +#define DDR2_CTL_NODE_STAT okay +#define DDR3_CTL_NODE_STAT okay + +#define DDR_REG0_SIZE_MSB 0x00000000 +#define DDR_REG0_SIZE_LSB 0x80000000 +#define DDR_REG1_SIZE_MSB 0x00000007 +#define DDR_REG1_SIZE_LSB 0x80000000 + + #define DDRSS0_CTL_00_DATA 0x00000B00 #define DDRSS0_CTL_01_DATA 0x00000000 #define DDRSS0_CTL_02_DATA 0x00000000 @@ -36,7 +65,7 @@ #define DDRSS0_CTL_17_DATA 0x00000005 #define DDRSS0_CTL_18_DATA 0x000010A9 #define DDRSS0_CTL_19_DATA 0x01010000 -#define DDRSS0_CTL_20_DATA 0x02011001 +#define DDRSS0_CTL_20_DATA 0x01011001 #define DDRSS0_CTL_21_DATA 0x02010000 #define DDRSS0_CTL_22_DATA 0x00020100 #define DDRSS0_CTL_23_DATA 0x0000000B @@ -51,7 +80,7 @@ #define DDRSS0_CTL_32_DATA 0x00000000 #define DDRSS0_CTL_33_DATA 0x00000000 #define DDRSS0_CTL_34_DATA 0x040C0000 -#define DDRSS0_CTL_35_DATA 0x12481248 +#define DDRSS0_CTL_35_DATA 0x12501250 #define DDRSS0_CTL_36_DATA 0x00050804 #define DDRSS0_CTL_37_DATA 0x09040008 #define DDRSS0_CTL_38_DATA 0x15000204 @@ -66,27 +95,27 @@ #define DDRSS0_CTL_47_DATA 0x1E161110 #define DDRSS0_CTL_48_DATA 0x1000922C #define DDRSS0_CTL_49_DATA 0x02030410 -#define DDRSS0_CTL_50_DATA 0x2C040500 +#define DDRSS0_CTL_50_DATA 0x2C060500 #define DDRSS0_CTL_51_DATA 0x08292C29 #define DDRSS0_CTL_52_DATA 0x14000E0A #define DDRSS0_CTL_53_DATA 0x04010A0A #define DDRSS0_CTL_54_DATA 0x01010004 -#define DDRSS0_CTL_55_DATA 0x04545408 +#define DDRSS0_CTL_55_DATA 0x0454540A #define DDRSS0_CTL_56_DATA 0x04313104 #define DDRSS0_CTL_57_DATA 0x00003131 #define DDRSS0_CTL_58_DATA 0x00010100 #define DDRSS0_CTL_59_DATA 0x03010000 #define DDRSS0_CTL_60_DATA 0x00001508 -#define DDRSS0_CTL_61_DATA 0x00000063 +#define DDRSS0_CTL_61_DATA 0x00000068 #define DDRSS0_CTL_62_DATA 0x0000032B #define DDRSS0_CTL_63_DATA 0x00001035 #define DDRSS0_CTL_64_DATA 0x0000032B #define DDRSS0_CTL_65_DATA 0x00001035 #define DDRSS0_CTL_66_DATA 0x00000005 #define DDRSS0_CTL_67_DATA 0x00050000 -#define DDRSS0_CTL_68_DATA 0x00CB0012 -#define DDRSS0_CTL_69_DATA 0x00CB0408 -#define DDRSS0_CTL_70_DATA 0x00400408 +#define DDRSS0_CTL_68_DATA 0x00CB0005 +#define DDRSS0_CTL_69_DATA 0x00CB0200 +#define DDRSS0_CTL_70_DATA 0x00400200 #define DDRSS0_CTL_71_DATA 0x00120103 #define DDRSS0_CTL_72_DATA 0x00100005 #define DDRSS0_CTL_73_DATA 0x2F080010 @@ -192,22 +221,22 @@ #define DDRSS0_CTL_173_DATA 0x00000000 #define DDRSS0_CTL_174_DATA 0x00000000 #define DDRSS0_CTL_175_DATA 0x3FF40084 -#define DDRSS0_CTL_176_DATA 0x33003FF4 -#define DDRSS0_CTL_177_DATA 0x00003333 +#define DDRSS0_CTL_176_DATA 0xF3003FF4 +#define DDRSS0_CTL_177_DATA 0x0000F3F3 #define DDRSS0_CTL_178_DATA 0x35000000 #define DDRSS0_CTL_179_DATA 0x27270035 #define DDRSS0_CTL_180_DATA 0x0F0F0000 #define DDRSS0_CTL_181_DATA 0x16000000 #define DDRSS0_CTL_182_DATA 0x00841616 #define DDRSS0_CTL_183_DATA 0x3FF43FF4 -#define DDRSS0_CTL_184_DATA 0x33333300 +#define DDRSS0_CTL_184_DATA 0xF3F3F300 #define DDRSS0_CTL_185_DATA 0x00000000 #define DDRSS0_CTL_186_DATA 0x00353500 #define DDRSS0_CTL_187_DATA 0x00002727 #define DDRSS0_CTL_188_DATA 0x00000F0F #define DDRSS0_CTL_189_DATA 0x16161600 #define DDRSS0_CTL_190_DATA 0x00000020 -#define DDRSS0_CTL_191_DATA 0x00000000 +#define DDRSS0_CTL_191_DATA 0x01000000 #define DDRSS0_CTL_192_DATA 0x00000001 #define DDRSS0_CTL_193_DATA 0x00000000 #define DDRSS0_CTL_194_DATA 0x01000000 @@ -307,14 +336,14 @@ #define DDRSS0_CTL_288_DATA 0x00000000 #define DDRSS0_CTL_289_DATA 0x00000000 #define DDRSS0_CTL_290_DATA 0x03030300 -#define DDRSS0_CTL_291_DATA 0x00000001 +#define DDRSS0_CTL_291_DATA 0x00010101 #define DDRSS0_CTL_292_DATA 0x00000000 #define DDRSS0_CTL_293_DATA 0x00000000 #define DDRSS0_CTL_294_DATA 0x00000000 #define DDRSS0_CTL_295_DATA 0x00000000 #define DDRSS0_CTL_296_DATA 0x00000000 -#define DDRSS0_CTL_297_DATA 0x00000000 -#define DDRSS0_CTL_298_DATA 0x00000000 +#define DDRSS0_CTL_297_DATA 0xFFFFFFFF +#define DDRSS0_CTL_298_DATA 0x00000FFF #define DDRSS0_CTL_299_DATA 0x00000000 #define DDRSS0_CTL_300_DATA 0x00000000 #define DDRSS0_CTL_301_DATA 0x00000000 @@ -335,7 +364,7 @@ #define DDRSS0_CTL_316_DATA 0x01010001 #define DDRSS0_CTL_317_DATA 0x00010101 #define DDRSS0_CTL_318_DATA 0x050A0A03 -#define DDRSS0_CTL_319_DATA 0x10081F1F +#define DDRSS0_CTL_319_DATA 0x10082323 #define DDRSS0_CTL_320_DATA 0x00090310 #define DDRSS0_CTL_321_DATA 0x0B0C030F #define DDRSS0_CTL_322_DATA 0x0B0C0306 @@ -410,7 +439,7 @@ #define DDRSS0_CTL_391_DATA 0x00000200 #define DDRSS0_CTL_392_DATA 0x00000200 #define DDRSS0_CTL_393_DATA 0x00000200 -#define DDRSS0_CTL_394_DATA 0x00000252 +#define DDRSS0_CTL_394_DATA 0x00000270 #define DDRSS0_CTL_395_DATA 0x000007BC #define DDRSS0_CTL_396_DATA 0x00000204 #define DDRSS0_CTL_397_DATA 0x0000206A @@ -420,7 +449,7 @@ #define DDRSS0_CTL_401_DATA 0x00000200 #define DDRSS0_CTL_402_DATA 0x0000613E #define DDRSS0_CTL_403_DATA 0x00014424 -#define DDRSS0_CTL_404_DATA 0x00000E15 +#define DDRSS0_CTL_404_DATA 0x00000E19 #define DDRSS0_CTL_405_DATA 0x0000206A #define DDRSS0_CTL_406_DATA 0x00000200 #define DDRSS0_CTL_407_DATA 0x00000200 @@ -428,7 +457,7 @@ #define DDRSS0_CTL_409_DATA 0x00000200 #define DDRSS0_CTL_410_DATA 0x0000613E #define DDRSS0_CTL_411_DATA 0x00014424 -#define DDRSS0_CTL_412_DATA 0x02020E15 +#define DDRSS0_CTL_412_DATA 0x02020E19 #define DDRSS0_CTL_413_DATA 0x03030202 #define DDRSS0_CTL_414_DATA 0x00000022 #define DDRSS0_CTL_415_DATA 0x00000000 @@ -445,7 +474,7 @@ #define DDRSS0_CTL_426_DATA 0x00000000 #define DDRSS0_CTL_427_DATA 0x02000000 #define DDRSS0_CTL_428_DATA 0x01000404 -#define DDRSS0_CTL_429_DATA 0x0B1E0B1E +#define DDRSS0_CTL_429_DATA 0x0B220B22 #define DDRSS0_CTL_430_DATA 0x00000105 #define DDRSS0_CTL_431_DATA 0x00010101 #define DDRSS0_CTL_432_DATA 0x00010101 @@ -488,8 +517,8 @@ #define DDRSS0_PI_09_DATA 0x00000000 #define DDRSS0_PI_10_DATA 0x00000000 #define DDRSS0_PI_11_DATA 0x00000000 -#define DDRSS0_PI_12_DATA 0x00000007 -#define DDRSS0_PI_13_DATA 0x00010002 +#define DDRSS0_PI_12_DATA 0x00000003 +#define DDRSS0_PI_13_DATA 0x00010001 #define DDRSS0_PI_14_DATA 0x0800000F #define DDRSS0_PI_15_DATA 0x00000103 #define DDRSS0_PI_16_DATA 0x00000005 @@ -537,18 +566,18 @@ #define DDRSS0_PI_58_DATA 0x00000000 #define DDRSS0_PI_59_DATA 0x00000000 #define DDRSS0_PI_60_DATA 0x0A0A140A -#define DDRSS0_PI_61_DATA 0x10020101 +#define DDRSS0_PI_61_DATA 0x10020201 #define DDRSS0_PI_62_DATA 0x00020805 #define DDRSS0_PI_63_DATA 0x01000404 #define DDRSS0_PI_64_DATA 0x00000000 #define DDRSS0_PI_65_DATA 0x00000000 #define DDRSS0_PI_66_DATA 0x00000100 -#define DDRSS0_PI_67_DATA 0x0001010F +#define DDRSS0_PI_67_DATA 0x0002020F #define DDRSS0_PI_68_DATA 0x00340000 #define DDRSS0_PI_69_DATA 0x00000000 #define DDRSS0_PI_70_DATA 0x00000000 #define DDRSS0_PI_71_DATA 0x0000FFFF -#define DDRSS0_PI_72_DATA 0x00000000 +#define DDRSS0_PI_72_DATA 0x01000000 #define DDRSS0_PI_73_DATA 0x00080000 #define DDRSS0_PI_74_DATA 0x02000200 #define DDRSS0_PI_75_DATA 0x01000100 @@ -637,37 +666,37 @@ #define DDRSS0_PI_158_DATA 0x00000000 #define DDRSS0_PI_159_DATA 0x00000401 #define DDRSS0_PI_160_DATA 0x00000000 -#define DDRSS0_PI_161_DATA 0x00010000 -#define DDRSS0_PI_162_DATA 0x00000000 -#define DDRSS0_PI_163_DATA 0x2B2B0200 +#define DDRSS0_PI_161_DATA 0x05010000 +#define DDRSS0_PI_162_DATA 0x00000001 +#define DDRSS0_PI_163_DATA 0x2B2B0201 #define DDRSS0_PI_164_DATA 0x00000034 -#define DDRSS0_PI_165_DATA 0x00000064 -#define DDRSS0_PI_166_DATA 0x00020064 +#define DDRSS0_PI_165_DATA 0x00000068 +#define DDRSS0_PI_166_DATA 0x00020068 #define DDRSS0_PI_167_DATA 0x02000200 -#define DDRSS0_PI_168_DATA 0x48120C04 -#define DDRSS0_PI_169_DATA 0x00154812 -#define DDRSS0_PI_170_DATA 0x00000063 +#define DDRSS0_PI_168_DATA 0x50120C04 +#define DDRSS0_PI_169_DATA 0x00155012 +#define DDRSS0_PI_170_DATA 0x00000068 #define DDRSS0_PI_171_DATA 0x0000032B #define DDRSS0_PI_172_DATA 0x00001035 #define DDRSS0_PI_173_DATA 0x0000032B #define DDRSS0_PI_174_DATA 0x04001035 #define DDRSS0_PI_175_DATA 0x01010404 -#define DDRSS0_PI_176_DATA 0x00001501 +#define DDRSS0_PI_176_DATA 0x00001500 #define DDRSS0_PI_177_DATA 0x00150015 #define DDRSS0_PI_178_DATA 0x01000100 #define DDRSS0_PI_179_DATA 0x00000100 #define DDRSS0_PI_180_DATA 0x00000000 #define DDRSS0_PI_181_DATA 0x01010101 -#define DDRSS0_PI_182_DATA 0x00000101 +#define DDRSS0_PI_182_DATA 0x00000000 #define DDRSS0_PI_183_DATA 0x00000000 #define DDRSS0_PI_184_DATA 0x00000000 -#define DDRSS0_PI_185_DATA 0x15040000 -#define DDRSS0_PI_186_DATA 0x0E0E0215 +#define DDRSS0_PI_185_DATA 0x19040000 +#define DDRSS0_PI_186_DATA 0x0E0E0219 #define DDRSS0_PI_187_DATA 0x00040402 #define DDRSS0_PI_188_DATA 0x000D0035 #define DDRSS0_PI_189_DATA 0x00218049 #define DDRSS0_PI_190_DATA 0x00218049 -#define DDRSS0_PI_191_DATA 0x01010101 +#define DDRSS0_PI_191_DATA 0x01000101 #define DDRSS0_PI_192_DATA 0x0004000E #define DDRSS0_PI_193_DATA 0x00040216 #define DDRSS0_PI_194_DATA 0x01000216 @@ -675,8 +704,8 @@ #define DDRSS0_PI_196_DATA 0x02170100 #define DDRSS0_PI_197_DATA 0x01000217 #define DDRSS0_PI_198_DATA 0x02170217 -#define DDRSS0_PI_199_DATA 0x32103200 -#define DDRSS0_PI_200_DATA 0x01013210 +#define DDRSS0_PI_199_DATA 0x2F1B3200 +#define DDRSS0_PI_200_DATA 0x01012F1B #define DDRSS0_PI_201_DATA 0x0A070601 #define DDRSS0_PI_202_DATA 0x1F130A0D #define DDRSS0_PI_203_DATA 0x1F130A14 @@ -688,13 +717,13 @@ #define DDRSS0_PI_209_DATA 0x00240216 #define DDRSS0_PI_210_DATA 0x00110216 #define DDRSS0_PI_211_DATA 0x32000056 -#define DDRSS0_PI_212_DATA 0x00000301 -#define DDRSS0_PI_213_DATA 0x005B0036 +#define DDRSS0_PI_212_DATA 0x00000101 +#define DDRSS0_PI_213_DATA 0x005F0036 #define DDRSS0_PI_214_DATA 0x03013212 #define DDRSS0_PI_215_DATA 0x00003600 -#define DDRSS0_PI_216_DATA 0x3212005B -#define DDRSS0_PI_217_DATA 0x09000301 -#define DDRSS0_PI_218_DATA 0x04010504 +#define DDRSS0_PI_216_DATA 0x3212005F +#define DDRSS0_PI_217_DATA 0x09000001 +#define DDRSS0_PI_218_DATA 0x06010504 #define DDRSS0_PI_219_DATA 0x04000364 #define DDRSS0_PI_220_DATA 0x0A032001 #define DDRSS0_PI_221_DATA 0x2C31110A @@ -751,29 +780,29 @@ #define DDRSS0_PI_272_DATA 0x00080804 #define DDRSS0_PI_273_DATA 0x00000000 #define DDRSS0_PI_274_DATA 0x00000000 -#define DDRSS0_PI_275_DATA 0x00330084 +#define DDRSS0_PI_275_DATA 0x00F30084 #define DDRSS0_PI_276_DATA 0x00160000 -#define DDRSS0_PI_277_DATA 0x35333FF4 +#define DDRSS0_PI_277_DATA 0x35F33FF4 #define DDRSS0_PI_278_DATA 0x00160F27 -#define DDRSS0_PI_279_DATA 0x35333FF4 +#define DDRSS0_PI_279_DATA 0x35F33FF4 #define DDRSS0_PI_280_DATA 0x00160F27 -#define DDRSS0_PI_281_DATA 0x00330084 +#define DDRSS0_PI_281_DATA 0x00F30084 #define DDRSS0_PI_282_DATA 0x00160000 -#define DDRSS0_PI_283_DATA 0x35333FF4 +#define DDRSS0_PI_283_DATA 0x35F33FF4 #define DDRSS0_PI_284_DATA 0x00160F27 -#define DDRSS0_PI_285_DATA 0x35333FF4 +#define DDRSS0_PI_285_DATA 0x35F33FF4 #define DDRSS0_PI_286_DATA 0x00160F27 -#define DDRSS0_PI_287_DATA 0x00330084 +#define DDRSS0_PI_287_DATA 0x00F30084 #define DDRSS0_PI_288_DATA 0x00160000 -#define DDRSS0_PI_289_DATA 0x35333FF4 +#define DDRSS0_PI_289_DATA 0x35F33FF4 #define DDRSS0_PI_290_DATA 0x00160F27 -#define DDRSS0_PI_291_DATA 0x35333FF4 +#define DDRSS0_PI_291_DATA 0x35F33FF4 #define DDRSS0_PI_292_DATA 0x00160F27 -#define DDRSS0_PI_293_DATA 0x00330084 +#define DDRSS0_PI_293_DATA 0x00F30084 #define DDRSS0_PI_294_DATA 0x00160000 -#define DDRSS0_PI_295_DATA 0x35333FF4 +#define DDRSS0_PI_295_DATA 0x35F33FF4 #define DDRSS0_PI_296_DATA 0x00160F27 -#define DDRSS0_PI_297_DATA 0x35333FF4 +#define DDRSS0_PI_297_DATA 0x35F33FF4 #define DDRSS0_PI_298_DATA 0x00160F27 #define DDRSS0_PI_299_DATA 0x00000000 @@ -789,7 +818,7 @@ #define DDRSS0_PHY_09_DATA 0x00000000 #define DDRSS0_PHY_10_DATA 0x00000000 #define DDRSS0_PHY_11_DATA 0x01000001 -#define DDRSS0_PHY_12_DATA 0x00000100 +#define DDRSS0_PHY_12_DATA 0x00000200 #define DDRSS0_PHY_13_DATA 0x000800C0 #define DDRSS0_PHY_14_DATA 0x060100CC #define DDRSS0_PHY_15_DATA 0x00030066 @@ -808,7 +837,7 @@ #define DDRSS0_PHY_28_DATA 0x2A000000 #define DDRSS0_PHY_29_DATA 0x00000808 #define DDRSS0_PHY_30_DATA 0x0F000000 -#define DDRSS0_PHY_31_DATA 0x00000F0F +#define DDRSS0_PHY_31_DATA 0x00000F08 #define DDRSS0_PHY_32_DATA 0x10400000 #define DDRSS0_PHY_33_DATA 0x0C002006 #define DDRSS0_PHY_34_DATA 0x00000000 @@ -877,9 +906,9 @@ #define DDRSS0_PHY_97_DATA 0x00050010 #define DDRSS0_PHY_98_DATA 0x51517041 #define DDRSS0_PHY_99_DATA 0x31C06001 -#define DDRSS0_PHY_100_DATA 0x07AB0340 +#define DDRSS0_PHY_100_DATA 0x07AB01AB #define DDRSS0_PHY_101_DATA 0x00C0C001 -#define DDRSS0_PHY_102_DATA 0x0E0D0001 +#define DDRSS0_PHY_102_DATA 0x0E0D0101 #define DDRSS0_PHY_103_DATA 0x10001000 #define DDRSS0_PHY_104_DATA 0x0C083E42 #define DDRSS0_PHY_105_DATA 0x0F0C3701 @@ -1045,7 +1074,7 @@ #define DDRSS0_PHY_265_DATA 0x00000000 #define DDRSS0_PHY_266_DATA 0x00000000 #define DDRSS0_PHY_267_DATA 0x01000001 -#define DDRSS0_PHY_268_DATA 0x00000100 +#define DDRSS0_PHY_268_DATA 0x00000200 #define DDRSS0_PHY_269_DATA 0x000800C0 #define DDRSS0_PHY_270_DATA 0x060100CC #define DDRSS0_PHY_271_DATA 0x00030066 @@ -1064,7 +1093,7 @@ #define DDRSS0_PHY_284_DATA 0x2A000000 #define DDRSS0_PHY_285_DATA 0x00000808 #define DDRSS0_PHY_286_DATA 0x0F000000 -#define DDRSS0_PHY_287_DATA 0x00000F0F +#define DDRSS0_PHY_287_DATA 0x00000F08 #define DDRSS0_PHY_288_DATA 0x10400000 #define DDRSS0_PHY_289_DATA 0x0C002006 #define DDRSS0_PHY_290_DATA 0x00000000 @@ -1133,9 +1162,9 @@ #define DDRSS0_PHY_353_DATA 0x00050010 #define DDRSS0_PHY_354_DATA 0x51517041 #define DDRSS0_PHY_355_DATA 0x31C06001 -#define DDRSS0_PHY_356_DATA 0x07AB0340 +#define DDRSS0_PHY_356_DATA 0x07AB01AB #define DDRSS0_PHY_357_DATA 0x00C0C001 -#define DDRSS0_PHY_358_DATA 0x0E0D0001 +#define DDRSS0_PHY_358_DATA 0x0E0D0101 #define DDRSS0_PHY_359_DATA 0x10001000 #define DDRSS0_PHY_360_DATA 0x0C083E42 #define DDRSS0_PHY_361_DATA 0x0F0C3701 @@ -1301,7 +1330,7 @@ #define DDRSS0_PHY_521_DATA 0x00000000 #define DDRSS0_PHY_522_DATA 0x00000000 #define DDRSS0_PHY_523_DATA 0x01000001 -#define DDRSS0_PHY_524_DATA 0x00000100 +#define DDRSS0_PHY_524_DATA 0x00000200 #define DDRSS0_PHY_525_DATA 0x000800C0 #define DDRSS0_PHY_526_DATA 0x060100CC #define DDRSS0_PHY_527_DATA 0x00030066 @@ -1320,7 +1349,7 @@ #define DDRSS0_PHY_540_DATA 0x2A000000 #define DDRSS0_PHY_541_DATA 0x00000808 #define DDRSS0_PHY_542_DATA 0x0F000000 -#define DDRSS0_PHY_543_DATA 0x00000F0F +#define DDRSS0_PHY_543_DATA 0x00000F08 #define DDRSS0_PHY_544_DATA 0x10400000 #define DDRSS0_PHY_545_DATA 0x0C002006 #define DDRSS0_PHY_546_DATA 0x00000000 @@ -1389,9 +1418,9 @@ #define DDRSS0_PHY_609_DATA 0x00050010 #define DDRSS0_PHY_610_DATA 0x51517041 #define DDRSS0_PHY_611_DATA 0x31C06001 -#define DDRSS0_PHY_612_DATA 0x07AB0340 +#define DDRSS0_PHY_612_DATA 0x07AB01AB #define DDRSS0_PHY_613_DATA 0x00C0C001 -#define DDRSS0_PHY_614_DATA 0x0E0D0001 +#define DDRSS0_PHY_614_DATA 0x0E0D0101 #define DDRSS0_PHY_615_DATA 0x10001000 #define DDRSS0_PHY_616_DATA 0x0C083E42 #define DDRSS0_PHY_617_DATA 0x0F0C3701 @@ -1557,7 +1586,7 @@ #define DDRSS0_PHY_777_DATA 0x00000000 #define DDRSS0_PHY_778_DATA 0x00000000 #define DDRSS0_PHY_779_DATA 0x01000001 -#define DDRSS0_PHY_780_DATA 0x00000100 +#define DDRSS0_PHY_780_DATA 0x00000200 #define DDRSS0_PHY_781_DATA 0x000800C0 #define DDRSS0_PHY_782_DATA 0x060100CC #define DDRSS0_PHY_783_DATA 0x00030066 @@ -1576,7 +1605,7 @@ #define DDRSS0_PHY_796_DATA 0x2A000000 #define DDRSS0_PHY_797_DATA 0x00000808 #define DDRSS0_PHY_798_DATA 0x0F000000 -#define DDRSS0_PHY_799_DATA 0x00000F0F +#define DDRSS0_PHY_799_DATA 0x00000F08 #define DDRSS0_PHY_800_DATA 0x10400000 #define DDRSS0_PHY_801_DATA 0x0C002006 #define DDRSS0_PHY_802_DATA 0x00000000 @@ -1645,9 +1674,9 @@ #define DDRSS0_PHY_865_DATA 0x00050010 #define DDRSS0_PHY_866_DATA 0x51517041 #define DDRSS0_PHY_867_DATA 0x31C06001 -#define DDRSS0_PHY_868_DATA 0x07AB0340 +#define DDRSS0_PHY_868_DATA 0x07AB01AB #define DDRSS0_PHY_869_DATA 0x00C0C001 -#define DDRSS0_PHY_870_DATA 0x0E0D0001 +#define DDRSS0_PHY_870_DATA 0x0E0D0101 #define DDRSS0_PHY_871_DATA 0x10001000 #define DDRSS0_PHY_872_DATA 0x0C083E42 #define DDRSS0_PHY_873_DATA 0x0F0C3701 @@ -1832,7 +1861,7 @@ #define DDRSS0_PHY_1052_DATA 0x00000033 #define DDRSS0_PHY_1053_DATA 0x00543210 #define DDRSS0_PHY_1054_DATA 0x003F0000 -#define DDRSS0_PHY_1055_DATA 0x000F013F +#define DDRSS0_PHY_1055_DATA 0x000F3F3F #define DDRSS0_PHY_1056_DATA 0x20202003 #define DDRSS0_PHY_1057_DATA 0x00202020 #define DDRSS0_PHY_1058_DATA 0x20008008 @@ -2080,7 +2109,7 @@ #define DDRSS0_PHY_1300_DATA 0x00040101 #define DDRSS0_PHY_1301_DATA 0x0000010F #define DDRSS0_PHY_1302_DATA 0x00000000 -#define DDRSS0_PHY_1303_DATA 0x0000FFFF +#define DDRSS0_PHY_1303_DATA 0x00000064 #define DDRSS0_PHY_1304_DATA 0x00000000 #define DDRSS0_PHY_1305_DATA 0x01010000 #define DDRSS0_PHY_1306_DATA 0x01080402 @@ -2174,7 +2203,7 @@ #define DDRSS0_PHY_1394_DATA 0x00000003 #define DDRSS0_PHY_1395_DATA 0x00000000 #define DDRSS0_PHY_1396_DATA 0x00001142 -#define DDRSS0_PHY_1397_DATA 0x010207AB +#define DDRSS0_PHY_1397_DATA 0x040207AB #define DDRSS0_PHY_1398_DATA 0x01000080 #define DDRSS0_PHY_1399_DATA 0x03900390 #define DDRSS0_PHY_1400_DATA 0x03900390 @@ -2221,7 +2250,7 @@ #define DDRSS1_CTL_17_DATA 0x00000005 #define DDRSS1_CTL_18_DATA 0x000010A9 #define DDRSS1_CTL_19_DATA 0x01010000 -#define DDRSS1_CTL_20_DATA 0x02011001 +#define DDRSS1_CTL_20_DATA 0x01011001 #define DDRSS1_CTL_21_DATA 0x02010000 #define DDRSS1_CTL_22_DATA 0x00020100 #define DDRSS1_CTL_23_DATA 0x0000000B @@ -2236,7 +2265,7 @@ #define DDRSS1_CTL_32_DATA 0x00000000 #define DDRSS1_CTL_33_DATA 0x00000000 #define DDRSS1_CTL_34_DATA 0x040C0000 -#define DDRSS1_CTL_35_DATA 0x12481248 +#define DDRSS1_CTL_35_DATA 0x12501250 #define DDRSS1_CTL_36_DATA 0x00050804 #define DDRSS1_CTL_37_DATA 0x09040008 #define DDRSS1_CTL_38_DATA 0x15000204 @@ -2251,27 +2280,27 @@ #define DDRSS1_CTL_47_DATA 0x1E161110 #define DDRSS1_CTL_48_DATA 0x1000922C #define DDRSS1_CTL_49_DATA 0x02030410 -#define DDRSS1_CTL_50_DATA 0x2C040500 +#define DDRSS1_CTL_50_DATA 0x2C060500 #define DDRSS1_CTL_51_DATA 0x08292C29 #define DDRSS1_CTL_52_DATA 0x14000E0A #define DDRSS1_CTL_53_DATA 0x04010A0A #define DDRSS1_CTL_54_DATA 0x01010004 -#define DDRSS1_CTL_55_DATA 0x04545408 +#define DDRSS1_CTL_55_DATA 0x0454540A #define DDRSS1_CTL_56_DATA 0x04313104 #define DDRSS1_CTL_57_DATA 0x00003131 #define DDRSS1_CTL_58_DATA 0x00010100 #define DDRSS1_CTL_59_DATA 0x03010000 #define DDRSS1_CTL_60_DATA 0x00001508 -#define DDRSS1_CTL_61_DATA 0x00000063 +#define DDRSS1_CTL_61_DATA 0x00000068 #define DDRSS1_CTL_62_DATA 0x0000032B #define DDRSS1_CTL_63_DATA 0x00001035 #define DDRSS1_CTL_64_DATA 0x0000032B #define DDRSS1_CTL_65_DATA 0x00001035 #define DDRSS1_CTL_66_DATA 0x00000005 #define DDRSS1_CTL_67_DATA 0x00050000 -#define DDRSS1_CTL_68_DATA 0x00CB0012 -#define DDRSS1_CTL_69_DATA 0x00CB0408 -#define DDRSS1_CTL_70_DATA 0x00400408 +#define DDRSS1_CTL_68_DATA 0x00CB0005 +#define DDRSS1_CTL_69_DATA 0x00CB0200 +#define DDRSS1_CTL_70_DATA 0x00400200 #define DDRSS1_CTL_71_DATA 0x00120103 #define DDRSS1_CTL_72_DATA 0x00100005 #define DDRSS1_CTL_73_DATA 0x2F080010 @@ -2377,22 +2406,22 @@ #define DDRSS1_CTL_173_DATA 0x00000000 #define DDRSS1_CTL_174_DATA 0x00000000 #define DDRSS1_CTL_175_DATA 0x3FF40084 -#define DDRSS1_CTL_176_DATA 0x33003FF4 -#define DDRSS1_CTL_177_DATA 0x00003333 +#define DDRSS1_CTL_176_DATA 0xF3003FF4 +#define DDRSS1_CTL_177_DATA 0x0000F3F3 #define DDRSS1_CTL_178_DATA 0x35000000 #define DDRSS1_CTL_179_DATA 0x27270035 #define DDRSS1_CTL_180_DATA 0x0F0F0000 #define DDRSS1_CTL_181_DATA 0x16000000 #define DDRSS1_CTL_182_DATA 0x00841616 #define DDRSS1_CTL_183_DATA 0x3FF43FF4 -#define DDRSS1_CTL_184_DATA 0x33333300 +#define DDRSS1_CTL_184_DATA 0xF3F3F300 #define DDRSS1_CTL_185_DATA 0x00000000 #define DDRSS1_CTL_186_DATA 0x00353500 #define DDRSS1_CTL_187_DATA 0x00002727 #define DDRSS1_CTL_188_DATA 0x00000F0F #define DDRSS1_CTL_189_DATA 0x16161600 #define DDRSS1_CTL_190_DATA 0x00000020 -#define DDRSS1_CTL_191_DATA 0x00000000 +#define DDRSS1_CTL_191_DATA 0x01000000 #define DDRSS1_CTL_192_DATA 0x00000001 #define DDRSS1_CTL_193_DATA 0x00000000 #define DDRSS1_CTL_194_DATA 0x01000000 @@ -2492,14 +2521,14 @@ #define DDRSS1_CTL_288_DATA 0x00000000 #define DDRSS1_CTL_289_DATA 0x00000000 #define DDRSS1_CTL_290_DATA 0x03030300 -#define DDRSS1_CTL_291_DATA 0x00000001 +#define DDRSS1_CTL_291_DATA 0x00010101 #define DDRSS1_CTL_292_DATA 0x00000000 #define DDRSS1_CTL_293_DATA 0x00000000 #define DDRSS1_CTL_294_DATA 0x00000000 #define DDRSS1_CTL_295_DATA 0x00000000 #define DDRSS1_CTL_296_DATA 0x00000000 -#define DDRSS1_CTL_297_DATA 0x00000000 -#define DDRSS1_CTL_298_DATA 0x00000000 +#define DDRSS1_CTL_297_DATA 0xFFFFFFFF +#define DDRSS1_CTL_298_DATA 0x00000FFF #define DDRSS1_CTL_299_DATA 0x00000000 #define DDRSS1_CTL_300_DATA 0x00000000 #define DDRSS1_CTL_301_DATA 0x00000000 @@ -2520,7 +2549,7 @@ #define DDRSS1_CTL_316_DATA 0x01010001 #define DDRSS1_CTL_317_DATA 0x00010101 #define DDRSS1_CTL_318_DATA 0x050A0A03 -#define DDRSS1_CTL_319_DATA 0x10081F1F +#define DDRSS1_CTL_319_DATA 0x10082323 #define DDRSS1_CTL_320_DATA 0x00090310 #define DDRSS1_CTL_321_DATA 0x0B0C030F #define DDRSS1_CTL_322_DATA 0x0B0C0306 @@ -2595,7 +2624,7 @@ #define DDRSS1_CTL_391_DATA 0x00000200 #define DDRSS1_CTL_392_DATA 0x00000200 #define DDRSS1_CTL_393_DATA 0x00000200 -#define DDRSS1_CTL_394_DATA 0x00000252 +#define DDRSS1_CTL_394_DATA 0x00000270 #define DDRSS1_CTL_395_DATA 0x000007BC #define DDRSS1_CTL_396_DATA 0x00000204 #define DDRSS1_CTL_397_DATA 0x0000206A @@ -2605,7 +2634,7 @@ #define DDRSS1_CTL_401_DATA 0x00000200 #define DDRSS1_CTL_402_DATA 0x0000613E #define DDRSS1_CTL_403_DATA 0x00014424 -#define DDRSS1_CTL_404_DATA 0x00000E15 +#define DDRSS1_CTL_404_DATA 0x00000E19 #define DDRSS1_CTL_405_DATA 0x0000206A #define DDRSS1_CTL_406_DATA 0x00000200 #define DDRSS1_CTL_407_DATA 0x00000200 @@ -2613,7 +2642,7 @@ #define DDRSS1_CTL_409_DATA 0x00000200 #define DDRSS1_CTL_410_DATA 0x0000613E #define DDRSS1_CTL_411_DATA 0x00014424 -#define DDRSS1_CTL_412_DATA 0x02020E15 +#define DDRSS1_CTL_412_DATA 0x02020E19 #define DDRSS1_CTL_413_DATA 0x03030202 #define DDRSS1_CTL_414_DATA 0x00000022 #define DDRSS1_CTL_415_DATA 0x00000000 @@ -2630,7 +2659,7 @@ #define DDRSS1_CTL_426_DATA 0x00000000 #define DDRSS1_CTL_427_DATA 0x02000000 #define DDRSS1_CTL_428_DATA 0x01000404 -#define DDRSS1_CTL_429_DATA 0x0B1E0B1E +#define DDRSS1_CTL_429_DATA 0x0B220B22 #define DDRSS1_CTL_430_DATA 0x00000105 #define DDRSS1_CTL_431_DATA 0x00010101 #define DDRSS1_CTL_432_DATA 0x00010101 @@ -2673,8 +2702,8 @@ #define DDRSS1_PI_09_DATA 0x00000000 #define DDRSS1_PI_10_DATA 0x00000000 #define DDRSS1_PI_11_DATA 0x00000000 -#define DDRSS1_PI_12_DATA 0x00000007 -#define DDRSS1_PI_13_DATA 0x00010002 +#define DDRSS1_PI_12_DATA 0x00000003 +#define DDRSS1_PI_13_DATA 0x00010001 #define DDRSS1_PI_14_DATA 0x0800000F #define DDRSS1_PI_15_DATA 0x00000103 #define DDRSS1_PI_16_DATA 0x00000005 @@ -2722,18 +2751,18 @@ #define DDRSS1_PI_58_DATA 0x00000000 #define DDRSS1_PI_59_DATA 0x00000000 #define DDRSS1_PI_60_DATA 0x0A0A140A -#define DDRSS1_PI_61_DATA 0x10020101 +#define DDRSS1_PI_61_DATA 0x10020201 #define DDRSS1_PI_62_DATA 0x00020805 #define DDRSS1_PI_63_DATA 0x01000404 #define DDRSS1_PI_64_DATA 0x00000000 #define DDRSS1_PI_65_DATA 0x00000000 #define DDRSS1_PI_66_DATA 0x00000100 -#define DDRSS1_PI_67_DATA 0x0001010F +#define DDRSS1_PI_67_DATA 0x0002020F #define DDRSS1_PI_68_DATA 0x00340000 #define DDRSS1_PI_69_DATA 0x00000000 #define DDRSS1_PI_70_DATA 0x00000000 #define DDRSS1_PI_71_DATA 0x0000FFFF -#define DDRSS1_PI_72_DATA 0x00000000 +#define DDRSS1_PI_72_DATA 0x01000000 #define DDRSS1_PI_73_DATA 0x00080000 #define DDRSS1_PI_74_DATA 0x02000200 #define DDRSS1_PI_75_DATA 0x01000100 @@ -2822,37 +2851,37 @@ #define DDRSS1_PI_158_DATA 0x00000000 #define DDRSS1_PI_159_DATA 0x00000401 #define DDRSS1_PI_160_DATA 0x00000000 -#define DDRSS1_PI_161_DATA 0x00010000 -#define DDRSS1_PI_162_DATA 0x00000000 -#define DDRSS1_PI_163_DATA 0x2B2B0200 +#define DDRSS1_PI_161_DATA 0x05010000 +#define DDRSS1_PI_162_DATA 0x00000001 +#define DDRSS1_PI_163_DATA 0x2B2B0201 #define DDRSS1_PI_164_DATA 0x00000034 -#define DDRSS1_PI_165_DATA 0x00000064 -#define DDRSS1_PI_166_DATA 0x00020064 +#define DDRSS1_PI_165_DATA 0x00000068 +#define DDRSS1_PI_166_DATA 0x00020068 #define DDRSS1_PI_167_DATA 0x02000200 -#define DDRSS1_PI_168_DATA 0x48120C04 -#define DDRSS1_PI_169_DATA 0x00154812 -#define DDRSS1_PI_170_DATA 0x00000063 +#define DDRSS1_PI_168_DATA 0x50120C04 +#define DDRSS1_PI_169_DATA 0x00155012 +#define DDRSS1_PI_170_DATA 0x00000068 #define DDRSS1_PI_171_DATA 0x0000032B #define DDRSS1_PI_172_DATA 0x00001035 #define DDRSS1_PI_173_DATA 0x0000032B #define DDRSS1_PI_174_DATA 0x04001035 #define DDRSS1_PI_175_DATA 0x01010404 -#define DDRSS1_PI_176_DATA 0x00001501 +#define DDRSS1_PI_176_DATA 0x00001500 #define DDRSS1_PI_177_DATA 0x00150015 #define DDRSS1_PI_178_DATA 0x01000100 #define DDRSS1_PI_179_DATA 0x00000100 #define DDRSS1_PI_180_DATA 0x00000000 #define DDRSS1_PI_181_DATA 0x01010101 -#define DDRSS1_PI_182_DATA 0x00000101 +#define DDRSS1_PI_182_DATA 0x00000000 #define DDRSS1_PI_183_DATA 0x00000000 #define DDRSS1_PI_184_DATA 0x00000000 -#define DDRSS1_PI_185_DATA 0x15040000 -#define DDRSS1_PI_186_DATA 0x0E0E0215 +#define DDRSS1_PI_185_DATA 0x19040000 +#define DDRSS1_PI_186_DATA 0x0E0E0219 #define DDRSS1_PI_187_DATA 0x00040402 #define DDRSS1_PI_188_DATA 0x000D0035 #define DDRSS1_PI_189_DATA 0x00218049 #define DDRSS1_PI_190_DATA 0x00218049 -#define DDRSS1_PI_191_DATA 0x01010101 +#define DDRSS1_PI_191_DATA 0x01000101 #define DDRSS1_PI_192_DATA 0x0004000E #define DDRSS1_PI_193_DATA 0x00040216 #define DDRSS1_PI_194_DATA 0x01000216 @@ -2860,8 +2889,8 @@ #define DDRSS1_PI_196_DATA 0x02170100 #define DDRSS1_PI_197_DATA 0x01000217 #define DDRSS1_PI_198_DATA 0x02170217 -#define DDRSS1_PI_199_DATA 0x32103200 -#define DDRSS1_PI_200_DATA 0x01013210 +#define DDRSS1_PI_199_DATA 0x2F1B3200 +#define DDRSS1_PI_200_DATA 0x01012F1B #define DDRSS1_PI_201_DATA 0x0A070601 #define DDRSS1_PI_202_DATA 0x1F130A0D #define DDRSS1_PI_203_DATA 0x1F130A14 @@ -2873,13 +2902,13 @@ #define DDRSS1_PI_209_DATA 0x00240216 #define DDRSS1_PI_210_DATA 0x00110216 #define DDRSS1_PI_211_DATA 0x32000056 -#define DDRSS1_PI_212_DATA 0x00000301 -#define DDRSS1_PI_213_DATA 0x005B0036 +#define DDRSS1_PI_212_DATA 0x00000101 +#define DDRSS1_PI_213_DATA 0x005F0036 #define DDRSS1_PI_214_DATA 0x03013212 #define DDRSS1_PI_215_DATA 0x00003600 -#define DDRSS1_PI_216_DATA 0x3212005B -#define DDRSS1_PI_217_DATA 0x09000301 -#define DDRSS1_PI_218_DATA 0x04010504 +#define DDRSS1_PI_216_DATA 0x3212005F +#define DDRSS1_PI_217_DATA 0x09000001 +#define DDRSS1_PI_218_DATA 0x06010504 #define DDRSS1_PI_219_DATA 0x04000364 #define DDRSS1_PI_220_DATA 0x0A032001 #define DDRSS1_PI_221_DATA 0x2C31110A @@ -2936,29 +2965,29 @@ #define DDRSS1_PI_272_DATA 0x00080804 #define DDRSS1_PI_273_DATA 0x00000000 #define DDRSS1_PI_274_DATA 0x00000000 -#define DDRSS1_PI_275_DATA 0x00330084 +#define DDRSS1_PI_275_DATA 0x00F30084 #define DDRSS1_PI_276_DATA 0x00160000 -#define DDRSS1_PI_277_DATA 0x35333FF4 +#define DDRSS1_PI_277_DATA 0x35F33FF4 #define DDRSS1_PI_278_DATA 0x00160F27 -#define DDRSS1_PI_279_DATA 0x35333FF4 +#define DDRSS1_PI_279_DATA 0x35F33FF4 #define DDRSS1_PI_280_DATA 0x00160F27 -#define DDRSS1_PI_281_DATA 0x00330084 +#define DDRSS1_PI_281_DATA 0x00F30084 #define DDRSS1_PI_282_DATA 0x00160000 -#define DDRSS1_PI_283_DATA 0x35333FF4 +#define DDRSS1_PI_283_DATA 0x35F33FF4 #define DDRSS1_PI_284_DATA 0x00160F27 -#define DDRSS1_PI_285_DATA 0x35333FF4 +#define DDRSS1_PI_285_DATA 0x35F33FF4 #define DDRSS1_PI_286_DATA 0x00160F27 -#define DDRSS1_PI_287_DATA 0x00330084 +#define DDRSS1_PI_287_DATA 0x00F30084 #define DDRSS1_PI_288_DATA 0x00160000 -#define DDRSS1_PI_289_DATA 0x35333FF4 +#define DDRSS1_PI_289_DATA 0x35F33FF4 #define DDRSS1_PI_290_DATA 0x00160F27 -#define DDRSS1_PI_291_DATA 0x35333FF4 +#define DDRSS1_PI_291_DATA 0x35F33FF4 #define DDRSS1_PI_292_DATA 0x00160F27 -#define DDRSS1_PI_293_DATA 0x00330084 +#define DDRSS1_PI_293_DATA 0x00F30084 #define DDRSS1_PI_294_DATA 0x00160000 -#define DDRSS1_PI_295_DATA 0x35333FF4 +#define DDRSS1_PI_295_DATA 0x35F33FF4 #define DDRSS1_PI_296_DATA 0x00160F27 -#define DDRSS1_PI_297_DATA 0x35333FF4 +#define DDRSS1_PI_297_DATA 0x35F33FF4 #define DDRSS1_PI_298_DATA 0x00160F27 #define DDRSS1_PI_299_DATA 0x00000000 @@ -2974,7 +3003,7 @@ #define DDRSS1_PHY_09_DATA 0x00000000 #define DDRSS1_PHY_10_DATA 0x00000000 #define DDRSS1_PHY_11_DATA 0x01000001 -#define DDRSS1_PHY_12_DATA 0x00000100 +#define DDRSS1_PHY_12_DATA 0x00000200 #define DDRSS1_PHY_13_DATA 0x000800C0 #define DDRSS1_PHY_14_DATA 0x060100CC #define DDRSS1_PHY_15_DATA 0x00030066 @@ -2993,7 +3022,7 @@ #define DDRSS1_PHY_28_DATA 0x2A000000 #define DDRSS1_PHY_29_DATA 0x00000808 #define DDRSS1_PHY_30_DATA 0x0F000000 -#define DDRSS1_PHY_31_DATA 0x00000F0F +#define DDRSS1_PHY_31_DATA 0x00000F08 #define DDRSS1_PHY_32_DATA 0x10400000 #define DDRSS1_PHY_33_DATA 0x0C002006 #define DDRSS1_PHY_34_DATA 0x00000000 @@ -3062,9 +3091,9 @@ #define DDRSS1_PHY_97_DATA 0x00050010 #define DDRSS1_PHY_98_DATA 0x51517041 #define DDRSS1_PHY_99_DATA 0x31C06001 -#define DDRSS1_PHY_100_DATA 0x07AB0340 +#define DDRSS1_PHY_100_DATA 0x07AB01AB #define DDRSS1_PHY_101_DATA 0x00C0C001 -#define DDRSS1_PHY_102_DATA 0x0E0D0001 +#define DDRSS1_PHY_102_DATA 0x0E0D0101 #define DDRSS1_PHY_103_DATA 0x10001000 #define DDRSS1_PHY_104_DATA 0x0C083E42 #define DDRSS1_PHY_105_DATA 0x0F0C3701 @@ -3230,7 +3259,7 @@ #define DDRSS1_PHY_265_DATA 0x00000000 #define DDRSS1_PHY_266_DATA 0x00000000 #define DDRSS1_PHY_267_DATA 0x01000001 -#define DDRSS1_PHY_268_DATA 0x00000100 +#define DDRSS1_PHY_268_DATA 0x00000200 #define DDRSS1_PHY_269_DATA 0x000800C0 #define DDRSS1_PHY_270_DATA 0x060100CC #define DDRSS1_PHY_271_DATA 0x00030066 @@ -3249,7 +3278,7 @@ #define DDRSS1_PHY_284_DATA 0x2A000000 #define DDRSS1_PHY_285_DATA 0x00000808 #define DDRSS1_PHY_286_DATA 0x0F000000 -#define DDRSS1_PHY_287_DATA 0x00000F0F +#define DDRSS1_PHY_287_DATA 0x00000F08 #define DDRSS1_PHY_288_DATA 0x10400000 #define DDRSS1_PHY_289_DATA 0x0C002006 #define DDRSS1_PHY_290_DATA 0x00000000 @@ -3318,9 +3347,9 @@ #define DDRSS1_PHY_353_DATA 0x00050010 #define DDRSS1_PHY_354_DATA 0x51517041 #define DDRSS1_PHY_355_DATA 0x31C06001 -#define DDRSS1_PHY_356_DATA 0x07AB0340 +#define DDRSS1_PHY_356_DATA 0x07AB01AB #define DDRSS1_PHY_357_DATA 0x00C0C001 -#define DDRSS1_PHY_358_DATA 0x0E0D0001 +#define DDRSS1_PHY_358_DATA 0x0E0D0101 #define DDRSS1_PHY_359_DATA 0x10001000 #define DDRSS1_PHY_360_DATA 0x0C083E42 #define DDRSS1_PHY_361_DATA 0x0F0C3701 @@ -3486,7 +3515,7 @@ #define DDRSS1_PHY_521_DATA 0x00000000 #define DDRSS1_PHY_522_DATA 0x00000000 #define DDRSS1_PHY_523_DATA 0x01000001 -#define DDRSS1_PHY_524_DATA 0x00000100 +#define DDRSS1_PHY_524_DATA 0x00000200 #define DDRSS1_PHY_525_DATA 0x000800C0 #define DDRSS1_PHY_526_DATA 0x060100CC #define DDRSS1_PHY_527_DATA 0x00030066 @@ -3505,7 +3534,7 @@ #define DDRSS1_PHY_540_DATA 0x2A000000 #define DDRSS1_PHY_541_DATA 0x00000808 #define DDRSS1_PHY_542_DATA 0x0F000000 -#define DDRSS1_PHY_543_DATA 0x00000F0F +#define DDRSS1_PHY_543_DATA 0x00000F08 #define DDRSS1_PHY_544_DATA 0x10400000 #define DDRSS1_PHY_545_DATA 0x0C002006 #define DDRSS1_PHY_546_DATA 0x00000000 @@ -3574,9 +3603,9 @@ #define DDRSS1_PHY_609_DATA 0x00050010 #define DDRSS1_PHY_610_DATA 0x51517041 #define DDRSS1_PHY_611_DATA 0x31C06001 -#define DDRSS1_PHY_612_DATA 0x07AB0340 +#define DDRSS1_PHY_612_DATA 0x07AB01AB #define DDRSS1_PHY_613_DATA 0x00C0C001 -#define DDRSS1_PHY_614_DATA 0x0E0D0001 +#define DDRSS1_PHY_614_DATA 0x0E0D0101 #define DDRSS1_PHY_615_DATA 0x10001000 #define DDRSS1_PHY_616_DATA 0x0C083E42 #define DDRSS1_PHY_617_DATA 0x0F0C3701 @@ -3742,7 +3771,7 @@ #define DDRSS1_PHY_777_DATA 0x00000000 #define DDRSS1_PHY_778_DATA 0x00000000 #define DDRSS1_PHY_779_DATA 0x01000001 -#define DDRSS1_PHY_780_DATA 0x00000100 +#define DDRSS1_PHY_780_DATA 0x00000200 #define DDRSS1_PHY_781_DATA 0x000800C0 #define DDRSS1_PHY_782_DATA 0x060100CC #define DDRSS1_PHY_783_DATA 0x00030066 @@ -3761,7 +3790,7 @@ #define DDRSS1_PHY_796_DATA 0x2A000000 #define DDRSS1_PHY_797_DATA 0x00000808 #define DDRSS1_PHY_798_DATA 0x0F000000 -#define DDRSS1_PHY_799_DATA 0x00000F0F +#define DDRSS1_PHY_799_DATA 0x00000F08 #define DDRSS1_PHY_800_DATA 0x10400000 #define DDRSS1_PHY_801_DATA 0x0C002006 #define DDRSS1_PHY_802_DATA 0x00000000 @@ -3830,9 +3859,9 @@ #define DDRSS1_PHY_865_DATA 0x00050010 #define DDRSS1_PHY_866_DATA 0x51517041 #define DDRSS1_PHY_867_DATA 0x31C06001 -#define DDRSS1_PHY_868_DATA 0x07AB0340 +#define DDRSS1_PHY_868_DATA 0x07AB01AB #define DDRSS1_PHY_869_DATA 0x00C0C001 -#define DDRSS1_PHY_870_DATA 0x0E0D0001 +#define DDRSS1_PHY_870_DATA 0x0E0D0101 #define DDRSS1_PHY_871_DATA 0x10001000 #define DDRSS1_PHY_872_DATA 0x0C083E42 #define DDRSS1_PHY_873_DATA 0x0F0C3701 @@ -4017,7 +4046,7 @@ #define DDRSS1_PHY_1052_DATA 0x00000033 #define DDRSS1_PHY_1053_DATA 0x00543210 #define DDRSS1_PHY_1054_DATA 0x003F0000 -#define DDRSS1_PHY_1055_DATA 0x000F013F +#define DDRSS1_PHY_1055_DATA 0x000F3F3F #define DDRSS1_PHY_1056_DATA 0x20202003 #define DDRSS1_PHY_1057_DATA 0x00202020 #define DDRSS1_PHY_1058_DATA 0x20008008 @@ -4265,7 +4294,7 @@ #define DDRSS1_PHY_1300_DATA 0x00040101 #define DDRSS1_PHY_1301_DATA 0x0000010F #define DDRSS1_PHY_1302_DATA 0x00000000 -#define DDRSS1_PHY_1303_DATA 0x0000FFFF +#define DDRSS1_PHY_1303_DATA 0x00000064 #define DDRSS1_PHY_1304_DATA 0x00000000 #define DDRSS1_PHY_1305_DATA 0x01010000 #define DDRSS1_PHY_1306_DATA 0x01080402 @@ -4359,7 +4388,7 @@ #define DDRSS1_PHY_1394_DATA 0x00000003 #define DDRSS1_PHY_1395_DATA 0x00000000 #define DDRSS1_PHY_1396_DATA 0x00001142 -#define DDRSS1_PHY_1397_DATA 0x010207AB +#define DDRSS1_PHY_1397_DATA 0x040207AB #define DDRSS1_PHY_1398_DATA 0x01000080 #define DDRSS1_PHY_1399_DATA 0x03900390 #define DDRSS1_PHY_1400_DATA 0x03900390 @@ -4406,7 +4435,7 @@ #define DDRSS2_CTL_17_DATA 0x00000005 #define DDRSS2_CTL_18_DATA 0x000010A9 #define DDRSS2_CTL_19_DATA 0x01010000 -#define DDRSS2_CTL_20_DATA 0x02011001 +#define DDRSS2_CTL_20_DATA 0x01011001 #define DDRSS2_CTL_21_DATA 0x02010000 #define DDRSS2_CTL_22_DATA 0x00020100 #define DDRSS2_CTL_23_DATA 0x0000000B @@ -4421,7 +4450,7 @@ #define DDRSS2_CTL_32_DATA 0x00000000 #define DDRSS2_CTL_33_DATA 0x00000000 #define DDRSS2_CTL_34_DATA 0x040C0000 -#define DDRSS2_CTL_35_DATA 0x12481248 +#define DDRSS2_CTL_35_DATA 0x12501250 #define DDRSS2_CTL_36_DATA 0x00050804 #define DDRSS2_CTL_37_DATA 0x09040008 #define DDRSS2_CTL_38_DATA 0x15000204 @@ -4436,27 +4465,27 @@ #define DDRSS2_CTL_47_DATA 0x1E161110 #define DDRSS2_CTL_48_DATA 0x1000922C #define DDRSS2_CTL_49_DATA 0x02030410 -#define DDRSS2_CTL_50_DATA 0x2C040500 +#define DDRSS2_CTL_50_DATA 0x2C060500 #define DDRSS2_CTL_51_DATA 0x08292C29 #define DDRSS2_CTL_52_DATA 0x14000E0A #define DDRSS2_CTL_53_DATA 0x04010A0A #define DDRSS2_CTL_54_DATA 0x01010004 -#define DDRSS2_CTL_55_DATA 0x04545408 +#define DDRSS2_CTL_55_DATA 0x0454540A #define DDRSS2_CTL_56_DATA 0x04313104 #define DDRSS2_CTL_57_DATA 0x00003131 #define DDRSS2_CTL_58_DATA 0x00010100 #define DDRSS2_CTL_59_DATA 0x03010000 #define DDRSS2_CTL_60_DATA 0x00001508 -#define DDRSS2_CTL_61_DATA 0x00000063 +#define DDRSS2_CTL_61_DATA 0x00000068 #define DDRSS2_CTL_62_DATA 0x0000032B #define DDRSS2_CTL_63_DATA 0x00001035 #define DDRSS2_CTL_64_DATA 0x0000032B #define DDRSS2_CTL_65_DATA 0x00001035 #define DDRSS2_CTL_66_DATA 0x00000005 #define DDRSS2_CTL_67_DATA 0x00050000 -#define DDRSS2_CTL_68_DATA 0x00CB0012 -#define DDRSS2_CTL_69_DATA 0x00CB0408 -#define DDRSS2_CTL_70_DATA 0x00400408 +#define DDRSS2_CTL_68_DATA 0x00CB0005 +#define DDRSS2_CTL_69_DATA 0x00CB0200 +#define DDRSS2_CTL_70_DATA 0x00400200 #define DDRSS2_CTL_71_DATA 0x00120103 #define DDRSS2_CTL_72_DATA 0x00100005 #define DDRSS2_CTL_73_DATA 0x2F080010 @@ -4562,22 +4591,22 @@ #define DDRSS2_CTL_173_DATA 0x00000000 #define DDRSS2_CTL_174_DATA 0x00000000 #define DDRSS2_CTL_175_DATA 0x3FF40084 -#define DDRSS2_CTL_176_DATA 0x33003FF4 -#define DDRSS2_CTL_177_DATA 0x00003333 +#define DDRSS2_CTL_176_DATA 0xF3003FF4 +#define DDRSS2_CTL_177_DATA 0x0000F3F3 #define DDRSS2_CTL_178_DATA 0x35000000 #define DDRSS2_CTL_179_DATA 0x27270035 #define DDRSS2_CTL_180_DATA 0x0F0F0000 #define DDRSS2_CTL_181_DATA 0x16000000 #define DDRSS2_CTL_182_DATA 0x00841616 #define DDRSS2_CTL_183_DATA 0x3FF43FF4 -#define DDRSS2_CTL_184_DATA 0x33333300 +#define DDRSS2_CTL_184_DATA 0xF3F3F300 #define DDRSS2_CTL_185_DATA 0x00000000 #define DDRSS2_CTL_186_DATA 0x00353500 #define DDRSS2_CTL_187_DATA 0x00002727 #define DDRSS2_CTL_188_DATA 0x00000F0F #define DDRSS2_CTL_189_DATA 0x16161600 #define DDRSS2_CTL_190_DATA 0x00000020 -#define DDRSS2_CTL_191_DATA 0x00000000 +#define DDRSS2_CTL_191_DATA 0x01000000 #define DDRSS2_CTL_192_DATA 0x00000001 #define DDRSS2_CTL_193_DATA 0x00000000 #define DDRSS2_CTL_194_DATA 0x01000000 @@ -4677,14 +4706,14 @@ #define DDRSS2_CTL_288_DATA 0x00000000 #define DDRSS2_CTL_289_DATA 0x00000000 #define DDRSS2_CTL_290_DATA 0x03030300 -#define DDRSS2_CTL_291_DATA 0x00000001 +#define DDRSS2_CTL_291_DATA 0x00010101 #define DDRSS2_CTL_292_DATA 0x00000000 #define DDRSS2_CTL_293_DATA 0x00000000 #define DDRSS2_CTL_294_DATA 0x00000000 #define DDRSS2_CTL_295_DATA 0x00000000 #define DDRSS2_CTL_296_DATA 0x00000000 -#define DDRSS2_CTL_297_DATA 0x00000000 -#define DDRSS2_CTL_298_DATA 0x00000000 +#define DDRSS2_CTL_297_DATA 0xFFFFFFFF +#define DDRSS2_CTL_298_DATA 0x00000FFF #define DDRSS2_CTL_299_DATA 0x00000000 #define DDRSS2_CTL_300_DATA 0x00000000 #define DDRSS2_CTL_301_DATA 0x00000000 @@ -4705,7 +4734,7 @@ #define DDRSS2_CTL_316_DATA 0x01010001 #define DDRSS2_CTL_317_DATA 0x00010101 #define DDRSS2_CTL_318_DATA 0x050A0A03 -#define DDRSS2_CTL_319_DATA 0x10081F1F +#define DDRSS2_CTL_319_DATA 0x10082323 #define DDRSS2_CTL_320_DATA 0x00090310 #define DDRSS2_CTL_321_DATA 0x0B0C030F #define DDRSS2_CTL_322_DATA 0x0B0C0306 @@ -4780,7 +4809,7 @@ #define DDRSS2_CTL_391_DATA 0x00000200 #define DDRSS2_CTL_392_DATA 0x00000200 #define DDRSS2_CTL_393_DATA 0x00000200 -#define DDRSS2_CTL_394_DATA 0x00000252 +#define DDRSS2_CTL_394_DATA 0x00000270 #define DDRSS2_CTL_395_DATA 0x000007BC #define DDRSS2_CTL_396_DATA 0x00000204 #define DDRSS2_CTL_397_DATA 0x0000206A @@ -4790,7 +4819,7 @@ #define DDRSS2_CTL_401_DATA 0x00000200 #define DDRSS2_CTL_402_DATA 0x0000613E #define DDRSS2_CTL_403_DATA 0x00014424 -#define DDRSS2_CTL_404_DATA 0x00000E15 +#define DDRSS2_CTL_404_DATA 0x00000E19 #define DDRSS2_CTL_405_DATA 0x0000206A #define DDRSS2_CTL_406_DATA 0x00000200 #define DDRSS2_CTL_407_DATA 0x00000200 @@ -4798,7 +4827,7 @@ #define DDRSS2_CTL_409_DATA 0x00000200 #define DDRSS2_CTL_410_DATA 0x0000613E #define DDRSS2_CTL_411_DATA 0x00014424 -#define DDRSS2_CTL_412_DATA 0x02020E15 +#define DDRSS2_CTL_412_DATA 0x02020E19 #define DDRSS2_CTL_413_DATA 0x03030202 #define DDRSS2_CTL_414_DATA 0x00000022 #define DDRSS2_CTL_415_DATA 0x00000000 @@ -4815,7 +4844,7 @@ #define DDRSS2_CTL_426_DATA 0x00000000 #define DDRSS2_CTL_427_DATA 0x02000000 #define DDRSS2_CTL_428_DATA 0x01000404 -#define DDRSS2_CTL_429_DATA 0x0B1E0B1E +#define DDRSS2_CTL_429_DATA 0x0B220B22 #define DDRSS2_CTL_430_DATA 0x00000105 #define DDRSS2_CTL_431_DATA 0x00010101 #define DDRSS2_CTL_432_DATA 0x00010101 @@ -4858,8 +4887,8 @@ #define DDRSS2_PI_09_DATA 0x00000000 #define DDRSS2_PI_10_DATA 0x00000000 #define DDRSS2_PI_11_DATA 0x00000000 -#define DDRSS2_PI_12_DATA 0x00000007 -#define DDRSS2_PI_13_DATA 0x00010002 +#define DDRSS2_PI_12_DATA 0x00000003 +#define DDRSS2_PI_13_DATA 0x00010001 #define DDRSS2_PI_14_DATA 0x0800000F #define DDRSS2_PI_15_DATA 0x00000103 #define DDRSS2_PI_16_DATA 0x00000005 @@ -4907,18 +4936,18 @@ #define DDRSS2_PI_58_DATA 0x00000000 #define DDRSS2_PI_59_DATA 0x00000000 #define DDRSS2_PI_60_DATA 0x0A0A140A -#define DDRSS2_PI_61_DATA 0x10020101 +#define DDRSS2_PI_61_DATA 0x10020201 #define DDRSS2_PI_62_DATA 0x00020805 #define DDRSS2_PI_63_DATA 0x01000404 #define DDRSS2_PI_64_DATA 0x00000000 #define DDRSS2_PI_65_DATA 0x00000000 #define DDRSS2_PI_66_DATA 0x00000100 -#define DDRSS2_PI_67_DATA 0x0001010F +#define DDRSS2_PI_67_DATA 0x0002020F #define DDRSS2_PI_68_DATA 0x00340000 #define DDRSS2_PI_69_DATA 0x00000000 #define DDRSS2_PI_70_DATA 0x00000000 #define DDRSS2_PI_71_DATA 0x0000FFFF -#define DDRSS2_PI_72_DATA 0x00000000 +#define DDRSS2_PI_72_DATA 0x01000000 #define DDRSS2_PI_73_DATA 0x00080000 #define DDRSS2_PI_74_DATA 0x02000200 #define DDRSS2_PI_75_DATA 0x01000100 @@ -5007,37 +5036,37 @@ #define DDRSS2_PI_158_DATA 0x00000000 #define DDRSS2_PI_159_DATA 0x00000401 #define DDRSS2_PI_160_DATA 0x00000000 -#define DDRSS2_PI_161_DATA 0x00010000 -#define DDRSS2_PI_162_DATA 0x00000000 -#define DDRSS2_PI_163_DATA 0x2B2B0200 +#define DDRSS2_PI_161_DATA 0x05010000 +#define DDRSS2_PI_162_DATA 0x00000001 +#define DDRSS2_PI_163_DATA 0x2B2B0201 #define DDRSS2_PI_164_DATA 0x00000034 -#define DDRSS2_PI_165_DATA 0x00000064 -#define DDRSS2_PI_166_DATA 0x00020064 +#define DDRSS2_PI_165_DATA 0x00000068 +#define DDRSS2_PI_166_DATA 0x00020068 #define DDRSS2_PI_167_DATA 0x02000200 -#define DDRSS2_PI_168_DATA 0x48120C04 -#define DDRSS2_PI_169_DATA 0x00154812 -#define DDRSS2_PI_170_DATA 0x00000063 +#define DDRSS2_PI_168_DATA 0x50120C04 +#define DDRSS2_PI_169_DATA 0x00155012 +#define DDRSS2_PI_170_DATA 0x00000068 #define DDRSS2_PI_171_DATA 0x0000032B #define DDRSS2_PI_172_DATA 0x00001035 #define DDRSS2_PI_173_DATA 0x0000032B #define DDRSS2_PI_174_DATA 0x04001035 #define DDRSS2_PI_175_DATA 0x01010404 -#define DDRSS2_PI_176_DATA 0x00001501 +#define DDRSS2_PI_176_DATA 0x00001500 #define DDRSS2_PI_177_DATA 0x00150015 #define DDRSS2_PI_178_DATA 0x01000100 #define DDRSS2_PI_179_DATA 0x00000100 #define DDRSS2_PI_180_DATA 0x00000000 #define DDRSS2_PI_181_DATA 0x01010101 -#define DDRSS2_PI_182_DATA 0x00000101 +#define DDRSS2_PI_182_DATA 0x00000000 #define DDRSS2_PI_183_DATA 0x00000000 #define DDRSS2_PI_184_DATA 0x00000000 -#define DDRSS2_PI_185_DATA 0x15040000 -#define DDRSS2_PI_186_DATA 0x0E0E0215 +#define DDRSS2_PI_185_DATA 0x19040000 +#define DDRSS2_PI_186_DATA 0x0E0E0219 #define DDRSS2_PI_187_DATA 0x00040402 #define DDRSS2_PI_188_DATA 0x000D0035 #define DDRSS2_PI_189_DATA 0x00218049 #define DDRSS2_PI_190_DATA 0x00218049 -#define DDRSS2_PI_191_DATA 0x01010101 +#define DDRSS2_PI_191_DATA 0x01000101 #define DDRSS2_PI_192_DATA 0x0004000E #define DDRSS2_PI_193_DATA 0x00040216 #define DDRSS2_PI_194_DATA 0x01000216 @@ -5045,8 +5074,8 @@ #define DDRSS2_PI_196_DATA 0x02170100 #define DDRSS2_PI_197_DATA 0x01000217 #define DDRSS2_PI_198_DATA 0x02170217 -#define DDRSS2_PI_199_DATA 0x32103200 -#define DDRSS2_PI_200_DATA 0x01013210 +#define DDRSS2_PI_199_DATA 0x2F1B3200 +#define DDRSS2_PI_200_DATA 0x01012F1B #define DDRSS2_PI_201_DATA 0x0A070601 #define DDRSS2_PI_202_DATA 0x1F130A0D #define DDRSS2_PI_203_DATA 0x1F130A14 @@ -5058,13 +5087,13 @@ #define DDRSS2_PI_209_DATA 0x00240216 #define DDRSS2_PI_210_DATA 0x00110216 #define DDRSS2_PI_211_DATA 0x32000056 -#define DDRSS2_PI_212_DATA 0x00000301 -#define DDRSS2_PI_213_DATA 0x005B0036 +#define DDRSS2_PI_212_DATA 0x00000101 +#define DDRSS2_PI_213_DATA 0x005F0036 #define DDRSS2_PI_214_DATA 0x03013212 #define DDRSS2_PI_215_DATA 0x00003600 -#define DDRSS2_PI_216_DATA 0x3212005B -#define DDRSS2_PI_217_DATA 0x09000301 -#define DDRSS2_PI_218_DATA 0x04010504 +#define DDRSS2_PI_216_DATA 0x3212005F +#define DDRSS2_PI_217_DATA 0x09000001 +#define DDRSS2_PI_218_DATA 0x06010504 #define DDRSS2_PI_219_DATA 0x04000364 #define DDRSS2_PI_220_DATA 0x0A032001 #define DDRSS2_PI_221_DATA 0x2C31110A @@ -5121,29 +5150,29 @@ #define DDRSS2_PI_272_DATA 0x00080804 #define DDRSS2_PI_273_DATA 0x00000000 #define DDRSS2_PI_274_DATA 0x00000000 -#define DDRSS2_PI_275_DATA 0x00330084 +#define DDRSS2_PI_275_DATA 0x00F30084 #define DDRSS2_PI_276_DATA 0x00160000 -#define DDRSS2_PI_277_DATA 0x35333FF4 +#define DDRSS2_PI_277_DATA 0x35F33FF4 #define DDRSS2_PI_278_DATA 0x00160F27 -#define DDRSS2_PI_279_DATA 0x35333FF4 +#define DDRSS2_PI_279_DATA 0x35F33FF4 #define DDRSS2_PI_280_DATA 0x00160F27 -#define DDRSS2_PI_281_DATA 0x00330084 +#define DDRSS2_PI_281_DATA 0x00F30084 #define DDRSS2_PI_282_DATA 0x00160000 -#define DDRSS2_PI_283_DATA 0x35333FF4 +#define DDRSS2_PI_283_DATA 0x35F33FF4 #define DDRSS2_PI_284_DATA 0x00160F27 -#define DDRSS2_PI_285_DATA 0x35333FF4 +#define DDRSS2_PI_285_DATA 0x35F33FF4 #define DDRSS2_PI_286_DATA 0x00160F27 -#define DDRSS2_PI_287_DATA 0x00330084 +#define DDRSS2_PI_287_DATA 0x00F30084 #define DDRSS2_PI_288_DATA 0x00160000 -#define DDRSS2_PI_289_DATA 0x35333FF4 +#define DDRSS2_PI_289_DATA 0x35F33FF4 #define DDRSS2_PI_290_DATA 0x00160F27 -#define DDRSS2_PI_291_DATA 0x35333FF4 +#define DDRSS2_PI_291_DATA 0x35F33FF4 #define DDRSS2_PI_292_DATA 0x00160F27 -#define DDRSS2_PI_293_DATA 0x00330084 +#define DDRSS2_PI_293_DATA 0x00F30084 #define DDRSS2_PI_294_DATA 0x00160000 -#define DDRSS2_PI_295_DATA 0x35333FF4 +#define DDRSS2_PI_295_DATA 0x35F33FF4 #define DDRSS2_PI_296_DATA 0x00160F27 -#define DDRSS2_PI_297_DATA 0x35333FF4 +#define DDRSS2_PI_297_DATA 0x35F33FF4 #define DDRSS2_PI_298_DATA 0x00160F27 #define DDRSS2_PI_299_DATA 0x00000000 @@ -5159,7 +5188,7 @@ #define DDRSS2_PHY_09_DATA 0x00000000 #define DDRSS2_PHY_10_DATA 0x00000000 #define DDRSS2_PHY_11_DATA 0x01000001 -#define DDRSS2_PHY_12_DATA 0x00000100 +#define DDRSS2_PHY_12_DATA 0x00000200 #define DDRSS2_PHY_13_DATA 0x000800C0 #define DDRSS2_PHY_14_DATA 0x060100CC #define DDRSS2_PHY_15_DATA 0x00030066 @@ -5178,7 +5207,7 @@ #define DDRSS2_PHY_28_DATA 0x2A000000 #define DDRSS2_PHY_29_DATA 0x00000808 #define DDRSS2_PHY_30_DATA 0x0F000000 -#define DDRSS2_PHY_31_DATA 0x00000F0F +#define DDRSS2_PHY_31_DATA 0x00000F08 #define DDRSS2_PHY_32_DATA 0x10400000 #define DDRSS2_PHY_33_DATA 0x0C002006 #define DDRSS2_PHY_34_DATA 0x00000000 @@ -5247,9 +5276,9 @@ #define DDRSS2_PHY_97_DATA 0x00050010 #define DDRSS2_PHY_98_DATA 0x51517041 #define DDRSS2_PHY_99_DATA 0x31C06001 -#define DDRSS2_PHY_100_DATA 0x07AB0340 +#define DDRSS2_PHY_100_DATA 0x07AB01AB #define DDRSS2_PHY_101_DATA 0x00C0C001 -#define DDRSS2_PHY_102_DATA 0x0E0D0001 +#define DDRSS2_PHY_102_DATA 0x0E0D0101 #define DDRSS2_PHY_103_DATA 0x10001000 #define DDRSS2_PHY_104_DATA 0x0C083E42 #define DDRSS2_PHY_105_DATA 0x0F0C3701 @@ -5415,7 +5444,7 @@ #define DDRSS2_PHY_265_DATA 0x00000000 #define DDRSS2_PHY_266_DATA 0x00000000 #define DDRSS2_PHY_267_DATA 0x01000001 -#define DDRSS2_PHY_268_DATA 0x00000100 +#define DDRSS2_PHY_268_DATA 0x00000200 #define DDRSS2_PHY_269_DATA 0x000800C0 #define DDRSS2_PHY_270_DATA 0x060100CC #define DDRSS2_PHY_271_DATA 0x00030066 @@ -5434,7 +5463,7 @@ #define DDRSS2_PHY_284_DATA 0x2A000000 #define DDRSS2_PHY_285_DATA 0x00000808 #define DDRSS2_PHY_286_DATA 0x0F000000 -#define DDRSS2_PHY_287_DATA 0x00000F0F +#define DDRSS2_PHY_287_DATA 0x00000F08 #define DDRSS2_PHY_288_DATA 0x10400000 #define DDRSS2_PHY_289_DATA 0x0C002006 #define DDRSS2_PHY_290_DATA 0x00000000 @@ -5503,9 +5532,9 @@ #define DDRSS2_PHY_353_DATA 0x00050010 #define DDRSS2_PHY_354_DATA 0x51517041 #define DDRSS2_PHY_355_DATA 0x31C06001 -#define DDRSS2_PHY_356_DATA 0x07AB0340 +#define DDRSS2_PHY_356_DATA 0x07AB01AB #define DDRSS2_PHY_357_DATA 0x00C0C001 -#define DDRSS2_PHY_358_DATA 0x0E0D0001 +#define DDRSS2_PHY_358_DATA 0x0E0D0101 #define DDRSS2_PHY_359_DATA 0x10001000 #define DDRSS2_PHY_360_DATA 0x0C083E42 #define DDRSS2_PHY_361_DATA 0x0F0C3701 @@ -5671,7 +5700,7 @@ #define DDRSS2_PHY_521_DATA 0x00000000 #define DDRSS2_PHY_522_DATA 0x00000000 #define DDRSS2_PHY_523_DATA 0x01000001 -#define DDRSS2_PHY_524_DATA 0x00000100 +#define DDRSS2_PHY_524_DATA 0x00000200 #define DDRSS2_PHY_525_DATA 0x000800C0 #define DDRSS2_PHY_526_DATA 0x060100CC #define DDRSS2_PHY_527_DATA 0x00030066 @@ -5690,7 +5719,7 @@ #define DDRSS2_PHY_540_DATA 0x2A000000 #define DDRSS2_PHY_541_DATA 0x00000808 #define DDRSS2_PHY_542_DATA 0x0F000000 -#define DDRSS2_PHY_543_DATA 0x00000F0F +#define DDRSS2_PHY_543_DATA 0x00000F08 #define DDRSS2_PHY_544_DATA 0x10400000 #define DDRSS2_PHY_545_DATA 0x0C002006 #define DDRSS2_PHY_546_DATA 0x00000000 @@ -5759,9 +5788,9 @@ #define DDRSS2_PHY_609_DATA 0x00050010 #define DDRSS2_PHY_610_DATA 0x51517041 #define DDRSS2_PHY_611_DATA 0x31C06001 -#define DDRSS2_PHY_612_DATA 0x07AB0340 +#define DDRSS2_PHY_612_DATA 0x07AB01AB #define DDRSS2_PHY_613_DATA 0x00C0C001 -#define DDRSS2_PHY_614_DATA 0x0E0D0001 +#define DDRSS2_PHY_614_DATA 0x0E0D0101 #define DDRSS2_PHY_615_DATA 0x10001000 #define DDRSS2_PHY_616_DATA 0x0C083E42 #define DDRSS2_PHY_617_DATA 0x0F0C3701 @@ -5927,7 +5956,7 @@ #define DDRSS2_PHY_777_DATA 0x00000000 #define DDRSS2_PHY_778_DATA 0x00000000 #define DDRSS2_PHY_779_DATA 0x01000001 -#define DDRSS2_PHY_780_DATA 0x00000100 +#define DDRSS2_PHY_780_DATA 0x00000200 #define DDRSS2_PHY_781_DATA 0x000800C0 #define DDRSS2_PHY_782_DATA 0x060100CC #define DDRSS2_PHY_783_DATA 0x00030066 @@ -5946,7 +5975,7 @@ #define DDRSS2_PHY_796_DATA 0x2A000000 #define DDRSS2_PHY_797_DATA 0x00000808 #define DDRSS2_PHY_798_DATA 0x0F000000 -#define DDRSS2_PHY_799_DATA 0x00000F0F +#define DDRSS2_PHY_799_DATA 0x00000F08 #define DDRSS2_PHY_800_DATA 0x10400000 #define DDRSS2_PHY_801_DATA 0x0C002006 #define DDRSS2_PHY_802_DATA 0x00000000 @@ -6015,9 +6044,9 @@ #define DDRSS2_PHY_865_DATA 0x00050010 #define DDRSS2_PHY_866_DATA 0x51517041 #define DDRSS2_PHY_867_DATA 0x31C06001 -#define DDRSS2_PHY_868_DATA 0x07AB0340 +#define DDRSS2_PHY_868_DATA 0x07AB01AB #define DDRSS2_PHY_869_DATA 0x00C0C001 -#define DDRSS2_PHY_870_DATA 0x0E0D0001 +#define DDRSS2_PHY_870_DATA 0x0E0D0101 #define DDRSS2_PHY_871_DATA 0x10001000 #define DDRSS2_PHY_872_DATA 0x0C083E42 #define DDRSS2_PHY_873_DATA 0x0F0C3701 @@ -6202,7 +6231,7 @@ #define DDRSS2_PHY_1052_DATA 0x00000033 #define DDRSS2_PHY_1053_DATA 0x00543210 #define DDRSS2_PHY_1054_DATA 0x003F0000 -#define DDRSS2_PHY_1055_DATA 0x000F013F +#define DDRSS2_PHY_1055_DATA 0x000F3F3F #define DDRSS2_PHY_1056_DATA 0x20202003 #define DDRSS2_PHY_1057_DATA 0x00202020 #define DDRSS2_PHY_1058_DATA 0x20008008 @@ -6450,7 +6479,7 @@ #define DDRSS2_PHY_1300_DATA 0x00040101 #define DDRSS2_PHY_1301_DATA 0x0000010F #define DDRSS2_PHY_1302_DATA 0x00000000 -#define DDRSS2_PHY_1303_DATA 0x0000FFFF +#define DDRSS2_PHY_1303_DATA 0x00000064 #define DDRSS2_PHY_1304_DATA 0x00000000 #define DDRSS2_PHY_1305_DATA 0x01010000 #define DDRSS2_PHY_1306_DATA 0x01080402 @@ -6544,7 +6573,7 @@ #define DDRSS2_PHY_1394_DATA 0x00000003 #define DDRSS2_PHY_1395_DATA 0x00000000 #define DDRSS2_PHY_1396_DATA 0x00001142 -#define DDRSS2_PHY_1397_DATA 0x010207AB +#define DDRSS2_PHY_1397_DATA 0x040207AB #define DDRSS2_PHY_1398_DATA 0x01000080 #define DDRSS2_PHY_1399_DATA 0x03900390 #define DDRSS2_PHY_1400_DATA 0x03900390 @@ -6591,7 +6620,7 @@ #define DDRSS3_CTL_17_DATA 0x00000005 #define DDRSS3_CTL_18_DATA 0x000010A9 #define DDRSS3_CTL_19_DATA 0x01010000 -#define DDRSS3_CTL_20_DATA 0x02011001 +#define DDRSS3_CTL_20_DATA 0x01011001 #define DDRSS3_CTL_21_DATA 0x02010000 #define DDRSS3_CTL_22_DATA 0x00020100 #define DDRSS3_CTL_23_DATA 0x0000000B @@ -6606,7 +6635,7 @@ #define DDRSS3_CTL_32_DATA 0x00000000 #define DDRSS3_CTL_33_DATA 0x00000000 #define DDRSS3_CTL_34_DATA 0x040C0000 -#define DDRSS3_CTL_35_DATA 0x12481248 +#define DDRSS3_CTL_35_DATA 0x12501250 #define DDRSS3_CTL_36_DATA 0x00050804 #define DDRSS3_CTL_37_DATA 0x09040008 #define DDRSS3_CTL_38_DATA 0x15000204 @@ -6621,27 +6650,27 @@ #define DDRSS3_CTL_47_DATA 0x1E161110 #define DDRSS3_CTL_48_DATA 0x1000922C #define DDRSS3_CTL_49_DATA 0x02030410 -#define DDRSS3_CTL_50_DATA 0x2C040500 +#define DDRSS3_CTL_50_DATA 0x2C060500 #define DDRSS3_CTL_51_DATA 0x08292C29 #define DDRSS3_CTL_52_DATA 0x14000E0A #define DDRSS3_CTL_53_DATA 0x04010A0A #define DDRSS3_CTL_54_DATA 0x01010004 -#define DDRSS3_CTL_55_DATA 0x04545408 +#define DDRSS3_CTL_55_DATA 0x0454540A #define DDRSS3_CTL_56_DATA 0x04313104 #define DDRSS3_CTL_57_DATA 0x00003131 #define DDRSS3_CTL_58_DATA 0x00010100 #define DDRSS3_CTL_59_DATA 0x03010000 #define DDRSS3_CTL_60_DATA 0x00001508 -#define DDRSS3_CTL_61_DATA 0x00000063 +#define DDRSS3_CTL_61_DATA 0x00000068 #define DDRSS3_CTL_62_DATA 0x0000032B #define DDRSS3_CTL_63_DATA 0x00001035 #define DDRSS3_CTL_64_DATA 0x0000032B #define DDRSS3_CTL_65_DATA 0x00001035 #define DDRSS3_CTL_66_DATA 0x00000005 #define DDRSS3_CTL_67_DATA 0x00050000 -#define DDRSS3_CTL_68_DATA 0x00CB0012 -#define DDRSS3_CTL_69_DATA 0x00CB0408 -#define DDRSS3_CTL_70_DATA 0x00400408 +#define DDRSS3_CTL_68_DATA 0x00CB0005 +#define DDRSS3_CTL_69_DATA 0x00CB0200 +#define DDRSS3_CTL_70_DATA 0x00400200 #define DDRSS3_CTL_71_DATA 0x00120103 #define DDRSS3_CTL_72_DATA 0x00100005 #define DDRSS3_CTL_73_DATA 0x2F080010 @@ -6747,22 +6776,22 @@ #define DDRSS3_CTL_173_DATA 0x00000000 #define DDRSS3_CTL_174_DATA 0x00000000 #define DDRSS3_CTL_175_DATA 0x3FF40084 -#define DDRSS3_CTL_176_DATA 0x33003FF4 -#define DDRSS3_CTL_177_DATA 0x00003333 -#define DDRSS3_CTL_178_DATA 0x35000000 +#define DDRSS3_CTL_176_DATA 0xF3003FF4 +#define DDRSS3_CTL_177_DATA 0x0000F3F3 +#define DDRSS3_CTL_178_DATA 0x35350000 #define DDRSS3_CTL_179_DATA 0x27270035 #define DDRSS3_CTL_180_DATA 0x0F0F0000 #define DDRSS3_CTL_181_DATA 0x16000000 #define DDRSS3_CTL_182_DATA 0x00841616 #define DDRSS3_CTL_183_DATA 0x3FF43FF4 -#define DDRSS3_CTL_184_DATA 0x33333300 +#define DDRSS3_CTL_184_DATA 0xF3F3F300 #define DDRSS3_CTL_185_DATA 0x00000000 -#define DDRSS3_CTL_186_DATA 0x00353500 +#define DDRSS3_CTL_186_DATA 0x00353535 #define DDRSS3_CTL_187_DATA 0x00002727 #define DDRSS3_CTL_188_DATA 0x00000F0F #define DDRSS3_CTL_189_DATA 0x16161600 #define DDRSS3_CTL_190_DATA 0x00000020 -#define DDRSS3_CTL_191_DATA 0x00000000 +#define DDRSS3_CTL_191_DATA 0x01000000 #define DDRSS3_CTL_192_DATA 0x00000001 #define DDRSS3_CTL_193_DATA 0x00000000 #define DDRSS3_CTL_194_DATA 0x01000000 @@ -6862,14 +6891,14 @@ #define DDRSS3_CTL_288_DATA 0x00000000 #define DDRSS3_CTL_289_DATA 0x00000000 #define DDRSS3_CTL_290_DATA 0x03030300 -#define DDRSS3_CTL_291_DATA 0x00000001 +#define DDRSS3_CTL_291_DATA 0x00010101 #define DDRSS3_CTL_292_DATA 0x00000000 #define DDRSS3_CTL_293_DATA 0x00000000 #define DDRSS3_CTL_294_DATA 0x00000000 #define DDRSS3_CTL_295_DATA 0x00000000 #define DDRSS3_CTL_296_DATA 0x00000000 -#define DDRSS3_CTL_297_DATA 0x00000000 -#define DDRSS3_CTL_298_DATA 0x00000000 +#define DDRSS3_CTL_297_DATA 0xFFFFFFFF +#define DDRSS3_CTL_298_DATA 0x00000FFF #define DDRSS3_CTL_299_DATA 0x00000000 #define DDRSS3_CTL_300_DATA 0x00000000 #define DDRSS3_CTL_301_DATA 0x00000000 @@ -6890,7 +6919,7 @@ #define DDRSS3_CTL_316_DATA 0x01010001 #define DDRSS3_CTL_317_DATA 0x00010101 #define DDRSS3_CTL_318_DATA 0x050A0A03 -#define DDRSS3_CTL_319_DATA 0x10081F1F +#define DDRSS3_CTL_319_DATA 0x10082323 #define DDRSS3_CTL_320_DATA 0x00090310 #define DDRSS3_CTL_321_DATA 0x0B0C030F #define DDRSS3_CTL_322_DATA 0x0B0C0306 @@ -6965,7 +6994,7 @@ #define DDRSS3_CTL_391_DATA 0x00000200 #define DDRSS3_CTL_392_DATA 0x00000200 #define DDRSS3_CTL_393_DATA 0x00000200 -#define DDRSS3_CTL_394_DATA 0x00000252 +#define DDRSS3_CTL_394_DATA 0x00000270 #define DDRSS3_CTL_395_DATA 0x000007BC #define DDRSS3_CTL_396_DATA 0x00000204 #define DDRSS3_CTL_397_DATA 0x0000206A @@ -6975,7 +7004,7 @@ #define DDRSS3_CTL_401_DATA 0x00000200 #define DDRSS3_CTL_402_DATA 0x0000613E #define DDRSS3_CTL_403_DATA 0x00014424 -#define DDRSS3_CTL_404_DATA 0x00000E15 +#define DDRSS3_CTL_404_DATA 0x00000E19 #define DDRSS3_CTL_405_DATA 0x0000206A #define DDRSS3_CTL_406_DATA 0x00000200 #define DDRSS3_CTL_407_DATA 0x00000200 @@ -6983,7 +7012,7 @@ #define DDRSS3_CTL_409_DATA 0x00000200 #define DDRSS3_CTL_410_DATA 0x0000613E #define DDRSS3_CTL_411_DATA 0x00014424 -#define DDRSS3_CTL_412_DATA 0x02020E15 +#define DDRSS3_CTL_412_DATA 0x02020E19 #define DDRSS3_CTL_413_DATA 0x03030202 #define DDRSS3_CTL_414_DATA 0x00000022 #define DDRSS3_CTL_415_DATA 0x00000000 @@ -7000,7 +7029,7 @@ #define DDRSS3_CTL_426_DATA 0x00000000 #define DDRSS3_CTL_427_DATA 0x02000000 #define DDRSS3_CTL_428_DATA 0x01000404 -#define DDRSS3_CTL_429_DATA 0x0B1E0B1E +#define DDRSS3_CTL_429_DATA 0x0B220B22 #define DDRSS3_CTL_430_DATA 0x00000105 #define DDRSS3_CTL_431_DATA 0x00010101 #define DDRSS3_CTL_432_DATA 0x00010101 @@ -7043,8 +7072,8 @@ #define DDRSS3_PI_09_DATA 0x00000000 #define DDRSS3_PI_10_DATA 0x00000000 #define DDRSS3_PI_11_DATA 0x00000000 -#define DDRSS3_PI_12_DATA 0x00000007 -#define DDRSS3_PI_13_DATA 0x00010002 +#define DDRSS3_PI_12_DATA 0x00000003 +#define DDRSS3_PI_13_DATA 0x00010001 #define DDRSS3_PI_14_DATA 0x0800000F #define DDRSS3_PI_15_DATA 0x00000103 #define DDRSS3_PI_16_DATA 0x00000005 @@ -7092,18 +7121,18 @@ #define DDRSS3_PI_58_DATA 0x00000000 #define DDRSS3_PI_59_DATA 0x00000000 #define DDRSS3_PI_60_DATA 0x0A0A140A -#define DDRSS3_PI_61_DATA 0x10020101 +#define DDRSS3_PI_61_DATA 0x10020201 #define DDRSS3_PI_62_DATA 0x00020805 #define DDRSS3_PI_63_DATA 0x01000404 #define DDRSS3_PI_64_DATA 0x00000000 #define DDRSS3_PI_65_DATA 0x00000000 #define DDRSS3_PI_66_DATA 0x00000100 -#define DDRSS3_PI_67_DATA 0x0001010F +#define DDRSS3_PI_67_DATA 0x0002020F #define DDRSS3_PI_68_DATA 0x00340000 #define DDRSS3_PI_69_DATA 0x00000000 #define DDRSS3_PI_70_DATA 0x00000000 #define DDRSS3_PI_71_DATA 0x0000FFFF -#define DDRSS3_PI_72_DATA 0x00000000 +#define DDRSS3_PI_72_DATA 0x01000000 #define DDRSS3_PI_73_DATA 0x00080000 #define DDRSS3_PI_74_DATA 0x02000200 #define DDRSS3_PI_75_DATA 0x01000100 @@ -7192,37 +7221,37 @@ #define DDRSS3_PI_158_DATA 0x00000000 #define DDRSS3_PI_159_DATA 0x00000401 #define DDRSS3_PI_160_DATA 0x00000000 -#define DDRSS3_PI_161_DATA 0x00010000 -#define DDRSS3_PI_162_DATA 0x00000000 -#define DDRSS3_PI_163_DATA 0x2B2B0200 +#define DDRSS3_PI_161_DATA 0x05010000 +#define DDRSS3_PI_162_DATA 0x00000001 +#define DDRSS3_PI_163_DATA 0x2B2B0201 #define DDRSS3_PI_164_DATA 0x00000034 -#define DDRSS3_PI_165_DATA 0x00000064 -#define DDRSS3_PI_166_DATA 0x00020064 +#define DDRSS3_PI_165_DATA 0x00000068 +#define DDRSS3_PI_166_DATA 0x00020068 #define DDRSS3_PI_167_DATA 0x02000200 -#define DDRSS3_PI_168_DATA 0x48120C04 -#define DDRSS3_PI_169_DATA 0x00154812 -#define DDRSS3_PI_170_DATA 0x00000063 +#define DDRSS3_PI_168_DATA 0x50120C04 +#define DDRSS3_PI_169_DATA 0x00155012 +#define DDRSS3_PI_170_DATA 0x00000068 #define DDRSS3_PI_171_DATA 0x0000032B #define DDRSS3_PI_172_DATA 0x00001035 #define DDRSS3_PI_173_DATA 0x0000032B #define DDRSS3_PI_174_DATA 0x04001035 #define DDRSS3_PI_175_DATA 0x01010404 -#define DDRSS3_PI_176_DATA 0x00001501 +#define DDRSS3_PI_176_DATA 0x00001500 #define DDRSS3_PI_177_DATA 0x00150015 #define DDRSS3_PI_178_DATA 0x01000100 #define DDRSS3_PI_179_DATA 0x00000100 #define DDRSS3_PI_180_DATA 0x00000000 #define DDRSS3_PI_181_DATA 0x01010101 -#define DDRSS3_PI_182_DATA 0x00000101 +#define DDRSS3_PI_182_DATA 0x00000000 #define DDRSS3_PI_183_DATA 0x00000000 #define DDRSS3_PI_184_DATA 0x00000000 -#define DDRSS3_PI_185_DATA 0x15040000 -#define DDRSS3_PI_186_DATA 0x0E0E0215 +#define DDRSS3_PI_185_DATA 0x19040000 +#define DDRSS3_PI_186_DATA 0x0E0E0219 #define DDRSS3_PI_187_DATA 0x00040402 #define DDRSS3_PI_188_DATA 0x000D0035 #define DDRSS3_PI_189_DATA 0x00218049 #define DDRSS3_PI_190_DATA 0x00218049 -#define DDRSS3_PI_191_DATA 0x01010101 +#define DDRSS3_PI_191_DATA 0x01000101 #define DDRSS3_PI_192_DATA 0x0004000E #define DDRSS3_PI_193_DATA 0x00040216 #define DDRSS3_PI_194_DATA 0x01000216 @@ -7230,8 +7259,8 @@ #define DDRSS3_PI_196_DATA 0x02170100 #define DDRSS3_PI_197_DATA 0x01000217 #define DDRSS3_PI_198_DATA 0x02170217 -#define DDRSS3_PI_199_DATA 0x32103200 -#define DDRSS3_PI_200_DATA 0x01013210 +#define DDRSS3_PI_199_DATA 0x2F1B3200 +#define DDRSS3_PI_200_DATA 0x01012F1B #define DDRSS3_PI_201_DATA 0x0A070601 #define DDRSS3_PI_202_DATA 0x1F130A0D #define DDRSS3_PI_203_DATA 0x1F130A14 @@ -7243,13 +7272,13 @@ #define DDRSS3_PI_209_DATA 0x00240216 #define DDRSS3_PI_210_DATA 0x00110216 #define DDRSS3_PI_211_DATA 0x32000056 -#define DDRSS3_PI_212_DATA 0x00000301 -#define DDRSS3_PI_213_DATA 0x005B0036 +#define DDRSS3_PI_212_DATA 0x00000101 +#define DDRSS3_PI_213_DATA 0x005F0036 #define DDRSS3_PI_214_DATA 0x03013212 #define DDRSS3_PI_215_DATA 0x00003600 -#define DDRSS3_PI_216_DATA 0x3212005B -#define DDRSS3_PI_217_DATA 0x09000301 -#define DDRSS3_PI_218_DATA 0x04010504 +#define DDRSS3_PI_216_DATA 0x3212005F +#define DDRSS3_PI_217_DATA 0x09000001 +#define DDRSS3_PI_218_DATA 0x06010504 #define DDRSS3_PI_219_DATA 0x04000364 #define DDRSS3_PI_220_DATA 0x0A032001 #define DDRSS3_PI_221_DATA 0x2C31110A @@ -7306,29 +7335,29 @@ #define DDRSS3_PI_272_DATA 0x00080804 #define DDRSS3_PI_273_DATA 0x00000000 #define DDRSS3_PI_274_DATA 0x00000000 -#define DDRSS3_PI_275_DATA 0x00330084 +#define DDRSS3_PI_275_DATA 0x35F30084 #define DDRSS3_PI_276_DATA 0x00160000 -#define DDRSS3_PI_277_DATA 0x35333FF4 +#define DDRSS3_PI_277_DATA 0x35F33FF4 #define DDRSS3_PI_278_DATA 0x00160F27 -#define DDRSS3_PI_279_DATA 0x35333FF4 +#define DDRSS3_PI_279_DATA 0x35F33FF4 #define DDRSS3_PI_280_DATA 0x00160F27 -#define DDRSS3_PI_281_DATA 0x00330084 +#define DDRSS3_PI_281_DATA 0x35F30084 #define DDRSS3_PI_282_DATA 0x00160000 -#define DDRSS3_PI_283_DATA 0x35333FF4 +#define DDRSS3_PI_283_DATA 0x35F33FF4 #define DDRSS3_PI_284_DATA 0x00160F27 -#define DDRSS3_PI_285_DATA 0x35333FF4 +#define DDRSS3_PI_285_DATA 0x35F33FF4 #define DDRSS3_PI_286_DATA 0x00160F27 -#define DDRSS3_PI_287_DATA 0x00330084 +#define DDRSS3_PI_287_DATA 0x35F30084 #define DDRSS3_PI_288_DATA 0x00160000 -#define DDRSS3_PI_289_DATA 0x35333FF4 +#define DDRSS3_PI_289_DATA 0x35F33FF4 #define DDRSS3_PI_290_DATA 0x00160F27 -#define DDRSS3_PI_291_DATA 0x35333FF4 +#define DDRSS3_PI_291_DATA 0x35F33FF4 #define DDRSS3_PI_292_DATA 0x00160F27 -#define DDRSS3_PI_293_DATA 0x00330084 +#define DDRSS3_PI_293_DATA 0x35F30084 #define DDRSS3_PI_294_DATA 0x00160000 -#define DDRSS3_PI_295_DATA 0x35333FF4 +#define DDRSS3_PI_295_DATA 0x35F33FF4 #define DDRSS3_PI_296_DATA 0x00160F27 -#define DDRSS3_PI_297_DATA 0x35333FF4 +#define DDRSS3_PI_297_DATA 0x35F33FF4 #define DDRSS3_PI_298_DATA 0x00160F27 #define DDRSS3_PI_299_DATA 0x00000000 @@ -7344,7 +7373,7 @@ #define DDRSS3_PHY_09_DATA 0x00000000 #define DDRSS3_PHY_10_DATA 0x00000000 #define DDRSS3_PHY_11_DATA 0x01000001 -#define DDRSS3_PHY_12_DATA 0x00000100 +#define DDRSS3_PHY_12_DATA 0x00000200 #define DDRSS3_PHY_13_DATA 0x000800C0 #define DDRSS3_PHY_14_DATA 0x060100CC #define DDRSS3_PHY_15_DATA 0x00030066 @@ -7363,7 +7392,7 @@ #define DDRSS3_PHY_28_DATA 0x2A000000 #define DDRSS3_PHY_29_DATA 0x00000808 #define DDRSS3_PHY_30_DATA 0x0F000000 -#define DDRSS3_PHY_31_DATA 0x00000F0F +#define DDRSS3_PHY_31_DATA 0x00000F08 #define DDRSS3_PHY_32_DATA 0x10400000 #define DDRSS3_PHY_33_DATA 0x0C002006 #define DDRSS3_PHY_34_DATA 0x00000000 @@ -7432,9 +7461,9 @@ #define DDRSS3_PHY_97_DATA 0x00050010 #define DDRSS3_PHY_98_DATA 0x51517041 #define DDRSS3_PHY_99_DATA 0x31C06001 -#define DDRSS3_PHY_100_DATA 0x07AB0340 +#define DDRSS3_PHY_100_DATA 0x07AB01AB #define DDRSS3_PHY_101_DATA 0x00C0C001 -#define DDRSS3_PHY_102_DATA 0x0E0D0001 +#define DDRSS3_PHY_102_DATA 0x0E0D0101 #define DDRSS3_PHY_103_DATA 0x10001000 #define DDRSS3_PHY_104_DATA 0x0C083E42 #define DDRSS3_PHY_105_DATA 0x0F0C3701 @@ -7600,7 +7629,7 @@ #define DDRSS3_PHY_265_DATA 0x00000000 #define DDRSS3_PHY_266_DATA 0x00000000 #define DDRSS3_PHY_267_DATA 0x01000001 -#define DDRSS3_PHY_268_DATA 0x00000100 +#define DDRSS3_PHY_268_DATA 0x00000200 #define DDRSS3_PHY_269_DATA 0x000800C0 #define DDRSS3_PHY_270_DATA 0x060100CC #define DDRSS3_PHY_271_DATA 0x00030066 @@ -7619,7 +7648,7 @@ #define DDRSS3_PHY_284_DATA 0x2A000000 #define DDRSS3_PHY_285_DATA 0x00000808 #define DDRSS3_PHY_286_DATA 0x0F000000 -#define DDRSS3_PHY_287_DATA 0x00000F0F +#define DDRSS3_PHY_287_DATA 0x00000F08 #define DDRSS3_PHY_288_DATA 0x10400000 #define DDRSS3_PHY_289_DATA 0x0C002006 #define DDRSS3_PHY_290_DATA 0x00000000 @@ -7688,9 +7717,9 @@ #define DDRSS3_PHY_353_DATA 0x00050010 #define DDRSS3_PHY_354_DATA 0x51517041 #define DDRSS3_PHY_355_DATA 0x31C06001 -#define DDRSS3_PHY_356_DATA 0x07AB0340 +#define DDRSS3_PHY_356_DATA 0x07AB01AB #define DDRSS3_PHY_357_DATA 0x00C0C001 -#define DDRSS3_PHY_358_DATA 0x0E0D0001 +#define DDRSS3_PHY_358_DATA 0x0E0D0101 #define DDRSS3_PHY_359_DATA 0x10001000 #define DDRSS3_PHY_360_DATA 0x0C083E42 #define DDRSS3_PHY_361_DATA 0x0F0C3701 @@ -7856,7 +7885,7 @@ #define DDRSS3_PHY_521_DATA 0x00000000 #define DDRSS3_PHY_522_DATA 0x00000000 #define DDRSS3_PHY_523_DATA 0x01000001 -#define DDRSS3_PHY_524_DATA 0x00000100 +#define DDRSS3_PHY_524_DATA 0x00000200 #define DDRSS3_PHY_525_DATA 0x000800C0 #define DDRSS3_PHY_526_DATA 0x060100CC #define DDRSS3_PHY_527_DATA 0x00030066 @@ -7875,7 +7904,7 @@ #define DDRSS3_PHY_540_DATA 0x2A000000 #define DDRSS3_PHY_541_DATA 0x00000808 #define DDRSS3_PHY_542_DATA 0x0F000000 -#define DDRSS3_PHY_543_DATA 0x00000F0F +#define DDRSS3_PHY_543_DATA 0x00000F08 #define DDRSS3_PHY_544_DATA 0x10400000 #define DDRSS3_PHY_545_DATA 0x0C002006 #define DDRSS3_PHY_546_DATA 0x00000000 @@ -7944,9 +7973,9 @@ #define DDRSS3_PHY_609_DATA 0x00050010 #define DDRSS3_PHY_610_DATA 0x51517041 #define DDRSS3_PHY_611_DATA 0x31C06001 -#define DDRSS3_PHY_612_DATA 0x07AB0340 +#define DDRSS3_PHY_612_DATA 0x07AB01AB #define DDRSS3_PHY_613_DATA 0x00C0C001 -#define DDRSS3_PHY_614_DATA 0x0E0D0001 +#define DDRSS3_PHY_614_DATA 0x0E0D0101 #define DDRSS3_PHY_615_DATA 0x10001000 #define DDRSS3_PHY_616_DATA 0x0C083E42 #define DDRSS3_PHY_617_DATA 0x0F0C3701 @@ -8112,7 +8141,7 @@ #define DDRSS3_PHY_777_DATA 0x00000000 #define DDRSS3_PHY_778_DATA 0x00000000 #define DDRSS3_PHY_779_DATA 0x01000001 -#define DDRSS3_PHY_780_DATA 0x00000100 +#define DDRSS3_PHY_780_DATA 0x00000200 #define DDRSS3_PHY_781_DATA 0x000800C0 #define DDRSS3_PHY_782_DATA 0x060100CC #define DDRSS3_PHY_783_DATA 0x00030066 @@ -8131,7 +8160,7 @@ #define DDRSS3_PHY_796_DATA 0x2A000000 #define DDRSS3_PHY_797_DATA 0x00000808 #define DDRSS3_PHY_798_DATA 0x0F000000 -#define DDRSS3_PHY_799_DATA 0x00000F0F +#define DDRSS3_PHY_799_DATA 0x00000F08 #define DDRSS3_PHY_800_DATA 0x10400000 #define DDRSS3_PHY_801_DATA 0x0C002006 #define DDRSS3_PHY_802_DATA 0x00000000 @@ -8200,9 +8229,9 @@ #define DDRSS3_PHY_865_DATA 0x00050010 #define DDRSS3_PHY_866_DATA 0x51517041 #define DDRSS3_PHY_867_DATA 0x31C06001 -#define DDRSS3_PHY_868_DATA 0x07AB0340 +#define DDRSS3_PHY_868_DATA 0x07AB01AB #define DDRSS3_PHY_869_DATA 0x00C0C001 -#define DDRSS3_PHY_870_DATA 0x0E0D0001 +#define DDRSS3_PHY_870_DATA 0x0E0D0101 #define DDRSS3_PHY_871_DATA 0x10001000 #define DDRSS3_PHY_872_DATA 0x0C083E42 #define DDRSS3_PHY_873_DATA 0x0F0C3701 @@ -8387,7 +8416,7 @@ #define DDRSS3_PHY_1052_DATA 0x00000033 #define DDRSS3_PHY_1053_DATA 0x00543210 #define DDRSS3_PHY_1054_DATA 0x003F0000 -#define DDRSS3_PHY_1055_DATA 0x000F013F +#define DDRSS3_PHY_1055_DATA 0x000F3F3F #define DDRSS3_PHY_1056_DATA 0x20202003 #define DDRSS3_PHY_1057_DATA 0x00202020 #define DDRSS3_PHY_1058_DATA 0x20008008 @@ -8635,7 +8664,7 @@ #define DDRSS3_PHY_1300_DATA 0x00040101 #define DDRSS3_PHY_1301_DATA 0x0000010F #define DDRSS3_PHY_1302_DATA 0x00000000 -#define DDRSS3_PHY_1303_DATA 0x0000FFFF +#define DDRSS3_PHY_1303_DATA 0x00000064 #define DDRSS3_PHY_1304_DATA 0x00000000 #define DDRSS3_PHY_1305_DATA 0x01010000 #define DDRSS3_PHY_1306_DATA 0x01080402 @@ -8729,7 +8758,7 @@ #define DDRSS3_PHY_1394_DATA 0x00000003 #define DDRSS3_PHY_1395_DATA 0x00000000 #define DDRSS3_PHY_1396_DATA 0x00001142 -#define DDRSS3_PHY_1397_DATA 0x010207AB +#define DDRSS3_PHY_1397_DATA 0x040207AB #define DDRSS3_PHY_1398_DATA 0x01000080 #define DDRSS3_PHY_1399_DATA 0x03900390 #define DDRSS3_PHY_1400_DATA 0x03900390 diff --git a/arch/arm/dts/lemans-evk-u-boot.dtsi b/arch/arm/dts/lemans-evk-u-boot.dtsi new file mode 100644 index 00000000000..cdd3d32f61a --- /dev/null +++ b/arch/arm/dts/lemans-evk-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/ { + /* Will be removed when bootloader updates later */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x3ee00000>, + <0x0 0xc0000000 0x0 0x0fd00000>, + <0xD 0x00000000 0x2 0x54100000>, + <0xA 0x80000000 0x1 0x80000000>, + <0x9 0x00000000 0x1 0x80000000>, + <0x1 0x00000000 0x3 0x00000000>, + <0x0 0xd0000000 0x0 0x01900000>, + <0x0 0xd3500000 0x0 0x2cb00000>; + }; +}; diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts index e74d0956194..b5d9caa73e6 100644 --- a/arch/arm/dts/ls1021a-tsn.dts +++ b/arch/arm/dts/ls1021a-tsn.dts @@ -173,7 +173,7 @@ status = "okay"; flash@0 { - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; }; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 4f65ee765e3..005a40eff23 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -205,7 +205,7 @@ clocks = <&sysclk>; }; - dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -218,7 +218,7 @@ status = "disabled"; }; - dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,vf610-dspi"; #address-cells = <1>; #size-cells = <0>; @@ -231,7 +231,7 @@ status = "disabled"; }; - qspi: quadspi@1550000 { + qspi: spi@1550000 { compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/mba6ulx-u-boot.dtsi b/arch/arm/dts/mba6ulx-u-boot.dtsi new file mode 100644 index 00000000000..73bed319ef2 --- /dev/null +++ b/arch/arm/dts/mba6ulx-u-boot.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +&uart1 { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +®_mba6ul_3v3 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi index d246be63293..c965b00bb5c 100644 --- a/arch/arm/dts/mt8189.dtsi +++ b/arch/arm/dts/mt8189.dtsi @@ -7,6 +7,8 @@ #include <dt-bindings/clock/mediatek,mt8189-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/ti-syscon.h> / { compatible = "mediatek,mt8189"; @@ -179,6 +181,96 @@ status = "disabled"; }; + nor_flash: spi@11018000 { + compatible = "mediatek,mt8189-nor","mediatek,mt8186-nor"; + reg = <0 0x11018000 0 0x1000>; + clocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>, + <&pericfg_ao_clk CLK_PERAO_SFLASH>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_F>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_H>, + <&pericfg_ao_clk CLK_PERAO_SFLASH_P>; + clock-names = "spi", "sf", "axi_f", "axi_h", "axi_p"; + assigned-clocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D8>; + interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + xhci0: usb@11200000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 207 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB0_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB0_FRMCNT>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x214 110>; + status = "disabled"; + }; + + xhci1: usb@11210000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11210000 0 0x1000>, + <0 0x11213e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 203 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port1 PHY_TYPE_USB2>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB1_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB1_FRMCNT>; + clock-names = "sys_ck", "ref_ck","mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x21c 110>; + status = "disabled"; + }; + + xhci2: usb@11220000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11220000 0 0x1000>, + <0 0x11223e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 193 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port2 PHY_TYPE_USB2>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB2_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB2_FRMCNT>; + clock-names = "sys_ck", "ref_ck","mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x27c 110>; + status = "disabled"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8189-mmc"; reg = <0 0x11230000 0 0x10000>, @@ -203,6 +295,55 @@ status = "disabled"; }; + xhci3: usb@11260000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11260000 0 0x2e00>, + <0 0x11263e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 188 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port3 PHY_TYPE_USB2>, + <&u3port3 PHY_TYPE_USB3>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB3_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB3_FRMCNT>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x284 110>; + status = "disabled"; + }; + + xhci4: usb@11270000 { + compatible = "mediatek,mt8189-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11270000 0 0x1000>, + <0 0x11273e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host","wakeup"; + phys = <&u2port4 PHY_TYPE_USB2>; + clocks = <&pericfg_ao_clk CLK_PERAO_SSUSB4_SYS>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_REF>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_H>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_F>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_XHCI>, + <&pericfg_ao_clk CLK_PERAO_SSUSB4_FRMCNT>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck", "frmcnt_ck"; + #address-cells = <1>; + #size-cells = <0>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg_ao_clk 0x28c 110>; + status = "disabled"; + }; + clock-controller@1000c000 { compatible = "mediatek,mt8189-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; @@ -240,6 +381,83 @@ #reset-cells = <1>; }; + eth: ethernet@1101a000 { + compatible = "mediatek,mt8189-gmac", "snps,dwmac-5.10a"; + reg = <0 0x1101a000 0 0x4000>; + interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + clock-names = "mac_main", + "ptp_ref"; + clocks = <&topckgen_clk CLK_TOP_ETH_250M_SEL>, + <&topckgen_clk CLK_TOP_ETH_62P4M_PTP_SEL>; + assigned-clocks = <&topckgen_clk CLK_TOP_ETH_250M_SEL>, + <&topckgen_clk CLK_TOP_ETH_62P4M_PTP_SEL>, + <&topckgen_clk CLK_TOP_ETH_50M_RMII_SEL>; + assigned-clock-parents = <&topckgen_clk CLK_TOP_ETHPLL_D2>, + <&topckgen_clk CLK_TOP_ETHPLL_D8>, + <&topckgen_clk CLK_TOP_ETHPLL_D10>; + mediatek,pericfg = <&pericfg_ao_clk>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + clk-csr = <4>; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr-osr-lmt = <0x7>; + snps,rd-osr-lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + queue3 { + snps,weight = <0x13>; + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; + }; + topckgen_clk: clock-controller@10000000 { compatible = "mediatek,mt8189-topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; @@ -286,6 +504,207 @@ #interrupt-cells = <2>; }; + ufshci: ufshci@112b0000 { + compatible = "mediatek,mt8183-ufshci"; + reg = <0 0x112b0000 0 0x2300>; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&topckgen_clk CLK_TOP_U_SEL>, + <&clk26m>, + <&topckgen_clk CLK_TOP_MSDCPLL_D2>, + <&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>, + <&topckgen_clk CLK_TOP_U_MBIST_SEL>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_UNIPRO_SYS>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_SAP_CFG>, + <&ufscfg_ao_reg_clk CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_UFS>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_AES>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AHB>, + <&ufscfg_pdn_reg_clk CLK_UFSCFG_REG_UFSHCI_U_AXI>; + + clock-names = "ufs_sel", + "ufs_sel_min_src", + "ufs_sel_max_src", + "ufs_fde", + "ufs_mbist", + "unipro_tx_sym", + "unipro_rx_sym0", + "unipro_rx_sym1", + "unipro_sys", + "unipro_phy_sap", + "phy_top_ahb_s_bus", + "ufshci_ufs", + "ufshci_aes", + "ufshci_ufs_ahb", + "ufshci_aes_axi"; + + freq-table-hz = <26000000 208000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + vcc-supply = <&mt6359_vemc_1_ldo_reg>; + vccq-supply = <&mt6359_vio18_ldo_reg>; + vccq2-supply = <&mt6359_vufs_ldo_reg>; + + resets = <&ufscfgpdn_rst 0>, + <&ufscfgpdn_rst 1>, + <&ufscfgpdn_rst 2>; + + reset-names = "unipro_rst", + "crypto_rst", + "hci_rst"; + + mediatek,ufs-disable-mcq; + mediatek,ufs-rtff-mtcmos; + mediatek,ufs-broken-vcc; + + status = "disabled"; + }; + + u3phy3: t-phy@11b00000 { + compatible = "mediatek,mt8189-tphy", + "mediatek,generic-tphy-v2"; + reg = <0 0x11b00000 0 0x700>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port3: usb-phy@11b00000 { + reg = <0 0x11b00000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P3_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port3: usb-phy@11b00700 { + reg = <0 0x11b00700 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P3_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u2phy4: xs-phy@11b10000 { + compatible = "mediatek,mt8189-xsphy", "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port4: usb-phy@11b10000 { + reg = <0 0x11b10000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P4_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u3phy0: xs-phy@11e80000 { + compatible = "mediatek,mt8189-xsphy", "mediatek,xsphy"; + reg = <0 0x11e83000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port0: usb-phy@11e80000 { + reg = <0 0x11e80000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P0_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@11e83000 { + reg = <0 0x11e83400 0 0x500>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P0_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u2phy1: xs-phy@11e90000 { + compatible = "mediatek,mt8189-xsphy", "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port1: usb-phy@11e90000 { + reg = <0 0x11e90000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P1_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u2phy2: xs-phy@11ef0000 { + compatible = "mediatek,mt8189-xsphy", "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + u2port2: usb-phy@11ef0000 { + reg = <0 0x11ef0000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_RF_P2_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + ufscfg_ao_reg_clk: syscon@112b8000 { + compatible = "mediatek,mt8189-ufscfg-ao", "syscon", "simple-mfd"; + reg = <0 0x112b8000 0 0x1000>; + #clock-cells = <1>; + + ufscfgao_rst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + /* ufs mphy reset */ + /* 8: mphy */ + 0x48 8 0x4c 8 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; + + ufscfg_pdn_reg_clk: syscon@112bb000 { + compatible = "mediatek,mt8189-ufscfg-pdn", "syscon", "simple-mfd"; + reg = <0 0x112bb000 0 0x1000>; + #clock-cells = <1>; + + ufscfgpdn_rst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + + ti,reset-bits = < + /* ufs ufschi/crypto/unipro reset */ + /* 0: unipro */ + 0x48 0 0x4c 0 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + /* 1: ufs-crypto */ + 0x48 1 0x4c 1 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + /* 2: ufshci */ + 0x48 2 0x4c 2 0 0 + (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + }; + pwrap: pwrap@1cc04000 { compatible = "mediatek,mt8189-pwrap", "mediatek,mt8195-pwrap", "syscon"; reg = <0 0x1cc04000 0 0x1000>; diff --git a/arch/arm/dts/mt8371-genio-common-ufs.dtso b/arch/arm/dts/mt8371-genio-common-ufs.dtso new file mode 100644 index 00000000000..b75fdafcf9b --- /dev/null +++ b/arch/arm/dts/mt8371-genio-common-ufs.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 MediaTek Inc. + * + * Adjusts for when boot DIP switches/jumpers on EVK are set for UFS boot + * instead of eMMC. + */ + +/dts-v1/; +/plugin/; + +&ufshci { + status = "okay"; +}; + +&mmc0 { + status = "disabled"; +}; diff --git a/arch/arm/dts/mt8371-genio-common.dtsi b/arch/arm/dts/mt8371-genio-common.dtsi index 58322193aef..123133b0eb8 100644 --- a/arch/arm/dts/mt8371-genio-common.dtsi +++ b/arch/arm/dts/mt8371-genio-common.dtsi @@ -19,6 +19,51 @@ stdout-path = "serial0:921600n8"; }; + usb_p0_vbus: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "p0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 82 0>; + enable-active-high; + }; + + usb_p1_vbus: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "p1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 0>; + enable-active-high; + }; + + usb_p2_vbus: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "p2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 85 0>; + enable-active-high; + }; + + usb_p3_vbus: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "p3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 86 0>; + enable-active-high; + }; + + usb_p4_vbus: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "p4_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 87 0>; + enable-active-high; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -117,6 +162,21 @@ regulator-always-on; }; +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &pio { mmc0_default_pins: mmc0-default-pins { pins-clk { @@ -229,6 +289,22 @@ }; }; + nor_pins: nor-pins { + pins-ck-io { + pinmux = <PINMUX_GPIO150__FUNC_SPINOR_CK>, + <PINMUX_GPIO152__FUNC_SPINOR_IO0>, + <PINMUX_GPIO153__FUNC_SPINOR_IO1>; + drive-strength = <8>; + bias-pull-down; + }; + + pins-cs { + pinmux = <PINMUX_GPIO151__FUNC_SPINOR_CS>; + drive-strength = <8>; + bias-pull-up; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = <PINMUX_GPIO31__FUNC_UTXD0>, @@ -236,8 +312,116 @@ bias-pull-up; }; }; + + eth_default_pins: eth-default-pins { + txd-pins { + pinmux = <PINMUX_GPIO119__FUNC_GBE_TXD3>, + <PINMUX_GPIO120__FUNC_GBE_TXD2>, + <PINMUX_GPIO121__FUNC_GBE_TXD1>, + <PINMUX_GPIO122__FUNC_GBE_TXD0>; + drive-strength = <MTK_DRIVE_8mA>; + }; + cc-pins { + pinmux = <PINMUX_GPIO127__FUNC_GBE_TXC>, + <PINMUX_GPIO130__FUNC_GBE_TXEN>, + <PINMUX_GPIO129__FUNC_GBE_RXDV>, + <PINMUX_GPIO128__FUNC_GBE_RXC>; + drive-strength = <MTK_DRIVE_8mA>; + }; + rxd-pins { + pinmux = <PINMUX_GPIO123__FUNC_GBE_RXD3>, + <PINMUX_GPIO124__FUNC_GBE_RXD2>, + <PINMUX_GPIO125__FUNC_GBE_RXD1>, + <PINMUX_GPIO126__FUNC_GBE_RXD0>; + drive-strength = <MTK_DRIVE_8mA>; + }; + mdio-pins { + pinmux = <PINMUX_GPIO131__FUNC_GBE_MDC>, + <PINMUX_GPIO132__FUNC_GBE_MDIO>; + drive-strength = <MTK_DRIVE_8mA>; + input-enable; + }; + power-pins { + pinmux = <PINMUX_GPIO133__FUNC_GPIO133>, + <PINMUX_GPIO134__FUNC_GPIO134>; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + txd-pins { + pinmux = <PINMUX_GPIO119__FUNC_GPIO119>, + <PINMUX_GPIO120__FUNC_GPIO120>, + <PINMUX_GPIO121__FUNC_GPIO121>, + <PINMUX_GPIO122__FUNC_GPIO122>; + }; + cc-pins { + pinmux = <PINMUX_GPIO127__FUNC_GPIO127>, + <PINMUX_GPIO130__FUNC_GPIO130>, + <PINMUX_GPIO129__FUNC_GPIO129>, + <PINMUX_GPIO128__FUNC_GPIO128>; + }; + rxd-pins { + pinmux = <PINMUX_GPIO123__FUNC_GPIO123>, + <PINMUX_GPIO124__FUNC_GPIO124>, + <PINMUX_GPIO125__FUNC_GPIO125>, + <PINMUX_GPIO126__FUNC_GPIO126>; + }; + mdio-pins { + pinmux = <PINMUX_GPIO131__FUNC_GPIO131>, + <PINMUX_GPIO132__FUNC_GPIO132>; + input-disable; + bias-disable; + }; + }; }; &pmic { interrupts-extended = <&pio 194 IRQ_TYPE_LEVEL_HIGH>; }; + +&xhci0{ + vbus-supply = <&usb_p0_vbus>; + status = "okay"; +}; + +&xhci1{ + vbus-supply = <&usb_p1_vbus>; + status = "okay"; +}; + +&xhci2{ + vbus-supply = <&usb_p2_vbus>; + status = "okay"; +}; + +&xhci3{ + vbus-supply = <&usb_p3_vbus>; + status = "okay"; +}; + +&xhci4{ + vbus-supply = <&usb_p4_vbus>; + status = "okay"; +}; + +ð { + /* + * TX clock is provided by MAC + */ + phy-mode = "rgmii-rxid"; + phy-handle = <&phy>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + phy: phy@0 { + compatible = "ethernet-phy-idc0ff.0421"; + reg = <0>; + }; + }; +}; diff --git a/arch/arm/dts/omap4-var-stk-om44-u-boot.dtsi b/arch/arm/dts/omap4-var-stk-om44-u-boot.dtsi new file mode 100644 index 00000000000..431a02b2ffd --- /dev/null +++ b/arch/arm/dts/omap4-var-stk-om44-u-boot.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Basically we override some "simple-pm-bus" compatibles with "simple-bus". + * It allows to access the basic hardware without power-domain support. The + * hardware that can be accessed this way is: + * - the console's UART + * - the TWL6030 power regulator through I2C1 + * - the SD card reader (MMC1) + * + */ + +/ { + ocp { + compatible = "simple-bus"; + }; + + chosen { + stdout-path = &uart3; + }; +}; + +&l4_per { + compatible = "simple-bus"; + + segment@0 { + /* UART 3 / I2C1 (TWL6030) / MMC1 */ + compatible = "simple-bus"; + + /* MMC3 (wifi) */ + target-module@d1000 { + mmc@0 { + status = "disabled"; + }; + }; + + /* MMC4 */ + target-module@d5000 { + mmc@0 { + status = "disabled"; + }; + }; + }; +}; + +&l4_cfg { + compatible = "simple-bus"; + + segment@0 { + /* MMC1's clock */ + compatible = "simple-bus"; + }; +}; diff --git a/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi index 8d4871135fa..c3ec4a317f7 100644 --- a/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi +++ b/arch/arm/dts/qcs6490-rb3gen2-u-boot.dtsi @@ -17,10 +17,6 @@ }; }; -&usb_1 { - dr_mode = "host"; -}; - // RAM Entry 0 : Base 0x0080000000 Size 0x003A800000 // RAM Entry 1 : Base 0x00C0000000 Size 0x0001800000 // RAM Entry 2 : Base 0x00C3400000 Size 0x003CC00000 diff --git a/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi b/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi index 34fba29e859..9a30425bdad 100644 --- a/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi +++ b/arch/arm/dts/r7s72100-gr-peach-u-boot.dtsi @@ -49,7 +49,6 @@ compatible = "renesas,r7s72100-rpc-if"; reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>; bank-width = <2>; - num-cs = <1>; status = "okay"; spi-max-frequency = <50000000>; #address-cells = <1>; diff --git a/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi b/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi index dcdddd9aed6..9a77e242af2 100644 --- a/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi +++ b/arch/arm/dts/r8a774c0-ek874-u-boot.dtsi @@ -14,7 +14,6 @@ }; &rpc { - num-cs = <1>; status = "okay"; spi-max-frequency = <50000000>; #address-cells = <1>; diff --git a/arch/arm/dts/r8a774c0-u-boot.dtsi b/arch/arm/dts/r8a774c0-u-boot.dtsi index 17b863d23c9..d7b98783196 100644 --- a/arch/arm/dts/r8a774c0-u-boot.dtsi +++ b/arch/arm/dts/r8a774c0-u-boot.dtsi @@ -6,18 +6,6 @@ * */ -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a774c0-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; - /delete-node/ &can0; /delete-node/ &can1; /delete-node/ &canfd; diff --git a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi index d88e839a890..a162173b493 100644 --- a/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-salvator-x-u-boot.dtsi @@ -23,11 +23,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77951-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index 13760f3d5d4..e8a7fa27a76 100644 --- a/arch/arm/dts/r8a77951-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -5,18 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a7795-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; - /delete-node/ &ak4613; /delete-node/ &audma0; /delete-node/ &audma1; diff --git a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi index 8269d967af9..81bf715d300 100644 --- a/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-ulcb-u-boot.dtsi @@ -32,11 +32,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi index 0a1602cdd23..3c90e2a87ad 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dtsi @@ -23,11 +23,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index 9cc0d52f634..b437792a172 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -5,18 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a7796-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; - /delete-node/ &ak4613; /delete-node/ &audma0; /delete-node/ &audma1; diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi index d2a0406be17..2cc222d756a 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dtsi @@ -32,11 +32,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi index 518466aca35..3ad407f022e 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dtsi @@ -23,11 +23,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index 3cf32d84ca0..57382e34912 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -5,18 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77965-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; - /delete-node/ &ak4613; /delete-node/ &audma0; /delete-node/ &audma1; diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi index 3905bf4e4f7..ce715f61976 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dtsi @@ -32,11 +32,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77970-eagle-u-boot.dtsi b/arch/arm/dts/r8a77970-eagle-u-boot.dtsi index c7971b9e9ce..27709ac8a71 100644 --- a/arch/arm/dts/r8a77970-eagle-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-eagle-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -#include "r8a77970-u-boot.dtsi" #include <dt-bindings/gpio/gpio.h> / { @@ -14,29 +13,8 @@ }; }; -&avb { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - -}; - -&phy0 { - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -}; - -&pfc { - avb0_pins: avb { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - }; -}; - &rpc { - num-cs = <1>; status = "okay"; - spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi deleted file mode 100644 index d00ef2f3105..00000000000 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A77970 SoC - * - * Copyright (C) 2018 Marek Vasut <[email protected]> - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77970-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi b/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi index c7b2e07793d..a94fe92c831 100644 --- a/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-v3msk-u-boot.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2019 Cogent Embedded, Inc. */ -#include "r8a77970-u-boot.dtsi" #include <dt-bindings/gpio/gpio.h> / { @@ -25,29 +24,8 @@ }; }; -&avb { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - -}; - -&phy0 { - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -}; - -&pfc { - avb0_pins: avb { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - }; -}; - &rpc { - num-cs = <1>; status = "okay"; - spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dtsi b/arch/arm/dts/r8a77980-condor-u-boot.dtsi index 382bfe8cacd..34acdb1717c 100644 --- a/arch/arm/dts/r8a77980-condor-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-condor-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2019 Marek Vasut <[email protected]> */ -#include "r8a77980-u-boot.dtsi" - / { aliases { spi0 = &rpc; @@ -28,9 +26,7 @@ }; &rpc { - num-cs = <1>; status = "okay"; - spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi b/arch/arm/dts/r8a77980-u-boot.dtsi deleted file mode 100644 index df862978cba..00000000000 --- a/arch/arm/dts/r8a77980-u-boot.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A77980 SoC - * - * Copyright (C) 2019 Marek Vasut <[email protected]> - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77980-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi b/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi index 2901d0e7b57..2a4bd2e5fdf 100644 --- a/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2019 Cogent Embedded, Inc. */ -#include "r8a77980-u-boot.dtsi" - / { aliases { spi0 = &rpc; @@ -14,9 +12,7 @@ }; &rpc { - num-cs = <1>; status = "okay"; - spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi index a52c5de4ddf..91b9a20a042 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -#include "r8a77990-u-boot.dtsi" - / { sysinfo { compatible = "renesas,rcar-sysinfo"; @@ -33,11 +31,6 @@ }; }; -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; - &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi deleted file mode 100644 index d9dcce00e90..00000000000 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A77990 SoC - * - * Copyright (C) 2018 Marek Vasut <[email protected]> - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77990-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dtsi b/arch/arm/dts/r8a77995-draak-u-boot.dtsi index 19d19542efd..d0dd06f08bf 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-draak-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2018 Marek Vasut <[email protected]> */ -#include "r8a77995-u-boot.dtsi" - / { sysinfo { compatible = "renesas,rcar-sysinfo"; @@ -22,8 +20,3 @@ bootph-all; }; }; - -&rpc { - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; - status = "disabled"; -}; diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi deleted file mode 100644 index 85fccbabfb3..00000000000 --- a/arch/arm/dts/r8a77995-u-boot.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A77995 SoC - * - * Copyright (C) 2018 Marek Vasut <[email protected]> - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi b/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi index 3b8a017cb41..c1d92d2d9bb 100644 --- a/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi +++ b/arch/arm/dts/r8a779a0-falcon-u-boot.dtsi @@ -5,8 +5,6 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include "r8a779a0-u-boot.dtsi" - / { aliases { spi0 = &rpc; @@ -16,8 +14,6 @@ &rpc { #address-cells = <1>; #size-cells = <0>; - num-cs = <1>; - spi-max-frequency = <50000000>; status = "okay"; flash@0 { diff --git a/arch/arm/dts/r8a779a0-u-boot.dtsi b/arch/arm/dts/r8a779a0-u-boot.dtsi deleted file mode 100644 index a4e75a67dc3..00000000000 --- a/arch/arm/dts/r8a779a0-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A779A0 SoC - * - * Copyright (C) 2020 Renesas Electronics Corp. - */ - -/ { - soc { - rpc: spi@ee200000 { - compatible = "renesas,r8a779a0-rpc-if", "renesas,rcar-gen3-rpc-if"; - reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>; - clocks = <&cpg CPG_MOD 629>; - bank-width = <2>; - num-cs = <1>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi index bd6a3d0713f..5a2d1fe66ce 100644 --- a/arch/arm/dts/r8a779g0-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-u-boot.dtsi @@ -93,11 +93,6 @@ bootph-all; }; -&rpc { - bank-width = <2>; - num-cs = <1>; -}; - &soc { apmu@e6170000 { /* Remoteproc */ compatible = "renesas,r8a779g0-cr52"; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi index c04d2ae2be4..f9c419b11d7 100644 --- a/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi +++ b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi @@ -5,36 +5,16 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ -#include "r8a779h0-u-boot.dtsi" - / { aliases { spi0 = &rpc; }; }; -&pfc { - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; -}; - &rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <40000000>; status = "disabled"; flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi b/arch/arm/dts/r8a779h0-u-boot.dtsi deleted file mode 100644 index 40e070be9a8..00000000000 --- a/arch/arm/dts/r8a779h0-u-boot.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -&rpc { - bank-width = <2>; - num-cs = <1>; -}; diff --git a/arch/arm/dts/r8a779md-geist-u-boot.dtsi b/arch/arm/dts/r8a779md-geist-u-boot.dtsi new file mode 100644 index 00000000000..fbda218002a --- /dev/null +++ b/arch/arm/dts/r8a779md-geist-u-boot.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot for the Geist board with r8a779md + * + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&pfc { + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; +}; + +/* + * SPI access works only if TFA is built with RCAR_RPC_HYPERFLASH_LOCKED=0 + * and SPD=none , otherwise the RPC access is blocked either by TFA in case + * the former is set to 1, or by OPTEE-OS in case SPD=opteed . + */ +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <40000000>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; +}; + +&vcc_sdhi0 { + u-boot,off-on-delay-us = <20000>; +}; diff --git a/arch/arm/dts/r8a779md-geist.dts b/arch/arm/dts/r8a779md-geist.dts new file mode 100644 index 00000000000..2921aba92a5 --- /dev/null +++ b/arch/arm/dts/r8a779md-geist.dts @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Geist board with R-Car M3Le + * + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "r8a779md.dtsi" + +/ { + model = "Renesas Geist board based on r8a779md"; + compatible = "renesas,geist", "renesas,r8a779md", "renesas,r8a77965"; + + aliases { + serial0 = &scif2; + serial1 = &hscif1; + ethernet0 = &avb; + mmc0 = &sdhi2; + mmc1 = &sdhi0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:115200n8"; + }; + + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2500/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + + brightness-levels = <256 128 64 16 8 4 0>; + default-brightness-level = <6>; + + power-supply = <®_12v>; + enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + }; + + cvbs-in { + compatible = "composite-video-connector"; + label = "CVBS IN"; + + port { + cvbs_con: endpoint { + remote-endpoint = <&adv7482_ain7>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + label = "HDMI IN"; + type = "a"; + + port { + hdmi_in_con: endpoint { + remote-endpoint = <&adv7482_hdmi>; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + linux,code = <KEY_1>; + label = "SW4-1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; + linux,code = <KEY_2>; + label = "SW4-2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + linux,code = <KEY_3>; + label = "SW4-3"; + wakeup-source; + debounce-interval = <20>; + }; + + key-4 { + gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_4>; + label = "SW4-4"; + wakeup-source; + debounce-interval = <20>; + }; + + key-a { + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_A>; + label = "TSW0"; + wakeup-source; + debounce-interval = <20>; + }; + + key-b { + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + linux,code = <KEY_B>; + label = "TSW1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-c { + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; + linux,code = <KEY_C>; + label = "TSW2"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "fixed-12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + sound_card: sound { + compatible = "audio-graph-card"; + + label = "rcar-sound"; + dais = <&rsnd_port0>; /* AK4619 Audio Codec */ + }; + + x12_clk: x12-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + /* External DU dot clocks */ + x21_clk: x21-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x22_clk: x22-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <33000000>; + }; + + x23_clk: x23-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + x3013_clk: x3013-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7482_txa>; + }; + }; + }; +}; + +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + /* Please only enable hscif1 or scif1 */ + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + ak4619: codec@10 { + compatible = "asahi-kasei,ak4619"; + reg = <0x10>; + clocks = <&rcar_sound 3>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + ak4619_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + }; + }; + }; + + /* Pin-to-pin, register map, and control compatible with CS2000 and CS2200 */ + cs2500: clock-controller@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2500", "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2500>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + versaclock3: clock-controller@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x3013_clk>; + assigned-clocks = <&versaclock3 4>, <&versaclock3 5>; + assigned-clock-rates = <100000000>, <100000000>; + }; + + versaclock5: clock-controller@6a { + compatible = "idt,5p49v5923"; + reg = <0x6a>; + #clock-cells = <1>; + clocks = <&x23_clk>; + clock-names = "xin"; + }; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70 0x71 0x72 0x73 0x74 0x75 + 0x60 0x61 0x62 0x63 0x64 0x65>; + reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", + "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; + + interrupts-extended = <&gpio6 30 IRQ_TYPE_LEVEL_LOW>, + <&gpio6 31 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "intrq1", "intrq2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; + }; + + port@a { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + + csa_vdd: adc@7c { + compatible = "maxim,max9611"; + reg = <0x7c>; + + shunt-resistor-micro-ohms = <5000>; + }; + + csa_dvfs: adc@7f { + compatible = "maxim,max9611"; + reg = <0x7f>; + + shunt-resistor-micro-ohms = <5000>; + }; +}; + +&i2c_dvfs { + status = "okay"; + + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; + status = "disabled"; +}; + +&pciec0 { + clocks = <&cpg CPG_MOD 319>, <&versaclock3 4>; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + + keys_pins: keys { + pins = "GP_5_17", "GP_5_20", "GP_5_22"; + bias-pull-up; + }; + + pwm1_pins: pwm1 { + groups = "pwm1_a"; + function = "pwm1"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_a", "scif1_ctrl"; + function = "scif1"; + }; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + function = "sdhi2"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + function = "audio_clk"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <12288000 11289600>; + + status = "okay"; + + /* update <audio_clk_b> to <cs2500> */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2500>, + <&audio_clk_c>, + <&cpg CPG_MOD 922>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + rsnd_port0: port@0 { + reg = <0>; + + rsnd_endpoint0: endpoint { + remote-endpoint = <&ak4619_endpoint>; + dai-format = "left_j"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + playback = <&ssi0>, <&src0>, <&dvc0>; + capture = <&ssi1>, <&src1>, <&dvc1>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + /* Please only enable hscif1 or scif1 */ + /* status = "okay"; */ +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + fixed-emmc-driver-type = <1>; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&usb_extal_clk { + clock-frequency = <50000000>; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; + +&vspb { + status = "okay"; +}; + +&vspi0 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a779md.dtsi b/arch/arm/dts/r8a779md.dtsi new file mode 100644 index 00000000000..f3065414134 --- /dev/null +++ b/arch/arm/dts/r8a779md.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car M3Le (R8A779MD) SoC + * + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +#include "r8a77965.dtsi" + +/ { + compatible = "renesas,r8a779md", "renesas,r8a77965"; +}; + +/delete-node/ &csi20; +/delete-node/ &drif00; +/delete-node/ &drif01; +/delete-node/ &drif10; +/delete-node/ &drif11; +/delete-node/ &drif20; +/delete-node/ &drif21; +/delete-node/ &drif30; +/delete-node/ &drif31; +/delete-node/ &du; +/delete-node/ &ehci1; +/delete-node/ &hdmi0; +/delete-node/ &lvds0; +/delete-node/ &mlp; +/delete-node/ &ohci1; +/delete-node/ &pciec1; +/delete-node/ &sata; +/delete-node/ &usb2_phy1; +/delete-node/ &usb3_peri0; +/delete-node/ &usb3_phy0; +/delete-node/ &vin0csi20; +/delete-node/ &vin1csi20; +/delete-node/ &vin2csi20; +/delete-node/ &vin3csi20; +/delete-node/ &vin4csi20; +/delete-node/ &vin5csi20; +/delete-node/ &vin6csi20; +/delete-node/ &vin7csi20; +/delete-node/ &xhci0; + +&sdhi0 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; +}; + +&sdhi1 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; +}; + +&sdhi2 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; +}; + +&sdhi3 { + compatible = "renesas,sdhi-r8a779md", "renesas,rcar-gen3-sdhi"; + no-mmc; +}; diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi new file mode 100644 index 00000000000..356f633135d --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot for the Ironhide CM33 board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include "r8a78000-ironhide-u-boot.dtsi" + +/ { + model = "Renesas Ironhide board CM33 based on r8a78000"; + compatible = "renesas,ironhide-cm33", "renesas,r8a78000-cm33"; + + aliases { + serial1 = &hscif1; + }; + + chosen { + stdout-path = "serial1:1843200n8"; + }; + + /delete-node/ firmware; + /delete-node/ memory@40000000; + /delete-node/ memory@60600000; + /delete-node/ memory@1080000000; + /delete-node/ memory@1200000000; + /delete-node/ memory@1400000000; + /delete-node/ memory@1600000000; + /delete-node/ memory@1800000000; + /delete-node/ memory@1a00000000; + /delete-node/ memory@1c00000000; + /delete-node/ memory@1e00000000; + /delete-node/ reserved-memory; + + memory@b8400000 { + device_type = "memory"; + reg = <0x0 0xb8400000 0x0 0x00200000>; + }; + + dummy_clk_rclk: dummy-clk-rclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + dummy_clk_sasyncd4_rt: dummy-clk-sasyncd4-rt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16660000>; + }; + + ctl: syscon@5fffd000 { + compatible = "renesas,r8a78000-ctl", + "renesas,rcar-gen5-ctl", + "syscon"; + reg = <0 0x5fffd000 0 0xc4>; + }; + + watchdog@5fffd800 { + compatible = "renesas,r8a78000-wwdt", + "renesas,rcar-gen5-wwdt"; + clocks = <&dummy_clk_rclk>, <&dummy_clk_sasyncd4_rt>; + clock-names = "cnt", "bus"; + reg = <0 0x5fffd800 0 0x10>; + syscon = <&ctl>; + }; + + ram@b8940000 { /* RT-VRAM */ + compatible = "renesas,r8a78000-rtvram"; + reg = <0 0xb8940000 0 0xf000>; + }; + + scp@c1340000 { + compatible = "renesas,r8a78000-rproc"; + reg = <0 0xc1340000 0 0x80000>; + }; + + ram@e9800000 { /* DBSC5 */ + compatible = "renesas,r8a78000-dbsc"; + reg = <0 0xe9800000 0 0x1000000>; + }; +}; + +&cpg { + /delete-property/ firmware; +}; + +ð_pcs { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&mdlc_hscn { + /delete-property/ firmware; +}; + +&mdlc_pere { + /delete-property/ firmware; +}; + +&mmc0 { + status = "disabled"; +}; + +&mp_phy { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&pfc { + hscif1_pins: hscif1 { + groups = "hscif1_data", "hscif1_ctrl"; + function = "hscif1"; + }; +}; + +&rswitch3 { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&soc { + dma-ranges = <0 0x00000000 0 0xa0000000 0 0x20000000>; +}; + +&ufs0 { + /delete-property/ power-domains; +}; + +&ufs1 { + /delete-property/ power-domains; + status = "disabled"; +}; diff --git a/arch/arm/dts/r8a78000-ironhide-cm33.dts b/arch/arm/dts/r8a78000-ironhide-cm33.dts new file mode 100644 index 00000000000..79ad844165c --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-cm33.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Ironhide CM33 board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include "../../../dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts" diff --git a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi index 9c72f3e55f4..299716f96a4 100644 --- a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi @@ -5,4 +5,190 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include <dt-bindings/net/ti-dp83869.h> #include "r8a78000-u-boot.dtsi" + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &mmc0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&cpg { + firmware = <&scmi>; +}; + +ð_pcs { + phys = <&mp_phy 2 1>; + status = "okay"; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&mdlc_hscn { + firmware = <&scmi>; +}; + +&mdlc_pere { + firmware = <&scmi>; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-1 = <&mmc0_pins>; + pinctrl-names = "default", "state_uhs"; + + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + + status = "okay"; +}; + +&mp_phy { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + eth25g2_pins: eth25g2 { + groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; + function = "eth25g2"; + drive-strength = <24>; + }; + + ethes0_pins: ethes0 { + groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; + function = "ethes0"; + drive-strength = <24>; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + mmc0_pins: mmc0 { + groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; + function = "mmc0"; + drive-strength = <24>; + }; + + rsw3_pins: rsw3 { + groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; + function = "rsw3"; + drive-strength = <24>; + }; + + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rswitch3 { + pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * NOTE: Only port@4 is configured for R-Car X5H board. + * Other ports (0-3, 5-12) are currently unused or not + * connected. + */ + port@4 { + reg = <4>; + renesas,connect_to_xpcs; + phy-handle = <&dp83869_phy>; + phy-mode = "sgmii"; + phys = <ð_pcs 5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + dp83869_phy: ethernet-phy@2 { + reg = <2>; + ti,sgmii-interface; + ti,max-output-impedance; + ti,refclk-output-enable; + ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; + }; + }; + }; + }; +}; + +&ufs0 { + status = "okay"; +}; + +&ufs1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a78000-ironhide.dts b/arch/arm/dts/r8a78000-ironhide.dts deleted file mode 100644 index 601f2740b54..00000000000 --- a/arch/arm/dts/r8a78000-ironhide.dts +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the Ironhide board - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a78000.dtsi" -#include <dt-bindings/net/ti-dp83869.h> - -/ { - model = "Renesas Ironhide board based on r8a78000"; - compatible = "renesas,ironhide", "renesas,r8a78000"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - mmc0 = &mmc0; - serial0 = &hscif0; - }; - - chosen { - stdout-path = "serial0:1843200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x80000000>; - }; - - memory@1080000000 { - device_type = "memory"; - reg = <0x10 0x80000000 0x0 0x80000000>; - }; - - memory@1200000000 { - device_type = "memory"; - reg = <0x12 0x00000000 0x1 0x00000000>; - }; - - memory@1400000000 { - device_type = "memory"; - reg = <0x14 0x00000000 0x1 0x00000000>; - }; - - memory@1600000000 { - device_type = "memory"; - reg = <0x16 0x00000000 0x1 0x00000000>; - }; - - memory@1800000000 { - device_type = "memory"; - reg = <0x18 0x00000000 0x1 0x00000000>; - }; - - memory@1a00000000 { - device_type = "memory"; - reg = <0x1a 0x00000000 0x1 0x00000000>; - }; - - memory@1c00000000 { - device_type = "memory"; - reg = <0x1c 0x00000000 0x1 0x00000000>; - }; - - memory@1e00000000 { - device_type = "memory"; - reg = <0x1e 0x00000000 0x1 0x00000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&extal_clk { - clock-frequency = <16666600>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; -}; - -ð_pcs { - phys = <&mp_phy 2 1>; - status = "okay"; -}; - -&mmc0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-1 = <&mmc0_pins>; - pinctrl-names = "default", "state_uhs"; - - bus-width = <8>; - full-pwr-cycle-in-suspend; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - no-sd; - no-sdio; - non-removable; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - - status = "okay"; -}; - -&ufs0 { - status = "okay"; -}; - -&ufs1 { - status = "okay"; -}; - -&mp_phy { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - eth25g2_pins: eth25g2 { - groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; - function = "eth25g2"; - drive-strength = <24>; - }; - - ethes0_pins: ethes0 { - groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; - function = "ethes0"; - drive-strength = <24>; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; - function = "mmc0"; - drive-strength = <24>; - }; - - rsw3_pins: rsw3 { - groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; - function = "rsw3"; - drive-strength = <24>; - }; - - scif_clk_pins: scif-clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rswitch3 { - pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; - pinctrl-names = "default"; - status = "okay"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * NOTE: Only port@4 is configured for R-Car X5H board. - * Other ports (0-3, 5-12) are currently unused or not - * connected. - */ - port@4 { - reg = <4>; - renesas,connect_to_xpcs; - phy-handle = <&dp83869_phy>; - phy-mode = "sgmii"; - phys = <ð_pcs 5>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - dp83869_phy: ethernet-phy@2 { - reg = <2>; - ti,sgmii-interface; - ti,max-output-impedance; - ti,refclk-output-enable; - ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>; - }; - }; - }; - }; -}; - -&scif_clk { - clock-frequency = <26000000>; -}; diff --git a/arch/arm/dts/r8a78000-u-boot.dtsi b/arch/arm/dts/r8a78000-u-boot.dtsi index 1bc73252430..df21a9e03a2 100644 --- a/arch/arm/dts/r8a78000-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-u-boot.dtsi @@ -5,9 +5,41 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include <dt-bindings/clock/r8a78000-clock-scmi.h> +#include <dt-bindings/power/r8a78000-power-scmi.h> +#include <dt-bindings/reset/r8a78000-reset-scmi.h> + / { - soc { - bootph-all; + firmware { + scmi: scmi { + compatible = "arm,scmi"; + arm,poll-transport; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 0>, <&mailbox 1>; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; + #address-cells = <1>; + #size-cells = <0>; + + protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; }; /* Placeholder clock until the clock provider is in place */ @@ -32,16 +64,12 @@ clk_stub_mmc: clk-stub-mmc { compatible = "renesas,compound-clock"; #clock-cells = <0>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>, - <&scmi_clk 1691>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_SDHI0>, + <&cpg SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN>; clock-names = "mdlc", "per"; }; }; -&cpg { - bootph-all; -}; - &extal_clk { bootph-all; }; @@ -50,90 +78,311 @@ bootph-all; }; -&gpio0 { - clocks = <&clk_stub_gpio>; +&prr { + bootph-all; }; -&gpio1 { - clocks = <&clk_stub_gpio>; -}; +&soc { + bootph-all; -&gpio2 { - clocks = <&clk_stub_gpio>; -}; + mailbox: mfis_mbox@18842000 { + compatible = "renesas,mfis-mbox"; + #mbox-cells = <1>; + reg = <0 0x18842004 0 0x8>; + interrupts = <GIC_SPI 4362 IRQ_TYPE_LEVEL_HIGH>; + }; -&gpio3 { - clocks = <&clk_stub_gpio>; -}; + pfc: pinctrl@c0400000 { + compatible = "renesas,pfc-r8a78000"; + reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, + <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, + <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, + <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, + <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, + <0 0xc9b00800 0 0x104>; + }; -&gpio4 { - clocks = <&clk_stub_gpio>; -}; + mmc0: mmc@c0880000 { + compatible = "renesas,rcar-gen5-sdhi"; + reg = <0 0xc0880000 0 0x2000>; + clock-names = "core"; + max-frequency = <200000000>; + clocks = <&clk_stub_mmc>; + status = "disabled"; + }; -&gpio5 { - clocks = <&clk_stub_gpio>; -}; + mdlc_pere: system-controller@c08f0000 { + compatible = "renesas,r8a78000-mdlc"; + reg = <0 0xc08f0000 0 0x1000>; + #power-domain-cells = <1>; + #reset-cells = <1>; + bootph-all; + }; -&gpio6 { - clocks = <&clk_stub_gpio>; -}; + ufs0: ufs@c0a80000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = <GIC_SPI 4284 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS0>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS0>; + resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS0>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; -&gpio7 { - clocks = <&clk_stub_gpio>; -}; + ufs1: ufs@c0a90000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = <GIC_SPI 4285 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mdlc_pere X5H_POWER_DOMAIN_ID_UFS1>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_UFS1>; + resets = <&mdlc_pere SCP_RESET_DOMAIN_ID_UFS1>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; -&gpio8 { - clocks = <&clk_stub_gpio>; -}; + scp: sram@c1000000 { + compatible = "arm,rcar-sram-ns", "mmio-sram"; + reg = <0x0 0xc1000000 0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc1000000 0x80000>; -&gpio9 { - clocks = <&clk_stub_gpio>; -}; + cpu_scp_lpri0: scp-shmem@60000 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61200 0x0100>; + }; -&gpio10 { - clocks = <&clk_stub_gpio>; -}; + cpu_scp_hpri0: scp-shmem@60300 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61300 0x100>; + }; + }; -&i2c0 { - clocks = <&clk_stub_i2c0>; -}; + cpg: clock-controller@c1320000 { + compatible = "renesas,r8a78000-cpg"; + reg = <0 0xc1320000 0 0x10000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <1>; + bootph-all; + }; -&i2c1 { - clocks = <&clk_stub_i2c1>; -}; + i2c0: i2c@c11d0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc11d0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_stub_i2c0>; + status = "disabled"; + }; -&i2c2 { - clocks = <&clk_stub_i2c1>; -}; + i2c1: i2c@c06c0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06c0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_stub_i2c1>; + status = "disabled"; + }; -&i2c3 { - clocks = <&clk_stub_i2c1>; -}; + gpio0: gpio@c1080110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 28>; + clocks = <&clk_stub_gpio>; + }; -&i2c4 { - clocks = <&clk_stub_i2c1>; -}; + gpio1: gpio@c1080910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 22>; + clocks = <&clk_stub_gpio>; + }; -&i2c5 { - clocks = <&clk_stub_i2c1>; -}; + gpio2: gpio@c1081110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1081110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 29>; + clocks = <&clk_stub_gpio>; + }; -&i2c6 { - clocks = <&clk_stub_i2c1>; -}; + gpio3: gpio@c0800110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 17>; + clocks = <&clk_stub_gpio>; + }; -&i2c7 { - clocks = <&clk_stub_i2c1>; -}; + gpio4: gpio@c0800910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 16>; + clocks = <&clk_stub_gpio>; + }; -&i2c8 { - clocks = <&clk_stub_i2c1>; -}; + gpio5: gpio@c0400110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 23>; + clocks = <&clk_stub_gpio>; + }; -&mmc0 { - clocks = <&clk_stub_mmc>; -}; + gpio6: gpio@c0400910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 31>; + clocks = <&clk_stub_gpio>; + }; -&prr { - bootph-all; + gpio7: gpio@c0401110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 31>; + clocks = <&clk_stub_gpio>; + }; + + gpio8: gpio@c0401910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 32>; + gpio-reserved-ranges = <16 10>; + clocks = <&clk_stub_gpio>; + }; + + gpio9: gpio@c9b00110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + clocks = <&clk_stub_gpio>; + }; + + gpio10: gpio@c9b00910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 14>; + clocks = <&clk_stub_gpio>; + }; + + mp_phy: mp_phy@c9a00000 { + compatible = "renesas,r8a78000-multi-protocol-phy"; + reg = <0 0xc9a00000 0 0x100000>; + #phy-cells = <2>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_MPPHY01>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY11>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY21>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY31>, + <&cpg SCP_CLOCK_ID_MDLC_MPPHY02>; + clock-names = "mpphy01", "mpphy11", "mpphy21", + "mpphy31", "mpphy02"; + power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP0>, + <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP1>, + <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP2>, + <&mdlc_hscn X5H_POWER_DOMAIN_ID_MPP3>; + resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY01>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY11>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY21>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY31>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_MPPHY02>; + status = "disabled"; + }; + + rswitch3: ethernet@c9bc0000 { + compatible = "renesas,r8a78000-ether-switch3", + "renesas,etherswitch"; + reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; + reg-names = "base", "secure_base"; + power-domains = <&mdlc_hscn X5H_POWER_DOMAIN_ID_RSW>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_RSW3>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSN>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3AES>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, + <&cpg SCP_CLOCK_ID_MDLC_RSW3MFWD>; + clock-names = "rsw3", "rsw3tsn", "rsw3aes", + "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", + "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", + "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; + status = "disabled"; + }; + + eth_pcs: phy@c9c50000 { + compatible = "renesas,r8a78000-ether-pcs"; + reg = <0 0xc9c50000 0 0x4000>; + #phy-cells = <1>; + clocks = <&cpg SCP_CLOCK_ID_MDLC_XPCS0>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS1>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS2>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS3>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS4>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS5>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS6>, + <&cpg SCP_CLOCK_ID_MDLC_XPCS7>; + clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + resets = <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS0>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS1>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS2>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS3>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS4>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS5>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS6>, + <&mdlc_hscn SCP_RESET_DOMAIN_ID_XPCS7>; + reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + status = "disabled"; + }; + + mdlc_hscn: system-controller@c9c90000 { + compatible = "renesas,r8a78000-mdlc"; + reg = <0 0xc9c90000 0 0x1000>; + #power-domain-cells = <1>; + #reset-cells = <1>; + bootph-all; + }; }; diff --git a/arch/arm/dts/r8a78000.dtsi b/arch/arm/dts/r8a78000.dtsi deleted file mode 100644 index 89c2881fa94..00000000000 --- a/arch/arm/dts/r8a78000.dtsi +++ /dev/null @@ -1,1164 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car X5H (R8A78000) SoC - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -#include <dt-bindings/clock/r8a78000-clock-scmi.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/r8a78000-power-scmi.h> -#include <dt-bindings/reset/r8a78000-reset-scmi.h> - -/ { - compatible = "renesas,r8a78000"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a720_0>; - }; - core1 { - cpu = <&a720_1>; - }; - core2 { - cpu = <&a720_2>; - }; - core3 { - cpu = <&a720_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&a720_4>; - }; - core1 { - cpu = <&a720_5>; - }; - core2 { - cpu = <&a720_6>; - }; - core3 { - cpu = <&a720_7>; - }; - }; - - cluster2 { - core0 { - cpu = <&a720_8>; - }; - core1 { - cpu = <&a720_9>; - }; - core2 { - cpu = <&a720_10>; - }; - core3 { - cpu = <&a720_11>; - }; - }; - - cluster3 { - core0 { - cpu = <&a720_12>; - }; - core1 { - cpu = <&a720_13>; - }; - core2 { - cpu = <&a720_14>; - }; - core3 { - cpu = <&a720_15>; - }; - }; - - cluster4 { - core0 { - cpu = <&a720_16>; - }; - core1 { - cpu = <&a720_17>; - }; - core2 { - cpu = <&a720_18>; - }; - core3 { - cpu = <&a720_19>; - }; - }; - - cluster5 { - core0 { - cpu = <&a720_20>; - }; - core1 { - cpu = <&a720_21>; - }; - core2 { - cpu = <&a720_22>; - }; - core3 { - cpu = <&a720_23>; - }; - }; - - cluster6 { - core0 { - cpu = <&a720_24>; - }; - core1 { - cpu = <&a720_25>; - }; - core2 { - cpu = <&a720_26>; - }; - core3 { - cpu = <&a720_27>; - }; - }; - - cluster7 { - core0 { - cpu = <&a720_28>; - }; - core1 { - cpu = <&a720_29>; - }; - core2 { - cpu = <&a720_30>; - }; - core3 { - cpu = <&a720_31>; - }; - }; - }; - - a720_0: cpu@0 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x0>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_0>; - }; - - a720_1: cpu@100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_1>; - }; - - a720_2: cpu@200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_2>; - }; - - a720_3: cpu@300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_3>; - }; - - a720_4: cpu@10000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_4>; - }; - - a720_5: cpu@10100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_5>; - }; - - a720_6: cpu@10200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_6>; - }; - - a720_7: cpu@10300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_7>; - }; - - a720_8: cpu@20000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_8>; - }; - - a720_9: cpu@20100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_9>; - }; - - a720_10: cpu@20200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_10>; - }; - - a720_11: cpu@20300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_11>; - }; - - a720_12: cpu@30000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_12>; - }; - - a720_13: cpu@30100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_13>; - }; - - a720_14: cpu@30200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_14>; - }; - - a720_15: cpu@30300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_15>; - }; - - a720_16: cpu@40000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_16>; - }; - - a720_17: cpu@40100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_17>; - }; - - a720_18: cpu@40200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_18>; - }; - - a720_19: cpu@40300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_19>; - }; - - a720_20: cpu@50000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_20>; - }; - - a720_21: cpu@50100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_21>; - }; - - a720_22: cpu@50200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_22>; - }; - - a720_23: cpu@50300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_23>; - }; - - a720_24: cpu@60000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_24>; - }; - - a720_25: cpu@60100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_25>; - }; - - a720_26: cpu@60200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_26>; - }; - - a720_27: cpu@60300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_27>; - }; - - a720_28: cpu@70000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_28>; - }; - - a720_29: cpu@70100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_29>; - }; - - a720_30: cpu@70200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_30>; - }; - - a720_31: cpu@70300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_31>; - }; - - L2_CA720_0: cache-controller-200 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_1: cache-controller-201 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_2: cache-controller-202 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_3: cache-controller-203 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_4: cache-controller-204 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_5: cache-controller-205 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_6: cache-controller-206 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_7: cache-controller-207 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_8: cache-controller-208 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_9: cache-controller-209 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_10: cache-controller-210 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_11: cache-controller-211 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_12: cache-controller-212 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_13: cache-controller-213 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_14: cache-controller-214 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_15: cache-controller-215 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_16: cache-controller-216 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_17: cache-controller-217 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_18: cache-controller-218 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_19: cache-controller-219 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_20: cache-controller-220 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_21: cache-controller-221 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_22: cache-controller-222 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_23: cache-controller-223 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_24: cache-controller-224 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_25: cache-controller-225 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_26: cache-controller-226 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_27: cache-controller-227 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_28: cache-controller-228 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_29: cache-controller-229 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_30: cache-controller-230 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_31: cache-controller-231 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L3_CA720_0: cache-controller-30 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_1: cache-controller-31 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_2: cache-controller-32 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_3: cache-controller-33 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_4: cache-controller-34 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_5: cache-controller-35 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_6: cache-controller-36 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_7: cache-controller-37 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - }; - - /* - * In the early phase, there is no clock control support, - * so assume that the clocks are enabled by default. - * Therefore, dummy clocks are used. - */ - dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <66666000>; - }; - - dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <266660000>; - }; - - extal_clk: extal-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* clock-frequency must be set on board */ - }; - - extalr_clk: extalr-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* clock-frequency must be set on board */ - }; - - firmware { - scmi { - compatible = "arm,scmi"; - arm,poll-transport; - mbox-names = "tx", "rx"; - mboxes = <&mailbox 0>, <&mailbox 1>; - shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_devpd: protocol@11 { - reg = <0x11>; - #power-domain-cells = <1>; - }; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; /* optional */ - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mailbox: mfis_mbox@18842000 { - compatible = "renesas,mfis-mbox"; - #mbox-cells = <1>; - reg = <0 0x18842004 0 0x8>; - interrupts = <GIC_SPI 4362 IRQ_TYPE_LEVEL_HIGH>; - }; - - prr: chipid@189e0044 { - compatible = "renesas,prr"; - reg = <0 0x189e0044 0 4>; - }; - - /* Application Processors manage View-1 of a GIC-720AE */ - gic: interrupt-controller@39000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x39000000 0 0x10000>, - <0 0x39080000 0 0x800000>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - }; - - pfc: pinctrl@c0400000 { - compatible = "renesas,pfc-r8a78000"; - reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, - <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, - <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, - <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, - <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, - <0 0xc9b00800 0 0x104>; - }; - - scif0: serial@c0700000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0700000 0 0x40>; - interrupts = <GIC_SPI 4074 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif1: serial@c0704000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0704000 0 0x40>; - interrupts = <GIC_SPI 4075 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif3: serial@c0708000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0708000 0 0x40>; - interrupts = <GIC_SPI 4076 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif4: serial@c070c000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc070c000 0 0x40>; - interrupts = <GIC_SPI 4077 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - mmc0: mmc@c0880000 { - compatible = "renesas,rcar-gen5-sdhi"; - reg = <0 0xc0880000 0 0x2000>; - clock-names = "core"; - max-frequency = <200000000>; - status = "disabled"; - }; - - ufs0: ufs@c0a80000 { - compatible = "renesas,r8a78000-ufs"; - reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; - reg-names = "hcr", "phy"; - interrupts = <GIC_SPI 4284 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS0>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS0>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS0>; - freq-table-hz = <38400000 38400000>; - status = "disabled"; - }; - - ufs1: ufs@c0a90000 { - compatible = "renesas,r8a78000-ufs"; - reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; - reg-names = "hcr", "phy"; - interrupts = <GIC_SPI 4285 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS1>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS1>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS1>; - freq-table-hz = <38400000 38400000>; - status = "disabled"; - }; - - scp: sram@c1000000 { - compatible = "arm,rcar-sram-ns", "mmio-sram"; - reg = <0x0 0xc1000000 0x0 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xc1000000 0x80000>; - - cpu_scp_lpri0: scp-shmem@60000 { - compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; - reg = <0x61200 0x0100>; - }; - - cpu_scp_hpri0: scp-shmem@60300 { - compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; - reg = <0x61300 0x100>; - }; - }; - - cpg: clock-controller@c64f0000 { - compatible = "renesas,r8a78000-cpg-mssr"; - reg = <0 0xc64f0000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - hscif0: serial@c0710000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0710000 0 0x60>; - interrupts = <GIC_SPI 4078 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif1: serial@c0714000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0714000 0 0x60>; - interrupts = <GIC_SPI 4079 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif2: serial@c0718000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0718000 0 0x60>; - interrupts = <GIC_SPI 4080 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif3: serial@c071c000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc071c000 0 0x60>; - interrupts = <GIC_SPI 4081 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - i2c0: i2c@c11d0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc11d0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@c06c0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06c0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@c06c8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06c8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@c06d0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06d0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@c06d8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06d8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@c06e0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06e0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@c06e8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06e8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@c06f0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06f0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@c06f8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06f8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gpio0: gpio@c1080110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1080110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 28>; - }; - - gpio1: gpio@c1080910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1080910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 22>; - }; - - gpio2: gpio@c1081110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1081110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 29>; - }; - - gpio3: gpio@c0800110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0800110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - }; - - gpio4: gpio@c0800910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0800910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 16>; - }; - - gpio5: gpio@c0400110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0400110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 23>; - }; - - gpio6: gpio@c0400910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0400910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 31>; - }; - - gpio7: gpio@c0401110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0401110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 31>; - }; - - gpio8: gpio@c0401910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0401910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 256 32>; - gpio-reserved-ranges = <16 10>; - }; - - gpio9: gpio@c9b00110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc9b00110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 288 17>; - }; - - gpio10: gpio@c9b00910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc9b00910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 320 14>; - }; - - mp_phy: mp_phy@c9a00000 { - compatible = "renesas,r8a78000-multi-protocol-phy"; - reg = <0 0xc9a00000 0 0x100000>; - #phy-cells = <2>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY01>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY11>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY21>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY31>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY02>; - clock-names = "mpphy01", "mpphy11", "mpphy21", - "mpphy31", "mpphy02"; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP0>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP1>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP2>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP3>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY01>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY11>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY21>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY31>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY02>; - status = "disabled"; - }; - - rswitch3: ethernet@c9bc0000 { - compatible = "renesas,r8a78000-ether-switch3", - "renesas,etherswitch"; - reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; - reg-names = "base", "secure_base"; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_RSW>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSN>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3AES>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3MFWD>; - clock-names = "rsw3", "rsw3tsn", "rsw3aes", - "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", - "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", - "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; - status = "disabled"; - }; - - eth_pcs: phy@c9c50000 { - compatible = "renesas,r8a78000-ether-pcs"; - reg = <0 0xc9c50000 0 0x4000>; - #phy-cells = <1>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS0>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS1>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS2>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS4>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS5>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS6>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS7>; - clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", - "xpcs4", "xpcs5", "xpcs6", "xpcs7"; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS0>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS1>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS2>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS3>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS4>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS5>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS6>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS7>; - reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", - "xpcs4", "xpcs5", "xpcs6", "xpcs7"; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; - }; -}; diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts deleted file mode 100644 index 93291d78734..00000000000 --- a/arch/arm/dts/rk3128-evb.dts +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rk3128.dtsi" - -/ { - model = "Rockchip RK3128 Evaluation board"; - compatible = "rockchip,rk3128-evb", "rockchip,rk3128"; - - chosen { - stdout-path = &uart2; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_host: vcc5v0-host-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&emmc { - fifo-mode; - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&u2phy { - status = "okay"; -}; - -&u2phy_otg { - status = "okay"; -}; - -&u2phy_host { - status = "okay"; -}; - -&usb_host_ehci { - status = "okay"; -}; - -&usb_host_ohci { - status = "okay"; -}; - -&usb_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&pinctrl { - usb_otg { - otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi deleted file mode 100644 index 3253c640341..00000000000 --- a/arch/arm/dts/rk3128.dtsi +++ /dev/null @@ -1,780 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3128-cru.h> - -/ { - compatible = "rockchip,rk3128"; - rockchip,sram = <&sram>; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - spi0 = &spi0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3128-smp"; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - }; - }; - - cpu_axi_bus: cpu_axi_bus { - compatible = "rockchip,cpu_axi_bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - qos { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - crypto { - reg = <0x10128080 0x20>; - }; - - core { - reg = <0x1012a000 0x20>; - }; - - peri { - reg = <0x1012c000 0x20>; - }; - - gpu { - reg = <0x1012d000 0x20>; - }; - - vpu { - reg = <0x1012e000 0x20>; - }; - - rga { - reg = <0x1012f000 0x20>; - }; - ebc { - reg = <0x1012f080 0x20>; - }; - - iep { - reg = <0x1012f100 0x20>; - }; - - lcdc { - reg = <0x1012f180 0x20>; - rockchip,priority = <3 3>; - }; - - vip { - reg = <0x1012f200 0x20>; - rockchip,priority = <3 3>; - }; - }; - - msch { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - msch@10128000 { - reg = <0x10128000 0x20>; - rockchip,read-latency = <0x3f>; - }; - }; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - migrate = <0x84000005>; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - ranges; - - pdma: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - arm,pl330-broken-no-flushp;//2 - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin12m: xin12m { - compatible = "fixed-clock"; - clock-frequency = <12000000>; - clock-output-names = "xin12m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - timer@20044000 { - compatible = "arm,armv7-timer"; - reg = <0x20044000 0xb8>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - rockchip,broadcast = <1>; - }; - - watchdog: watchdog@2004c000 { - compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; - reg = <0x2004c000 0x100>; - clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - rockchip,irq = <1>; - rockchip,timeout = <60>; - rockchip,atboot = <1>; - rockchip,debug = <0>; - }; - - reset: reset@20000110 { - compatible = "rockchip,reset"; - reg = <0x20000110 0x24>; - #reset-cells = <1>; - }; - - nandc: nand-controller@10500000 { - compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; - reg = <0x10500000 0x4000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>; - clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; - clock-names = "ahb", "nfc"; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3128-cru"; - reg = <0x20000000 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - dmas = <&pdma 2>, <&pdma 3>; - #dma-cells = <2>; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - dmas = <&pdma 4>, <&pdma 5>; - #dma-cells = <2>; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - dmas = <&pdma 6>, <&pdma 7>; - #dma-cells = <2>; - }; - - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050000 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050010 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; - }; - - sram: sram@10080400 { - compatible = "rockchip,rk3128-smp-sram", "mmio-sram"; - reg = <0x10080400 0x1C00>; - map-exec; - map-cacheable; - }; - - pmu: syscon@100a0000 { - compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; - reg = <0x100a0000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - reg = <0x10139000 0x1000>, - <0x1013a000 0x1000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = <GIC_PPI 9 0xf04>; - }; - - u2phy: usb2phy { - compatible = "rockchip,rk3128-usb2phy"; - reg = <0x017c 0x0c>; - rockchip,grf = <&grf>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "usb480m_phy"; - status = "disabled"; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - status = "disabled"; - }; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host_ehci: usb@101c0000 { - compatible = "generic-ehci"; - reg = <0x101c0000 0x20000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host_ohci: usb@101e0000 { - compatible = "generic-ohci"; - reg = <0x101e0000 0x20000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - phys = <&u2phy_host>; - phy-names = "usb"; - status = "disabled"; - }; - - sdmmc: mmc@10214000 { - compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - max-frequency = <150000000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - bus-width = <4>; - status = "disabled"; - }; - - emmc: mmc@1021c000 { - compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x1021c000 0x4000>; - max-frequency = <150000000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - default-sample-phase = <158>; - num-slots = <1>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - i2c0: i2c@20072000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <20072000 0x1000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - }; - - i2c2: i2c@2005a000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005a000 0x1000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - }; - - i2c3: i2c@2005e000 { - compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; - reg = <0x2005e000 0x1000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - }; - - spi0: spi@20074000 { - compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; - reg = <0x20074000 0x1000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>; - rockchip,spi-src-clk = <0>; - num-cs = <2>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&pdma 8>, <&pdma 9>; - #dma-cells = <2>; - dma-names = "tx", "rx"; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3128-grf", "syscon"; - reg = <0x20008000 0x1000>; - }; - - pinctrl: pinctrl@20008000 { - compatible = "rockchip,rk3128-pinctrl"; - reg = <0x20008000 0xA8>, - <0x200080A8 0x4C>, - <0x20008118 0x20>, - <0x20008100 0x04>; - reg-names = "base", "mux", "pull", "drv"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@20088000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20088000 0x100>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, - <1 RK_PD1 2 &pcfg_pull_none>, - <1 RK_PD2 2 &pcfg_pull_none>, - <1 RK_PD3 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>, - <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD6 2 &pcfg_pull_none>, - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - nandc{ - nandc_ale:nandc-ale { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_cle:nandc-cle { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_wrn:nandc-wrn { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_rdn:nandc-rdn { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_rdy:nandc-rdy { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_cs0:nandc-cs0 { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - nandc_data: nandc-data { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>, - <0 RK_PC1 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>, - <2 RK_PC7 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>; - }; - - sdmmc_wp: sdmmc-wp { - rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>; - }; - - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>, - <1 RK_PC3 1 &pcfg_pull_up>, - <1 RK_PC4 1 &pcfg_pull_up>, - <1 RK_PC5 1 &pcfg_pull_up>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, - <2 RK_PC5 3 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_txd_mux0:spi0-txd-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_rxd_mux0:spi0-rxd-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_clk_mux0:spi0-clk-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_cs0_mux0:spi0-cs0-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - - spi0_cs1_mux0:spi0-cs1-mux0 { - rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; - }; - }; - - }; -}; diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts deleted file mode 100644 index 797476e8bef..00000000000 --- a/arch/arm/dts/rk3229-evb.dts +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include <dt-bindings/input/input.h> -#include "rk3229.dtsi" - -/ { - model = "Rockchip RK3229 Evaluation board"; - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - - aliases { - mmc0 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - ext_gmac: ext_gmac { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vccio_1v8>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vccio_1v8: vccio-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vccio_3v3: vccio-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - gpio_keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power_key: power-key { - label = "GPIO Key Power"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - debounce-interval = <100>; - wakeup-source; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_3v3>; - vccio2-supply = <&vccio_1v8>; - vccio4-supply = <&vccio_3v3>; -}; - -&pinctrl { - keys { - pwr_key: pwr-key { - rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_ehci { - status = "okay"; -}; - -&usb_host2_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3229.dtsi b/arch/arm/dts/rk3229.dtsi deleted file mode 100644 index c340fb30e77..00000000000 --- a/arch/arm/dts/rk3229.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include "rk322x.dtsi" - -/ { - compatible = "rockchip,rk3229"; - - /delete-node/ opp-table0; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1325000>; - }; - opp-1392000000 { - opp-hz = /bits/ 64 <1392000000>; - opp-microvolt = <1375000>; - }; - opp-1464000000 { - opp-hz = /bits/ 64 <1464000000>; - opp-microvolt = <1400000>; - }; - }; -}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi deleted file mode 100644 index 8eed9e3a92e..00000000000 --- a/arch/arm/dts/rk322x.dtsi +++ /dev/null @@ -1,1293 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3228-cru.h> -#include <dt-bindings/thermal/thermal.h> -#include <dt-bindings/power/rk3228-power.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &spi0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - enable-method = "psci"; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - i2s1: i2s1@100b0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100b0000 0x4000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - dmas = <&pdma 14>, <&pdma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s0: i2s0@100c0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100c0000 0x4000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - dmas = <&pdma 11>, <&pdma 12>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spdif: spdif@100d0000 { - compatible = "rockchip,rk3228-spdif"; - reg = <0x100d0000 0x1000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; - clock-names = "mclk", "hclk"; - dmas = <&pdma 10>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - i2s2: i2s2@100e0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100e0000 0x4000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - grf: syscon@11000000 { - compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; - reg = <0x11000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rk3228-io-voltage-domain"; - status = "disabled"; - }; - - power: power-controller { - compatible = "rockchip,rk3228-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3228_PD_VIO { - reg = <RK3228_PD_VIO>; - clocks = <&cru ACLK_HDCP>, - <&cru SCLK_HDCP>, - <&cru ACLK_IEP>, - <&cru HCLK_IEP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>, - <&cru SCLK_RGA>; - pm_qos = <&qos_hdcp>, - <&qos_iep>, - <&qos_rga_r>, - <&qos_rga_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VOP { - reg = <RK3228_PD_VOP>; - clocks =<&cru ACLK_VOP>, - <&cru DCLK_VOP>, - <&cru HCLK_VOP>; - pm_qos = <&qos_vop>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VPU { - reg = <RK3228_PD_VPU>; - clocks = <&cru ACLK_VPU>, - <&cru HCLK_VPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_RKVDEC { - reg = <RK3228_PD_RKVDEC>; - clocks = <&cru ACLK_RKVDEC>, - <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - pm_qos = <&qos_rkvdec_r>, - <&qos_rkvdec_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_GPU { - reg = <RK3228_PD_GPU>; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; - - u2phy0: usb2phy@760 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0760 0x0c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - #clock-cells = <0>; - status = "disabled"; - - u2phy0_otg: otg-port { - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0_host: host-port { - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - u2phy1: usb2phy@800 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0800 0x0c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - #clock-cells = <0>; - status = "disabled"; - - u2phy1_otg: otg-port { - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy1_host: host-port { - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - efuse: efuse@11040000 { - compatible = "rockchip,rk3228-efuse"; - reg = <0x11040000 0x20>; - clocks = <&cru PCLK_EFUSE_256>; - clock-names = "pclk_efuse"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x7 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - spi0: spi@11090000 { - compatible = "rockchip,rk3228-spi"; - reg = <0x11090000 0x1000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; - status = "disabled"; - }; - - wdt: watchdog@110a0000 { - compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; - reg = <0x110a0000 0x100>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_CPU>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - <&cru PLL_GPLL>, <&cru ARMCLK>, - <&cru PLL_CPLL>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>; - assigned-clock-rates = - <594000000>, <816000000>, - <500000000>, <150000000>, - <150000000>, <75000000>, - <150000000>, <150000000>, - <75000000>; - }; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <32768>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - hdmi_phy: hdmi-phy@12030000 { - compatible = "rockchip,rk3228-hdmi-phy"; - reg = <0x12030000 0x10000>; - clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - #clock-cells = <0>; - clock-output-names = "hdmiphy_phy"; - #phy-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@20000000 { - compatible = "rockchip,rk3228-mali", "arm,mali-400"; - reg = <0x20000000 0x10000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - power-domains = <&power RK3228_PD_GPU>; - resets = <&cru SRST_GPU_A>; - status = "disabled"; - }; - - vpu: video-codec@20020000 { - compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; - reg = <0x20020000 0x800>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3228_PD_VPU>; - }; - - vpu_mmu: iommu@20020800 { - compatible = "rockchip,iommu"; - reg = <0x20020800 0x100>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VPU>; - #iommu-cells = <0>; - }; - - vdec: video-codec@20030000 { - compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; - reg = <0x20030000 0x480>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; - assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <300000000>, <300000000>; - iommus = <&vdec_mmu>; - power-domains = <&power RK3228_PD_RKVDEC>; - }; - - vdec_mmu: iommu@20030480 { - compatible = "rockchip,iommu"; - reg = <0x20030480 0x40>, <0x200304c0 0x40>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_RKVDEC>; - #iommu-cells = <0>; - }; - - vop: vop@20050000 { - compatible = "rockchip,rk3228-vop"; - reg = <0x20050000 0x1ffc>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - power-domains = <&power RK3228_PD_VOP>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@20053f00 { - compatible = "rockchip,iommu"; - reg = <0x20053f00 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VOP>; - #iommu-cells = <0>; - status = "disabled"; - }; - - rga: rga@20060000 { - compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; - reg = <0x20060000 0x1000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk", "hclk", "sclk"; - power-domains = <&power RK3228_PD_VIO>; - resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; - reset-names = "core", "axi", "ahb"; - }; - - iep_mmu: iommu@20070800 { - compatible = "rockchip,iommu"; - reg = <0x20070800 0x100>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@200a0000 { - compatible = "rockchip,rk3228-dw-hdmi"; - reg = <0x200a0000 0x20000>; - reg-io-width = <4>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - assigned-clocks = <&cru SCLK_HDMI_PHY>; - assigned-clock-parents = <&hdmi_phy>; - clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; - clock-names = "isfr", "iahb", "cec"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; - resets = <&cru SRST_HDMI_P>; - reset-names = "hdmi"; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - }; - - sdmmc: mmc@30000000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30000000 0x4000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "disabled"; - }; - - sdio: mmc@30010000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30010000 0x4000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; - status = "disabled"; - }; - - emmc: mmc@30020000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - rockchip,default-sample-phase = <158>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - usb_otg: usb@30040000 { - compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30040000 0x40000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ehci: usb@30080000 { - compatible = "generic-ehci"; - reg = <0x30080000 0x20000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@300a0000 { - compatible = "generic-ohci"; - reg = <0x300a0000 0x20000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@300c0000 { - compatible = "generic-ehci"; - reg = <0x300c0000 0x20000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@300e0000 { - compatible = "generic-ohci"; - reg = <0x300e0000 0x20000>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ehci: usb@30100000 { - compatible = "generic-ehci"; - reg = <0x30100000 0x20000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ohci: usb@30120000 { - compatible = "generic-ohci"; - reg = <0x30120000 0x20000>; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rk3228-gmac"; - reg = <0x30200000 0x10000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - qos_iep: qos@31030080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030080 0x20>; - }; - - qos_rga_w: qos@31030100 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030100 0x20>; - }; - - qos_hdcp: qos@31030180 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030180 0x20>; - }; - - qos_rga_r: qos@31030200 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030200 0x20>; - }; - - qos_vpu: qos@31040000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31040000 0x20>; - }; - - qos_gpu: qos@31050000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31050000 0x20>; - }; - - qos_vop: qos@31060000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31060000 0x20>; - }; - - qos_rkvdec_r: qos@31070000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070000 0x20>; - }; - - qos_rkvdec_w: qos@31070080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070080 0x20>; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, - <1 RK_PD1 2 &pcfg_pull_none>, - <1 RK_PD2 2 &pcfg_pull_none>, - <1 RK_PD3 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>, - <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD6 2 &pcfg_pull_none>, - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC5 2 &pcfg_pull_none>, - <2 RK_PC4 2 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - phy_pins: phy-pins { - rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, - <2 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, - <0 RK_PA7 2 &pcfg_pull_none>; - }; - - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, - <0 RK_PB1 1 &pcfg_pull_none>, - <0 RK_PB3 1 &pcfg_pull_none>, - <0 RK_PB4 1 &pcfg_pull_none>, - <0 RK_PB5 1 &pcfg_pull_none>, - <0 RK_PB6 1 &pcfg_pull_none>, - <1 RK_PA2 2 &pcfg_pull_none>, - <1 RK_PA4 2 &pcfg_pull_none>, - <1 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, - <2 RK_PD3 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - uart21_xfer: uart21-xfer { - rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi index a18d33b3d36..31345df6295 100644 --- a/arch/arm/dts/rk3528-u-boot.dtsi +++ b/arch/arm/dts/rk3528-u-boot.dtsi @@ -23,7 +23,7 @@ reg = <0x0 0xffc50000 0x0 0x200>; }; - otp: nvmem@ffce0000 { + otp: efuse@ffce0000 { compatible = "rockchip,rk3528-otp"; reg = <0x0 0xffce0000 0x0 0x4000>; }; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 738b9673d35..d09dab35b31 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -21,15 +21,9 @@ bootph-all; }; - otp: nvmem@fe38c000 { + otp: efuse@fe38c000 { compatible = "rockchip,rk3568-otp"; reg = <0x0 0xfe38c000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - cpu_id: id@a { - reg = <0x0a 0x10>; - }; }; }; diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index 018c9cc8d69..8db9495c6d4 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -12,7 +12,7 @@ }; chosen { - u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci, &ufshc; }; dmc { @@ -81,6 +81,17 @@ bootph-some-ram; }; +#ifdef CONFIG_SPL_UFS_SUPPORT +&gpio4 { + /* This is specifically for GPIO4_D0, which is the only 1.2V capable + * pin on RK3576 available for use as the UFS device reset, thus + * &gpio4 is required for booting from UFS on RK3576. + */ + bootph-pre-ram; + bootph-some-ram; +}; +#endif + &ioc_grf { bootph-all; }; @@ -89,6 +100,11 @@ bootph-some-ram; }; +&pcfg_pull_down { + bootph-pre-ram; + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; @@ -172,6 +188,21 @@ bootph-pre-ram; }; +&ufshc { + bootph-pre-ram; + bootph-some-ram; +}; + +&ufs_refclk { + bootph-pre-ram; + bootph-some-ram; +}; + +&ufs_rstgpio { + bootph-pre-ram; + bootph-some-ram; +}; + &xin24m { bootph-all; }; diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi index dcda4f99d6e..0fbbb50fc5a 100644 --- a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi +++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi @@ -21,6 +21,12 @@ bootph-some-ram; }; +&gpio0 { + /* Need gpio0 in SPL for spl_board_init() to control GPIO0_D0 */ + /* TODO: once we have a U-Boot TPL, use bootph-pre-sram; */ + bootph-pre-ram; +}; + &gpio2 { bootph-pre-ram; bootph-some-ram; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index e07b549c767..ddc177344eb 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -19,33 +19,6 @@ bootph-some-ram; }; -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4m1_xfer>; - status = "okay"; - - usbc0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio3>; - interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - status = "okay"; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "sink"; - try-power-role = "sink"; - op-sink-microwatt = <1000000>; - sink-pdos = - <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>, - <PDO_VAR(5000, 20000, 5000)>; - }; - }; -}; - &saradc { bootph-pre-ram; vdd-microvolts = <1800000>; @@ -63,20 +36,6 @@ }; }; -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; +&usbc0 { status = "okay"; }; diff --git a/arch/arm/dts/rz-g2-beacon-u-boot.dtsi b/arch/arm/dts/rz-g2-beacon-u-boot.dtsi index 84416fceaff..97c4d4d292a 100644 --- a/arch/arm/dts/rz-g2-beacon-u-boot.dtsi +++ b/arch/arm/dts/rz-g2-beacon-u-boot.dtsi @@ -47,7 +47,6 @@ &rpc { pinctrl-0 = <&qspi_pins>; pinctrl-names = "default"; - num-cs = <1>; spi-max-frequency = <40000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/sc573-ezkit.dts b/arch/arm/dts/sc573-ezlite.dts index 4a3d1ed5c56..f128c4f9697 100644 --- a/arch/arm/dts/sc573-ezkit.dts +++ b/arch/arm/dts/sc573-ezlite.dts @@ -9,11 +9,13 @@ #include "sc57x.dtsi" / { - model = "ADI SC573-EZKIT"; - compatible = "adi,sc573-ezkit", "adi,sc57x"; + model = "ADI SC573-EZLITE"; + compatible = "adi,sc573-ezlite", "adi,sc57x"; }; &i2c0 { + status = "okay"; + gpio_expander0: mcp23017@21 { compatible = "microchip,mcp23017"; reg = <0x21>; diff --git a/arch/arm/dts/sc584-ezkit.dts b/arch/arm/dts/sc584-ezkit.dts index 176faa50672..3a6d60b3f29 100644 --- a/arch/arm/dts/sc584-ezkit.dts +++ b/arch/arm/dts/sc584-ezkit.dts @@ -13,6 +13,8 @@ }; &i2c2 { + status = "okay"; + gpio_expander0: mcp23017@21 { compatible = "microchip,mcp23017"; reg = <0x21>; diff --git a/arch/arm/dts/sc589-ezkit.dts b/arch/arm/dts/sc589-ezkit.dts index d8eb5b6f8fe..04ad8e44cbb 100644 --- a/arch/arm/dts/sc589-ezkit.dts +++ b/arch/arm/dts/sc589-ezkit.dts @@ -17,6 +17,8 @@ &i2c0 { #address-cells = <1>; #size-cells = <0>; + status = "okay"; + gpio_expander0: mcp23017@21 { compatible = "microchip,mcp23017"; reg = <0x21>; diff --git a/arch/arm/dts/sc594-som-ezkit.dts b/arch/arm/dts/sc594-som-ezkit.dts index dea9a6e27f2..396502b6745 100644 --- a/arch/arm/dts/sc594-som-ezkit.dts +++ b/arch/arm/dts/sc594-som-ezkit.dts @@ -130,7 +130,7 @@ gige-reset { gpio-hog; - gpios = <15 GPIO_ACTIVE_HIGH>; + gpios = <15 GPIO_ACTIVE_LOW>; output-high; line-name = "gige-reset"; bootph-pre-ram; diff --git a/arch/arm/dts/sc594-som.dtsi b/arch/arm/dts/sc594-som.dtsi index 1c2adc601dd..c4373aea60f 100644 --- a/arch/arm/dts/sc594-som.dtsi +++ b/arch/arm/dts/sc594-som.dtsi @@ -79,6 +79,7 @@ &i2c2 { clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>; + status = "okay"; som_gpio_expander: mcp23017@21 { compatible = "microchip,mcp23017"; @@ -153,6 +154,18 @@ }; }; +&i2c3 { + clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>; +}; + +&i2c4 { + clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>; +}; + +&i2c5 { + clocks = <&clk ADSP_SC594_CLK_CGU0_SCLK0>; +}; + &ospi { status = "okay"; diff --git a/arch/arm/dts/sc598-som-revD.dtsi b/arch/arm/dts/sc598-som-revD.dtsi index 26e272966ff..06d550b8532 100644 --- a/arch/arm/dts/sc598-som-revD.dtsi +++ b/arch/arm/dts/sc598-som-revD.dtsi @@ -8,6 +8,8 @@ #include "sc598-som.dtsi" &i2c2 { + status = "okay"; + som_gpio_expander: mcp23018@20 { compatible = "microchip,mcp23018"; reg = <0x20>; diff --git a/arch/arm/dts/sc598-som-revE.dtsi b/arch/arm/dts/sc598-som-revE.dtsi index bec504102e7..1f48d52109b 100644 --- a/arch/arm/dts/sc598-som-revE.dtsi +++ b/arch/arm/dts/sc598-som-revE.dtsi @@ -8,6 +8,8 @@ #include "sc598-som.dtsi" &i2c2 { + status = "okay"; + som_gpio_expander: adp5587@34 { compatible = "adi,adp5587"; reg = <0x34>; diff --git a/arch/arm/dts/sc598-som.dtsi b/arch/arm/dts/sc598-som.dtsi index bc212ef25cb..ac1f24c86c3 100644 --- a/arch/arm/dts/sc598-som.dtsi +++ b/arch/arm/dts/sc598-som.dtsi @@ -138,6 +138,18 @@ clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>; }; +&i2c3 { + clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>; +}; + +&i2c4 { + clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>; +}; + +&i2c5 { + clocks = <&clk ADSP_SC598_CLK_CGU0_SCLK0>; +}; + &spi2 { clocks = <&clk ADSP_SC598_CLK_SPI>; }; diff --git a/arch/arm/dts/sc59x.dtsi b/arch/arm/dts/sc59x.dtsi index ff279cca2d1..64e5a1afc53 100644 --- a/arch/arm/dts/sc59x.dtsi +++ b/arch/arm/dts/sc59x.dtsi @@ -86,6 +86,36 @@ pinctrl-0 = <&usb0_default>; status = "disabled"; }; + + i2c3: i2c3@31001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi-i2c"; + reg = <0x31001000 0x100>; + clock-names = "i2c"; + status = "disabled"; + bootph-pre-ram; + }; + + i2c4: i2c4@31001100 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi-i2c"; + reg = <0x31001100 0x100>; + clock-names = "i2c"; + status = "disabled"; + bootph-pre-ram; + }; + + i2c5: i2c5@31001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi-i2c"; + reg = <0x31001200 0x100>; + clock-names = "i2c"; + status = "disabled"; + bootph-pre-ram; + }; }; }; diff --git a/arch/arm/dts/sc5xx.dtsi b/arch/arm/dts/sc5xx.dtsi index 9d346ae62e0..b821deddda7 100644 --- a/arch/arm/dts/sc5xx.dtsi +++ b/arch/arm/dts/sc5xx.dtsi @@ -25,47 +25,6 @@ bootph-pre-ram; }; -#ifdef CONFIG_SC5XX_USE_BINMAN - binman { - filename = CONFIG_SC5XX_BINMAN_FILENAME; - stage1-boot { - offset = <CONFIG_SC5XX_UBOOT_SPL_OFFSET>; - type = "blob-ext"; - filename = "spl/u-boot-spl.ldr"; - }; - - /* since falcon mode can jump from SPL to OS directly - * full u-boot is optional - * - * @todo: review if we can say this given support has - * not yet been upstreamed. Otherwise we might have to - * invoke binman only for full u-boot. - */ - stage2-boot { - offset = <CONFIG_SC5XX_UBOOT_OFFSET>; - type = "blob-ext"; - filename = "u-boot.ldr"; - optional; - }; - -#ifdef CONFIG_SC5XX_FITIMAGE_NAME - fitImage { - offset = <CONFIG_SC5XX_FITIMAGE_OFFSET>; - type = "blob-ext"; - filename = CONFIG_SC5XX_FITIMAGE_NAME; - }; -#endif - -#ifdef CONFIG_SC5XX_ROOTFS_NAME - rfs { - offset = <CONFIG_SC5XX_ROOTFS_OFFSET>; - type = "blob-ext"; - filename = CONFIG_SC5XX_ROOTFS_NAME; - }; -#endif - }; -#endif - clocks { dummy: dummy { compatible = "fixed-clock"; @@ -181,9 +140,9 @@ #address-cells = <1>; #size-cells = <0>; compatible = "adi-i2c"; - reg = <0x31001400 0x1000>; + reg = <0x31001400 0x100>; clock-names = "i2c"; - status = "okay"; + status = "disabled"; bootph-pre-ram; }; @@ -191,9 +150,9 @@ #address-cells = <1>; #size-cells = <0>; compatible = "adi-i2c"; - reg = <0x31001500 0x1000>; + reg = <0x31001500 0x100>; clock-names = "i2c"; - status = "okay"; + status = "disabled"; bootph-pre-ram; }; @@ -201,9 +160,9 @@ #address-cells = <1>; #size-cells = <0>; compatible = "adi-i2c"; - reg = <0x31001600 0x1000>; + reg = <0x31001600 0x100>; clock-names = "i2c"; - status = "okay"; + status = "disabled"; bootph-pre-ram; }; }; diff --git a/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi index 79494ecad90..600316205fc 100644 --- a/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi @@ -21,6 +21,13 @@ pinctrl1 = &pinctrl_z; }; + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + timeout-sec = <32>; + status = "okay"; + }; + binman: binman { multiple-images; }; @@ -103,7 +110,7 @@ }; &iwdg2 { - bootph-all; + status = "disabled"; }; /* pre-reloc probe = reserve video frame buffer in video_reserve() */ diff --git a/arch/arm/dts/t8103-j274-u-boot.dtsi b/arch/arm/dts/t8103-j274-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j274-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j274.dts b/arch/arm/dts/t8103-j274.dts deleted file mode 100644 index 9bc592bcdbf..00000000000 --- a/arch/arm/dts/t8103-j274.dts +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple Mac mini (M1, 2020) - * - * target-type: J274 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j274", "apple,t8103", "apple,arm-platform"; - model = "Apple Mac mini (M1, 2020)"; - - aliases { - ethernet0 = ðernet0; - }; -}; - -&wifi0 { - brcm,board-type = "apple,atlantisb"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Back-left"; -}; - -&typec1 { - label = "USB-C Back-right"; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ - -&port01 { - bus-range = <2 2>; -}; - -&port02 { - bus-range = <3 3>; - ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 10 18 00 00 00]; - }; -}; - -&i2c1 { - clock-frequency = <50000>; - - speaker_amp: codec@31 { - compatible = "ti,tas5770l", "ti,tas2770"; - reg = <0x31>; - reset-gpios = <&pinctrl_ap 181 GPIO_ACTIVE_HIGH>; - #sound-dai-cells = <0>; - }; -}; - -&i2c2 { - status = "okay"; - - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Mac mini integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - format = "left_j"; - tdm-slot-width = <32>; - mclk-fs = <64>; - - link0_cpu: cpu { - sound-dai = <&mca 0>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&speaker_amp>; - }; - }; - - simple-audio-card,dai-link@1 { - bitclock-inversion; - frame-inversion; - reg = <1>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link1_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link1_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j293-u-boot.dtsi b/arch/arm/dts/t8103-j293-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j293-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j293.dts b/arch/arm/dts/t8103-j293.dts deleted file mode 100644 index de1a21d97cd..00000000000 --- a/arch/arm/dts/t8103-j293.dts +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple MacBook Pro (13-inch, M1, 2020) - * - * target-type: J293 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; - model = "Apple MacBook Pro (13-inch, M1, 2020)"; -}; - -&wifi0 { - brcm,board-type = "apple,honshu"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Left-back"; -}; - -&typec1 { - label = "USB-C Left-front"; -}; - -&spi3 { - status = "okay"; - - hid-transport@0 { - compatible = "apple,spi-hid-transport"; - reg = <0>; - spi-max-frequency = <8000000>; - /* - * cs-setup and cs-hold delays are derived from Apple's ADT - * Mac OS driver meta data secify 45 us for 'cs to clock' and - * 'clock to cs' delays. - */ - spi-cs-setup-delay-ns = <20000>; - spi-cs-hold-delay-ns = <20000>; - spi-cs-inactive-delay-ns = <250000>; - spien-gpios = <&pinctrl_ap 195 0>; - interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* - * Remove unused PCIe ports and disable the associated DARTs. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -&pcie0_dart_2 { - status = "disabled"; -}; - -/delete-node/ &port01; -/delete-node/ &port02; - -&i2c2 { - status = "okay"; - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -&i2c4 { - status = "okay"; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "MacBook integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j313-u-boot.dtsi b/arch/arm/dts/t8103-j313-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j313-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j313.dts b/arch/arm/dts/t8103-j313.dts deleted file mode 100644 index 5efe8d7a63b..00000000000 --- a/arch/arm/dts/t8103-j313.dts +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple MacBook Air (M1, 2020) - * - * target-type: J313 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j313", "apple,t8103", "apple,arm-platform"; - model = "Apple MacBook Air (M1, 2020)"; -}; - -&wifi0 { - brcm,board-type = "apple,shikoku"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Left-back"; -}; - -&typec1 { - label = "USB-C Left-front"; -}; - -&spi3 { - status = "okay"; - - hid-transport@0 { - compatible = "apple,spi-hid-transport"; - reg = <0>; - spi-max-frequency = <8000000>; - /* - * cs-setup and cs-hold delays are derived from Apple's ADT - * Mac OS driver meta data secify 45 us for 'cs to clock' and - * 'clock to cs' delays. - */ - spi-cs-setup-delay-ns = <20000>; - spi-cs-hold-delay-ns = <20000>; - spi-cs-inactive-delay-ns = <250000>; - spien-gpios = <&pinctrl_ap 195 0>; - interrupts-extended = <&pinctrl_nub 13 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* - * Remove unused PCIe ports and disable the associated DARTs. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -&pcie0_dart_2 { - status = "disabled"; -}; - -/delete-node/ &port01; -/delete-node/ &port02; - -&i2c3 { - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "MacBook integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j456-u-boot.dtsi b/arch/arm/dts/t8103-j456-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j456-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j456.dts b/arch/arm/dts/t8103-j456.dts deleted file mode 100644 index 8624168bdb7..00000000000 --- a/arch/arm/dts/t8103-j456.dts +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple iMac (24-inch, 4x USB-C, M1, 2020) - * - * target-type: J456 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j456", "apple,t8103", "apple,arm-platform"; - model = "Apple iMac (24-inch, 4x USB-C, M1, 2020)"; - - aliases { - ethernet0 = ðernet0; - }; -}; - -&wifi0 { - brcm,board-type = "apple,capri"; -}; - -&i2c0 { - hpm2: usb-pd@3b { - compatible = "apple,cd321x"; - reg = <0x3b>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - }; - - hpm3: usb-pd@3c { - compatible = "apple,cd321x"; - reg = <0x3c>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - }; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Back-right"; -}; - -&typec1 { - label = "USB-C Back-right-middle"; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ - -&port01 { - bus-range = <2 2>; -}; - -&port02 { - bus-range = <3 3>; - ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 10 18 00 00 00]; - }; -}; - -&i2c1 { - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "iMac integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-j457-u-boot.dtsi b/arch/arm/dts/t8103-j457-u-boot.dtsi deleted file mode 100644 index 6c8dd5a56f8..00000000000 --- a/arch/arm/dts/t8103-j457-u-boot.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "t8103-u-boot.dtsi" diff --git a/arch/arm/dts/t8103-j457.dts b/arch/arm/dts/t8103-j457.dts deleted file mode 100644 index f3eec8d4729..00000000000 --- a/arch/arm/dts/t8103-j457.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple iMac (24-inch, 2x USB-C, M1, 2020) - * - * target-type: J457 - * - * Copyright The Asahi Linux Contributors - */ - -/dts-v1/; - -#include "t8103.dtsi" -#include "t8103-jxxx.dtsi" - -/ { - compatible = "apple,j457", "apple,t8103", "apple,arm-platform"; - model = "Apple iMac (24-inch, 2x USB-C, M1, 2020)"; - - aliases { - ethernet0 = ðernet0; - }; -}; - -&wifi0 { - brcm,board-type = "apple,santorini"; -}; - -/* - * Provide labels for the USB type C ports. - */ - -&typec0 { - label = "USB-C Back-right"; -}; - -&typec1 { - label = "USB-C Back-left"; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ - -&port02 { - bus-range = <3 3>; - ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 10 18 00 00 00]; - }; -}; - -/* - * Remove unused PCIe port and disable the associated DART. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -/delete-node/ &port01; - -&i2c1 { - clock-frequency = <50000>; - - jack_codec: codec@48 { - compatible = "cirrus,cs42l83", "cirrus,cs42l42"; - reg = <0x48>; - reset-gpios = <&pinctrl_nub 11 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <183 IRQ_TYPE_LEVEL_LOW>; - #sound-dai-cells = <0>; - cirrus,ts-inv = <1>; - }; -}; - -/ { - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "iMac integrated audio"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - bitclock-inversion; - frame-inversion; - reg = <0>; - format = "i2s"; - mclk-fs = <64>; - tdm-slot-width = <32>; - - link0_cpu: cpu { - sound-dai = <&mca 2>; - bitclock-master; - frame-master; - }; - - link0_codec: codec { - sound-dai = <&jack_codec>; - }; - }; - }; -}; diff --git a/arch/arm/dts/t8103-jxxx.dtsi b/arch/arm/dts/t8103-jxxx.dtsi deleted file mode 100644 index b4bd8c4238a..00000000000 --- a/arch/arm/dts/t8103-jxxx.dtsi +++ /dev/null @@ -1,143 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple M1 Mac mini, MacBook Air/Pro, iMac 24" (M1, 2020/2021) - * - * This file contains parts common to all Apple M1 devices using the t8103. - * - * target-type: J274, J293, J313, J456, J457 - * - * Copyright The Asahi Linux Contributors - */ - -#include <dt-bindings/spmi/spmi.h> - -/ { - aliases { - serial0 = &serial0; - serial2 = &serial2; - wifi0 = &wifi0; - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - stdout-path = "serial0"; - - framebuffer0: framebuffer@0 { - compatible = "apple,simple-framebuffer", "simple-framebuffer"; - reg = <0 0 0 0>; /* To be filled by loader */ - /* Format properties will be added by loader */ - status = "disabled"; - }; - }; - - memory@800000000 { - device_type = "memory"; - reg = <0x8 0 0x2 0>; /* To be filled by loader */ - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - hpm0: usb-pd@38 { - compatible = "apple,cd321x"; - reg = <0x38>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - typec0: connector { - compatible = "usb-c-connector"; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - typec0_con_hs: endpoint { - remote-endpoint = <&typec0_usb_hs>; - }; - }; - }; - }; - }; - - hpm1: usb-pd@3f { - compatible = "apple,cd321x"; - reg = <0x3f>; - interrupt-parent = <&pinctrl_ap>; - interrupts = <106 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; - - typec1: connector { - compatible = "usb-c-connector"; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - typec1_con_hs: endpoint { - remote-endpoint = <&typec1_usb_hs>; - }; - }; - }; - }; - }; -}; - -/* USB controllers */ -&dwc3_0 { - port { - typec0_usb_hs: endpoint { - remote-endpoint = <&typec0_con_hs>; - }; - }; -}; - -&dwc3_1 { - port { - typec1_usb_hs: endpoint { - remote-endpoint = <&typec1_con_hs>; - }; - }; -}; - -/* - * Force the bus number assignments so that we can declare some of the - * on-board devices and properties that are populated by the bootloader - * (such as MAC addresses). - */ -&port00 { - bus-range = <1 1>; - pwren-gpios = <&smc 13 0>; - wifi0: network@0,0 { - compatible = "pci14e4,4425"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - /* To be filled by the loader */ - local-mac-address = [00 00 00 00 00 00]; - apple,antenna-sku = "XX"; - }; -}; - -&spmi { - status = "okay"; - - pmu@f { - compatible = "apple,sera-pmu"; - reg = <0xf SPMI_USID>; - }; -}; diff --git a/arch/arm/dts/t8103-pmgr.dtsi b/arch/arm/dts/t8103-pmgr.dtsi deleted file mode 100644 index 82ea4aa322e..00000000000 --- a/arch/arm/dts/t8103-pmgr.dtsi +++ /dev/null @@ -1,1138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * PMGR Power domains for the Apple T8103 "M1" SoC - * - * Copyright The Asahi Linux Contributors - */ - - -&pmgr { - ps_sbr: power-controller@100 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x100 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sbr"; - apple,always-on; /* Core device */ - }; - - ps_aic: power-controller@108 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x108 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "aic"; - apple,always-on; /* Core device */ - }; - - ps_dwi: power-controller@110 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x110 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dwi"; - apple,always-on; /* Core device */ - }; - - ps_soc_spmi0: power-controller@118 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x118 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_spmi0"; - }; - - ps_soc_spmi1: power-controller@120 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x120 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_spmi1"; - }; - - ps_soc_spmi2: power-controller@128 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x128 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_spmi2"; - }; - - ps_gpio: power-controller@130 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x130 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "gpio"; - }; - - ps_pms_busif: power-controller@138 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x138 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_busif"; - apple,always-on; /* Core device */ - }; - - ps_pms: power-controller@140 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x140 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms"; - apple,always-on; /* Core device */ - }; - - ps_pms_fpwm0: power-controller@148 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x148 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm0"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm1: power-controller@150 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x150 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm1"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm2: power-controller@158 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x158 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm2"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm3: power-controller@160 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x160 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm3"; - power-domains = <&ps_pms>; - }; - - ps_pms_fpwm4: power-controller@168 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x168 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_fpwm4"; - power-domains = <&ps_pms>; - }; - - ps_soc_dpe: power-controller@170 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x170 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "soc_dpe"; - apple,always-on; /* Core device */ - }; - - ps_pmgr_soc_ocla: power-controller@178 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x178 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pmgr_soc_ocla"; - }; - - ps_ispsens0: power-controller@180 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x180 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens0"; - }; - - ps_ispsens1: power-controller@188 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x188 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens1"; - }; - - ps_ispsens2: power-controller@190 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x190 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens2"; - }; - - ps_ispsens3: power-controller@198 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x198 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ispsens3"; - }; - - ps_pcie_ref: power-controller@1a0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1a0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pcie_ref"; - }; - - ps_aft0: power-controller@1a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1a8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "aft0"; - }; - - ps_devc0_ivdmc: power-controller@1b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1b0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "devc0_ivdmc"; - }; - - ps_imx: power-controller@1b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1b8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "imx"; - apple,always-on; /* Apple fabric, critical block */ - }; - - ps_sio_busif: power-controller@1c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1c0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio_busif"; - }; - - ps_sio: power-controller@1c8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1c8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio"; - power-domains = <&ps_sio_busif>; - }; - - ps_sio_cpu: power-controller@1d0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1d0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio_cpu"; - power-domains = <&ps_sio>; - }; - - ps_fpwm0: power-controller@1d8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1d8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "fpwm0"; - }; - - ps_fpwm1: power-controller@1e0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1e0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "fpwm1"; - }; - - ps_fpwm2: power-controller@1e8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1e8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "fpwm2"; - }; - - ps_i2c0: power-controller@1f0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1f0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c0"; - power-domains = <&ps_sio>; - }; - - ps_i2c1: power-controller@1f8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x1f8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c1"; - power-domains = <&ps_sio>; - }; - - ps_i2c2: power-controller@200 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x200 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c2"; - power-domains = <&ps_sio>; - }; - - ps_i2c3: power-controller@208 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x208 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c3"; - power-domains = <&ps_sio>; - }; - - ps_i2c4: power-controller@210 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x210 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "i2c4"; - power-domains = <&ps_sio>; - }; - - ps_spi_p: power-controller@218 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x218 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi_p"; - power-domains = <&ps_sio>; - }; - - ps_uart_p: power-controller@220 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x220 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart_p"; - power-domains = <&ps_sio>; - }; - - ps_audio_p: power-controller@228 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x228 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "audio_p"; - power-domains = <&ps_sio>; - }; - - ps_sio_adma: power-controller@230 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x230 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sio_adma"; - power-domains = <&ps_sio>, <&ps_pms>; - }; - - ps_aes: power-controller@238 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x238 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "aes"; - power-domains = <&ps_sio>; - }; - - ps_spi0: power-controller@240 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x240 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi0"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_spi1: power-controller@248 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x248 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi1"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_spi2: power-controller@250 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x250 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi2"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_spi3: power-controller@258 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x258 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi3"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_uart_n: power-controller@268 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x268 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart_n"; - power-domains = <&ps_uart_p>; - }; - - ps_uart0: power-controller@270 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x270 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart0"; - power-domains = <&ps_uart_p>; - }; - - ps_uart1: power-controller@278 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x278 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart1"; - power-domains = <&ps_uart_p>; - }; - - ps_uart2: power-controller@280 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x280 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart2"; - power-domains = <&ps_uart_p>; - }; - - ps_uart3: power-controller@288 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x288 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart3"; - power-domains = <&ps_uart_p>; - }; - - ps_uart4: power-controller@290 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x290 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart4"; - power-domains = <&ps_uart_p>; - }; - - ps_uart5: power-controller@298 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x298 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart5"; - power-domains = <&ps_uart_p>; - }; - - ps_uart6: power-controller@2a0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2a0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart6"; - power-domains = <&ps_uart_p>; - }; - - ps_uart7: power-controller@2a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2a8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart7"; - power-domains = <&ps_uart_p>; - }; - - ps_uart8: power-controller@2b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2b0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "uart8"; - power-domains = <&ps_uart_p>; - }; - - ps_mca0: power-controller@2b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2b8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca0"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; - }; - - ps_mca1: power-controller@2c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2c0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca1"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca2: power-controller@2c8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2c8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca2"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca3: power-controller@2d0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2d0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca3"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca4: power-controller@2d8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2d8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca4"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_mca5: power-controller@2e0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2e0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mca5"; - power-domains = <&ps_audio_p>, <&ps_sio_adma>; - }; - - ps_dpa0: power-controller@2e8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2e8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dpa0"; - power-domains = <&ps_audio_p>; - }; - - ps_dpa1: power-controller@2f0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2f0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dpa1"; - power-domains = <&ps_audio_p>; - }; - - ps_mcc: power-controller@2f8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x2f8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mcc"; - apple,always-on; /* Memory controller */ - }; - - ps_spi4: power-controller@260 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x260 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi4"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - - ps_dcs0: power-controller@300 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x300 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs0"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs1: power-controller@310 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x310 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs1"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs2: power-controller@308 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x308 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs2"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs3: power-controller@318 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x318 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs3"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_smx: power-controller@340 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x340 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "smx"; - apple,always-on; /* Apple fabric, critical block */ - }; - - ps_apcie: power-controller@348 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x348 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "apcie"; - power-domains = <&ps_imx>, <&ps_pcie_ref>; - }; - - ps_rmx: power-controller@350 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x350 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "rmx"; - /* Apple Fabric, display/image stuff: this can power down */ - }; - - ps_mmx: power-controller@358 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x358 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mmx"; - /* Apple Fabric, media stuff: this can power down */ - }; - - ps_disp0_fe: power-controller@360 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x360 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "disp0_fe"; - power-domains = <&ps_rmx>; - apple,always-on; /* TODO: figure out if we can enable PM here */ - }; - - ps_dispext_fe: power-controller@368 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x368 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispext_fe"; - power-domains = <&ps_rmx>; - }; - - ps_dispext_cpu0: power-controller@378 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x378 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispext_cpu0"; - power-domains = <&ps_dispext_fe>; - apple,min-state = <4>; - }; - - ps_jpg: power-controller@3c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3c0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "jpg"; - power-domains = <&ps_mmx>; - }; - - ps_msr: power-controller@3c8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3c8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "msr"; - power-domains = <&ps_mmx>; - }; - - ps_msr_ase_core: power-controller@3d0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3d0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "msr_ase_core"; - }; - - ps_pmp: power-controller@3d8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3d8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pmp"; - }; - - ps_pms_sram: power-controller@3e0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3e0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "pms_sram"; - }; - - ps_apcie_gp: power-controller@3e8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3e8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "apcie_gp"; - power-domains = <&ps_apcie>; - }; - - ps_ans2: power-controller@3f0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3f0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ans2"; - /* - * The ADT makes ps_apcie_st depend on ps_ans2 instead, but this - * doesn't make much sense since ANS2 uses APCIE_ST. - */ - power-domains = <&ps_apcie_st>; - }; - - ps_gfx: power-controller@3f8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3f8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "gfx"; - }; - - ps_dcs4: power-controller@320 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x320 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs4"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs5: power-controller@330 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x330 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs5"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs6: power-controller@328 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x328 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs6"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dcs7: power-controller@338 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x338 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dcs7"; - apple,always-on; /* LPDDR4 interface */ - }; - - ps_dispdfr_fe: power-controller@3a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3a8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispdfr_fe"; - power-domains = <&ps_rmx>; - }; - - ps_dispdfr_be: power-controller@3b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3b0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "dispdfr_be"; - power-domains = <&ps_dispdfr_fe>; - }; - - ps_mipi_dsi: power-controller@3b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x3b8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "mipi_dsi"; - power-domains = <&ps_dispdfr_be>; - }; - - ps_isp_sys: power-controller@400 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x400 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "isp_sys"; - power-domains = <&ps_rmx>; - }; - - ps_venc_sys: power-controller@408 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x408 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_sys"; - power-domains = <&ps_mmx>; - }; - - ps_avd_sys: power-controller@410 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x410 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "avd_sys"; - power-domains = <&ps_mmx>; - }; - - ps_apcie_st: power-controller@418 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x418 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "apcie_st"; - power-domains = <&ps_apcie>; - }; - - ps_ane_sys: power-controller@470 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x470 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ane_sys"; - }; - - ps_atc0_common: power-controller@420 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x420 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_common"; - }; - - ps_atc0_pcie: power-controller@428 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x428 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_pcie"; - power-domains = <&ps_atc0_common>; - }; - - ps_atc0_cio: power-controller@430 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x430 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_cio"; - power-domains = <&ps_atc0_common>; - }; - - ps_atc0_cio_pcie: power-controller@438 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x438 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_cio_pcie"; - power-domains = <&ps_atc0_cio>; - }; - - ps_atc0_cio_usb: power-controller@440 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x440 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_cio_usb"; - power-domains = <&ps_atc0_cio>; - }; - - ps_atc1_common: power-controller@448 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x448 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_common"; - }; - - ps_atc1_pcie: power-controller@450 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x450 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_pcie"; - power-domains = <&ps_atc1_common>; - }; - - ps_atc1_cio: power-controller@458 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x458 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_cio"; - power-domains = <&ps_atc1_common>; - }; - - ps_atc1_cio_pcie: power-controller@460 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x460 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_cio_pcie"; - power-domains = <&ps_atc1_cio>; - }; - - ps_atc1_cio_usb: power-controller@468 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x468 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_cio_usb"; - power-domains = <&ps_atc1_cio>; - }; - - ps_sep: power-controller@c00 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xc00 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "sep"; - apple,always-on; /* Locked on */ - }; - - ps_venc_dma: power-controller@8000 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8000 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_dma"; - power-domains = <&ps_venc_sys>; - }; - - ps_venc_pipe4: power-controller@8008 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8008 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_pipe4"; - power-domains = <&ps_venc_dma>; - }; - - ps_venc_pipe5: power-controller@8010 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8010 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_pipe5"; - power-domains = <&ps_venc_dma>; - }; - - ps_venc_me0: power-controller@8018 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8018 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_me0"; - power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; - }; - - ps_venc_me1: power-controller@8020 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x8020 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "venc_me1"; - power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>; - }; - - ps_ane_sys_cpu: power-controller@c000 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xc000 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "ane_sys_cpu"; - power-domains = <&ps_ane_sys>; - }; - - ps_disp0_cpu0: power-controller@10018 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x10018 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "disp0_cpu0"; - power-domains = <&ps_disp0_fe>; - apple,always-on; /* TODO: figure out if we can enable PM here */ - apple,min-state = <4>; - }; -}; - -&pmgr_mini { - ps_debug: power-controller@58 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x58 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "debug"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_spmi0: power-controller@60 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x60 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_spmi0"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_aon: power-controller@70 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x70 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_aon"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_gpio: power-controller@80 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x80 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_gpio"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_fabric: power-controller@a8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xa8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_fabric"; - apple,always-on; /* Core AON device */ - }; - - ps_nub_sram: power-controller@b0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xb0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_sram"; - apple,always-on; /* Core AON device */ - }; - - ps_debug_usb: power-controller@b8 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xb8 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "debug_usb"; - apple,always-on; /* Core AON device */ - power-domains = <&ps_debug>; - }; - - ps_debug_auth: power-controller@c0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xc0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "debug_auth"; - apple,always-on; /* Core AON device */ - power-domains = <&ps_debug>; - }; - - ps_nub_spmi1: power-controller@68 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x68 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "nub_spmi1"; - apple,always-on; /* Core AON device */ - }; - - ps_msg: power-controller@78 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x78 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "msg"; - }; - - ps_atc0_usb_aon: power-controller@88 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x88 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_usb_aon"; - }; - - ps_atc1_usb_aon: power-controller@90 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x90 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_usb_aon"; - }; - - ps_atc0_usb: power-controller@98 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x98 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc0_usb"; - power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>; - }; - - ps_atc1_usb: power-controller@a0 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0xa0 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "atc1_usb"; - power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>; - }; -}; diff --git a/arch/arm/dts/t8103-u-boot.dtsi b/arch/arm/dts/t8103-u-boot.dtsi deleted file mode 100644 index e9e593a00cf..00000000000 --- a/arch/arm/dts/t8103-u-boot.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT - -&serial0 { - bootph-all; -}; - -&pmgr { - bootph-all; -}; - -&ps_sio_busif { - bootph-all; -}; - -&ps_sio { - bootph-all; -}; - -&ps_uart_p { - bootph-all; -}; - -&ps_uart0 { - bootph-all; -}; diff --git a/arch/arm/dts/t8103.dtsi b/arch/arm/dts/t8103.dtsi deleted file mode 100644 index ed7840f94b6..00000000000 --- a/arch/arm/dts/t8103.dtsi +++ /dev/null @@ -1,696 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Apple T8103 "M1" SoC - * - * Other names: H13G, "Tonga" - * - * Copyright The Asahi Linux Contributors - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/apple-aic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/apple.h> - -/ { - compatible = "apple,t8103", "apple,arm-platform"; - - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu1: cpu@1 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu2: cpu@2 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu3: cpu@3 { - compatible = "apple,icestorm"; - device_type = "cpu"; - reg = <0x0 0x3>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu4: cpu@10100 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10100>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu5: cpu@10101 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10101>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu6: cpu@10102 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10102>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - - cpu7: cpu@10103 { - compatible = "apple,firestorm"; - device_type = "cpu"; - reg = <0x0 0x10103>; - enable-method = "spin-table"; - cpu-release-addr = <0 0>; /* To be filled by loader */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&aic>; - interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; - interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, - <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, - <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, - <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; - }; - - clkref: clock-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "clkref"; - }; - - clk_120m: clock-120m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <120000000>; - clock-output-names = "clk_120m"; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - - ranges; - nonposted-mmio; - - i2c0: i2c@235010000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35010000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c0>; - }; - - i2c1: i2c@235014000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35014000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c1>; - }; - - i2c2: i2c@235018000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35018000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c2>; - status = "disabled"; /* not used in all devices */ - }; - - i2c3: i2c@23501c000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x3501c000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c3>; - }; - - i2c4: i2c@235020000 { - compatible = "apple,t8103-i2c", "apple,i2c"; - reg = <0x2 0x35020000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - #address-cells = <0x1>; - #size-cells = <0x0>; - power-domains = <&ps_i2c4>; - status = "disabled"; /* only used in J293 */ - }; - - spi3: spi@23510c000 { - compatible = "apple,t8103-spi", "apple,spi"; - reg = <0x2 0x3510c000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_120m>; - pinctrl-0 = <&spi3_pins>; - pinctrl-names = "default"; - power-domains = <&ps_spi3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; /* only used in J293/J313 */ - }; - - serial0: serial@235200000 { - compatible = "apple,s5l-uart"; - reg = <0x2 0x35200000 0x0 0x1000>; - reg-io-width = <4>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; - /* - * TODO: figure out the clocking properly, there may - * be a third selectable clock. - */ - clocks = <&clkref>, <&clkref>; - clock-names = "uart", "clk_uart_baud0"; - power-domains = <&ps_uart0>; - status = "disabled"; - }; - - serial2: serial@235208000 { - compatible = "apple,s5l-uart"; - reg = <0x2 0x35208000 0x0 0x1000>; - reg-io-width = <4>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clkref>, <&clkref>; - clock-names = "uart", "clk_uart_baud0"; - power-domains = <&ps_uart2>; - status = "disabled"; - }; - - aic: interrupt-controller@23b100000 { - compatible = "apple,t8103-aic", "apple,aic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x2 0x3b100000 0x0 0x8000>; - power-domains = <&ps_aic>; - }; - - pmgr: power-management@23b700000 { - compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2 0x3b700000 0 0x14000>; - }; - - pinctrl_ap: pinctrl@23c100000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3c100000 0x0 0x100000>; - power-domains = <&ps_gpio>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_ap 0 0 212>; - apple,npins = <212>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; - - i2c0_pins: i2c0-pins { - pinmux = <APPLE_PINMUX(192, 1)>, - <APPLE_PINMUX(188, 1)>; - }; - - i2c1_pins: i2c1-pins { - pinmux = <APPLE_PINMUX(201, 1)>, - <APPLE_PINMUX(199, 1)>; - }; - - i2c2_pins: i2c2-pins { - pinmux = <APPLE_PINMUX(163, 1)>, - <APPLE_PINMUX(162, 1)>; - }; - - i2c3_pins: i2c3-pins { - pinmux = <APPLE_PINMUX(73, 1)>, - <APPLE_PINMUX(72, 1)>; - }; - - i2c4_pins: i2c4-pins { - pinmux = <APPLE_PINMUX(135, 1)>, - <APPLE_PINMUX(134, 1)>; - }; - - spi3_pins: spi3-pins { - pinmux = <APPLE_PINMUX(46, 1)>, - <APPLE_PINMUX(47, 1)>, - <APPLE_PINMUX(48, 1)>, - <APPLE_PINMUX(49, 1)>; - }; - - pcie_pins: pcie-pins { - pinmux = <APPLE_PINMUX(150, 1)>, - <APPLE_PINMUX(151, 1)>, - <APPLE_PINMUX(32, 1)>; - }; - }; - - spmi: spmi@23d0d9300 { - compatible = "apple,t8103-spmi", "apple,spmi"; - reg = <0x2 0x3d0d9300 0x0 0x100>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 343 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <0>; - status = "disabled"; - }; - - pinctrl_nub: pinctrl@23d1f0000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3d1f0000 0x0 0x4000>; - power-domains = <&ps_nub_gpio>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_nub 0 0 23>; - apple,npins = <23>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmgr_mini: power-management@23d280000 { - compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2 0x3d280000 0 0x4000>; - }; - - wdt: watchdog@23d2b0000 { - compatible = "apple,t8103-wdt", "apple,wdt"; - reg = <0x2 0x3d2b0000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>; - }; - - pinctrl_smc: pinctrl@23e820000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x3e820000 0x0 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_smc 0 0 16>; - apple,npins = <16>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; - }; - - smc_mbox: mbox@23e408000 { - compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; - reg = <0x2 0x3e408000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 400 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 401 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 402 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 403 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "send-empty", "send-not-empty", - "recv-empty", "recv-not-empty"; - #mbox-cells = <0>; - }; - - smc: smc@23e050000 { - compatible = "apple,smc"; - reg = <0x2 0x3e050000 0x0 0x4000>; - mboxes = <&smc_mbox>; - gpio-controller; - #gpio-cells = <2>; - gpio-13 = <0x00800000>; - }; - - pinctrl_aop: pinctrl@24a820000 { - compatible = "apple,t8103-pinctrl", "apple,pinctrl"; - reg = <0x2 0x4a820000 0x0 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aop 0 0 42>; - apple,npins = <42>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; - }; - - ans_mbox: mbox@277408000 { - compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; - reg = <0x2 0x77408000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "send-empty", "send-not-empty", - "recv-empty", "recv-not-empty"; - #mbox-cells = <0>; - power-domains = <&ps_ans2>; - }; - - sart: sart@27bc50000 { - compatible = "apple,t8103-sart", "apple,sart2"; - reg = <0x2 0x7bc50000 0x0 0x10000>; - power-domains = <&ps_ans2>; - }; - - nvme@27bcc0000 { - compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2"; - reg = <0x2 0x7bcc0000 0x0 0x40000>, - <0x2 0x77400000 0x0 0x4000>; - reg-names = "nvme", "ans"; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>; - mboxes = <&ans_mbox>; - apple,sart = <&sart>; - power-domains = <&ps_ans2>; - resets = <&ps_ans2>; - }; - - dwc3_0: usb@382280000 { - compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3"; - reg = <0x3 0x82280000 0x0 0x100000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>; - usb-role-switch; - role-switch-default-mode = "host"; - iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; - power-domains = <&ps_atc0_usb>; - }; - - dwc3_0_dart_0: iommu@382f00000 { - compatible = "apple,t8103-dart"; - reg = <0x3 0x82f00000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_atc0_usb>; - }; - - dwc3_0_dart_1: iommu@382f80000 { - compatible = "apple,t8103-dart"; - reg = <0x3 0x82f80000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_atc0_usb>; - }; - - dwc3_1: usb@502280000 { - compatible = "apple,t8103-dwc3", "apple,dwc3", "snps,dwc3"; - reg = <0x5 0x02280000 0x0 0x100000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>; - usb-role-switch; - role-switch-default-mode = "host"; - iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; - power-domains = <&ps_atc1_usb>; - }; - - dwc3_1_dart_0: iommu@502f00000 { - compatible = "apple,t8103-dart"; - reg = <0x5 0x02f00000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_atc1_usb>; - }; - - dwc3_1_dart_1: iommu@502f80000 { - compatible = "apple,t8103-dart"; - reg = <0x5 0x02f80000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_atc1_usb>; - }; - - pcie0_dart_0: dart@681008000 { - compatible = "apple,t8103-dart"; - reg = <0x6 0x81008000 0x0 0x4000>; - #iommu-cells = <1>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&ps_apcie_gp>; - }; - - pcie0_dart_1: dart@682008000 { - compatible = "apple,t8103-dart"; - reg = <0x6 0x82008000 0x0 0x4000>; - #iommu-cells = <1>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&ps_apcie_gp>; - }; - - pcie0_dart_2: dart@683008000 { - compatible = "apple,t8103-dart"; - reg = <0x6 0x83008000 0x0 0x4000>; - #iommu-cells = <1>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&ps_apcie_gp>; - }; - - pcie0: pcie@690000000 { - compatible = "apple,t8103-pcie", "apple,pcie"; - device_type = "pci"; - - reg = <0x6 0x90000000 0x0 0x1000000>, - <0x6 0x80000000 0x0 0x100000>, - <0x6 0x81000000 0x0 0x4000>, - <0x6 0x82000000 0x0 0x4000>, - <0x6 0x83000000 0x0 0x4000>; - reg-names = "config", "rc", "port0", "port1", "port2"; - - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; - - msi-controller; - msi-parent = <&pcie0>; - msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; - - - iommu-map = <0x100 &pcie0_dart_0 1 1>, - <0x200 &pcie0_dart_1 1 1>, - <0x300 &pcie0_dart_2 1 1>; - iommu-map-mask = <0xff00>; - - bus-range = <0 3>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, - <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; - - power-domains = <&ps_apcie_gp>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - - port00: pci@0,0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &port00 0 0 0 0>, - <0 0 0 2 &port00 0 0 0 1>, - <0 0 0 3 &port00 0 0 0 2>, - <0 0 0 4 &port00 0 0 0 3>; - }; - - port01: pci@1,0 { - device_type = "pci"; - reg = <0x800 0x0 0x0 0x0 0x0>; - reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &port01 0 0 0 0>, - <0 0 0 2 &port01 0 0 0 1>, - <0 0 0 3 &port01 0 0 0 2>, - <0 0 0 4 &port01 0 0 0 3>; - }; - - port02: pci@2,0 { - device_type = "pci"; - reg = <0x1000 0x0 0x0 0x0 0x0>; - reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; - - #address-cells = <3>; - #size-cells = <2>; - ranges; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &port02 0 0 0 0>, - <0 0 0 2 &port02 0 0 0 1>, - <0 0 0 3 &port02 0 0 0 2>, - <0 0 0 4 &port02 0 0 0 3>; - }; - }; - - dart_sio: iommu@235004000 { - compatible = "apple,t8103-dart", "apple,dart"; - reg = <0x2 0x35004000 0x0 0x4000>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - power-domains = <&ps_sio_cpu>; - }; - - nco_inp: clock-ref { - compatible = "fixed-factor-clock"; - clocks = <&clkref>; - #clock-cells = <0>; - clock-mult = <75>; - clock-div = <2>; // 24 MHz * (75/2) = 900 MHz - clock-output-names = "nco_inp"; - }; - - nco: nco@23b044000 { - compatible = "apple,t8103-nco", "apple,nco"; - reg = <0x2 0x3b044000 0x0 0x14000>; - clocks = <&nco_inp>; - #clock-cells = <1>; - apple,nchannels = <5>; - }; - - admac: dma-controller@238200000 { - compatible = "apple,t8103-admac", "apple,admac"; - reg = <0x2 0x38200000 0x0 0x34000>; - dma-channels = <12>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - iommus = <&dart_sio 2>; - power-domains = <&ps_sio_adma>; - }; - - mca: mca { - compatible = "apple,t8103-mca", "apple,mca"; - reg = <0x2 0x38400000 0x0 0x18000>, - <0x2 0x38300000 0x0 0x30000>; - reg-names = "clusters", "switch"; - clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>; - power-domains = <&ps_mca0>; //, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; - resets = <&ps_mca0>, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; - - #sound-dai-cells = <1>; - apple,nclusters = <6>; - apple,mclk-range = <2600000 25000000>; - - route { - dmas = <&admac 2>; - dma-names = "tx"; - apple,serdes = <1>; - sound-dai = <&mca 0>; - }; - - route2 { - dmas = <&admac 6>; - dma-names = "tx"; - apple,serdes = <3>; - sound-dai = <&mca 2>; - }; - }; - }; -}; - -#include "t8103-pmgr.dtsi" diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 482f432ba7f..877962df2b3 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -3,7 +3,7 @@ * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -49,6 +49,14 @@ clock-frequency = <27000000>; clock-output-names = "aux_ref_clk"; }; + + rtc_clk: rtc-clk { + bootph-all; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; + }; }; &zynqmp_firmware { @@ -302,3 +310,8 @@ <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; + +&rtc { + clocks = <&rtc_clk>; + clock-names = "rtc"; +}; diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index d48b6f3a8ec..83c39ce1a26 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -90,6 +90,9 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ + nvmem-cells = <ð_mac>; + nvmem-cell-names = "mac-address"; + mdio: mdio { #address-cells = <1>; #size-cells = <0>; @@ -119,10 +122,10 @@ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ - "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 - 89 */ - "", "", "", "", "", /* 90 - 94 */ - "", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ + "", "", "", "", "PMOD_0", /* 80 - 84 */ + "PMOD_1", "PMOD_2", "PMOD_3", "PMOD_4", "PMOD_5", /* 85 -89 */ + "PMOD_6", "PMOD_7", "", "", "", /* 90 - 94 */ + "", "", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ @@ -153,6 +156,12 @@ eeprom: eeprom@50 { /* u46 */ compatible = "atmel,24c32"; reg = <0x50>; + #address-cells = <1>; + #size-cells = <1>; + + eth_mac: mac-address@20 { + reg = <0x20 0x6>; + }; }; /* u138 - TUSB320IRWBR - for USB-C */ }; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index aebceb20736..824d189d246 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -51,83 +51,103 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 7c9764c31f7..bf4ea35067c 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -40,26 +40,32 @@ ina226-u74 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index f9d7528ff2e..2bf6af9c065 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -45,27 +45,33 @@ ina226-vcc-aux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index b4da0d341c3..fbeae394c62 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -45,22 +45,27 @@ ina226-vcc-aux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 729efd4098c..33a86fad604 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -45,22 +45,27 @@ ina226-vcc-aux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 6181072c1da..afaecfa5a27 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -136,7 +136,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; @@ -194,93 +193,97 @@ /* QSPI should also have PINCTRL setup */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ - partition@0 { - label = "Image Selector"; - reg = <0x0 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@80000 { - label = "Image Selector Golden"; - reg = <0x80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@100000 { - label = "Persistent Register"; - reg = <0x100000 0x20000>; /* 128KB */ - }; - partition@120000 { - label = "Persistent Register Backup"; - reg = <0x120000 0x20000>; /* 128KB */ - }; - partition@140000 { - label = "Open_1"; - reg = <0x140000 0xc0000>; /* 768KB */ - }; - partition@200000 { - label = "Image A (FSBL, PMU, ATF, U-Boot)"; - reg = <0x200000 0xd00000>; /* 13MB */ - }; - partition@f00000 { - label = "ImgSel Image A Catch"; - reg = <0xf00000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@f80000 { - label = "Image B (FSBL, PMU, ATF, U-Boot)"; - reg = <0xf80000 0xd00000>; /* 13MB */ - }; - partition@1c80000 { - label = "ImgSel Image B Catch"; - reg = <0x1c80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@1d00000 { - label = "Open_2"; - reg = <0x1d00000 0x100000>; /* 1MB */ - }; - partition@1e00000 { - label = "Recovery Image"; - reg = <0x1e00000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2000000 { - label = "Recovery Image Backup"; - reg = <0x2000000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2200000 { - label = "U-Boot storage variables"; - reg = <0x2200000 0x20000>; /* 128KB */ - }; - partition@2220000 { - label = "U-Boot storage variables backup"; - reg = <0x2220000 0x20000>; /* 128KB */ - }; - partition@2240000 { - label = "SHA256"; - reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ - read-only; - lock; - }; - partition@2280000 { - label = "Secure OS Storage"; - reg = <0x2280000 0x20000>; /* 128KB */ - }; - partition@22a0000 { - label = "User"; - reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Image Selector"; + reg = <0x0 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@80000 { + label = "Image Selector Golden"; + reg = <0x80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@100000 { + label = "Persistent Register"; + reg = <0x100000 0x20000>; /* 128KB */ + }; + partition@120000 { + label = "Persistent Register Backup"; + reg = <0x120000 0x20000>; /* 128KB */ + }; + partition@140000 { + label = "Open_1"; + reg = <0x140000 0xc0000>; /* 768KB */ + }; + partition@200000 { + label = "Image A (FSBL, PMU, ATF, U-Boot)"; + reg = <0x200000 0xd00000>; /* 13MB */ + }; + partition@f00000 { + label = "ImgSel Image A Catch"; + reg = <0xf00000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@f80000 { + label = "Image B (FSBL, PMU, ATF, U-Boot)"; + reg = <0xf80000 0xd00000>; /* 13MB */ + }; + partition@1c80000 { + label = "ImgSel Image B Catch"; + reg = <0x1c80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@1d00000 { + label = "Open_2"; + reg = <0x1d00000 0x100000>; /* 1MB */ + }; + partition@1e00000 { + label = "Recovery Image"; + reg = <0x1e00000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2000000 { + label = "Recovery Image Backup"; + reg = <0x2000000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2200000 { + label = "U-Boot storage variables"; + reg = <0x2200000 0x20000>; /* 128KB */ + }; + partition@2220000 { + label = "U-Boot storage variables backup"; + reg = <0x2220000 0x20000>; /* 128KB */ + }; + partition@2240000 { + label = "SHA256"; + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ + read-only; + lock; + }; + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22a0000 { + label = "User"; + reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts index 530a4a5f080..b9b192f0986 100644 --- a/arch/arm/dts/zynqmp-sc-revC.dts +++ b/arch/arm/dts/zynqmp-sc-revC.dts @@ -23,7 +23,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { /* ADI1300 */ - #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2400>; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso index e94b784e8e1..7212ee9df86 100644 --- a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP VEK280 revA * - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -13,8 +13,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA", - "xlnx,zynqmp-vek280", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso index a3983f330d0..a57e9b50b20 100644 --- a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP VEK280 revB * - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -10,6 +10,5 @@ #include "zynqmp-sc-vek280-revA.dtso" &{/} { - compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", - "xlnx,zynqmp-vek280", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp"; }; diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso index fd25731b0b4..2fe35596143 100644 --- a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VHK158 revA * * (C) Copyright 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA", - "xlnx,zynqmp-vhk158", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-sc-vhk158", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso index 4d0f10e13c3..58be0e1c890 100644 --- a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP VM-P-M1369-00 * - * Copyright (C) 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2024-2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -18,66 +18,82 @@ ina226-u19 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>; }; ina226-u287 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; }; ina226-u288 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>; }; ina226-u289 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; }; ina226-u290 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>; }; ina226-u291 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; }; ina226-u292 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; }; ina226-u293 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; }; ina226-u294 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; }; ina226-u295 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>; }; ina226-u298 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>; }; ina226-u296 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>; }; ina226-u299 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; }; ina226-u300 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; }; ina226-u301 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; }; ina226-u297 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>; }; }; @@ -393,7 +409,7 @@ }; /* connected via J425 connector - ucd90320: power-sequencer@73 { // u16 + ucd90320: power-sequencer@73 { // u16 compatible = "ti,ucd90320"; reg = <0x73>; };*/ diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso index 5a4e5f09250..39be25be8f6 100644 --- a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso @@ -22,66 +22,82 @@ ina226-u1700 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; }; ina226-u1732 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>; }; ina226-u1733 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; }; ina226-u1736 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>; }; ina226-u1737 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; }; ina226-u1739 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; }; ina226-u1741 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; }; ina226-u1743 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; }; ina226-u1745 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>; }; ina226-u1747 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>; }; ina226-u1750 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>yp_avcc_ina 0>, <>yp_avcc_ina 1>, <>yp_avcc_ina 2>; }; ina226-u1752 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>yp_avtt_ina 0>, <>yp_avtt_ina 1>, <>yp_avtt_ina 2>; }; ina226-u1754 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>yp_avccaux_ina 0>, <>yp_avccaux_ina 1>, <>yp_avccaux_ina 2>; }; ina226-u1756 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; }; ina226-u1758 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; }; ina226-u1760 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; }; diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso index 29b3a73fde0..ae0691c0127 100644 --- a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VPK120 revB * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB", - "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-sc-vpk120", "xlnx,zynqmp"; }; &i2c0 { diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso index 10466ce99de..9b6534f6383 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VPK180 revA * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA", - "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso index 74e1c5c6dc9..941d26c025a 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP VPK180 revA + * dts file for Xilinx ZynqMP VPK180 revB * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB", - "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 8342479b108..a32073fa040 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -50,6 +50,24 @@ gpio-controller; gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &can0 { @@ -76,7 +94,6 @@ slg7xl45106: gpio@11 { /* u13 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "", @@ -124,6 +141,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -148,7 +167,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@8 { /* Adin u31 */ - #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <8>; adi,rx-internal-delay-ps = <2000>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index db042ffb4f3..31b3c3582c2 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -66,6 +66,7 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + dpcon { compatible = "dp-connector"; label = "P11"; @@ -85,6 +86,24 @@ gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -105,7 +124,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", @@ -196,6 +214,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -233,6 +253,8 @@ peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; reset-gpios = <&slg_delay 1 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -265,7 +287,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@4 { /* u81 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <4>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; @@ -277,7 +298,6 @@ reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; phy1: ethernet-phy@8 { /* u36 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <8>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index e3567d0abfe..f1114a35aae 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -86,6 +86,24 @@ gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -106,7 +124,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", @@ -197,6 +214,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -234,6 +253,8 @@ peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; reset-gpios = <&slg_delay 1 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -266,7 +287,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@4 { /* u81 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <4>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; @@ -278,7 +298,6 @@ reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; phy1: ethernet-phy@8 { /* u36 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <8>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index f93c7460a55..967548744d5 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -85,6 +85,24 @@ gpio-controller; gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -169,6 +187,8 @@ reg = <1>; peer-hub = <&hub_3_0>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -209,7 +229,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { - #phy-cells = <1>; reg = <1>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; @@ -227,23 +246,23 @@ status = "okay"; pinctrl_gpio0_default: gpio0-default { - conf { - groups = "gpio0_38_grp"; - bias-pull-up; - power-source = <IO_STANDARD_LVCMOS18>; - }; + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; - mux { - groups = "gpio0_38_grp"; - function = "gpio0"; - }; + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; - conf-tx { - pins = "MIO38"; - bias-disable; - output-enable; - }; - }; + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; pinctrl_uart1_default: uart1-default { conf { @@ -402,9 +421,9 @@ }; &gpio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; }; &uart1 { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 70de6933600..0fa5a990adc 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for KV260 revA Carrier Card + * dts file for KV260 revB Carrier Card * * (C) Copyright 2020 - 2022, Xilinx, Inc. * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. @@ -81,6 +81,24 @@ gpio-controller; gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -156,6 +174,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -200,7 +220,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { - #phy-cells = <1>; reg = <1>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts index 653bd936226..34ee6af801d 100644 --- a/arch/arm/dts/zynqmp-sm-k24-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SM-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2022, Advanced Micro Devices, Inc. + * (C) Copyright 2022-2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -21,3 +21,8 @@ reg = <0 0 0 0x80000000>; }; }; + +&cma { + size = <0x0 0x4000000>; + alignment = <0x0 0x4000000>; +}; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 0abec77b3f3..c7fe253244f 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -61,6 +61,15 @@ reg = <0x0 0x7ff00000 0x0 0x100000>; no-map; }; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; }; gpio-keys { diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index 2037686b9b4..1dc0414b33d 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -63,23 +63,27 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <166000000>; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "qspi-boot-bin"; - reg = <0x00000 0x60000>; - }; - partition@60000 { - label = "qspi-u-boot-itb"; - reg = <0x60000 0x100000>; - }; - partition@160000 { - label = "qspi-u-boot-env"; - reg = <0x160000 0x20000>; - }; - partition@200000 { - label = "qspi-rootfs"; - reg = <0x200000 0x1e00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi-boot-bin"; + reg = <0x00000 0x60000>; + }; + partition@60000 { + label = "qspi-u-boot-itb"; + reg = <0x60000 0x100000>; + }; + partition@160000 { + label = "qspi-u-boot-env"; + reg = <0x160000 0x20000>; + }; + partition@200000 { + label = "qspi-rootfs"; + reg = <0x200000 0x1e00000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index e9c6d249a8d..94167770ed6 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -88,15 +88,19 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; - partition@0 { /* for testing purpose */ - label = "qspi"; - reg = <0 0x4000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index bd1e2557187..3e461d9c4d0 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -88,15 +88,19 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; - partition@0 { /* for testing purpose */ - label = "qspi"; - reg = <0 0x4000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 9dcb9095371..f0e2a0b4588 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -31,6 +31,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { @@ -40,28 +55,32 @@ &qspi { status = "okay"; flash@0 { - compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ - #address-cells = <1>; - #size-cells = <1>; + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index cf3e9583204..e92caefd3aa 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -32,6 +32,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { @@ -42,27 +57,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 32f317f3df4..2897c423f82 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -41,6 +41,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -357,28 +372,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index e3d5cf972e8..0b1185d862c 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -39,6 +39,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &can0 { @@ -138,8 +153,6 @@ nand@0 { reg = <0x0>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; @@ -147,35 +160,39 @@ nand-ecc-strength = <24>; nand-on-flash-bbt; - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; nand@1 { reg = <0x1>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; @@ -183,29 +200,35 @@ nand-ecc-strength = <24>; nand-on-flash-bbt; - partition@0 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; }; @@ -503,15 +526,18 @@ pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "spi0-data"; - reg = <0x0 0x100000>; + partition@0 { + label = "spi0-data"; + reg = <0x0 0x100000>; + }; }; }; }; @@ -523,15 +549,18 @@ pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "spi1-data"; - reg = <0x0 0x84000>; + partition@0 { + label = "spi1-data"; + reg = <0x0 0x84000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index a8856c20f5b..bfcc92cedfa 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -39,6 +39,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -133,8 +148,6 @@ nand@0 { reg = <0x0>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; @@ -142,65 +155,74 @@ nand-ecc-strength = <24>; nand-on-flash-bbt; - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; nand@1 { reg = <0x1>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; - partition@0 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partition@0 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 3b03b39e456..9b59952993f 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -38,6 +38,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &can0 { @@ -174,27 +189,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 53aa3dca1dc..722b2e833b4 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -37,6 +37,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &fpd_dma_chan1 { diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 4ec8a400494..81353b60b38 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> * Nathalie Chan King Choy @@ -47,6 +47,21 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -61,6 +76,7 @@ iio-hwmon { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, @@ -120,6 +136,7 @@ ina226 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 6b1aea95e65..4d5f4754171 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -45,6 +45,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -68,74 +83,92 @@ ina226-u76 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; @@ -217,7 +250,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@21 { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <21>; ti,rx-internal-delay = <0x8>; @@ -987,28 +1019,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 3c28130909b..bad59d7b1d2 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -19,7 +19,6 @@ phy-handle = <&phyc>; mdio: mdio { phyc: ethernet-phy@c { - #phy-cells = <0x1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 0bfeed4293c..4479ff73514 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -126,7 +141,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -453,27 +467,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index a7387f4a0e6..0f1b1fd92a7 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -43,8 +43,24 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + ina226 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; @@ -131,7 +147,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -465,27 +480,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 7b1097579fc..ad76159084e 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -45,6 +45,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -68,74 +83,92 @@ ina226-u76 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; @@ -217,7 +250,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; reg = <0xc>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <0x8>; @@ -981,28 +1013,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index ba1b6339100..a9a47360237 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -45,6 +45,21 @@ /* Another 4GB connected to PL */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -68,58 +83,72 @@ ina226-u67 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; @@ -189,7 +218,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -804,28 +832,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index cc9f5b16025..1a49ae3ba4e 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -32,6 +32,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { @@ -46,27 +61,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index f78da036280..1b6f7a605d6 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -35,6 +35,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { @@ -73,27 +88,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 86a3217f9ab..b2d71f0f455 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -36,6 +36,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 888f711aad9..60231d7d3a2 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -66,61 +81,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; @@ -176,7 +205,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index ccdbf8967aa..bfe6f97a760 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -66,61 +81,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; @@ -183,7 +212,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts index 058d6b2e648..08e88745477 100644 --- a/arch/arm/dts/zynqmp-zcu670-revA.dts +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU670 (67DR) * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -46,6 +46,21 @@ /* Another 4GB connected to PL */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -69,61 +84,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; @@ -185,7 +214,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts index 010d412b202..5c9195239f1 100644 --- a/arch/arm/dts/zynqmp-zcu670-revB.dts +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -46,6 +46,21 @@ /* Another 4GB connected to PL */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -69,61 +84,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; @@ -185,7 +214,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 13cfca66657..c225eb219f4 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1006,7 +1006,6 @@ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "alarm", "sec"; - calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 13960db2fbd..80b0707131f 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -12,31 +12,10 @@ #include <asm/arch/clocks_am33xx.h> #include <asm/arch/hardware.h> +#include <asm/ti-common/omap_clock.h> #define LDELAY 1000000 -/*CM_<clock_domain>__CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 - -/* CM_<clock_domain>_<module>_CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 #define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) @@ -53,26 +32,6 @@ #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_FAST_RELOCK_BYPASS 6 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F /* CM_SSC_DELTAM_DPLL */ #define CM_SSC_DELTAM_DPLL_FRAC_SHIFT 0 diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index adb574e8f13..583364bf826 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -22,7 +22,6 @@ #define UART_CLK_RUNNING_MASK 0x1 #define UART_SMART_IDLE_EN (0x1 << 0x3) -#define CM_DLL_CTRL_NO_OVERRIDE 0x0 #define CM_DLL_READYST 0x4 #define NUM_OPPS 6 diff --git a/arch/arm/include/asm/arch-aspeed/fmc_hdr.h b/arch/arm/include/asm/arch-aspeed/fmc_hdr.h new file mode 100644 index 00000000000..c60277e1a81 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/fmc_hdr.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef __ASM_AST2700_FMC_HDR_H__ +#define __ASM_AST2700_FMC_HDR_H__ + +#include <linux/types.h> + +#define HDR_MAGIC 0x48545341 /* ASTH */ +#define HDR_PB_MAX 30 + +enum prebuilt_type { + PBT_END_MARK = 0x0, + + PBT_DDR4_PMU_TRAIN_IMEM, + PBT_DDR4_PMU_TRAIN_DMEM, + PBT_DDR4_2D_PMU_TRAIN_IMEM, + PBT_DDR4_2D_PMU_TRAIN_DMEM, + PBT_DDR5_PMU_TRAIN_IMEM, + PBT_DDR5_PMU_TRAIN_DMEM, + PBT_DP_FW, + PBT_UEFI_X64_AST2700, + + PBT_NUM +}; + +struct fmc_hdr_preamble { + u32 magic; + u32 version; +}; + +struct fmc_hdr_body { + u32 fmc_size; + union { + struct { + u32 type; + u32 size; + } pbs[0]; + u32 raz[29]; + }; +}; + +struct fmc_hdr { + struct fmc_hdr_preamble preamble; + struct fmc_hdr_body body; +} __packed; + +int fmc_hdr_get_prebuilt(u32 type, u32 *ofst, u32 *size); + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h index 589abd4a3f6..82699c03c00 100644 --- a/arch/arm/include/asm/arch-aspeed/platform.h +++ b/arch/arm/include/asm/arch-aspeed/platform.h @@ -18,8 +18,36 @@ #define ASPEED_DRAM_BASE 0x80000000 #define ASPEED_SRAM_BASE 0x10000000 #define ASPEED_SRAM_SIZE 0x16000 +#elif defined(CONFIG_ASPEED_AST2700) +#define ASPEED_CPU_AHBC_BASE 0x12000000 +#define ASPEED_CPU_REVISION_ID 0x12C02000 +#define ASPEED_CPU_SCU_BASE 0x12C02000 +#define ASPEED_CPU_HW_STRAP1 0x12C02010 +#define ASPEED_CPU_RESET_LOG1 0x12C02050 +#define ASPEED_CPU_RESET_LOG2 0x12C02060 +#define ASPEED_CPU_RESET_LOG3 0x12C02070 +#define ASPEED_MAC_COUNT 3 +#define ASPEED_DRAM_BASE 0x400000000 +#define ASPEED_SRAM_BASE 0x10000000 +#define ASPEED_SRAM_SIZE 0x20000 +#define ASPEED_FMC_REG_BASE 0x14000000 +#define ASPEED_FMC_CS0_BASE 0x100000000 +#define ASPEED_FMC_CS0_SIZE 0x80000000 +#define ASPEED_IO_MAC0_BASE 0x14050000 +#define ASPEED_IO_MAC1_BASE 0x14060000 +#define ASPEED_IO_AHBC_BASE 0x140b0000 +#define ASPEED_IO_REVISION_ID 0x14C02000 +#define CHIP_AST2700A1_ID_MASK BIT(16) +#define ASPEED_IO_SCU_BASE 0x14C02000 +#define ASPEED_IO_HW_STRAP1 0x14C02010 +#define ASPEED_IO_RESET_LOG1 0x14C02050 +#define ASPEED_IO_RESET_LOG2 0x14C02060 +#define ASPEED_IO_RESET_LOG3 0x14C02070 +#define ASPEED_IO_RESET_LOG4 0x14C02080 +#define ASPEED_IO_GPIO_BASE 0x14C0B000 +#define ASPEED_WDTA_BASE 0x14C37400 #else -#err "Unrecognized Aspeed platform." +#error "Unrecognized Aspeed platform." #endif #endif diff --git a/arch/arm/include/asm/arch-aspeed/scu.h b/arch/arm/include/asm/arch-aspeed/scu.h new file mode 100644 index 00000000000..1aa7d38bace --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/scu.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef __ASM_AST2700_SCU_H__ +#define __ASM_AST2700_SCU_H__ + +/* SCU0: CPU-die SCU */ +#define SCU0_HWSTRAP 0x010 +#define SCU0_HWSTRAP_DIS_RVAS BIT(30) +#define SCU0_HWSTRAP_DIS_WDTFULL BIT(25) +#define SCU0_HWSTRAP_DISARMICE_TZ BIT(22) +#define SCU0_HWSTRAP_DISABLE_XHCI BIT(21) +#define SCU0_HWSTRAP_BOOTEMMCSPEED BIT(20) +#define SCU0_HWSTRAP_VGA_CC BIT(18) +#define SCU0_HWSTRAP_EN_OPROM BIT(17) +#define SCU0_HWSTRAP_DISARMICE BIT(16) +#define SCU0_HWSTRAP_TSPRSNTSEL BIT(9) +#define SCU0_HWSTRAP_DISDEBUG BIT(8) +#define SCU0_HWSTRAP_HCLKHPLL BIT(7) +#define SCU0_HWSTRAP_HCLKSEL GENMASK(6, 5) +#define SCU0_HWSTRAP_CPUHPLL BIT(4) +#define SCU0_HWSTRAP_HPLLFREQ GENMASK(3, 2) +#define SCU0_HWSTRAP_BOOTSPI BIT(1) +#define SCU0_HWSTRAP_HWSTRAP_DISCPU BIT(0) +#define SCU0_DBGCTL 0x0c8 +#define SCU0_DBGCTL_MASK GENMASK(14, 0) +#define SCU0_DBGCTL_UARTDBG BIT(1) +#define SCU0_RSTCTL1 0x200 +#define SCU0_RSTCTL1_EMMC BIT(17) +#define SCU0_RSTCTL1_HACE BIT(4) +#define SCU0_RSTCTL1_CLR 0x204 +#define SCU0_RSTCTL1_CLR_EMMC BIT(17) +#define SCU0_RSTCTL1_CLR_HACE BIT(4) +#define SCU0_CLKGATE1 0x240 +#define SCU0_CLKGATE1_EMMC BIT(27) +#define SCU0_CLKGATE1_HACE BIT(13) +#define SCU0_CLKGATE1_DDRPHY BIT(11) +#define SCU0_CLKGATE1_CLR 0x244 +#define SCU0_CLKGATE1_CLR_EMMC BIT(27) +#define SCU0_CLKGATE1_CLR_HACE BIT(13) +#define SCU0_CLKGATE1_CLR_DDRPHY BIT(11) +#define SCU0_VGA0_SCRATCH 0x900 +#define SCU0_VGA0_SCRATCH_DRAM_INIT BIT(6) +#define SCU0_PCI_MISC70 0xa70 +#define SCU0_PCI_MISC70_EN_PCIEXHCI0 BIT(3) +#define SCU0_PCI_MISC70_EN_PCIEEHCI0 BIT(2) +#define SCU0_PCI_MISC70_EN_PCIEVGA0 BIT(0) +#define SCU0_PCI_MISC80 0xa80 +#define SCU0_PCI_MISC80_EN_PCIEXHCI1 BIT(3) +#define SCU0_PCI_MISC80_EN_PCIEEHCI1 BIT(2) +#define SCU0_PCI_MISC80_EN_PCIEVGA1 BIT(0) +#define SCU0_PCI_MISCF0 0xaf0 +#define SCU0_PCI_MISCF0_EN_PCIEXHCI1 BIT(3) +#define SCU0_PCI_MISCF0_EN_PCIEEHCI1 BIT(2) +#define SCU0_PCI_MISCF0_EN_PCIEVGA1 BIT(0) +#define SCU0_WPROT1 0xe04 +#define SCU0_WPROT1_0C8 BIT(18) + +/* SCU1: IO-die SCU */ +#define SCU1_REVISION 0x000 +#define SCU1_REVISION_HWID GENMASK(23, 16) +#define SCU1_REVISION_CHIP_EFUSE GENMASK(15, 8) +#define SCU1_HWSTRAP1 0x010 +#define SCU1_HWSTRAP1_DIS_CPTRA BIT(30) +#define SCU1_HWSTRAP1_RECOVERY_USB_PORT GENMASK(29, 28) +#define SCU1_HWSTRAP1_RECOVERY_INTERFACE GENMASK(27, 26) +#define SCU1_HWSTRAP1_RECOVERY_I3C (BIT(26) | BIT(27)) +#define SCU1_HWSTRAP1_RECOVERY_I2C BIT(27) +#define SCU1_HWSTRAP1_RECOVERY_USB BIT(26) +#define SCU1_HWSTRAP1_SPI_FLASH_4_BYTE_MODE BIT(25) +#define SCU1_HWSTRAP1_SPI_FLASH_WAIT_READY BIT(24) +#define SCU1_HWSTRAP1_BOOT_UFS BIT(23) +#define SCU1_HWSTRAP1_DIS_ROM BIT(22) +#define SCU1_HWSTRAP1_DIS_CPTRAJTAG BIT(20) +#define SCU1_HWSTRAP1_UARTDBGSEL BIT(19) +#define SCU1_HWSTRAP1_DIS_UARTDBG BIT(18) +#define SCU1_HWSTRAP1_DIS_WDTFULL BIT(17) +#define SCU1_HWSTRAP1_DISDEBUG1 BIT(16) +#define SCU1_HWSTRAP1_LTPI0_IO_DRIVING GENMASK(15, 14) +#define SCU1_HWSTRAP1_ACPI_1 BIT(13) +#define SCU1_HWSTRAP1_ACPI_0 BIT(12) +#define SCU1_HWSTRAP1_BOOT_EMMC_UFS BIT(11) +#define SCU1_HWSTRAP1_DDR4 BIT(10) +#define SCU1_HWSTRAP1_LOW_SECURE BIT(8) +#define SCU1_HWSTRAP1_EN_EMCS BIT(7) +#define SCU1_HWSTRAP1_EN_GPIOPT BIT(6) +#define SCU1_HWSTRAP1_EN_SECBOOT BIT(5) +#define SCU1_HWSTRAP1_EN_RECOVERY_BOOT BIT(4) +#define SCU1_HWSTRAP1_LTPI0_EN BIT(3) +#define SCU1_HWSTRAP1_LTPI_IDX BIT(2) +#define SCU1_HWSTRAP1_LTPI1_EN BIT(1) +#define SCU1_HWSTRAP1_LTPI_MODE BIT(0) +#define SCU1_HWSTRAP2 0x030 +#define SCU1_HWSTRAP2_FMC_ABR_SINGLE_FLASH BIT(29) +#define SCU1_HWSTRAP2_FMC_ABR_CS_SWAP_DIS BIT(28) +#define SCU1_HWSTRAP2_SPI_TPM_PCR_EXT_EN BIT(27) +#define SCU1_HWSTRAP2_SPI_TPM_HASH_ALGO GENMASK(26, 25) +#define SCU1_HWSTRAP2_BOOT_SPI_FREQ GENMASK(24, 23) +#define SCU1_HWSTRAP2_RESERVED GENMASK(22, 19) +#define SCU1_HWSTRAP2_FWSPI_CRTM GENMASK(18, 17) +#define SCU1_HWSTRAP2_EN_FWSPIAUX BIT(16) +#define SCU1_HWSTRAP2_FWSPISIZE GENMASK(15, 13) +#define SCU1_HWSTRAP2_DIS_REC BIT(12) +#define SCU1_HWSTRAP2_EN_CPTRA_DBG BIT(11) +#define SCU1_HWSTRAP2_TPM_PCR_INDEX GENMASK(6, 2) +#define SCU1_HWSTRAP2_ROM_CLEAR_SRAM BIT(1) +#define SCU1_HWSTRAP2_ABR BIT(0) +#define SCU1_RSTLOG0 0x050 +#define SCU1_RSTLOG0_BMC_CPU BIT(12) +#define SCU1_RSTLOG0_ABR BIT(2) +#define SCU1_RSTLOG0_EXTRSTN BIT(1) +#define SCU1_RSTLOG0_SRST BIT(0) +#define SCU1_MISC1 0x0c0 +#define SCU1_MISC1_UARTDBG_ROUTE GENMASK(23, 22) +#define SCU1_MISC1_UART12_ROUTE GENMASK(21, 20) +#define SCU1_DBGCTL 0x0c8 +#define SCU1_DBGCTL_MASK GENMASK(7, 0) +#define SCU1_DBGCTL_UARTDBG BIT(6) +#define SCU1_RNG_DATA 0x0f4 +#define SCU1_RSTCTL1 0x200 +#define SCU1_RSTCTL1_I3C(x) (BIT(16) << (x)) +#define SCU1_RSTCTL1_CLR 0x204 +#define SCU1_RSTCTL1_CLR_I3C(x) (BIT(16) << (x)) +#define SCU1_RSTCTL2 0x220 +#define SCU1_RSTCTL2_LTPI1 BIT(22) +#define SCU1_RSTCTL2_LTPI0 BIT(20) +#define SCU1_RSTCTL2_I2C BIT(15) +#define SCU1_RSTCTL2_CPTRA BIT(9) +#define SCU1_RSTCTL2_CLR 0x224 +#define SCU1_RSTCTL2_CLR_I2C BIT(15) +#define SCU1_RSTCTL2_CLR_CPTRA BIT(9) +#define SCU1_CLKGATE1 0x240 +#define SCU1_CLKGATE1_I3C(x) (BIT(16) << (x)) +#define SCU1_CLKGATE1_I2C BIT(15) +#define SCU1_CLKGATE1_CLR 0x244 +#define SCU1_CLKGATE1_CLR_I3C(x) (BIT(16) << (x)) +#define SCU1_CLKGATE1_CLR_I2C BIT(15) +#define SCU1_CLKGATE2 0x260 +#define SCU1_CLKGATE2_LTPI1_TX BIT(19) +#define SCU1_CLKGATE2_LTPI_AHB BIT(10) +#define SCU1_CLKGATE2_LTPI0_TX BIT(9) +#define SCU1_CLKGATE2_CLR 0x264 + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2700.h b/arch/arm/include/asm/arch-aspeed/scu_ast2700.h new file mode 100644 index 00000000000..b973fcc6610 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2700.h @@ -0,0 +1,514 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef _ASM_ARCH_SCU_AST2700_H +#define _ASM_ARCH_SCU_AST2700_H + +#include <linux/types.h> + +/* SoC0 SCU Register */ +#define SCU_CPU_REVISION_ID_HW GENMASK(23, 16) +#define SCU_CPU_REVISION_ID_EFUSE GENMASK(15, 8) + +#define SCU_CPU_HWSTRAP_DIS_RVAS BIT(30) +#define SCU_CPU_HWSTRAP_DP_SRC BIT(29) +#define SCU_CPU_HWSTRAP_DAC_SRC BIT(28) +#define SCU_CPU_HWSTRAP_VRAM_SIZE GENMASK(11, 10) +#define SCU_CPU_HWSTRAP_DIS_CPU BIT(0) + +#define SCU_CPU_MISC_DP_RESET_SRC BIT(11) +#define SCU_CPU_MISC_XDMA_CLIENT_EN BIT(4) +#define SCU_CPU_MISC_2D_CLIENT_EN BIT(3) + +#define SCU_CPU_RST_SSP BIT(30) +#define SCU_CPU_RST_DPMCU BIT(29) +#define SCU_CPU_RST_DP BIT(28) +#define SCU_CPU_RST_XDMA1 BIT(26) +#define SCU_CPU_RST_XDMA0 BIT(25) +#define SCU_CPU_RST_EMMC BIT(17) +#define SCU_CPU_RST_EN_DP_PCI BIT(15) +#define SCU_CPU_RST_CRT BIT(13) +#define SCU_CPU_RST_RVAS1 BIT(10) +#define SCU_CPU_RST_RVAS0 BIT(9) +#define SCU_CPU_RST_2D BIT(7) +#define SCU_CPU_RST_VIDEO BIT(6) +#define SCU_CPU_RST_SOC BIT(5) +#define SCU_CPU_RST_DDRPHY BIT(1) + +#define SCU_CPU_RST2_VGA BIT(12) +#define SCU_CPU_RST2_E2M1 BIT(11) +#define SCU_CPU_RST2_E2M0 BIT(10) +#define SCU_CPU_RST2_TSP BIT(9) + +#define SCU_CPU_VGA_FUNC_DAC_OUTPUT GENMASK(11, 10) +#define SCU_CPU_VGA_FUNC_DP_OUTPUT GENMASK(9, 8) +#define SCU_CPU_VGA_FUNC_DAC_DISABLE BIT(7) + +#define SCU_CPU_PCI_MISC0C_FB_SIZE GENMASK(4, 0) + +#define SCU_CPU_PCI_MISC70_EN_XHCI BIT(3) +#define SCU_CPU_PCI_MISC70_EN_EHCI BIT(2) +#define SCU_CPU_PCI_MISC70_EN_IPMI BIT(1) +#define SCU_CPU_PCI_MISC70_EN_VGA BIT(0) + +#define SCU_CPU_HPLL_P GENMASK(22, 19) +#define SCU_CPU_HPLL_N GENMASK(18, 13) +#define SCU_CPU_HPLL_M GENMASK(12, 0) + +#define SCU_CPU_HPLL2_LOCK BIT(31) +#define SCU_CPU_HPLL2_BWADJ GENMASK(11, 0) + +#define SCU_CPU_SSP_TSP_RESET_STS BIT(8) +#define SCU_CPU_SSP_TSP_SRAM_SD BIT(7) +#define SCU_CPU_SSP_TSP_SRAM_DSLP BIT(6) +#define SCU_CPU_SSP_TSP_SRAM_SLP BIT(5) +#define SCU_CPU_SSP_TSP_NIDEN BIT(4) +#define SCU_CPU_SSP_TSP_DBGEN BIT(3) +#define SCU_CPU_SSP_TSP_DBG_ENABLE BIT(2) +#define SCU_CPU_SSP_TSP_RESET BIT(1) +#define SCU_CPU_SSP_TSP_ENABLE BIT(0) + +/* SoC1 SCU Register */ +#define SCU_IO_HWSTRAP_UFS BIT(23) +#define SCU_IO_HWSTRAP_EMMC BIT(11) +#define SCU_IO_HWSTRAP_SECBOOT BIT(5) +#define SCU_IO_HWSTRAP_LTPI0_EN BIT(3) +#define SCU_IO_HWSTRAP_LTPI1_EN BIT(1) + +/* CLK information */ +#define CLKIN_25M 25000000UL + +#define SCU_CPU_CLKGATE1_RVAS1 BIT(28) +#define SCU_CPU_CLKGATE1_RVAS0 BIT(25) +#define SCU_CPU_CLKGATE1_E2M1 BIT(19) +#define SCU_CPU_CLKGATE1_DP BIT(18) +#define SCU_CPU_CLKGATE1_DAC BIT(17) +#define SCU_CPU_CLKGATE1_E2M0 BIT(12) +#define SCU_CPU_CLKGATE1_VGA1 BIT(10) +#define SCU_CPU_CLKGATE1_VGA0 BIT(5) + +/* + * Clock divider/multiplier configuration struct. + * For H-PLL and M-PLL the formula is + * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) + * M - Numerator + * N - Denumerator + * P - Post Divider + * They have the same layout in their control register. + * + */ +union ast2700_pll_reg { + u32 w; + struct { + uint16_t m : 13; /* bit[12:0] */ + uint8_t n : 6; /* bit[18:13] */ + uint8_t p : 4; /* bit[22:19] */ + uint8_t off : 1; /* bit[23] */ + uint8_t bypass : 1; /* bit[24] */ + uint8_t reset : 1; /* bit[25] */ + uint8_t reserved : 6; /* bit[31:26] */ + } b; +}; + +struct ast2700_pll_cfg { + union ast2700_pll_reg reg; + unsigned int ext_reg; +}; + +struct ast2700_pll_desc { + u32 in; + u32 out; + struct ast2700_pll_cfg cfg; +}; + +struct aspeed_clks { + ulong id; + const char *name; +}; + +#ifndef __ASSEMBLY__ +struct ast2700_scu0 { + u32 chip_id1; /* 0x000 */ + u32 rsv_0x04[3]; /* 0x004 ~ 0x00C */ + u32 hwstrap1; /* 0x010 */ + u32 hwstrap1_clr; /* 0x014 */ + u32 rsv_0x18[2]; /* 0x018 ~ 0x01C */ + u32 hwstrap1_lock; /* 0x020 */ + u32 hwstrap1_sec1; /* 0x024 */ + u32 hwstrap1_sec2; /* 0x028 */ + u32 hwstrap1_sec3; /* 0x02C */ + u32 rsv_0x30[8]; /* 0x030 ~ 0x4C */ + u32 sysrest_log1; /* 0x050 */ + u32 sysrest_log1_sec1; /* 0x054 */ + u32 sysrest_log1_sec2; /* 0x058 */ + u32 sysrest_log1_sec3; /* 0x05C */ + u32 sysrest_log2; /* 0x060 */ + u32 sysrest_log2_sec1; /* 0x064 */ + u32 sysrest_log2_sec2; /* 0x068 */ + u32 sysrest_log2_sec3; /* 0x06C */ + u32 sysrest_log3; /* 0x070 */ + u32 sysrest_log3_sec1; /* 0x074 */ + u32 sysrest_log3_sec2; /* 0x078 */ + u32 sysrest_log3_sec3; /* 0x07C */ + u32 rsv_0x80[8]; /* 0x080 ~ 0x9C */ + u32 probe_sig_select; /* 0x0A0 */ + u32 probe_sig_enable1; /* 0x0A4 */ + u32 probe_sig_enable2; /* 0x0A8 */ + u32 uart_dbg_rate; /* 0x0AC */ + u32 rsv_0xB0[4]; /* 0x0B0 ~ 0xBC*/ + u32 misc; /* 0x0C0 */ + u32 rsv_0xC4; /* 0x0C4 */ + u32 debug_ctrl; /* 0x0C8 */ + u32 rsv_0xCC[5]; /* 0x0CC ~ 0x0DC */ + u32 free_counter_read_low; /* 0x0E0 */ + u32 free_counter_read_high; /* 0x0E4 */ + u32 rsv_0xE8[2]; /* 0x0E8 ~ 0x0EC */ + u32 random_num_ctrl; /* 0x0F0 */ + u32 random_num_data; /* 0x0F4 */ + u32 rsv_0xF8[10]; /* 0x0F8 ~ 0x11C */ + u32 ssp_ctrl_1; /* 0x120 */ + u32 ssp_ctrl_2; /* 0x124 */ + u32 ssp_ctrl_3; /* 0x128 */ + u32 ssp_ctrl_4; /* 0x12C */ + u32 ssp_ctrl_5; /* 0x130 */ + u32 ssp_ctrl_6; /* 0x134 */ + u32 ssp_ctrl_7; /* 0x138 */ + u32 rsv_0x13c[1]; /* 0x13C */ + u32 ssp_remap0_base; /* 0x140 */ + u32 ssp_remap0_size; /* 0x144 */ + u32 ssp_remap1_base; /* 0x148 */ + u32 ssp_remap1_size; /* 0x14c */ + u32 ssp_remap2_base; /* 0x150 */ + u32 ssp_remap2_size; /* 0x154 */ + u32 rsv_0x158[2]; /* 0x158 ~ 0x15C */ + u32 tsp_ctrl_1; /* 0x160 */ + u32 rsv_0x164[1]; /* 0x164 */ + u32 tsp_ctrl_3; /* 0x168 */ + u32 tsp_ctrl_4; /* 0x16C */ + u32 tsp_ctrl_5; /* 0x170 */ + u32 tsp_ctrl_6; /* 0x174 */ + u32 tsp_ctrl_7; /* 0x178 */ + u32 rsv_0x17c[6]; /* 0x17C ~ 0x190 */ + u32 tsp_remap_size; /* 0x194 */ + u32 rsv_0x198[26]; /* 0x198 ~ 0x1FC */ + u32 modrst1_ctrl; /* 0x200 */ + u32 modrst1_clr; /* 0x204 */ + u32 rsv_0x208[2]; /* 0x208 ~ 0x20C */ + u32 modrst1_lock; /* 0x210 */ + u32 modrst1_prot1; /* 0x214 */ + u32 modrst1_prot2; /* 0x218 */ + u32 modrst1_prot3; /* 0x21C */ + u32 modrst2_ctrl; /* 0x220 */ + u32 modrst2_clr; /* 0x224 */ + u32 rsv_0x228[2]; /* 0x228 ~ 0x22C */ + u32 modrst2_lock; /* 0x230 */ + u32 modrst2_prot1; /* 0x234 */ + u32 modrst2_prot2; /* 0x238 */ + u32 modrst2_prot3; /* 0x23C */ + u32 clkgate_ctrl; /* 0x240 */ + u32 clkgate_clr; /* 0x244 */ + u32 rsv_0x248[2]; /* 0x248 */ + u32 clkgate_lock; /* 0x250 */ + u32 clkgate_secure1; /* 0x254 */ + u32 clkgate_secure2; /* 0x258 */ + u32 clkgate_secure3; /* 0x25c */ + u32 rsv_0x260[8]; /* 0x260 */ + u32 clk_sel1; /* 0x280 */ + u32 clk_sel2; /* 0x284 */ + u32 clk_sel3; /* 0x288 */ + u32 rsv_0x28c; /* 0x28c */ + u32 clk_sel1_lock; /* 0x290 */ + u32 clk_sel2_lock; /* 0x294 */ + u32 clk_sel3_lock; /* 0x298 */ + u32 rsv_0x29c; /* 0x29c */ + u32 clk_sel1_secure1; /* 0x2a0 */ + u32 clk_sel1_secure2; /* 0x2a4 */ + u32 clk_sel1_secure3; /* 0x2a8 */ + u32 rsv_0x2ac; /* 0x2ac */ + u32 clk_sel2_secure1; /* 0x2b0 */ + u32 clk_sel2_secure2; /* 0x2b4 */ + u32 clk_sel2_secure3; /* 0x2b8 */ + u32 rsv_0x2bc; /* 0x2bc */ + u32 clk_sel3_secure1; /* 0x2c0 */ + u32 clk_sel3_secure2; /* 0x2c4 */ + u32 clk_sel3_secure3; /* 0x2c8 */ + u32 rsv_0x2cc[9]; /* 0x2cc */ + u32 extrst_sel; /* 0x2f0 */ + u32 rsv_0x2f4[3]; /* 0x2f4 */ + u32 hpll; /* 0x300 */ + u32 hpll_ext; /* 0x304 */ + u32 dpll; /* 0x308 */ + u32 dpll_ext; /* 0x30C */ + u32 mpll; /* 0x310 */ + u32 mpll_ext; /* 0x314 */ + u32 rsv_0x318[2]; /* 0x318 ~ 0x31C */ + u32 d1clk_para; /* 0x320 */ + u32 rsv_0x324[3]; /* 0x324 ~ 0x32C */ + u32 d2clk_para; /* 0x330 */ + u32 rsv_0x334[3]; /* 0x334 ~ 0x33C */ + u32 crt1clk_para; /* 0x340 */ + u32 rsv_0x344[3]; /* 0x344 ~ 0x34C */ + u32 crt2clk_para; /* 0x350 */ + u32 rsv_0x354[3]; /* 0x354 ~ 0x35C */ + u32 mphyclk_para; /* 0x360 */ + u32 rsv_0x364[7]; /* 0x364 ~ 0x37C */ + u32 clkduty_meas_ctrl; /* 0x380 */ + u32 clkduty1; /* 0x384 */ + u32 clkduty2; /* 0x368 */ + u32 clkduty_meas_res; /* 0x38c */ + u32 rsv_0x390[4]; /* 0x390 ~ 0x39C */ + u32 freq_counter_ctrl; /* 0x3a0 */ + u32 freq_counter_cmp; /* 0x3a4 */ + u32 prog_delay_ring_ctrl0; /* 0x3a8 */ + u32 prog_delay_ring_ctrl1; /* 0x3ac */ + u32 freq_counter_readback; /* 0x3b0 */ + u32 rsv_0x3b4[19]; /* 0x3b4 */ + u32 pinmux1; /* 0x400 */ + u32 pinmux2; /* 0x404 */ + u32 pinmux3; /* 0x408 */ + u32 rsv_0x40c; /* 0x40C */ + u32 pinmux4; /* 0x410 */ + u32 vga_func_ctrl; /* 0x414 */ + u32 rsv_0x418[2]; /* 0x418 */ + u32 pinmux_lock0; /* 0x420 */ + u32 pinmux_lock1; /* 0x424 */ + u32 pinmux_lock2; /* 0x428 */ + u32 rsv_0x42c; + u32 pinmux_lock3; /* 0x430 */ + u32 pinmux_lock4; /* 0x434 */ + u32 rsv_0x438[18]; + u32 gpio18d0_ioctrl; /* 0x480 */ + u32 gpio18d1_ioctrl; /* 0x484 */ + u32 gpio18d2_ioctrl; /* 0x488 */ + u32 gpio18d3_ioctrl; /* 0x48c */ + u32 gpio18d4_ioctrl; /* 0x490 */ + u32 gpio18d5_ioctrl; /* 0x494 */ + u32 gpio18d6_ioctrl; /* 0x498 */ + u32 gpio18d7_ioctrl; /* 0x49c */ + u32 gpio18e0_ioctrl; /* 0x4a0 */ + u32 gpio18e1_ioctrl; /* 0x4a4 */ + u32 gpio18e2_ioctrl; /* 0x4a8 */ + u32 gpio18e3_ioctrl; /* 0x4ac */ + u32 jtag_ioctrl; /* 0x4b0 */ + u32 uart_ioctrl; /* 0x4b4 */ + u32 misc_ioctrl; /* 0x4b8 */ + u32 rsv_0x4bc[17]; /* 0x4bc ~ 0x4fc */ + u32 pinmux_seucre0_0; /* 0x500 */ + u32 pinmux_seucre0_1; /* 0x504 */ + u32 pinmux_seucre0_2; /* 0x508 */ + u32 rsv_0x50c; + u32 pinmux_seucre0_3; /* 0x510 */ + u32 pinmux_seucre0_4; /* 0x514 */ + u32 rsv_0x518[58]; + u32 pinmux_seucre1_0; /* 0x600 */ + u32 pinmux_seucre1_1; /* 0x604 */ + u32 pinmux_seucre1_2; /* 0x608 */ + u32 rsv_0x60c; + u32 pinmux_seucre1_3; /* 0x610 */ + u32 pinmux_seucre1_4; /* 0x614 */ + u32 rsv_0x618[58]; + u32 pinmux_seucre2_0; /* 0x700 */ + u32 pinmux_seucre2_1; /* 0x704 */ + u32 pinmux_seucre2_2; /* 0x708 */ + u32 rsv_0x70c; + u32 pinmux_seucre2_3; /* 0x710 */ + u32 pinmux_seucre2s_4; /* 0x714 */ + u32 rsv_0x718[26]; + u32 cpu_scratch[96]; /* 0x780 ~ 0x8FC */ + u32 vga0_scratch1[4]; /* 0x900 ~ 0x90C */ + u32 vga1_scratch1[4]; /* 0x910 ~ 0x91C */ + u32 vga0_scratch2[8]; /* 0x920 ~ 0x93C */ + u32 vga1_scratch2[8]; /* 0x940 ~ 0x95C */ + u32 pci_cfg1[3]; /* 0x960 ~ 0x968 */ + u32 rsv_0x96c; /* 0x96C */ + u32 pcie_cfg1; /* 0x970 */ + u32 mmio_decode1; /* 0x974 */ + u32 reloc_ctrl_decode1[2]; /* 0x978 ~ 0x97C */ + u32 rsv_0x980[4]; /* 0x980 ~ 0x98C */ + u32 mbox_decode1; /* 0x990 */ + u32 shared_sram_decode1[2];/* 0x994 ~ 0x998 */ + u32 rsv_0x99c; /* 0x99C */ + u32 pci_cfg2[3]; /* 0x9A0 ~ 0x9A8 */ + u32 rsv_0x9ac; /* 0x9AC */ + u32 pcie_cfg2; /* 0x9B0 */ + u32 mmio_decode2; /* 0x9B4 */ + u32 reloc_ctrl_decode2[2]; /* 0x9B8 ~ 0x9BC */ + u32 rsv_0x9c0[4]; /* 0x9C0 ~ 0x9CC */ + u32 mbox_decode2; /* 0x9D0 */ + u32 shared_sram_decode2[2];/* 0x9D4 ~ 0x9D8 */ + u32 rsv_0x9dc[9]; /* 0x9DC ~ 0x9FC */ + u32 pci0_misc[32]; /* 0xA00 ~ 0xA7C */ + u32 pci1_misc[32]; /* 0xA80 ~ 0xAFC */ +}; + +struct ast2700_scu1 { + u32 chip_id1; /* 0x000 */ + u32 rsv_0x04[3]; /* 0x004 ~ 0x00C */ + u32 hwstrap1; /* 0x010 */ + u32 hwstrap1_clr; /* 0x014 */ + u32 rsv_0x18[2]; /* 0x018 ~ 0x01C */ + u32 hwstrap1_lock; /* 0x020 */ + u32 hwstrap1_sec1; /* 0x024 */ + u32 hwstrap1_sec2; /* 0x028 */ + u32 hwstrap1_sec3; /* 0x02C */ + u32 hwstrap2; /* 0x030 */ + u32 hwstrap2_clr; /* 0x034 */ + u32 rsv_0x38[2]; /* 0x038 ~ 0x03C */ + u32 hwstrap2_lock; /* 0x040 */ + u32 hwstrap2_sec1; /* 0x044 */ + u32 hwstrap2_sec2; /* 0x048 */ + u32 hwstrap2_sec3; /* 0x04C */ + u32 sysrest_log1; /* 0x050 */ + u32 sysrest_log1_sec1; /* 0x054 */ + u32 sysrest_log1_sec2; /* 0x058 */ + u32 sysrest_log1_sec3; /* 0x05C */ + u32 sysrest_log2; /* 0x060 */ + u32 sysrest_log2_sec1; /* 0x064 */ + u32 sysrest_log2_sec2; /* 0x068 */ + u32 sysrest_log2_sec3; /* 0x06C */ + u32 sysrest_log3; /* 0x070 */ + u32 sysrest_log3_sec1; /* 0x074 */ + u32 sysrest_log3_sec2; /* 0x078 */ + u32 sysrest_log3_sec3; /* 0x07C */ + u32 sysrest_log4; /* 0x080 */ + u32 sysrest_log4_sec1; /* 0x084 */ + u32 sysrest_log4_sec2; /* 0x088 */ + u32 sysrest_log4_sec3; /* 0x08C */ + u32 rsv_0x90[7]; /* 0x090 ~ 0xA8 */ + u32 uart_dbg_rate; /* 0x0AC */ + u32 rsv_0xB0[4]; /* 0x0B0 ~ 0xBC*/ + u32 misc; /* 0x0C0 */ + u32 rsv_0xC4; /* 0x0C4 */ + u32 debug_ctrl; /* 0x0C8 */ + u32 rsv_0xCC; /* 0x0CC */ + u32 dac_ctrl; /* 0x0D0 */ + u32 dac_crc_ctrl; /* 0x0D4 */ + u32 rsv_0xD8[2]; /* 0x0D8 ~ 0x0DC */ + u32 video_input_ctrl; /* 0x0E0 */ + u32 rsv_0xE4[3]; /* 0x0E4 ~ 0x0EC */ + u32 random_num_ctrl; /* 0x0F0 */ + u32 random_num_data; /* 0x0F4 */ + u32 rsv_0xF0[2]; /* 0x0F8 ~ 0x0FC */ + u32 rsv_0x100[32]; /* 0x100 ~ 0x17C */ + u32 scratch[32]; /* 0x180 ~ 0x1FC */ + u32 modrst1_ctrl; /* 0x200 */ + u32 modrst1_clr; /* 0x204 */ + u32 rsv_0x208[2]; /* 0x208 ~ 0x20C */ + u32 modrst_lock1; /* 0x210 */ + u32 modrst1_sec1; /* 0x214 */ + u32 modrst1_sec2; /* 0x218 */ + u32 modrst1_sec3; /* 0x21C */ + u32 modrst2_ctrl; /* 0x220 */ + u32 modrst2_clr; /* 0x224 */ + u32 rsv_0x228[2]; /* 0x228 ~ 0x22C */ + u32 modrst2_lock; /* 0x230 */ + u32 modrst2_prot1; /* 0x234 */ + u32 modrst2_prot2; /* 0x238 */ + u32 modrst2_prot3; /* 0x23C */ + u32 clkgate_ctrl1; /* 0x240 */ + u32 clkgate_clr1; /* 0x244 */ + u32 rsv_0x248[2]; /* 0x248 */ + u32 clkgate_lock1; /* 0x250 */ + u32 clkgate_secure11; /* 0x254 */ + u32 clkgate_secure12; /* 0x258 */ + u32 clkgate_secure13; /* 0x25c */ + u32 clkgate_ctrl2; /* 0x260 */ + u32 clkgate_clr2; /* 0x264 */ + u32 rsv_0x268[2]; /* 0x268 */ + u32 clkgate_lock2; /* 0x270 */ + u32 clkgate_secure21; /* 0x274 */ + u32 clkgate_secure22; /* 0x278 */ + u32 clkgate_secure23; /* 0x27c */ + u32 clk_sel1; /* 0x280 */ + u32 clk_sel2; /* 0x284 */ + u32 rsv_0x288[2]; /* 0x288 */ + u32 clk_sel1_lock; /* 0x290 */ + u32 clk_sel2_lock; /* 0x294 */ + u32 rsv_0x298[2]; /* 0x298 */ + u32 clk_sel1_secure1; /* 0x2a0 */ + u32 clk_sel1_secure2; /* 0x2a4 */ + u32 rsv_0x2a8[2]; /* 0x2a8 */ + u32 clk_sel2_secure1; /* 0x2b0 */ + u32 clk_sel2_secure2; /* 0x2b4 */ + u32 rsv_0x2b8[2]; /* 0x2b8 */ + u32 clk_sel3_secure1; /* 0x2c0 */ + u32 clk_sel3_secure2; /* 0x2c4 */ + u32 rsv_0x2c8[10]; /* 0x2c8 */ + u32 extrst_sel1; /* 0x2f0 */ + u32 extrst_sel2; /* 0x2f4 */ + u32 rsv_0x2f8[2]; /* 0x2f8 */ + u32 hpll; /* 0x300 */ + u32 hpll_ext; /* 0x304 */ + u32 rsv_0x308[2]; /* 0x308 ~ 0x30C */ + u32 apll; /* 0x310 */ + u32 apll_ext; /* 0x314 */ + u32 rsv_0x318[2]; /* 0x318 ~ 0x31C */ + u32 dpll; /* 0x320 */ + u32 dpll_ext; /* 0x324 */ + u32 rsv_0x328[2]; /* 0x328 ~ 0x32C */ + u32 uxclk_ctrl; /* 0x330 */ + u32 huxclk_ctrl; /* 0x334 */ + u32 rsv_0x338[18]; /* 0x338 ~ 0x37C */ + u32 clkduty_meas_ctrl; /* 0x380 */ + u32 clkduty1; /* 0x384 */ + u32 clkduty2; /* 0x388 */ + u32 rsv_0x38c; /* 0x38c */ + u32 mac_delay; /* 0x390 */ + u32 mac_100m_delay; /* 0x394 */ + u32 mac_10m_delay; /* 0x398 */ + u32 rsv_0x39c; /* 0x39c */ + u32 freq_counter_ctrl; /* 0x3a0 */ + u32 freq_counter_cmp; /* 0x3a4 */ + u32 rsv_0x3a8[2]; /* 0x3a8 ~ 0x3aC */ + u32 usb_ctrl; /* 0x3b0 */ + u32 usb_lock; /* 0x3b4 */ + u32 usb_secure1; /* 0x3b8 */ + u32 usb_secure2; /* 0x3bc */ + u32 usb_secure3; /* 0x3c0 */ + u32 rsv_0x3c4[15]; /* 0x3c4 ~ 0x3fc */ + u32 pinumx1; /* 0x400 */ + u32 pinumx2; /* 0x404 */ + u32 pinumx3; /* 0x408 */ + u32 pinumx4; /* 0x40c */ + u32 pinumx5; /* 0x410 */ + u32 pinumx6; /* 0x414 */ + u32 pinumx7; /* 0x418 */ + u32 pinumx8; /* 0x41c */ + u32 pinumx9; /* 0x420 */ + u32 pinumx10; /* 0x424 */ + u32 pinumx11; /* 0x428 */ + u32 pinumx12; /* 0x42c */ + u32 pinumx13; /* 0x430 */ + u32 pinumx14; /* 0x434 */ + u32 pinumx15; /* 0x438 */ + u32 pinumx16; /* 0x43c */ + u32 pinumx17; /* 0x440 */ + u32 pinumx18; /* 0x444 */ + u32 pinumx19; /* 0x448 */ + u32 pinumx20; /* 0x44c */ + u32 pinumx21; /* 0x450 */ + u32 pinumx22; /* 0x454 */ + u32 pinumx23; /* 0x458 */ + u32 pinumx24; /* 0x45c */ + u32 pinumx25; /* 0x460 */ + u32 pinumx26; /* 0x464 */ + u32 pinumx27; /* 0x468 */ + u32 rsv_0x46c[4]; /* 0x46c ~ 0x478 */ + u32 pinumx31; /* 0x47c */ + u32 pull_down_dis[8]; /* 0x480 ~ 0x49c */ + u32 pin_conf; /* 0x4a0 */ + u32 rsv_0x4a4[7]; /* 0x4a4 ~ 0x4bc */ + u32 io_driving0; /* 0x4c0 */ + u32 io_driving1; /* 0x4c4 */ + u32 io_driving2; /* 0x4c8 */ + u32 io_driving3; /* 0x4cc */ + u32 io_driving4; /* 0x4d0 */ + u32 io_driving5; /* 0x4d4 */ + u32 io_driving6; /* 0x4d8 */ + u32 io_driving7; /* 0x4dc */ + u32 io_driving8; /* 0x4e0 */ +}; + +#endif +#endif diff --git a/arch/arm/include/asm/arch-aspeed/sdram.h b/arch/arm/include/asm/arch-aspeed/sdram.h new file mode 100644 index 00000000000..daf48dd6ed1 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/sdram.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef __ASM_AST2700_SDRAM_H__ +#define __ASM_AST2700_SDRAM_H__ + +struct sdrammc_regs { + u32 prot_key; + u32 intr_status; + u32 intr_clear; + u32 intr_mask; + u32 mcfg; + u32 mctl; + u32 msts; + u32 error_status; + u32 actime1; + u32 actime2; + u32 actime3; + u32 actime4; + u32 actime5; + u32 actime6; + u32 actime7; + u32 dfi_timing; + u32 dcfg; + u32 dctl; + u32 mrctl; + u32 mrwr; + u32 mrrd; + u32 mr01; + u32 mr23; + u32 mr45; + u32 mr67; + u32 refctl; + u32 refmng_ctl; + u32 refsts; + u32 zqctl; + u32 ecc_addr_range; + u32 ecc_failure_status; + u32 ecc_failure_addr; + u32 ecc_test_control; + u32 ecc_test_status; + u32 arbctl; + u32 enccfg; + u32 protect_lock_set; + u32 protect_lock_status; + u32 protect_lock_reset; + u32 enc_min_addr; + u32 enc_max_addr; + u32 enc_key[4]; + u32 enc_iv[3]; + u32 bistcfg; + u32 bist_addr; + u32 bist_size; + u32 bist_patt; + u32 bist_res; + u32 bist_fail_addr; + u32 bist_fail_data[4]; + u32 reserved2[2]; + u32 debug_control; + u32 debug_status; + u32 phy_intf_status; + u32 testcfg; + u32 gfmcfg; + u32 gfm0ctl; + u32 gfm1ctl; + u32 reserved3[0xf8]; +}; + +#define DRAMC_UNLK_KEY 0x1688a8a8 + +/* offset 0x04 */ +#define DRAMC_IRQSTA_PWRCTL_ERR BIT(16) +#define DRAMC_IRQSTA_PHY_ERR BIT(15) +#define DRAMC_IRQSTA_LOWPOWER_DONE BIT(12) +#define DRAMC_IRQSTA_FREQ_CHG_DONE BIT(11) +#define DRAMC_IRQSTA_REF_DONE BIT(10) +#define DRAMC_IRQSTA_ZQ_DONE BIT(9) +#define DRAMC_IRQSTA_BIST_DONE BIT(8) +#define DRAMC_IRQSTA_ECC_RCVY_ERR BIT(5) +#define DRAMC_IRQSTA_ECC_ERR BIT(4) +#define DRAMC_IRQSTA_PROT_ERR BIT(3) +#define DRAMC_IRQSTA_OVERSZ_ERR BIT(2) +#define DRAMC_IRQSTA_MR_DONE BIT(1) +#define DRAMC_IRQSTA_PHY_INIT_DONE BIT(0) + +/* offset 0x14 */ +#define DRAMC_MCTL_WB_SOFT_RESET BIT(24) +#define DRAMC_MCTL_PHY_CLK_DIS BIT(18) +#define DRAMC_MCTL_PHY_RESET BIT(17) +#define DRAMC_MCTL_PHY_POWER_ON BIT(16) +#define DRAMC_MCTL_FREQ_CHG_START BIT(3) +#define DRAMC_MCTL_PHY_LOWPOWER_START BIT(2) +#define DRAMC_MCTL_SELF_REF_START BIT(1) +#define DRAMC_MCTL_PHY_INIT_START BIT(0) + +/* offset 0x40 */ +#define DRAMC_DFICFG_WD_POL BIT(18) +#define DRAMC_DFICFG_CKE_OUT BIT(17) +#define DRAMC_DFICFG_RESET BIT(16) + +/* offset 0x48 */ +#define DRAMC_MRCTL_ERR_STATUS BIT(31) +#define DRAMC_MRCTL_READY_STATUS BIT(30) +#define DRAMC_MRCTL_MR_ADDR BIT(8) +#define DRAMC_MRCTL_CMD_DLL_RST BIT(7) +#define DRAMC_MRCTL_CMD_DQ_SEL BIT(6) +#define DRAMC_MRCTL_CMD_TYPE BIT(2) +#define DRAMC_MRCTL_CMD_WR_CTL BIT(1) +#define DRAMC_MRCTL_CMD_START BIT(0) + +/* offset 0xC0 */ +#define DRAMC_BISTRES_RUNNING BIT(10) +#define DRAMC_BISTRES_FAIL BIT(9) +#define DRAMC_BISTRES_DONE BIT(8) +#define DRAMC_BISTCFG_INIT_MODE BIT(7) +#define DRAMC_BISTCFG_PMODE GENMASK(6, 4) +#define DRAMC_BISTCFG_BMODE GENMASK(3, 2) +#define DRAMC_BISTCFG_ENABLE BIT(1) +#define DRAMC_BISTCFG_START BIT(0) +#define BIST_PMODE_CRC (3) +#define BIST_BMODE_RW_SWITCH (3) + +/* DRAMC048 MR Control Register */ +#define MR_TYPE_SHIFT 2 +#define MR_RW (0 << MR_TYPE_SHIFT) +#define MR_MPC BIT(2) +#define MR_VREFCS (2 << MR_TYPE_SHIFT) +#define MR_VREFCA (3 << MR_TYPE_SHIFT) +#define MR_ADDRESS_SHIFT 8 +#define MR_ADDR(n) (((n) << MR_ADDRESS_SHIFT) | DRAMC_MRCTL_CMD_WR_CTL) +#define MR_NUM_SHIFT 4 +#define MR_NUM(n) ((n) << MR_NUM_SHIFT) +#define MR_DLL_RESET BIT(7) +#define MR_1T_MODE BIT(16) + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h new file mode 100644 index 00000000000..3b78e73c726 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/sys_proto.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2026 Free Mobile - Vincent Jardin + * + * Layerscape mirror of the i.MX <asm/mach-imx/sys_proto.h>: declares + * the SoC-personality helpers consumed by generic drivers that work on + * both i.MX and QorIQ/Layerscape parts (e.g. drivers/thermal/imx_tmu.c + * for the QorIQ TMU variant). + */ + +#ifndef _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H +#define _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H + +#include <linux/types.h> + +/* + * Per LX2160A Reference Manual, Rev. 1 (10/2021): + * - section 1.12.1: "NXP specs max power at 105 degC junction" for + * commercial / embedded operating conditions. + * - section 28.1: TMU "Accuracy within +/- 3 degC". + * + * Layerscape SoCs do not expose an OCOTP-style "CPU temp grade" fuse, + * so the implementation returns the documented junction-temperature + * limit from the data sheet (-40 .. 105 degC commercial range). The + * thermal driver subtracts 10 degC for its alert threshold, which + * comfortably clears the +/- 3 degC TMU accuracy in both directions. + */ +u32 get_cpu_temp_grade(int *minc, int *maxc); + +#endif /* _ASM_ARCH_FSL_LAYERSCAPE_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 25d0f205fde..bbc4b421a02 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -48,6 +48,8 @@ #define MXC_CPU_IMX8MPL 0x187 /* dummy ID */ #define MXC_CPU_IMX8MPD 0x188 /* dummy ID */ #define MXC_CPU_IMX8MPUL 0x189 /* dummy ID */ +#define MXC_CPU_IMX8MPD2 0x18c /* dummy ID */ +#define MXC_CPU_IMX8MP5 0x18d /* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h index a038cc1df33..f9c5e21c14f 100644 --- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h @@ -20,8 +20,6 @@ #define SIM1_BASE_ADDR 0x29290000 -#define WDG3_RBASE 0x292a0000UL - #define SIM_SEC_BASE_ADDR 0x2802B000 #define CGC1_SOSCDIV_ADDR 0x292C0108 diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index a8e3f7354c7..b0f90b53f64 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2022 NXP + * Copyright 2022-2026 NXP */ #ifndef __ASM_ARCH_IMX8M_DDR_H @@ -13,21 +13,21 @@ #define DDR_PHY_BASE 0x4E100000 #define DDRMIX_BLK_CTRL_BASE 0x4E010000 -#define REG_DDR_SDRAM_MD_CNTL (DDR_CTL_BASE + 0x120) -#define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0) -#define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8) +#define REG_DDR_SDRAM_MD_CNTL (DDR_CTL_BASE + 0x120) +#define REG_DDR_CS0_BNDS (DDR_CTL_BASE + 0x0) +#define REG_DDR_CS1_BNDS (DDR_CTL_BASE + 0x8) #define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) -#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104) +#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104) #define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) -#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160) +#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160) #define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48) -#define REG_DDR_SDRAM_CFG_3 (DDR_CTL_BASE + 0x260) -#define REG_DDR_SDRAM_CFG_4 (DDR_CTL_BASE + 0x264) -#define REG_DDR_SDRAM_MD_CNTL_2 (DDR_CTL_BASE + 0x270) -#define REG_DDR_SDRAM_MPR4 (DDR_CTL_BASE + 0x28C) -#define REG_DDR_SDRAM_MPR5 (DDR_CTL_BASE + 0x290) +#define REG_DDR_SDRAM_CFG_3 (DDR_CTL_BASE + 0x260) +#define REG_DDR_SDRAM_CFG_4 (DDR_CTL_BASE + 0x264) +#define REG_DDR_SDRAM_MD_CNTL_2 (DDR_CTL_BASE + 0x270) +#define REG_DDR_SDRAM_MPR4 (DDR_CTL_BASE + 0x28C) +#define REG_DDR_SDRAM_MPR5 (DDR_CTL_BASE + 0x290) -#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000) +#define REG_DDR_ERR_EN (DDR_CTL_BASE + 0x1000) #define SRC_BASE_ADDR (0x44460000) #define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400) @@ -100,6 +100,52 @@ struct dram_timing_info { extern struct dram_timing_info dram_timing; +/* Quick Boot related */ +#define DDRPHY_QB_CSR_SIZE 5168 +#define DDRPHY_QB_ACSM_SIZE (4 * 1024) +#define DDRPHY_QB_MSB_SIZE 0x200 +#define DDRPHY_QB_PSTATES 0 +#define DDRPHY_QB_PST_SIZE (DDRPHY_QB_PSTATES * 4 * 1024) + +/* + * This structure needs to be aligned with the one in OEI. + */ +struct ddrphy_qb_state { + u32 crc; /* Used for ensuring integrity in DRAM */ +#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */ + u32 mac[MAC_LENGTH]; /* For 95A0/1 use mac[0] to keep CRC32 value */ + u8 trained_vrefca_a0; + u8 trained_vrefca_a1; + u8 trained_vrefca_b0; + u8 trained_vrefca_b1; + u8 trained_vrefdq_a0; + u8 trained_vrefdq_a1; + u8 trained_vrefdq_b0; + u8 trained_vrefdq_b1; + u8 trained_vrefdqu_a0; + u8 trained_vrefdqu_a1; + u8 trained_vrefdqu_b0; + u8 trained_vrefdqu_b1; + u8 trained_dramdfe_a0; + u8 trained_dramdfe_a1; + u8 trained_dramdfe_b0; + u8 trained_dramdfe_b1; + u8 trained_dramdca_a0; + u8 trained_dramdca_a1; + u8 trained_dramdca_b0; + u8 trained_dramdca_b1; + u16 qb_pll_upll_prog0; + u16 qb_pll_upll_prog1; + u16 qb_pll_upll_prog2; + u16 qb_pll_upll_prog3; + u16 qb_pll_ctrl1; + u16 qb_pll_ctrl4; + u16 qb_pll_ctrl5; + u16 csr[DDRPHY_QB_CSR_SIZE]; + u16 acsm[DDRPHY_QB_ACSM_SIZE]; + u16 pst[DDRPHY_QB_PST_SIZE]; +}; + void ddr_load_train_firmware(enum fw_type type); int ddr_init(struct dram_timing_info *timing_info); int ddr_cfg_phy(struct dram_timing_info *timing_info); diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index 2d084e5227a..fbf2e6a2b01 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -17,15 +17,6 @@ #define ANATOP_BASE_ADDR 0x44480000UL -#ifdef CONFIG_IMX94 -#define WDG3_BASE_ADDR 0x49220000UL -#define WDG4_BASE_ADDR 0x49230000UL -#else -#define WDG3_BASE_ADDR 0x42490000UL -#define WDG4_BASE_ADDR 0x424a0000UL -#endif -#define WDG5_BASE_ADDR 0x424b0000UL - #define GPIO2_BASE_ADDR 0x43810000UL #define GPIO3_BASE_ADDR 0x43820000UL #define GPIO4_BASE_ADDR 0x43840000UL diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index dead7a99a66..d43e54e72aa 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -22,6 +22,11 @@ int low_drive_freq_update(void *blob); enum imx9_soc_voltage_mode soc_target_voltage_mode(void); int get_reset_reason(bool sys, bool lm); +int imx9_uboot_fixup_by_fuse(void *fdt); + +int scmi_get_boot_device_offset(unsigned long *img_off); +int scmi_get_boot_stage(u8 *stage); +u8 scmi_get_imgset_sel(void); #define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode)) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 81af89c631f..9c5f3090bd8 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -82,7 +82,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); void mxs_set_lcdclk(u32 base_addr, u32 freq); -void select_ldb_di_clock_source(enum ldb_di_clock clk); +void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1); void enable_eim_clk(unsigned char enable); int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h new file mode 100644 index 00000000000..f020c94428a --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <[email protected]> + */ +#ifndef _CLOCKS_OMAP4_H_ +#define _CLOCKS_OMAP4_H_ + +#define LDELAY 1000000 + +#include <asm/ti-common/omap_clock.h> + +/* ALTCLKSRC */ +#define ALTCLKSRC_MODE_ACTIVE 1 +#define ALTCLKSRC_MODE_MASK 3 +#define ALTCLKSRC_ENABLE_INT_MASK 4 +#define ALTCLKSRC_ENABLE_EXT_MASK 8 + +/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ +#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K BIT(8) + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK BIT(8) + +/* TWL6030 SMPS */ +#define SMPS_REG_ADDR_VCORE1 0x55 +#define SMPS_REG_ADDR_VCORE2 0x5B +#define SMPS_REG_ADDR_VCORE3 0x61 +/* TWL6032 SMPS */ +#define SMPS_REG_ADDR_SMPS1 0x55 +#define SMPS_REG_ADDR_SMPS2 0x5B +#define SMPS_REG_ADDR_SMPS5 0x49 + +/* PMIC */ +#define SMPS_I2C_SLAVE_ADDR 0x12 + +/* Clock Defines */ +#define V_OSCK 38400000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +struct omap4_scrm_regs { + u32 revision; /* 0x0000 */ + u32 pad00[63]; + u32 clksetuptime; /* 0x0100 */ + u32 pmicsetuptime; /* 0x0104 */ + u32 pad01[2]; + u32 altclksrc; /* 0x0110 */ + u32 pad02[2]; + u32 c2cclkm; /* 0x011c */ + u32 pad03[56]; + u32 extclkreq; /* 0x0200 */ + u32 accclkreq; /* 0x0204 */ + u32 pwrreq; /* 0x0208 */ + u32 pad04[1]; + u32 auxclkreq0; /* 0x0210 */ + u32 auxclkreq1; /* 0x0214 */ + u32 auxclkreq2; /* 0x0218 */ + u32 auxclkreq3; /* 0x021c */ + u32 auxclkreq4; /* 0x0220 */ + u32 auxclkreq5; /* 0x0224 */ + u32 pad05[3]; + u32 c2cclkreq; /* 0x0234 */ + u32 pad06[54]; + u32 auxclk0; /* 0x0310 */ + u32 auxclk1; /* 0x0314 */ + u32 auxclk2; /* 0x0318 */ + u32 auxclk3; /* 0x031c */ + u32 auxclk4; /* 0x0320 */ + u32 auxclk5; /* 0x0324 */ + u32 pad07[54]; + u32 rsttime_reg; /* 0x0400 */ + u32 pad08[6]; + u32 c2crstctrl; /* 0x041c */ + u32 extpwronrstctrl; /* 0x0420 */ + u32 pad09[59]; + u32 extwarmrstst_reg; /* 0x0510 */ + u32 apewarmrstst_reg; /* 0x0514 */ + u32 pad10[1]; + u32 c2cwarmrstst_reg; /* 0x051C */ +}; + +#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h new file mode 100644 index 00000000000..4c9ed455833 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2010 + * Texas Instruments, <www.ti.com> + */ + +#ifndef _CPU_H +#define _CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include <asm/arch/hardware.h> + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct gptimer { + u32 tidr; /* 0x00 r */ + u8 res[0xc]; + u32 tiocp_cfg; /* 0x10 rw */ + u32 tistat; /* 0x14 r */ + u32 tisr; /* 0x18 rw */ + u32 tier; /* 0x1c rw */ + u32 twer; /* 0x20 rw */ + u32 tclr; /* 0x24 rw */ + u32 tcrr; /* 0x28 rw */ + u32 tldr; /* 0x2c rw */ + u32 ttgr; /* 0x30 rw */ + u32 twpc; /* 0x34 r */ + u32 tmar; /* 0x38 rw */ + u32 tcar1; /* 0x3c r */ + u32 tcicr; /* 0x40 rw */ + u32 tcar2; /* 0x44 r */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/* Watchdog */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct watchdog { + u8 res1[0x34]; + u32 wwps; /* 0x34 r */ + u8 res2[0x10]; + u32 wspr; /* 0x48 rw */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* I2C base */ +#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) +#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) +#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) +#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) + +/* MUSB base */ +#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) + +/* OMAP4 GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x0118 +#define OMAP_GPIO_IRQSTATUS2 0x0128 +#define OMAP_GPIO_IRQENABLE2 0x012c +#define OMAP_GPIO_IRQENABLE1 0x011c +#define OMAP_GPIO_WAKE_EN 0x0120 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 +#define OMAP_GPIO_SETIRQENABLE1 0x0164 +#define OMAP_GPIO_CLEARWKUENA 0x0180 +#define OMAP_GPIO_SETWKUENA 0x0184 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4A306000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x07EA + +#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h new file mode 100644 index 00000000000..447c6b1320f --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/ehci.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * OMAP EHCI port support + * Based on LINUX KERNEL + * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com + * Author: Govindraj R <[email protected]> + */ + +#ifndef _OMAP4_EHCI_H_ +#define _OMAP4_EHCI_H_ + +#define OMAP_EHCI_BASE (OMAP44XX_L4_CORE_BASE + 0x64C00) +#define OMAP_UHH_BASE (OMAP44XX_L4_CORE_BASE + 0x64000) +#define OMAP_USBTLL_BASE (OMAP44XX_L4_CORE_BASE + 0x62000) + +/* UHH, TLL and opt clocks */ +#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4A009358UL + +#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK BIT(24) + +/* TLL Register Set */ +#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE BIT(3) +#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP_USBTLL_SYSCONFIG_SOFTRESET BIT(1) +#define OMAP_USBTLL_SYSCONFIG_CACTIVITY BIT(8) +#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 + +#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 +#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE BIT(2) +#define OMAP_UHH_SYSCONFIG_NOIDLE BIT(2) +#define OMAP_UHH_SYSCONFIG_NOSTDBY BIT(4) + +#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ + OMAP_UHH_SYSCONFIG_NOSTDBY) + +#endif /* _OMAP4_EHCI_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/gpio.h b/arch/arm/include/asm/arch-omap4/gpio.h new file mode 100644 index 00000000000..aceb3e227c9 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/gpio.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <[email protected]> + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä <[email protected]> + */ +#ifndef _GPIO_OMAP4_H +#define _GPIO_OMAP4_H + +#include <asm/omap_gpio.h> + +#define OMAP_MAX_GPIO 192 + +#define OMAP44XX_GPIO1_BASE 0x4A310000 +#define OMAP44XX_GPIO2_BASE 0x48055000 +#define OMAP44XX_GPIO3_BASE 0x48057000 +#define OMAP44XX_GPIO4_BASE 0x48059000 +#define OMAP44XX_GPIO5_BASE 0x4805B000 +#define OMAP44XX_GPIO6_BASE 0x4805D000 + +#endif /* _GPIO_OMAP4_H */ diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h new file mode 100644 index 00000000000..67e3dae7bce --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/hardware.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include <asm/arch/omap.h> + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h new file mode 100644 index 00000000000..c8f2f9716f1 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/i2c.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2010 + * Texas Instruments, <www.ti.com> + */ +#ifndef _OMAP4_I2C_H_ +#define _OMAP4_I2C_H_ + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#endif /* _OMAP4_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h new file mode 100644 index 00000000000..3026a002db3 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mem.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * Author + * Mansoor Ahamed <[email protected]> + * + * Initial Code from: + * Richard Woodruff <[email protected]> + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h new file mode 100644 index 00000000000..bda9bc7db82 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +#include <asm/omap_mmc.h> + +/* + * OMAP HSMMC register definitions + */ + +#define OMAP_HSMMC1_BASE 0x4809C000 +#define OMAP_HSMMC2_BASE 0x480B4000 +#define OMAP_HSMMC3_BASE 0x480AD000 + +#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h new file mode 100644 index 00000000000..637d920e0f3 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h @@ -0,0 +1,325 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated + * Richard Woodruff <[email protected]> + * Aneesh V <[email protected]> + * Balaji Krishnamoorthy <[email protected]> + */ +#ifndef _MUX_OMAP4_H_ +#define _MUX_OMAP4_H_ + +#include <asm/types.h> + +struct pad_conf_entry { + u16 offset; + u16 val; +}; + +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD BIT(12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN BIT(10) +#define OFF_OUT (0 << 10) +#define OFF_EN BIT(9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN BIT(8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD BIT(3) +#define EN BIT(3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define GPMC_AD0 0x0040 +#define GPMC_AD1 0x0042 +#define GPMC_AD2 0x0044 +#define GPMC_AD3 0x0046 +#define GPMC_AD4 0x0048 +#define GPMC_AD5 0x004A +#define GPMC_AD6 0x004C +#define GPMC_AD7 0x004E +#define GPMC_AD8 0x0050 +#define GPMC_AD9 0x0052 +#define GPMC_AD10 0x0054 +#define GPMC_AD11 0x0056 +#define GPMC_AD12 0x0058 +#define GPMC_AD13 0x005A +#define GPMC_AD14 0x005C +#define GPMC_AD15 0x005E +#define GPMC_A16 0x0060 +#define GPMC_A17 0x0062 +#define GPMC_A18 0x0064 +#define GPMC_A19 0x0066 +#define GPMC_A20 0x0068 +#define GPMC_A21 0x006A +#define GPMC_A22 0x006C +#define GPMC_A23 0x006E +#define GPMC_A24 0x0070 +#define GPMC_A25 0x0072 +#define GPMC_NCS0 0x0074 +#define GPMC_NCS1 0x0076 +#define GPMC_NCS2 0x0078 +#define GPMC_NCS3 0x007A +#define GPMC_NWP 0x007C +#define GPMC_CLK 0x007E +#define GPMC_NADV_ALE 0x0080 +#define GPMC_NOE 0x0082 +#define GPMC_NWE 0x0084 +#define GPMC_NBE0_CLE 0x0086 +#define GPMC_NBE1 0x0088 +#define GPMC_WAIT0 0x008A +#define GPMC_WAIT1 0x008C +#define C2C_DATA11 0x008E +#define C2C_DATA12 0x0090 +#define C2C_DATA13 0x0092 +#define C2C_DATA14 0x0094 +#define C2C_DATA15 0x0096 +#define HDMI_HPD 0x0098 +#define HDMI_CEC 0x009A +#define HDMI_DDC_SCL 0x009C +#define HDMI_DDC_SDA 0x009E +#define CSI21_DX0 0x00A0 +#define CSI21_DY0 0x00A2 +#define CSI21_DX1 0x00A4 +#define CSI21_DY1 0x00A6 +#define CSI21_DX2 0x00A8 +#define CSI21_DY2 0x00AA +#define CSI21_DX3 0x00AC +#define CSI21_DY3 0x00AE +#define CSI21_DX4 0x00B0 +#define CSI21_DY4 0x00B2 +#define CSI22_DX0 0x00B4 +#define CSI22_DY0 0x00B6 +#define CSI22_DX1 0x00B8 +#define CSI22_DY1 0x00BA +#define CAM_SHUTTER 0x00BC +#define CAM_STROBE 0x00BE +#define CAM_GLOBALRESET 0x00C0 +#define USBB1_ULPITLL_CLK 0x00C2 +#define USBB1_ULPITLL_STP 0x00C4 +#define USBB1_ULPITLL_DIR 0x00C6 +#define USBB1_ULPITLL_NXT 0x00C8 +#define USBB1_ULPITLL_DAT0 0x00CA +#define USBB1_ULPITLL_DAT1 0x00CC +#define USBB1_ULPITLL_DAT2 0x00CE +#define USBB1_ULPITLL_DAT3 0x00D0 +#define USBB1_ULPITLL_DAT4 0x00D2 +#define USBB1_ULPITLL_DAT5 0x00D4 +#define USBB1_ULPITLL_DAT6 0x00D6 +#define USBB1_ULPITLL_DAT7 0x00D8 +#define USBB1_HSIC_DATA 0x00DA +#define USBB1_HSIC_STROBE 0x00DC +#define USBC1_ICUSB_DP 0x00DE +#define USBC1_ICUSB_DM 0x00E0 +#define SDMMC1_CLK 0x00E2 +#define SDMMC1_CMD 0x00E4 +#define SDMMC1_DAT0 0x00E6 +#define SDMMC1_DAT1 0x00E8 +#define SDMMC1_DAT2 0x00EA +#define SDMMC1_DAT3 0x00EC +#define SDMMC1_DAT4 0x00EE +#define SDMMC1_DAT5 0x00F0 +#define SDMMC1_DAT6 0x00F2 +#define SDMMC1_DAT7 0x00F4 +#define ABE_MCBSP2_CLKX 0x00F6 +#define ABE_MCBSP2_DR 0x00F8 +#define ABE_MCBSP2_DX 0x00FA +#define ABE_MCBSP2_FSX 0x00FC +#define ABE_MCBSP1_CLKX 0x00FE +#define ABE_MCBSP1_DR 0x0100 +#define ABE_MCBSP1_DX 0x0102 +#define ABE_MCBSP1_FSX 0x0104 +#define ABE_PDM_UL_DATA 0x0106 +#define ABE_PDM_DL_DATA 0x0108 +#define ABE_PDM_FRAME 0x010A +#define ABE_PDM_LB_CLK 0x010C +#define ABE_CLKS 0x010E +#define ABE_DMIC_CLK1 0x0110 +#define ABE_DMIC_DIN1 0x0112 +#define ABE_DMIC_DIN2 0x0114 +#define ABE_DMIC_DIN3 0x0116 +#define UART2_CTS 0x0118 +#define UART2_RTS 0x011A +#define UART2_RX 0x011C +#define UART2_TX 0x011E +#define HDQ_SIO 0x0120 +#define I2C1_SCL 0x0122 +#define I2C1_SDA 0x0124 +#define I2C2_SCL 0x0126 +#define I2C2_SDA 0x0128 +#define I2C3_SCL 0x012A +#define I2C3_SDA 0x012C +#define I2C4_SCL 0x012E +#define I2C4_SDA 0x0130 +#define MCSPI1_CLK 0x0132 +#define MCSPI1_SOMI 0x0134 +#define MCSPI1_SIMO 0x0136 +#define MCSPI1_CS0 0x0138 +#define MCSPI1_CS1 0x013A +#define MCSPI1_CS2 0x013C +#define MCSPI1_CS3 0x013E +#define UART3_CTS_RCTX 0x0140 +#define UART3_RTS_SD 0x0142 +#define UART3_RX_IRRX 0x0144 +#define UART3_TX_IRTX 0x0146 +#define SDMMC5_CLK 0x0148 +#define SDMMC5_CMD 0x014A +#define SDMMC5_DAT0 0x014C +#define SDMMC5_DAT1 0x014E +#define SDMMC5_DAT2 0x0150 +#define SDMMC5_DAT3 0x0152 +#define MCSPI4_CLK 0x0154 +#define MCSPI4_SIMO 0x0156 +#define MCSPI4_SOMI 0x0158 +#define MCSPI4_CS0 0x015A +#define UART4_RX 0x015C +#define UART4_TX 0x015E +#define USBB2_ULPITLL_CLK 0x0160 +#define USBB2_ULPITLL_STP 0x0162 +#define USBB2_ULPITLL_DIR 0x0164 +#define USBB2_ULPITLL_NXT 0x0166 +#define USBB2_ULPITLL_DAT0 0x0168 +#define USBB2_ULPITLL_DAT1 0x016A +#define USBB2_ULPITLL_DAT2 0x016C +#define USBB2_ULPITLL_DAT3 0x016E +#define USBB2_ULPITLL_DAT4 0x0170 +#define USBB2_ULPITLL_DAT5 0x0172 +#define USBB2_ULPITLL_DAT6 0x0174 +#define USBB2_ULPITLL_DAT7 0x0176 +#define USBB2_HSIC_DATA 0x0178 +#define USBB2_HSIC_STROBE 0x017A +#define UNIPRO_TX0 0x017C +#define UNIPRO_TY0 0x017E +#define UNIPRO_TX1 0x0180 +#define UNIPRO_TY1 0x0182 +#define UNIPRO_TX2 0x0184 +#define UNIPRO_TY2 0x0186 +#define UNIPRO_RX0 0x0188 +#define UNIPRO_RY0 0x018A +#define UNIPRO_RX1 0x018C +#define UNIPRO_RY1 0x018E +#define UNIPRO_RX2 0x0190 +#define UNIPRO_RY2 0x0192 +#define USBA0_OTG_CE 0x0194 +#define USBA0_OTG_DP 0x0196 +#define USBA0_OTG_DM 0x0198 +#define FREF_CLK1_OUT 0x019A +#define FREF_CLK2_OUT 0x019C +#define SYS_NIRQ1 0x019E +#define SYS_NIRQ2 0x01A0 +#define SYS_BOOT0 0x01A2 +#define SYS_BOOT1 0x01A4 +#define SYS_BOOT2 0x01A6 +#define SYS_BOOT3 0x01A8 +#define SYS_BOOT4 0x01AA +#define SYS_BOOT5 0x01AC +#define DPM_EMU0 0x01AE +#define DPM_EMU1 0x01B0 +#define DPM_EMU2 0x01B2 +#define DPM_EMU3 0x01B4 +#define DPM_EMU4 0x01B6 +#define DPM_EMU5 0x01B8 +#define DPM_EMU6 0x01BA +#define DPM_EMU7 0x01BC +#define DPM_EMU8 0x01BE +#define DPM_EMU9 0x01C0 +#define DPM_EMU10 0x01C2 +#define DPM_EMU11 0x01C4 +#define DPM_EMU12 0x01C6 +#define DPM_EMU13 0x01C8 +#define DPM_EMU14 0x01CA +#define DPM_EMU15 0x01CC +#define DPM_EMU16 0x01CE +#define DPM_EMU17 0x01D0 +#define DPM_EMU18 0x01D2 +#define DPM_EMU19 0x01D4 +#define WAKEUPEVENT_0 0x01D8 +#define WAKEUPEVENT_1 0x01DC +#define WAKEUPEVENT_2 0x01E0 +#define WAKEUPEVENT_3 0x01E4 +#define WAKEUPEVENT_4 0x01E8 +#define WAKEUPEVENT_5 0x01EC +#define WAKEUPEVENT_6 0x01F0 + +#define WKUP_REVISION 0x0000 +#define WKUP_HWINFO 0x0004 +#define WKUP_SYSCONFIG 0x0010 +#define PAD0_SIM_IO 0x0040 +#define PAD1_SIM_CLK 0x0042 +#define PAD0_SIM_RESET 0x0044 +#define PAD1_SIM_CD 0x0046 +#define PAD0_SIM_PWRCTRL 0x0048 +#define PAD1_SR_SCL 0x004A +#define PAD0_SR_SDA 0x004C +#define PAD1_FREF_XTAL_IN 0x004E +#define PAD0_FREF_SLICER_IN 0x0050 +#define PAD1_FREF_CLK_IOREQ 0x0052 +#define PAD0_FREF_CLK0_OUT 0x0054 +#define PAD1_FREF_CLK3_REQ 0x0056 +#define PAD0_FREF_CLK3_OUT 0x0058 +#define PAD1_FREF_CLK4_REQ 0x005A +#define PAD0_FREF_CLK4_OUT 0x005C +#define PAD1_SYS_32K 0x005E +#define PAD0_SYS_NRESPWRON 0x0060 +#define PAD1_SYS_NRESWARM 0x0062 +#define PAD0_SYS_PWR_REQ 0x0064 +#define PAD1_SYS_PWRON_RESET 0x0066 +#define PAD0_SYS_BOOT6 0x0068 +#define PAD1_SYS_BOOT7 0x006A +#define PAD0_JTAG_NTRST 0x006C +#define PAD1_JTAG_TCK 0x006D +#define PAD0_JTAG_RTCK 0x0070 +#define PAD1_JTAG_TMS_TMSC 0x0072 +#define PAD0_JTAG_TDI 0x0074 +#define PAD1_JTAG_TDO 0x0076 +#define PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_SPARE_RW 0x0614 +#define CONTROL_SPARE_R 0x0618 +#define CONTROL_SPARE_R_C0 0x061C + +#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A +#endif /* _MUX_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h new file mode 100644 index 00000000000..2912bbc6376 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Authors: + * Aneesh V <[email protected]> + * + * Derived from OMAP3 work by + * Richard Woodruff <[email protected]> + * Syed Mohammed Khasim <[email protected]> + */ + +#ifndef _OMAP4_H_ +#define _OMAP4_H_ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#include <linux/sizes.h> + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP44XX_L4_CORE_BASE 0x4A000000 +#define OMAP44XX_L4_WKUP_BASE 0x4A300000 +#define OMAP44XX_L4_PER_BASE 0x48000000 + +#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 +#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 +#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START +#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END + +/* CONTROL_ID_CODE */ +#define CONTROL_ID_CODE 0x4A002204 + +#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F +#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F +#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F + +/* UART */ +#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) +#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) +#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) + +/* General Purpose Timers */ +#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) +#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) +#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) + +/* Watchdog Timer2 - MPU watchdog */ +#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) + +/* + * Hardware Register Details + */ + +/* Watchdog Timer */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* GP Timer */ +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* Control Module */ +#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) +#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f +#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 +#define CONTROL_EFUSE_2_OVERRIDE 0x99084000 + +/* LPDDR2 IO regs */ +#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C +#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E +#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C +#define LPDDR2IO_GR10_WD_MASK (3 << 17) +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F + +/* CONTROL_EFUSE_2 */ +#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 + +#define MMC1_PWRDNZ BIT(26) +#define MMC1_PBIASLITE_PWRDNZ BIT(22) +#define MMC1_PBIASLITE_VMODE BIT(21) + +#ifndef __ASSEMBLY__ + +struct s32ktimer { + unsigned char res[0x10]; + unsigned int s32k_cr; /* 0x10 */ +}; + +#define DEVICE_TYPE_SHIFT (0x8) +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) + +#endif /* __ASSEMBLY__ */ + +/* + * Non-secure SRAM Addresses + * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE + * at 0x40304000(EMU base) so that our code works for both EMU and GP + */ +#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ +#define NON_SECURE_SRAM_IMG_END 0x4030C000 +#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_ROM_VECT_BASE 0x4030D000 + +/* ABB settings */ +#define OMAP_ABB_SETTLING_TIME 50 +#define OMAP_ABB_CLOCK_CYCLES 16 + +/* ABB tranxdone mask */ +#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) + +#define OMAP44XX_SAR_RAM_BASE 0x4a326000 +#define OMAP_REBOOT_REASON_OFFSET 0xA0C +#define OMAP_REBOOT_REASON_SIZE 0x0F + +/* Boot parameters */ +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + unsigned int boot_message; + unsigned int boot_device_descriptor; + unsigned char boot_device; + unsigned char reset_reason; + unsigned char ch_flags; +}; + +int omap_reboot_mode(char *mode, unsigned int length); +int omap_reboot_mode_clear(void); +int omap_reboot_mode_store(char *mode); +#endif + +#endif diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h new file mode 100644 index 00000000000..d24944af0ae --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2012 + * Texas Instruments, <www.ti.com> + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_ARCH_SPL_H_ + +#define BOOT_DEVICE_NONE 0x00 +#define BOOT_DEVICE_XIP 0x01 +#define BOOT_DEVICE_XIPWAIT 0x02 +#define BOOT_DEVICE_NAND 0x03 +#define BOOT_DEVICE_ONENAND 0x04 +#define BOOT_DEVICE_MMC1 0x05 +#define BOOT_DEVICE_MMC2 0x06 +#define BOOT_DEVICE_MMC2_2 0x07 +#define BOOT_DEVICE_UART 0x43 +#define BOOT_DEVICE_USB 0x45 + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 +#endif diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h new file mode 100644 index 00000000000..c6e6f6ca480 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include <asm/arch/omap.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <asm/omap_common.h> +#include <linux/mtd/omap_gpmc.h> +#include <asm/arch/mux_omap4.h> +#include <asm/ti-common/sys_proto.h> + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; +extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; +extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2; +extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2; +extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2; +#else +extern const struct lpddr2_device_details elpida_2G_S4_details; +extern const struct lpddr2_device_details elpida_4G_S4_details; +#endif + +#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +extern const struct lpddr2_device_timings jedec_default_timings; +#else +extern const struct lpddr2_device_timings elpida_2G_S4_timings; +#endif + +struct omap_sysinfo { + char *board_string; +}; + +extern const struct omap_sysinfo sysinfo; + +void gpmc_init(void); +void watchdog_init(void); +u32 get_device_type(void); +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs(void); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, + u32 bound); +void sdelay(unsigned long loops); +void setup_early_clocks(void); +void prcm_init(void); +void do_board_detect(void); +void bypass_dpll(u32 const base); +void freq_update_core(void); +u32 get_sys_clk_freq(void); +u32 omap4_ddr_clk(void); +void cancel_out(u32 *num, u32 *den, u32 den_limit); +void sdram_init(void); +u32 omap_sdram_size(void); +u32 cortex_rev(void); +void save_omap_boot_params(void); +void init_omap_revision(void); +void do_io_settings(void); +void sri2c_init(void); +int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); +void force_emif_self_refresh(void); +void setup_warmreset_time(void); + +#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 + +#endif diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index eeb3c6f2a6c..02dcc0e4356 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -9,6 +9,8 @@ #ifndef _CLOCKS_OMAP5_H_ #define _CLOCKS_OMAP5_H_ +#include <asm/ti-common/omap_clock.h> + /* * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per * loop, allow for a minimum of 2 ms wait (in reality the wait will be @@ -19,7 +21,6 @@ /* CM_DLL_CTRL */ #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) -#define CM_DLL_CTRL_NO_OVERRIDE 0 /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 @@ -32,20 +33,6 @@ #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_FAST_RELOCK_BYPASS 6 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 /* SGX */ #define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) @@ -54,24 +41,6 @@ /* CM_CLKSEL_DPLL */ #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F -#define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) - -/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 - -/* CM_CLKSEL_CORE */ -#define CLKSEL_CORE_SHIFT 0 -#define CLKSEL_L3_SHIFT 4 -#define CLKSEL_L4_SHIFT 8 - -#define CLKSEL_CORE_X2_DIV_1 0 -#define CLKSEL_L3_CORE_DIV_2 1 -#define CLKSEL_L4_L3_DIV_2 1 /* CM_ABE_PLL_REF_CLKSEL */ #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 @@ -91,57 +60,12 @@ #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 -/* CM_SHADOW_FREQ_CONFIG1 */ -#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 -#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 -#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 - -#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 -#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) - -#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 -#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) - -/*CM_<clock_domain>__CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 -#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - -/* CM_<clock_domain>_<module>_CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) -#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) - /* CM_IPU1_IPU1_CLKCTRL CLKSEL MASK */ #define IPU1_CLKCTRL_CLKSEL_MASK BIT(24) /* CM_L3INIT_SATA_CLKCTRL */ #define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) -/* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) - /* CM_CAM_ISS_CLKCTRL */ #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) @@ -181,12 +105,6 @@ /* CM_L3INIT_OCP2SCP1_CLKCTRL */ #define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) -/* CM_MPU_MPU_CLKCTRL */ -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) - /* CM_WKUPAON_SCRM_CLKCTRL */ #define OPTFCLKEN_SCRM_PER_SHIFT 9 #define OPTFCLKEN_SCRM_PER_MASK (1 << 9) @@ -201,12 +119,6 @@ #define RSTTIME1_SHIFT 0 #define RSTTIME1_MASK (0x3ff << 0) -/* Clock frequencies */ -#define OMAP_SYS_CLK_IND_38_4_MHZ 6 - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 - /* CTRL_CORE_SRCOMP_NORTH_SIDE */ #define USB2PHY_DISCHGDET (1 << 29) #define USB2PHY_AUTORESUME_EN (1 << 30) @@ -402,16 +314,4 @@ /* CKO buffer control */ #define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) -/* AUXCLKx reg fields */ -#define AUXCLK_ENABLE_MASK (1 << 8) -#define AUXCLK_SRCSELECT_SHIFT 1 -#define AUXCLK_SRCSELECT_MASK (3 << 1) -#define AUXCLK_CLKDIV_SHIFT 16 -#define AUXCLK_CLKDIV_MASK (0xF << 16) - -#define AUXCLK_SRCSELECT_SYS_CLK 0 -#define AUXCLK_SRCSELECT_CORE_DPLL 1 -#define AUXCLK_SRCSELECT_PER_DPLL 2 -#define AUXCLK_SRCSELECT_ALTERNATE 3 - #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index b15938c021d..f9ecb6858f0 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -51,6 +51,7 @@ enum { BROM_BOOTSOURCE_SPINOR = 3, BROM_BOOTSOURCE_SPINAND = 4, BROM_BOOTSOURCE_SD = 5, + BROM_BOOTSOURCE_UFS = 7, BROM_BOOTSOURCE_I2C = 8, BROM_BOOTSOURCE_SPI = 9, BROM_BOOTSOURCE_USB = 10, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h index c51750beff2..fb77fbd7307 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h @@ -222,6 +222,20 @@ enum { REF_CLK0_OUT_PLL_DIV_SHIFT = 0, REF_CLK0_OUT_PLL_DIV_MASK = 0xff << REF_CLK0_OUT_PLL_DIV_SHIFT, + /* CRU_CLK_SEL36_CON */ + CLK_REFCLKO25M_GMAC0_DIV_SHIFT = 0, + CLK_REFCLKO25M_GMAC0_DIV_MASK = 0x7f << CLK_REFCLKO25M_GMAC0_DIV_SHIFT, + CLK_REFCLKO25M_GMAC0_SEL_SHIFT = 7, + CLK_REFCLKO25M_GMAC0_SEL_MASK = 1 << CLK_REFCLKO25M_GMAC0_SEL_SHIFT, + CLK_REFCLKO25M_GMAC0_SEL_GPLL = 0, + CLK_REFCLKO25M_GMAC0_SEL_CPLL = 1, + CLK_REFCLKO25M_GMAC1_DIV_SHIFT = 8, + CLK_REFCLKO25M_GMAC1_DIV_MASK = 0x7f << CLK_REFCLKO25M_GMAC1_DIV_SHIFT, + CLK_REFCLKO25M_GMAC1_SEL_SHIFT = 15, + CLK_REFCLKO25M_GMAC1_SEL_MASK = 1 << CLK_REFCLKO25M_GMAC1_SEL_SHIFT, + CLK_REFCLKO25M_GMAC1_SEL_GPLL = 0, + CLK_REFCLKO25M_GMAC1_SEL_CPLL = 1, + /* CRU_CLK_SEL55_CON */ ACLK_BUS_ROOT_SEL_SHIFT = 9, ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT, diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 8aa5f9721c4..8e6989810b0 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -187,6 +187,13 @@ void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv); */ void dump_pagetable(u64 ttbr, u64 tcr); +/** + * tlb_debug_lookup() - Perform a software TLB walk printing each stage + * + * @addr: the address to look-up in the TLB. + */ +void tlb_debug_lookup(u64 addr); + struct mm_region { u64 virt; u64 phys; @@ -222,6 +229,11 @@ u64 get_tcr(u64 *pips, u64 *pva_bits); * mmu_setup() - Sets up the mmu page tables as per mem_map */ void mmu_setup(void); + +/** + * mmu_enable() - Enable the MMU by setting 'M' bit in SCTLR register + */ +void mmu_enable(void); #endif #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 650783ae732..eba7bae9351 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,3 +1,5 @@ +#include <linux/types.h> + #ifdef CONFIG_GPIO_EXTRA_HEADER #include <asm/arch/gpio.h> #endif diff --git a/arch/arm/include/asm/mach-imx/ahab.h b/arch/arm/include/asm/mach-imx/ahab.h index 4884f056251..dad170cee47 100644 --- a/arch/arm/include/asm/mach-imx/ahab.h +++ b/arch/arm/include/asm/mach-imx/ahab.h @@ -8,7 +8,7 @@ #include <imx_container.h> -int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length); +void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length); int ahab_auth_release(void); int ahab_verify_cntr_image(struct boot_img_t *img, int image_index); diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 04e7f20a2a6..8d779d6ae1b 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -30,6 +30,7 @@ #define ELE_START_RNG (0xA3) #define ELE_CMD_DERIVE_KEY (0xA9) #define ELE_GENERATE_DEK_BLOB (0xAF) +#define ELE_V2X_GET_STATE_REQ (0xB2) #define ELE_ENABLE_PATCH_REQ (0xC3) #define ELE_RELEASE_RDC_REQ (0xC4) #define ELE_GET_FW_STATUS_REQ (0xC5) @@ -141,6 +142,12 @@ struct ele_get_info_data { u32 reserved[8]; }; +struct v2x_get_state { + u8 v2x_state; + u8 v2x_power_state; + u32 v2x_err_code; +}; + int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response); int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response); int ele_release_container(u32 *response); @@ -166,4 +173,5 @@ int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); int ele_set_gmid(u32 *response); int ele_volt_change_start_req(void); int ele_volt_change_finish_req(void); +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response); #endif diff --git a/arch/arm/include/asm/mach-imx/qb.h b/arch/arm/include/asm/mach-imx/qb.h new file mode 100644 index 00000000000..a874c9c5e36 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/qb.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2026 NXP + */ + +#ifndef __IMX_QB_H__ +#define __IMX_QB_H__ + +#include <stdbool.h> + +bool imx_qb_check(void); +int imx_qb(const char *ifname, const char *dev, bool save); +void spl_imx_qb_save(void); + +#endif diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index ab573413128..d25c08f8fe7 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -74,9 +74,12 @@ struct bd_info; #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD)) #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS)) #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ - is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL)) + is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL) || \ + is_cpu_type(MXC_CPU_IMX8MP5) || is_cpu_type(MXC_CPU_IMX8MPD2)) #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) +#define is_imx8mpd2() (is_cpu_type(MXC_CPU_IMX8MPD2)) #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) +#define is_imx8mp5() (is_cpu_type(MXC_CPU_IMX8MP5)) #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) #define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL)) diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 2713b1d2c55..e73df782d2c 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -5050,4 +5050,5 @@ #define MACH_TYPE_NASM25 5112 #define MACH_TYPE_TOMATO 5113 #define MACH_TYPE_OMAP3_MRC3D 5114 +#define MACH_TYPE_OMAP4_VAR_SOM 5115 #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 5e74f41dd97..9945eeb66b8 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -490,7 +490,7 @@ struct omap_sys_ctrl_regs { u32 ctrl_core_sma_sw_1; }; -#if defined(CONFIG_OMAP54XX) +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) struct dpll_params { u32 m; u32 n; @@ -523,7 +523,7 @@ struct dpll_regs { u32 cm_div_h23_dpll; u32 cm_div_h24_dpll; }; -#endif /* CONFIG_OMAP54XX */ +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ struct dplls { const struct dpll_params *mpu; @@ -547,7 +547,7 @@ struct pmic_data { int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); }; -#if defined(CONFIG_OMAP54XX) +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) enum { OPP_LOW, OPP_NOM, @@ -593,7 +593,7 @@ struct vcores_data { struct volts eve; struct volts iva; }; -#endif /* CONFIG_OMAP54XX */ +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; @@ -626,7 +626,7 @@ const struct dpll_params *get_iva_dpll_params(struct dplls const *); const struct dpll_params *get_usb_dpll_params(struct dplls const *); const struct dpll_params *get_abe_dpll_params(struct dplls const *); -#if defined(CONFIG_OMAP54XX) +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) void do_enable_clocks(u32 const *clk_domains, u32 const *clk_modules_hw_auto, u32 const *clk_modules_explicit_en, @@ -635,7 +635,7 @@ void do_enable_clocks(u32 const *clk_domains, void do_disable_clocks(u32 const *clk_domains, u32 const *clk_modules_disable, u8 wait_for_disable); -#endif /* CONFIG_OMAP54XX */ +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ void do_enable_ipu_clocks(u32 const *clk_domains, u32 const *clk_modules_hw_auto, @@ -653,9 +653,9 @@ void enable_basic_uboot_clocks(void); void enable_usb_clocks(int index); void disable_usb_clocks(int index); -#if defined(CONFIG_OMAP54XX) +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) void scale_vcores(struct vcores_data const *); -#endif /* CONFIG_OMAP54XX */ +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ int get_voltrail_opp(int rail_offset); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 9e3ad57073d..5ed6833c155 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -342,6 +342,7 @@ void smc_call(struct pt_regs *args); void __noreturn psci_system_reset(void); void __noreturn psci_system_reset2(u32 reset_level, u32 cookie); void __noreturn psci_system_off(void); +int psci_features(u32 psci_func_id); #ifdef CONFIG_ARMV8_PSCI extern char __secure_start[]; diff --git a/arch/arm/include/asm/ti-common/omap_clock.h b/arch/arm/include/asm/ti-common/omap_clock.h new file mode 100644 index 00000000000..4a37b0bc8c3 --- /dev/null +++ b/arch/arm/include/asm/ti-common/omap_clock.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _OMAP_CLOCK_H_ +#define _OMAP_CLOCK_H_ + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_NO_OVERRIDE 0 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DCC_EN_SHIFT 22 +#define CM_CLKSEL_DCC_EN_MASK BIT(22) + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/*CM_<clock_domain>__CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/* CM_<clock_domain>_<module>_CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK BIT(8) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK BIT(24) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK BIT(24) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) + +/* Clock frequencies */ +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 + +/* AUXCLKx reg fields */ +#define AUXCLK_ENABLE_MASK BIT(8) +#define AUXCLK_SRCSELECT_SHIFT 1 +#define AUXCLK_SRCSELECT_MASK (3 << 1) +#define AUXCLK_CLKDIV_SHIFT 16 +#define AUXCLK_CLKDIV_MASK (0xF << 16) +#define AUXCLK_CLKDIV_2 1 + +#define AUXCLK_SRCSELECT_SYS_CLK 0 +#define AUXCLK_SRCSELECT_CORE_DPLL 1 +#define AUXCLK_SRCSELECT_PER_DPLL 2 +#define AUXCLK_SRCSELECT_ALTERNATE 3 + +/* CM_MPU_MPU_CLKCTRL */ +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK BIT(26) + +#endif /* _OMAP_CLOCK_H_ */ diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 2671f9a0ebf..a82ceeaf22f 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -35,14 +35,13 @@ int arch_fixup_fdt(void *blob) { __maybe_unused int ret = 0; #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT) - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; #ifdef CONFIG_ARMV7_NONSEC ret = armv7_apply_memory_carveout(&start[bank], &size[bank]); if (ret) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 1cde655bc80..9a115cc6078 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -64,8 +64,8 @@ static void setup_memory_tags(struct bd_info *bd) params->hdr.tag = ATAG_MEM; params->hdr.size = tag_size (tag_mem32); - params->u.mem.start = bd->bi_dram[i].start; - params->u.mem.size = bd->bi_dram[i].size; + params->u.mem.start = gd->dram[i].start; + params->u.mem.size = gd->dram[i].size; params = tag_next (params); } diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 947012f2996..28bb6fd36c8 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -94,17 +94,16 @@ void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys, __weak void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - /* bd->bi_dram is available only after relocation */ + /* gd->dram is available only after relocation */ if ((gd->flags & GD_FLG_RELOC) == 0) return; debug("%s: bank: %d\n", __func__, bank); - for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + - (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); + for (i = gd->dram[bank].start >> MMU_SECTION_SHIFT; + i < (gd->dram[bank].start >> MMU_SECTION_SHIFT) + + (gd->dram[bank].size >> MMU_SECTION_SHIFT); i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/lib/gic-v2.c b/arch/arm/lib/gic-v2.c index b70434a45d4..378bdb54c89 100644 --- a/arch/arm/lib/gic-v2.c +++ b/arch/arm/lib/gic-v2.c @@ -38,7 +38,7 @@ static int acpi_gicv2_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -static struct acpi_ops gic_v2_acpi_ops = { +static const struct acpi_ops gic_v2_acpi_ops = { .fill_madt = acpi_gicv2_fill_madt, }; #endif diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index 34f05e94672..064b93b2aa1 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -81,7 +81,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist) int i; u64 redist_lpi_base; u64 pend_base; - ulong pend_tab_total_sz = num_redist * LPI_PENDBASE_SZ; + ulong pend_tab_total_sz; void *pend_tab_va; if (gic_v3_its_get_gic_addr(&priv)) @@ -133,6 +133,7 @@ int gic_lpi_tables_init(u64 base, u32 num_redist) } redist_lpi_base = base + LPI_PROPBASE_SZ; + pend_tab_total_sz = num_redist * LPI_PENDBASE_SZ; pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz, MAP_NOCACHE); memset(pend_tab_va, 0, pend_tab_total_sz); @@ -196,7 +197,7 @@ static int acpi_gicv3_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -struct acpi_ops gic_v3_acpi_ops = { +static const struct acpi_ops gic_v3_acpi_ops = { .fill_madt = acpi_gicv3_fill_madt, }; #endif diff --git a/arch/arm/lib/image.c b/arch/arm/lib/image.c index 1f672eee2c8..2268661de93 100644 --- a/arch/arm/lib/image.c +++ b/arch/arm/lib/image.c @@ -69,7 +69,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, if (!force_reloc && (le64_to_cpu(ih->flags) & BIT(3))) dst = image - text_offset; else - dst = gd->bd->bi_dram[0].start; + dst = gd->dram[0].start; *relocated_addr = ALIGN(dst, SZ_2M) + text_offset; diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c index ab32706a79d..f33527ca129 100644 --- a/arch/arm/mach-airoha/an7581/init.c +++ b/arch/arm/mach-airoha/an7581/init.c @@ -23,12 +23,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = gd->ram_base + SZ_2G; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; diff --git a/arch/arm/mach-apple/Kconfig b/arch/arm/mach-apple/Kconfig index 294690ec0e8..fdc8c32152f 100644 --- a/arch/arm/mach-apple/Kconfig +++ b/arch/arm/mach-apple/Kconfig @@ -3,12 +3,22 @@ if ARCH_APPLE config TEXT_BASE default 0x00000000 -config SYS_CONFIG_NAME +config SYS_SOC default "apple" -config SYS_SOC +config SYS_VENDOR default "apple" +config SYS_BOARD + string "Board name" + default "mac" + help + This option contains information about board name. + Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will + be used. + Apple silicon based devices are expected to use the generic board name + "mac". + config SYS_MALLOC_LEN default 0x4000000 diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 4cd8979bdc2..e74a5a76919 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -673,6 +673,83 @@ static struct mm_region t6022_mem_map[] = { } }; +/* Apple M3 */ + +static struct mm_region t8122_mem_map[] = { + { + /* I/O */ + .virt = 0x200000000, + .phys = 0x200000000, + .size = 4UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* NVMe */ + .virt = 0x300000000, + .phys = 0x300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x580000000, + .phys = 0x580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5a0000000, + .phys = 0x5a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5c0000000, + .phys = 0x5c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC0 */ + .virt = 0x700000000, + .phys = 0x700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O ATC1 */ + .virt = 0xb00000000, + .phys = 0xb00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x10000000000, + .phys = 0x10000000000, + .size = 8UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + struct mm_region *mem_map; int board_init(void) @@ -720,6 +797,8 @@ void build_mem_map(void) mem_map = t6020_mem_map; else if (of_machine_is_compatible("apple,t6022")) mem_map = t6022_mem_map; + else if (of_machine_is_compatible("apple,t8122")) + mem_map = t8122_mem_map; else panic("Unsupported SoC\n"); @@ -728,8 +807,8 @@ void build_mem_map(void) ; /* Align RAM mapping to page boundaries */ - base = gd->bd->bi_dram[0].start; - size = gd->bd->bi_dram[0].size; + base = gd->dram[0].start; + size = gd->dram[0].size; size += (base - ALIGN_DOWN(base, SZ_4K)); base = ALIGN_DOWN(base, SZ_4K); size = ALIGN(size, SZ_4K); diff --git a/arch/arm/mach-apple/rtkit_helper.c b/arch/arm/mach-apple/rtkit_helper.c index b7d60e15700..cbdc204f141 100644 --- a/arch/arm/mach-apple/rtkit_helper.c +++ b/arch/arm/mach-apple/rtkit_helper.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <asm/arch/rtkit.h> #include <linux/iopoll.h> +#include <linux/sizes.h> /* ASC registers */ #define REG_CPU_CTRL 0x0044 diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index c88b1e59366..f4b038ebd9e 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -36,9 +36,20 @@ config ASPEED_AST2600 It is used as Board Management Controller on many server boards, which is enabled by support of LPC and eSPI peripherals. +config ASPEED_AST2700 + bool "Support Aspeed AST2700 SoC" + select ARM64 + select SYS_ARCH_TIMER + help + Support for the Aspeed AST2700, an arm64 (Cortex-A35) Baseboard + Management Controller (BMC) SoC. This is the 8th-generation BMC + SoC family from Aspeed and features a dual-die architecture + (CPU die + I/O die) connected via an internal coherent bus. + endchoice source "arch/arm/mach-aspeed/ast2500/Kconfig" source "arch/arm/mach-aspeed/ast2600/Kconfig" +source "arch/arm/mach-aspeed/ast2700/Kconfig" endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile index 42599c125b8..d0b4eb74c6c 100644 --- a/arch/arm/mach-aspeed/Makefile +++ b/arch/arm/mach-aspeed/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o obj-$(CONFIG_ASPEED_AST2500) += ast2500/ obj-$(CONFIG_ASPEED_AST2600) += ast2600/ +obj-$(CONFIG_ASPEED_AST2700) += ast2700/ diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds index 303ace2f61c..894eda1db77 100644 --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -42,6 +42,7 @@ SECTIONS . = ALIGN(4); __u_boot_list : { KEEP(*(SORT(__u_boot_list*))); + . = ALIGN(8); } > .nor . = ALIGN(4); @@ -49,7 +50,6 @@ SECTIONS __binman_sym_start = .; KEEP(*(SORT(.binman_sym*))); __binman_sym_end = .; - . = ALIGN(8); } > .nor /* diff --git a/arch/arm/mach-aspeed/ast2700/Kconfig b/arch/arm/mach-aspeed/ast2700/Kconfig new file mode 100644 index 00000000000..3dd68db76db --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/Kconfig @@ -0,0 +1,36 @@ +if ASPEED_AST2700 + +config SYS_CPU + default "armv8" + +config SPI_KERNEL_FIT_ADDR + hex "SPI address of kernel FIT image" + default 0x100420000 + help + Address in the SPI flash where the kernel FIT image is stored. + Used by the bootspi command to load and boot the kernel image + from the SPI flash on AST2700 platforms. + +choice + prompt "AST2700 board select" + depends on ASPEED_AST2700 + default TARGET_EVB_AST2700 + help + Select the AST2700 board model. Each board option configures + the board-specific Kconfig, defaults and devicetree. + +config TARGET_EVB_AST2700 + bool "EVB-AST2700" + depends on ASPEED_AST2700 + select ARCH_MISC_INIT + help + EVB-AST2700 is Aspeed evaluation board for AST2700A0 chip. + It has 512M of RAM, 32M of SPI flash, two Ethernet ports, + 4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot, + 20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs. + +endchoice + +source "board/aspeed/evb_ast2700/Kconfig" + +endif diff --git a/arch/arm/mach-aspeed/ast2700/Makefile b/arch/arm/mach-aspeed/ast2700/Makefile new file mode 100644 index 00000000000..38bd52f3d5d --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel_init.o board_common.o arm64-mmu.o platform.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o diff --git a/arch/arm/mach-aspeed/ast2700/arm64-mmu.c b/arch/arm/mach-aspeed/ast2700/arm64-mmu.c new file mode 100644 index 00000000000..a068e6ede97 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/arm64-mmu.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <dm.h> +#include <asm/armv8/mmu.h> + +static struct mm_region aspeed2700_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, + { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x2C0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE, + }, + { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = aspeed2700_mem_map; + +u64 get_page_table_size(void) +{ + return 0x80000; +} diff --git a/arch/arm/mach-aspeed/ast2700/board_common.c b/arch/arm/mach-aspeed/ast2700/board_common.c new file mode 100644 index 00000000000..6d2160bbca4 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/board_common.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <dm.h> +#include <ram.h> +#include <init.h> +#include <timer.h> +#include <asm/io.h> +#include <asm/arch/timer.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <dm/uclass.h> +#include <asm/arch-aspeed/scu_ast2700.h> + +#define AHBC_GROUP(x) (0x40 * (x)) +#define AHBC_HREADY_WAIT_CNT_REG 0x34 +#define AHBC_HREADY_WAIT_CNT_MAX 0x3f + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + struct udevice *dev; + struct ram_info ram; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("cannot get DRAM driver\n"); + debug("cannot get DRAM driver\n"); + return ret; + } + + ret = ram_get_info(dev, &ram); + if (ret) { + debug("cannot get DRAM information\n"); + return ret; + } + + gd->ram_size = ram.size; + + return 0; +} + +static void ahbc_init(void) +{ + u32 reg_val; + int i; + + reg_val = readl(ASPEED_CPU_REVISION_ID); + if (FIELD_GET(SCU_CPU_REVISION_ID_HW, reg_val)) + return; + + /* CPU-die AHBC timeout counter */ + for (i = 0; i < 4; i++) + writel(AHBC_HREADY_WAIT_CNT_MAX, + (void *)ASPEED_CPU_AHBC_BASE + AHBC_GROUP(i) + AHBC_HREADY_WAIT_CNT_REG); + + /* IO-die AHBC timeout counter */ + for (i = 0; i < 8; i++) + writel(AHBC_HREADY_WAIT_CNT_MAX, + (void *)ASPEED_IO_AHBC_BASE + AHBC_GROUP(i) + AHBC_HREADY_WAIT_CNT_REG); +} + +int board_init(void) +{ + struct udevice *dev; + int i = 0; + int ret; + + ahbc_init(); + + /* + * Loop over all MISC uclass drivers to call the comphy code + * and init all CP110 devices enabled in the DT + */ + while (1) { + /* Call the comphy code via the MISC uclass driver */ + ret = uclass_get_device(UCLASS_MISC, i++, &dev); + + /* We're done, once no further CP110 device is found */ + if (ret) + break; + } + + return 0; +} diff --git a/arch/arm/mach-aspeed/ast2700/cpu-info.c b/arch/arm/mach-aspeed/ast2700/cpu-info.c new file mode 100644 index 00000000000..7f29c4d8c33 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/cpu-info.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + * Ryan Chen <[email protected]> + */ + +#include <command.h> +#include <asm/io.h> +#include <asm/arch/platform.h> +#include <asm/arch/scu_ast2700.h> + +/* SoC mapping Table */ +#define SOC_ID(str, rev) { .name = str, .rev_id = rev, } + +struct soc_id { + const char *name; + u64 rev_id; +}; + +static struct soc_id soc_map_table[] = { + SOC_ID("AST2750-A0", 0x0600000306000003), + SOC_ID("AST2700-A0", 0x0600010306000103), + SOC_ID("AST2720-A0", 0x0600020306000203), + SOC_ID("AST2750-A1", 0x0601000306010003), + SOC_ID("AST2700-A1", 0x0601010306010103), + SOC_ID("AST2720-A1", 0x0601020306010203), + SOC_ID("AST2750-A2", 0x0602000306020003), + SOC_ID("AST2700-A2", 0x0602010306020103), + SOC_ID("AST2720-A2", 0x0602020306020203), +}; + +void ast2700_print_soc_id(void) +{ + int i; + u64 rev_id; + + rev_id = readl(ASPEED_CPU_REVISION_ID); + rev_id = ((u64)readl(ASPEED_IO_REVISION_ID) << 32) | rev_id; + + for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) { + if (rev_id == soc_map_table[i].rev_id) + break; + } + if (i == ARRAY_SIZE(soc_map_table)) + printf("Unknown-SOC: %llx\n", rev_id); + else + printf("SOC: %4s\n", soc_map_table[i].name); +} + +#define SYS_DRAM_ECCRST BIT(3) +#define SYS_ABRRST BIT(2) +#define SYS_EXTRST BIT(1) +#define SYS_SRST BIT(0) + +#define WDT_RST_BIT_MASK(s) (GENMASK(3, 0) << (s)) +#define BIT_WDT_FULL(s) (BIT(0) << (s)) +#define BIT_WDT_ARM(s) (BIT(1) << (s)) +#define BIT_WDT_SOC(s) (BIT(2) << (s)) +#define BIT_WDT_SW(s) (BIT(3) << (s)) + +void ast2700_print_wdtrst_info(void) +{ + u32 wdt_rst = readl(ASPEED_IO_RESET_LOG4); + int i; + + for (i = 0; i < 8; i++) { + if (wdt_rst & WDT_RST_BIT_MASK(i * 4)) { + printf("RST: WDT%d ", i); + if (wdt_rst & BIT_WDT_SOC(i * 4)) { + printf("SOC "); + writel(BIT_WDT_SOC(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_FULL(i * 4)) { + printf("FULL "); + writel(BIT_WDT_FULL(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_ARM(i * 4)) { + printf("ARM "); + writel(BIT_WDT_ARM(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_SW(i * 4)) { + printf("SW "); + writel(BIT_WDT_SW(i * 4), ASPEED_IO_RESET_LOG4); + } + printf("\n"); + } + } +} + +#define SYS_EXTRST BIT(1) +#define SYS_SRST BIT(0) + +void ast2700_print_sysrst_info(void) +{ + u32 sys_rst = readl(ASPEED_CPU_RESET_LOG1); + + if (sys_rst & SYS_SRST) { + printf("RST: Power On\n"); + writel(SYS_SRST, ASPEED_CPU_RESET_LOG1); + } else if (sys_rst & SYS_EXTRST) { + printf("RST: EXTRST\n"); + writel(SYS_EXTRST, ASPEED_CPU_RESET_LOG1); + } else { + ast2700_print_wdtrst_info(); + } +} + +int print_cpuinfo(void) +{ + ast2700_print_soc_id(); + ast2700_print_sysrst_info(); + + return 0; +} diff --git a/arch/arm/mach-aspeed/ast2700/lowlevel_init.S b/arch/arm/mach-aspeed/ast2700/lowlevel_init.S new file mode 100644 index 00000000000..9b78fed0b26 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/lowlevel_init.S @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) ASPEED Technology Inc. + */ +#include <config.h> +#include <linux/linkage.h> + +/* + * SMP mailbox + * +-----------------------+ 0x40 + * | | + * | mailbox insn. for | + * | cpuN GO sign polling | + * | | + * +-----------------------+ 0x20 + * | cpu3 entrypoint | + * +-----------------------+ 0x18 + * | cpu2 entrypoint | + * +-----------------------+ 0x10 + * | cpu1 entrypoint | + * +-----------------------+ 0x8 + * | reserved | + * +-----------------------+ 0x4 + * | mailbox ready | + * +-----------------------+ SCU_CPU + 0x780 + */ + +#define SCU_CPU_BASE 0x12c02000 +#define SCU_CPU_SMP_READY (SCU_CPU_BASE + 0x780) +#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) +#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) +#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) +#define SCU_CPU_SMP_POLLINSN (SCU_CPU_BASE + 0x7a0) + +ENTRY(lowlevel_init) + /* backup LR */ + mov x29, lr + +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + /* reset SMP mailbox ASAP */ + ldr x0, =SCU_CPU_SMP_READY + str wzr, [x0] + + /* + * get cpu core id + * + * ast2700 has 1-cluster, 4-cores CPU topology. + * Affinity level 0 in MPIDR is sufficient. + */ + mrs x4, mpidr_el1 + ands x4, x4, #0xff + + /* cpu0 is the primary core to setup SMP mailbox */ + beq do_primary_core_setup + + /* hold cpuN until mailbox is ready */ + ldr x0, =SCU_CPU_SMP_READY + movz w1, #0xcafe + movk w1, #0xbabe, lsl #16 + +poll_mailbox_ready: + wfe + ldr w2, [x0] + cmp w1, w2 + bne poll_mailbox_ready + + /* + * parameters for relocated SMP go polling insn. + * x4 = cpu id + * x5 = SCU_CPU_SMP_EPx + */ + add x5, x0, x4, lsl #3 + + /* jump to the polling loop in SMP mailbox, no return */ + ldr x0, =SCU_CPU_SMP_POLLINSN + br x0 + +do_primary_core_setup: + /* relocate mailbox insn. for cpuN to poll for SMP go signal */ + adr x0, smp_mbox_insn + adr x1, smp_mbox_insn_end + ldr x2, =SCU_CPU_SMP_POLLINSN + +relocate_smp_mbox_insn: + ldr w3, [x0], #0x4 + str w3, [x2], #0x4 + cmp x0, x1 + bne relocate_smp_mbox_insn + + /* reset cpuN entrypoints */ + ldr x0, =SCU_CPU_SMP_EP1 + str xzr, [x0], #8 + str xzr, [x0], #8 + str xzr, [x0] + + /* notify cpuN that SMP mailbox is ready */ + movz w0, #0xcafe + movk w0, #0xbabe, lsl #16 + ldr x1, =SCU_CPU_SMP_READY + str w0, [x1] + + sev +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ + + /* back to arch calling code */ + mov lr, x29 + ret +ENDPROC(lowlevel_init) + +/* + * insn. inside mailbox to poll SMP go signal. + * + * Note that this code will be relocated, any absolute + * addressing should NOT be used. + */ +smp_mbox_insn: + /* + * x4 = cpu id + * x5 = SCU_CPU_SMP_EPx + */ +poll_smp_mbox_go: + wfe + ldr x0, [x5] + cmp x0, xzr + beq poll_smp_mbox_go + + /* jump to secondary core entrypoint */ + br x0 + +smp_mbox_insn_end: + /* should never reach */ + b . diff --git a/arch/arm/mach-aspeed/ast2700/platform.c b/arch/arm/mach-aspeed/ast2700/platform.c new file mode 100644 index 00000000000..9cca85766f6 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/platform.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <dm.h> +#include <asm/arch-aspeed/scu_ast2700.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <env.h> +#include <env_internal.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum env_location env_loc = ENVL_UNKNOWN; + u32 strap = readl(ASPEED_IO_HW_STRAP1); + + if (prio) + return env_loc; + + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) { + env_loc = ENVL_NOWHERE; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && + !(strap & SCU_IO_HWSTRAP_EMMC)) { + env_loc = ENVL_SPI_FLASH; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) && + (strap & SCU_IO_HWSTRAP_EMMC) && + !(strap & SCU_IO_HWSTRAP_UFS)) { + env_loc = ENVL_MMC; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) { + /* + * This tree does not carry an ENV_IS_IN_UFS backend yet. + * Fall back to SPI flash when that backend exists. + */ + env_loc = ENVL_SPI_FLASH; + } else { + env_loc = ENVL_NOWHERE; + } + + return env_loc; +} + +int arch_misc_init(void) +{ + if (IS_ENABLED(CONFIG_ARCH_MISC_INIT)) { + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_EMMC)) { + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_UFS)) + env_set("boot_device", "ufs"); + else + env_set("boot_device", "mmc"); + } else { + env_set("boot_device", "spi"); + } + + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_SECBOOT)) + env_set("verify", "yes"); + else + env_set("verify", "no"); + } + + return 0; +} diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 7d00f1650b4..19e3ac360dd 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -78,7 +78,6 @@ choice config TARGET_AT91SAM9260EK bool "Atmel at91sam9260 reference board" select AT91SAM9260 - select BOARD_EARLY_INIT_F config TARGET_GURNARD bool "Support gurnard" @@ -96,7 +95,6 @@ config TARGET_GURNARD config TARGET_AT91SAM9261EK bool "Atmel at91sam9261 reference board" select AT91SAM9261 - select BOARD_EARLY_INIT_F config TARGET_PM9261 bool "Ronetix pm9261 board" @@ -105,7 +103,6 @@ config TARGET_PM9261 config TARGET_AT91SAM9263EK bool "Atmel at91sam9263 reference board" select AT91SAM9263 - select BOARD_EARLY_INIT_F config TARGET_USB_A9263 bool "Caloa USB A9260 board" @@ -119,7 +116,6 @@ config TARGET_PM9263 config TARGET_AT91SAM9M10G45EK bool "Atmel AT91SAM9M10G45-EK board" select AT91SAM9M10G45 - select BOARD_EARLY_INIT_F select SUPPORT_SPL config TARGET_PM9G45 @@ -129,18 +125,15 @@ config TARGET_PM9G45 config TARGET_AT91SAM9N12EK bool "Atmel AT91SAM9N12-EK board" select AT91SAM9N12 - select BOARD_EARLY_INIT_F select SUPPORT_SPL config TARGET_AT91SAM9RLEK bool "Atmel at91sam9rl reference board" select AT91SAM9RL - select BOARD_EARLY_INIT_F config TARGET_AT91SAM9X5EK bool "Atmel AT91SAM9X5-EK board" select AT91SAM9X5 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SUPPORT_SPL @@ -154,31 +147,26 @@ config TARGET_GARDENA_SMART_GATEWAY_AT91SAM config TARGET_SAM9X60EK bool "SAM9X60-EK board" select SAM9X60 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT config TARGET_SAM9X60_CURIOSITY - bool "SAM9X60 CURIOSITY board" - select SAM9X60 - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT + bool "SAM9X60 CURIOSITY board" + select SAM9X60 + select BOARD_LATE_INIT config TARGET_SAM9X75_CURIOSITY bool "SAM9X75 CURIOSITY board" select SAM9X7 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT imply OF_UPSTREAM config TARGET_SAMA5D2_PTC_EK bool "SAMA5D2 PTC EK board" - select BOARD_EARLY_INIT_F select SAMA5D2 select BOARD_LATE_INIT config TARGET_SAMA5D2_XPLAINED bool "SAMA5D2 Xplained board" - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SAMA5D2 select SUPPORT_SPL @@ -186,7 +174,6 @@ config TARGET_SAMA5D2_XPLAINED config TARGET_SAMA5D27_SOM1_EK bool "SAMA5D27 SOM1 EK board" select SAMA5D2 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select CPU_V7A select SUPPORT_SPL @@ -201,7 +188,6 @@ config TARGET_SAMA5D27_SOM1_EK config TARGET_SAMA5D27_WLSOM1_EK bool "SAMA5D27 WLSOM1 EK board" select SAMA5D2 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select CPU_V7A select SUPPORT_SPL @@ -228,7 +214,6 @@ config TARGET_SAMA5D2_ICP bool "SAMA5D2 Industrial Connectivity Platform (ICP)" select SAMA5D2 select SUPPORT_SPL - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT help The SAMA5D2 ICP embeds SAMA5D27 rev. C SoC, together with @@ -248,28 +233,24 @@ config TARGET_SAMA5D29_CURIOSITY config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" - select BOARD_EARLY_INIT_F select SAMA5D3 select SUPPORT_SPL select BOARD_LATE_INIT config TARGET_SAMA5D3XEK bool "SAMA5D3X-EK board" - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SAMA5D3 select SUPPORT_SPL config TARGET_SAMA5D4_XPLAINED bool "SAMA5D4 Xplained board" - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SAMA5D4 select SUPPORT_SPL config TARGET_SAMA5D4EK bool "SAMA5D4 Evaluation Kit" - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select SAMA5D4 select SUPPORT_SPL @@ -289,10 +270,9 @@ config TARGET_CORVUS imply CMD_DM config TARGET_SAMA7G5EK - bool "SAMA7G5 EK board" - select SAMA7G5 - select BOARD_EARLY_INIT_F - select BOARD_LATE_INIT + bool "SAMA7G5 EK board" + select SAMA7G5 + select BOARD_LATE_INIT config TARGET_SAMA7G54_CURIOSITY bool "SAMA7G54 CURIOSITY board" @@ -307,7 +287,6 @@ config TARGET_SAMA7G54_CURIOSITY config TARGET_SAMA7D65_CURIOSITY bool "SAMA7D65 CURIOSITY board" select SAMA7D65 - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT imply OF_UPSTREAM diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 7bfbadf0483..32cf78b3bf6 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -132,7 +132,8 @@ void board_init_f(ulong dummy) timer_init(); - board_early_init_f(); + if (IS_ENABLED(CONFIG_BOARD_EARLY_INIT_F)) + board_early_init_f(); at91_mem_init(); diff --git a/arch/arm/mach-axiado/Kconfig b/arch/arm/mach-axiado/Kconfig new file mode 100644 index 00000000000..12ad44070eb --- /dev/null +++ b/arch/arm/mach-axiado/Kconfig @@ -0,0 +1,22 @@ +if ARCH_AXIADO + +config SYS_ARCH + default "arm" + +config SYS_SOC + default "axiado" + +config AXIADO_AX3005 + bool + select ARM64 + select ARMV8_SWITCH_TO_EL1 + select DM + select DM_SERIAL + select GICV3 + select ZYNQ_SERIAL + select MMC_SDHCI_AXIADO + select PHY_AXIADO_EMMC + +source "arch/arm/mach-axiado/scm3005/Kconfig" + +endif diff --git a/arch/arm/mach-axiado/Makefile b/arch/arm/mach-axiado/Makefile new file mode 100644 index 00000000000..2acd5466dd9 --- /dev/null +++ b/arch/arm/mach-axiado/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). +# + +obj-$(CONFIG_AXIADO_AX3005) += scm3005/ diff --git a/arch/arm/mach-axiado/scm3005/Kconfig b/arch/arm/mach-axiado/scm3005/Kconfig new file mode 100644 index 00000000000..fc74aa0871b --- /dev/null +++ b/arch/arm/mach-axiado/scm3005/Kconfig @@ -0,0 +1,11 @@ +if AXIADO_AX3005 + +config TARGET_SCM3005 + bool "Support Axiado AX3005 SCM3005" + help + Support for the Axiado AX3005 SCM3005 board. + Based on the Axiado AX3005 quad-core ARMv8 Cortex-A53 SoC. + +source "board/axiado/scm3005/Kconfig" + +endif diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h index a86875b1833..c72b47e1b10 100644 --- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h +++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h @@ -54,6 +54,7 @@ #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 #define MISC_CTRL_MAX_BURST_SIZE_128 0x0 +#define MISC_CTRL_MAX_BURST_SIZE_128_2712 0x100000 #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c @@ -70,6 +71,7 @@ #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f +#define PCIE_MISC_PCIE_CTRL 0x4064 #define PCIE_MISC_PCIE_STATUS 0x4068 #define STATUS_PCIE_PORT_MASK 0x80 #define STATUS_PCIE_PORT_SHIFT 7 @@ -108,6 +110,10 @@ #define PCIE_RGR1_SW_INIT_1 0x9210 #define PCIE_EXT_CFG_INDEX 0x9000 +#define RGR1_SW_INIT_1_PERST_MASK 0x1 +#define RGR1_SW_INIT_1_PERSTB_MASK 0x4 +#define RGR1_SW_INIT_1_INIT_MASK 0x2 + /* A small window pointing at the ECAM of the device selected by CFG_INDEX */ #define PCIE_EXT_CFG_DATA 0x8000 diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c index 7a1de22e0ae..7a2faaa4de6 100644 --- a/arch/arm/mach-bcm283x/init.c +++ b/arch/arm/mach-bcm283x/init.c @@ -18,7 +18,7 @@ #ifdef CONFIG_ARM64 #include <asm/armv8/mmu.h> -#define MEM_MAP_MAX_ENTRIES (4) +#define MEM_MAP_MAX_ENTRIES (5) static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = { { @@ -84,6 +84,14 @@ static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + /* Whole PCIe section */ + .virt = 0x1800000000UL, + .phys = 0x1800000000UL, + .size = 0x0800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* SoC bus */ .virt = 0x107c000000UL, .phys = 0x107c000000UL, diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 07125eac7cd..2281686d633 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -33,8 +33,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index e4014226582..561f1ee044a 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -71,10 +71,38 @@ config CSF_SIZE Define the maximum size for Command Sequence File (CSF) binary this information is used to define the image boot data. +config IMX_QB + bool "Support Quickboot flow for Synopsis DDR PHY on iMX platforms" + default y + depends on IMX94 || IMX95 || IMX952 + help + Enable the logic for saving DDR training data from volatile + memory to non-volatile storage. OEI uses the saved data to + run Quickboot flow and skip re-training the DDR PHY. + +config SPL_IMX_QB + bool "Run qb save during SPL" + depends on SPL && IMX_QB + help + Automatically save DDR training data (Quickboot data) + to current boot device when needed (when OEI runs Training + flow and saves qb data to volatile memory). + +config CMD_IMX_QB + bool "Support the 'qb' command" + default y + depends on IMX_QB + help + Enable qb command to write/erase DDR quick boot training + data to/from a chosen boot device. Using 'qb save/erase' + without arguments implies using the current boot device's + first bootable partition (e.g. boot0 for eMMC). For use in + uuu scripts, the boot device must be specified explicitly. + config CMD_BMODE bool "Support the 'bmode' command" default y - depends on ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5 + depends on IMX95 || ARCH_IMX8M || ARCH_MX7 || ARCH_MX6 || ARCH_MX5 help This enables the 'bmode' (bootmode) command for forcing a boot from specific media. @@ -129,7 +157,7 @@ config CMD_PRIBLOB depends on HAS_CAAM && IMX_HAB help This option enables the priblob command which can be used - to set the priblob setting to 0x3. + to set the priblob setting to 0x3. config CMD_HDMIDETECT bool "Support the 'hdmidet' command" diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index bf6820de655..43febc10460 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -80,6 +80,7 @@ endif ifneq ($(CONFIG_XPL_BUILD),y) obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o +obj-$(CONFIG_CMD_IMX_QB) += cmd_qb.o obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o endif diff --git a/arch/arm/mach-imx/cmd_qb.c b/arch/arm/mach-imx/cmd_qb.c new file mode 100644 index 00000000000..a6b654d342f --- /dev/null +++ b/arch/arm/mach-imx/cmd_qb.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024-2026 NXP + */ +#include <command.h> +#include <spl.h> +#include <stdlib.h> + +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/sys_proto.h> +#include <asm/mach-imx/qb.h> + +static void parse_qb_args(int argc, char * const argv[], + const char **ifname, const char **dev) +{ + /* qb save/erase -> use boot device */ + if (argc < 2) { + *ifname = "auto"; + return; + } + + *ifname = argv[1]; + + if (argc == 3) + *dev = argv[2]; +} + +static int do_qb(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[], bool save) +{ + const char *ifname, *dev; + + parse_qb_args(argc, argv, &ifname, &dev); + + if (imx_qb(ifname, dev, save)) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_qb_check(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + return imx_qb_check() ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} + +static int do_qb_save(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + return do_qb(cmdtp, flag, argc, argv, true); +} + +static int do_qb_erase(struct cmd_tbl *cmdtp, int flag, + int argc, char * const argv[]) +{ + return do_qb(cmdtp, flag, argc, argv, false); +} + +static struct cmd_tbl cmd_qb[] = { + U_BOOT_CMD_MKENT(check, 1, 1, do_qb_check, "", ""), + U_BOOT_CMD_MKENT(save, 3, 1, do_qb_save, "", ""), + U_BOOT_CMD_MKENT(erase, 3, 1, do_qb_erase, "", ""), +}; + +static int do_qbops(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct cmd_tbl *cp; + + cp = find_cmd_tbl(argv[1], cmd_qb, ARRAY_SIZE(cmd_qb)); + + /* Drop the qb command */ + argc--; + argv++; + + if (!cp) { + printf("qb: %s: command not found\n", argv[0] ? argv[0] : " "); + return CMD_RET_USAGE; + } + + if (argc > cp->maxargs) { + printf("qb %s: too many arguments: %d > %d\n", cp->name, + argc - 1, cp->maxargs - 1); + return CMD_RET_USAGE; + } + + if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) { + printf("qb %s: repeat flag set but command is not repeatable\n", + cp->name); + return CMD_RET_SUCCESS; + } + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + qb, 4, 1, do_qbops, + "DDR Quick Boot sub system", + "check - check if quick boot data is stored in mem by training flow\n" + "qb save [interface] [dev] - save quick boot data in NVM => trigger quick boot flow\n" + "qb erase [interface] [dev] - erase quick boot data from NVM => trigger training flow\n" +); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 8af45e14707..93be5644c88 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -47,7 +47,7 @@ u32 get_imx_reset_cause(void) return reset_cause; } -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(CPU) static char *get_reset_cause(void) { switch (get_imx_reset_cause()) { @@ -75,11 +75,6 @@ static char *get_reset_cause(void) return "WDOG4"; case 0x00200: return "TEMPSENSE"; -#elif defined(CONFIG_IMX8M) - case 0x00100: - return "WDOG2"; - case 0x00200: - return "TEMPSENSE"; #else case 0x00100: return "TEMPSENSE"; @@ -90,59 +85,10 @@ static char *get_reset_cause(void) return "unknown reset"; } } -#endif - -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case MXC_CPU_IMX8MP: - return "8MP[8]"; /* Quad-core version of the imx8mp */ - case MXC_CPU_IMX8MPD: - return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ - case MXC_CPU_IMX8MPL: - return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ - case MXC_CPU_IMX8MP6: - return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ - case MXC_CPU_IMX8MPUL: - return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */ - case MXC_CPU_IMX8MN: - return "8MNano Quad"; /* Quad-core version */ - case MXC_CPU_IMX8MND: - return "8MNano Dual"; /* Dual-core version */ - case MXC_CPU_IMX8MNS: - return "8MNano Solo"; /* Single-core version */ - case MXC_CPU_IMX8MNL: - return "8MNano QuadLite"; /* Quad-core Lite version */ - case MXC_CPU_IMX8MNDL: - return "8MNano DualLite"; /* Dual-core Lite version */ - case MXC_CPU_IMX8MNSL: - return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */ - case MXC_CPU_IMX8MNUQ: - return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */ - case MXC_CPU_IMX8MNUD: - return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */ - case MXC_CPU_IMX8MNUS: - return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */ - case MXC_CPU_IMX8MM: - return "8MMQ"; /* Quad-core version of the imx8mm */ - case MXC_CPU_IMX8MML: - return "8MMQL"; /* Quad-core Lite version of the imx8mm */ - case MXC_CPU_IMX8MMD: - return "8MMD"; /* Dual-core version of the imx8mm */ - case MXC_CPU_IMX8MMDL: - return "8MMDL"; /* Dual-core Lite version of the imx8mm */ - case MXC_CPU_IMX8MMS: - return "8MMS"; /* Single-core version of the imx8mm */ - case MXC_CPU_IMX8MMSL: - return "8MMSL"; /* Single-core Lite version of the imx8mm */ - case MXC_CPU_IMX8MQ: - return "8MQ"; /* Quad-core version of the imx8mq */ - case MXC_CPU_IMX8MQL: - return "8MQLite"; /* Quad-core Lite version of the imx8mq */ - case MXC_CPU_IMX8MD: - return "8MD"; /* Dual-core version of the imx8mq */ case MXC_CPU_MX7S: return "7S"; /* Single-core version of the mx7 */ case MXC_CPU_MX7D: diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 9794391fb35..e1284833ac5 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -255,7 +255,7 @@ static void display_ahab_auth_ind(u32 event) printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]); } -int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) { int err; u32 resp; @@ -271,9 +271,10 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) printf("Authenticate container hdr failed, return %d, resp 0x%x\n", err, resp); display_ahab_auth_ind(resp); + return NULL; } - return err; + return (void *)IMG_CONTAINER_BASE; /* Return authenticated container header */ } int ahab_auth_release(void) @@ -310,12 +311,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } @@ -327,7 +327,6 @@ int authenticate_os_container(ulong addr) { struct container_hdr *phdr; int i, ret = 0; - int err; u16 length; struct boot_img_t *img; unsigned long s, e; @@ -357,8 +356,8 @@ int authenticate_os_container(ulong addr) debug("container length %u\n", length); - err = ahab_auth_cntr_hdr(phdr, length); - if (err) { + phdr = ahab_auth_cntr_hdr(phdr, length); + if (!phdr) { ret = -EIO; goto exit; } @@ -367,7 +366,7 @@ int authenticate_os_container(ulong addr) /* Copy images to dest address */ for (i = 0; i < phdr->num_images; i++) { - img = (struct boot_img_t *)(addr + + img = (struct boot_img_t *)((ulong)phdr + sizeof(struct container_hdr) + i * sizeof(struct boot_img_t)); diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c index f19ab9edce4..1ef26718463 100644 --- a/arch/arm/mach-imx/fdt.c +++ b/arch/arm/mach-imx/fdt.c @@ -3,6 +3,7 @@ * Copyright 2024 NXP */ +#include <env.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> @@ -91,6 +92,15 @@ int fixup_thermal_trips(void *blob, const char *name) int minc, maxc; int node, trip; + /* + * During development or various dangerous experiments, it may + * be necessary to override the trip points. Allow users to do + * that. However, do keep in mind that this may damage the SoC. + */ + if (CONFIG_IS_ENABLED(ENV_SUPPORT)) + if (env_get("imx_skip_fixup_thermal_trips")) + return 0; + node = fdt_path_offset(blob, "/thermal-zones"); if (node < 0) return node; diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 7bfcc9d7e9d..bdb43d138f2 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -240,6 +240,14 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type) return offset; } +#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE) + int ret; + ret = scmi_get_boot_device_offset(&offset); + if (!ret) + return offset; + /* fall back to boot from primary set if get rom passover failed */ +#endif + sec_boot = check_secondary_cnt_set(&sec_set_off); if (sec_boot) printf("Secondary set selected\n"); @@ -366,10 +374,17 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc) part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) { - unsigned long sec_set_off = 0; bool sec_boot = false; - +#if IS_ENABLED(CONFIG_ARCH_IMX9) && IS_ENABLED(CONFIG_SCMI_FIRMWARE) + u8 stage; + int ret; + ret = scmi_get_boot_stage(&stage); + if (!ret) + sec_boot = (stage == 0x9); +#else + unsigned long sec_set_off = 0; sec_boot = check_secondary_cnt_set(&sec_set_off); +#endif if (sec_boot) part = (part == EMMC_BOOT_PART_BOOT1) ? EMMC_HWPART_BOOT2 : EMMC_HWPART_BOOT1; } else if (part == EMMC_BOOT_PART_USER) { diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index f13baa871cc..34712747fa3 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; #define AHAB_HASH_TYPE_MASK 0x00000700 #define AHAB_HASH_TYPE_SHA256 0 -int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) +void *ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) { int err; @@ -37,10 +37,12 @@ int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length) err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); - if (err) + if (err) { printf("Authenticate container hdr failed, return %d\n", err); + return NULL; + } - return err; + return (void *)SEC_SECURE_RAM_BASE; /* Return authenticated container header */ } int ahab_auth_release(void) @@ -109,12 +111,11 @@ int ahab_verify_cntr_image(struct boot_img_t *img, int image_index) static inline bool check_in_dram(ulong addr) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - if (addr >= bd->bi_dram[i].start && - addr < (bd->bi_dram[i].start + bd->bi_dram[i].size)) + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) return true; } } @@ -126,7 +127,7 @@ int authenticate_os_container(ulong addr) { struct container_hdr *phdr; int i, ret = 0; - int err; + __maybe_unused int err; u16 length; struct boot_img_t *img; unsigned long s, e; @@ -159,15 +160,15 @@ int authenticate_os_container(ulong addr) debug("container length %u\n", length); - err = ahab_auth_cntr_hdr(phdr, length); - if (err) { + phdr = ahab_auth_cntr_hdr(phdr, length); + if (!phdr) { ret = -EIO; goto exit; } /* Copy images to dest address */ for (i = 0; i < phdr->num_images; i++) { - img = (struct boot_img_t *)(addr + + img = (struct boot_img_t *)((ulong)phdr + sizeof(struct container_hdr) + i * sizeof(struct boot_img_t)); diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index f4738e3fda8..b52675d8aba 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -604,18 +604,18 @@ static void dram_bank_sort(int current_bank) phys_size_t size; while (current_bank > 0) { - if (gd->bd->bi_dram[current_bank - 1].start > - gd->bd->bi_dram[current_bank].start) { - start = gd->bd->bi_dram[current_bank - 1].start; - size = gd->bd->bi_dram[current_bank - 1].size; + if (gd->dram[current_bank - 1].start > + gd->dram[current_bank].start) { + start = gd->dram[current_bank - 1].start; + size = gd->dram[current_bank - 1].size; - gd->bd->bi_dram[current_bank - 1].start = - gd->bd->bi_dram[current_bank].start; - gd->bd->bi_dram[current_bank - 1].size = - gd->bd->bi_dram[current_bank].size; + gd->dram[current_bank - 1].start = + gd->dram[current_bank].start; + gd->dram[current_bank - 1].size = + gd->dram[current_bank].size; - gd->bd->bi_dram[current_bank].start = start; - gd->bd->bi_dram[current_bank].size = size; + gd->dram[current_bank].start = start; + gd->dram[current_bank].size = size; } current_bank--; } @@ -643,24 +643,24 @@ int dram_init_banksize(void) continue; if (start >= phys_sdram_1_start && start <= end1) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end1) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end1 - start; + gd->dram[i].size = end1 - start; dram_bank_sort(i); i++; } else if (start >= phys_sdram_2_start && start <= end2) { - gd->bd->bi_dram[i].start = start; + gd->dram[i].start = start; if ((end + 1) <= end2) - gd->bd->bi_dram[i].size = + gd->dram[i].size = end - start + 1; else - gd->bd->bi_dram[i].size = end2 - start; + gd->dram[i].size = end2 - start; dram_bank_sort(i); i++; @@ -670,10 +670,10 @@ int dram_init_banksize(void) /* If error, set to the default value */ if (!i) { - gd->bd->bi_dram[0].start = phys_sdram_1_start; - gd->bd->bi_dram[0].size = phys_sdram_1_size; - gd->bd->bi_dram[1].start = phys_sdram_2_start; - gd->bd->bi_dram[1].size = phys_sdram_2_size; + gd->dram[0].start = phys_sdram_1_start; + gd->dram[0].size = phys_sdram_1_size; + gd->dram[1].start = phys_sdram_2_start; + gd->dram[1].size = phys_sdram_2_size; } return 0; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 8b0d48b07b3..5f7d7e4c66e 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -10,6 +10,7 @@ config IMX8M select ARMV8_CRYPTO imply CPU imply CPU_IMX + imply DM_THERMAL imply IMX_TMU config IMX8MQ @@ -79,11 +80,13 @@ config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" select IMX8MQ select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MQ_REFORM2 bool "imx8mq_reform2" select IMX8MQ select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MM_DATA_MODUL_EDM_SBC bool "Data Modul eDM SBC i.MX8M Mini" @@ -112,6 +115,7 @@ config TARGET_IMX8MM_ICORE_MX8MM select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM help i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM. @@ -136,6 +140,7 @@ config TARGET_IMX8MM_PHG select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MM_VENICE bool "Support Gateworks Venice iMX8M Mini module" @@ -261,6 +266,7 @@ config TARGET_IMX8MP_ICORE_MX8MP select IMX8MP select IMX8M_LPDDR4 select SUPPORT_SPL + imply OF_UPSTREAM help i.Core MX8M Plus is an EDIMM SOM based on NXP i.MX8MP. @@ -308,6 +314,7 @@ config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" select IMX8MQ select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_IMX8MN_VAR_SOM bool "Variscite imx8mn_var_som" @@ -324,6 +331,7 @@ config TARGET_KONTRON_PITX_IMX8M bool "Support Kontron pITX-imx8m" select IMX8MQ select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_TORADEX_SMARC_IMX8MP bool "Support Toradex SMARC iMX8M Plus module" @@ -420,12 +428,14 @@ config TARGET_MSC_SM2S_IMX8MP select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_LIBREM5 bool "Purism Librem5 Phone" select IMX8MQ select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM endchoice diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 1fe083ae94f..909bd7476db 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -224,11 +224,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8m_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8m_mem_map[entry].phys = gd->dram[i].start; + imx8m_mem_map[entry].virt = gd->dram[i].start; + imx8m_mem_map[entry].size = gd->dram[i].size; imx8m_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size); @@ -290,24 +290,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -315,8 +315,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; @@ -442,7 +442,7 @@ static u32 get_cpu_variant_type(u32 type) u32 flag = 0; if ((value0 & 0xc0000) == 0x80000) - return MXC_CPU_IMX8MPD; + flag |= (1 << 10); /* vpu disabled */ if ((value0 & 0x43000000) == 0x43000000) @@ -475,6 +475,12 @@ static u32 get_cpu_variant_type(u32 type) return MXC_CPU_IMX8MPL; case 2: return MXC_CPU_IMX8MP6; + case 0x400: + return MXC_CPU_IMX8MPD; + case 0x4: + return MXC_CPU_IMX8MP5; + case 0x404: + return MXC_CPU_IMX8MPD2; default: break; } @@ -1433,13 +1439,15 @@ usb_modify_speed: if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6()) disable_npu_nodes(blob); - if (is_imx8mpul() || is_imx8mpl()) + if (is_imx8mpul() || is_imx8mpl() || + is_imx8mpd2() || is_imx8mp5()) disable_isp_nodes(blob); - if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6()) + if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6() || + is_imx8mpd2() || is_imx8mp5()) disable_dsp_nodes(blob); - if (is_imx8mpd()) + if (is_imx8mpd() || is_imx8mpd2()) disable_cpu_nodes(blob, nodes_path, 2, 4); #endif @@ -1472,6 +1480,33 @@ void reset_cpu(void) #endif #if IS_ENABLED(CONFIG_ARCH_MISC_INIT) +static char *get_reset_cause(void) +{ + switch (get_imx_reset_cause()) { + case 0x00001: + case 0x00011: + return "POR"; + case 0x00004: + return "CSU"; + case 0x00008: + return "IPP USER"; + case 0x00010: + return "WDOG"; + case 0x00020: + return "JTAG HIGH-Z"; + case 0x00040: + return "JTAG SW"; + case 0x00080: + return "WDOG3"; + case 0x00100: + return "WDOG2"; + case 0x00200: + return "TEMPSENSE"; + default: + return "unknown reset"; + } +} + int arch_misc_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { @@ -1483,6 +1518,9 @@ int arch_misc_init(void) printf("Failed to initialize caam_jr: %d\n", ret); } + if (IS_ENABLED(CONFIG_XPL_BUILD)) + printf("Reset cause: %s\n", get_reset_cause()); + return 0; } #endif diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 1ee483065e8..3e9566bd7ca 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -254,11 +254,6 @@ static char *get_reset_cause(char *ret) } #if defined(CONFIG_DISPLAY_CPUINFO) -const char *get_imx_type(u32 imxtype) -{ - return "8ULP"; -} - int print_cpuinfo(void) { u32 cpurev; @@ -266,8 +261,7 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); - printf("CPU: i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), + printf("CPU: i.MX8ULP rev%d.%d at %d MHz\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); @@ -343,7 +337,17 @@ static void disable_wdog(void __iomem *wdog_base) void init_wdog(void) { - disable_wdog((void __iomem *)WDG3_RBASE); + ofnode node; + + ofnode_for_each_compatible_node(node, "fsl,imx8ulp-wdt") { + phys_addr_t base; + + base = ofnode_get_addr(node); + if (base == FDT_ADDR_T_NONE) + continue; + + disable_wdog((void __iomem *)base); + } } static struct mm_region imx8ulp_arm64_mem_map[] = { @@ -502,11 +506,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx8ulp_arm64_mem_map[entry].phys = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].virt = gd->dram[i].start; + imx8ulp_arm64_mem_map[entry].size = gd->dram[i].size; imx8ulp_arm64_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size); @@ -558,24 +562,24 @@ int dram_init_banksize(void) if (ret) return ret; - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_size; + gd->dram[bank].size = sdram_size; } return 0; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 2308457df23..cbd0078ba2a 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -1,18 +1,20 @@ if ARCH_IMX9 config AHAB_BOOT - bool "Support i.MX9 AHAB features" - help - This option enables the support for AHAB secure boot. + bool "Support i.MX9 AHAB features" + help + This option enables the support for AHAB secure boot. config IMX9 bool + select ARCH_MISC_INIT select BINMAN select CPU select CPU_IMX select HAS_CAAM select ROM_UNIFIED_SECTIONS imply IMX_TMU + imply OF_LIVE config IMX93 bool @@ -22,7 +24,6 @@ config IMX93 config IMX91 bool select IMX9 - select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS config IMX95_A0 @@ -30,7 +31,6 @@ config IMX95_A0 config IMX95 bool - select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS select IMX9 select DM_MAILBOX @@ -69,6 +69,7 @@ config TARGET_IMX91_11X11_EVK select IMX91 imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND + imply OF_UPSTREAM config TARGET_IMX91_11X11_FRDM bool "imx91_11x11_frdm" @@ -77,6 +78,7 @@ config TARGET_IMX91_11X11_FRDM select IMX9_LPDDR4X imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND + imply OF_UPSTREAM config TARGET_IMX93_9X9_QSB bool "imx93_qsb" @@ -114,11 +116,13 @@ config TARGET_IMX93_FRDM select REMOTEPROC_IMX select REGMAP select SYSCON + imply OF_UPSTREAM config TARGET_IMX93_VAR_SOM bool "imx93_var_som" select IMX93 select IMX9_LPDDR4X + imply OF_UPSTREAM config TARGET_KONTRON_MX93 bool "Kontron OSM-S/BL i.MX93" @@ -147,6 +151,7 @@ config TARGET_PHYCORE_IMX93 config TARGET_IMX95_19X19_EVK bool "imx95_19x19_evk" + select OF_BOARD_FIXUP select IMX95 imply BOOTSTD_BOOTCOMMAND imply BOOTSTD_FULL @@ -154,6 +159,7 @@ config TARGET_IMX95_19X19_EVK config TARGET_IMX95_15X15_EVK bool "imx95_15x15_evk" + select OF_BOARD_FIXUP select IMX95 imply BOOTSTD_BOOTCOMMAND imply BOOTSTD_FULL @@ -161,18 +167,28 @@ config TARGET_IMX95_15X15_EVK config TARGET_IMX943_EVK bool "imx943_evk" + select OF_BOARD_FIXUP select IMX94 imply BOOTSTD_BOOTCOMMAND imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_AQUILA_IMX95 + bool "Support Toradex Aquila iMX95" + select IMX95 + config TARGET_TORADEX_SMARC_IMX95 bool "Support Toradex SMARC iMX95" select IMX95 imply OF_UPSTREAM +config TARGET_VERDIN_IMX95 + bool "Support Toradex Verdin iMX95 module" + select IMX95 + config TARGET_IMX952_EVK bool "imx952_evk" + select OF_BOARD_FIXUP select IMX_SM_CPU select IMX_SM_LMM select IMX952 @@ -194,7 +210,9 @@ source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" +source "board/toradex/aquila-imx95/Kconfig" source "board/toradex/smarc-imx95/Kconfig" +source "board/toradex/verdin-imx95/Kconfig" source "board/nxp/imx952_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index 53cc97c6b47..ec08430d41d 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright 2022 NXP +# Copyright 2022,2026 NXP obj-y += lowlevel_init.o @@ -11,5 +11,7 @@ obj-y += soc.o clock.o clock_root.o trdc.o endif ifneq ($(CONFIG_SPL_BUILD),y) -obj-y += imx_bootaux.o -endif
\ No newline at end of file +obj-y += imx_bootaux.o misc.o +endif + +obj-$(CONFIG_$(PHASE_)IMX_QB) += qb.o diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 14a2bdf5762..4ccff67b7ab 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -478,6 +478,7 @@ u32 get_clk_src_rate(enum ccm_clk_src source) switch (source) { case ARM_PLL_CLK: ctrl = readl(&ana_regs->arm_pll.ctrl.reg); + break; case AUDIO_PLL_CLK: ctrl = readl(&ana_regs->audio_pll.ctrl.reg); break; diff --git a/arch/arm/mach-imx/imx9/misc.c b/arch/arm/mach-imx/imx9/misc.c new file mode 100644 index 00000000000..3cad67aed43 --- /dev/null +++ b/arch/arm/mach-imx/imx9/misc.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023-2026 NXP + * + */ + +#include <command.h> +#include <cpu_func.h> +#include <init.h> +#include <log.h> +#include <asm/io.h> +#include <errno.h> +#include <linux/bitops.h> +#include <asm/arch-imx/cpu.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/arch/sys_proto.h> +#include <linux/delay.h> +#include <linux/sizes.h> +#include <display_options.h> + +static int do_v2x_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + u32 resp = 0; + struct v2x_get_state state; + + if (is_imx91() || is_imx93()) { + printf("No V2X supported\n"); + return CMD_RET_FAILURE; + } + + ret = ele_v2x_get_state(&state, &resp); + if (ret) { + printf("get v2x state failed, resp 0x%x, ret %d\n", resp, ret); + return CMD_RET_FAILURE; + } + + printf("V2X state: 0x%x\n", state.v2x_state); + printf("V2X power state: 0x%x\n", state.v2x_power_state); + printf("V2X err code: 0x%x\n", state.v2x_err_code); + + return CMD_RET_SUCCESS; +} + +static int do_ele_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + u32 res = 0, length; + struct ele_get_info_data *info; + + /* ELE can't access full DDR */ + info = (struct ele_get_info_data *)(CONFIG_TEXT_BASE + SZ_2M - + sizeof(struct ele_get_info_data)); + flush_dcache_range((ulong)info, (ulong)info + sizeof(struct ele_get_info_data)); + + ret = ele_get_info(info, &res); + if (ret) { + printf("Get ELE info failed, resp 0x%x, ret %d\n", res, ret); + return CMD_RET_FAILURE; + } + + invalidate_dcache_range((ulong)info, (ulong)info + sizeof(struct ele_get_info_data)); + + printf("SOC: 0x%x\n", info->soc); + printf("LC: 0x%x\n", info->lc); + + printf("\nUID:\n"); + print_buffer(0, &info->uid, 4, 4, 0); + + printf("\nSHA256 ROM PATCH:\n"); + print_buffer(0, &info->sha256_rom_patch, 4, 8, 0); + + printf("\nSHA FW:\n"); + print_buffer(0, &info->sha_fw, 4, 8, 0); + + printf("\nOEM SRKH:\n"); + print_buffer(0, &info->oem_srkh, 4, 16, 0); + + printf("\nSTATE: 0x%x\n", info->state); + + length = (info->hdr >> 16) & 0xffff; + if (length == sizeof(struct ele_get_info_data)) { + printf("\nOEM PQC SRKH:\n"); + print_buffer(0, &info->oem_pqc_srkh, 4, 16, 0); + } + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(v2x_status, CONFIG_SYS_MAXARGS, 1, do_v2x_status, + "display v2x status", + "" +); + +U_BOOT_CMD(ele_info, CONFIG_SYS_MAXARGS, 1, do_ele_info, + "display ELE information", + "" +); diff --git a/arch/arm/mach-imx/imx9/qb.c b/arch/arm/mach-imx/imx9/qb.c new file mode 100644 index 00000000000..d13f6acf569 --- /dev/null +++ b/arch/arm/mach-imx/imx9/qb.c @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024-2026 NXP + */ +#include <dm/device-internal.h> +#include <dm/uclass.h> +#include <errno.h> +#include <imx_container.h> +#include <linux/bitfield.h> +#include <mmc.h> +#include <spi_flash.h> +#include <spl.h> +#include <stdlib.h> +#include <u-boot/crc.h> + +#include <asm/arch/ddr.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/sys_proto.h> + +#define QB_STATE_LOAD_SIZE SZ_64K + +#define BLK_DEV 0 +#define SPI_DEV 1 + +#define IMG_FLAGS_IMG_TYPE_MASK 0xF +#define IMG_FLAGS_IMG_TYPE(x) FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x)) + +#define IMG_TYPE_DDR_TDATA_DUMMY 0xD /* dummy DDR training data image */ + +static const struct { + const char *ifname; + const char *dev; +} imx_boot_devs[] = { + [BOOT_DEVICE_MMC1] = { "mmc", "0" }, + [BOOT_DEVICE_MMC2] = { "mmc", "1" }, + [BOOT_DEVICE_SPI] = { "spi", "" }, +}; + +static int imx_qb_get_board_boot_device(void) +{ + switch (get_boot_device()) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +static int imx_qb_get_boot_dev_str(const char **ifname, const char **dev) +{ + int boot_dev; + + if (IS_ENABLED(CONFIG_XPL_BUILD)) + boot_dev = spl_boot_device(); + else + boot_dev = imx_qb_get_board_boot_device(); + + if (boot_dev == BOOT_DEVICE_NONE || boot_dev == BOOT_DEVICE_BOARD) + return -EINVAL; + + *ifname = imx_boot_devs[boot_dev].ifname; + *dev = imx_boot_devs[boot_dev].dev; + + return 0; +} + +bool imx_qb_check(void) +{ + struct ddrphy_qb_state *qb_state; + u32 size, crc; + + /* + * Ensure CRC is not empty, the reason is that + * the data is invalidated after first save run + * or after it is overwritten. + */ + qb_state = (struct ddrphy_qb_state *)CONFIG_QB_SAVED_STATE_BASE; + size = sizeof(struct ddrphy_qb_state) - sizeof(qb_state->crc); + crc = crc32(0, (u8 *)qb_state->mac, size); + + if (!qb_state->crc || crc != qb_state->crc) + return false; + + return true; +} + +static int imx_qb_get_blk_boot_part(const char * const ifname, + const char * const dev, + struct blk_desc **bdesc) +{ + struct udevice *udev; + struct disk_partition info; + struct mmc *mmc; + int part; + int ret; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return blk_get_device_part_str(ifname, dev, bdesc, &info, 1); + + /* + * SPL does not have access to part_get_info, + * so get the partition manually. Currently only + * supporting MMC devices. + */ + ret = blk_get_device_by_str(ifname, dev, bdesc); + + if (ret < 0) + return -ENODEV; + + if ((*bdesc)->uclass_id != UCLASS_MMC) + return -EOPNOTSUPP; + + udev = dev_get_parent((*bdesc)->bdev); + mmc = mmc_get_mmc_dev(udev); + + if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) + return 0; + + part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2) + return part; + + return 0; +} + +static ulong imx_qb_get_boot_device_offset(void *dev, int dev_type) +{ + struct blk_desc *bdesc; + + switch (dev_type) { + case BLK_DEV: + bdesc = dev; + + /* eMMC boot partition */ + if (bdesc->hwpart) + return CONTAINER_HDR_EMMC_OFFSET; + + return CONTAINER_HDR_MMCSD_OFFSET; + case SPI_DEV: + return CONTAINER_HDR_QSPI_OFFSET; + default: + return -EOPNOTSUPP; + } +} + +static int imx_qb_parse_container(void *addr, u64 *qb_data_off) +{ + struct container_hdr *phdr; + struct boot_img_t *img_entry; + u32 img_type, img_end; + int i; + + phdr = addr; + if (phdr->tag != 0x87 || (phdr->version != 0x0 && phdr->version != 0x2)) + return -EINVAL; + + img_entry = addr + sizeof(struct container_hdr); + for (i = 0; i < phdr->num_images; i++) { + img_type = IMG_FLAGS_IMG_TYPE(img_entry->hab_flags); + if (img_type == IMG_TYPE_DDR_TDATA_DUMMY && img_entry->size == 0) { + /* Image entry pointing to DDR Training Data */ + *qb_data_off = img_entry->offset; + return 0; + } + + img_end = img_entry->offset + img_entry->size; + if (i + 1 < phdr->num_images) { + img_entry++; + if (img_end + QB_STATE_LOAD_SIZE == img_entry->offset) { + /* hole detected */ + *qb_data_off = img_end; + return 0; + } + } + } + + return -EINVAL; +} + +static int imx_qb_get_dev_qbdata_offset(void *dev, int dev_type, ulong offset, + u64 *qbdata_offset) +{ + struct blk_desc *bdesc; + u8 *buf; + ulong count; + int ret; + + buf = malloc(CONTAINER_HDR_ALIGNMENT); + if (!buf) + return -ENOMEM; + + switch (dev_type) { + case BLK_DEV: + bdesc = dev; + + count = blk_dread(bdesc, + offset / bdesc->blksz, + CONTAINER_HDR_ALIGNMENT / bdesc->blksz, + buf); + if (count == 0) { + printf("Read container image from MMC/SD failed\n"); + ret = -EIO; + goto imx_qb_get_dev_qbdata_offset_exit; + } + break; + case SPI_DEV: + if (!CONFIG_IS_ENABLED(SPI)) { + ret = -EOPNOTSUPP; + goto imx_qb_get_dev_qbdata_offset_exit; + } + + ret = spi_flash_read_dm(dev, offset, + CONTAINER_HDR_ALIGNMENT, buf); + if (ret) { + printf("Read container header from SPI failed\n"); + ret = -EIO; + goto imx_qb_get_dev_qbdata_offset_exit; + } + break; + default: + printf("Support for device %d not enabled\n", dev_type); + ret = -EOPNOTSUPP; + goto imx_qb_get_dev_qbdata_offset_exit; + } + + ret = imx_qb_parse_container(buf, qbdata_offset); + +imx_qb_get_dev_qbdata_offset_exit: + free(buf); + + return ret; +} + +static int imx_qb_get_qbdata_offset(void *dev, int dev_type, + u64 *qbdata_offset) +{ + u64 cont_offset; + int ret, i; + + cont_offset = imx_qb_get_boot_device_offset(dev, dev_type); + + for (i = 0; i < 3; i++) { + ret = imx_qb_get_dev_qbdata_offset(dev, dev_type, cont_offset, + qbdata_offset); + if (ret == 0) { + (*qbdata_offset) += cont_offset; + break; + } + + cont_offset += CONTAINER_HDR_ALIGNMENT; + } + + return ret; +} + +static int imx_qb_blk(const char * const ifname, + const char * const dev, bool save) +{ + struct blk_desc *bdesc; + u64 offset; + u64 load_size; + int part, orig_part; + int ret; + + part = imx_qb_get_blk_boot_part(ifname, dev, &bdesc); + + if (part < 0) { + printf("Failed to find %s %s\n", ifname, dev); + return -ENODEV; + } + + orig_part = bdesc->hwpart; + + ret = blk_dselect_hwpart(bdesc, part); + if (ret && ret != -EMEDIUMTYPE) { + printf("Failed to select hwpart, ret %d\n", ret); + return ret; + } + + ret = imx_qb_get_qbdata_offset(bdesc, BLK_DEV, &offset); + if (ret) { + printf("get_qbdata_offset failed, ret = %d\n", ret); + return ret; + } + + offset /= bdesc->blksz; + load_size = QB_STATE_LOAD_SIZE / bdesc->blksz; + + if (save) { + /* QB data is stored in DDR -> can use it as buf */ + ret = blk_dwrite(bdesc, offset, load_size, + (const void *)CONFIG_QB_SAVED_STATE_BASE); + } else { + /* erase */ + ret = blk_derase(bdesc, offset, load_size); + } + + if (ret != load_size) { + printf("Failed to %s block device\n", save ? "write to" : "erase"); + return -EIO; + } + + /* Return to original partition */ + ret = blk_dselect_hwpart(bdesc, orig_part); + if (ret && ret != -EMEDIUMTYPE) { + printf("Failed to select hwpart, ret %d\n", ret); + return ret; + } + + return 0; +} + +static int imx_qb_spi(bool save) +{ + struct udevice *flash; + u64 offset; + int ret; + + if (!CONFIG_IS_ENABLED(SPI)) { + printf("SPI not enabled\n"); + return -EOPNOTSUPP; + } + + ret = uclass_first_device_err(UCLASS_SPI_FLASH, &flash); + if (ret) { + printf("SPI flash not found.\n"); + return -ENODEV; + } + + ret = imx_qb_get_qbdata_offset(flash, SPI_DEV, &offset); + if (ret) { + printf("get_qbdata_offset failed, ret = %d\n", ret); + return ret; + } + + ret = spi_flash_erase_dm(flash, offset, QB_STATE_LOAD_SIZE); + + if (ret) + return ret; + + if (!save) + return 0; + + /* QB data is stored in DDR -> can use it as buf */ + ret = spi_flash_write_dm(flash, offset, + QB_STATE_LOAD_SIZE, + (const void *)CONFIG_QB_SAVED_STATE_BASE); + + return ret; +} + +int imx_qb(const char *ifname, const char *dev, bool save) +{ + int ret; + + ret = 0; + + /* Try to use boot device */ + if (!strcmp(ifname, "auto")) + ret = imx_qb_get_boot_dev_str(&ifname, &dev); + + if (ret) + return ret; + + if (save && !imx_qb_check()) + return -EINVAL; + + if (!strcmp(ifname, "spi")) + ret = imx_qb_spi(save); + else + ret = imx_qb_blk(ifname, dev, save); + + if (ret) + return ret; + + if (!save) + return 0; + + /* + * invalidate qb_state mem so that at next boot + * the check function will fail and save won't happen + */ + memset((void *)CONFIG_QB_SAVED_STATE_BASE, 0, + sizeof(struct ddrphy_qb_state)); + + return 0; +} + +void spl_imx_qb_save(void) +{ + /* Save QB data on current boot device */ + if (imx_qb("auto", "", true)) + printf("QB save failed\n"); +} diff --git a/arch/arm/mach-imx/imx9/scmi/Makefile b/arch/arm/mach-imx/imx9/scmi/Makefile index b98744e1ecb..e83d27327cb 100644 --- a/arch/arm/mach-imx/imx9/scmi/Makefile +++ b/arch/arm/mach-imx/imx9/scmi/Makefile @@ -5,5 +5,5 @@ # Add include path for NXP device tree header files from Linux. ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/ -obj-y += soc.o +obj-y += soc.o fdt.o obj-y += clock_scmi.o clock.o diff --git a/arch/arm/mach-imx/imx9/scmi/fdt.c b/arch/arm/mach-imx/imx9/scmi/fdt.c new file mode 100644 index 00000000000..a1d9afbf69a --- /dev/null +++ b/arch/arm/mach-imx/imx9/scmi/fdt.c @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + * + */ + +#include <asm/arch/sys_proto.h> +#include <linux/bitfield.h> +#include <fuse.h> +#include <fdt_support.h> +#include <fdtdec.h> + +struct periph_fuse_info { + u32 bit_mask; + u32 soc_type; /* 0 means for all */ + bool of_board_fix; + int (*disable_func)(void *blob, u32 fuse_val); +}; + +int num_a55_cores_disabled; +int gpu_disabled; + +static int delete_fdt_nodes(void *blob, const char *const nodes_path[], int size_array) +{ + int i = 0; + int rc; + int nodeoff; + + for (i = 0; i < size_array; i++) { + nodeoff = fdt_path_offset(blob, nodes_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + debug("Found %s node\n", nodes_path[i]); + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) { + printf("Unable to delete node %s, err=%s\n", + nodes_path[i], fdt_strerror(rc)); + } else { + printf("Delete node %s\n", nodes_path[i]); + } + } + + return 0; +} + +static int disable_fdt_nodes(void *blob, const char *const nodes_path[], + int size_array, const char *prop, const char *value) +{ + int i = 0; + int rc; + int nodeoff; + const char *status = "disabled"; + const char *prop_str; + + for (i = 0; i < size_array; i++) { + nodeoff = fdt_path_offset(blob, nodes_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + debug("Found %s node\n", nodes_path[i]); + + if (prop && value) { + prop_str = fdt_stringlist_get(blob, nodeoff, prop, 0, NULL); + + if (!prop_str || strcmp(prop_str, value)) + continue; + } + +add_status: + rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1); + if (rc) { + if (rc == -FDT_ERR_NOSPACE) { + rc = fdt_increase_size(blob, 512); + if (!rc) + goto add_status; + } + printf("Unable to update property %s:%s, err=%s\n", + nodes_path[i], "status", fdt_strerror(rc)); + } else { + debug("Modify %s:%s disabled\n", nodes_path[i], "status"); + } + } + + return 0; +} + +static int get_cooling_device_list(void *blob, u32 nodeoff, + const char *const path, u32 *cooling_dev, int max_cnt) +{ + int cnt, j; + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", + cooling_dev, max_cnt); + if (cnt < 0) { + printf("cnt incorrect, path %s, cnt = %d\n", path, cnt); + return cnt; + } + if (cnt != max_cnt) + printf("Warning: %s, cooling-device count %d\n", path, cnt); + + for (j = 0; j < cnt; j++) + cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]); + + return cnt; +} + +static void disable_thermal_vpu_node(void *blob, u32 disabled_cores, u32 gpu_disabled) +{ + static const char * const thermal_path[] = { + "/thermal-zones/ana/cooling-maps/map0", + "/thermal-zones/ana-thermal/cooling-maps/map0", + }; + int num_cpus = (is_imx94() || is_imx952()) ? 4 : 6; + u32 array_cnt = (num_cpus + 2) * 3 - (disabled_cores * 3) - (gpu_disabled * 3); + u32 cooling_dev[array_cnt]; + + int nodeoff, ret, i, cnt; + + for (i = 0; i < ARRAY_SIZE(thermal_path); i++) { + nodeoff = fdt_path_offset(blob, thermal_path[i]); + if (nodeoff < 0) { + printf("path not found %s\n", thermal_path[i]); + continue; /* Not found, skip it */ + } + + cnt = get_cooling_device_list(blob, nodeoff, + thermal_path[i], cooling_dev, array_cnt); + /* VPU map does not exist in cooling dev*/ + if (cnt <= ((num_cpus - disabled_cores) * 3 + (gpu_disabled ? 0 : 3))) + continue; + + /* Remove VPU it the last two nodes in the fdt ana blob */ + ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev, + sizeof(u32) * (array_cnt - 3)); + + if (ret < 0) { + printf("Warning: %s, cooling-device setprop failed %d\n", + thermal_path[i], ret); + continue; + } + + printf("Update node %s, cooling-device prop\n", thermal_path[i]); + } +} + +static void disable_thermal_gpu_node(void *blob, u32 disabled_cores) +{ + static const char * const thermal_path[] = { + "/thermal-zones/ana/cooling-maps/map0", + "/thermal-zones/ana-thermal/cooling-maps/map0", + }; + int num_cpus = (is_imx94() || is_imx952()) ? 4 : 6; + u32 array_cnt = (num_cpus + 2) * 3 - (disabled_cores * 3); + u32 cooling_dev[array_cnt]; + int nodeoff, ret, i, cnt; + + for (i = 0; i < ARRAY_SIZE(thermal_path); i++) { + nodeoff = fdt_path_offset(blob, thermal_path[i]); + if (nodeoff < 0) { + printf("path not found %s\n", thermal_path[i]); + continue; /* Not found, skip it */ + } + + cnt = get_cooling_device_list(blob, nodeoff, thermal_path[i], + cooling_dev, array_cnt); + if (cnt <= (num_cpus - disabled_cores) * 3) + continue; /* GPU map does not exist in cooling dev*/ + + /* Remove GPU and VPU as these are the last two nodes in the fdt ana blob */ + ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev, + sizeof(u32) * (array_cnt - 6)); + if (ret < 0) { + printf("Warning: %s, cooling-device setprop failed %d\n", + thermal_path[i], ret); + continue; + } + + if (cnt == array_cnt) { + /* Add VPU node back to ana thermal-zone. */ + ret = fdt_appendprop(blob, nodeoff, "cooling-device", + &cooling_dev[array_cnt - 3], sizeof(u32) * 3); + if (ret < 0) { + printf("Warning: %s, cooling-device appendprop failed %d\n", + thermal_path[i], ret); + continue; + } + } + + printf("Update node %s, cooling-device prop\n", thermal_path[i]); + } +} + +static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores) +{ + static const char * const thermal_path[] = { + "/thermal-zones/pf53_arm/cooling-maps/map0", + "/thermal-zones/ana/cooling-maps/map0", + "/thermal-zones/a55/cooling-maps/map0", + "/thermal-zones/a55-thermal/cooling-maps/map0", + "/thermal-zones/ana-thermal/cooling-maps/map0", + }; + u32 cooling_dev[24]; + int nodeoff, ret, i, cnt; + int prop_size = 3 * ((is_imx94() || is_imx952()) ? 4 : 6); + + for (i = 0; i < ARRAY_SIZE(thermal_path); i++) { + nodeoff = fdt_path_offset(blob, thermal_path[i]); + if (nodeoff < 0) { + printf("path not found %s\n", thermal_path[i]); + continue; /* Not found, skip it */ + } + cnt = get_cooling_device_list(blob, nodeoff, thermal_path[i], cooling_dev, 24); + + ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev, + sizeof(u32) * (prop_size - disabled_cores * 3)); + + if (ret < 0) { + printf("Warning: %s, cooling-device setprop failed %d\n", + thermal_path[i], ret); + continue; + } + + /* Add GPU and VPU nodes back to ana thermal-zone. */ + if (cnt > prop_size) { + ret = fdt_appendprop(blob, nodeoff, "cooling-device", + &cooling_dev[prop_size], + sizeof(u32) * (cnt - prop_size)); + if (ret < 0) { + printf("Warning: %s, cooling-device appendprop failed %d\n", + thermal_path[i], ret); + continue; + } + } + + printf("Update node %s, cooling-device prop\n", thermal_path[i]); + } +} + +static int disable_ld_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_ld[] = { + "/remoteproc", + "/disp-mu", + "/soc/syscon@4b070000", + "/soc/mailbox@4b080000", + "/soc/mailbox@4b090000", + }; + + return delete_fdt_nodes(blob, nodes_path_ld, ARRAY_SIZE(nodes_path_ld)); +} + +static int disable_npu_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_npu[] = { + "/soc/imx95-neutron-remoteproc@4ab00000", + "/soc/imx95-neutron@4ab00004", + "/soc/neutron-remoteproc@4ab00000", + "/soc/neutron@4ab00004", + }; + + return delete_fdt_nodes(blob, nodes_path_npu, ARRAY_SIZE(nodes_path_npu)); +} + +static int disable_arm_cpu_nodes(void *blob, u32 fuse_val) +{ + u32 i = 0; + int rc; + int nodeoff; + char nodes_path[32]; + int num_cpus = (is_imx94() || is_imx952()) ? 4 : 6; + + num_a55_cores_disabled = 0; + + if (fuse_val & BIT(2)) /* A55C2 */ + num_a55_cores_disabled++; + + if (fuse_val & BIT(3)) /* A55C2 */ + num_a55_cores_disabled++; + + if (fuse_val & BIT(4)) /* A55C3 */ + num_a55_cores_disabled++; + + if (fuse_val & BIT(5)) /* A55C4 */ + num_a55_cores_disabled++; + + if (fuse_val & BIT(6)) /* A55C5 */ + num_a55_cores_disabled++; + + for (i = num_cpus; i > (num_cpus - num_a55_cores_disabled); i--) { + sprintf(nodes_path, "/cpus/cpu@%u00", i - 1); + + nodeoff = fdt_path_offset(blob, nodes_path); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + debug("Found %s node\n", nodes_path); + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) { + printf("Unable to delete node %s, err=%s\n", + nodes_path, fdt_strerror(rc)); + } else { + printf("Delete node %s\n", nodes_path); + + /* Remove node from cpu-map/cluster0 */ + sprintf(nodes_path, "/cpus/cpu-map/cluster0/core%u", i - 1); + nodeoff = fdt_path_offset(blob, nodes_path); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + rc = fdt_del_node(blob, nodeoff); + if (rc < 0) + printf("Unable to delete node %s, err=%s\n", + nodes_path, fdt_strerror(rc)); + } + } + + disable_thermal_cpu_nodes(blob, num_a55_cores_disabled); + + return 0; +} + +static int disable_jpegdec_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_jpegdec[] = { + "/soc/jpegdec@4c500000", + }; + + return delete_fdt_nodes(blob, nodes_path_jpegdec, ARRAY_SIZE(nodes_path_jpegdec)); +} + +static int disable_jpegenc_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_jpegenc[] = { + "/soc/jpegenc@4c550000", + }; + + return delete_fdt_nodes(blob, nodes_path_jpegenc, ARRAY_SIZE(nodes_path_jpegenc)); +} + +static int disable_mipicsi0_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_mipicsi0[] = { + "/soc/csi@4ad30000", + }; + + return delete_fdt_nodes(blob, nodes_path_mipicsi0, ARRAY_SIZE(nodes_path_mipicsi0)); +} + +static int disable_mipicsi1_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_mipicsi1[] = { + "/soc/csi@4ad40000", + }; + + return delete_fdt_nodes(blob, nodes_path_mipicsi1, ARRAY_SIZE(nodes_path_mipicsi1)); +} + +static int disable_isp_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_isp[] = { + "/soc@0/isp@4ae00000", + "/soc/isp@4ae00000", + }; + + return delete_fdt_nodes(blob, nodes_path_isp, ARRAY_SIZE(nodes_path_isp)); +} + +static int disable_vpu_node(void *blob, u32 fuse_val) +{ + int ret = 0; + + static const char * const nodes_path_vpu[] = { + "/soc/vpu-ctrl@4c4c0000", + "/soc/vpu-ctrl@4c4f0000", + "/soc/vpu@4c480000", + "/soc/vpu@4c490000", + "/soc/vpu@4c4a0000", + "/soc/vpu@4c4b0000", + "/soc/vpu@4c4c0000", + "/soc/vpu@4c4d0000", + "/soc/vpu@4c4e0000", + "/soc/jpegdec@4c500000", + "/soc/jpegenc@4c550000", + "/soc/vpuenc@4c460000", + "/soc/syscon@4c410000" + }; + + ret = delete_fdt_nodes(blob, nodes_path_vpu, ARRAY_SIZE(nodes_path_vpu)); + if (!ret) + disable_thermal_vpu_node(blob, num_a55_cores_disabled, gpu_disabled); + + return ret; +} + +static int disable_vpuenc_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_vpuenc[] = { + "/soc/vpuenc@4c460000", + }; + + return delete_fdt_nodes(blob, nodes_path_vpuenc, ARRAY_SIZE(nodes_path_vpuenc)); +} + +static int disable_vpuwave511_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_vpu511[] = { + "/soc/vpu-ctrl@4c4f0000", + "/soc/vpu@4c4b0000", + "/soc/vpu@4c4c0000", + "/soc/vpu@4c4d0000", + "/soc/vpu@4c4e0000", + }; + + return delete_fdt_nodes(blob, nodes_path_vpu511, ARRAY_SIZE(nodes_path_vpu511)); +} + +static int disable_gpu_node(void *blob, u32 fuse_val) +{ + int ret = 0; + + static const char * const nodes_path_gpu[] = { + "/soc/gpu@4d900000", + "/thermal-zones@1/ana/cooling-maps/map1/cooling-device/gpu@4d900000", + "/thermal-zones/ana/cooling-maps/map1/cooling-device/gpu@4d900000", + "/thermal-zones@1/ana/cooling-maps/map1/cooling-device", + "/thermal-zones/ana/cooling-maps/map1/cooling-device", + "/thermal-zones@1/ana/cooling-maps/map1", + "/thermal-zones/ana/cooling-maps/map1", + }; + + ret = delete_fdt_nodes(blob, nodes_path_gpu, ARRAY_SIZE(nodes_path_gpu)); + if (!ret) { + disable_thermal_gpu_node(blob, num_a55_cores_disabled); + gpu_disabled = 1; + } + return ret; +} + +static int disable_pciea_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_pciea[] = { + "/soc/pcie@4c300000", + "/soc/pcie-ep@4c300000" + }; + + return delete_fdt_nodes(blob, nodes_path_pciea, ARRAY_SIZE(nodes_path_pciea)); +} + +static int disable_pcieb_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_pcieb[] = { + "/soc/pcie@4c380000", + "/soc/pcie-ep@4c380000" + }; + + return delete_fdt_nodes(blob, nodes_path_pcieb, ARRAY_SIZE(nodes_path_pcieb)); +} + +int disable_enet10g_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_enet10g[] = { + "/pcie@4ca00000/ethernet@10,0", + "/soc/pcie@4ca00000/ethernet@10,0", + "/soc/syscon@4ca00000/ethernet@10,0", + "/soc/netc-blk-ctrl@4cde0000/pcie@4ca00000/ethernet@10,0", + }; + + return disable_fdt_nodes(blob, nodes_path_enet10g, ARRAY_SIZE(nodes_path_enet10g), + NULL, NULL); +} + +int disable_enet25g_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_enet25g[] = { + "/soc/system-controller@4ceb0000/pcie@4ca00000/ethernet-switch@0,2/ports/port@0", + "/soc/system-controller@4ceb0000/pcie@4ca00000/ethernet-switch@0,2/ports/port@1", + }; + + return disable_fdt_nodes(blob, nodes_path_enet25g, ARRAY_SIZE(nodes_path_enet25g), + "phy-mode", "sgmii"); +} + +int disable_mipidsi_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_mipidsi[] = { + "/soc/dsi@4acf0000", + "/soc/syscon@4acf0000", + "/soc/dsi@4b060000", + "/soc/phy@4b110000", + }; + + return delete_fdt_nodes(blob, nodes_path_mipidsi, ARRAY_SIZE(nodes_path_mipidsi)); +} + +int disable_dpu_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_dpu[] = { + "/soc/bridge@4b0d0000/channel@0/port@0/endpoint", + "/soc/bridge@4b0d0000/channel@0/port@1/endpoint", + "/soc/bridge@4b0d0000/channel@1/port@0/endpoint", + "/soc/bridge@4b0d0000/channel@1/port@1/endpoint", + "/soc/display-controller@4b400000/ports/port@0/endpoint", + "/soc/display-controller@4b400000/ports/port@1/endpoint", + "/soc/display-controller@4b400000", + "/soc/syscon@4b010000/bridge@8/ports/port@0/endpoint", + "/soc/syscon@4b010000/bridge@8/ports/port@1/endpoint", + "/soc/syscon@4b010000/bridge@8/ports/port@2/endpoint@0", + "/soc/syscon@4b010000/bridge@8/ports/port@2/endpoint@1", + "/soc/syscon@4b010000/bridge@8/ports/port@3/endpoint@0", + "/soc/syscon@4b010000/bridge@8/ports/port@3/endpoint@1", + "/soc/syscon@4b010000/bridge@8", + "/soc/syscon@4b010000", + "/soc/syscon@4b0a0000", + "/soc/interrupt-controller@4b0b0000", + "/soc/bridge@4b0d0000" + }; + + return delete_fdt_nodes(blob, nodes_path_dpu, ARRAY_SIZE(nodes_path_dpu)); +} + +int disable_lvds_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_lvds[] = { + "/soc/syscon@4b0c0000/ldb@4/channel@0", + "/soc/syscon@4b0c0000/phy@8", + "/soc/syscon@4b0c0000/ldb@4/channel@1", + "/soc/syscon@4b0c0000/phy@c", + "/soc/syscon@4b0c0000" + }; + + return delete_fdt_nodes(blob, nodes_path_lvds, ARRAY_SIZE(nodes_path_lvds)); +} + +int disable_cm70_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_cm70[] = { + "/reserved-memory/vdev0vring0@82000000", + "/reserved-memory/vdev0vring1@82008000", + "/reserved-memory/vdev1vring0@82010000", + "/reserved-memory/vdev1vring1@82018000", + "/reserved-memory/rsc-table@82220000", + "/reserved-memory/vdevbuffer@82020000", + "/imx943-cm70", + }; + + return delete_fdt_nodes(blob, nodes_path_cm70, ARRAY_SIZE(nodes_path_cm70)); +} + +int disable_cm71_node(void *blob, u32 fuse_val) +{ + static const char * const nodes_path_cm71[] = { + "/reserved-memory/vdev0vring0@84000000", + "/reserved-memory/vdev0vring1@84008000", + "/reserved-memory/vdev1vring0@84010000", + "/reserved-memory/vdev1vring1@84018000", + "/reserved-memory/rsc-table@84220000", + "/reserved-memory/vdevbuffer@84020000", + "/imx943-cm71", + }; + + return delete_fdt_nodes(blob, nodes_path_cm71, ARRAY_SIZE(nodes_path_cm71)); +} + +/* There is order dependency between cpu->gpu->vpu */ +struct periph_fuse_info f17_grp[] = { + { BIT(30), MXC_CPU_IMX952, false, disable_ld_node }, +}; + +struct periph_fuse_info f18_grp[] = { + { BIT(0), 0, false, disable_npu_node }, + { GENMASK(6, 2), 0, false, disable_arm_cpu_nodes }, + { BIT(9), 0, true, disable_cm70_node }, + { BIT(17), MXC_CPU_IMX94, true, disable_cm71_node }, + { BIT(22), 0, true, disable_dpu_node }, + { BIT(27), 0, true, disable_lvds_node }, + { BIT(29), 0, false, disable_isp_node }, +}; + +struct periph_fuse_info f19_grp[] = { + { BIT(6), 0, true, disable_pciea_node }, + { BIT(7), 0, true, disable_pcieb_node }, + { BIT(17), 0, false, disable_gpu_node }, + { BIT(18), 0, false, disable_vpu_node }, + { BIT(19), 0, false, disable_jpegenc_node }, + { BIT(20), 0, false, disable_jpegdec_node }, + { BIT(22), 0, false, disable_mipicsi0_node }, + { BIT(23), 0, false, disable_mipicsi1_node }, + { BIT(24), 0, true, disable_mipidsi_node }, + { BIT(26), 0, false, disable_vpuenc_node }, + { BIT(27), 0, false, disable_vpuwave511_node }, +}; + +struct periph_fuse_info f20_grp[] = { + { BIT(12), MXC_CPU_IMX95, true, disable_enet10g_node }, + { BIT(12), MXC_CPU_IMX94, true, disable_enet25g_node }, +}; + +static void ft_disable_periph(void *blob, u32 fuse_bank, u32 fuse_word, + struct periph_fuse_info *info, u32 info_num, + bool board_fix_fdt) +{ + int i, ret; + u32 val = 0; + + ret = fuse_read(fuse_bank, fuse_word, &val); + if (ret) + return; + + for (i = 0; i < info_num; i++) { + if (val & info[i].bit_mask) { + if (board_fix_fdt && !info[i].of_board_fix) + continue; + + if (!info[i].soc_type || is_cpu_type(info[i].soc_type)) + info[i].disable_func(blob, val); + } + } +} + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + /* Common peripheral disable fuse process */ + ft_disable_periph(blob, 2, 1, f17_grp, ARRAY_SIZE(f17_grp), false); + ft_disable_periph(blob, 2, 2, f18_grp, ARRAY_SIZE(f18_grp), false); + ft_disable_periph(blob, 2, 3, f19_grp, ARRAY_SIZE(f19_grp), false); + ft_disable_periph(blob, 2, 4, f20_grp, ARRAY_SIZE(f20_grp), false); + + return 0; +} + +/* Fix uboot dtb based on fuses. */ +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) && !IS_ENABLED(CONFIG_XPL_BUILD) +int imx9_uboot_fixup_by_fuse(void *fdt) +{ + ft_disable_periph(fdt, 2, 2, f18_grp, ARRAY_SIZE(f18_grp), true); + ft_disable_periph(fdt, 2, 3, f19_grp, ARRAY_SIZE(f19_grp), true); + ft_disable_periph(fdt, 2, 4, f20_grp, ARRAY_SIZE(f20_grp), true); + + return 0; +} +#endif diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index fbee435786c..18d00355999 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP * * Peng Fan <[email protected]> */ @@ -186,8 +186,9 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) *minc = -40; *maxc = 105; } else if (val == TEMP_EXTCOMMERCIAL) { - *minc = -20; - *maxc = 105; + /* Map to Ext industrial */ + *minc = -40; + *maxc = 125; } else { *minc = 0; *maxc = 95; @@ -311,6 +312,13 @@ static struct mm_region imx9_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + /* QB data */ + .virt = CONFIG_QB_SAVED_STATE_BASE, + .phys = CONFIG_QB_SAVED_STATE_BASE, + .size = 0x200000UL, /* 2M */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE + }, { /* empty entry to split table entry 5 if needed when TEEs are used */ 0, }, { @@ -348,11 +356,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx9_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx9_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx9_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx9_mem_map[entry].phys = gd->dram[i].start; + imx9_mem_map[entry].virt = gd->dram[i].start; + imx9_mem_map[entry].size = gd->dram[i].size; imx9_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx9_mem_map[entry].phys, imx9_mem_map[entry].size); @@ -445,24 +453,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (rom_pointer[1] && PHYS_SDRAM < (phys_addr_t)rom_pointer[0]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -470,8 +478,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; @@ -507,6 +515,35 @@ phys_size_t get_effective_memsize(void) } } +static inline u64 ether_addr_to_u64(const u8 *addr) +{ + u64 u = 0; + int i; + + for (i = 0; i < 6; i++) + u = u << 8 | addr[i]; + + return u; +} + +static inline void u64_to_ether_addr(u64 u, u8 *addr) +{ + int i; + + for (i = 6 - 1; i >= 0; i--) { + addr[i] = u & 0xff; + u = u >> 8; + } +} + +static inline void eth_addr_add(u8 *addr, long offset) +{ + u64 u = ether_addr_to_u64(addr); + + u += offset; + u64_to_ether_addr(u, addr); +} + void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { u32 val[2] = {}; @@ -551,16 +588,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) * | 10 | netc switch | swp2 | */ if (dev_id == 0) - mac[5] = mac[5] + 2; /* enetc3 mac/swp0 */ + eth_addr_add(mac, 2); /* enetc3 mac/swp0 */ if (dev_id == 1) - mac[5] = mac[5] + 8; /* enetc1 */ + eth_addr_add(mac, 8); /* enetc1 */ if (dev_id == 2) - mac[5] = mac[5] + 9; /* enetc2 */ + eth_addr_add(mac, 9); /* enetc2 */ } else { if (dev_id == 1) - mac[5] = mac[5] + 3; + eth_addr_add(mac, 3); if (dev_id == 2) - mac[5] = mac[5] + 6; + eth_addr_add(mac, 6); } debug("%s: MAC%d: %pM\n", __func__, dev_id, mac); @@ -665,11 +702,11 @@ int get_reset_reason(bool sys, bool lm) } if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n", - rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], - out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, - out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON], + out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags) : -1, + out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags) : -1 ); } } @@ -696,11 +733,11 @@ int get_reset_reason(bool sys, bool lm) if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n", - rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], - out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, - out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON], + out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags) : -1, + out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags) : -1 ); } } @@ -708,14 +745,88 @@ int get_reset_reason(bool sys, bool lm) return 0; } -const char *get_imx_type(u32 imxtype) +const char *get_cpu_variant_type_name(u32 type) { - switch (imxtype) { - case SCMI_CPU: - return IMX_PLAT_STR; - default: - return "??"; + u32 val, core_num, part_num; + int ret; + + ret = fuse_read(2, 1, &val); + if (ret) + return NULL; + + /* Get part num */ + part_num = (val >> 4) & 0xff; + if (!part_num) + return NULL; + + if (type == MXC_CPU_IMX95 || type == MXC_CPU_IMX952) { + u32 segment; + static char name[8] = "95294"; + char pn[2]; + + core_num = part_num & 0x3; + segment = (part_num >> 2) & 0xf; + + switch (segment) { + case 0xa: + pn[0] = 'T'; + break; + case 0xb: + pn[0] = 'V'; + break; + case 0xc: + pn[0] = 'C'; + break; + case 0xd: + pn[0] = 'G'; + break; + case 0xe: + pn[0] = 'I'; + break; + case 0xf: + pn[0] = 'N'; + break; + default: + pn[0] = segment + '0'; + break; + } + + pn[1] = core_num * 2 + '0'; + + if (type == MXC_CPU_IMX95) + sprintf(name, "95%c%c", pn[0], pn[1]); + else + sprintf(name, "952%c%c", pn[0], pn[1]); + + return name; + } else if (type == MXC_CPU_IMX94) { + static char *name = "94398"; + + core_num = 8; + + ret = fuse_read(2, 2, &val); + if (ret) + return NULL; + + if (part_num > 30) { /* 943 */ + /* A55 2 & 3 disabled */ + if ((val & 0x18) == 0x18) + core_num = 6; + } else if (part_num > 20) { /* 942 */ + core_num = 5; + + /* m7_0 disabled */ + if ((val & 0x200) == 0x200) + core_num = 4; + } else if (part_num > 10) { /* 941 */ + core_num = 5; + } + sprintf(name, "94%u%u", part_num, core_num); + + return name; } + + return NULL; } void build_info(void) @@ -745,21 +856,49 @@ void build_info(void) puts("\n"); } -int arch_misc_init(void) +int scmi_get_boot_device_offset(unsigned long *img_off) { - build_info(); + int ret; + rom_passover_t rom_data = {0}; + + ret = scmi_get_rom_data(&rom_data); + if (!ret) + *img_off = rom_data.img_ofs; + return 0; } -#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_SPL_BUILD) -int board_fix_fdt(void *fdt) +int scmi_get_boot_stage(u8 *stage) { + int ret; + rom_passover_t rom_data = {0}; + + ret = scmi_get_rom_data(&rom_data); + if (!ret) + *stage = rom_data.boot_stage; + + return ret; +} + +u8 scmi_get_imgset_sel(void) +{ + rom_passover_t rdata = { 0 }; + int ret = scmi_get_rom_data(&rdata); + + if (!ret) + return rdata.img_set_sel; + return 0; } -#endif -int ft_system_setup(void *blob, struct bd_info *bd) +int boot_mode_getprisec(void) +{ + return !!scmi_get_imgset_sel(); +} + +int arch_misc_init(void) { + build_info(); return 0; } @@ -786,9 +925,16 @@ static void gpio_reset(ulong gpio_base) int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { - if (!IS_ENABLED(CONFIG_IMX952)) { - disable_wdog((void __iomem *)WDG3_BASE_ADDR); - disable_wdog((void __iomem *)WDG4_BASE_ADDR); + ofnode node; + + ofnode_for_each_compatible_node(node, "fsl,imx93-wdt") { + phys_addr_t base; + + base = ofnode_get_addr(node); + if (base == FDT_ADDR_T_NONE) + continue; + + disable_wdog((void __iomem *)base); } gpio_reset(GPIO2_BASE_ADDR); @@ -985,10 +1131,11 @@ enum boot_device get_boot_device(void) bool arch_check_dst_in_secure(void *start, ulong size) { - ulong ns_end = CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE; -#ifdef PHYS_SDRAM_2_SIZE - ns_end += PHYS_SDRAM_2_SIZE; -#endif + ulong ns_end; + phys_size_t dram_size; + + board_phys_sdram_size(&dram_size); + ns_end = CFG_SYS_SDRAM_BASE + dram_size; if ((ulong)start < CFG_SYS_SDRAM_BASE || (ulong)start + size > ns_end) return true; @@ -998,5 +1145,10 @@ bool arch_check_dst_in_secure(void *start, ulong size) void *arch_get_container_trampoline(void) { - return (void *)((ulong)CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE - SZ_16M); + phys_size_t size; + + board_phys_sdram_size(&size); + size = (size > PHYS_SDRAM_SIZE) ? PHYS_SDRAM_SIZE : size; + + return (void *)((ulong)CFG_SYS_SDRAM_BASE + size - SZ_16M); } diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 44b3e0f5310..dcf2fff1aa6 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -21,6 +21,7 @@ #include <asm/armv8/mmu.h> #include <dm/device.h> #include <dm/device_compat.h> +#include <dm/ofnode.h> #include <dm/uclass.h> #include <env.h> #include <env_internal.h> @@ -198,26 +199,15 @@ static u32 get_cpu_variant_type(u32 type) bool npu_disable = !!(val & BIT(13)); bool core1_disable = !!(val & BIT(15)); u32 pack_9x9_fused = BIT(4) | BIT(5) | BIT(17) | BIT(19) | BIT(24); - u32 nxp_recog = (val & GENMASK(23, 16)) >> 16; + u32 speed = (val & GENMASK(11, 6)) >> 6; /* For iMX91 */ if (type == MXC_CPU_IMX91) { - switch (nxp_recog) { - case 0x9: - case 0xA: + if ((val2 & pack_9x9_fused) == pack_9x9_fused) type = MXC_CPU_IMX9111; - break; - case 0xD: - case 0xE: - type = MXC_CPU_IMX9121; - break; - case 0xF: - case 0x10: - type = MXC_CPU_IMX9101; - break; - default: - break; /* 9131 as default */ - } + + if (speed == 0xf) /* 800Mhz arm */ + type += 1; return type; } @@ -281,9 +271,17 @@ static void disable_wdog(void __iomem *wdog_base) void init_wdog(void) { - disable_wdog((void __iomem *)WDG3_BASE_ADDR); - disable_wdog((void __iomem *)WDG4_BASE_ADDR); - disable_wdog((void __iomem *)WDG5_BASE_ADDR); + ofnode node; + + ofnode_for_each_compatible_node(node, "fsl,imx93-wdt") { + phys_addr_t base; + + base = ofnode_get_addr(node); + if (base == FDT_ADDR_T_NONE) + continue; + + disable_wdog((void __iomem *)base); + } } static struct mm_region imx93_mem_map[] = { @@ -370,11 +368,11 @@ void enable_caches(void) while (i < CONFIG_NR_DRAM_BANKS && entry < ARRAY_SIZE(imx93_mem_map)) { - if (gd->bd->bi_dram[i].start == 0) + if (gd->dram[i].start == 0) break; - imx93_mem_map[entry].phys = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].virt = gd->bd->bi_dram[i].start; - imx93_mem_map[entry].size = gd->bd->bi_dram[i].size; + imx93_mem_map[entry].phys = gd->dram[i].start; + imx93_mem_map[entry].virt = gd->dram[i].start; + imx93_mem_map[entry].size = gd->dram[i].size; imx93_mem_map[entry].attrs = attrs; debug("Added memory mapping (%d): %llx %llx\n", entry, imx93_mem_map[entry].phys, imx93_mem_map[entry].size); @@ -448,24 +446,24 @@ int dram_init_banksize(void) sdram_b2_size = 0; } - gd->bd->bi_dram[bank].start = PHYS_SDRAM; + gd->dram[bank].start = PHYS_SDRAM; if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) { phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; phys_size_t optee_size = (size_t)rom_pointer[1]; - gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; + gd->dram[bank].size = optee_start - gd->dram[bank].start; if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) { if (++bank >= CONFIG_NR_DRAM_BANKS) { puts("CONFIG_NR_DRAM_BANKS is not enough\n"); return -1; } - gd->bd->bi_dram[bank].start = optee_start + optee_size; - gd->bd->bi_dram[bank].size = PHYS_SDRAM + - sdram_b1_size - gd->bd->bi_dram[bank].start; + gd->dram[bank].start = optee_start + optee_size; + gd->dram[bank].size = PHYS_SDRAM + + sdram_b1_size - gd->dram[bank].start; } } else { - gd->bd->bi_dram[bank].size = sdram_b1_size; + gd->dram[bank].size = sdram_b1_size; } if (sdram_b2_size) { @@ -473,8 +471,8 @@ int dram_init_banksize(void) puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n"); return -1; } - gd->bd->bi_dram[bank].start = 0x100000000UL; - gd->bd->bi_dram[bank].size = sdram_b2_size; + gd->dram[bank].start = 0x100000000UL; + gd->dram[bank].size = sdram_b2_size; } return 0; @@ -741,13 +739,16 @@ int arch_cpu_init(void) int imx9_probe_mu(void) { struct udevice *devp; - int node, ret; + ofnode node; + int ret; u32 res; struct ele_get_info_data info; - node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4"); + node = ofnode_by_compatible(ofnode_null(), "fsl,imx93-mu-s4"); + if (!ofnode_valid(node)) + return -ENODEV; - ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); + ret = uclass_get_device_by_ofnode(UCLASS_MISC, node, &devp); if (ret) return ret; diff --git a/arch/arm/mach-imx/mx5/mx53_dram.c b/arch/arm/mach-imx/mx5/mx53_dram.c index 180a745d435..5f7709e00b0 100644 --- a/arch/arm/mach-imx/mx5/mx53_dram.c +++ b/arch/arm/mach-imx/mx5/mx53_dram.c @@ -35,11 +35,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); return 0; } diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index d198d9932f4..a38adfed02b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -95,10 +95,10 @@ config MX6_OCRAM_256KB bool "Support 256KB OCRAM" depends on MX6D || MX6Q help - Allows using the full 256KB size of the OCRAM on the MX6Q/MX6D series - of chips, such as for SPL. The OCRAM of the Lite series of chips is - only 128KB, so using this option will prevent the resulting code from - working on those chips. + Allows using the full 256KB size of the OCRAM on the MX6Q/MX6D series + of chips, such as for SPL. The OCRAM of the Lite series of chips is + only 128KB, so using this option will prevent the resulting code from + working on those chips. config MX6_DDRCAL bool "Include dynamic DDR calibration routines" @@ -633,6 +633,26 @@ config TARGET_TQMA6 imply CMD_SF imply CMD_DM +config TARGET_TQMA6UL + bool "TQ-Systems TQMa6UL[L]x" + depends on MX6UL || MX6ULL + select TQ_COMMON_SOM + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select OF_SYSTEM_SETUP + select DM + select DM_I2C + select SUPPORT_SPL + select SPL_SEPARATE_BSS if SPL + imply DM_GPIO + imply DM_MMC + imply DM_SPI if SPI + imply DM_SPI_FLASH if SPI + imply SPI + help + TQMa6UL[L]x is a TQ SoM with i.MX6UL/i.MX6ULL CPU + The SoM can be used on various baseboards. + config TARGET_UDOO bool "udoo" depends on MX6QDL @@ -678,10 +698,10 @@ config TARGET_BRPPT2 select SUPPORT_SPL select SPL_DM if SPL select SPL_OF_CONTROL if SPL - help - Support - B&R BRPPT2 platform - based on Freescale's iMX6 SoC + help + Support + B&R BRPPT2 platform + based on Freescale's iMX6 SoC config TARGET_O4_IMX6ULL_NANO bool "O4-iMX6ULL-NANO" @@ -739,6 +759,7 @@ source "board/technexion/pico-imx6/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tq/tqma6/Kconfig" +source "board/tq/tqma6ul/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" source "board/toradex/colibri-imx6ull/Kconfig" diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index b5aa606b8d0..d366180e788 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1452,7 +1452,7 @@ static void enable_ldb_di_clock_sources(void) * Try call this function as early in the boot process as possible since the * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5. */ -void select_ldb_di_clock_source(enum ldb_di_clock clk) +void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; @@ -1525,8 +1525,8 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk) reg = readl(&mxc_ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK); - reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) - | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); + reg |= ((clk0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (clk1 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)); writel(reg, &mxc_ccm->cs2cdr); /* Unbypass pll3_sw_clk */ diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index 8b23d48a854..2ad9499ef46 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -12,6 +12,54 @@ static struct fuse_entry_desc mx6_fuse_descs[] = { #if defined(CONFIG_MX6ULL) + {MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22}, + {MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22}, + {MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23}, + {MODULE_EPDC, "/soc/bus@2200000/epdc@228c000", 0x430, 24}, + {MODULE_ESAI, "/soc/bus@2000000/spba-bus@2000000/esai@2024000", 0x430, 25}, + {MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26}, + {MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27}, + {MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2}, + {MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3}, + {MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3}, + {MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4}, + {MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4}, + {MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5}, + {MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5}, + {MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6}, + {MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6}, + {MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7}, + {MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8}, + {MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9}, + {MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10}, + {MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11}, + {MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12}, + {MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13}, + {MODULE_DCP, "/soc/bus@2200000/dcp@2280000", 0x440, 14}, + {MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15}, + {MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24}, + {MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24}, + {MODULE_DCP_CRYPTO, "/soc/bus@2200000/dcp@2280000", 0x440, 25}, + {MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26}, + {MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26}, + {MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26}, + {MODULE_UART8, "/soc/bus@2200000/serial@2288000", 0x440, 26}, + {MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27}, + {MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27}, + {MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27}, + {MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28}, + {MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29}, + {MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29}, + {MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30}, + {MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30}, + {MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31}, + {MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22}, {MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23}, {MODULE_EPDC, "/soc/aips-bus@2200000/epdc@228c000", 0x430, 24}, @@ -90,6 +138,55 @@ static struct fuse_entry_desc mx6_fuse_descs[] = { {MODULE_GPT2, "/soc/aips-bus@02000000/gpt@020e8000", 0x440, 30}, {MODULE_EPIT2, "/soc/aips-bus@02000000/epit@020d4000", 0x440, 31}, #elif defined(CONFIG_MX6UL) + {MODULE_TSC, "/soc/bus@2000000/touchscreen@2040000", 0x430, 22}, + {MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22}, + {MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23}, + {MODULE_SIM1, "/soc/bus@2100000/sim@218c000", 0x430, 24}, + {MODULE_SIM2, "/soc/bus@2100000/sim@21b4000", 0x430, 25}, + {MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26}, + {MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27}, + {MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2}, + {MODULE_EIM, "/soc/bus@2100000/memory-controller@21b8000", 0x440, 3}, + {MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3}, + {MODULE_SD1, "/soc/bus@2100000/mmc@2190000", 0x440, 4}, + {MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4}, + {MODULE_SD2, "/soc/bus@2100000/mmc@2194000", 0x440, 5}, + {MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5}, + {MODULE_QSPI1, "/soc/bus@2100000/spi@21e0000", 0x440, 6}, + {MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6}, + {MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-controller@1804000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7}, + {MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8}, + {MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9}, + {MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10}, + {MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11}, + {MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12}, + {MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13}, + {MODULE_CAAM, "/soc/bus@2100000/crypto@2140000", 0x440, 14}, + {MODULE_CAAM, "/soc/bus@2100000/caam@2140000", 0x440, 14}, + {MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15}, + {MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24}, + {MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24}, + {MODULE_BEE, "/soc/bus@2000000/bee@2044000", 0x440, 25}, + {MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26}, + {MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26}, + {MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26}, + {MODULE_UART8, "/soc/bus@2000000/spba-bus@2000000/serial@2024000", 0x440, 26}, + {MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27}, + {MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27}, + {MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27}, + {MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/spi@2010000", 0x440, 28}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/spi@2014000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28}, + {MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29}, + {MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29}, + {MODULE_GPT2, "/soc/bus@2000000/timer@20e8000", 0x440, 30}, + {MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30}, + {MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31}, + {MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22}, {MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23}, {MODULE_SIM1, "/soc/aips-bus@2100000/sim@218c000", 0x430, 24}, diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index f576ee650f0..597eca142af 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -90,6 +90,21 @@ config TARGET_COLIBRI_IMX7 select MX7D imply CMD_DM +config TARGET_TQMA7 + bool "TQ-Systems TQMa7x SoM" + select BOARD_LATE_INIT + select SUPPORT_SPL + select SPL_SEPARATE_BSS if SPL + select DM + select DM_SERIAL + select MX7 + imply MX7D + imply CMD_DM + imply DM_THERMAL + help + TQMa7x is a TQ SoM with i.MX7 CPU + The SoM can be used on various baseboards. + endchoice config SYS_SOC @@ -102,6 +117,7 @@ source "board/novtech/meerkat96/Kconfig" source "board/storopack/smegw01/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" +source "board/tq/tqma7/Kconfig" source "board/warp7/Kconfig" endif diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index e8cb58bc89f..eac3a2ad6af 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -35,6 +35,7 @@ config TARGET_MX7ULP_COM select SPL_SEPARATE_BSS if SPL select SPL_SERIAL if SPL select SUPPORT_SPL + imply OF_UPSTREAM config TARGET_MX7ULP_EVK bool "Support mx7ulp EVK board" @@ -42,6 +43,7 @@ config TARGET_MX7ULP_EVK select SYS_ARCH_TIMER select FSL_CAAM select ARCH_MISC_INIT + imply OF_UPSTREAM endchoice diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 5306e76223f..1dd350cf50e 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -83,8 +83,12 @@ enum bt_mode get_boot_mode(void) return LOW_POWER_BOOT; } +static void init_wdog(void); int arch_cpu_init(void) { + /* Disable wdog */ + init_wdog(); + enable_ca7_smp(); return 0; } @@ -146,7 +150,7 @@ static void disable_wdog(u32 wdog_base) while (!(readl(wdog_base + 0x00) & 0x400)); } -void init_wdog(void) +static void init_wdog(void) { /* * ROM will configure WDOG1, disable it or enable it @@ -161,8 +165,17 @@ void init_wdog(void) * In this function, we will disable both WDOG1 and WDOG2, * and set update bit for both. So that kernel can reconfigure them. */ - disable_wdog(WDG1_RBASE); - disable_wdog(WDG2_RBASE); + ofnode node; + + ofnode_for_each_compatible_node(node, "fsl,imx7ulp-wdt") { + phys_addr_t base; + + base = ofnode_get_addr(node); + if (base == FDT_ADDR_T_NONE) + continue; + + disable_wdog((u32)base); + } } static bool ldo_mode_is_enabled(void) @@ -221,9 +234,6 @@ static void init_ldo_mode(void) void s_init(void) { - /* Disable wdog */ - init_wdog(); - /* clock configuration. */ clock_init(); @@ -249,11 +259,6 @@ void reset_cpu(void) #endif #if defined(CONFIG_DISPLAY_CPUINFO) -const char *get_imx_type(u32 imxtype) -{ - return "7ULP"; -} - int print_cpuinfo(void) { u32 cpurev; @@ -261,8 +266,7 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), + printf("CPU: Freescale i.MX7ULP rev%d.%d at %d MHz\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c index 65924483bc8..c22435c1676 100644 --- a/arch/arm/mach-imx/priblob.c +++ b/arch/arm/mach-imx/priblob.c @@ -10,6 +10,7 @@ * to decrypt an encrypted boot image. */ +#include <config.h> #include <asm/io.h> #include <command.h> #include <fsl_sec.h> diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 57ae81c7834..1029c1e4e85 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -375,8 +375,8 @@ void *spl_load_simple_fit_fix_load(const void *fit) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = imx_ddr_size(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = imx_ddr_size(); return 0; } diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index a15adf1cb1e..94c006aa350 100644 --- a/arch/arm/mach-k3/am64x/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -212,14 +212,14 @@ void board_init_f(ulong dummy) #if defined(CONFIG_K3_LOAD_SYSFW) /* - * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue + * Process pinctrl for serial1 a.k.a. MAIN UART1 module and continue * regardless of the result of pinctrl. Do this without probing the * device, but instead by searching the device that would request the * given sequence number if probed. The UART will be used by the system * firmware (SYSFW) image for various purposes and SYSFW depends on us * to initialize its pin settings. */ - ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev); + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 1, &dev); if (!ret) pinctrl_select_state(dev, "default"); @@ -255,6 +255,8 @@ void board_init_f(ulong dummy) if (rst_src == COLD_BOOT || rst_src & (SW_POR_MCU | SW_POR_MAIN)) { printf("Resetting on cold boot to workaround ErrataID:i2331\n"); printf("Please resend tiboot3.bin in case of UART/DFU boot\n"); + /* clear MCU_RST_SRC register before reset */ + writel(0xFFFFFFFF, CTRLMMR_MCU_RST_SRC); do_reset(NULL, 0, 0, NULL); } #endif diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index b0a75988714..6e382efdb3b 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -191,6 +191,33 @@ enum k3_device_type get_device_type(void) } } +int k3_fit_config_match_security_state(const char *name) +{ + const char *suffix; + size_t name_len, suffix_len; + + switch (get_device_type()) { + case K3_DEVICE_TYPE_HS_SE: + suffix = "-hs-se"; + break; + case K3_DEVICE_TYPE_HS_FS: + suffix = "-hs-fs"; + break; + case K3_DEVICE_TYPE_GP: + suffix = "-gp"; + break; + default: + return -EINVAL; + } + + name_len = strlen(name); + suffix_len = strlen(suffix); + if (name_len < suffix_len) + return -EINVAL; + + return strncmp(name + name_len - suffix_len, suffix, suffix_len); +} + #if defined(CONFIG_DISPLAY_CPUINFO) static const char *get_device_type_name(void) { @@ -294,6 +321,7 @@ void enable_caches(void) __func__, ret); } + mmu_enable(); icache_enable(); dcache_enable(); } diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 466ad22f895..37ff98d8992 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -32,15 +32,6 @@ enum k3_firewall_region_type { K3_FIREWALL_REGION_BACKGROUND }; -enum k3_device_type { - K3_DEVICE_TYPE_BAD, - K3_DEVICE_TYPE_GP, - K3_DEVICE_TYPE_TEST, - K3_DEVICE_TYPE_EMU, - K3_DEVICE_TYPE_HS_FS, - K3_DEVICE_TYPE_HS_SE, -}; - void setup_k3_mpu_regions(void); int early_console_init(void); void disable_linefill_optimization(void); @@ -55,7 +46,6 @@ const struct k3_speed_grade_map *k3_get_speed_grade_map(void); void k3_fix_rproc_clock(const char *path); void mmr_unlock(uintptr_t base, u32 partition); bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data); -enum k3_device_type get_device_type(void); struct ti_sci_handle *get_ti_sci_handle(void); void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 81b5f1fa45e..2c771a1195f 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -124,6 +124,27 @@ struct rom_extended_boot_data { u32 num_components; }; +enum k3_device_type { + K3_DEVICE_TYPE_BAD, + K3_DEVICE_TYPE_GP, + K3_DEVICE_TYPE_TEST, + K3_DEVICE_TYPE_EMU, + K3_DEVICE_TYPE_HS_FS, + K3_DEVICE_TYPE_HS_SE, +}; + u32 get_boot_device(void); const char *get_reset_reason(void); +enum k3_device_type get_device_type(void); +int k3_fit_config_match_security_state(const char *name); + +#define writel_verify(val, addr) \ +do { \ + u32 readback; \ + writel(val, addr); \ + readback = readl(addr); \ + if (readback != val) \ + printf("writel_verify failed: addr=0x%p, expected=0x%x, got=0x%x\n", \ + (void *)(addr), (val), readback); \ +} while (0) #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/j721s2/j721s2_init.c b/arch/arm/mach-k3/j721s2/j721s2_init.c index b5453d8895d..780d853423f 100644 --- a/arch/arm/mach-k3/j721s2/j721s2_init.c +++ b/arch/arm/mach-k3/j721s2/j721s2_init.c @@ -40,6 +40,15 @@ #define NB_THREADMAP_BIT1 BIT(1) #define NB_THREADMAP_BIT2 BIT(2) +/* + * RAT mapping for errata ID: i2437 + */ +#define RAT_ERRATA_2437_BASE_REGION0 0x40f90000 +#define RAT_ERRATA_2437_IN_ADDR 0xc0000000 +#define RAT_ERRATA_2437_OUT_ADDR_U 0x0000004d +#define RAT_ERRATA_2437_OUT_ADDR_L 0x21000000 +#define RAT_ERRATA_2437_CTRL 0x80000010 + struct fwl_data cbass_hc_cfg0_fwls[] = { { "PCIE0_CFG", 2577, 7 }, { "EMMC8SS0_CFG", 2579, 4 }, @@ -346,6 +355,36 @@ void board_init_f(ulong dummy) if (ret) printf("AVS init failed: %d\n", ret); } + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * Errata ID i2437: SE Clock-Gating Turning Off Too Early + * + * A hardware bug is present in the C7120 Streaming Engine top level + * clock gating logic that can lead to the C7120 CPU hanging. + + * Workaround: The DSP_<COREID>_DEBUG_CLKEN_OVERRIDE fields of the + * COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register (where COREID is the + * name of the specific C7120 core) must be enabled before power-up + * of the C7120 core to override all clock-gating. + */ + + /* Setup RAT mapping */ + debug("Errata i2437: Use RAT for COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register\n"); + writel_verify(RAT_ERRATA_2437_IN_ADDR, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_L, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_U, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + writel_verify(RAT_ERRATA_2437_CTRL, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + + /* Enable DSP_X_DEBUG_CLKEN_OVERRIDE for C71x cores */ + writel_verify(0x300, RAT_ERRATA_2437_IN_ADDR + 0x200); + + /* Clear RAT mapping */ + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + } } #endif diff --git a/arch/arm/mach-k3/j784s4/Kconfig b/arch/arm/mach-k3/j784s4/Kconfig index fff44dbf7c9..f5447b0b836 100644 --- a/arch/arm/mach-k3/j784s4/Kconfig +++ b/arch/arm/mach-k3/j784s4/Kconfig @@ -14,6 +14,7 @@ config TARGET_AQUILA_AM69_A72 select ARM64 select SYS_DISABLE_DCACHE_OPS select BINMAN + imply OF_UPSTREAM config TARGET_AQUILA_AM69_R5 bool "Toradex Aquila AM69 running on R5" diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 53f152ccd9c..507b7ab685a 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -45,6 +45,15 @@ #define NB_THREADMAP_BIT1 BIT(1) #define NB_THREADMAP_BIT2 BIT(2) +/* + * RAT mapping for errata ID: i2437 + */ +#define RAT_ERRATA_2437_BASE_REGION0 0x40f90000 +#define RAT_ERRATA_2437_IN_ADDR 0xc0000000 +#define RAT_ERRATA_2437_OUT_ADDR_U 0x0000004d +#define RAT_ERRATA_2437_OUT_ADDR_L 0x21000000 +#define RAT_ERRATA_2437_CTRL 0x80000010 + struct fwl_data infra_cbass0_fwls[] = { { "PSC0", 5, 1 }, { "PLL_CTRL0", 6, 1 }, @@ -322,6 +331,36 @@ void board_init_f(ulong dummy) setup_navss_nb(); setup_qos(); + + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * Errata ID i2437 SE Clock-Gating Turning Off Too Early + * + * A hardware bug is present in the C7120 Streaming Engine top level + * clock gating logic that can lead to the C7120 CPU hanging. + + * Workaround: The DSP_<COREID>_DEBUG_CLKEN_OVERRIDE fields of the + * COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register (where COREID is the + * name of the specific C7120 core) must be enabled before power-up + * of the C7120 core to override all clock-gating. + */ + + /* Setup RAT mapping */ + debug("Errata i2437: Use RAT for COMPUTE_CLUSTER_CFG_WRAP_0_CC_CNTRL register\n"); + writel_verify(RAT_ERRATA_2437_IN_ADDR, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_L, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(RAT_ERRATA_2437_OUT_ADDR_U, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + writel_verify(RAT_ERRATA_2437_CTRL, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + + /* Enable DSP_X_DEBUG_CLKEN_OVERRIDE for C71x cores */ + writel_verify(0xF00, RAT_ERRATA_2437_IN_ADDR + 0x200); + + /* Clear RAT mapping */ + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x20); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x24); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x28); + writel_verify(0, RAT_ERRATA_2437_BASE_REGION0 + 0x2c); + } } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/k3-ddr.c b/arch/arm/mach-k3/k3-ddr.c index 6e3e60cdc86..35c30b1a16f 100644 --- a/arch/arm/mach-k3/k3-ddr.c +++ b/arch/arm/mach-k3/k3-ddr.c @@ -59,8 +59,8 @@ void fixup_memory_node(struct spl_image_info *spl_image) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 484d96f9536..13736ca5dbc 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -348,19 +348,7 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, } if (i < IMAGE_AMT && i > IMAGE_ID_DM_FW) { - int device_type = get_device_type(); - - if ((device_type == K3_DEVICE_TYPE_HS_SE && - strcmp(os, "tifsstub-hs")) || - (device_type == K3_DEVICE_TYPE_HS_FS && - strcmp(os, "tifsstub-fs")) || - (device_type == K3_DEVICE_TYPE_GP && - strcmp(os, "tifsstub-gp"))) { - *p_size = 0; - } else { - debug("tifsstub-type: %s\n", os); - } - + debug("tifsstub-type: %s\n", os); return; } diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 9bf71a9b453..82efc9f7c40 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -18,9 +18,9 @@ config TARGET_K2L_EVM config TARGET_K2G_EVM bool "TI Keystone 2 Galileo EVM" - select BOARD_LATE_INIT + select BOARD_LATE_INIT select SOC_K2G - select TI_I2C_BOARD_DETECT + select TI_I2C_BOARD_DETECT endchoice diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index f1ccedba5d7..8d56ca1a6e3 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -22,13 +22,13 @@ config KIRKWOOD_COMMON select SYS_NS16550 config HAS_CUSTOM_SYS_INIT_SP_ADDR - bool "Use a custom location for the initial stack pointer address" - default y + bool "Use a custom location for the initial stack pointer address" + default y config CUSTOM_SYS_INIT_SP_ADDR - hex "Static location for the initial stack pointer" - depends on HAS_CUSTOM_SYS_INIT_SP_ADDR - default 0x5ff000 + hex "Static location for the initial stack pointer" + depends on HAS_CUSTOM_SYS_INIT_SP_ADDR + default 0x5ff000 choice prompt "Marvell Kirkwood board select" diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index a432abe615d..af59d63811c 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -99,16 +99,16 @@ static void kw_sysrst_action(void) if (!s) { debug("Error.. %s failed, check sysrstcmd\n", - __FUNCTION__); + __func__); return; } - debug("Starting %s process...\n", __FUNCTION__); + debug("Starting %s process...\n", __func__); ret = run_command(s, 0); if (ret != 0) - debug("Error.. %s failed\n", __FUNCTION__); + debug("Error.. %s failed\n", __func__); else - debug("%s process finished\n", __FUNCTION__); + debug("%s process finished\n", __func__); } static void kw_sysrst_check(void) @@ -152,7 +152,7 @@ int print_cpuinfo(void) u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { - printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid); + printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __func__, devid); return -1; } diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index b5b06f4e5b2..5e6c50ca64d 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -45,7 +45,7 @@ config TARGET_MT7981 help The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53. including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C, - built-in Wi-Fi, and PCIe. + built-in Wi-Fi, and PCIe. config TARGET_MT7986 bool "MediaTek MT7986 SoC" @@ -89,9 +89,9 @@ config TARGET_MT8188 select ARM64 help The MediaTek MT8188 is a ARM64-based SoC with a dual-core Cortex-A78 - cluster and a six-core Cortex-A55 cluster. It includes UART, SPI, - USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and - several LPDDR3 and LPDDR4 options. + cluster and a six-core Cortex-A55 cluster. It includes UART, SPI, + USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and + several LPDDR3 and LPDDR4 options. config TARGET_MT8189 bool "MediaTek MT8189 SoC" @@ -120,13 +120,13 @@ config TARGET_MT8365 I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. config TARGET_MT8512 - bool "MediaTek MT8512 SoC" - select ARM64 - help - The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53. - including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, - IR RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth digital - and several LPDDR3 and LPDDR4 options. + bool "MediaTek MT8512 SoC" + select ARM64 + help + The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + IR RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth digital + and several LPDDR3 and LPDDR4 options. config TARGET_MT8516 bool "MediaTek MT8516 SoC" @@ -154,7 +154,7 @@ config MTK_MEM_MAP_DDR_BASE_PHY hex "DDR physical base address" default 0x40000000 help - Target-specific DDR physical base address. + Target-specific DDR physical base address. config MTK_MEM_MAP_DDR_SIZE hex "DDR .size in mem_map" @@ -164,14 +164,14 @@ config MTK_MEM_MAP_DDR_SIZE default 0x40000000 if TARGET_MT7622 || TARGET_MT8512 default 0x20000000 help - Target-specific DDR region size in mem_map. + Target-specific DDR region size in mem_map. config MTK_MEM_MAP_MMIO_SIZE hex "MMIO .size in mem_map" default 0x40000000 if TARGET_MT7622 || TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8512 default 0x20000000 help - Target-specific MMIO region size in mem_map. + Target-specific MMIO region size in mem_map. endif @@ -195,13 +195,10 @@ config SYS_BOARD be used. config SYS_CONFIG_NAME - default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 - default "mt7987" if TARGET_MT7987 - default "mt7988" if TARGET_MT7988 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 7f4d934bfe9..5b37a91cd72 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -6,6 +6,7 @@ #include <fdtdec.h> #include <init.h> +#include <linux/kernel.h> #include <linux/sizes.h> #include <asm/armv8/mmu.h> #include <asm/global_data.h> @@ -26,6 +27,15 @@ int dram_init(void) return 0; } +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + /* + * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like + * MMC requires DMA buffer allocated below SZ_4G. + */ + return min(gd->ram_top, SZ_4G); +} + void reset_cpu(ulong addr) { psci_system_reset(); diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c index a48a41f3b97..1108bc19373 100644 --- a/arch/arm/mach-mediatek/mt8188/init.c +++ b/arch/arm/mach-mediatek/mt8188/init.c @@ -20,13 +20,13 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -phys_size_t get_effective_memsize(void) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like * MMC requires DMA buffer allocated below SZ_4G. */ - return min(SZ_4G - gd->ram_base, gd->ram_size); + return min(gd->ram_top, SZ_4G); } void reset_cpu(void) diff --git a/arch/arm/mach-mediatek/mt8189/init.c b/arch/arm/mach-mediatek/mt8189/init.c index ec7587c3586..4435c75a656 100644 --- a/arch/arm/mach-mediatek/mt8189/init.c +++ b/arch/arm/mach-mediatek/mt8189/init.c @@ -20,13 +20,13 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -phys_size_t get_effective_memsize(void) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like * MMC requires DMA buffer allocated below SZ_4G. */ - return min(SZ_4G - gd->ram_base, gd->ram_size); + return min(gd->ram_top, SZ_4G); } void reset_cpu(ulong addr) diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c index e31d4eec0fb..83cac9d01d6 100644 --- a/arch/arm/mach-mediatek/mt8195/init.c +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -20,13 +20,13 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -phys_size_t get_effective_memsize(void) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like * MMC requires DMA buffer allocated below SZ_4G. */ - return min(SZ_4G - gd->ram_base, gd->ram_size); + return min(gd->ram_top, SZ_4G); } int mtk_soc_early_init(void) diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index bc1d515fcca..6a9ae776794 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -29,10 +29,10 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -phys_size_t get_effective_memsize(void) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* limit stack below tee reserve memory */ - return gd->ram_size - 6 * SZ_1M; + return gd->ram_base + gd->ram_size - 6 * SZ_1M; } void reset_cpu(void) diff --git a/arch/arm/mach-mediatek/tzcfg.c b/arch/arm/mach-mediatek/tzcfg.c index c8fe8ac0e9b..fbc96d96a4b 100644 --- a/arch/arm/mach-mediatek/tzcfg.c +++ b/arch/arm/mach-mediatek/tzcfg.c @@ -35,12 +35,13 @@ struct tz_reserved_region { }; static bool fix_tz_region(struct tz_reserved_region region[], - uint32_t used_regions) + uint32_t used_regions, + phys_addr_t ram_top) { phys_addr_t size; - if (region[0].addr + region[0].size > gd->ram_top) { - if (region[0].addr >= gd->ram_top) { + if (region[0].addr + region[0].size > ram_top) { + if (region[0].addr >= ram_top) { debug("Discarded region 0x%08llx, size 0x%llx\n", region[0].addr, region[0].size); @@ -50,7 +51,7 @@ static bool fix_tz_region(struct tz_reserved_region region[], return true; } - size = gd->ram_top - region[0].addr; + size = ram_top - region[0].addr; debug("Truncated region 0x%08llx, size 0x%llx -> 0x%llx\n", region[0].addr, region[0].size, size); @@ -63,12 +64,15 @@ static bool fix_tz_region(struct tz_reserved_region region[], phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { - phys_addr_t uboot_ram_top, pstore_size, uboot_size = 0; + phys_addr_t uboot_ram_top, ram_top, pstore_size = 0, uboot_size = 0; struct tz_reserved_region region[2], tmp; phys_addr_t top_addr, low_addr; struct arm_smccc_res res; u32 used_regions = 1; + /* ram_top must be <= 4GiB due to DMA limitations */ + ram_top = min_t(phys_addr_t, gd->ram_top, SZ_4G); + /* BL31 region */ arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); if (res.a0) { @@ -119,14 +123,14 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) } debug("Effective memory @ 0x%08zx, size 0x%llx\n", gd->ram_base, - gd->ram_top - gd->ram_base); + ram_top - gd->ram_base); /* Discard/fix region which is outside the effective memory */ - if (fix_tz_region(region, used_regions)) { + if (fix_tz_region(region, used_regions, ram_top)) { used_regions--; if (used_regions) { - if (fix_tz_region(region, used_regions)) + if (fix_tz_region(region, used_regions, ram_top)) used_regions--; } } @@ -144,7 +148,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) uboot_size += U_BOOT_MIN_STACK_SIZE + REGION_ALIGNMENT - 1; uboot_size &= ~(REGION_ALIGNMENT - 1); - uboot_ram_top = gd->ram_top & ~(REGION_ALIGNMENT - 1); + uboot_ram_top = ram_top & ~(REGION_ALIGNMENT - 1); if (!used_regions || (uboot_ram_top - region[0].addr - region[0].size >= uboot_size)) { diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index ef86129b535..c687ef822a2 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -12,6 +12,8 @@ config MESON64_COMMON select MMC_PWRSEQ select BOARD_LATE_INIT select MESON_SM + imply SYSRESET + imply SYSRESET_PSCI imply CMD_DM config MESON_GX diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c index a5afc2d75c0..c34b81e5e78 100644 --- a/arch/arm/mach-meson/board-common.c +++ b/arch/arm/mach-meson/board-common.c @@ -155,16 +155,14 @@ int board_late_init(void) return meson_board_late_init(); } +#if defined(CONFIG_XPL) || !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(void) { -#if CONFIG_SPL_BUILD /* * We do not have BL31 running yet, so no PSCI. * Instead, let the watchdog reset the board. */ for (;;) ; -#else - psci_system_reset(); -#endif } +#endif diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 4afaee234ea..3465ccfc151 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -166,6 +166,14 @@ config TARGET_MVEBU_ARMADA_8K select BOARD_LATE_INIT imply SCSI +config TARGET_NBX10G + bool "Support Freebox Nodebox 10G" + select ARMADA_8K + select BOARD_LATE_INIT + help + Enable support for the Freebox Nodebox 10G board based on the + Marvell Armada 8040 SoC with dual CP110 companion chips. + config TARGET_MVEBU_ALLEYCAT5 bool "Support AlleyCat 5 platforms" select ALLEYCAT_5 @@ -226,6 +234,10 @@ config TARGET_X240 select ALLEYCAT_5 imply BOOTSTD_DEFAULTS +config TARGET_X220 + bool "Support Allied Telesis x220" + select 98DX3336 + config TARGET_DB_XC3_24G4XG bool "Support DB-XC3-24G4XG" select 98DX3336 @@ -310,6 +322,7 @@ config SYS_BOARD default "x530" if TARGET_X530 default "x250" if TARGET_X250 default "x240" if TARGET_X240 + default "x220" if TARGET_X220 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 @@ -335,6 +348,7 @@ config SYS_CONFIG_NAME default "x530" if TARGET_X530 default "x250" if TARGET_X250 default "x240" if TARGET_X240 + default "x220" if TARGET_X220 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 @@ -360,6 +374,7 @@ config SYS_VENDOR default "alliedtelesis" if TARGET_X530 default "alliedtelesis" if TARGET_X250 default "alliedtelesis" if TARGET_X240 + default "alliedtelesis" if TARGET_X220 default "mikrotik" if TARGET_CRS3XX_98DX3236 default "Marvell" if TARGET_MVEBU_ALLEYCAT5 @@ -508,5 +523,6 @@ config ARMADA_32BIT_SYSCON_SYSRESET source "board/solidrun/clearfog/Kconfig" source "board/kobol/helios4/Kconfig" +source "board/freebox/nbx10g/Kconfig" endif diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index be2d9a25bf9..3ebb4294bdd 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -138,8 +138,8 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c index 17525691e68..38d9b40f482 100644 --- a/arch/arm/mach-mvebu/armada3700/cpu.c +++ b/arch/arm/mach-mvebu/armada3700/cpu.c @@ -256,7 +256,7 @@ int a3700_dram_init_banksize(void) * build_mem_map. */ if (last_end == dram_wins[win].base) { - gd->bd->bi_dram[bank - 1].size += size; + gd->dram[bank - 1].size += size; last_end += size; } else { if (bank == CONFIG_NR_DRAM_BANKS) { @@ -264,8 +264,8 @@ int a3700_dram_init_banksize(void) return -ENOBUFS; } - gd->bd->bi_dram[bank].start = dram_wins[win].base; - gd->bd->bi_dram[bank].size = size; + gd->dram[bank].start = dram_wins[win].base; + gd->dram[bank].size = size; last_end = dram_wins[win].base + size; ++bank; } @@ -276,8 +276,8 @@ int a3700_dram_init_banksize(void) * the rest with zeros. */ for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) { - gd->bd->bi_dram[bank].start = 0; - gd->bd->bi_dram[bank].size = 0; + gd->dram[bank].start = 0; + gd->dram[bank].size = 0; } return 0; diff --git a/arch/arm/mach-mvebu/armada8k/Makefile b/arch/arm/mach-mvebu/armada8k/Makefile index 0a4756717a3..723239d9894 100644 --- a/arch/arm/mach-mvebu/armada8k/Makefile +++ b/arch/arm/mach-mvebu/armada8k/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2016 Stefan Roese <[email protected]> -obj-y = cpu.o cache_llc.o dram.o +obj-y = cpu.o cache_llc.o dram.o soc_info.o diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 3eb93c82387..220b32dd025 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -15,6 +15,8 @@ #include <asm/armv8/mmu.h> #include <mach/fw_info.h> +#include "soc_info.h" + /* Armada 7k/8k */ #define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000)) #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84) @@ -111,3 +113,13 @@ int mmc_get_env_dev(void) return CONFIG_ENV_MMC_DEVICE_INDEX; } + +int print_cpuinfo(void) +{ + if (!IS_ENABLED(CONFIG_DISPLAY_CPUINFO)) + return 0; + + soc_print_clock_info(); + soc_print_soc_info(); + return 0; +} diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index fd58551d0e3..af37dfa2252 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,16 +38,16 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } - gd->bd->bi_dram[0].size = max_bank0_size; + gd->dram[0].size = max_bank0_size; if (CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = gd->ram_size - max_bank0_size; } return 0; diff --git a/arch/arm/mach-mvebu/armada8k/soc_info.c b/arch/arm/mach-mvebu/armada8k/soc_info.c new file mode 100644 index 00000000000..18cc083c0db --- /dev/null +++ b/arch/arm/mach-mvebu/armada8k/soc_info.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Marvell International Ltd. + * + * Marvell Armada 8K SoC info: SAR, Clock frequencies, LLC status + * Ported from Marvell U-Boot 2015.01 to mainline U-Boot. + */ + +#include <config.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <stdio.h> +#include <asm/io.h> +#include <asm/arch/soc.h> + +/* Clock frequency units */ +#define KHz 1000 +#define MHz 1000000 +#define GHz 1000000000 + +/* AP806 SAR (Sample-At-Reset) register */ +#define AP806_SAR_REG_BASE (SOC_REGS_PHY_BASE + 0x6F4400) +#define SAR_CLOCK_FREQ_MODE_OFFSET 0 +#define SAR_CLOCK_FREQ_MODE_MASK (0x1f << SAR_CLOCK_FREQ_MODE_OFFSET) + +/* LLC (Last Level Cache) registers */ +#define LLC_BASE (SOC_REGS_PHY_BASE + 0x8000) +#define LLC_CTRL 0x100 +#define LLC_CTRL_EN 0x1 +#define LLC_EXCLUSIVE_EN 0x100 + +/* MSS clock is fixed at 200MHz on AP806 */ +#define AP806_MSS_CLOCK (200 * MHz) + +/* Clock ID indices in PLL frequency table */ +#define CPU_CLOCK_ID 0 +#define DDR_CLOCK_ID 1 +#define RING_CLOCK_ID 2 + +/* Clocking options (SAR field values) */ +enum clocking_options { + CPU_2000_DDR_1200_RCLK_1200 = 0x0, + CPU_2000_DDR_1050_RCLK_1050 = 0x1, + CPU_1600_DDR_800_RCLK_800 = 0x4, + CPU_1800_DDR_1200_RCLK_1200 = 0x6, + CPU_1800_DDR_1050_RCLK_1050 = 0x7, + CPU_1600_DDR_900_RCLK_900 = 0x0b, + CPU_1600_DDR_1050_RCLK_1050 = 0x0d, + CPU_1600_DDR_900_RCLK_900_2 = 0x0e, + CPU_1000_DDR_650_RCLK_650 = 0x13, + CPU_1300_DDR_800_RCLK_800 = 0x14, + CPU_1300_DDR_650_RCLK_650 = 0x17, + CPU_1200_DDR_800_RCLK_800 = 0x19, + CPU_1400_DDR_800_RCLK_800 = 0x1a, + CPU_600_DDR_800_RCLK_800 = 0x1b, + CPU_800_DDR_800_RCLK_800 = 0x1c, + CPU_1000_DDR_800_RCLK_800 = 0x1d, +}; + +/* + * PLL frequency table: maps SAR clock mode to actual frequencies. + * Format: { CPU_freq, DDR_freq, RING_freq, SAR_value } + */ +static const u32 pll_freq_tbl[16][4] = { + /* CPU */ /* DDR */ /* Ring */ + {2000 * MHz, 1200 * MHz, 1200 * MHz, CPU_2000_DDR_1200_RCLK_1200}, + {2000 * MHz, 1050 * MHz, 1050 * MHz, CPU_2000_DDR_1050_RCLK_1050}, + {1800 * MHz, 1200 * MHz, 1200 * MHz, CPU_1800_DDR_1200_RCLK_1200}, + {1800 * MHz, 1050 * MHz, 1050 * MHz, CPU_1800_DDR_1050_RCLK_1050}, + {1600 * MHz, 1050 * MHz, 1050 * MHz, CPU_1600_DDR_1050_RCLK_1050}, + {1600 * MHz, 900 * MHz, 900 * MHz, CPU_1600_DDR_900_RCLK_900_2}, + {1300 * MHz, 800 * MHz, 800 * MHz, CPU_1300_DDR_800_RCLK_800}, + {1300 * MHz, 650 * MHz, 650 * MHz, CPU_1300_DDR_650_RCLK_650}, + {1600 * MHz, 800 * MHz, 800 * MHz, CPU_1600_DDR_800_RCLK_800}, + {1600 * MHz, 900 * MHz, 900 * MHz, CPU_1600_DDR_900_RCLK_900}, + {1000 * MHz, 650 * MHz, 650 * MHz, CPU_1000_DDR_650_RCLK_650}, + {1200 * MHz, 800 * MHz, 800 * MHz, CPU_1200_DDR_800_RCLK_800}, + {1400 * MHz, 800 * MHz, 800 * MHz, CPU_1400_DDR_800_RCLK_800}, + {600 * MHz, 800 * MHz, 800 * MHz, CPU_600_DDR_800_RCLK_800}, + {800 * MHz, 800 * MHz, 800 * MHz, CPU_800_DDR_800_RCLK_800}, + {1000 * MHz, 800 * MHz, 800 * MHz, CPU_1000_DDR_800_RCLK_800} +}; + +/* + * Get the clock frequency mode index from SAR register. + * Returns index into pll_freq_tbl, or -1 if not found. + */ +static int sar_get_clock_freq_mode(void) +{ + u32 i; + u32 clock_freq; + + clock_freq = (readl(AP806_SAR_REG_BASE) & SAR_CLOCK_FREQ_MODE_MASK) + >> SAR_CLOCK_FREQ_MODE_OFFSET; + + for (i = 0; i < ARRAY_SIZE(pll_freq_tbl); i++) { + if (pll_freq_tbl[i][3] == clock_freq) + return i; + } + + pr_err("SAR: unsupported clock freq mode %d\n", clock_freq); + return -1; +} + +/* + * Get CPU clock frequency in Hz. + */ +static u32 soc_cpu_clk_get(void) +{ + int mode = sar_get_clock_freq_mode(); + + if (mode < 0) + return 0; + return pll_freq_tbl[mode][CPU_CLOCK_ID]; +} + +/* + * Get DDR clock frequency in Hz. + */ +static u32 soc_ddr_clk_get(void) +{ + int mode = sar_get_clock_freq_mode(); + + if (mode < 0) + return 0; + return pll_freq_tbl[mode][DDR_CLOCK_ID]; +} + +/* + * Get Ring (Fabric) clock frequency in Hz. + */ +static u32 soc_ring_clk_get(void) +{ + int mode = sar_get_clock_freq_mode(); + + if (mode < 0) + return 0; + return pll_freq_tbl[mode][RING_CLOCK_ID]; +} + +/* + * Get MSS clock frequency in Hz. + */ +static u32 soc_mss_clk_get(void) +{ + return AP806_MSS_CLOCK; +} + +/* + * Get LLC status and mode. + * Returns 1 if LLC is enabled, 0 otherwise. + * If excl_mode is not NULL, sets it to 1 if exclusive mode is enabled. + */ +static int llc_mode_get(int *excl_mode) +{ + u32 val; + int ret = 0, excl = 0; + + val = readl(LLC_BASE + LLC_CTRL); + if (val & LLC_CTRL_EN) { + ret = 1; + if (val & LLC_EXCLUSIVE_EN) + excl = 1; + } + if (excl_mode) + *excl_mode = excl; + + return ret; +} + +/* + * Print SoC clock information. + */ +void soc_print_clock_info(void) +{ + printf("Clock: CPU %-4d [MHz]\n", soc_cpu_clk_get() / MHz); + printf("\tDDR %-4d [MHz]\n", soc_ddr_clk_get() / MHz); + printf("\tFABRIC %-4d [MHz]\n", soc_ring_clk_get() / MHz); + printf("\tMSS %-4d [MHz]\n", soc_mss_clk_get() / MHz); +} + +/* + * Print SoC-specific information: DDR width and LLC status. + */ +void soc_print_soc_info(void) +{ + int llc_en, llc_excl_mode; + + printf("\tDDR 64 Bit width\n"); + + llc_en = llc_mode_get(&llc_excl_mode); + printf("\tLLC %s%s\n", llc_en ? "Enabled" : "Disabled", + llc_excl_mode ? " (Exclusive Mode)" : ""); +} diff --git a/arch/arm/mach-mvebu/armada8k/soc_info.h b/arch/arm/mach-mvebu/armada8k/soc_info.h new file mode 100644 index 00000000000..41afe7a2508 --- /dev/null +++ b/arch/arm/mach-mvebu/armada8k/soc_info.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2015 Marvell International Ltd. + * + * Marvell Armada 8K SoC info functions + */ + +#ifndef _ARMADA8K_SOC_INFO_H_ +#define _ARMADA8K_SOC_INFO_H_ + +void soc_print_clock_info(void); +void soc_print_soc_info(void); + +#endif /* _ARMADA8K_SOC_INFO_H_ */ diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index c00c6b9b3fc..41eaaa24bd0 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -294,11 +294,11 @@ int dram_init_banksize(void) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mvebu_sdram_bar(i); - gd->bd->bi_dram[i].size = mvebu_sdram_bs(i); + gd->dram[i].start = mvebu_sdram_bar(i); + gd->dram[i].size = mvebu_sdram_bs(i); /* Clip the banksize to 1GiB if it exceeds the max size */ - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; if (size > MVEBU_SDRAM_SIZE_MAX) mvebu_sdram_bs_set(i, 0x40000000); } diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1e989ac48ac..767ca904b61 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -29,6 +29,25 @@ config OMAP34XX imply SYS_THUMB_BUILD imply TWL4030_POWER +config OMAP44XX + bool "OMAP44XX SoC" + select DM_EVENT + select SPL_USE_TINY_PRINTF + select SPL_SYS_NO_VECTOR_TABLE if SPL + imply SPL_FS_FAT + imply SPL_GPIO + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_MMC + imply SPL_POWER + imply SPL_SERIAL + imply SYS_I2C_OMAP24XX + imply SYS_THUMB_BUILD + help + Support for OMAP44x SOC from Texas Instruments. + OMAP44x features two Cortex-A9 cores. + config OMAP54XX bool "OMAP54XX SoC" select ARM_CORTEX_A15_CVE_2017_5715 @@ -139,7 +158,7 @@ config SYS_AUTOMATIC_SDRAM_DETECTION bool choice - depends on OMAP54XX + depends on OMAP44XX || OMAP54XX prompt "Static or dynamic DDR timing calculations" default SYS_EMIF_PRECALCULATED_TIMING_REGS help @@ -152,6 +171,7 @@ config SYS_EMIF_PRECALCULATED_TIMING_REGS config SYS_DEFAULT_LPDDR2_TIMINGS bool "Use default LPDDR2 timing values" + depends on !OMAP44XX select SYS_AUTOMATIC_SDRAM_DETECTION endchoice @@ -195,6 +215,8 @@ endif source "arch/arm/mach-omap2/omap3/Kconfig" +source "arch/arm/mach-omap2/omap4/Kconfig" + source "arch/arm/mach-omap2/omap5/Kconfig" source "arch/arm/mach-omap2/am33xx/Kconfig" diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index fb5ea97e56e..c34caca78af 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -5,6 +5,7 @@ obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(CONFIG_OMAP34XX) += omap3/ +obj-$(CONFIG_OMAP44XX) += omap4/ obj-$(CONFIG_OMAP54XX) += omap5/ obj-y += reset.o @@ -18,7 +19,7 @@ endif obj-y += utils.o obj-y += sysinfo-common.o -ifdef CONFIG_OMAP54XX +ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) obj-y += hwinit-common.o obj-y += clocks-common.o obj-y += emif-common.o diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 4e9ad8935e3..729533d02d4 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -80,8 +80,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } @@ -259,25 +259,34 @@ int arch_misc_init(void) { return 0; } -#else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ +#else /* CONFIG_AM335X_USB* && CONFIG_XPL_BUILD */ int arch_misc_init(void) { struct udevice *dev; - int ret; + int ret = 0; - ret = uclass_first_device_err(UCLASS_MISC, &dev); - if (ret) - return ret; + if (IS_ENABLED(CONFIG_USB_MUSB_TI) && !IS_ENABLED(CONFIG_OF_UPSTREAM)) { + /* + * Trigger probe of the UCLASS_MISC device which is a USB + * wrapper driver ti-musb-wrapper that handles all usb host and + * gadget devices. Note that with OF_UPSTREAM the devices are + * bound directly, no wrapper necessary. + */ + ret = uclass_first_device_err(UCLASS_MISC, &dev); + if (ret) + printf("Failed probing USB %d, continue without USB\n", ret); + } #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) - usb_ether_init(); + if (!ret) + usb_ether_init(); #endif return 0; } -#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ +#endif /* CONFIG_AM335X_USB* && CONFIG_XPL_BUILD */ #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 41eec005cb1..a40813a99d8 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -185,10 +185,10 @@ void config_sdram(const struct emif_regs *regs, int nr) if (regs->zq_config) { writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); /* Trigger initialization */ writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); /* Wait 1ms because of L3 timeout error */ udelay(1000); diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index f19c66822d2..96e239b31a0 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -29,12 +29,21 @@ static struct cm_device_inst *cm_device = static void config_vtp(int nr) { - writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, - &vtpreg[nr]->vtp0ctrlreg); - writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), - &vtpreg[nr]->vtp0ctrlreg); - writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, - &vtpreg[nr]->vtp0ctrlreg); + /* + * A warm reset will result in DDR going into self refresh. Once the + * reset is released we will exit self refresh and resume normally + * so a reinitialization of the controller is not needed. + * + * Check to see if VTP is ready before we reinitialize the controller + */ + if ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != VTP_CTRL_READY) { + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, + &vtpreg[nr]->vtp0ctrlreg); + } /* Poll for READY */ while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index c83ba770669..ba57c7ecac4 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -104,9 +104,9 @@ ifdef CONFIG_SPL_LOAD_FIT MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) + $(patsubst %,-b $(dt_dir)/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) -OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) +OF_LIST_TARGETS = $(patsubst %,$(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) $(OF_LIST_TARGETS): dtbs %.dtb_HS: %.dtb FORCE diff --git a/arch/arm/mach-omap2/omap-cache.c b/arch/arm/mach-omap2/omap-cache.c index 200a08fa5c8..f08a9b263f6 100644 --- a/arch/arm/mach-omap2/omap-cache.c +++ b/arch/arm/mach-omap2/omap-cache.c @@ -53,11 +53,10 @@ void enable_caches(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; - u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + u32 start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + u32 size = gd->dram[bank].size >> MMU_SECTION_SHIFT; u32 end = start + size; debug("%s: bank: %d\n", __func__, bank); diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index 049eedfeb65..67e14d70e92 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -150,10 +150,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 24fae484369..c4187369c29 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -222,10 +222,10 @@ int dram_init_banksize(void) size0 = get_sdr_cs_size(CS0); size1 = get_sdr_cs_size(CS1); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = size0; + gd->dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->dram[1].size = size1; return 0; } diff --git a/arch/arm/mach-omap2/omap4/Kconfig b/arch/arm/mach-omap2/omap4/Kconfig new file mode 100644 index 00000000000..a170467f452 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/Kconfig @@ -0,0 +1,23 @@ +if OMAP44XX + +choice + prompt "OMAP4 board select" + optional + help + Select your OMAP4 board, available boards are: + - TI OMAP4 Variscite SOM + +config TARGET_OMAP4_VAR_SOM + bool "TI OMAP4 Variscite SOM" + help + OMAP4-based system on module. + Boots from the SD card reader + +endchoice + +config SYS_SOC + default "omap4" + +source "board/variscite/omap4_var_som/Kconfig" + +endif diff --git a/arch/arm/mach-omap2/omap4/Makefile b/arch/arm/mach-omap2/omap4/Makefile new file mode 100644 index 00000000000..2566c6ca2d3 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2010 +# Wolfgang Denk, DENX Software Engineering, [email protected]. + +obj-y += boot.o +obj-y += sdram_elpida.o +obj-y += hwinit.o +obj-y += prcm-regs.o +obj-y += hw_data.o diff --git a/arch/arm/mach-omap2/omap4/boot.c b/arch/arm/mach-omap2/omap4/boot.c new file mode 100644 index 00000000000..fc71db42d90 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/boot.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OMAP4 boot + * + * Copyright (C) 2015 Paul Kocialkowski <[email protected]> + */ + +#include <asm/io.h> +#include <asm/omap_common.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> + +static u32 boot_devices[] = { + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NONE, + BOOT_DEVICE_XIPWAIT, +}; + +u32 omap_sys_boot_device(void) +{ + u32 sys_boot; + + /* Grab the first 5 bits of the status register for SYS_BOOT. */ + sys_boot = readl((u32 *)(*ctrl)->control_status) & ((1 << 5) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} + +int omap_reboot_mode(char *mode, unsigned int length) +{ + unsigned int limit; + unsigned int i; + + if (length < 2) + return -1; + + if (!warm_reset()) + return -1; + + limit = (length < OMAP_REBOOT_REASON_SIZE) ? length : + OMAP_REBOOT_REASON_SIZE; + + for (i = 0; i < (limit - 1); i++) + mode[i] = readb((u8 *)(OMAP44XX_SAR_RAM_BASE + + OMAP_REBOOT_REASON_OFFSET + i)); + + mode[i] = '\0'; + + return 0; +} + +int omap_reboot_mode_clear(void) +{ + writeb(0, (u8 *)(OMAP44XX_SAR_RAM_BASE + OMAP_REBOOT_REASON_OFFSET)); + + return 0; +} + +int omap_reboot_mode_store(char *mode) +{ + unsigned int i; + + for (i = 0; i < (OMAP_REBOOT_REASON_SIZE - 1) && mode[i] != '\0'; i++) + writeb(mode[i], (u8 *)(OMAP44XX_SAR_RAM_BASE + + OMAP_REBOOT_REASON_OFFSET + i)); + + writeb('\0', (u8 *)(OMAP44XX_SAR_RAM_BASE + + OMAP_REBOOT_REASON_OFFSET + i)); + + return 0; +} diff --git a/arch/arm/mach-omap2/omap4/hw_data.c b/arch/arm/mach-omap2/omap4/hw_data.c new file mode 100644 index 00000000000..bda7443da79 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/hw_data.c @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * HW data initialization for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * Sricharan R <[email protected]> + */ +#include <asm/arch/omap.h> +#include <asm/arch/sys_proto.h> +#include <asm/omap_common.h> +#include <asm/arch/clock.h> +#include <asm/omap_gpio.h> +#include <asm/io.h> + +/* TPS */ +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_VSEL0_GPIO 7 +#define TPS62361_BASE_VOLT_MV 500 + +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 + +struct prcm_regs const **prcm = (struct prcm_regs const **)OMAP_SRAM_SCRATCH_PRCM_PTR; +struct dplls const **dplls_data = (struct dplls const **)OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = (struct vcores_data const **)OMAP_SRAM_SCRATCH_VCORES_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; + +/* + * The M & N values in the following tables are created using the + * following tool: + * tools/omap/clocks_get_m_n.c + * Please use this tool for creating the table for any new frequency. + */ + +/* + * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF + * OMAP4460 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { + {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* + * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) + * OMAP4430 OPP_TURBO frequency + * OMAP4470 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* + * dpll locked at 1200 MHz - MPU clk at 600 MHz + * OMAP4430 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4460 OPP_NOM frequency */ +/* OMAP4470 OPP_NOM (Low Power) frequency */ +static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4430 ES1 OPP_NOM frequency */ +static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { + {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4430 ES2.X OPP_NOM frequency */ +static const struct dpll_params + core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { + {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { + {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { + {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 +}; + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +struct dplls omap4430_dplls_es1 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es1_1524mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4430_dplls_es20 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es2_1600mhz_ddr200mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4430_dplls = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4460_dplls = { + .mpu = mpu_dpll_params_1400mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4470_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, + .abe = &abe_dpll_params_32k_196608khz, + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct pmic_data twl6030_4430es1 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, + .step = 12660, /* 12.66 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +/* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ +struct pmic_data twl6030 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, + .step = 12660, /* 12.66 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +struct pmic_data tps62361 = { + .base_offset = TPS62361_BASE_VOLT_MV, + .step = 10000, /* 10 mV represented in uV */ + .start_code = 0, + .gpio = TPS62361_VSEL0_GPIO, + .gpio_en = 1, + .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, + .pmic_bus_init = sri2c_init, + .pmic_write = omap_vc_bypass_send_value, +}; + +struct vcores_data omap4430_volts_es1 = { + .mpu.value[OPP_NOM] = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030_4430es1, + + .core.value[OPP_NOM] = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030_4430es1, + + .mm.value[OPP_NOM] = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030_4430es1, +}; + +struct vcores_data omap4430_volts = { + .mpu.value[OPP_NOM] = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030, + + .core.value[OPP_NOM] = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030, + + .mm.value[OPP_NOM] = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030, +}; + +struct vcores_data omap4460_volts = { + .mpu.value[OPP_NOM] = 1203, + .mpu.addr = TPS62361_REG_ADDR_SET1, + .mpu.pmic = &tps62361, + + .core.value[OPP_NOM] = 1200, + .core.addr = SMPS_REG_ADDR_VCORE1, + .core.pmic = &twl6030, + + .mm.value[OPP_NOM] = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030, +}; + +/* + * Take closest integer part of the mV value corresponding to a TWL6032 SMPS + * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. + */ +struct vcores_data omap4470_volts = { + .mpu.value[OPP_NOM] = 1202, + .mpu.addr = SMPS_REG_ADDR_SMPS1, + .mpu.pmic = &twl6030, + + .core.value[OPP_NOM] = 1126, + .core.addr = SMPS_REG_ADDR_SMPS2, + .core.pmic = &twl6030, + + .mm.value[OPP_NOM] = 1139, + .mm.addr = SMPS_REG_ADDR_SMPS5, + .mm.pmic = &twl6030, +}; + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +void enable_basic_clocks(void) +{ + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, GPTIMER1_CLKCTRL_CLKSEL_MASK); + + /* Enable optional 48M functional clock for USB PHY */ + setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); + + /* Enable 32 KHz clock for USB PHY */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void enable_basic_uboot_clocks(void) +{ + u32 const clk_domains_essential[] = { + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbotg_clkctrl, + (*prcm)->cm_l3init_usbphy_clkctrl, + (*prcm)->cm_clksel_usb_60mhz, + (*prcm)->cm_l3init_hsusbtll_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l3init_hsusbhost_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void hw_data_init(void) +{ + u32 omap_rev = omap_revision(); + + (*prcm) = &omap4_prcm; + + switch (omap_rev) { + case OMAP4430_ES1_0: + *dplls_data = &omap4430_dplls_es1; + *omap_vcores = &omap4430_volts_es1; + break; + case OMAP4430_ES2_0: + *dplls_data = &omap4430_dplls_es20; + *omap_vcores = &omap4430_volts; + break; + case OMAP4430_ES2_1: + case OMAP4430_ES2_2: + case OMAP4430_ES2_3: + *dplls_data = &omap4430_dplls; + *omap_vcores = &omap4430_volts; + break; + case OMAP4460_ES1_0: + case OMAP4460_ES1_1: + *dplls_data = &omap4460_dplls; + *omap_vcores = &omap4460_volts; + break; + case OMAP4470_ES1_0: + *dplls_data = &omap4470_dplls; + *omap_vcores = &omap4470_volts; + break; + default: + printf("\n INVALID OMAP REVISION "); + } + + *ctrl = &omap4_ctrl; +} diff --git a/arch/arm/mach-omap2/omap4/hwinit.c b/arch/arm/mach-omap2/omap4/hwinit.c new file mode 100644 index 00000000000..9beecb8ad49 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/hwinit.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * Common functions for OMAP4 based boards + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Author : + * Aneesh V <[email protected]> + * Steve Sakoman <[email protected]> + */ +#include <palmas.h> +#include <asm/armv7.h> +#include <asm/arch/cpu.h> +#include <asm/arch/sys_proto.h> +#include <linux/sizes.h> +#include <asm/emif.h> +#include <asm/arch/gpio.h> +#include <asm/omap_common.h> + +u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; + +#if !CONFIG_IS_ENABLED(DM_GPIO) +static const struct gpio_bank gpio_bank_44xx[6] = { + { (void *)OMAP44XX_GPIO1_BASE }, + { (void *)OMAP44XX_GPIO2_BASE }, + { (void *)OMAP44XX_GPIO3_BASE }, + { (void *)OMAP44XX_GPIO4_BASE }, + { (void *)OMAP44XX_GPIO5_BASE }, + { (void *)OMAP44XX_GPIO6_BASE }, +}; + +const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; +#endif + +/* + * Some tuning of IOs for optimal power and performance + */ +void do_io_settings(void) +{ + u32 omap4_rev = omap_revision(); + u32 lpddr2io; + + if (omap4_rev == OMAP4430_ES1_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; + else if (omap4_rev == OMAP4430_ES2_0) + lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; + else + lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; + + /* EMIF1 */ + writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); + /* No pull for GR10 as per hw team's recommendation */ + writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, (*ctrl)->control_lpddr2io1_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); + + /* EMIF2 */ + writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); + /* No pull for GR10 as per hw team's recommendation */ + writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, (*ctrl)->control_lpddr2io2_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); + + /* + * Some of these settings (TRIM values) come from eFuse and are + * in turn programmed in the eFuse at manufacturing time after + * calibration of the device. Do the software over-ride only if + * the device is not correctly trimmed + */ + if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + (*ctrl)->control_ldosram_iva_voltage_ctrl); + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + (*ctrl)->control_ldosram_mpu_voltage_ctrl); + + writel(LDOSRAM_VOLT_CTRL_OVERRIDE, + (*ctrl)->control_ldosram_core_voltage_ctrl); + } + + /* + * Over-ride the register + * i. unconditionally for all 4430 + * ii. only if un-trimmed for 4460 + */ + if (!readl((*ctrl)->control_efuse_1)) + writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1); + + if (omap4_rev < OMAP4460_ES1_0 || !readl((*ctrl)->control_efuse_2)) + writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2); +} + +/* dummy function for omap4 */ +void config_data_eye_leveling_samples(u32 emif_base) +{ +} + +void init_omap_revision(void) +{ + /* + * For some of the ES2/ES1 boards ID_CODE is not reliable: + * Also, ES1 and ES2 have different ARM revisions + * So use ARM revision for identification + */ + unsigned int arm_rev = cortex_rev(); + + switch (arm_rev) { + case MIDR_CORTEX_A9_R0P1: + *omap_si_rev = OMAP4430_ES1_0; + break; + case MIDR_CORTEX_A9_R1P2: + switch (readl(CONTROL_ID_CODE)) { + case OMAP4_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP4430_ES2_0; + break; + case OMAP4_CONTROL_ID_CODE_ES2_1: + *omap_si_rev = OMAP4430_ES2_1; + break; + case OMAP4_CONTROL_ID_CODE_ES2_2: + *omap_si_rev = OMAP4430_ES2_2; + break; + default: + *omap_si_rev = OMAP4430_ES2_0; + break; + } + break; + case MIDR_CORTEX_A9_R1P3: + *omap_si_rev = OMAP4430_ES2_3; + break; + case MIDR_CORTEX_A9_R2P10: + switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; + case OMAP4460_CONTROL_ID_CODE_ES1_1: + *omap_si_rev = OMAP4460_ES1_1; + break; + case OMAP4460_CONTROL_ID_CODE_ES1_0: + default: + *omap_si_rev = OMAP4460_ES1_0; + break; + } + break; + default: + *omap_si_rev = OMAP4430_SILICON_ID_INVALID; + break; + } +} + +void omap_die_id(unsigned int *die_id) +{ + die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); + die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); + die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); + die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); +} + +void v7_outer_cache_enable(void) +{ + if (!IS_ENABLED(CONFIG_SYS_L2CACHE_OFF)) + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); +} + +void v7_outer_cache_disable(void) +{ + if (!IS_ENABLED(CONFIG_SYS_L2CACHE_OFF)) + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); +} + +void vmmc_pbias_config(uint voltage) +{ + u32 value = 0; + + value = readl((*ctrl)->control_pbiaslite); + value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ); + writel(value, (*ctrl)->control_pbiaslite); + value = readl((*ctrl)->control_pbiaslite); + value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ; + writel(value, (*ctrl)->control_pbiaslite); +} diff --git a/arch/arm/mach-omap2/omap4/prcm-regs.c b/arch/arm/mach-omap2/omap4/prcm-regs.c new file mode 100644 index 00000000000..eaf98b38914 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/prcm-regs.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * + * HW regs data for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * Sricharan R <[email protected]> + */ + +#include <asm/omap_common.h> + +struct prcm_regs const omap4_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_m4_dpll_core = 0x4a004138, + .cm_div_m5_dpll_core = 0x4a00413c, + .cm_div_m6_dpll_core = 0x4a004140, + .cm_div_m7_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_emu_override_dpll_core = 0x4a004150, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_m4_dpll_iva = 0x4a0041b8, + .cm_div_m5_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_m4_dpll_ddrphy = 0x4a004238, + .cm_div_m5_dpll_ddrphy = 0x4a00423c, + .cm_div_m6_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_m4_dpll_per = 0x4a008158, + .cm_div_m5_dpll_per = 0x4a00815c, + .cm_div_m6_dpll_per = 0x4a008160, + .cm_div_m7_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40, + .cm_ivahd_clkstctrl = 0x4a008f00, + + /* cm2.ivahd */ + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_iss_clkctrl = 0x4a009020, + .cm_cam_fdif_clkctrl = 0x4a009028, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsi_clkctrl = 0x4a009338, + .cm_l3init_hsusbhost_clkctrl = 0x4a009358, + .cm_l3init_hsusbotg_clkctrl = 0x4a009360, + .cm_l3init_hsusbtll_clkctrl = 0x4a009368, + .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_fsusb_clkctrl = 0x4a0093d0, + .cm_l3init_usbphy_clkctrl = 0x4a0093e0, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009400, + .cm_l4per_dynamicdep = 0x4a009408, + .cm_l4per_adc_clkctrl = 0x4a009420, + .cm_l4per_gptimer10_clkctrl = 0x4a009428, + .cm_l4per_gptimer11_clkctrl = 0x4a009430, + .cm_l4per_gptimer2_clkctrl = 0x4a009438, + .cm_l4per_gptimer3_clkctrl = 0x4a009440, + .cm_l4per_gptimer4_clkctrl = 0x4a009448, + .cm_l4per_gptimer9_clkctrl = 0x4a009450, + .cm_l4per_elm_clkctrl = 0x4a009458, + .cm_l4per_gpio2_clkctrl = 0x4a009460, + .cm_l4per_gpio3_clkctrl = 0x4a009468, + .cm_l4per_gpio4_clkctrl = 0x4a009470, + .cm_l4per_gpio5_clkctrl = 0x4a009478, + .cm_l4per_gpio6_clkctrl = 0x4a009480, + .cm_l4per_hdq1w_clkctrl = 0x4a009488, + .cm_l4per_hecc1_clkctrl = 0x4a009490, + .cm_l4per_hecc2_clkctrl = 0x4a009498, + .cm_l4per_i2c1_clkctrl = 0x4a0094a0, + .cm_l4per_i2c2_clkctrl = 0x4a0094a8, + .cm_l4per_i2c3_clkctrl = 0x4a0094b0, + .cm_l4per_i2c4_clkctrl = 0x4a0094b8, + .cm_l4per_l4per_clkctrl = 0x4a0094c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, + .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0, + .cm_l4per_mgate_clkctrl = 0x4a0094e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009500, + .cm_l4per_mcspi4_clkctrl = 0x4a009508, + .cm_l4per_mmcsd3_clkctrl = 0x4a009520, + .cm_l4per_mmcsd4_clkctrl = 0x4a009528, + .cm_l4per_msprohg_clkctrl = 0x4a009530, + .cm_l4per_slimbus2_clkctrl = 0x4a009538, + .cm_l4per_uart1_clkctrl = 0x4a009540, + .cm_l4per_uart2_clkctrl = 0x4a009548, + .cm_l4per_uart3_clkctrl = 0x4a009550, + .cm_l4per_uart4_clkctrl = 0x4a009558, + .cm_l4per_mmcsd5_clkctrl = 0x4a009560, + .cm_l4per_i2c5_clkctrl = 0x4a009568, + .cm_l4sec_clkstctrl = 0x4a009580, + .cm_l4sec_staticdep = 0x4a009584, + .cm_l4sec_dynamicdep = 0x4a009588, + .cm_l4sec_aes1_clkctrl = 0x4a0095a0, + .cm_l4sec_aes2_clkctrl = 0x4a0095a8, + .cm_l4sec_des3des_clkctrl = 0x4a0095b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, + .cm_l4sec_rng_clkctrl = 0x4a0095c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4a30610c, + .cm_sys_clksel = 0x4a306110, + .cm_wkup_clkstctrl = 0x4a307800, + .cm_wkup_l4wkup_clkctrl = 0x4a307820, + .cm_wkup_wdtimer1_clkctrl = 0x4a307828, + .cm_wkup_wdtimer2_clkctrl = 0x4a307830, + .cm_wkup_gpio1_clkctrl = 0x4a307838, + .cm_wkup_gptimer1_clkctrl = 0x4a307840, + .cm_wkup_gptimer12_clkctrl = 0x4a307848, + .cm_wkup_synctimer_clkctrl = 0x4a307850, + .cm_wkup_usim_clkctrl = 0x4a307858, + .cm_wkup_sarram_clkctrl = 0x4a307860, + .cm_wkup_keyboard_clkctrl = 0x4a307878, + .cm_wkup_rtc_clkctrl = 0x4a307880, + .cm_wkup_bandgap_clkctrl = 0x4a307888, + .prm_vc_val_bypass = 0x4a307ba0, + .prm_vc_cfg_channel = 0x4a307ba4, + .prm_vc_cfg_i2c_mode = 0x4a307ba8, + .prm_vc_cfg_i2c_clk = 0x4a307bac, +}; + +struct omap_sys_ctrl_regs const omap4_ctrl = { + .control_status = 0x4A0022C4, + .control_std_fuse_die_id_0 = 0x4A002200, + .control_std_fuse_die_id_1 = 0x4A002208, + .control_std_fuse_die_id_2 = 0x4A00220C, + .control_std_fuse_die_id_3 = 0x4A002210, + .control_std_fuse_opp_bgap = 0x4a002260, + .control_status = 0x4a0022c4, + .control_ldosram_iva_voltage_ctrl = 0x4A002320, + .control_ldosram_mpu_voltage_ctrl = 0x4A002324, + .control_ldosram_core_voltage_ctrl = 0x4A002328, + .control_usbotghs_ctrl = 0x4A00233C, + .control_padconf_core_base = 0x4A100000, + .control_pbiaslite = 0x4A100600, + .control_lpddr2io1_0 = 0x4A100638, + .control_lpddr2io1_1 = 0x4A10063C, + .control_lpddr2io1_2 = 0x4A100640, + .control_lpddr2io1_3 = 0x4A100644, + .control_lpddr2io2_0 = 0x4A100648, + .control_lpddr2io2_1 = 0x4A10064C, + .control_lpddr2io2_2 = 0x4A100650, + .control_lpddr2io2_3 = 0x4A100654, + .control_efuse_1 = 0x4A100700, + .control_efuse_2 = 0x4A100704, + .control_padconf_wkup_base = 0x4A31E000, +}; diff --git a/arch/arm/mach-omap2/omap4/sdram_elpida.c b/arch/arm/mach-omap2/omap4/sdram_elpida.c new file mode 100644 index 00000000000..b2bac429a85 --- /dev/null +++ b/arch/arm/mach-omap2/omap4/sdram_elpida.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Timing and Organization details of the Elpida parts used in OMAP4 + * SDPs and Panda + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <[email protected]> + */ + +#include <asm/emif.h> +#include <asm/arch/sys_proto.h> + +/* + * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430 + * SDP and Panda. Since the parts used and geometry are identical for + * SDP and Panda for a given OMAP4 revision, this information is kept + * here instead of being in board directory. However the key functions + * exported are weakly linked so that they can be over-ridden in the board + * directory if there is a OMAP4 board in the future that uses a different + * memory device or geometry. + * + * For any new board with different memory devices over-ride one or more + * of the following functions as per the CONFIG flags you intend to enable: + * - emif_get_reg_dump() + * - emif_get_dmm_regs() + * - emif_get_device_details() + * - emif_get_device_timings() + */ + +const struct emif_regs emif_regs_elpida_200_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x0000030c, + .sdram_tim1 = 0x08648311, + .sdram_tim2 = 0x101b06ca, + .sdram_tim3 = 0x0048a19f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff808 +}; + +const struct emif_regs emif_regs_elpida_380_mhz_1cs = { + .sdram_config_init = 0x80000eb1, + .sdram_config = 0x80001ab1, + .ref_ctrl = 0x000005cd, + .sdram_tim1 = 0x10cb0622, + .sdram_tim2 = 0x20350d52, + .sdram_tim3 = 0x00b1431f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { + .sdram_config_init = 0x80800eb2, + .sdram_config = 0x80801ab2, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3215, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct emif_regs emif_regs_elpida_400_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0xd00b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80540300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x1 +}; + +__weak void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + u32 omap4_rev = omap_revision(); + + /* Same devices and geometry on both EMIFs */ + if (omap4_rev == OMAP4430_ES1_0) + *regs = &emif_regs_elpida_380_mhz_1cs; + else if (omap4_rev == OMAP4430_ES2_0) + *regs = &emif_regs_elpida_200_mhz_2cs; + else if (omap4_rev < OMAP4470_ES1_0) + *regs = &emif_regs_elpida_400_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_1cs; +} + +__weak void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + u32 omap_rev = omap_revision(); + + if (omap_rev == OMAP4430_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; + else if (omap_rev < OMAP4460_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else + *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; +} + +static const struct lpddr2_ac_timings timings_elpida_400_mhz = { + .max_freq = 400000000, + .RL = 6, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_ac_timings timings_elpida_333_mhz = { + .max_freq = 333000000, + .RL = 5, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 15, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_ac_timings timings_elpida_200_mhz = { + .max_freq = 200000000, + .RL = 3, + .tRPab = 21, + .tRCD = 18, + .tWR = 15, + .tRASmin = 42, + .tRRD = 10, + .tWTRx2 = 20, + .tXSR = 140, + .tXPx2 = 15, + .tRFCab = 130, + .tRTPx2 = 15, + .tCKE = 3, + .tCKESR = 15, + .tZQCS = 90, + .tZQCL = 360, + .tZQINIT = 1000, + .tDQSCKMAXx2 = 11, + .tRASmax = 70, + .tFAW = 50 +}; + +static const struct lpddr2_min_tck min_tck_elpida = { + .tRL = 3, + .tRP_AB = 3, + .tRCD = 3, + .tWR = 3, + .tRAS_MIN = 3, + .tRRD = 2, + .tWTR = 2, + .tXP = 2, + .tRTP = 2, + .tCKE = 3, + .tCKESR = 3, + .tFAW = 8 +}; + +static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = { + &timings_elpida_200_mhz, + &timings_elpida_333_mhz, + &timings_elpida_400_mhz +}; + +const struct lpddr2_device_timings elpida_2G_S4_timings = { + .ac_timings = elpida_ac_timings, + .min_tck = &min_tck_elpida, +}; + +__weak void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + u32 omap_rev = omap_revision(); + + /* Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &elpida_2G_S4_timings; + + if (omap_rev == OMAP4430_ES1_0 || omap_rev == OMAP4470_ES1_0) + *cs1_device_timings = NULL; + else + *cs1_device_timings = &elpida_2G_S4_timings; +} + +const struct lpddr2_mr_regs mr_regs = { + .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3, + .mr2 = 0x4, + .mr3 = -1, + .mr10 = MR10_ZQ_ZQINIT, + .mr16 = MR16_REF_FULL_ARRAY +}; + +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) +{ + *regs = &mr_regs; +} + +__weak const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + return 0; +} diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 5394529658b..2a96a8418e2 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -64,7 +64,7 @@ config OMAP_PLATFORM_RESET_TIME_MAX_USEC 1: Time taken by the Osciallator to stop and restart 2: PMIC OTP time 3: Voltage ramp time, which can be derived using the PMIC slew rate - and value of voltage ramp needed. + and value of voltage ramp needed. if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM menu "Voltage Domain OPP selections" @@ -72,7 +72,7 @@ menu "Voltage Domain OPP selections" choice prompt "MPU Voltage Domain" default DRA7_MPU_OPP_NOM - help + help Select the Operating Performance Point(OPP) for the MPU voltage domain on DRA7xx & AM57xx SoCs. @@ -86,7 +86,7 @@ endchoice choice prompt "DSPEVE Voltage Domain" - help + help Select the Operating Performance Point(OPP) for the DSPEVE voltage domain on DRA7xx & AM57xx SoCs. @@ -110,7 +110,7 @@ endchoice choice prompt "IVA Voltage Domain" - help + help Select the Operating Performance Point(OPP) for the IVA voltage domain on DRA7xx & AM57xx SoCs. @@ -134,7 +134,7 @@ endchoice choice prompt "GPU Voltage Domain" - help + help Select the Operating Performance Point(OPP) for the GPU voltage domain on DRA7xx & AM57xx SoCs. diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index cb377aa1272..92d2682a3f2 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -46,6 +46,8 @@ #define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 #define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + /** * omap_vc_init() - Initialization for Voltage controller * @speed_khz: I2C buspeed in KHz diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig index 76d3998884d..4d1bfb778ee 100644 --- a/arch/arm/mach-owl/Kconfig +++ b/arch/arm/mach-owl/Kconfig @@ -1,21 +1,21 @@ if ARCH_OWL choice - prompt "Actions Semi Owl SoC Variant" + prompt "Actions Semi Owl SoC Variant" optional config MACH_S900 - bool "Actions Semi S900 SoC" - select ARM64 + bool "Actions Semi S900 SoC" + select ARM64 config MACH_S700 - bool "Actions Semi S700 SoC" - select ARM64 + bool "Actions Semi S700 SoC" + select ARM64 endchoice config TEXT_BASE - default 0x11000000 + default 0x11000000 config SYS_CONFIG_NAME default "owl-common" diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 0130cad7678..e316c2cc40e 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,8 +50,8 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig index fa4e312a4dd..f86acc31039 100644 --- a/arch/arm/mach-renesas/Kconfig +++ b/arch/arm/mach-renesas/Kconfig @@ -1,15 +1,19 @@ if ARCH_RENESAS -# Renesas ARM SoCs R-Car Gen3/Gen4 (64bit) +config TMU_TIMER + bool + +# Renesas ARM SoCs R-Car Gen3/Gen4/Gen5 (64bit Cortex-A / 32bit Cortex-M/R) config RCAR_64 bool - select ARM64 + select CPU_V8M if RCAR_64_RSIP + select ARM64 if !RCAR_64_RSIP select CMD_CACHE - select OF_BOARD_SETUP + select OF_BOARD_SETUP if !RCAR_64_RSIP select PHY select PINCONF select PINCTRL - select POSITION_INDEPENDENT + select POSITION_INDEPENDENT if !RCAR_64_RSIP imply CMD_FS_UUID imply CMD_GPT imply CMD_MMC_SWRITE if MMC diff --git a/arch/arm/mach-renesas/Kconfig.32 b/arch/arm/mach-renesas/Kconfig.32 index bbc61ccf480..3ee52c40da7 100644 --- a/arch/arm/mach-renesas/Kconfig.32 +++ b/arch/arm/mach-renesas/Kconfig.32 @@ -134,17 +134,17 @@ choice config QOS_PRI_NORMAL bool "Non primary" help - Select normal mode for QoS setting. + Select normal mode for QoS setting. config QOS_PRI_MEDIA bool "Media primary" help - Select multimedia primary mode for QoS setting. + Select multimedia primary mode for QoS setting. config QOS_PRI_GFX bool "GFX primary" help - Select GFX(graphics) primary mode for QoS setting. + Select GFX(graphics) primary mode for QoS setting. endchoice diff --git a/arch/arm/mach-renesas/Kconfig.rcar3 b/arch/arm/mach-renesas/Kconfig.rcar3 index 0d5f7486218..6bed7684fb8 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar3 +++ b/arch/arm/mach-renesas/Kconfig.rcar3 @@ -96,35 +96,35 @@ config TARGET_CONDOR bool "Condor board" imply R8A77980 help - Support for Renesas R-Car Gen3 Condor platform + Support for Renesas R-Car Gen3 Condor platform config TARGET_V3HSK bool "V3HSK board" help - Support for Renesas R-Car Gen3 V3HSK platform + Support for Renesas R-Car Gen3 V3HSK platform config TARGET_DRAAK bool "Draak board" imply R8A77995 help - Support for Renesas R-Car Gen3 Draak platform + Support for Renesas R-Car Gen3 Draak platform config TARGET_EAGLE bool "Eagle board" imply R8A77970 help - Support for Renesas R-Car Gen3 Eagle platform + Support for Renesas R-Car Gen3 Eagle platform config TARGET_V3MSK bool "V3MSK board" help - Support for Renesas R-Car Gen3 V3MSK platform + Support for Renesas R-Car Gen3 V3MSK platform config TARGET_EBISU bool "Ebisu board" imply R8A77990 help - Support for Renesas R-Car Gen3 Ebisu platform + Support for Renesas R-Car Gen3 Ebisu platform config TARGET_HIHOPE_RZG2 bool "HiHope RZ/G2 board" @@ -135,14 +135,14 @@ config TARGET_HIHOPE_RZG2 imply RZ_G2 imply SYS_MALLOC_F help - Support for RZG2 HiHope platform + Support for RZG2 HiHope platform config TARGET_SILINUX_EK874 bool "Silicon Linux EK874 board" imply R8A774C0 imply RZ_G2 help - Support for Silicon Linux EK874 platform + Support for Silicon Linux EK874 platform config TARGET_SALVATOR_X bool "Salvator-X board" @@ -152,7 +152,7 @@ config TARGET_SALVATOR_X imply R8A77965 imply SYS_MALLOC_F help - Support for Renesas R-Car Gen3 platform + Support for Renesas R-Car Gen3 platform config TARGET_ULCB bool "ULCB board" @@ -162,7 +162,14 @@ config TARGET_ULCB imply R8A77965 imply SYS_MALLOC_F help - Support for Renesas R-Car Gen3 ULCB platform + Support for Renesas R-Car Gen3 ULCB platform + +config TARGET_GEIST + bool "Geist board" + imply R8A77965 + imply SYS_MALLOC_F + help + Support for Renesas R-Car Gen3 Geist platform endchoice @@ -170,6 +177,7 @@ source "board/renesas/condor/Kconfig" source "board/renesas/draak/Kconfig" source "board/renesas/eagle/Kconfig" source "board/renesas/ebisu/Kconfig" +source "board/renesas/geist/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" source "board/renesas/v3hsk/Kconfig" diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4 index 04418f7aa05..39814950b1a 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar4 +++ b/arch/arm/mach-renesas/Kconfig.rcar4 @@ -11,12 +11,14 @@ config R8A779A0 config R8A779F0 bool "Renesas SoC R8A779F0" select GICV3 + select GICV3_SUPPORT_GIC600 imply CLK_R8A779F0 imply PINCTRL_PFC_R8A779F0 config R8A779G0 bool "Renesas SoC R8A779G0" select GICV3 + select GICV3_SUPPORT_GIC600 select BINMAN select SUPPORT_SPL imply SPL @@ -33,6 +35,7 @@ config R8A779G0 config R8A779H0 bool "Renesas SoC R8A779H0" select GICV3 + select GICV3_SUPPORT_GIC600 imply CLK_R8A779H0 imply PINCTRL_PFC_R8A779H0 @@ -46,7 +49,7 @@ config TARGET_FALCON bool "Falcon board" imply R8A779A0 help - Support for Renesas R-Car Gen3 Falcon platform + Support for Renesas R-Car Gen3 Falcon platform config TARGET_SPIDER bool "Spider board" diff --git a/arch/arm/mach-renesas/Kconfig.rcar5 b/arch/arm/mach-renesas/Kconfig.rcar5 index 528fc5aecc9..33ad8522f07 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar5 +++ b/arch/arm/mach-renesas/Kconfig.rcar5 @@ -1,11 +1,22 @@ if RCAR_GEN5 +config RCAR_64_RSIP + bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)" + select LMB_ARCH_MEM_MAP + select SKIP_RELOCATE_CODE + select TMU_TIMER + help + Build U-Boot for the Cortex-M33 RSIP core present on selected SoC. + The default is n, meaning U-Boot is built for the Cortex-A core. + menu "Select Target SoC" config R8A78000 bool "Renesas SoC R8A78000" select GICV3 + imply CLK_R8A78000 imply PINCTRL_PFC_R8A78000 + imply RENESAS_R8A78000_POWER_DOMAIN endmenu @@ -23,4 +34,7 @@ endchoice source "board/renesas/ironhide/Kconfig" +config SKIP_RELOCATE_CODE_DATA_OFFSET + default 0xa0000000 if RCAR_64_RSIP + endif diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile index 652a392ba6f..4c8dbc465a6 100644 --- a/arch/arm/mach-renesas/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -40,6 +40,29 @@ else srec_cat_le_cmd := "-l-e-constant" endif +ifneq ($(CONFIG_RCAR_GEN5),) +quiet_cmd_srec_cat = SRECCAT $@ + cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ + -Output_Block_Size 16 \ + -generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \ + -generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4 + +quiet_cmd_srec_shdr_cat = SRECCAT $@ + cmd_srec_shdr_cat = srec_cat -output $@ -M 8 \ + -Output_Block_Size 16 \ + -DISable Data_Count \ + -Execution_Start_Address 0x18400000 \ + -generate 0x18400000 0x18400004 $(srec_cat_le_cmd) 0x00000003 4 \ + -generate 0x18400004 0x18400008 $(srec_cat_le_cmd) 0x0 4 \ + -generate 0x18402000 0x18402004 $(srec_cat_le_cmd) 0x6b657963 4 \ + -generate 0x18402004 0x18402008 $(srec_cat_le_cmd) 0x00010010 4 \ + -generate 0x18402008 0x1840200c $(srec_cat_le_cmd) 0x0 4 \ + -generate 0x1840200c 0x18402010 $(srec_cat_le_cmd) 0x34040000 4 \ + -generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \ + -generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4 \ + -generate 0x18402018 0x1840201c $(srec_cat_le_cmd) 0x0 4 \ + -generate 0x1840201c 0x18402020 $(srec_cat_le_cmd) 0x0 4 +else ifneq ($(CONFIG_RCAR_GEN4),) quiet_cmd_srec_cat = SRECCAT $@ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \ @@ -106,10 +129,17 @@ quiet_cmd_srec_cat = SRECCAT $@ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 endif endif +endif spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin $(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}')) +u-boot-elf.scif: u-boot-elf.srec u-boot.bin + $(call cmd,srec_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}')) + +u-boot-elf.shdr: u-boot-elf.srec u-boot.bin + $(call cmd,srec_shdr_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}')) + # if srec_cat is present build u-boot-spl.scif by default has_srec_cat = $(call try-run,srec_cat -VERSion,y,n) INPUTS-$(has_srec_cat) += u-boot-spl.scif diff --git a/arch/arm/mach-renesas/cpu_info.c b/arch/arm/mach-renesas/cpu_info.c index f040d732a51..42183e2daa5 100644 --- a/arch/arm/mach-renesas/cpu_info.c +++ b/arch/arm/mach-renesas/cpu_info.c @@ -114,6 +114,8 @@ int arch_misc_init(void) int print_cpuinfo(void) { + const uintptr_t pfc_base = 0xe6060000; + void __iomem *rcar_m3nm3l_ident = (void __iomem *)pfc_base + 0x800; int i = renesas_cpuinfo_idx(); if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A7796 && @@ -123,6 +125,17 @@ int print_cpuinfo(void) return 0; } + /* + * M3Le PRR ID is the same as M3N , but PFC register 0x800 reads 0 + * on M3N and 1 on M3Le. Use this to discern M3Le from M3N . + */ + if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A77965 && + readl(rcar_m3nm3l_ident) == 1) { + printf("CPU: Renesas Electronics R8A779MD rev %d.%d\n", + renesas_get_cpu_rev_integer(), renesas_get_cpu_rev_fraction()); + return 0; + } + printf("CPU: Renesas Electronics %s rev %d.%d\n", get_cpu_name(i), renesas_get_cpu_rev_integer(), renesas_get_cpu_rev_fraction()); diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h index f9af3ef885a..35b0d00e45c 100644 --- a/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h @@ -9,7 +9,13 @@ /* * R-Car (R8A78000) I/O Addresses */ +#if defined(CONFIG_RCAR_64_RSIP) +/* Cortex-M33 address */ +#define TMU_BASE 0xC0680000 +#else +/* Cortex-A720AE address */ #define TMU_BASE 0x1C030000 +#endif /* Arm Generic Timer */ #define CNTCR_BASE 0x1C000FFF /* Region 0 */ diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index d24419f5daa..f7dc2be6cca 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -70,8 +70,8 @@ void enable_caches(void) /* Generate entires for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) @@ -114,8 +114,8 @@ void enable_caches(void) /* Generate entires for DRAM in 64bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c index 3b3c6f7cde9..5981b3c9c4d 100644 --- a/arch/arm/mach-renesas/memmap-rzg2l.c +++ b/arch/arm/mach-renesas/memmap-rzg2l.c @@ -67,8 +67,8 @@ void enable_caches(void) /* Generate entries for DRAM in 32bit address space */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = gd->bd->bi_dram[bank].start; - size = gd->bd->bi_dram[bank].size; + start = gd->dram[bank].start; + size = gd->dram[bank].size; /* Skip empty DRAM banks */ if (!size) diff --git a/arch/arm/mach-renesas/u-boot-rsip.lds b/arch/arm/mach-renesas/u-boot-rsip.lds new file mode 100644 index 00000000000..c5a74f8a608 --- /dev/null +++ b/arch/arm/mach-renesas/u-boot-rsip.lds @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <[email protected]> + */ + +#include <config.h> +#include <asm/psci.h> + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ +#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) + /* + * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not + * bundle with u-boot, and code offsets are fixed. Secure zone + * only needs to be copied from the loading address to + * CONFIG_ARMV7_SECURE_BASE, which is the linking and running + * address for secure code. + * + * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will + * be included in u-boot address space, and some absolute address + * were used in secure code. The absolute addresses of the secure + * code also needs to be relocated along with the accompanying u-boot + * code. + * + * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. + */ + /DISCARD/ : { *(.rel._secure*) } +#endif + . = 0x00000000; + + . = ALIGN(4); + __image_copy_start = ADDR(.text); + .text : + { + CPUDIR/start.o (.text*) + *(.vectors) + } + + /* This needs to come before *(.text*) */ + .efi_runtime : { + __efi_runtime_start = .; + *(.text.efi_runtime*) + *(.rodata.efi_runtime*) + *(.data.efi_runtime*) + __efi_runtime_stop = .; + } + + .text_rest : + { + *(.text*) + } + +#ifdef CONFIG_ARMV7_NONSEC + + /* Align the secure section only if we're going to use it in situ */ + .__secure_start +#ifndef CONFIG_ARMV7_SECURE_BASE + ALIGN(CONSTANT(COMMONPAGESIZE)) +#endif + : { + KEEP(*(.__secure_start)) + } + +#ifndef CONFIG_ARMV7_SECURE_BASE +#define __ARMV7_SECURE_BASE +#define __ARMV7_PSCI_STACK_IN_RAM +#else +#define __ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_BASE +#endif + + .secure_text __ARMV7_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + } + + .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) + { + *(._secure.data) + } + +#ifdef CONFIG_ARMV7_PSCI + .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data), + CONSTANT(COMMONPAGESIZE)) (NOLOAD) : +#ifdef __ARMV7_PSCI_STACK_IN_RAM + AT(ADDR(.secure_stack)) +#else + AT(LOADADDR(.secure_data) + SIZEOF(.secure_data)) +#endif + { + KEEP(*(.__secure_stack_start)) + + /* Skip addresses for stack */ + . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; + + /* Align end of stack section to page boundary */ + . = ALIGN(CONSTANT(COMMONPAGESIZE)); + + KEEP(*(.__secure_stack_end)) + +#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE + /* + * We are not checking (__secure_end - __secure_start) here, + * as these are the load addresses, and do not include the + * stack section. Instead, use the end of the stack section + * and the start of the text section. + */ + ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE, + "Error: secure section exceeds secure memory size"); +#endif + } + +#ifndef __ARMV7_PSCI_STACK_IN_RAM + /* Reset VMA but don't allocate space if we have secure SRAM */ + . = LOADADDR(.secure_stack); +#endif + +#endif + + .__secure_end : AT(ADDR(.__secure_end)) { + *(.__secure_end) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + __data_start = .; + *(.data*) + __data_end = .; + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); + } + + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.rel*.efi_runtime) + *(.rel*.efi_runtime.*) + __efi_runtime_rel_stop = .; + } + + . = ALIGN(8); + __image_copy_end = .; + + /* + * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start + * needs to be a multiple of 8 and we overlay .bss with .rel.dyn + */ + .rel.dyn ALIGN(8) : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + . = ALIGN(8); + } + + _end = .; + _image_binary_end = .; + +/* + * These sections occupy the same memory, but their lifetimes do + * not overlap: U-Boot initializes .bss only after applying dynamic + * relocations and therefore after it doesn't need .rel.dyn any more. + */ + + /* BSS goes to special read-write offset below U-Boot entry point */ + . = 0xb8400000; + .bss (OVERLAY): { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynbss) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu.hash) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } +} + +ASSERT(_image_binary_end % 8 == 0, \ + "_image_binary_end must be 8-byte aligned for device tree"); diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 108713488af..1a2e7847c9e 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -65,6 +65,7 @@ config ROCKCHIP_RK3066 config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD help The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 @@ -108,6 +109,7 @@ config ROCKCHIP_RK322X select TPL_OF_LIBFDT select TPL_HAVE_INIT_STACK if TPL select SPL_DRIVERS_MISC + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL imply SPL_ROCKCHIP_COMMON_BOARD @@ -605,8 +607,8 @@ config SPL_ROCKCHIP_BACK_TO_BROM depends on SPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, - SPL will return to the boot rom, which will then load the U-Boot - binary to keep going on. + SPL will return to the boot rom, which will then load the U-Boot + binary to keep going on. config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" @@ -616,8 +618,8 @@ config TPL_ROCKCHIP_BACK_TO_BROM depends on TPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, - SPL will return to the boot rom, which will then load the U-Boot - binary to keep going on. + SPL will return to the boot rom, which will then load the U-Boot + binary to keep going on. config ROCKCHIP_COMMON_BOARD bool "Rockchip common board file" @@ -659,7 +661,7 @@ config ROCKCHIP_BOOT_MODE_REG config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on PMIC_RK8XX - ---help--- + help Say Y here to prevent the device from booting up because of a plug-in event. When set, the device will boot briefly to determine why it was powered on, and if it was determined because of a plug-in event @@ -687,7 +689,7 @@ config ROCKCHIP_BROM_HELPER bool config SPL_ROCKCHIP_EARLYRETURN_TO_BROM - bool "SPL requires early-return (for RK3188-style BROM) to BROM" + bool "SPL requires early-return (for RK3188-style BROM) to BROM" depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK help Some Rockchip BROM variants (e.g. on the RK3188) load the @@ -708,7 +710,7 @@ config ROCKCHIP_DISABLE_FORCE_JTAG Rockchip SoCs can automatically switch between jtag and sdmmc based on the following rules: - all the SDMMC pins including SDMMC_DET set as SDMMC function in - GRF, + GRF, - force_jtag bit in GRF is 1, - SDMMC_DET is low (no card detected), @@ -725,7 +727,7 @@ config ROCKCHIP_DISABLE_FORCE_JTAG If unsure, say Y. config TPL_ROCKCHIP_EARLYRETURN_TO_BROM - bool "TPL requires early-return (for RK3188-style BROM) to BROM" + bool "TPL requires early-return (for RK3188-style BROM) to BROM" depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK help Some Rockchip BROM variants (e.g. on the RK3188) load the diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 2b57b166894..adba1b49a52 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -18,7 +18,7 @@ config TARGET_PX30_CORE * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam. * PX30.Core needs to mount on top of EDIMM2.2 for creating complete - PX30.Core EDIMM2.2 Starter Kit. + PX30.Core EDIMM2.2 Starter Kit. PX30.Core CTOUCH2: * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. @@ -39,7 +39,7 @@ config TARGET_RINGNECK_PX30 bool "Theobroma Systems PX30-uQ7 (Ringneck)" help The PX30-uQ7 (Ringneck) SoM is a uQseven-compatible (40mmx70mm, - MXM-230 connector) system-on-module from Theobroma Systems[1], + MXM-230 connector) system-on-module from Theobroma Systems[1], featuring the Rockchip PX30. It provides the following feature set: diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 9ad1f54055b..ba694093990 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -27,10 +27,10 @@ config SPL_SERIAL default y config TPL_STACK - default 0x10088000 + default 0x10088000 config TPL_TEXT_BASE - default 0x10081000 + default 0x10081000 source "board/rockchip/evb_rk3229/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 128ee362f8a..91e11910876 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -91,7 +91,7 @@ config TARGET_MIQI_RK3288 config TARGET_PHYCORE_RK3288 bool "phyCORE-RK3288" - select BOARD_LATE_INIT + select BOARD_LATE_INIT help Add basic support for the PCM-947 carrier board, a RK3288 based development board made by PHYTEC. This board works in a combination @@ -128,7 +128,7 @@ config TARGET_ROCK2 config TARGET_TINKER_RK3288 bool "Tinker-RK3288" - select BOARD_LATE_INIT + select BOARD_LATE_INIT select ROCKCHIP_COMMON_STACK_ADDR select TPL help @@ -173,7 +173,7 @@ config SPL_SERIAL default y config TPL_STACK - default 0xff718000 + default 0xff718000 config TPL_SYS_MALLOC_F_LEN default 0x2000 diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index b8d25c52542..540ddc93cd0 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -5,7 +5,7 @@ config TARGET_EVB_RK3308 select BOARD_LATE_INIT config TARGET_ROC_RK3308_CC - bool "Firefly roc-rk3308-cc" + bool "Firefly roc-rk3308-cc" select BOARD_LATE_INIT config ROCKCHIP_BOOT_MODE_REG diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index a7be30bbd89..6c6ca02c309 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -13,14 +13,14 @@ config TARGET_GEEKBOX bool "GeekBox" config TARGET_EVB_PX5 - bool "Evb-PX5" + bool "Evb-PX5" select ARCH_EARLY_INIT_R - help - PX5 EVB is designed by Rockchip for automotive field - with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS - HDMI video input/output interface, audio codec ES8396, - WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity - sensor STK3410. + help + PX5 EVB is designed by Rockchip for automotive field + with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS + HDMI video input/output interface, audio codec ES8396, + WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity + sensor STK3410. endchoice config ROCKCHIP_BOOT_MODE_REG @@ -49,9 +49,9 @@ config SPL_STACK_R_ADDR default 0x04000000 config TPL_STACK - default 0xff8cffff + default 0xff8cffff config TPL_TEXT_BASE - default 0xff8c1000 + default 0xff8c1000 endif diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 5c21b08a5ae..d84a9da8ed5 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -145,10 +145,10 @@ config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" config TPL_STACK - default 0xff8effff + default 0xff8effff config TPL_TEXT_BASE - default 0xff8c2000 + default 0xff8c2000 if BOOTCOUNT_LIMIT diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index f9bfc445b85..a39cb8be9a1 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -95,7 +95,7 @@ void rockchip_stimer_init(void) if (reg & TIMER_EN) return; - asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + asm volatile("msr cntfrq_el0, %x0" : : "r" (CONFIG_COUNTER_FREQUENCY)); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS index 393edd3984c..79cf9e97f70 100644 --- a/arch/arm/mach-rockchip/rk3576/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -10,6 +10,12 @@ S: Maintained F: arch/arm/dts/rk3576-nanopi-m5* F: configs/nanopi-m5-rk3576_defconfig +NANOPI-R76S-RK3576 +M: Jonas Karlman <[email protected]> +S: Maintained +F: arch/arm/dts/rk3576-nanopi-r76s* +F: configs/nanopi-r76s-rk3576_defconfig + OMNI3576-RK3576 M: Jonas Karlman <[email protected]> S: Maintained diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index c17ba418ced..e3e93f66395 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -49,6 +49,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0", [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", + [BROM_BOOTSOURCE_UFS] = "/soc/ufshc@2a2d0000", }; static struct mm_region rk3576_mem_map[] = { @@ -130,7 +131,7 @@ void rockchip_stimer_init(void) if (reg & TIMER_EN) return; - asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + asm volatile("msr cntfrq_el0, %x0" : : "r" (CONFIG_COUNTER_FREQUENCY)); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index eedce7b9b08..f69792670d0 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -167,7 +167,7 @@ void rockchip_stimer_init(void) if (reg & TIMER_EN) return; - asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + asm volatile("msr cntfrq_el0, %x0" : : "r" (CONFIG_COUNTER_FREQUENCY)); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); @@ -243,14 +243,14 @@ int arch_cpu_init(void) int rockchip_dram_init_banksize_fixup(struct bd_info *bd) { - size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size; + size_t ram_top = gd->dram[1].start + gd->dram[1].size; if (ram_top > DRAM_GAP_START) { - bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start; + gd->dram[1].size = DRAM_GAP_START - gd->dram[1].start; if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) { - bd->bi_dram[2].start = DRAM_GAP_END; - bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start; + gd->dram[2].start = DRAM_GAP_END; + gd->dram[2].size = ram_top - gd->dram[2].start; } } diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig index 43eeaa9c449..d066df9a86e 100644 --- a/arch/arm/mach-rockchip/rv1126/Kconfig +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -47,7 +47,7 @@ config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl.lds" config TPL_STACK - default 0xff718000 + default 0xff718000 config TPL_SYS_MALLOC_F_LEN default 0x2000 diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index ea0e3621af7..2e404df1b20 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -171,7 +171,7 @@ static int rockchip_dram_init_banksize(void) /* * Rockchip guaranteed DDR_MEM is ordered so no need to worry about - * bi_dram order. + * dram order. */ for (i = 0, j = 0; i < ddr_info->count; i++, j++) { phys_size_t size = ddr_info->bank[(i + ddr_info->count)]; @@ -261,8 +261,8 @@ static int rockchip_dram_init_banksize(void) * split the region in two, one for before the * reserved memory area and one for after. */ - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = rsrv_start - start_addr; + gd->dram[j].start = start_addr; + gd->dram[j].size = rsrv_start - start_addr; j++; @@ -281,8 +281,8 @@ static int rockchip_dram_init_banksize(void) return -ENOMEM; } - gd->bd->bi_dram[j].start = start_addr; - gd->bd->bi_dram[j].size = size; + gd->dram[j].start = start_addr; + gd->dram[j].size = size; } return 0; @@ -294,10 +294,20 @@ __weak int rockchip_dram_init_banksize_fixup(struct bd_info *bd) return 0; } +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + /* Make sure U-Boot only uses the space below the 4G address boundary */ + u64 usable_top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G); + + return (gd->ram_top > usable_top) ? usable_top : gd->ram_top; +} + int dram_init_banksize(void) { - size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE); - size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top)); + /* Make sure first bank uses the space below the 4G address boundary */ + u64 usable_top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G); + size_t ram_top = (unsigned long)(CFG_SYS_SDRAM_BASE + gd->ram_size); + size_t top = min((unsigned long)ram_top, (unsigned long)(usable_top)); #ifdef CONFIG_ARM64 int ret = rockchip_dram_init_banksize(); @@ -309,15 +319,15 @@ int dram_init_banksize(void) ret); /* Reserve 2M for ATF bl31 */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M; + gd->dram[0].size = top - gd->dram[0].start; /* Add usable memory beyond the blob of space for peripheral near 4GB */ if (ram_top > SZ_4G && top < SZ_4G) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = ram_top - gd->dram[1].start; } else if (ram_top > SZ_4G && top == SZ_4G) { - gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start; + gd->dram[0].size = ram_top - gd->dram[0].start; } #else #ifdef CONFIG_SPL_OPTEE_IMAGE @@ -327,23 +337,23 @@ int dram_init_banksize(void) TRUST_PARAMETER_OFFSET); if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = tos_parameter->tee_mem.phy_addr - CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + + gd->dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].size = top - gd->dram[1].start; } else { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x8400000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE - + gd->bd->bi_dram[0].size + 0x2000000; - gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; + gd->dram[1].start = CFG_SYS_SDRAM_BASE + + gd->dram[0].size + 0x2000000; + gd->dram[1].size = top - gd->dram[1].start; } #else - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = top - gd->dram[0].start; #endif #endif @@ -507,11 +517,3 @@ int dram_init(void) return 0; } - -phys_addr_t board_get_usable_ram_top(phys_size_t total_size) -{ - /* Make sure U-Boot only uses the space below the 4G address boundary */ - u64 top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G); - - return (gd->ram_top > top) ? top : gd->ram_top; -} diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 6572dde29f6..d2dd5e10935 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -76,6 +76,9 @@ static int spl_node_to_boot_device(int node) if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) return BOOT_DEVICE_SPI; + if (!uclass_find_device_by_of_offset(UCLASS_UFS, node, &parent)) + return BOOT_DEVICE_UFS; + return -1; } @@ -231,6 +234,17 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen) return -ENODEV; } + if (boot_device == BOOT_DEVICE_UFS) { + ret = uclass_find_device(UCLASS_UFS, 0, &dev); + if (ret) { + debug("%s: could not find device for UFS: %d\n", + __func__, ret); + return ret; + } + + return ofnode_get_path(dev_ofnode(dev), buf, buflen); + } + #if CONFIG_IS_ENABLED(BLK) dev_num = (boot_device == BOOT_DEVICE_MMC1) ? 0 : 1; diff --git a/arch/arm/mach-sc5xx/Kconfig b/arch/arm/mach-sc5xx/Kconfig index cfa7ed46a82..0f4e63a355e 100644 --- a/arch/arm/mach-sc5xx/Kconfig +++ b/arch/arm/mach-sc5xx/Kconfig @@ -25,7 +25,7 @@ config SC57X bool "SC57x series" select COMMON_CLK_ADI_SC57X select CPU_V7A - select TARGET_SC573_EZKIT + select TARGET_SC573_EZLITE config SC58X bool "SC58x series" @@ -51,8 +51,8 @@ endchoice if SC57X -config TARGET_SC573_EZKIT - bool "Support SC573-EZKIT" +config TARGET_SC573_EZLITE + bool "Support SC573-EZLITE" endif @@ -116,69 +116,6 @@ endchoice endif -config SC5XX_UBOOT_SPL_OFFSET - hex "SPL offset" - default 0x0 - help - The default offset where the SPL is located. - -config SC5XX_UBOOT_OFFSET - hex "U-Boot offset" - default 0x40000 - help - The default offset where u-boot is located. - -config SC5XX_FITIMAGE_OFFSET - hex "FitImage offset" - default 0x1a0000 - help - The default offset where the fitImage is located. - -config SC5XX_ROOTFS_OFFSET - hex "RootFS offset" - default 0x102000 - help - The default offset where the rootfs is located. - -config SC5XX_LOADADDR - hex "Load address" - default 0x90000000 - help - The default load address for u-boot. - -menu "Binman configuration" -config SC5XX_USE_BINMAN - bool "Use binman for final image" - select BINMAN - help - If you wish to use binman to assemble an image, say 'Y' here. - This will enable binman-specific sections in the device tree. - -config SC5XX_BINMAN_FILENAME - string "Image name" - default "sc5xx-image.img" - depends on SC5XX_USE_BINMAN - help - The name of the image that will be created by binman. - This is used to create the final image. - -config SC5XX_FITIMAGE_NAME - string "FitImage name" - default "fitImage" - depends on SC5XX_USE_BINMAN - help - The name of the fitImage to be packed by binman. - This is used to create the final image. - -config SC5XX_ROOTFS_NAME - string "RootFS name" - default "rootfs" - depends on SC5XX_USE_BINMAN - help - The name of the rootfs to be packed by binman. - This is used to create the final image. -endmenu - config ADI_IMAGE string "ADI fitImage type" help @@ -633,6 +570,6 @@ source "board/adi/sc594-som-ezlite/Kconfig" source "board/adi/sc589-ezkit/Kconfig" source "board/adi/sc589-mini/Kconfig" source "board/adi/sc584-ezkit/Kconfig" -source "board/adi/sc573-ezkit/Kconfig" +source "board/adi/sc573-ezlite/Kconfig" endif diff --git a/arch/arm/mach-sc5xx/init/dmcinit.c b/arch/arm/mach-sc5xx/init/dmcinit.c index 12052613feb..2026735cc21 100644 --- a/arch/arm/mach-sc5xx/init/dmcinit.c +++ b/arch/arm/mach-sc5xx/init/dmcinit.c @@ -101,7 +101,7 @@ #ifdef CONFIG_TARGET_SC584_EZKIT #define DMC_PADCTL2_VALUE 0x0078283C -#elif CONFIG_TARGET_SC573_EZKIT +#elif CONFIG_TARGET_SC573_EZLITE #define DMC_PADCTL2_VALUE 0x00782828 #elif CONFIG_TARGET_SC589_MINI || CONFIG_TARGET_SC589_EZKIT #define DMC_PADCTL2_VALUE 0x00783C3C diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 5fb3240acc5..35735f1551c 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -73,19 +73,19 @@ static int ddr_bank_cmp(const void *v1, const void *v2) } /* This has to be done post-relocation since gd->bd isn't preserved */ -static void qcom_configure_bi_dram(void) +static void qcom_configure_dram(void) { int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = prevbl_ddr_banks[i].start; - gd->bd->bi_dram[i].size = prevbl_ddr_banks[i].size; + gd->dram[i].start = prevbl_ddr_banks[i].start; + gd->dram[i].size = prevbl_ddr_banks[i].size; } } int dram_init_banksize(void) { - qcom_configure_bi_dram(); + qcom_configure_dram(); return 0; } @@ -555,6 +555,11 @@ int board_late_init(void) fdt_status |= !lmb_alloc(SZ_2M, &addr) ? env_set_hex("fdt_addr_r", addr) : 1; + if (IS_ENABLED(CONFIG_OF_LIBFDT_OVERLAY)) { + status |= !lmb_alloc(SZ_1M, &addr) ? + env_set_hex("fdtoverlay_addr_r", addr) : 1; + } + if (status || fdt_status) log_warning("%s: Failed to set run time variables\n", __func__); @@ -589,15 +594,15 @@ static void build_mem_map(void) */ mem_map[0].phys = 0x1000; mem_map[0].virt = mem_map[0].phys; - mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys; + mem_map[0].size = gd->dram[0].start - mem_map[0].phys; mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; - for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->bd->bi_dram[j].size; i++, j++) { - mem_map[i].phys = gd->bd->bi_dram[j].start; + for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 && gd->dram[j].size; i++, j++) { + mem_map[i].phys = gd->dram[j].start; mem_map[i].virt = mem_map[i].phys; - mem_map[i].size = gd->bd->bi_dram[j].size; + mem_map[i].size = gd->dram[j].size; mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \ PTE_BLOCK_INNER_SHARE; } diff --git a/arch/arm/mach-snapdragon/of_fixup.c b/arch/arm/mach-snapdragon/of_fixup.c index 5b6076ea8e5..374e6262db4 100644 --- a/arch/arm/mach-snapdragon/of_fixup.c +++ b/arch/arm/mach-snapdragon/of_fixup.c @@ -4,7 +4,7 @@ * * This file implements runtime fixups for Qualcomm DT to improve * compatibility with U-Boot. This includes adjusting the USB nodes - * to only use USB high-speed. + * to only use USB high-speed if SSPHY driver is not available. * * We use OF_LIVE for this rather than early FDT fixup for a couple * of reasons: it has a much nicer API, is most likely more efficient, @@ -21,26 +21,108 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dm/of_access.h> #include <dm/of.h> +#include <dm/device.h> +#include <dm/lists.h> #include <event.h> #include <fdt_support.h> #include <linux/errno.h> +#include <linker_lists.h> #include <stdlib.h> +#include <tee/optee.h> #include <time.h> -/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3 - * USB controllers. Rather than requiring source level DT changes, we fix up - * DT here. This improves compatibility with upstream DT and simplifies the - * porting process for new devices. +/** + * find_ssphy_node() - Find the super-speed PHY node referenced by DWC3 + * @dwc3: DWC3 device node + * + * Returns: Pointer to SS-PHY node if found, NULL otherwise */ +static struct device_node *find_ssphy_node(struct device_node *dwc3) +{ + const __be32 *phandles; + const char *phy_name; + int len, i, ret; + + phandles = of_get_property(dwc3, "phys", &len); + if (!phandles) + return NULL; + + len /= sizeof(*phandles); + + /* Iterate through PHY phandles to find the SS-PHY */ + for (i = 0; i < len; i++) { + ret = of_property_read_string_index(dwc3, "phy-names", i, &phy_name); + if (ret) + continue; + + /* Check if this is the super-speed PHY */ + if (!strncmp("usb3-phy", phy_name, strlen("usb3-phy")) || + !strncmp("usb3_phy", phy_name, strlen("usb3_phy"))) { + return of_find_node_by_phandle(NULL, be32_to_cpu(phandles[i])); + } + } + + return NULL; +} + +/** + * has_driver_for_node() - Check if any PHY driver can bind to this node + * @np: Device node to check + * + * Returns: true if a PHY driver with matching compatible string exists, false otherwise + */ +static bool has_driver_for_node(struct device_node *np) +{ + struct driver *driver = ll_entry_start(struct driver, driver); + const int n_ents = ll_entry_count(struct driver, driver); + const char *compat_list, *compat; + int compat_length, i; + struct driver *entry; + + if (!np) + return false; + + /* Get compatible strings from the node */ + compat_list = of_get_property(np, "compatible", &compat_length); + if (!compat_list) + return false; + + /* Check each compatible string against PHY drivers only */ + for (i = 0; i < compat_length; i += strlen(compat) + 1) { + compat = compat_list + i; + + /* Iterate through all registered drivers */ + for (entry = driver; entry != driver + n_ents; entry++) { + const struct udevice_id *of_match = entry->of_match; + + /* Skip non-PHY drivers to improve performance */ + if (entry->id != UCLASS_PHY) + continue; + + if (!of_match) + continue; + + while (of_match->compatible) { + if (!strcmp(of_match->compatible, compat)) { + debug("Found PHY driver '%s' for SS-PHY compatible '%s'\n", + entry->name, compat); + return true; + } + of_match++; + } + } + } + + return false; +} + static int fixup_qcom_dwc3(struct device_node *root, struct device_node *glue_np, bool flat) { - struct device_node *dwc3; + struct device_node *dwc3, *ssphy_np; int ret, len, hsphy_idx = 1; const __be32 *phandles; const char *second_phy_name; - debug("Fixing up %s\n", glue_np->name); - /* New DT flattens the glue and controller into a single node. */ if (flat) { dwc3 = glue_np; @@ -54,30 +136,43 @@ static int fixup_qcom_dwc3(struct device_node *root, struct device_node *glue_np } } - /* Tell the glue driver to configure the wrapper for high-speed only operation */ - ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL); - if (ret) { - log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': %d\n", ret); - return ret; - } + debug("Checking USB configuration for %s\n", dwc3->name); phandles = of_get_property(dwc3, "phys", &len); len /= sizeof(*phandles); if (len == 1) { - log_debug("Only one phy, not a superspeed controller\n"); + debug("Only one phy, not a superspeed controller\n"); return 0; } - /* Figure out if the superspeed phy is present and if so then which phy is it? */ + /* Figure out if the superspeed phy is present */ ret = of_property_read_string_index(dwc3, "phy-names", 1, &second_phy_name); if (ret == -ENODATA) { - log_debug("Only one phy, not a super-speed controller\n"); + debug("Only one phy, not a super-speed controller\n"); return 0; } else if (ret) { log_err("Failed to read second phy name: %d\n", ret); return ret; } + /* Find the super-speed PHY node and check if a driver is available */ + ssphy_np = find_ssphy_node(dwc3); + if (ssphy_np && has_driver_for_node(ssphy_np)) { + debug("Skipping USB fixup for %s (SS-PHY driver available)\n", + dwc3->name); + return 0; + } + + /* No driver available - apply the fixup */ + debug("Applying USB high-speed fixup to %s\n", dwc3->name); + + /* Tell the glue driver to configure the wrapper for high-speed only operation */ + ret = of_write_prop(dwc3, "qcom,select-utmi-as-pipe-clk", 0, NULL); + if (ret) { + log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': %d\n", ret); + return ret; + } + /* * Determine which phy is the superspeed phy by checking the name of the second phy * since it is typically the superspeed one. @@ -134,33 +229,34 @@ static void fixup_usb_nodes(struct device_node *root) } } -/* Remove all references to the rpmhpd device */ -static void fixup_power_domains(struct device_node *root) +static void add_optee_node(struct device_node *root) { - struct device_node *pd = NULL, *np = NULL; - struct property *prop; - const __be32 *val; + struct device_node *fw = NULL, *optee = NULL; + int ret; - /* All Qualcomm platforms name the rpm(h)pd "power-controller" */ - for_each_of_allnodes_from(root, pd) { - if (pd->name && !strcmp("power-controller", pd->name)) - break; + fw = of_find_node_by_path("/firmware"); + if (!fw) { + log_err("Failed to find /firmware node\n"); + return; } - /* Sanity check that this is indeed a power domain controller */ - if (!of_find_property(pd, "#power-domain-cells", NULL)) { - log_err("Found power-controller but it doesn't have #power-domain-cells\n"); + ret = of_add_subnode(fw, "optee", strlen("optee") + 1, &optee); + if (ret) { + log_err("Failed to add 'optee' subnode: %d\n", ret); return; } - /* Remove all references to the power domain controller */ - for_each_of_allnodes_from(root, np) { - if (!(prop = of_find_property(np, "power-domains", NULL))) - continue; + ret = of_write_prop(optee, "compatible", strlen("linaro,optee-tz") + 1, + "linaro,optee-tz"); + if (ret) { + log_err("Failed to add optee 'compatible' property: %d\n", ret); + return; + } - val = prop->value; - if (val[0] == cpu_to_fdt32(pd->phandle)) - of_remove_property(np, prop); + ret = of_write_prop(optee, "method", strlen("smc") + 1, "smc"); + if (ret) { + log_err("Failed to add optee 'method' property: %d\n", ret); + return; } } @@ -176,7 +272,9 @@ static int qcom_of_fixup_nodes(void * __maybe_unused ctx, struct event *event) struct device_node *root = event->data.of_live_built.root; time_call(fixup_usb_nodes, root); - time_call(fixup_power_domains, root); + + if (IS_ENABLED(CONFIG_OPTEE) && is_optee_smc_api()) + time_call(add_optee_node, root); return 0; } diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index fb98b647442..a9b639a5ed9 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -15,8 +15,8 @@ config SOCFPGA_SECURE_VAB_AUTH select SHA512 select SPL_FIT_IMAGE_POST_PROCESS help - All images loaded from FIT will be authenticated by Secure Device - Manager. + All images loaded from FIT will be authenticated by Secure Device + Manager. config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE bool "Allow non-FIT VAB signed images" diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 4d7f0b9a79c..b202ca258bc 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -202,11 +202,10 @@ void board_prep_linux(struct bootm_headers *images) void lmb_arch_add_memory(void) { int i; - struct bd_info *bd = gd->bd; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (bd->bi_dram[i].size) - lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size); + if (gd->dram[i].size) + lmb_add(gd->dram[i].start, gd->dram[i].size); } } #endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7e0f3875b7c..338f73d6e73 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -246,7 +246,6 @@ int qspi_flash_software_reset(void) void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; u32 start, size; int i; @@ -261,11 +260,11 @@ void dram_bank_mmu_setup(int bank) * The default implementation of this function allows the DRAM dcache * to be enabled only after relocation. However, to speed up ECC * initialization, we want to be able to enable DRAM dcache before - * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram + * relocation, so we don't check GD_FLG_RELOC (this assumes gd->dram * is set first). */ - start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + start = gd->dram[bank].start >> MMU_SECTION_SHIFT; + size = gd->dram[bank].size >> MMU_SECTION_SHIFT; for (i = start; i < start + size; i++) set_section_dcache(i, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index d9e264024c8..df26e7b8ef2 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -14,7 +14,7 @@ config TARGET_STIH410_B2260 Specifications. Features: - 1GB DDR - On-Board USB combo WiFi/Bluetooth RTL8723BU - with PCB soldered antenna + with PCB soldered antenna - Ethernet 1000-BaseT - Sata - HDMI diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index de9d8547e61..1c6de559142 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -10,7 +10,6 @@ config STM32F4 select PINCTRL_STM32 select RAM select STM32_RCC - select STM32_RESET select STM32_SDRAM select STM32_SERIAL select STM32_TIMER @@ -27,7 +26,6 @@ config STM32F7 select PINCTRL_STM32 select RAM select STM32_RCC - select STM32_RESET select STM32_SDRAM select STM32_SERIAL select STM32_TIMER @@ -47,7 +45,6 @@ config STM32H7 select RAM select REGMAP select STM32_RCC - select STM32_RESET select STM32_SDRAM select STM32_SERIAL select STM32_TIMER diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 31b2746379d..f45010ddbd0 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -50,15 +50,14 @@ config STM32MP13X select OF_BOARD_SETUP select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select SUPPORT_SPL if !TFABOOT select SYS_ARCH_TIMER imply CMD_NVEDIT_INFO imply OF_UPSTREAM help - support of STMicroelectronics SOC STM32MP13x family - STMicroelectronics MPU with core ARMv7 + support of STMicroelectronics SOC STM32MP13x family + STMicroelectronics MPU with core ARMv7 config STM32MP15X bool "Support STMicroelectronics STM32MP15x Soc" @@ -72,17 +71,16 @@ config STM32MP15X select OF_BOARD_SETUP select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select SUPPORT_SPL select SYS_ARCH_TIMER imply CMD_NVEDIT_INFO imply OF_UPSTREAM help - support of STMicroelectronics SOC STM32MP15x family - STM32MP157, STM32MP153 or STM32MP151 - STMicroelectronics MPU with core ARMv7 - dual core A7 for STM32MP157/3, monocore for STM32MP151 + support of STMicroelectronics SOC STM32MP15x family + STM32MP157, STM32MP153 or STM32MP151 + STMicroelectronics MPU with core ARMv7 + dual core A7 for STM32MP157/3, monocore for STM32MP151 config STM32MP21X bool "Support STMicroelectronics STM32MP21x Soc" @@ -91,7 +89,6 @@ config STM32MP21X select OF_BOARD select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select STM32MP_TAMP_NVMEM select SYS_ARCH_TIMER @@ -107,8 +104,8 @@ config STM32MP21X imply TEE imply VERSION_VARIABLE help - Support of STMicroelectronics SOC STM32MP21X family - STMicroelectronics MPU with 1 A35 core and 1 M33 core + Support of STMicroelectronics SOC STM32MP21X family + STMicroelectronics MPU with 1 A35 core and 1 M33 core config STM32MP23X bool "Support STMicroelectronics STM32MP23x Soc" @@ -117,7 +114,6 @@ config STM32MP23X select OF_BOARD select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select STM32MP_TAMP_NVMEM select SYS_ARCH_TIMER @@ -133,8 +129,8 @@ config STM32MP23X imply TEE imply VERSION_VARIABLE help - Support of STMicroelectronics SOC STM32MP23x family - STMicroelectronics MPU with 2 * A53 core and 1 M33 core + Support of STMicroelectronics SOC STM32MP23x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core config STM32MP25X bool "Support STMicroelectronics STM32MP25x Soc" @@ -143,7 +139,6 @@ config STM32MP25X select OF_BOARD select PINCTRL_STM32 select STM32_RCC - select STM32_RESET select STM32_SERIAL select SYS_ARCH_TIMER select TFABOOT @@ -158,8 +153,8 @@ config STM32MP25X imply TEE imply VERSION_VARIABLE help - Support of STMicroelectronics SOC STM32MP25x family - STMicroelectronics MPU with 2 * A53 core and 1 M33 core + Support of STMicroelectronics SOC STM32MP25x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core endchoice config NR_DRAM_BANKS @@ -169,13 +164,13 @@ config DDR_CACHEABLE_SIZE hex "Size of the DDR marked cacheable in pre-reloc stage" default 0x40000000 help - Define the size of the DDR marked as cacheable in U-Boot - pre-reloc stage. - This option can be useful to avoid speculatif access - to secured area of DDR used by TF-A or OP-TEE before U-Boot - initialization. - The areas marked "no-map" in device tree should be located - before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. + Define the size of the DDR marked as cacheable in U-Boot + pre-reloc stage. + This option can be useful to avoid speculatif access + to secured area of DDR used by TF-A or OP-TEE before U-Boot + initialization. + The areas marked "no-map" in device tree should be located + before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 hex "Partition on MMC2 to use to load U-Boot from" @@ -208,10 +203,10 @@ config CMD_STM32KEY bool "command stm32key to fuse public key hash" depends on CMDLINE help - fuse public key hash in corresponding fuse used to authenticate - binary. - This command is used to evaluate the secure boot on stm32mp SOC, - it is deactivated by default in real products. + fuse public key hash in corresponding fuse used to authenticate + binary. + This command is used to evaluate the secure boot on stm32mp SOC, + it is deactivated by default in real products. config MFD_STM32_TIMERS bool "STM32 multifonction timer support" @@ -231,15 +226,15 @@ config STM32MP15_PWR depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X) default y if STM32MP15X help - This config enables implementation of driver-model pmic and - regulator uclass features for access to STM32MP15x PWR. + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR. config SPL_STM32MP15_PWR bool "Enable driver for STM32MP15x PWR in SPL" depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || STM32MP15X) default y if STM32MP15X help - This config enables implementation of driver-model pmic and - regulator uclass features for access to STM32MP15x PWR in SPL. + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR in SPL. endif diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 647e0a4c2bf..5ae57d13340 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -10,10 +10,10 @@ config CMD_STM32PROG imply DFU_MMC if MMC imply DFU_MTD if MTD help - activate a specific command stm32prog for STM32MP soc family - witch update the device with the tools STM32CubeProgrammer - NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based - on U-Boot DFU framework + activate a specific command stm32prog for STM32MP soc family + witch update the device with the tools STM32CubeProgrammer + NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based + on U-Boot DFU framework config CMD_STM32PROG_USB bool "support stm32prog over USB" @@ -21,9 +21,9 @@ config CMD_STM32PROG_USB depends on USB_GADGET_DOWNLOAD default y help - activate the command "stm32prog usb" for STM32MP soc family - witch update the device with the tools STM32CubeProgrammer, - using USB with DFU protocol + activate the command "stm32prog usb" for STM32MP soc family + witch update the device with the tools STM32CubeProgrammer, + using USB with DFU protocol config CMD_STM32PROG_SERIAL bool "support stm32prog over UART" @@ -32,13 +32,13 @@ config CMD_STM32PROG_SERIAL imply SILENT_CONSOLE default y help - activate the command "stm32prog serial" for STM32MP soc family - with the tools STM32CubeProgrammer using U-Boot serial device - and UART protocol. + activate the command "stm32prog serial" for STM32MP soc family + with the tools STM32CubeProgrammer using U-Boot serial device + and UART protocol. config CMD_STM32PROG_OTP bool "support stm32prog for OTP update" depends on CMD_STM32PROG default y if ARM_SMCCC || OPTEE help - Support the OTP update with the command "stm32prog" for STM32MP + Support the OTP update with the command "stm32prog" for STM32MP diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 835eaf48dfa..76c324b55ae 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -825,8 +825,8 @@ static int init_device(struct stm32prog_data *data, dev->mtd = mtd; break; case STM32PROG_RAM: - first_addr = gd->bd->bi_dram[0].start; - last_addr = first_addr + gd->bd->bi_dram[0].size; + first_addr = gd->dram[0].start; + last_addr = first_addr + gd->dram[0].size; dev->erase_size = 1; break; default: diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 7f349f3b68d..42e3735847a 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -135,6 +135,9 @@ enum forced_boot_mode { /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) +#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) +#define TAMP_FWU_BOOT_IDX_OFFSET 0 + #ifdef CONFIG_STM32MP15X #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) @@ -144,9 +147,6 @@ enum forced_boot_mode { #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21) -#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) - -#define TAMP_FWU_BOOT_IDX_OFFSET 0 #define TAMP_COPRO_STATE_OFF 0 #define TAMP_COPRO_STATE_INIT 1 #define TAMP_COPRO_STATE_CRUN 2 @@ -196,8 +196,6 @@ enum forced_boot_mode { /* TAMP registers zone 3 RIF 1 (RW) at 96*/ #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) -#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) -#define TAMP_FWU_BOOT_IDX_OFFSET 0 #endif /* defined(CONFIG_STM32MP21X) || defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */ /* offset used for BSEC driver: misc_read and misc_write */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index a875907ac3e..05ce869c428 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -61,20 +61,20 @@ /* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ #define CPU_STM32MP257Cxx 0x00002000 #define CPU_STM32MP255Cxx 0x00082000 -#define CPU_STM32MP253Cxx 0x000B2004 -#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP253Cxx 0x000B300C +#define CPU_STM32MP251Cxx 0x000B306D #define CPU_STM32MP257Axx 0x40002E00 #define CPU_STM32MP255Axx 0x40082E00 -#define CPU_STM32MP253Axx 0x400B2E04 -#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP253Axx 0x400B3E0C +#define CPU_STM32MP251Axx 0x400B3E6D #define CPU_STM32MP257Fxx 0x80002000 #define CPU_STM32MP255Fxx 0x80082000 -#define CPU_STM32MP253Fxx 0x800B2004 -#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP253Fxx 0x800B300C +#define CPU_STM32MP251Fxx 0x800B306D #define CPU_STM32MP257Dxx 0xC0002E00 #define CPU_STM32MP255Dxx 0xC0082E00 -#define CPU_STM32MP253Dxx 0xC00B2E04 -#define CPU_STM32MP251Dxx 0xC00B3E65 +#define CPU_STM32MP253Dxx 0xC00B3E0C +#define CPU_STM32MP251Dxx 0xC00B3E6D /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); diff --git a/arch/arm/mach-stm32mp/soc.c b/arch/arm/mach-stm32mp/soc.c index fa56b0d2e0f..67be55e3381 100644 --- a/arch/arm/mach-stm32mp/soc.c +++ b/arch/arm/mach-stm32mp/soc.c @@ -64,7 +64,7 @@ __weak int setup_mac_address(void) struct udevice *dev; int nb_eth, nb_otp, index; - if (!IS_ENABLED(CONFIG_NET)) + if (!IS_ENABLED(CONFIG_NET_LEGACY)) return 0; nb_eth = get_eth_nb(); diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 252aef1852e..4d81c70b230 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -52,7 +52,6 @@ u32 get_bootauth(void) */ void dram_bank_mmu_setup(int bank) { - struct bd_info *bd = gd->bd; int i; phys_addr_t start; phys_addr_t addr; @@ -67,9 +66,9 @@ void dram_bank_mmu_setup(int bank) size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); #endif } else if (gd->flags & GD_FLG_RELOC) { - /* bd->bi_dram is available only after relocation */ - start = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + /* gd->dram is available only after relocation */ + start = gd->dram[bank].start; + size = gd->dram[bank].size; use_lmb = true; } else { /* mark cacheable and executable the beggining of the DDR */ diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index e63bdaaf42f..d2e41b8e65f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -90,11 +90,6 @@ void spl_display_print(void) } #endif -__weak int board_early_init_f(void) -{ - return 0; -} - uint32_t stm32mp_get_dram_size(void) { struct ram_info ram; @@ -204,10 +199,12 @@ void board_init_f(ulong dummy) /* enable console uart printing */ preloader_console_init(); - ret = board_early_init_f(); - if (ret) { - log_debug("board_early_init_f() failed: %d\n", ret); - hang(); + if (IS_ENABLED(CONFIG_BOARD_EARLY_INIT_F)) { + ret = board_early_init_f(); + if (ret) { + log_debug("board_early_init_f() failed: %d\n", ret); + hang(); + } } ret = uclass_get_device(UCLASS_RAM, 0, &dev); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 89f0e77bcdb..5ace74567dd 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -151,7 +151,6 @@ config DRAM_SUNXI_TPR3 config DRAM_SUNXI_TPR6 hex "DRAM TPR6 parameter" - default 0x3300c080 help TPR6 value from vendor DRAM settings. @@ -224,11 +223,11 @@ config SUNXI_SRAM_ADDRESS default 0x44000 if MACH_SUN55I_A523 default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2 default 0x0 - ---help--- - Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, - with the first SRAM region being located at address 0. - Some newer SoCs map the boot ROM at address 0 instead and move the - SRAM to a different address. + help + Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, + with the first SRAM region being located at address 0. + Some newer SoCs map the boot ROM at address 0 instead and move the + SRAM to a different address. config SUNXI_RVBAR_ADDRESS hex @@ -237,26 +236,26 @@ config SUNXI_RVBAR_ADDRESS default 0x08000040 if MACH_SUN55I_A523 default 0x09010040 if SUN50I_GEN_H6 default 0x017000a0 - ---help--- - The read-only RVBAR system register holds the address of the first - instruction to execute after a reset. Allwinner cores provide a - writable MMIO backing store for this register, to allow to set the - entry point when switching to AArch64. This store is on different - addresses, depending on the SoC. + help + The read-only RVBAR system register holds the address of the first + instruction to execute after a reset. Allwinner cores provide a + writable MMIO backing store for this register, to allow to set the + entry point when switching to AArch64. This store is on different + addresses, depending on the SoC. config SUNXI_RVBAR_ALTERNATIVE hex depends on ARM64 default 0x08100040 if MACH_SUN50I_H616 default SUNXI_RVBAR_ADDRESS - ---help--- - The H616 die exists in at least two variants, with one having the - RVBAR registers at a different address. If the SoC variant ID - (stored in SRAM_VER_REG[7:0]) is not 0, we need to use the - other address. - Set this alternative address to the same as the normal address - for all other SoCs, so the content of the SRAM_VER_REG becomes - irrelevant there, and we can use the same code. + help + The H616 die exists in at least two variants, with one having the + RVBAR registers at a different address. If the SoC variant ID + (stored in SRAM_VER_REG[7:0]) is not 0, we need to use the + other address. + Set this alternative address to the same as the normal address + for all other SoCs, so the content of the SRAM_VER_REG becomes + irrelevant there, and we can use the same code. config SUNXI_BL31_BASE hex @@ -283,16 +282,16 @@ config SUNXI_A64_TIMER_ERRATUM # not supported by Kconfig config SUNXI_GEN_SUN4I bool - ---help--- - Select this for sunxi SoCs which have resets and clocks set up - as the original A10 (mach-sun4i). + help + Select this for sunxi SoCs which have resets and clocks set up + as the original A10 (mach-sun4i). config SUNXI_GEN_SUN6I bool - ---help--- - Select this for sunxi SoCs which have sun6i like periphery, like - separate ahb reset control registers, custom pmic bus, new style - watchdog, etc. + help + Select this for sunxi SoCs which have sun6i like periphery, like + separate ahb reset control registers, custom pmic bus, new style + watchdog, etc. config SUN50I_GEN_H6 bool @@ -300,38 +299,38 @@ config SUN50I_GEN_H6 select SPL_LOAD_FIT if SPL select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL - ---help--- - Select this for sunxi SoCs which have H6 like peripherals, clocks - and memory map. + help + Select this for sunxi SoCs which have H6 like peripherals, clocks + and memory map. config SUNXI_GEN_NCAT2 bool select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL - ---help--- - Select this for sunxi SoCs which have D1 like peripherals, clocks - and memory map. + help + Select this for sunxi SoCs which have D1 like peripherals, clocks + and memory map. config SUNXI_DRAM_DW bool - ---help--- - Select this for sunxi SoCs which uses a DRAM controller like the - DesignWare controller used in H3, mainly SoCs after H3, which do - not have official open-source DRAM initialization code, but can - use modified H3 DRAM initialization code. + help + Select this for sunxi SoCs which uses a DRAM controller like the + DesignWare controller used in H3, mainly SoCs after H3, which do + not have official open-source DRAM initialization code, but can + use modified H3 DRAM initialization code. if SUNXI_DRAM_DW config SUNXI_DRAM_DW_16BIT bool - ---help--- - Select this for sunxi SoCs with DesignWare DRAM controller and - have only 16-bit memory buswidth. + help + Select this for sunxi SoCs with DesignWare DRAM controller and + have only 16-bit memory buswidth. config SUNXI_DRAM_DW_32BIT bool - ---help--- - Select this for sunxi SoCs with DesignWare DRAM controller with - 32-bit memory buswidth. + help + Select this for sunxi SoCs with DesignWare DRAM controller with + 32-bit memory buswidth. endif config MACH_SUNXI_H3_H5 @@ -577,25 +576,25 @@ config MACH_SUN8I config RESERVE_ALLWINNER_BOOT0_HEADER bool "reserve space for Allwinner boot0 header" select ENABLE_ARM_SOC_BOOT0_HOOK - ---help--- - Prepend a 1536 byte (empty) header to the U-Boot image file, to be - filled with magic values post build. The Allwinner provided boot0 - blob relies on this information to load and execute U-Boot. - Only needed on 64-bit Allwinner boards so far when using boot0. + help + Prepend a 1536 byte (empty) header to the U-Boot image file, to be + filled with magic values post build. The Allwinner provided boot0 + blob relies on this information to load and execute U-Boot. + Only needed on 64-bit Allwinner boards so far when using boot0. config ARM_BOOT_HOOK_RMR bool depends on ARM64 default y select ENABLE_ARM_SOC_BOOT0_HOOK - ---help--- - Insert some ARM32 code at the very beginning of the U-Boot binary - which uses an RMR register write to bring the core into AArch64 mode. - The very first instruction acts as a switch, since it's carefully - chosen to be a NOP in one mode and a branch in the other, so the - code would only be executed if not already in AArch64. - This allows both the SPL and the U-Boot proper to be entered in - either mode and switch to AArch64 if needed. + help + Insert some ARM32 code at the very beginning of the U-Boot binary + which uses an RMR register write to bring the core into AArch64 mode. + The very first instruction acts as a switch, since it's carefully + chosen to be a NOP in one mode and a branch in the other, so the + code would only be executed if not already in AArch64. + This allows both the SPL and the U-Boot proper to be entered in + either mode and switch to AArch64 if needed. if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616 || DRAM_SUN50I_A133 || DRAM_SUN55I_A523 config SUNXI_DRAM_DDR3 @@ -623,33 +622,33 @@ config SUNXI_DRAM_DDR3_1333 bool "DDR3 1333" select SUNXI_DRAM_DDR3 depends on !DRAM_SUN50I_A133 - ---help--- - This option is the original only supported memory type, which suits - many H3/H5/A64 boards available now. + help + This option is the original only supported memory type, which suits + many H3/H5/A64 boards available now. config SUNXI_DRAM_LPDDR3_STOCK bool "LPDDR3 with Allwinner stock configuration" select SUNXI_DRAM_LPDDR3 depends on !DRAM_SUN50I_A133 - ---help--- - This option is the LPDDR3 timing used by the stock boot0 by - Allwinner. + help + This option is the LPDDR3 timing used by the stock boot0 by + Allwinner. config SUNXI_DRAM_H6_LPDDR3 bool "LPDDR3 DRAM chips on the H6 DRAM controller" select SUNXI_DRAM_LPDDR3 depends on DRAM_SUN50I_H6 - ---help--- - This option is the LPDDR3 timing used by the stock boot0 by - Allwinner. + help + This option is the LPDDR3 timing used by the stock boot0 by + Allwinner. config SUNXI_DRAM_H6_DDR3_1333 bool "DDR3-1333 boot0 timings on the H6 DRAM controller" select SUNXI_DRAM_DDR3 depends on DRAM_SUN50I_H6 - ---help--- - This option is the DDR3 timing used by the boot0 on H6 TV boxes - which use a DDR3-1333 timing. + help + This option is the DDR3 timing used by the boot0 on H6 TV boxes + which use a DDR3-1333 timing. config SUNXI_DRAM_H616_LPDDR3 bool "LPDDR3 DRAM chips on the H616 DRAM controller" @@ -695,9 +694,9 @@ config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2 depends on MACH_SUN8I_V3S - ---help--- - This option is only for the DDR2 memory chip which is co-packaged in - Allwinner V3s SoC. + help + This option is only for the DDR2 memory chip which is co-packaged in + Allwinner V3s SoC. config SUNXI_DRAM_A523_DDR3 bool "DDR3 DRAM chips on the A523/T527 DRAM controller" @@ -721,8 +720,8 @@ config DRAM_TYPE int "sunxi dram type" depends on MACH_SUN8I_A83T default 3 - ---help--- - Set the dram type, 3: DDR3, 7: LPDDR3 + help + Set the dram type, 3: DDR3, 7: LPDDR3 config DRAM_CLK int "sunxi dram clock speed" @@ -735,17 +734,17 @@ config DRAM_CLK default 744 if MACH_SUN50I_H6 default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133 default 1200 if MACH_SUN55I_A523 - ---help--- - Set the dram clock speed, valid range 240 - 480 (prior to sun9i), - must be a multiple of 24. For the sun9i (A80), the tested values - (for DDR3-1600) are 312 to 792. + help + Set the dram clock speed, valid range 240 - 480 (prior to sun9i), + must be a multiple of 24. For the sun9i (A80), the tested values + (for DDR3-1600) are 312 to 792. if MACH_SUN5I || MACH_SUN7I config DRAM_MBUS_CLK int "sunxi mbus clock speed" default 300 - ---help--- - Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. + help + Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. endif @@ -761,8 +760,8 @@ config DRAM_ZQ default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6 default 4145117 if MACH_SUN9I default 3881915 if MACH_SUN50I - ---help--- - Set the dram zq value. + help + Set the dram zq value. config DRAM_ODT_EN bool "sunxi dram odt enable" @@ -773,72 +772,72 @@ config DRAM_ODT_EN default y if MACH_SUN8I_R40 default y if MACH_SUN50I default y if MACH_SUN50I_H6 - ---help--- - Select this to enable dram odt (on die termination). + help + Select this to enable dram odt (on die termination). if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I config DRAM_EMR1 int "sunxi dram emr1 value" default 0 if MACH_SUN4I default 4 if MACH_SUN5I || MACH_SUN7I - ---help--- - Set the dram controller emr1 value. + help + Set the dram controller emr1 value. config DRAM_TPR3 hex "sunxi dram tpr3 value" default 0x0 - ---help--- - Set the dram controller tpr3 parameter. This parameter configures - the delay on the command lane and also phase shifts, which are - applied for sampling incoming read data. The default value 0 - means that no phase/delay adjustments are necessary. Properly - configuring this parameter increases reliability at high DRAM - clock speeds. + help + Set the dram controller tpr3 parameter. This parameter configures + the delay on the command lane and also phase shifts, which are + applied for sampling incoming read data. The default value 0 + means that no phase/delay adjustments are necessary. Properly + configuring this parameter increases reliability at high DRAM + clock speeds. config DRAM_DQS_GATING_DELAY hex "sunxi dram dqs_gating_delay value" default 0x0 - ---help--- - Set the dram controller dqs_gating_delay parmeter. Each byte - encodes the DQS gating delay for each byte lane. The delay - granularity is 1/4 cycle. For example, the value 0x05060606 - means that the delay is 5 quarter-cycles for one lane (1.25 - cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. - The default value 0 means autodetection. The results of hardware - autodetection are not very reliable and depend on the chip - temperature (sometimes producing different results on cold start - and warm reboot). But the accuracy of hardware autodetection - is usually good enough, unless running at really high DRAM - clocks speeds (up to 600MHz). If unsure, keep as 0. + help + Set the dram controller dqs_gating_delay parmeter. Each byte + encodes the DQS gating delay for each byte lane. The delay + granularity is 1/4 cycle. For example, the value 0x05060606 + means that the delay is 5 quarter-cycles for one lane (1.25 + cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. + The default value 0 means autodetection. The results of hardware + autodetection are not very reliable and depend on the chip + temperature (sometimes producing different results on cold start + and warm reboot). But the accuracy of hardware autodetection + is usually good enough, unless running at really high DRAM + clocks speeds (up to 600MHz). If unsure, keep as 0. choice prompt "sunxi dram timings" default DRAM_TIMINGS_VENDOR_MAGIC - ---help--- - Select the timings of the DDR3 chips. + help + Select the timings of the DDR3 chips. config DRAM_TIMINGS_VENDOR_MAGIC bool "Magic vendor timings from Android" - ---help--- - The same DRAM timings as in the Allwinner boot0 bootloader. + help + The same DRAM timings as in the Allwinner boot0 bootloader. config DRAM_TIMINGS_DDR3_1066F_1333H bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" - ---help--- - Use the timings of the standard JEDEC DDR3-1066F speed bin for - DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin - for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips - used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 - or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm - that down binning to DDR3-1066F is supported (because DDR3-1066F - uses a bit faster timings than DDR3-1333H). + help + Use the timings of the standard JEDEC DDR3-1066F speed bin for + DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin + for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips + used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 + or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm + that down binning to DDR3-1066F is supported (because DDR3-1066F + uses a bit faster timings than DDR3-1333H). config DRAM_TIMINGS_DDR3_800E_1066G_1333J bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" - ---help--- - Use the timings of the slowest possible JEDEC speed bin for the - selected DRAM_CLK. Depending on the DRAM_CLK value, it may be - DDR3-800E, DDR3-1066G or DDR3-1333J. + help + Use the timings of the slowest possible JEDEC speed bin for the + selected DRAM_CLK. Depending on the DRAM_CLK value, it may be + DDR3-800E, DDR3-1066G or DDR3-1333J. endchoice @@ -848,11 +847,11 @@ if MACH_SUN8I_A23 config DRAM_ODT_CORRECTION int "sunxi dram odt correction value" default 0 - ---help--- - Set the dram odt correction value (range -255 - 255). In allwinner - fex files, this option is found in bits 8-15 of the u32 odt_en variable - in the [dram] section. When bit 31 of the odt_en variable is set - then the correction is negative. Usually the value for this is 0. + help + Set the dram odt correction value (range -255 - 255). In allwinner + fex files, this option is found in bits 8-15 of the u32 odt_en variable + in the [dram] section. When bit 31 of the odt_en variable is set + then the correction is negative. Usually the value for this is 0. endif config SYS_CLK_FREQ @@ -889,59 +888,59 @@ config SUNXI_MINIMUM_DRAM_MB default 32 if MACH_SUNIV default 64 if MACH_SUN8I_V3S default 256 - ---help--- - Minimum DRAM size expected on the board. Traditionally we assumed - 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM - we have smaller sizes, though, so that U-Boot's own load address and - the default payload addresses must be shifted down. - This is expected to be fixed by the SoC selection. + help + Minimum DRAM size expected on the board. Traditionally we assumed + 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM + we have smaller sizes, though, so that U-Boot's own load address and + the default payload addresses must be shifted down. + This is expected to be fixed by the SoC selection. config UART0_PORT_F bool "UART0 on MicroSD breakout board" - ---help--- - Repurpose the SD card slot for getting access to the UART0 serial - console. Primarily useful only for low level u-boot debugging on - tablets, where normal UART0 is difficult to access and requires - device disassembly and/or soldering. As the SD card can't be used - at the same time, the system can be only booted in the FEL mode. - Only enable this if you really know what you are doing. + help + Repurpose the SD card slot for getting access to the UART0 serial + console. Primarily useful only for low level u-boot debugging on + tablets, where normal UART0 is difficult to access and requires + device disassembly and/or soldering. As the SD card can't be used + at the same time, the system can be only booted in the FEL mode. + Only enable this if you really know what you are doing. config OLD_SUNXI_KERNEL_COMPAT bool "Enable workarounds for booting old kernels" - ---help--- - Set this to enable various workarounds for old kernels, this results in - sub-optimal settings for newer kernels, only enable if needed. + help + Set this to enable various workarounds for old kernels, this results in + sub-optimal settings for newer kernels, only enable if needed. config MMC1_PINS_PH bool "Pins for mmc1 are on Port H" depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40 - ---help--- - Select this option for boards where mmc1 uses the Port H pinmux. + help + Select this option for boards where mmc1 uses the Port H pinmux. config MMC_SUNXI_SLOT_EXTRA int "mmc extra slot number" default -1 - ---help--- - sunxi builds always enable mmc0, some boards also have a second sdcard - slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable - support for this. + help + sunxi builds always enable mmc0, some boards also have a second sdcard + slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable + support for this. config I2C0_ENABLE bool "Enable I2C/TWI controller 0" default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 default n if MACH_SUN6I || MACH_SUN8I select CMD_I2C - ---help--- - This allows enabling I2C/TWI controller 0 by muxing its pins, enabling - its clock and setting up the bus. This is especially useful on devices - with slaves connected to the bus or with pins exposed through e.g. an - expansion port/header. + help + This allows enabling I2C/TWI controller 0 by muxing its pins, enabling + its clock and setting up the bus. This is especially useful on devices + with slaves connected to the bus or with pins exposed through e.g. an + expansion port/header. config I2C1_ENABLE bool "Enable I2C/TWI controller 1" select CMD_I2C - ---help--- - See I2C0_ENABLE help text. + help + See I2C0_ENABLE help text. if SUNXI_GEN_SUN6I || SUN50I_GEN_H6 || SUNXI_GEN_NCAT2 config R_I2C_ENABLE @@ -949,20 +948,20 @@ config R_I2C_ENABLE # This is used for the pmic on H3 default y if SY8106A_POWER select CMD_I2C - ---help--- - Set this to y to enable the I2C controller which is part of the PRCM. + help + Set this to y to enable the I2C controller which is part of the PRCM. endif config AXP_GPIO bool "Enable support for gpio-s on axp PMICs" depends on AXP_PMIC_BUS - ---help--- - Say Y here to enable support for the gpio pins of the axp PMIC ICs. + help + Say Y here to enable support for the gpio pins of the axp PMIC ICs. config AXP_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER - ---help--- + help Say Y here to prevent the device from booting up because of a plug-in event. When set, the device will boot into the SPL briefly to determine why it was powered on, and if it was determined because of @@ -983,127 +982,127 @@ config VIDEO_SUNXI imply VIDEO_DAMAGE imply VIDEO_DT_SIMPLEFB default y - ---help--- - Say Y here to add support for using a graphical console on the HDMI, - LCD or VGA output found on older sunxi devices. This will also provide - a simple_framebuffer device for Linux. + help + Say Y here to add support for using a graphical console on the HDMI, + LCD or VGA output found on older sunxi devices. This will also provide + a simple_framebuffer device for Linux. config VIDEO_HDMI bool "HDMI output support" depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV default y - ---help--- - Say Y here to add support for outputting video over HDMI. + help + Say Y here to add support for outputting video over HDMI. config VIDEO_VGA bool "VGA output support" depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I) - ---help--- - Say Y here to add support for outputting video over VGA. + help + Say Y here to add support for outputting video over VGA. config VIDEO_VGA_VIA_LCD bool "VGA via LCD controller support" depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) - ---help--- - Say Y here to add support for external DACs connected to the parallel - LCD interface driving a VGA connector, such as found on the - Olimex A13 boards. + help + Say Y here to add support for external DACs connected to the parallel + LCD interface driving a VGA connector, such as found on the + Olimex A13 boards. config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH bool "Force sync active high for VGA via LCD controller support" depends on VIDEO_VGA_VIA_LCD - ---help--- - Say Y here if you've a board which uses opendrain drivers for the vga - hsync and vsync signals. Opendrain drivers cannot generate steep enough - positive edges for a stable video output, so on boards with opendrain - drivers the sync signals must always be active high. + help + Say Y here if you've a board which uses opendrain drivers for the vga + hsync and vsync signals. Opendrain drivers cannot generate steep enough + positive edges for a stable video output, so on boards with opendrain + drivers the sync signals must always be active high. config VIDEO_VGA_EXTERNAL_DAC_EN string "LCD panel power enable pin" depends on VIDEO_VGA_VIA_LCD default "" - ---help--- - Set the enable pin for the external VGA DAC. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + help + Set the enable pin for the external VGA DAC. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. config VIDEO_COMPOSITE bool "Composite video output support" depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) - ---help--- - Say Y here to add support for outputting composite video. + help + Say Y here to add support for outputting composite video. config VIDEO_LCD_MODE string "LCD panel timing details" depends on VIDEO_SUNXI default "" - ---help--- - LCD panel timing details string, leave empty if there is no LCD panel. - This is in drivers/video/videomodes.c: video_get_params() format, e.g. - x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 - Also see: http://linux-sunxi.org/LCD + help + LCD panel timing details string, leave empty if there is no LCD panel. + This is in drivers/video/videomodes.c: video_get_params() format, e.g. + x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 + Also see: http://linux-sunxi.org/LCD config VIDEO_LCD_DCLK_PHASE int "LCD panel display clock phase" depends on VIDEO_SUNXI || VIDEO default 1 range 0 3 - ---help--- - Select LCD panel display clock phase shift + help + Select LCD panel display clock phase shift config VIDEO_LCD_POWER string "LCD panel power enable pin" depends on VIDEO_SUNXI default "" - ---help--- - Set the power enable pin for the LCD panel. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + help + Set the power enable pin for the LCD panel. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_RESET string "LCD panel reset pin" depends on VIDEO_SUNXI default "" - ---help--- - Set the reset pin for the LCD panel. This takes a string in the format - understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + help + Set the reset pin for the LCD panel. This takes a string in the format + understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_BL_EN string "LCD panel backlight enable pin" depends on VIDEO_SUNXI default "" - ---help--- - Set the backlight enable pin for the LCD panel. This takes a string in the - the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of - port H. + help + Set the backlight enable pin for the LCD panel. This takes a string in the + the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of + port H. config VIDEO_LCD_BL_PWM string "LCD panel backlight pwm pin" depends on VIDEO_SUNXI default "" - ---help--- - Set the backlight pwm pin for the LCD panel. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + help + Set the backlight pwm pin for the LCD panel. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_BL_PWM_ACTIVE_LOW bool "LCD panel backlight pwm is inverted" depends on VIDEO_SUNXI default y - ---help--- - Set this if the backlight pwm output is active low. + help + Set this if the backlight pwm output is active low. config VIDEO_LCD_PANEL_I2C bool "LCD panel needs to be configured via i2c" depends on VIDEO_SUNXI select DM_I2C_GPIO - ---help--- - Say y here if the LCD panel needs to be configured via i2c. This - will add a bitbang i2c controller using gpios to talk to the LCD. + help + Say y here if the LCD panel needs to be configured via i2c. This + will add a bitbang i2c controller using gpios to talk to the LCD. config VIDEO_LCD_PANEL_I2C_NAME string "LCD panel i2c interface node name" depends on VIDEO_LCD_PANEL_I2C default "i2c" - ---help--- - Set the device tree node name for the LCD i2c interface. + help + Set the device tree node name for the LCD i2c interface. # Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig @@ -1124,16 +1123,16 @@ config VIDEO_DE2 select VIDEO_DW_HDMI imply VIDEO_DT_SIMPLEFB default y - ---help--- - Say y here if you want to build DE2 video driver which is present on - newer SoCs. Currently only HDMI output is supported. + help + Say y here if you want to build DE2 video driver which is present on + newer SoCs. Currently only HDMI output is supported. choice prompt "LCD panel support" depends on VIDEO_SUNXI - ---help--- - Select which type of LCD panel to support. + help + Select which type of LCD panel to support. config VIDEO_LCD_PANEL_PARALLEL bool "Generic parallel interface LCD panel" @@ -1147,40 +1146,40 @@ config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" select VIDEO_LCD_SSD2828 select VIDEO_LCD_IF_PARALLEL - ---help--- - 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 + help + 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" select VIDEO_LCD_ANX9804 select VIDEO_LCD_IF_PARALLEL select VIDEO_LCD_PANEL_I2C - ---help--- - Select this for eDP LCD panels with 4 lanes running at 1.62G, - connected via an ANX9804 bridge chip. + help + Select this for eDP LCD panels with 4 lanes running at 1.62G, + connected via an ANX9804 bridge chip. config VIDEO_LCD_PANEL_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LCD panel" select VIDEO_LCD_HITACHI_TX18D42VM select VIDEO_LCD_IF_LVDS - ---help--- - 7.85" 1024x768 Hitachi tx18d42vm LCD panel support + help + 7.85" 1024x768 Hitachi tx18d42vm LCD panel support config VIDEO_LCD_TL059WV5C0 bool "tl059wv5c0 LCD panel" select VIDEO_LCD_PANEL_I2C select VIDEO_LCD_IF_PARALLEL - ---help--- - 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and - Aigo M60/M608/M606 tablets. + help + 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and + Aigo M60/M608/M606 tablets. endchoice config GMAC_TX_DELAY int "GMAC Transmit Clock Delay Chain" default 0 - ---help--- - Set the GMAC Transmit Clock Delay Chain value. + help + Set the GMAC Transmit Clock Delay Chain value. config SPL_STACK_R_ADDR default 0x81e00000 if MACH_SUNIV @@ -1245,15 +1244,17 @@ config SPL_SUNXI_LED_STATUS if SPL_SUNXI_LED_STATUS -config SPL_SUNXI_LED_STATUS_BIT +config SPL_SUNXI_LED_STATUS_GPIO int "GPIO number for GPIO status LED" help GPIO number for the GPIO controlling the GPIO status LED in SPL. -config SPL_SUNXI_LED_STATUS_STATE - bool "GPIO status LED initial state is on" +config SPL_SUNXI_LED_STATUS_ACTIVE_HIGH + bool "GPIO status LED is active high" + default y help - Whether the initial state of the status LED in SPL must be on or off. + Whether the GPIO of the status LED must be set high or low to turn + the LED on. endif # SPL_SUNXI_LED_STATUS diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 3345c9b8e82..42a0550e015 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -975,7 +975,7 @@ static bool mctl_phy_init(const struct dram_para *para, val = para->tpr6 & 0xff; break; case SUNXI_DRAM_TYPE_LPDDR3: - val = para->tpr6 >> 8 & 0xff; + val = para->tpr6 >> 16 & 0xff; break; case SUNXI_DRAM_TYPE_LPDDR4: val = para->tpr6 >> 24 & 0xff; diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 396851c5bd8..1763f95ace4 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -393,18 +393,18 @@ int dram_init_banksize(void) /* fall back to default DRAM bank size computation */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = usable_ram_size_below_4g(); #ifdef CONFIG_PHYS_64BIT if (gd->ram_size > SZ_2G) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } else #endif { - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; @@ -418,7 +418,7 @@ int dram_init_banksize(void) * carve-out, as mentioned above. * * This function is called before dram_init_banksize(), so we can't simply - * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. + * return gd->dram[1].start + gd->dram[1].size. */ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c index e2342b2aece..ff15fa28eb5 100644 --- a/arch/arm/mach-tegra/cboot.c +++ b/arch/arm/mach-tegra/cboot.c @@ -185,8 +185,8 @@ int cboot_dram_init_banksize(void) } for (i = 0; i < ram_bank_count; i++) { - gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt; - gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size; + gd->dram[i].start = tegra_mem_map[1 + i].virt; + gd->dram[i].size = tegra_mem_map[1 + i].size; } return 0; diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index c570fb3294d..d2fa72f4724 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -4,7 +4,7 @@ config SYS_CONFIG_NAME default "uniphier" choice - prompt "UniPhier SoC select" + prompt "UniPhier SoC select" config ARCH_UNIPHIER_V7_MULTI bool "UniPhier V7 SoCs" diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 0e1164a2680..ae495808dec 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -280,9 +280,9 @@ int dram_init_banksize(void) return ret; for (i = 0; i < ARRAY_SIZE(dram_map); i++) { - if (i < ARRAY_SIZE(gd->bd->bi_dram)) { - gd->bd->bi_dram[i].start = dram_map[i].base; - gd->bd->bi_dram[i].size = dram_map[i].size; + if (i < ARRAY_SIZE(gd->dram)) { + gd->dram[i].start = dram_map[i].base; + gd->dram[i].size = dram_map[i].size; } if (!dram_map[i].size) diff --git a/arch/arm/mach-uniphier/fdt-fixup.c b/arch/arm/mach-uniphier/fdt-fixup.c index dfa32fdd48b..4e1de15cd98 100644 --- a/arch/arm/mach-uniphier/fdt-fixup.c +++ b/arch/arm/mach-uniphier/fdt-fixup.c @@ -4,6 +4,7 @@ * Author: Masahiro Yamada <[email protected]> */ +#include <asm/global_data.h> #include <fdt_support.h> #include <fdtdec.h> #include <jffs2/load_kernel.h> @@ -20,6 +21,7 @@ */ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) { + DECLARE_GLOBAL_DATA_PTR; unsigned long rsv_addr; const unsigned long rsv_size = 64; int i, ret; @@ -28,11 +30,11 @@ static int uniphier_ld20_fdt_mem_rsv(void *fdt, struct bd_info *bd) uniphier_get_soc_id() != UNIPHIER_LD20_ID) return 0; - for (i = 0; i < ARRAY_SIZE(bd->bi_dram); i++) { - if (!bd->bi_dram[i].size) + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { + if (!gd->dram[i].size) continue; - rsv_addr = bd->bi_dram[i].start + bd->bi_dram[i].size; + rsv_addr = gd->dram[i].start + gd->dram[i].size; rsv_addr -= rsv_size; ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index d088e440f63..7df7c49ac71 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -7,6 +7,10 @@ */ #include <init.h> +#include <log.h> +#include <malloc.h> +#include <time.h> +#include <vsprintf.h> #include <asm/armv8/mmu.h> #include <asm/cache.h> #include <asm/global_data.h> @@ -15,6 +19,9 @@ #include <asm/arch/sys_proto.h> #include <asm/cache.h> #include <dm/platdata.h> +#include <linux/bitfield.h> +#include <linux/string.h> +#include "../../../board/xilinx/common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -69,12 +76,12 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; @@ -88,6 +95,148 @@ u64 get_page_table_size(void) return 0x14000; } +void versal_net_timer_setup(void) +{ + u32 val; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); +} + +u32 versal_net_bootmode_reg(void) +{ + return readl(&crp_base->boot_mode_usr); +} + +u8 __weak versal_net_get_bootmode(void) +{ + u32 reg = versal_net_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} + +static u32 platform_id, platform_version; + +char *soc_name_decode(void) +{ + char *name, *platform_name; + + switch (platform_id) { + case VERSAL_NET_SPP: + platform_name = "ipp"; + break; + case VERSAL_NET_EMU: + platform_name = "emu"; + break; + case VERSAL_NET_QEMU: + platform_name = "qemu"; + break; + default: + return NULL; + } + + /* + * --rev. are 6 chars + * max platform name is qemu which is 4 chars + * platform version number are 1+1 + * Plus 1 char for \n + */ + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); + if (!name) + return NULL; + + sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD, + platform_name, platform_version / 10, + platform_version % 10); + + return name; +} + +bool soc_detection(void) +{ + u32 version, ps_version; + + version = readl(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + ps_version = FIELD_GET(PS_VERSION_MASK, version); + + debug("idcode %x, version %x, usercode %x\n", + readl(PMC_TAP_IDCODE), version, + readl(PMC_TAP_USERCODE)); + + debug("pmc_ver %lx, ps version %x, rtl version %lx\n", + FIELD_GET(PMC_VERSION_MASK, version), + ps_version, + FIELD_GET(RTL_VERSION_MASK, version)); + + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + if (platform_id == VERSAL_NET_SPP || + platform_id == VERSAL_NET_EMU) { + if (ps_version == PS_VERSION_PRODUCTION) { + /* + * ES1 version ends at 1.9 version where there was +9 + * used because of IPP/SPP conversion. Production + * version have platform_version started from 0 again + * that's why adding +20 to continue with the same line. + * It means the last ES1 version ends at 1.9 version and + * new PRODUCTION line starts at 2.0. + */ + platform_version += 20; + } else { + /* + * 9 is diff for + * 0 means 0.9 version + * 1 means 1.0 version + * 2 means 1.1 version + * etc, + */ + platform_version += 9; + } + } + + debug("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10, platform_version % 10); + + return true; +} + U_BOOT_DRVINFO(soc_xilinx_versal_net) = { .name = "soc_xilinx_versal_net", }; diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h index 23374d10a6b..4907dae1108 100644 --- a/arch/arm/mach-versal-net/include/mach/sys_proto.h +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h @@ -7,3 +7,9 @@ #include <linux/build_bug.h> void mem_map_fill(void); +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void versal_net_timer_setup(void); +/* Overridable bootmode decode: weak MMIO default, firmware override */ +u8 versal_net_get_bootmode(void); +/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */ +u32 versal_net_bootmode_reg(void); diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 363ce3007fd..7521d45bc1a 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -1,10 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 - 2018 Xilinx, Inc. + * (C) Copyright 2026, Advanced Micro Devices, Inc. + * * Michal Simek <[email protected]> */ #include <init.h> +#include <log.h> +#include <time.h> #include <asm/armv8/mmu.h> #include <asm/cache.h> #include <asm/global_data.h> @@ -16,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; -#define VERSAL_MEM_MAP_USED 5 +#define VERSAL_MEM_MAP_USED 3 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS @@ -44,26 +48,13 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, { /* FPD_AXI_PL_high */ .virt = 0x400000000UL, .phys = 0x400000000UL, .size = 0x200000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x600000000UL, - .phys = 0x600000000UL, - .size = 0x800000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe00000000UL, - .phys = 0xe00000000UL, - .size = 0xf200000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN } }; @@ -82,21 +73,21 @@ void mem_map_fill(void) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; #if defined(CONFIG_VERSAL_NO_DDR) - if (gd->bd->bi_dram[i].start < 0x80000000UL || - gd->bd->bi_dram[i].start > 0x100000000UL) { + if (gd->dram[i].start < 0x80000000UL || + gd->dram[i].start > 0x100000000UL) { printf("Ignore caches over %llx/%llx\n", - gd->bd->bi_dram[i].start, - gd->bd->bi_dram[i].size); + gd->dram[i].start, + gd->dram[i].size); continue; } #endif - versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; - versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; - versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].virt = gd->dram[i].start; + versal_mem_map[banks].phys = gd->dram[i].start; + versal_mem_map[banks].size = gd->dram[i].size; versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; @@ -121,6 +112,72 @@ int arm_reserve_mmu(void) } #endif +u32 versal_multi_boot_reg(void) +{ + return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK; +} + +u32 __weak versal_pmc_multi_boot(void) +{ + return versal_multi_boot_reg(); +} + +void versal_timer_setup(void) +{ + u32 val; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); +} + +u32 versal_bootmode_reg(void) +{ + return readl(&crp_base->boot_mode_usr); +} + +u8 __weak versal_get_bootmode(void) +{ + u32 reg = versal_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} + U_BOOT_DRVINFO(soc_xilinx_versal) = { .name = "soc_xilinx_versal", }; diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index b5f80a8e3a9..66eca18998a 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -100,3 +100,6 @@ struct crp_regs { #define MIO_PIN_12 0xF1060030 #define BANK0_OUTPUT 0xF1020040 #define BANK0_TRI 0xF1060200 + +#define PMC_GLOBAL_PGGS3_REG 0xF111005C +#define PMC_GLOBAL_PGGS4_REG 0xF1110060 diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index a6dfa556966..cb373e6fad9 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -3,6 +3,9 @@ * Copyright 2016 - 2018 Xilinx, Inc. */ +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + #include <linux/build_bug.h> enum tcm_mode { @@ -13,3 +16,16 @@ enum tcm_mode { void initialize_tcm(enum tcm_mode mode); void tcm_init(enum tcm_mode mode); void mem_map_fill(void); + +/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */ +u32 versal_pmc_multi_boot(void); +/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */ +u32 versal_multi_boot_reg(void); +/* Overridable bootmode decode: weak MMIO default, firmware override */ +u8 versal_get_bootmode(void); +/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */ +u32 versal_bootmode_reg(void); +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void versal_timer_setup(void); + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index 9a02fe40733..6cc6592b0fc 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -1,24 +1,36 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ #include <init.h> +#include <log.h> +#include <malloc.h> +#include <time.h> +#include <vsprintf.h> #include <asm/armv8/mmu.h> #include <asm/cache.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/system.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/cache.h> #include <dm/platdata.h> +#include <linux/bitfield.h> +#include <linux/string.h> +#include "../../../board/xilinx/common/board.h" DECLARE_GLOBAL_DATA_PTR; -#define VERSAL2_MEM_MAP_USED 5 +#if CONFIG_IS_ENABLED(PCIE_DW_AMD) +#define VERSAL2_MEM_MAP_USED 4 +#else +#define VERSAL2_MEM_MAP_USED 3 +#endif #define DRAM_BANKS CONFIG_NR_DRAM_BANKS @@ -47,19 +59,16 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN +#if CONFIG_IS_ENABLED(PCIE_DW_AMD) }, { - .virt = 0x600000000UL, - .phys = 0x600000000UL, - .size = 0x800000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe00000000UL, - .phys = 0xe00000000UL, - .size = 0xf200000000UL, + /* PCIe DBI (1 MB) and config space (255 MB) are contiguous */ + .virt = 0x100000000000UL, + .phys = 0x100000000000UL, + .size = 0x10000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN +#endif } }; @@ -69,7 +78,7 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { * @num_banks: Number of valid DRAM banks in bank_info array * * Copies DRAM bank information into the global versal2_mem_map[] array - * starting at index VERSAL2_MEM_MAP_USED (5), which is after the fixed + * starting at index VERSAL2_MEM_MAP_USED, which is after the fixed * device mappings. This must be called early in boot before MMU * initialization so that get_page_table_size() can calculate the * required page table size based on actual memory configuration. @@ -95,7 +104,7 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) * fill_bd_mem_info() - Copy DRAM banks from mem_map to bd_info * * Transfers DRAM bank information from the global versal2_mem_map[] - * array to bd->bi_dram[] for passing memory configuration to the + * array to gd->dram[] for passing memory configuration to the * Linux kernel via boot parameters (ATAGS/FDT). Each bank's physical * address and size are copied. * @@ -105,15 +114,14 @@ void mem_map_fill(struct mm_region *bank_info, u32 num_banks) */ void fill_bd_mem_info(void) { - struct bd_info *bd = gd->bd; int banks = VERSAL2_MEM_MAP_USED; for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { if (!versal2_mem_map[banks].size) break; - bd->bi_dram[i].start = versal2_mem_map[banks].phys; - bd->bi_dram[i].size = versal2_mem_map[banks].size; + gd->dram[i].start = versal2_mem_map[banks].phys; + gd->dram[i].size = versal2_mem_map[banks].size; banks++; } } @@ -127,6 +135,141 @@ u64 get_page_table_size(void) } #endif +u32 versal2_multi_boot_reg(void) +{ + return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK; +} + +u32 __weak versal2_pmc_multi_boot(void) +{ + return versal2_multi_boot_reg(); +} + +u8 __weak versal2_get_bootmode(void) +{ + u8 bootmode; + u32 reg; + + reg = readl(&crp_base->boot_mode_usr); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + return bootmode; +} + +void versal2_timer_setup(void) +{ + u32 val; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); +} + +static u32 platform_id, platform_version; + +char *soc_name_decode(void) +{ + char *name, *platform_name; + + switch (platform_id) { + case VERSAL2_SPP: + platform_name = "spp"; + break; + case VERSAL2_EMU: + platform_name = "emu"; + break; + case VERSAL2_SPP_MMD: + platform_name = "spp-mmd"; + break; + case VERSAL2_EMU_MMD: + platform_name = "emu-mmd"; + break; + case VERSAL2_QEMU: + platform_name = "qemu"; + break; + default: + return NULL; + } + + /* + * --rev.-el are 9 chars + * max platform name is emu-mmd which is 7 chars + * platform version number are 1+1 + * el is 1 char + * Plus 1 char for NULL byte + */ + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20); + if (!name) + return NULL; + + sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD, + platform_name, platform_version / 10, + platform_version % 10, current_el()); + + return name; +} + +bool soc_detection(void) +{ + u32 version, ps_version; + + version = readl(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + ps_version = FIELD_GET(PS_VERSION_MASK, version); + + debug("idcode %x, version %x, usercode %x\n", + readl(PMC_TAP_IDCODE), version, + readl(PMC_TAP_USERCODE)); + + debug("pmc_ver %lx, ps version %x, rtl version %lx\n", + FIELD_GET(PMC_VERSION_MASK, version), + ps_version, + FIELD_GET(RTL_VERSION_MASK, version)); + + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + debug("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10, platform_version % 10); + + return true; +} + U_BOOT_DRVINFO(soc_amd_versal2) = { .name = "soc_amd_versal2", }; diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h index 81a0df89357..1bebf20910a 100644 --- a/arch/arm/mach-versal2/include/mach/hardware.h +++ b/arch/arm/mach-versal2/include/mach/hardware.h @@ -105,3 +105,6 @@ enum versal2_platform { #define PMXC_UFS_CAL_1_OFFSET 0xBE8 #define PMXC_SRAM_CSR 0x4C #define PMXC_TX_RX_CFG_RDY 0x54 + +#define PMC_GLOBAL_PGGS3_REG 0xF111005C +#define PMC_GLOBAL_PGGS4_REG 0xF1110060 diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index cee13488620..b8d12d1dd3b 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -4,8 +4,22 @@ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. */ +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + #include <linux/build_bug.h> #include <asm/armv8/mmu.h> void mem_map_fill(struct mm_region *bank_info, u32 num_banks); void fill_bd_mem_info(void); + +/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */ +u32 versal2_pmc_multi_boot(void); +/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */ +u32 versal2_multi_boot_reg(void); +/* Weak bootmode decode (MMIO default); a firmware/SCMI build may override */ +u8 versal2_get_bootmode(void); +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void versal2_timer_setup(void); + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 5f194aaff9a..088cc962189 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -8,6 +8,7 @@ #include <time.h> #include <linux/errno.h> #include <linux/types.h> +#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/armv8/mmu.h> @@ -92,12 +93,12 @@ void mem_map_fill(void) #if !defined(CONFIG_ZYNQMP_NO_DDR) for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ - if (!gd->bd->bi_dram[i].size) + if (!gd->dram[i].size) break; - zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start; - zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size; + zynqmp_mem_map[banks].virt = gd->dram[i].start; + zynqmp_mem_map[banks].phys = gd->dram[i].start; + zynqmp_mem_map[banks].size = gd->dram[i].size; zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; banks = banks + 1; @@ -171,15 +172,19 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_SILICON; } -static int zynqmp_mmio_rawwrite(const u32 address, - const u32 mask, - const u32 value) +int zynqmp_mmio_rawread(const u32 address, u32 *value) +{ + *value = readl((ulong)address); + return 0; +} + +int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value) { u32 data; u32 value_local = value; int ret; - ret = zynqmp_mmio_read(address, &data); + ret = zynqmp_mmio_rawread(address, &data); if (ret) return ret; @@ -190,48 +195,44 @@ static int zynqmp_mmio_rawwrite(const u32 address, return 0; } -static int zynqmp_mmio_rawread(const u32 address, u32 *value) +int __weak zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) { - *value = readl((ulong)address); - return 0; + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) + return zynqmp_mmio_rawwrite(address, mask, value); + + return -EINVAL; } -int zynqmp_mmio_write(const u32 address, - const u32 mask, - const u32 value) +int __weak zynqmp_mmio_read(const u32 address, u32 *value) { + if (!value) + return -EINVAL; + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) - return zynqmp_mmio_rawwrite(address, mask, value); -#if defined(CONFIG_ZYNQMP_FIRMWARE) - else - return xilinx_pm_request(PM_MMIO_WRITE, address, mask, - value, 0, 0, 0, NULL); -#endif + return zynqmp_mmio_rawread(address, value); return -EINVAL; } -int zynqmp_mmio_read(const u32 address, u32 *value) +void zynqmp_timer_setup(void) { - u32 ret = -EINVAL; + u32 val; - if (!value) - return ret; + val = readl(&crlapb_base->timestamp_ref_ctrl); + val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { - ret = zynqmp_mmio_rawread(address, value); - } -#if defined(CONFIG_ZYNQMP_FIRMWARE) - else { - u32 ret_payload[PAYLOAD_ARG_CNT]; + if (!val) { + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + writel(val, &crlapb_base->timestamp_ref_ctrl); - ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, - 0, 0, 0, ret_payload); - *value = ret_payload[1]; + /* Program freq register in System counter */ + writel(zynqmp_get_system_timer_freq(), + &iou_scntr_secure->base_frequency_id_register); + /* And enable system counter */ + writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, + &iou_scntr_secure->counter_control_register); } -#endif - - return ret; } U_BOOT_DRVINFO(soc_xilinx_zynqmp) = { diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index b6a41df1da4..d2bb10ffcbb 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -54,5 +54,10 @@ void mem_map_fill(void); #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) void tcm_init(enum tcm_mode mode); #endif +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void zynqmp_timer_setup(void); +/* Direct MMIO accessors (EL3/SPL or no-firmware path) */ +int zynqmp_mmio_rawread(const u32 address, u32 *value); +int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value); #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 6ce8f577e3a..61a1845c2ee 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -11,57 +11,58 @@ config STATIC_RELA config MCF520x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF52x2 select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF523x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF530x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF5301x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF532x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF537x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF5441x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE + select CREATE_ARCH_SYMLINK bool config M680x0 @@ -190,17 +191,19 @@ config TARGET_AMCORE select M5307 config TARGET_STMARK2 - bool "Support stmark2" - select CF_DSPI - select M54418 + bool "Support stmark2" + select CF_DSPI + select M54418 config TARGET_QEMU_M68K - bool "Support QEMU m68k virt" - select M68040 - imply CMD_DM - help - This target supports the QEMU m68k virtual machine (-M virt). - It simulates a Motorola 68040 CPU with Goldfish peripherals. + bool "Support QEMU m68k virt" + select M68040 + select BOARD_EARLY_INIT_R + select VIRTIO_MMIO + imply CMD_DM + help + This target supports the QEMU m68k virtual machine (-M virt). + It simulates a Motorola 68040 CPU with Goldfish peripherals. endchoice diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index f0264671d38..ae0e7c35d87 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -114,7 +114,7 @@ vector192_255: /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ asm_sbf_img_hdr: .long 0x00000000 /* checksum, not yet implemented */ - .long 0x00040000 /* image length */ + .long CONFIG_SYS_MONITOR_LEN /* image length */ .long CONFIG_TEXT_BASE /* image to be relocated at */ asm_dram_init: @@ -292,7 +292,6 @@ asm_dspi_rd_status: move.b (%a3), %d1 rts #endif /* CONFIG_CF_SBF */ - #ifdef CONFIG_SYS_NAND_BOOT /* copy 4 boot pages to dram as soon as possible */ /* each page is 996 bytes (1056 total with 60 ECC bytes */ diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi index dcca36312f5..7cd6072d4a5 100644 --- a/arch/m68k/dts/mcf5441x.dtsi +++ b/arch/m68k/dts/mcf5441x.dtsi @@ -163,5 +163,13 @@ clock-frequency = <100000>; status = "disabled"; }; + + esdhc: mmc@0xfc0cc000 { + compatible = "fsl,esdhc"; + reg = <0xfc0cc000 0x8000>; + non-removable; + bus-width = <4>; + status = "disabled"; + }; }; }; diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts index 3ba68b77d64..8e196fa65ff 100644 --- a/arch/m68k/dts/stmark2.dts +++ b/arch/m68k/dts/stmark2.dts @@ -45,3 +45,7 @@ &i2c0 { status = "okay"; }; + +&esdhc { + status = "okay"; +}; diff --git a/arch/m68k/include/asm/arch-mcf5445x/clock.h b/arch/m68k/include/asm/arch-mcf5445x/clock.h new file mode 100644 index 00000000000..10ceecafcea --- /dev/null +++ b/arch/m68k/include/asm/arch-mcf5445x/clock.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * ColdFire clock support + * + * Copyright 2026 Kernelspace. + * Angelo Dureghello <[email protected]> + */ + +#ifndef __CLOCK_H +#define __CLOCK_H + +/* Stub to use fsl/nxp drivers. */ +enum mxc_clock { + MXC_ESDHC_CLK, +}; + +int mxc_get_clock(enum mxc_clock clk); + +#endif /* __CLOCK_H */ diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index 35ad4a1c044..2577081d836 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -23,18 +23,27 @@ #define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w)) #define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l)) -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) -#if !defined(__BIG_ENDIAN) -#define readw(addr) (*(volatile u16 *) (addr)) -#define readl(addr) (*(volatile u32 *) (addr)) -#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) +#define readb(addr) in_8((volatile u8 *)(addr)) +#define writeb(b, addr) out_8((volatile u8 *)(addr), (b)) +#ifdef CONFIG_M680x0 +/* + * For classic m68k these work the same way as Linux: + * Read a little endian value, swap to the CPU endian. + */ +#define readw(addr) in_le16((volatile u16 *)(addr)) +#define readl(addr) in_le32((volatile u32 *)(addr)) +#define writew(b, addr) out_le16((volatile u16 *)(addr), (b)) +#define writel(b, addr) out_le32((volatile u32 *)(addr), (b)) #else -#define readw(addr) in_be16((volatile u16 *)(addr)) -#define readl(addr) in_be32((volatile u32 *)(addr)) -#define writew(b,addr) out_be16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_be32((volatile u32 *)(addr),(b)) +/* + * For coldfire these read a big endian value and use it + * as-is. This means that for little endian devices on the + * bus like PCI device these won't work as expected currently. + */ +#define readw(addr) in_be16((volatile u16 *)(addr)) +#define readl(addr) in_be32((volatile u32 *)(addr)) +#define writew(b, addr) out_be16((volatile u16 *)(addr), (b)) +#define writel(b, addr) out_be32((volatile u32 *)(addr), (b)) #endif /* diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile index cf93715637a..9ad67c4272c 100644 --- a/arch/m68k/lib/Makefile +++ b/arch/m68k/lib/Makefile @@ -9,3 +9,4 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o ashrdi3.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_ARCH_COLDFIRE) += cache.o interrupts.o time.o traps.o bdinfo.o fec.o +obj-$(CONFIG_MCF5441x) += clock.o diff --git a/arch/m68k/lib/clock.c b/arch/m68k/lib/clock.c new file mode 100644 index 00000000000..5d9aeed96c3 --- /dev/null +++ b/arch/m68k/lib/clock.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2026 Kernelspace + * Angelo Dureghello <[email protected]> + */ + +#include <config.h> +#include <asm/arch/clock.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; +/* + * Stub to use existing nxp/fsl drivers. + */ +int mxc_get_clock(enum mxc_clock clk) +{ + if (clk == MXC_ESDHC_CLK) + return gd->arch.sdhc_clk; + + printf("Unsupported MXC CLK: %d\n", clk); + + return 0; +} diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 36612756294..75913d4f1ae 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -267,8 +267,8 @@ config CPU_MIPS64_OCTEON select 64BIT select SPL_64BIT if SPL help - Choose this option for Marvell Octeon CPUs. These CPUs are between - MIPS64 R5 and R6 with other extensions. + Choose this option for Marvell Octeon CPUs. These CPUs are between + MIPS64 R5 and R6 with other extensions. endchoice @@ -351,7 +351,7 @@ config MIPS_RELOCATION_TABLE_SIZE range 0x100 0x10000 default "0xc000" if TARGET_MALTA default "0x8000" - ---help--- + help A table of relocation data will be appended to the U-Boot binary and parsed in relocate_code() to fix up all offsets in the relocated U-Boot. @@ -526,7 +526,7 @@ config MIPS_SRAM_INIT config DMA_ADDR_T_64BIT bool help - Select this to enable 64-bit DMA addressing + Select this to enable 64-bit DMA addressing config SYS_DCACHE_SIZE int diff --git a/arch/mips/dts/mt7621-u-boot.dtsi b/arch/mips/dts/mt7621-u-boot.dtsi index fbac2ade25a..a6e585a0853 100644 --- a/arch/mips/dts/mt7621-u-boot.dtsi +++ b/arch/mips/dts/mt7621-u-boot.dtsi @@ -47,13 +47,13 @@ &binman { u-boot-spl-ddr { - align = <4>; - align-size = <4>; + align = <8>; + align-size = <8>; filename = "u-boot-spl-ddr.bin"; pad-byte = <0xff>; u-boot-spl { - align-end = <4>; + align-end = <8>; filename = "u-boot-spl.bin"; }; @@ -90,7 +90,7 @@ #ifndef CONFIG_MT7621_BOOT_FROM_NAND u-boot-tpl { - align-end = <4>; + align-end = <8>; filename = "u-boot-tpl.bin"; }; #endif diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h index 00699c4c11a..1156e299433 100644 --- a/arch/mips/include/asm/system.h +++ b/arch/mips/include/asm/system.h @@ -259,9 +259,9 @@ extern void __die_if_kernel(const char *, struct pt_regs *, const char *where, unsigned long line); #define die(msg, regs) \ - __die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) + __die(msg, regs, __FILE__ ":" __func__, __LINE__) #define die_if_kernel(msg, regs) \ - __die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__) + __die_if_kernel(msg, regs, __FILE__ ":" __func__, __LINE__) static inline void execution_hazard_barrier(void) { diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index 6105cdcf96e..cd1e377c79d 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -25,8 +25,8 @@ choice config SOC_OCTEON3 bool "Octeon III family" help - This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx - and CNF75XX. + This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx + and CNF75XX. endchoice @@ -38,14 +38,14 @@ config TARGET_OCTEON_EBB7304 bool "Marvell Octeon EBB7304" select OCTEON_CN73XX help - Choose this for the Octeon EBB7304 board + Choose this for the Octeon EBB7304 board config TARGET_OCTEON_NIC23 bool "Marvell Octeon NIC23" select ARCH_MISC_INIT select OCTEON_CN73XX help - Choose this for the Octeon NIC23 board + Choose this for the Octeon NIC23 board endchoice diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 5b1311d8b5b..817728aa569 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -41,8 +41,8 @@ int dram_init(void) * No DDR init yet -> run in L2 cache */ gd->ram_size = (4 << 20); - gd->bd->bi_dram[0].size = gd->ram_size; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = gd->ram_size; + gd->dram[1].size = 0; } return 0; diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 6e30df6504e..32e86d84a12 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -32,7 +32,7 @@ archprepare: checkgcc4 # GCC 3.x is reported to have problems generating the type of relocation # that U-Boot wants. -# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html +# See https://patch.msgid.link/1348500648.2514.2.camel@petert/ checkgcc4: @if test "$(call cc-name)" = "gcc" -a \ $(call cc-version) -lt 0400; then \ diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 55152ab227e..32a140b0913 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -966,14 +966,14 @@ config E500 bool default y help - Enable PowerPC E500 cores, including e500v1, e500v2, e500mc + Enable PowerPC E500 cores, including e500v1, e500v2, e500mc config E500MC bool select BTB imply CMD_PCI help - Enble PowerPC E500MC core + Enable PowerPC E500MC core config E5500 bool @@ -982,7 +982,7 @@ config E6500 bool select BTB help - Enable PowerPC E6500 core + Enable PowerPC E6500 core config NOBQFMAN bool @@ -990,7 +990,7 @@ config NOBQFMAN config FSL_LAW bool help - Use Freescale common code for Local Access Window + Use Freescale common code for Local Access Window config HETROGENOUS_CLUSTERS bool @@ -1054,10 +1054,10 @@ config SYS_CCSRBAR_DEFAULT ARCH_T4240 default 0xe0000000 if ARCH_QEMU_E500 help - Default value of CCSRBAR comes from power-on-reset. It - is fixed on each SoC. Some SoCs can have different value - if changed by pre-boot regime. The value here must match - the current value in SoC. If not sure, do not change. + Default value of CCSRBAR comes from power-on-reset. It + is fixed on each SoC. Some SoCs can have different value + if changed by pre-boot regime. The value here must match + the current value in SoC. If not sure, do not change. config SYS_DPAA_PME bool @@ -1287,8 +1287,8 @@ config SYS_FSL_NUM_LAWS default 8 if ARCH_MPC8540 || \ ARCH_MPC8560 help - Number of local access windows. This is fixed per SoC. - If not sure, do not change. + Number of local access windows. This is fixed per SoC. + If not sure, do not change. config SYS_FSL_CORES_PER_CLUSTER int @@ -1308,8 +1308,8 @@ config SYS_NUM_TLBCAMS default 64 if E500MC default 16 help - Number of TLB CAM entries for Book-E chips. 64 for E500MC, - 16 for other E500 SoCs. + Number of TLB CAM entries for Book-E chips. 64 for E500MC, + 16 for other E500 SoCs. config L2_CACHE bool "Enable L2 cache support" @@ -1375,7 +1375,7 @@ config SYS_L3_SIZE int default 262144 if SYS_L3_SIZE_256KB default 524288 if SYS_L3_SIZE_512KB - default 1048576 if SYS_L3_SIZE_512KB + default 1048576 if SYS_L3_SIZE_1024KB config SYS_PPC64 bool @@ -1401,12 +1401,12 @@ config SYS_PPC_E500_DEBUG_TLB ARCH_BSC9132 || \ ARCH_C29X help - Select a temporary TLB entry to be used during boot to work - around limitations in e500v1 and e500v2 external debugger - support. This reduces the portions of the boot code where - breakpoints and single stepping do not work. The value of this - symbol should be set to the TLB1 entry to be used for this - purpose. If unsure, do not change. + Select a temporary TLB entry to be used during boot to work + around limitations in e500v1 and e500v2 external debugger + support. This reduces the portions of the boot code where + breakpoints and single stepping do not work. The value of this + symbol should be set to the TLB1 entry to be used for this + purpose. If unsure, do not change. config SYS_FSL_IFC_CLK_DIV int "Divider of platform clock" @@ -1419,8 +1419,8 @@ config SYS_FSL_IFC_CLK_DIV ARCH_T4240 default 1 help - Defines divider of platform clock(clock input to - IFC controller). + Defines divider of platform clock(clock input to + IFC controller). config SYS_FSL_LBC_CLK_DIV int "Divider of platform clock" @@ -1435,8 +1435,8 @@ config SYS_FSL_LBC_CLK_DIV default 1 help - Defines divider of platform clock(clock input to - eLBC controller). + Defines divider of platform clock(clock input to + eLBC controller). config ENABLE_36BIT_PHYS bool "Enable 36bit physical address space support" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 739d14f8002..414782c835f 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -41,10 +41,12 @@ #ifdef CONFIG_FSL_CAAM #include <fsl_sec.h> #endif -#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_FSL_CORENET) #include <asm/fsl_pamu.h> +#if defined(CONFIG_NXP_ESBC) #include <fsl_secboot_err.h> #endif +#endif #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include <nand.h> #include <errno.h> @@ -899,6 +901,8 @@ int cpu_init_r(void) #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET) if (pamu_init() < 0) fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#elif defined(CONFIG_FSL_CORENET) + pamu_init(); #endif #ifdef CONFIG_FSL_CAAM diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index af6731cbb3a..ddf0ac99cf6 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -110,7 +110,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, break; #endif default: - printf("Error: Invalid device type to %s\n", __FUNCTION__); + printf("Error: Invalid device type to %s\n", __func__); return; } diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 766b0c05951..4fd3478ac2f 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -14,7 +14,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb -dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi deleted file mode 100644 index ad09b138fc8..00000000000 --- a/arch/powerpc/dts/p2041.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P2041 Silicon/SoC Device Tree Source (pre include) - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/dts-v1/; - -/include/ "e500mc_power_isa.dtsi" - -/ { - compatible = "fsl,P2041"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: PowerPC,e500mc@0 { - device_type = "cpu"; - reg = <0>; - fsl,portid-mapping = <0x80000000>; - }; - cpu1: PowerPC,e500mc@1 { - device_type = "cpu"; - reg = <1>; - fsl,portid-mapping = <0x40000000>; - }; - cpu2: PowerPC,e500mc@2 { - device_type = "cpu"; - reg = <2>; - fsl,portid-mapping = <0x20000000>; - }; - cpu3: PowerPC,e500mc@3 { - device_type = "cpu"; - reg = <3>; - fsl,portid-mapping = <0x10000000>; - }; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "simple-bus"; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <4>; - reg = <0x40000 0x40000>; - compatible = "fsl,mpic", "chrp,open-pic"; - device_type = "open-pic"; - clock-frequency = <0x0>; - }; - - espi0: spi@110000 { - compatible = "fsl,mpc8536-espi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x110000 0x1000>; - fsl,espi-num-chipselects = <4>; - status = "disabled"; - }; - - usb0: usb@210000 { - compatible = "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - phy_type = "utmi"; - }; - - usb1: usb@211000 { - compatible = "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - phy_type = "utmi"; - }; - - sata: sata@220000 { - compatible = "fsl,pq-sata-v2"; - reg = <0x220000 0x1000>; - interrupts = <68 0x2 0 0>; - sata-offset = <0x1000>; - sata-number = <2>; - sata-fpdma = <0>; - }; - - esdhc: esdhc@114000 { - compatible = "fsl,esdhc"; - reg = <0x114000 0x1000>; - clock-frequency = <0>; - }; - - /include/ "qoriq-i2c-0.dtsi" - /include/ "qoriq-i2c-1.dtsi" - }; - - pcie@ffe200000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ - law_trgt_if = <0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe201000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ - law_trgt_if = <1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe202000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ - law_trgt_if = <2>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; -}; diff --git a/arch/powerpc/dts/p2041rdb-u-boot.dtsi b/arch/powerpc/dts/p2041rdb-u-boot.dtsi new file mode 100644 index 00000000000..1dc83cf846b --- /dev/null +++ b/arch/powerpc/dts/p2041rdb-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&serial0 { + bootph-all; +}; + +&soc { + i2c@118000 { + bootph-all; + }; + + spi@110000 { + flash@0 { + spi-max-frequency = <10000000>; + }; + }; +}; + +#include "u-boot.dtsi" diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts deleted file mode 100644 index 0fa1f098524..00000000000 --- a/arch/powerpc/dts/p2041rdb.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P2041RDB Device Tree Source - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/include/ "p2041.dtsi" - -/ { - model = "fsl,P2041RDB"; - compatible = "fsl,P2041RDB"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - aliases { - phy_rgmii_0 = &phy_rgmii_0; - phy_rgmii_1 = &phy_rgmii_1; - phy_sgmii_2 = &phy_sgmii_2; - phy_sgmii_3 = &phy_sgmii_3; - phy_sgmii_4 = &phy_sgmii_4; - phy_sgmii_1c = &phy_sgmii_1c; - phy_sgmii_1d = &phy_sgmii_1d; - phy_sgmii_1e = &phy_sgmii_1e; - phy_sgmii_1f = &phy_sgmii_1f; - phy_xgmii_2 = &phy_xgmii_2; - spi0 = &espi0; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - - fman@400000 { - ethernet@e0000 { - phy-handle = <&phy_sgmii_2>; - phy-connection-type = "sgmii"; - }; - - mdio@e1120 { - phy_rgmii_0: ethernet-phy@0 { - reg = <0x0>; - }; - - phy_rgmii_1: ethernet-phy@1 { - reg = <0x1>; - }; - - phy_sgmii_2: ethernet-phy@2 { - reg = <0x2>; - }; - - phy_sgmii_3: ethernet-phy@3 { - reg = <0x3>; - }; - - phy_sgmii_4: ethernet-phy@4 { - reg = <0x4>; - }; - - phy_sgmii_1c: ethernet-phy@1c { - reg = <0x1c>; - }; - - phy_sgmii_1d: ethernet-phy@1d { - reg = <0x1d>; - }; - - phy_sgmii_1e: ethernet-phy@1e { - reg = <0x1e>; - }; - - phy_sgmii_1f: ethernet-phy@1f { - reg = <0x1f>; - }; - }; - - ethernet@e2000 { - phy-handle = <&phy_sgmii_3>; - phy-connection-type = "sgmii"; - }; - - ethernet@e4000 { - phy-handle = <&phy_sgmii_4>; - phy-connection-type = "sgmii"; - }; - - ethernet@e6000 { - phy-handle = <&phy_rgmii_1>; - phy-connection-type = "rgmii"; - }; - - ethernet@e8000 { - phy-handle = <&phy_rgmii_0>; - phy-connection-type = "rgmii"; - }; - - ethernet@f0000 { - phy-handle = <&phy_xgmii_2>; - phy-connection-type = "xgmii"; - }; - - mdio@f1000 { - phy_xgmii_2: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0x0>; - }; - }; - }; - }; -}; - -&espi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - /* input clock */ - spi-max-frequency = <10000000>; - }; -}; - -/include/ "p2041si-post.dtsi" diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi deleted file mode 100644 index 8819199646f..00000000000 --- a/arch/powerpc/dts/p2041si-post.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * P2041/P2040 Silicon/SoC Device Tree Source (post include) - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2020 NXP - * - */ - -&soc { - -/include/ "qoriq-clockgen1.dtsi" -/include/ "qoriq-gpio-0.dtsi" -/include/ "qoriq-sec4.2-0.dtsi" - -/* include used FMan blocks */ -/include/ "qoriq-fman-0.dtsi" -/include/ "qoriq-fman-0-1g-0.dtsi" -/include/ "qoriq-fman-0-1g-1.dtsi" -/include/ "qoriq-fman-0-1g-2.dtsi" -/include/ "qoriq-fman-0-1g-3.dtsi" -/include/ "qoriq-fman-0-1g-4.dtsi" -/include/ "qoriq-fman-0-10g-0.dtsi" - fman@400000 { - enet0: ethernet@e0000 { - }; - - enet1: ethernet@e2000 { - }; - - enet2: ethernet@e4000 { - }; - - enet3: ethernet@e6000 { - }; - - enet4: ethernet@e8000 { - }; - - enet5: ethernet@f0000 { - }; - }; -}; diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ad7589123c6..485067ed266 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -14,9 +14,6 @@ config TARGET_ANDES_AE350 config TARGET_ANDES_VOYAGER bool "Support Andes Voyager Board" -config TARGET_BANANAPI_F3 - bool "Support BananaPi F3 Board" - config TARGET_BEAGLEBOARD_BEAGLEVFIRE bool "Support BeagleBoard BeagleV-Fire Board (based on Microchip MPFS)" @@ -50,6 +47,9 @@ config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 +config TARGET_SPACEMIT_K1 + bool "Support Spacemit K1 SoC" + config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board" select BOARD_LATE_INIT @@ -119,7 +119,7 @@ source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/sophgo/milkv_duo/Kconfig" source "board/sophgo/licheerv_nano/Kconfig" -source "board/spacemit/bananapi-f3/Kconfig" +source "board/spacemit/k1/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig index 14201df80f2..b155535658d 100644 --- a/arch/riscv/cpu/k1/Kconfig +++ b/arch/riscv/cpu/k1/Kconfig @@ -1,12 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-or-later # # Copyright (C) 2024, Kongyang Liu <[email protected]> +# Copyright (C) 2025-2026, RISCstar Ltd. + +if TARGET_SPACEMIT_K1 config SPACEMIT_K1 bool select BINMAN select ARCH_EARLY_INIT_R select SYS_CACHE_SHIFT_6 + select SUPPORT_SPL imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) @@ -17,3 +21,5 @@ config SPACEMIT_K1 imply SPL_CPU imply SPL_OPENSBI imply SPL_LOAD_FIT + +endif diff --git a/arch/riscv/cpu/k1/dram.c b/arch/riscv/cpu/k1/dram.c index cc1e903c9dd..2893bc6b99a 100644 --- a/arch/riscv/cpu/k1/dram.c +++ b/arch/riscv/cpu/k1/dram.c @@ -56,12 +56,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = min_t(phys_size_t, gd->ram_size, SZ_2G); if (gd->ram_size > SZ_2G && CONFIG_NR_DRAM_BANKS > 1) { - gd->bd->bi_dram[1].start = 0x100000000; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = 0x100000000; + gd->dram[1].size = gd->ram_size - SZ_2G; } return 0; @@ -82,8 +82,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - start[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + start[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 8e591cb7aa9..71c5c13d221 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -2,7 +2,6 @@ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb -dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index b518560bb94..84c261c6849 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -93,9 +93,7 @@ configurations { -#ifndef CONFIG_MULTI_DTB_FIT default = "conf-1"; -#endif #if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT) @conf-SEQ { diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi new file mode 100644 index 00000000000..7f9443d6951 --- /dev/null +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2026 RISCstar Ltd. + */ + +#include "binman.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; +}; + +&uart0 { + bootph-pre-ram; +}; + +&osc_32k { + bootph-pre-ram; +}; + +&vctcxo_1m { + bootph-pre-ram; +}; + +&vctcxo_3m { + bootph-pre-ram; +}; + +&vctcxo_24m { + bootph-pre-ram; +}; + +&syscon_mpmu { + bootph-pre-ram; +}; + +&pll { + bootph-pre-ram; +}; + +&syscon_apmu { + bootph-pre-ram; +}; + +&syscon_apbc { + bootph-pre-ram; +}; + +&i2c2 { + bootph-pre-ram; + resets = <&syscon_apbc RESET_TWSI2>; + + eeprom@50 { + bootph-pre-ram; + }; +}; + +/* + * The kernel pmic@41 nodes use the standard regulator-* properties only; + * U-Boot's regulator framework looks up suppliers by `regulator-name`. + * Carry the U-Boot-specific names (vdd_core / vdd_1v8 / vdd_1v8_mmc) here + * so SPL can program the bucks that DDR training depends on. + */ +&i2c8 { + bootph-pre-ram; + resets = <&syscon_apbc RESET_TWSI8>; + + pmic@41 { + bootph-pre-ram; + + regulators { + buck1 { + regulator-name = "vdd_core"; + bootph-pre-ram; + }; + + buck3 { + regulator-name = "vdd_1v8"; + bootph-pre-ram; + }; + + aldo1 { + regulator-name = "vdd_1v8_mmc"; + bootph-pre-ram; + }; + }; + }; +}; + +&binman { + u-boot-spl-ddr { + type = "section"; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + }; + + ddr-fw { + type = "blob"; + filename = "ddr_fw.bin"; + align = <64>; + }; + + u-boot-any { + type = "section"; + size = <0>; + offset = <0>; + }; + }; +}; diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts deleted file mode 100644 index 6b5b83bcdb9..00000000000 --- a/arch/riscv/dts/k1-bananapi-f3.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2024 Yangyu Chen <[email protected]> - */ - -#include "k1.dtsi" -#include "binman.dtsi" -#include "k1-pinctrl.dtsi" - -/ { - model = "Banana Pi BPI-F3"; - compatible = "bananapi,bpi-f3", "spacemit,k1"; - - chosen { - stdout-path = "serial0"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x80000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; -}; diff --git a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi new file mode 100644 index 00000000000..8a9a2a09de9 --- /dev/null +++ b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2026 RISCstar Ltd. + */ + +#include <dt-bindings/clock/spacemit,k1-syscon.h> +#include "binman.dtsi" + +/ { + aliases { + console = &uart0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; +}; + +&syscon_mpmu { + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, + <&pll CLK_PLL1_D4>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", + "pll1_d4"; +}; + +&syscon_apbc { + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, + <&pll CLK_PLL1_D4>, + <&syscon_mpmu CLK_PLL1_31P5>, + <&syscon_apmu CLK_PMUA_ACLK>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", + "pll1_d4", "pll1_d78_31p5", "pmua_aclk"; +}; + +&uart0 { + bootph-pre-ram; +}; + +&osc_32k { + bootph-pre-ram; +}; + +&vctcxo_1m { + bootph-pre-ram; +}; + +&vctcxo_3m { + bootph-pre-ram; +}; + +&vctcxo_24m { + bootph-pre-ram; +}; + +&syscon_mpmu { + bootph-pre-ram; +}; + +&pll { + bootph-pre-ram; +}; + +&syscon_apmu { + bootph-pre-ram; +}; + +&syscon_apbc { + bootph-pre-ram; +}; + +&i2c2 { + bootph-pre-ram; + status = "okay"; + pinctrl-0 = <&i2c2_0_cfg>; + pinctrl-names = "default"; + resets = <&syscon_apbc RESET_TWSI2>; + + eeprom@50 { + bootph-pre-ram; + status = "okay"; + compatible = "atmel,24c02"; + reg = <0x50>; + vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ + pagesize = <16>; + read-only; + size = <256>; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + mac-address { + #nvmem-cell-cells = <1>; + }; + + num-macs { + }; + + serial-number { + }; + }; + }; +}; + +&i2c8 { + bootph-pre-ram; + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + resets = <&syscon_apbc RESET_TWSI8>; + status = "okay"; + + pmic@41 { + bootph-pre-ram; + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + status = "okay"; + + regulators { + buck1 { + bootph-pre-ram; + regulator-name = "vdd_core"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + bootph-pre-ram; + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + bootph-pre-ram; + regulator-name = "vdd_1v8_mmc"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + +&qspi { + bootph-pre-ram; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + m25p,fast-read; + broken-flash-reset; + status = "okay"; + }; +}; + +&binman { + u-boot-spl-ddr { + type = "section"; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + }; + + ddr-fw { + type = "blob"; + filename = "ddr_fw.bin"; + align = <64>; + }; + + u-boot-any { + type = "section"; + size = <0>; + offset = <0>; + }; + }; +}; diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1-pinctrl.dtsi deleted file mode 100644 index 14e7096fbcf..00000000000 --- a/arch/riscv/dts/k1-pinctrl.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 Spacemit Inc. - * Copyright (C) 2025 Yixun Lan <[email protected]> - */ - -#define K1_PADCONF(pin, func) (((pin) << 16) | (func)) - -&pinctrl { - uart0_2_cfg: uart0-2-cfg { - uart0-2-pins { - pinmux = <K1_PADCONF(68, 2)>, - <K1_PADCONF(69, 2)>; - - bias-pull-up = <0>; - drive-strength = <32>; - }; - }; -}; diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi deleted file mode 100644 index a633e43da32..00000000000 --- a/arch/riscv/dts/k1.dtsi +++ /dev/null @@ -1,480 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2024 Yangyu Chen <[email protected]> - */ - -/dts-v1/; -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "SpacemiT K1"; - compatible = "spacemit,k1"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - serial8 = &uart9; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <24000000>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_0>; - }; - core1 { - cpu = <&cpu_1>; - }; - core2 { - cpu = <&cpu_2>; - }; - core3 { - cpu = <&cpu_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu_4>; - }; - core1 { - cpu = <&cpu_5>; - }; - core2 { - cpu = <&cpu_6>; - }; - core3 { - cpu = <&cpu_7>; - }; - }; - }; - - cpu_0: cpu@0 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <0>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_1: cpu@1 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <1>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_2: cpu@2 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <2>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_3: cpu@3 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <3>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_4: cpu@4 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <4>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu4_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_5: cpu@5 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <5>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu5_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_6: cpu@6 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <6>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu6_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_7: cpu@7 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <7>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu7_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cluster0_l2_cache: l2-cache0 { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-size = <524288>; - cache-sets = <512>; - cache-unified; - }; - - cluster1_l2_cache: l2-cache1 { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-size = <524288>; - cache-sets = <512>; - cache-unified; - }; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <2>; - #size-cells = <2>; - dma-noncoherent; - ranges; - - uart0: serial@d4017000 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017000 0x0 0x100>; - interrupts = <42>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@d4017100 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017100 0x0 0x100>; - interrupts = <44>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@d4017200 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017200 0x0 0x100>; - interrupts = <45>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart4: serial@d4017300 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017300 0x0 0x100>; - interrupts = <46>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart5: serial@d4017400 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017400 0x0 0x100>; - interrupts = <47>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart6: serial@d4017500 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017500 0x0 0x100>; - interrupts = <48>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart7: serial@d4017600 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017600 0x0 0x100>; - interrupts = <49>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart8: serial@d4017700 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017700 0x0 0x100>; - interrupts = <50>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart9: serial@d4017800 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017800 0x0 0x100>; - interrupts = <51>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - plic: interrupt-controller@e0000000 { - compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xe0000000 0x0 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>, - <&cpu5_intc 11>, <&cpu5_intc 9>, - <&cpu6_intc 11>, <&cpu6_intc 9>, - <&cpu7_intc 11>, <&cpu7_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - riscv,ndev = <159>; - }; - - clint: timer@e4000000 { - compatible = "spacemit,k1-clint", "sifive,clint0"; - reg = <0x0 0xe4000000 0x0 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>, - <&cpu4_intc 3>, <&cpu4_intc 7>, - <&cpu5_intc 3>, <&cpu5_intc 7>, - <&cpu6_intc 3>, <&cpu6_intc 7>, - <&cpu7_intc 3>, <&cpu7_intc 7>; - }; - - sec_uart1: serial@f0612000 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xf0612000 0x0 0x100>; - interrupts = <43>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "reserved"; /* for TEE usage */ - }; - - reset: reset-controller@d4050000 { - compatible = "spacemit,k1-reset"; - reg = <0x0 0xd4050000 0x0 0x209c>, - <0x0 0xd4282800 0x0 0x400>, - <0x0 0xd4015000 0x0 0x1000>, - <0x0 0xd4090000 0x0 0x1000>, - <0x0 0xd4282c00 0x0 0x400>, - <0x0 0xd8440000 0x0 0x98>, - <0x0 0xc0000000 0x0 0x4280>, - <0x0 0xf0610000 0x0 0x20>; - reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2"; - #reset-cells = <1>; - status = "disabled"; - }; - - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k1-pinctrl", "pinctrl-single"; - reg = <0x0 0xd401e000 0x0 0x400>; - pinctrl-single,register-width = <32>; - }; - }; -}; diff --git a/arch/sandbox/Makefile b/arch/sandbox/Makefile index 5bbf9f1f96b..0360d2bd886 100644 --- a/arch/sandbox/Makefile +++ b/arch/sandbox/Makefile @@ -1,13 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -head-y := arch/sandbox/cpu/start.o -head-$(CONFIG_SANDBOX_SDL) += arch/sandbox/cpu/sdl.o libs-y += arch/sandbox/cpu/ libs-y += arch/sandbox/lib/ - -# sdl.c fails to compile with -fshort-wchar using musl. -cmd_cc_sdl.o = $(CC) $(filter-out -nostdinc -fshort-wchar, \ - $(patsubst -I%,-idirafter%,$(c_flags))) -fno-lto -c -o $@ $< - -$(obj)/sdl.o: $(src)/sdl.c FORCE - $(call if_changed_dep,cc_sdl.o) diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index ee3c04c49e1..eb6bf6302e2 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -5,9 +5,8 @@ # (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, [email protected]. -obj-y := cache.o cpu.o state.o initjmp.o os.o -extra-y := start.o -extra-$(CONFIG_SANDBOX_SDL) += sdl.o +obj-y := start.o cache.o cpu.o state.o initjmp.o os.o +obj-$(CONFIG_SANDBOX_SDL) += sdl.o obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_ETH_SANDBOX_RAW) += eth-raw-os.o diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 7ee4975523e..460013f933b 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -131,8 +131,8 @@ SPL_LOAD_IMAGE_METHOD("sandbox_image", 7, BOOT_DEVICE_BOARD, load_from_image); int dram_init_banksize(void) { /* These are necessary so TFTP can use LMBs to check its load address */ - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); return 0; } @@ -265,6 +265,43 @@ int sandbox_spl_load_fit(char *fname, int maxlen, struct spl_image_info *image) return 0; } +int sandbox_spl_load_fit_full(char *fname, int maxlen, + struct spl_image_info *image) +{ + struct legacy_img_hdr *header; + long long size; + int ret; + int fd; + + ret = sandbox_find_next_phase(fname, maxlen, true); + if (ret) { + printf("%s not found, error %d\n", fname, ret); + return log_msg_ret("nph", ret); + } + + log_debug("reading from %s\n", fname); + fd = os_open(fname, OS_O_RDONLY); + if (fd < 0) { + printf("Failed to open '%s'\n", fname); + return log_msg_ret("ope", -errno); + } + + if (os_get_filesize(fname, &size)) + return log_msg_ret("fis", -ENOENT); + + header = spl_get_load_buffer(0, size); + + if (os_read(fd, header, size) != size) + return log_msg_ret("rea", -EIO); + os_close(fd); + + ret = spl_load_fit_image(image, header); + if (ret) + return log_msg_ret("slf", ret); + + return 0; +} + static int upl_load_from_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { diff --git a/arch/sandbox/dts/sandbox-boot.sh b/arch/sandbox/dts/sandbox-boot.sh new file mode 100644 index 00000000000..4f7fa661151 --- /dev/null +++ b/arch/sandbox/dts/sandbox-boot.sh @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +echo "* default script" diff --git a/arch/sandbox/dts/sandbox-inner.sh b/arch/sandbox/dts/sandbox-inner.sh new file mode 100644 index 00000000000..b8fc8f7484b --- /dev/null +++ b/arch/sandbox/dts/sandbox-inner.sh @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +# Some comment. +echo "* inner" diff --git a/arch/sandbox/dts/sandbox-outer.sh b/arch/sandbox/dts/sandbox-outer.sh new file mode 100644 index 00000000000..40294085433 --- /dev/null +++ b/arch/sandbox/dts/sandbox-outer.sh @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +echo "* outer 1" +source ${fdtcontroladdr}:inner +echo "* outer 2" diff --git a/arch/sandbox/dts/sandbox_pmic.dtsi b/arch/sandbox/dts/sandbox_pmic.dtsi index ff2cb42844c..d90ab040827 100644 --- a/arch/sandbox/dts/sandbox_pmic.dtsi +++ b/arch/sandbox/dts/sandbox_pmic.dtsi @@ -47,6 +47,12 @@ regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; }; + + ldo3 { + regulator-name = "SUPPLY_1.8_3.3V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; }; &mc34708 { diff --git a/arch/sandbox/dts/sandbox_scripts.dtsi b/arch/sandbox/dts/sandbox_scripts.dtsi new file mode 100644 index 00000000000..c800ec39e87 --- /dev/null +++ b/arch/sandbox/dts/sandbox_scripts.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/ { + images { + default = "boot"; + boot { + description = "Test boot script"; + data = /incbin/("sandbox-boot.sh"); + type = "script"; + compression = "none"; + }; + outer { + description = "Script testing recursion"; + data = /incbin/("sandbox-outer.sh"); + type = "script"; + compression = "none"; + }; + inner { + description = "Another test script"; + data = /incbin/("sandbox-inner.sh"); + type = "script"; + compression = "none"; + }; + }; +}; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index ac92ebf1afd..d24feec5422 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -16,6 +16,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/sandbox-pinmux.h> #include <dt-bindings/mux/mux.h> +#include <dt-bindings/phy/phy.h> / { model = "sandbox"; @@ -175,7 +176,7 @@ storage = "mmc3"; skip-offset = <0x800000>; area-start = <0>; - area-size = <0xe00000>; + area-size = <0x2000000>; state-offset = <0xdffc00>; state-size = <0x40>; version-offset = <0xdffe00>; @@ -502,6 +503,65 @@ phy-names = "phy1"; }; + /* PHY common props test nodes */ + phy_common_props_missing: phy-common-props-missing { + /* empty: no rx-polarity or tx-polarity properties */ + }; + + phy_common_props_more_values: phy-common-props-more-values { + /* 3 values but only 2 names => count mismatch */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT PHY_POL_NORMAL>; + rx-polarity-names = "sgmii", "2500base-x"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT PHY_POL_NORMAL>; + tx-polarity-names = "sgmii", "2500base-x"; + }; + + phy_common_props_single: phy-common-props-single { + /* 1 value, no names array => value applies to all modes */ + rx-polarity = <PHY_POL_INVERT>; + tx-polarity = <PHY_POL_INVERT>; + }; + + phy_common_props_more_names: phy-common-props-more-names { + /* 2 values but 3 names => count mismatch */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + rx-polarity-names = "sgmii", "2500base-x", "1000base-x"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + tx-polarity-names = "sgmii", "2500base-x", "1000base-x"; + }; + + phy_common_props_find_by_name: phy-common-props-find-by-name { + /* valid 3-element arrays, lookup by mode name */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT PHY_POL_AUTO>; + rx-polarity-names = "sgmii", "2500base-x", "usb-ss"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT PHY_POL_NORMAL>; + tx-polarity-names = "sgmii", "2500base-x", "1000base-x"; + }; + + phy_common_props_no_default: phy-common-props-no-default { + /* name not in array, no "default" entry => -EINVAL */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + rx-polarity-names = "2500base-x", "1000base-x"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + tx-polarity-names = "2500base-x", "1000base-x"; + }; + + phy_common_props_with_default: phy-common-props-with-default { + /* name not in array, but "default" entry exists */ + rx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + rx-polarity-names = "2500base-x", "default"; + tx-polarity = <PHY_POL_NORMAL PHY_POL_INVERT>; + tx-polarity-names = "2500base-x", "default"; + }; + + phy_common_props_unsupported: phy-common-props-unsupported { + /* PHY_POL_AUTO is not supported for manual-only modes */ + rx-polarity = <PHY_POL_AUTO>; + rx-polarity-names = "sgmii"; + tx-polarity = <PHY_POL_AUTO>; + tx-polarity-names = "sgmii"; + }; + some-bus { #address-cells = <1>; #size-cells = <0>; @@ -967,6 +1027,9 @@ emul1: emull { compatible = "sandbox,i2c-rtc-emul"; }; + emul_pmbus: emul-pmbus { + compatible = "sandbox,i2c-pmbus"; + }; }; sandbox_pmic: sandbox_pmic@40 { @@ -978,6 +1041,13 @@ reg = <0x41>; sandbox,emul = <&emul_pmic1>; }; + + pmbus@70 { + reg = <0x70>; + compatible = "pmbus"; + regulator-name = "sandbox-pmbus-vout"; + sandbox,emul = <&emul_pmbus>; + }; }; i3c0 { @@ -1470,10 +1540,16 @@ #reset-cells = <1>; }; + resetc_fb: reset-ctl-fallback { + compatible = "sandbox,reset-ctl-fallback-only"; + #reset-cells = <1>; + }; + reset-ctl-test { compatible = "sandbox,reset-ctl-test"; - resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>; - reset-names = "other", "test", "test2", "test3"; + resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>, + <&resetc_fb 5>; + reset-names = "other", "test", "test2", "test3", "fallback"; }; rng { diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h index f0709b41c09..2890e0dc09b 100644 --- a/arch/sandbox/include/asm/reset.h +++ b/arch/sandbox/include/asm/reset.h @@ -10,6 +10,7 @@ struct udevice; int sandbox_reset_query(struct udevice *dev, unsigned long id); int sandbox_reset_is_requested(struct udevice *dev, unsigned long id); +int sandbox_reset_get_count(struct udevice *dev, unsigned long id); int sandbox_reset_test_get(struct udevice *dev); int sandbox_reset_test_get_devm(struct udevice *dev); @@ -19,6 +20,8 @@ int sandbox_reset_test_assert(struct udevice *dev); int sandbox_reset_test_assert_bulk(struct udevice *dev); int sandbox_reset_test_deassert(struct udevice *dev); int sandbox_reset_test_deassert_bulk(struct udevice *dev); +int sandbox_reset_test_reset(struct udevice *dev); +int sandbox_reset_test_reset_bulk(struct udevice *dev); int sandbox_reset_test_free(struct udevice *dev); int sandbox_reset_test_release_bulk(struct udevice *dev); diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h index d824b2123a2..49a613ba92d 100644 --- a/arch/sandbox/include/asm/spl.h +++ b/arch/sandbox/include/asm/spl.h @@ -46,4 +46,18 @@ int sandbox_find_next_phase(char *fname, int maxlen, bool use_img); */ int sandbox_spl_load_fit(char *fname, int maxlen, struct spl_image_info *image); +/** + * sandbox_spl_load_fit_full() - Load the next phase from a FIT with the "full" loader + * + * Loads a FIT containing the next phase and sets it up for booting, using the + * "full" FIT loader + * + * @fname: Returns filename loaded + * @maxlen: Maximum length for @fname including \0 + * @image: Place to put SPL-image information + * Return: 0 if OK, -ve on error + */ +int sandbox_spl_load_fit_full(char *fname, int maxlen, + struct spl_image_info *image); + #endif diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 0e8d19ce232..0438790028b 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -244,6 +244,14 @@ uint sandbox_spi_get_speed(struct udevice *dev); uint sandbox_spi_get_mode(struct udevice *dev); /** + * sandbox_spi_get_wordlen() - Get current wordlen setting of a sandbox spi slave + * + * @dev: Device to check + * Return: current wordlen + */ +uint sandbox_spi_get_wordlen(struct udevice *dev); + +/** * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status * * @dev: Device to check diff --git a/arch/sh/include/asm/string.h b/arch/sh/include/asm/string.h index 999febcb6b7..12a9a8f796c 100644 --- a/arch/sh/include/asm/string.h +++ b/arch/sh/include/asm/string.h @@ -8,8 +8,6 @@ * from linux kernel code. */ -#ifdef __KERNEL__ /* only set these up for kernel code */ - #define __HAVE_ARCH_STRCPY static inline char *strcpy(char *__dest, const char *__src) { @@ -81,53 +79,4 @@ static inline int strcmp(const char *__cs, const char *__ct) return __res; } -#undef __HAVE_ARCH_STRNCMP -extern int strncmp(const char *__cs, const char *__ct, size_t __n); - -#undef __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, size_t __count); - -#undef __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, size_t __n); - -#undef __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, size_t __n); - -#undef __HAVE_ARCH_MEMCHR -extern void *memchr(const void *__s, int __c, size_t __n); - -#undef __HAVE_ARCH_STRLEN -extern size_t strlen(const char *); - -/* arch/sh/lib/strcasecmp.c */ -extern int strcasecmp(const char *, const char *); - -#else /* KERNEL */ - -/* - * let user libraries deal with these, - * IMHO the kernel has no place defining these functions for user apps - */ - -#define __HAVE_ARCH_STRCPY 1 -#define __HAVE_ARCH_STRNCPY 1 -#define __HAVE_ARCH_STRCAT 1 -#define __HAVE_ARCH_STRNCAT 1 -#define __HAVE_ARCH_STRCMP 1 -#define __HAVE_ARCH_STRNCMP 1 -#define __HAVE_ARCH_STRNICMP 1 -#define __HAVE_ARCH_STRCHR 1 -#define __HAVE_ARCH_STRRCHR 1 -#define __HAVE_ARCH_STRSTR 1 -#define __HAVE_ARCH_STRLEN 1 -#define __HAVE_ARCH_STRNLEN 1 -#define __HAVE_ARCH_MEMSET 1 -#define __HAVE_ARCH_MEMCPY 1 -#define __HAVE_ARCH_MEMMOVE 1 -#define __HAVE_ARCH_MEMSCAN 1 -#define __HAVE_ARCH_MEMCMP 1 -#define __HAVE_ARCH_MEMCHR 1 -#define __HAVE_ARCH_STRTOK 1 - -#endif /* KERNEL */ #endif /* __ASM_SH_STRING_H */ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 8f21b78dbe4..ec4d484a669 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -44,9 +44,9 @@ config X86_RUN_64BIT_NO_SPL bool "64-bit" select X86_64 help - Build U-Boot as a 64-bit binary without SPL. As U-Boot enters - in 64-bit mode, the assumption is that the silicon is fully - initialized (MP, page tables, etc.). + Build U-Boot as a 64-bit binary without SPL. As U-Boot enters + in 64-bit mode, the assumption is that the silicon is fully + initialized (MP, page tables, etc.). endchoice @@ -585,11 +585,11 @@ config DCACHE_RAM_MRC_VAR_SIZE not boot. config HAVE_REFCODE - bool "Add a Reference Code binary" - help - Select this option to add a Reference Code binary to the resulting - U-Boot image. This is an Intel binary blob that handles system - initialisation, in this case the PCH and System Agent. + bool "Add a Reference Code binary" + help + Select this option to add a Reference Code binary to the resulting + U-Boot image. This is an Intel binary blob that handles system + initialisation, in this case the PCH and System Agent. Note: Without this binary (on platforms that need it such as broadwell) U-Boot will be missing some critical setup steps. @@ -617,8 +617,8 @@ config SMP_AP_WORK bool depends on SMP help - Allow APs to do other work after initialisation instead of going - to sleep. + Allow APs to do other work after initialisation instead of going + to sleep. config MAX_CPUS int "Maximum number of CPUs permitted" diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index f480bb1d8c3..d1f592ec57e 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -171,11 +171,9 @@ static int cpu_apl_probe(struct udevice *dev) return 0; } -#ifdef CONFIG_ACPIGEN -struct acpi_ops apl_cpu_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_cpu_acpi_ops = { .fill_ssdt = acpi_cpu_fill_ssdt, }; -#endif static const struct cpu_ops cpu_x86_apl_ops = { .get_desc = cpu_x86_get_desc, diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 8198667fa50..080c5a58575 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -6,7 +6,7 @@ */ #include <dm.h> -#include <ec_commands.h> +#include <cros_ec.h> #include <init.h> #include <log.h> #include <spi_flash.h> diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 284f16cfd91..360d091121c 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -366,7 +366,7 @@ ulong sa_get_tseg_base(struct udevice *dev) return sa_read_reg(dev, TSEG); } -struct acpi_ops apl_hostbridge_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_hostbridge_acpi_ops = { .get_name = apl_acpi_hb_get_name, #if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) .write_tables = apl_acpi_hb_write_tables, diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index f34c199bf73..008c4dc0037 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -119,7 +119,7 @@ static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "LPCB"); } -struct acpi_ops apl_lpc_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_lpc_acpi_ops = { .get_name = apl_acpi_lpc_get_name, #ifdef CONFIG_GENERATE_ACPI_TABLE .write_tables = intel_southbridge_write_acpi_tables, diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index cc1edd7badd..81604ee12fb 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -91,8 +91,8 @@ int dram_init_banksize(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; if (memrange->type == CB_MEM_RAM) { - gd->bd->bi_dram[j].start = memrange->base; - gd->bd->bi_dram[j].size = memrange->size; + gd->dram[j].start = memrange->base; + gd->dram[j].size = memrange->size; j++; if (j >= CONFIG_NR_DRAM_BANKS) break; diff --git a/arch/x86/cpu/efi/payload.c b/arch/x86/cpu/efi/payload.c index 6845ce72ff9..b86d50b2cab 100644 --- a/arch/x86/cpu/efi/payload.c +++ b/arch/x86/cpu/efi/payload.c @@ -123,8 +123,8 @@ int dram_init_banksize(void) if (desc->type != EFI_CONVENTIONAL_MEMORY || (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20) continue; - gd->bd->bi_dram[num_banks].start = desc->physical_start; - gd->bd->bi_dram[num_banks].size = desc->num_pages << + gd->dram[num_banks].start = desc->physical_start; + gd->dram[num_banks].size = desc->num_pages << EFI_PAGE_SHIFT; num_banks++; } diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c index 6fe40071140..e09fce8bb1b 100644 --- a/arch/x86/cpu/efi/sdram.c +++ b/arch/x86/cpu/efi/sdram.c @@ -24,8 +24,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = efi_get_ram_base(); - gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE; + gd->dram[0].start = efi_get_ram_base(); + gd->dram[0].size = CONFIG_EFI_RAM_SIZE; return 0; } diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c index 75fa4e01d8a..1a24c10ab0b 100644 --- a/arch/x86/cpu/intel_common/generic_wifi.c +++ b/arch/x86/cpu/intel_common/generic_wifi.c @@ -102,7 +102,7 @@ static int intel_wifi_acpi_fill_ssdt(const struct udevice *dev, return 0; } -struct acpi_ops wifi_acpi_ops = { +static const struct acpi_ops wifi_acpi_ops = { .fill_ssdt = intel_wifi_acpi_fill_ssdt, }; diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index baa1f0e32d6..11ce97b5143 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -67,8 +67,8 @@ void mrc_common_dram_init_banksize(void) if (area->start >= 1ULL << 32) continue; - gd->bd->bi_dram[num_banks].start = area->start; - gd->bd->bi_dram[num_banks].size = area->size; + gd->dram[num_banks].start = area->start; + gd->dram[num_banks].size = area->size; num_banks++; } } diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c index d20c9a2a379..a5e81dfada5 100644 --- a/arch/x86/cpu/ivybridge/sdram_nop.c +++ b/arch/x86/cpu/ivybridge/sdram_nop.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = 1ULL << 31; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/qemu/dram.c b/arch/x86/cpu/qemu/dram.c index ba3638e6acc..3cba04f2c3e 100644 --- a/arch/x86/cpu/qemu/dram.c +++ b/arch/x86/cpu/qemu/dram.c @@ -69,13 +69,13 @@ int dram_init_banksize(void) { u64 high_mem_size; - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = qemu_get_low_memory_size(); + gd->dram[0].start = 0; + gd->dram[0].size = qemu_get_low_memory_size(); high_mem_size = qemu_get_high_memory_size(); if (high_mem_size) { - gd->bd->bi_dram[1].start = SZ_4G; - gd->bd->bi_dram[1].size = high_mem_size; + gd->dram[1].start = SZ_4G; + gd->dram[1].size = high_mem_size; } return 0; diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c index 34e576940d4..34fdb7e026a 100644 --- a/arch/x86/cpu/quark/dram.c +++ b/arch/x86/cpu/quark/dram.c @@ -169,8 +169,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c index 75ca5273625..5aa4f6d3e07 100644 --- a/arch/x86/cpu/slimbootloader/sdram.c +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -129,8 +129,8 @@ int dram_init_banksize(void) return 0; /* simply use a single bank to have whole size for now */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c index 6192f2296b8..6ce96b0569b 100644 --- a/arch/x86/cpu/tangier/sdram.c +++ b/arch/x86/cpu/tangier/sdram.c @@ -160,8 +160,8 @@ static int sfi_get_bank_size(void) if (mentry->type != SFI_MEM_CONV) continue; - gd->bd->bi_dram[bank].start = mentry->phys_start; - gd->bd->bi_dram[bank].size = mentry->pages << 12; + gd->dram[bank].start = mentry->phys_start; + gd->dram[bank].size = mentry->pages << 12; bank++; } diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index cde4fbf3557..e054f42fa86 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -43,14 +43,13 @@ void bootm_announce_and_cleanup(void) #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL) int arch_fixup_memory_node(void *blob) { - struct bd_info *bd = gd->bd; int bank; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 730721dc176..a45e4060ef2 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -64,8 +64,8 @@ int dram_init_banksize(void) update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2); if (!ll_boot_init()) { - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = 0; + gd->dram[0].size = gd->ram_size; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); @@ -89,21 +89,21 @@ int dram_init_banksize(void) mtrr_top = max(mtrr_top, res_desc->phys_start + res_desc->len); } else { - gd->bd->bi_dram[bank].start = res_desc->phys_start; - gd->bd->bi_dram[bank].size = res_desc->len; + gd->dram[bank].start = res_desc->phys_start; + gd->dram[bank].size = res_desc->len; if (update_mtrr) mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, res_desc->len); log_debug("ram %llx %llx\n", - gd->bd->bi_dram[bank].start, - gd->bd->bi_dram[bank].size); + gd->dram[bank].start, + gd->dram[bank].size); } } /* Add the memory below 4GB */ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = low_end; + gd->dram[0].start = 0; + gd->dram[0].size = low_end; /* * Set up an MTRR to the top of low, reserved memory. This is necessary @@ -184,7 +184,7 @@ unsigned int install_e820_map(unsigned int max_entries, #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) int handoff_arch_save(struct spl_handoff *ho) { - ho->arch.usable_ram_top = gd->bd->bi_dram[0].size; + ho->arch.usable_ram_top = gd->dram[0].size; ho->arch.hob_list = gd->arch.hob_list; return 0; diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index ad25020086c..d425e80760b 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -150,7 +150,7 @@ static int fsp_video_acpi_write_tables(const struct udevice *dev, } #endif -struct acpi_ops fsp_video_acpi_ops = { +static const struct acpi_ops __maybe_unused fsp_video_acpi_ops = { #ifdef CONFIG_INTEL_GMA_ACPI .write_tables = fsp_video_acpi_write_tables, #endif |