diff options
Diffstat (limited to 'arch')
155 files changed, 2597 insertions, 1878 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index e59528e576e..ad232435eb2 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -1006,7 +1006,7 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level) /* Can we can just modify the current level block/page? */ if (is_aligned(start, size, levelsize)) { - if (attrs == PTE_TYPE_FAULT) { + if (attrs == PTE_TYPE_FAULT && flag) { if (pte_type(pte) == PTE_TYPE_TABLE && level < 3) *pte = 0; else diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 88adcf35432..37687a96600 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1402,32 +1402,43 @@ static int tfa_dram_init_banksize(void) dram_size -= gd->dram[i].size; i++; - } while (dram_size); + } while (dram_size && i < CONFIG_NR_DRAM_BANKS); + + if (dram_size) + printf("Warning: CONFIG_NR_DRAM_BANKS is too small, %llx bytes left unassigned\n", + dram_size); if (i > 0) ret = 0; #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD) /* Assign memory for MC */ -#ifdef CONFIG_SYS_DDR_BLOCK3_BASE - if (gd->dram[2].size >= +#if defined(CONFIG_SYS_DDR_BLOCK3_BASE) && (CONFIG_NR_DRAM_BANKS >= 3) + if (gd->dram[2].size && + gd->dram[2].size >= board_reserve_ram_top(gd->dram[2].size)) { gd->arch.resv_ram = gd->dram[2].start + - gd->dram[2].size - - board_reserve_ram_top(gd->dram[2].size); + gd->dram[2].size - + board_reserve_ram_top(gd->dram[2].size); } else #endif { - if (gd->dram[1].size >= +#if defined(CFG_SYS_DDR_BLOCK2_BASE) && (CONFIG_NR_DRAM_BANKS >= 2) + if (gd->dram[1].size && + gd->dram[1].size >= board_reserve_ram_top(gd->dram[1].size)) { gd->arch.resv_ram = gd->dram[1].start + gd->dram[1].size - board_reserve_ram_top(gd->dram[1].size); - } else if (gd->dram[0].size > - board_reserve_ram_top(gd->dram[0].size)) { - gd->arch.resv_ram = gd->dram[0].start + - gd->dram[0].size - - board_reserve_ram_top(gd->dram[0].size); + } else +#endif + { + if (gd->dram[0].size > + board_reserve_ram_top(gd->dram[0].size)) { + gd->arch.resv_ram = gd->dram[0].start + + gd->dram[0].size - + board_reserve_ram_top(gd->dram[0].size); + } } } #endif /* CONFIG_RESV_RAM */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d85a630f8a3..24ccb8bb0c4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -65,6 +65,11 @@ int ls_gic_rd_tables_init(void *blob) u64 gic_lpi_base; int ret; + if (!gd->arch.resv_ram) { + debug("%s: failed to reserve memory for gic-lpi-tables\n", __func__); + return -ENOMEM; + } + gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE); if (ret) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 25234697e6a..a02dad22f27 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -170,7 +170,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ cn9130-crb-B.dtb \ ac5-98dx35xx-rd.dtb \ ac5-98dx35xx-atl-x240.dtb \ - cn9130-atl-x250.dtb + cn9130-atl-x250.dtb \ + cn9130-atl-x960-28ysq.dtb endif dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb @@ -1154,7 +1155,7 @@ dtb-$(CONFIG_TARGET_SC589_MINI) += sc589-mini.dtb dtb-$(CONFIG_TARGET_SC589_EZKIT) += sc589-ezkit.dtb dtb-$(CONFIG_TARGET_SC594_SOM_EZKIT) += sc594-som-ezkit.dtb dtb-$(CONFIG_TARGET_SC594_SOM_EZLITE) += sc594-som-ezlite.dtb -dtb-$(CONFIG_TARGET_SC598_SOM_EZKIT) += sc598-som-ezkit.dtb +dtb-$(CONFIG_TARGET_SC598_SOM_EZKIT) += sc598-som-ezkit.dtb sc598-som-ezkit-sd.dtb dtb-$(CONFIG_TARGET_SC598_SOM_EZLITE) += sc598-som-ezlite.dtb ifneq ($(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)$(CONFIG_TARGET_IMX8MP_RSB3720A1_6G),) diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 595b4b5abba..1123a81a1a4 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -147,12 +147,12 @@ * for IO and the rest 112 MB (64+32+16) for MEM. Controller supports 32-bit IO mapping. * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): - * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 - * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf - * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 + * https://git.u-boot-project.org/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 + * https://git.u-boot-project.org/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf + * https://git.u-boot-project.org/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 * Bug related to requirement of same child and parent addresses for first range is fixed * in U-Boot version 2022.04 by following commit: - * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 + * https://git.u-boot-project.org/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 */ #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/dts/cn9130-atl-x960-28ysq.dts b/arch/arm/dts/cn9130-atl-x960-28ysq.dts new file mode 100644 index 00000000000..177d09b25b3 --- /dev/null +++ b/arch/arm/dts/cn9130-atl-x960-28ysq.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Allied Telesis Labs + */ + +#include "cn9130.dtsi" + +/ { + model = "Allied Telesis x960-28YSQ"; + compatible = "alliedtelesis,x960-28ysq", + "marvell,cn9130", + "marvell,armada-ap806-quad", + "marvell,armada-ap806"; + + aliases { + serial0 = &uart0; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + +}; + +/* + * AP related configuration + */ +&ap_pinctl { + /* AP_MPP Pins: + * GPIO & NC [0-10,12] + * UART0 [11,19] + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0 0 0 0 0 0 0 0 0 0 + 0 3 0 0 0 0 0 0 0 3 >; +}; + +&ap_gpio0 { + pp-reset { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "pp-reset"; + }; + + usb-en { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-en"; + }; + + fan-en { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "fan-en"; + }; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + /* MPP Bus: + * [0-1] DEV + * [2-8] GPIO + * [9] DEV + * [10-12] GPIO + * [13] ND_RB + * [14] GPIO + * [15-28] DEV + * [29-30] GPIO + * [31] DEV + * [32-34] GPIO + * [35-36] I2C1 + * [37-38] I2C0 + * [39-46] GPIO + * [47] SMI + * [48] GPIO + * [49] SMI + * [49-55] GPIO + * [56-60] SPI + * [61-62] GPIO + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 0 0 0 0 0 0 0 1 + 0 0 0 2 0 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 0 + 0 1 0 0 0 2 2 2 2 0 + 0 0 0 0 0 0 0 8 0 8 + 0 0 0 0 0 0 6 6 6 6 + 6 0 0>; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins = <37 38>; + marvell,function = <2>; + }; + + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins = <35 36>; + marvell,function = <2>; + }; + + cp0_nand_pins: cp0-nand-pins { + marvell,pins = <0 1 9 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31>; + marvell,function = <1>; + }; + + cp0_smi_pins: cp0-smi-pins { + marvell,pins = <47 49>; + marvell,function = <8>; + }; + + cp0_nand_rb: cp0-nand-rb { + marvell,pins = <13>; + marvell,function = <2>; + }; + + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins = <56 57 58 59 60>; + marvell,function = <6>; + }; +}; + +&cp0_i2c0 { + status = "okay"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&cp0_i2c0_pins>; + + mux@70 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9546"; + reg = <0x70>; + i2c-mux-idle-disconnect; + reset-gpios = <&ap_gpio0 2 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hwmon@2d { + compatible = "adi,adt7476"; + reg = <0x2d>; + adi,pwm-active-state = <0 0 0>; + }; + + hwmon@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; + + rtc:rtc@68 { + compatible = "adi,max31343"; + reg = <0x68>; + }; + }; + + /* Switch/EEPROM */ + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + /* PSU0 */ + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + eeprom@51 { + compatible = "i2c-eeprom"; + reg = <0x51>; + }; + }; + + /* PSU1 */ + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + eeprom@51 { + compatible = "i2c-eeprom"; + reg = <0x51>; + }; + }; + + }; +}; + +&cp0_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; +}; + +&cp0_comphy { + phy0 { + phy-type = <COMPHY_TYPE_PEX0>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_IGNORE>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_IGNORE>; + }; + + phy3 { + phy-type = <COMPHY_TYPE_IGNORE>; + }; + + phy4 { + phy-type = <COMPHY_TYPE_IGNORE>; + }; + + phy5 { + phy-type = <COMPHY_TYPE_SGMII0>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; +}; + +&cp0_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_smi_pins>; + status = "okay"; + cp0_phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth2 { + status = "okay"; + phy = <&cp0_phy0>; + phy-mode = "sgmii"; + phy-reset-gpios = <&cp0_gpio0 10 GPIO_ACTIVE_LOW>; +}; + +&cp0_pcie0 { + num-lanes = <1>; + /* non-prefetchable memory */ + ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>; + status = "disabled"; +}; + +&uart0 { + status = "okay"; +}; + +&cp0_utmi0 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_spi0_pins>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + +&cp0_nand { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-timing-mode = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@user { + reg = <0x00000000 0x20000000>; + label = "user"; + }; + }; +}; + +&cp0_gpio0 +{ + nand-protect { + gpio-hog; + gpios = <29 GPIO_ACTIVE_LOW>; + output-low; + line-name = "nand-protect"; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi index b6522069207..529adfcbaf4 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -25,28 +25,28 @@ status = "okay"; managed = "in-band-status"; phy-mode = "qsgmii"; - phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@8}>; }; &mscc_felix_port1 { status = "okay"; managed = "in-band-status"; phy-mode = "qsgmii"; - phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@9}>; }; &mscc_felix_port2 { status = "okay"; managed = "in-band-status"; phy-mode = "qsgmii"; - phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@a}>; }; &mscc_felix_port3 { status = "okay"; managed = "in-band-status"; phy-mode = "qsgmii"; - phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@b}>; }; &mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index ac5b2d9dde9..92757260560 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -147,7 +147,7 @@ mdio-parent-bus = <&enetc_mdio_pf3>; /* on-board MDIO with a single RGMII PHY */ - mdio@00 { + mdio@0 { #address-cells = <1>; #size-cells = <0>; reg = <0x00>; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi index 83635a2e40d..5bdc8675aa2 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi @@ -41,7 +41,7 @@ mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5 mdio-parent-bus = <&emdio1>; - mdio@00 { + mdio@0 { #address-cells = <1>; #size-cells = <0>; reg = <0x00>; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index 6fa36de0622..c213088bdf0 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -161,7 +161,7 @@ mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 mdio-parent-bus = <&emdio1>; - mdio@00 { + mdio@0 { #address-cells = <1>; #size-cells = <0>; reg = <0x00>; @@ -170,7 +170,7 @@ reg = <0x1>; }; }; - mdio@08 { + mdio@8 { #address-cells = <1>; #size-cells = <0>; reg = <0x40>; diff --git a/arch/arm/dts/fsl-sch-28021.dtsi b/arch/arm/dts/fsl-sch-28021.dtsi index 61245287b96..d819308ed8c 100644 --- a/arch/arm/dts/fsl-sch-28021.dtsi +++ b/arch/arm/dts/fsl-sch-28021.dtsi @@ -12,18 +12,18 @@ * PHY addresses are 0x08 - 0x0b. * On the card the first port is the top port (farthest from PEX connector). */ -phy@08 { +phy@8 { reg = <0x08>; }; -phy@09 { +phy@9 { reg = <0x09>; }; -phy@0a { +phy@a { reg = <0x0a>; }; -phy@0b { +phy@b { reg = <0x0b>; }; diff --git a/arch/arm/dts/imx6dl-mba6.dtsi b/arch/arm/dts/imx6dl-mba6.dtsi deleted file mode 100644 index b749b424bbd..00000000000 --- a/arch/arm/dts/imx6dl-mba6.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel <[email protected]> - */ - -ðphy { - rxdv-skew-ps = <180>; - txen-skew-ps = <0>; - rxd3-skew-ps = <180>; - rxd2-skew-ps = <180>; - rxd1-skew-ps = <180>; - rxd0-skew-ps = <180>; - txd3-skew-ps = <120>; - txd2-skew-ps = <0>; - txd1-skew-ps = <300>; - txd0-skew-ps = <120>; - txc-skew-ps = <1860>; - rxc-skew-ps = <1860>; -}; diff --git a/arch/arm/dts/imx6dl-mba6a-u-boot.dtsi b/arch/arm/dts/imx6dl-mba6a-u-boot.dtsi new file mode 100644 index 00000000000..d484a5dda00 --- /dev/null +++ b/arch/arm/dts/imx6dl-mba6a-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include "imx6qdl-mba6-u-boot.dtsi" diff --git a/arch/arm/dts/imx6dl-mba6a.dts b/arch/arm/dts/imx6dl-mba6a.dts deleted file mode 100644 index df0a96b28af..00000000000 --- a/arch/arm/dts/imx6dl-mba6a.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel <[email protected]> - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include "imx6dl-tqma6a.dtsi" -#include "imx6qdl-mba6.dtsi" -#include "imx6qdl-mba6a.dtsi" -#include "imx6dl-mba6.dtsi" - -/ { - model = "TQ TQMa6S/DL on MBa6x"; - compatible = "tq,imx6dl-mba6x-a", "tq,mba6a", - "tq,imx6dl-tqma6dl-a", "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-mba6b-u-boot.dtsi b/arch/arm/dts/imx6dl-mba6b-u-boot.dtsi index bb17ba9b424..d484a5dda00 100644 --- a/arch/arm/dts/imx6dl-mba6b-u-boot.dtsi +++ b/arch/arm/dts/imx6dl-mba6b-u-boot.dtsi @@ -1,3 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ #include "imx6qdl-mba6-u-boot.dtsi" diff --git a/arch/arm/dts/imx6q-mba6.dtsi b/arch/arm/dts/imx6q-mba6.dtsi deleted file mode 100644 index 0d7be456729..00000000000 --- a/arch/arm/dts/imx6q-mba6.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel <[email protected]> - */ - -&ecspi5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi5_mba6x>; - cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; -}; - -ðphy { - rxdv-skew-ps = <180>; - txen-skew-ps = <120>; - rxd3-skew-ps = <180>; - rxd2-skew-ps = <180>; - rxd1-skew-ps = <180>; - rxd0-skew-ps = <180>; - txd3-skew-ps = <120>; - txd2-skew-ps = <0>; - txd1-skew-ps = <180>; - txd0-skew-ps = <360>; - txc-skew-ps = <1860>; - rxc-skew-ps = <1860>; -}; - -&sata { - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi5_mba6x: ecspi5grp-mba6x { - fsl,pins = < - /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ - MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b099 - MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0xb099 - MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0xb099 - MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0xb099 /* eCSPI5 SS0 */ - >; - }; -}; diff --git a/arch/arm/dts/imx6q-mba6a-u-boot.dtsi b/arch/arm/dts/imx6q-mba6a-u-boot.dtsi new file mode 100644 index 00000000000..d484a5dda00 --- /dev/null +++ b/arch/arm/dts/imx6q-mba6a-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include "imx6qdl-mba6-u-boot.dtsi" diff --git a/arch/arm/dts/imx6q-mba6a.dts b/arch/arm/dts/imx6q-mba6a.dts deleted file mode 100644 index 349a08605a5..00000000000 --- a/arch/arm/dts/imx6q-mba6a.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel <[email protected]> - */ - -/dts-v1/; - -#include "imx6q-tqma6a.dtsi" -#include "imx6qdl-mba6.dtsi" -#include "imx6qdl-mba6a.dtsi" -#include "imx6q-mba6.dtsi" - -/ { - model = "TQ TQMa6Q on MBa6x"; - compatible = "tq,imx6q-mba6x-a", "tq,mba6a", - "tq,imx6q-tqma6q-a", "fsl,imx6q"; -}; diff --git a/arch/arm/dts/imx6q-mba6b-u-boot.dtsi b/arch/arm/dts/imx6q-mba6b-u-boot.dtsi index bb17ba9b424..d484a5dda00 100644 --- a/arch/arm/dts/imx6q-mba6b-u-boot.dtsi +++ b/arch/arm/dts/imx6q-mba6b-u-boot.dtsi @@ -1,3 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ #include "imx6qdl-mba6-u-boot.dtsi" diff --git a/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi index c8c0fc1fba7..22f67c6f966 100644 --- a/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi @@ -1,29 +1,38 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ -#include "imx6qdl-u-boot.dtsi" +#include "imx6qdl-tqma6-u-boot.dtsi" -/ { - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog1>; - bootph-pre-ram; - }; +&gpio1 { + bootph-pre-ram; }; -&aips2 { - bootph-all; +&i2c1 { + bootph-pre-ram; }; &pinctrl_uart2 { - bootph-all; + bootph-pre-ram; }; -&soc { - bootph-all; +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_wdog1{ + bootph-pre-ram; }; &uart2 { - bootph-all; + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; }; &wdog1 { diff --git a/arch/arm/dts/imx6qdl-mba6.dtsi b/arch/arm/dts/imx6qdl-mba6.dtsi deleted file mode 100644 index 78555a61885..00000000000 --- a/arch/arm/dts/imx6qdl-mba6.dtsi +++ /dev/null @@ -1,535 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel <[email protected]> - */ - -#include <dt-bindings/clock/imx6qdl-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/sound/fsl-imx-audmux.h> - -/ { - aliases { - mmc0 = &usdhc3; - mmc1 = &usdhc2; - /delete-property/ mmc2; - /delete-property/ mmc3; - rtc0 = &rtc0; - }; - - chosen { - stdout-path = &uart2; - }; - - beeper: gpio-beeper { - compatible = "gpio-beeper"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiobeeper>; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; - }; - - gpio_buttons: gpio-buttons { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiobuttons>; - - button1 { - label = "s6"; - linux,code = <KEY_F6>; - gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button2 { - label = "s7"; - linux,code = <KEY_F7>; - gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button3 { - label = "s8"; - linux,code = <KEY_F8>; - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpioled>; - - led1 { - label = "led1"; - gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - led2 { - label = "led2"; - gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - reg_mba6_3p3v: regulator-mba6-3p3v { - compatible = "regulator-fixed"; - regulator-name = "supply-mba6-3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_pcie: regulator-pcie { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regpcie>; - regulator-name = "supply-pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* PCIE.PWR_EN */ - gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_mba6_3p3v>; - }; - - reg_vcc3v3_audio: regulator-vcc3v3-audio { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3-audio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_mba6_3p3v>; - }; - - sound { - compatible = "fsl,imx-audio-tlv320aic32x4"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - model = "imx-audio-tlv320aic32x4"; - ssi-controller = <&ssi1>; - audio-codec = <&tlv320aic32x4>; - audio-asrc = <&asrc>; - audio-routing = - "IN3_L", "Mic Jack", - "Mic Jack", "Mic Bias", - "IN1_L", "Line In Jack", - "IN1_R", "Line In Jack", - "Line Out Jack", "LOL", - "Line Out Jack", "LOR"; - mux-int-port = <1>; - mux-ext-port = <3>; - }; -}; - -&audmux { - status = "okay"; - - ssi0 { - fsl,audmux-port = <MX31_AUDMUX_PORT1_SSI0>; - fsl,port-config = < - (IMX_AUDMUX_V2_PTCR_SYN | - IMX_AUDMUX_V2_PTCR_TFSDIR | - IMX_AUDMUX_V2_PTCR_TFSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) | - IMX_AUDMUX_V2_PTCR_TCLKDIR | - IMX_AUDMUX_V2_PTCR_TCSEL(MX31_AUDMUX_PORT3_SSI_PINS_3)) - IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT3_SSI_PINS_3) - >; - }; - - aud3 { - fsl,audmux-port = <MX31_AUDMUX_PORT3_SSI_PINS_3>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN - IMX_AUDMUX_V2_PDCR_RXDSEL(MX31_AUDMUX_PORT1_SSI0) - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_mba6>; - cs-gpios = <&gpio3 19 0>, <&gpio3 24 0>; -}; - -&fec { - phy-mode = "rgmii-id"; - phy-handle = <ðphy>; - mac-address = [00 00 00 00 00 00]; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - interrupt-parent = <&gpio1>; - interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <1000>; - reset-deassert-us = <100000>; - micrel,force-master; - max-speed = <1000>; - }; - }; -}; - -&i2c1 { - tlv320aic32x4: audio-codec@18 { - compatible = "ti,tlv320aic32x4"; - reg = <0x18>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_codec>; - ldoin-supply = <®_vcc3v3_audio>; - iov-supply = <®_mba6_3p3v>; - }; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = <&gpio6 7 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - uart-has-rtscts; - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - status = "okay"; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - power-active-high; - over-current-active-low; - srp-disable; - hnp-disable; - adp-disable; - dr_mode = "otg"; - status = "okay"; -}; - -/* SD card slot */ -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_mba6_3p3v>; - bus-width = <4>; - no-1-8-v; - no-mmc; - no-sdio; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; - /* does not work on unmodified starter kit */ - /* fsl,ext-reset-output; */ - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0xb099 - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0xb099 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0xb099 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0xb099 - >; - }; - - pinctrl_codec: codecgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0xb0 /* CLK */ - >; - }; - - pinctrl_ecspi1_mba6: ecspimba6grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__GPIO3_IO24 0xb099 /* eCSPI1 SS2 */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - /* FEC phy IRQ */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x00011008 - /* FEC phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b099 - /* DSE = 100, 100k up, SPEED = MED */ - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0xb0a0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0xb0a0 - /* DSE = 111, pull 100k up */ - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0xb038 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0xb038 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0xb038 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0xb038 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0xb038 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0xb038 - /* DSE = 111, pull external */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x0038 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x0038 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x0038 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x0038 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x0038 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x0038 - /* HYS = 1, DSE = 111, 100k up, SPEED = HIGH */ - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0f0 - >; - }; - - pinctrl_gpiobeeper: gpiobeepergrp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0xb099 - >; - }; - - pinctrl_gpiobuttons: gpiobuttongrp { - fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0001b099 - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b099 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b099 - >; - }; - - pinctrl_gpioled: gpioledgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0xb099 /* LED V15 */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb099 /* LED V16 */ - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 - - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 - - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b099 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0001b099 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0001b099 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0001b099 - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0001b099 - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0001b099 - MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x0001b099 - - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0001b099 - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0001b099 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0001b099 - MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0001b099 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0001b099 - - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b099 - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b099 - MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x0001b099 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x0001b099 - - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x0001b099 - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x0001b099 - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x0001b099 - - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b099 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x0001b099 - >; - }; - - pinctrl_pcie: pciegrp { - fsl,pins = < - /* HYS = 1, DSE = 110, 100k up, SPEED = HIGH (11)*/ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - /* 100 k PD, DSE 120 OHM, SPPEED LO */ - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x00003050 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - /* 100 k PD, DSE 120 OHM, SPPEED LO */ - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x00003050 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - /* 100 k PD, DSE 120 OHM, SPPEED LO */ - MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x00003050 - >; - }; - - pinctrl_regpcie: regpciegrp { - fsl,pins = < - /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1 - MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - /* CLK: 47k Pup SPD_LOW DSE 40Ohm SRE_FAST HYS */ - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00017071 - /* SD2: 47k Pup SPD_LOW DSE 80Ohm SRE_FAST HYS */ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 - - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0001b0b0 - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x00017059 - MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0001b099 - >; - }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - /* Watchdog out */ - MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-mba6a.dtsi b/arch/arm/dts/imx6qdl-mba6a.dtsi deleted file mode 100644 index df8fa169e9f..00000000000 --- a/arch/arm/dts/imx6qdl-mba6a.dtsi +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel <[email protected]> - */ - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; -}; - -&i2c1 { - lm75: temperature-sensor@49 { - compatible = "national,lm75"; - reg = <0x49>; - }; - - m24c64_57: eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - pagesize = <32>; - }; - - rtc0: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; diff --git a/arch/arm/dts/imx6qdl-mba6b.dtsi b/arch/arm/dts/imx6qdl-mba6b.dtsi deleted file mode 100644 index 7d1cd7454c7..00000000000 --- a/arch/arm/dts/imx6qdl-mba6b.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel <[email protected]> - */ - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_recovery>; - scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; -}; - -&i2c3 { - lm75: temperature-sensor@49 { - compatible = "national,lm75"; - reg = <0x49>; - }; - - m24c64_57: eeprom@57 { - compatible = "atmel,24c64"; - reg = <0x57>; - pagesize = <32>; - }; - - rtc0: rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&iomuxc { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-tqma6-u-boot.dtsi b/arch/arm/dts/imx6qdl-tqma6-u-boot.dtsi new file mode 100644 index 00000000000..b5269748058 --- /dev/null +++ b/arch/arm/dts/imx6qdl-tqma6-u-boot.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +/* SOC specific U-Boot DT adjustments */ + +#include "imx6qdl-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; +}; + +&aips1 { + bootph-pre-ram; +}; + +&aips2 { + bootph-pre-ram; +}; + +&ecspi1 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&m25p80 { + bootph-pre-ram; +}; + +&pinctrl_ecspi1 { + bootph-pre-ram; +}; + +&pinctrl_i2c1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&usdhc3 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx6qdl-tqma6a-u-boot.dtsi b/arch/arm/dts/imx6qdl-tqma6a-u-boot.dtsi new file mode 100644 index 00000000000..af72ac77a79 --- /dev/null +++ b/arch/arm/dts/imx6qdl-tqma6a-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +/* SOC specific U-Boot DT adjustments */ + +#include "imx6qdl-tqma6-u-boot.dtsi" + +&i2c1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx6qdl-tqma6b-u-boot.dtsi b/arch/arm/dts/imx6qdl-tqma6b-u-boot.dtsi new file mode 100644 index 00000000000..8ae7f2900f3 --- /dev/null +++ b/arch/arm/dts/imx6qdl-tqma6b-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +/* SOC specific U-Boot DT adjustments */ + +#include "imx6qdl-tqma6-u-boot.dtsi" + +&i2c3 { + bootph-pre-ram; +}; + +&pinctrl_i2c3 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx6ul-tqma6ul-common-u-boot.dtsi b/arch/arm/dts/imx6ul-tqma6ul-common-u-boot.dtsi index 09f94f23074..c9e6cef38a2 100644 --- a/arch/arm/dts/imx6ul-tqma6ul-common-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-tqma6ul-common-u-boot.dtsi @@ -14,6 +14,12 @@ u-boot,mmc-env-offset = <0x100000>; u-boot,mmc-env-offset-redundant = <0x110000>; }; + + sysinfo: sysinfo { + compatible = "tq,eeprom-sysinfo"; + nvmem-cells = <&module_info>; + nvmem-cell-names = "device_info"; + }; }; &clks { @@ -24,6 +30,18 @@ bootph-pre-ram; }; +&m24c64_50 { + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + module_info: module-info@20 { + reg = <0x20 0x60>; + }; + }; +}; + &osc { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi b/arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi index 26361780c01..452bf3d41f1 100644 --- a/arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-phygate-tauri-l-u-boot.dtsi @@ -6,6 +6,21 @@ #include "imx8mm-u-boot.dtsi" / { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * Limit memory usage below the 4 GB (32-bit) boundary. + * The i.MX8MM DMA and peripherals cannot access >32-bit + * addresses. This prevents allocation failures in UEFI mode. + */ + u_boot_sdma_shield: sdma-shield@100000000 { + reg = <0x1 0x00000000 0x0 0x40000000>; + }; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -29,6 +44,10 @@ }; }; +&pinctrl_i2c1 { + bootph-pre-ram; +}; + &pinctrl_uart3 { bootph-pre-ram; }; @@ -73,6 +92,10 @@ bootph-pre-ram; }; +&i2c1 { + bootph-pre-ram; +}; + &usdhc2 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 50ecb6cad39..d5a5681c23f 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -62,7 +62,6 @@ filename = "u-boot-spl-mkimage.bin"; #ifdef CONFIG_FSPI_CONF_HEADER nxp,boot-from = "fspi"; - nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE; #else nxp,boot-from = "sd"; #endif @@ -165,6 +164,7 @@ }; #endif +#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -179,6 +179,7 @@ optional; }; }; +#endif binman_fip: fip { arch = "arm64"; @@ -208,7 +209,11 @@ fdt = "fdt-SEQ"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI +#ifdef CONFIG_OPTEE loadables = "atf", "tee"; +#else + loadables = "atf"; +#endif #endif }; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 690f56e65bb..9a5afa7c807 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -116,7 +116,6 @@ filename = "u-boot-spl-mkimage.bin"; #ifdef CONFIG_FSPI_CONF_HEADER nxp,boot-from = "fspi"; - nxp,fspi-header-filename = CONFIG_FSPI_CONF_FILE; #else nxp,boot-from = "sd"; #endif @@ -241,6 +240,7 @@ }; #endif +#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -255,6 +255,7 @@ optional; }; }; +#endif binman_fip: fip { arch = "arm64"; @@ -284,7 +285,11 @@ fdt = "fdt-SEQ"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI +#ifdef CONFIG_OPTEE loadables = "atf", "tee"; +#else + loadables = "atf"; +#endif #endif }; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index d9d220c70db..58b6863f003 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -189,6 +189,7 @@ }; #endif +#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -203,6 +204,7 @@ optional; }; }; +#endif @fdt-SEQ { description = "NAME"; @@ -223,7 +225,11 @@ fdt = "fdt-SEQ"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI +#ifdef CONFIG_OPTEE loadables = "atf", "tee"; +#else + loadables = "atf"; +#endif #endif }; }; diff --git a/arch/arm/dts/imx8mq-librem5-devkit-u-boot.dtsi b/arch/arm/dts/imx8mq-librem5-devkit-u-boot.dtsi new file mode 100644 index 00000000000..46a4dfe4e8a --- /dev/null +++ b/arch/arm/dts/imx8mq-librem5-devkit-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "imx8mq-u-boot.dtsi" + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&uart1 { /* console */ + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index b4deaa92160..c6947401750 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -173,6 +173,7 @@ }; #endif +#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -187,6 +188,7 @@ optional; }; }; +#endif fdt { compression = "none"; @@ -208,7 +210,11 @@ fdt = "fdt"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI +#ifdef CONFIG_OPTEE loadables = "atf", "tee"; +#else + loadables = "atf"; +#endif #endif }; }; diff --git a/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi b/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi index 41111b1a95a..2ce9f46b2ad 100644 --- a/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi @@ -12,6 +12,13 @@ bootph-pre-ram; bootph-some-ram; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; &A55_0 { diff --git a/arch/arm/dts/imx943-evk-u-boot.dtsi b/arch/arm/dts/imx943-evk-u-boot.dtsi index 3b3619d2232..3c395610c5f 100644 --- a/arch/arm/dts/imx943-evk-u-boot.dtsi +++ b/arch/arm/dts/imx943-evk-u-boot.dtsi @@ -126,19 +126,6 @@ status = "okay"; }; -&usb3_dwc3 { - bootph-pre-ram; - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - role-switch-default-mode = "peripheral"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - status = "okay"; -}; - &usb3_phy { bootph-pre-ram; orientation-switch; @@ -272,3 +259,31 @@ &pinctrl_usdhc2_gpio { bootph-pre-ram; }; + +&pcal6416_i2c3_u46 { + label = "u46"; +}; + +&pcal6416_i2c3_u171 { + label = "u171"; +}; + +&pcal6416_i2c3_u48 { + label = "u48"; +}; + +&pcal6408_i2c3_u172 { + label = "u172"; +}; + +&pcal6416_i2c6_u50 { + label = "u50"; +}; + +&pcal6408_i2c6_u170 { + label = "u170"; +}; + +&pcal6416_i2c6_u44 { + label = "u44"; +}; diff --git a/arch/arm/dts/imx943-u-boot.dtsi b/arch/arm/dts/imx943-u-boot.dtsi index 74481aeefb5..8bd63d2e213 100644 --- a/arch/arm/dts/imx943-u-boot.dtsi +++ b/arch/arm/dts/imx943-u-boot.dtsi @@ -249,35 +249,6 @@ &{/soc} { bootph-all; - usb3: usb@4c010010 { - compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; - reg = <0x0 0x4c010010 0x0 0x04>, - <0x0 0x4c1f0000 0x0 0x20>; - ranges; - interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - clocks = <&scmi_clk IMX94_CLK_HSIO>, - <&scmi_clk IMX94_CLK_32K>; - clock-names = "hsio", "suspend"; - power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; - status = "disabled"; - - usb3_dwc3: usb@4c100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x4c100000 0x0 0x10000>; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&scmi_clk IMX94_CLK_HSIO>, - <&scmi_clk IMX94_CLK_24M>, - <&scmi_clk IMX94_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - phys = <&usb3_phy>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,gfladj-refclk-lpm-sel-quirk; - snps,parkmode-disable-ss-quirk; - }; - }; - usb3_phy: phy@4c1f0040 { compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; reg = <0x0 0x4c1f0040 0x0 0x40>, diff --git a/arch/arm/dts/imx95-15x15-frdm-u-boot.dtsi b/arch/arm/dts/imx95-15x15-frdm-u-boot.dtsi new file mode 100644 index 00000000000..aa289bd65aa --- /dev/null +++ b/arch/arm/dts/imx95-15x15-frdm-u-boot.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include "imx95-u-boot.dtsi" + +/ { + aliases { + pci0 = &netc_bus0; + pci1 = &netc_bus1; + }; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-imem} { + filename = "lpddr4x_imem_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-dmem} { + filename = "lpddr4x_dmem_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-imem-qb} { + filename = "lpddr4x_imem_qb_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-dmem-qb} { + filename = "lpddr4x_dmem_qb_v202409.bin"; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi index 36640f31d61..56677cd6f6d 100644 --- a/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi +++ b/arch/arm/dts/ipq5424-rdp466-u-boot.dtsi @@ -24,7 +24,7 @@ mmc-hs200-1_8v; max-frequency = <192000000>; bus-width = <4>; - pinctrl-0 = <&sdc_default_state>; + pinctrl-0 = <&qpic_snand_default_state>; pinctrl-names = "default"; non-removable; diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index 2a4f0e45365..cd13b5c3cd1 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -319,6 +319,34 @@ bootph-all; }; +&buck1_reg { + bootph-all; +}; + +&buck2_reg { + bootph-all; +}; + +&buck3_reg { + bootph-all; +}; + +&ldo1_reg { + bootph-all; +}; + +&ldo2_reg { + bootph-all; +}; + +&ldo3_reg { + bootph-all; +}; + +&ldo4_reg { + bootph-all; +}; + &cpsw_port2 { status = "disabled"; }; diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts index 4570ff6edbf..6ea640856b4 100644 --- a/arch/arm/dts/k3-am62a7-r5-sk.dts +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -42,3 +42,7 @@ status = "okay"; bootph-pre-ram; }; + +&main_pktdma { + ti,sci = <&dm_tifs>; +}; diff --git a/arch/arm/dts/k3-am68-phyboard-izar-u-boot.dtsi b/arch/arm/dts/k3-am68-phyboard-izar-u-boot.dtsi index cd40506d3ac..503ed69d123 100644 --- a/arch/arm/dts/k3-am68-phyboard-izar-u-boot.dtsi +++ b/arch/arm/dts/k3-am68-phyboard-izar-u-boot.dtsi @@ -8,14 +8,27 @@ #include "k3-am68-phycore-som-binman.dtsi" +&wkup_pmx2 { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ + >; + }; +}; + &cbass_main { bootph-all; }; -&watchdog1 { - status = "disabled"; +&mcu_i2c0 { + status = "okay"; }; &mcu_uart0 { bootph-all; }; + +&watchdog1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/mt7623-u-boot.dtsi b/arch/arm/dts/mt7623-u-boot.dtsi index b9fd49900ce..06414180f29 100644 --- a/arch/arm/dts/mt7623-u-boot.dtsi +++ b/arch/arm/dts/mt7623-u-boot.dtsi @@ -8,10 +8,6 @@ bootph-all; }; -&topckgen { - bootph-all; -}; - &pericfg { bootph-all; }; diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi index 5b4cadc22f7..675b14a0b7e 100644 --- a/arch/arm/dts/mt7981.dtsi +++ b/arch/arm/dts/mt7981.dtsi @@ -94,7 +94,6 @@ topckgen: topckgen@1001b000 { compatible = "mediatek,mt7981-topckgen"; reg = <0x1001b000 0x1000>; - clock-parent = <&fixed_plls>; #clock-cells = <1>; bootph-all; }; @@ -102,7 +101,6 @@ infracfg: infracfg@10001000 { compatible = "mediatek,mt7981-infracfg"; reg = <0x10001000 0x30>; - clock-parent = <&topckgen>; #clock-cells = <1>; bootph-all; }; @@ -221,7 +219,6 @@ ethsys: syscon@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0x15000000 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi index b2c57098a5e..5b62d8917ac 100644 --- a/arch/arm/dts/mt7986.dtsi +++ b/arch/arm/dts/mt7986.dtsi @@ -111,14 +111,12 @@ topckgen: topckgen@1001B000 { compatible = "mediatek,mt7986-topckgen"; reg = <0x1001B000 0x1000>; - clock-parent = <&fixed_plls>; #clock-cells = <1>; }; infracfg: infracfg@10001040 { compatible = "mediatek,mt7986-infracfg"; reg = <0x10001000 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; @@ -217,7 +215,6 @@ ethsys: syscon@15000000 { compatible = "mediatek,mt7986-ethsys", "syscon"; reg = <0x15000000 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi index 2d57c6f5709..0f7a85230d4 100644 --- a/arch/arm/dts/mt7988.dtsi +++ b/arch/arm/dts/mt7988.dtsi @@ -106,7 +106,6 @@ topckgen: topckgen@1001b000 { compatible = "mediatek,mt7988-topckgen", "syscon"; reg = <0 0x1001b000 0 0x1000>; - clock-parent = <&apmixedsys>; #clock-cells = <1>; }; @@ -129,28 +128,24 @@ sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7988-sgmiisys_0", "syscon"; reg = <0 0x10060000 0 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; sgmiisys1: syscon@10070000 { compatible = "mediatek,mt7988-sgmiisys_1", "syscon"; reg = <0 0x10070000 0 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; usxgmiisys0: syscon@10080000 { compatible = "mediatek,mt7988-usxgmiisys_0", "syscon"; reg = <0 0x10080000 0 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; usxgmiisys1: syscon@10081000 { compatible = "mediatek,mt7988-usxgmiisys_1", "syscon"; reg = <0 0x10081000 0 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; @@ -378,21 +373,18 @@ xfi_pextp0: syscon@11f20000 { compatible = "mediatek,mt7988-xfi_pextp_0", "syscon"; reg = <0 0x11f20000 0 0x10000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; xfi_pextp1: syscon@11f30000 { compatible = "mediatek,mt7988-xfi_pextp_1", "syscon"; reg = <0 0x11f30000 0 0x10000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; xfi_pll: syscon@11f40000 { compatible = "mediatek,mt7988-xfi_pll", "syscon"; reg = <0 0x11f40000 0 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; @@ -400,14 +392,12 @@ compatible = "mediatek,mt7988-topmisc", "syscon", "mediatek,mt7988-power-controller"; reg = <0 0x11d10000 0 0x10000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; infracfg: infracfg@10001000 { compatible = "mediatek,mt7988-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; }; @@ -572,7 +562,6 @@ ethdma: syscon@15000000 { compatible = "mediatek,mt7988-ethdma", "syscon"; reg = <0 0x15000000 0 0x20000>; - clock-parent = <&topckgen>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -580,7 +569,6 @@ ethwarp: syscon@15031000 { compatible = "mediatek,mt7988-ethwarp", "syscon"; reg = <0 0x15031000 0 0x1000>; - clock-parent = <&topckgen>; #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/arch/arm/dts/mt8183-pumpkin.dts b/arch/arm/dts/mt8183-pumpkin.dts index 470a7693997..623561b6a63 100644 --- a/arch/arm/dts/mt8183-pumpkin.dts +++ b/arch/arm/dts/mt8183-pumpkin.dts @@ -88,10 +88,6 @@ }; &usb { - status = "okay"; -}; - -&ssusb { mediatek,force-vbus; maximum-speed = "high-speed"; dr_mode = "peripheral"; diff --git a/arch/arm/dts/mt8183.dtsi b/arch/arm/dts/mt8183.dtsi index 294aa2b8979..323a88a7ac9 100644 --- a/arch/arm/dts/mt8183.dtsi +++ b/arch/arm/dts/mt8183.dtsi @@ -236,9 +236,9 @@ }; }; - usb: usb@11200000 { + usb: usb@11201000 { compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; - reg = <0 0x11200000 0 0x3e00>, + reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; @@ -251,16 +251,9 @@ ranges; status = "disabled"; - ssusb: ssusb@11200000 { - compatible = "mediatek,ssusb"; - reg = <0 0x11200000 0 0x3e00>; - reg-names = "mac"; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; - status = "disabled"; - }; - - usb_host: xhci@11200000 { - compatible = "mediatek,mtk-xhci"; + usb_host: usb@11200000 { + compatible = "mediatek,mt8183-xhci", + "mediatek,mtk-xhci"; reg = <0 0x11200000 0 0x1000>; reg-names = "mac"; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi b/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi new file mode 100644 index 00000000000..586d15bf72e --- /dev/null +++ b/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan <[email protected]> + */ + +#include "mt8188-u-boot.dtsi" diff --git a/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi b/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi new file mode 100644 index 00000000000..586d15bf72e --- /dev/null +++ b/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan <[email protected]> + */ + +#include "mt8188-u-boot.dtsi" diff --git a/arch/arm/dts/mt8512-bm1-emmc.dts b/arch/arm/dts/mt8512-bm1-emmc.dts index 12511b5fed4..13d3f804cb4 100644 --- a/arch/arm/dts/mt8512-bm1-emmc.dts +++ b/arch/arm/dts/mt8512-bm1-emmc.dts @@ -114,13 +114,9 @@ }; }; -&ssusb { +&usb3 { dr_mode = "peripheral"; maximum-speed = "high-speed"; - status = "okay"; -}; - -&usb3 { vbus-supply = <&usb_p0_vbus>; status = "okay"; }; diff --git a/arch/arm/dts/mt8512.dtsi b/arch/arm/dts/mt8512.dtsi index bdb84f8ef00..eb0a09826f9 100644 --- a/arch/arm/dts/mt8512.dtsi +++ b/arch/arm/dts/mt8512.dtsi @@ -101,27 +101,18 @@ status = "disabled"; }; - usb3: usb@11213e00 { + usb3: usb@11211000 { compatible = "mediatek,mt8512-mtu3", "mediatek,mtu3"; - reg = <0x11213e00 0x0100>; - reg-names = "ippc"; + reg = <0x11211000 0x2e00>, + <0x11213e00 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; phys = <&u2port0 PHY_TYPE_USB2>, <&u2port1 PHY_TYPE_USB2>; clocks = <&infracfg CLK_INFRA_USB_SYS>, <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, <&infracfg CLK_INFRA_ICUSB>; clock-names = "sys_ck", "ref_ck", "mcu_ck"; - #address-cells = <1>; - #size-cells = <1>; - ranges; status = "disabled"; - - ssusb: usb@11210000 { - compatible = "mediatek,ssusb"; - reg = <0x11210000 0x3e00>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; - reg-names = "mac"; - status = "disabled"; - }; }; u3phy: usb-phy@11cc0000 { diff --git a/arch/arm/dts/r8a77951-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index e8a7fa27a76..0c00cc8bef9 100644 --- a/arch/arm/dts/r8a77951-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -11,6 +11,8 @@ /delete-node/ &can0; /delete-node/ &can1; /delete-node/ &canfd; +/delete-node/ &cluster0_opp; +/delete-node/ &cluster1_opp; /delete-node/ &csi20; /delete-node/ &csi40; /delete-node/ &csi41; @@ -62,6 +64,38 @@ /delete-node/ vga; }; +&a53_0 { + /delete-property/ operating-points-v2; +}; + +&a53_1 { + /delete-property/ operating-points-v2; +}; + +&a53_2 { + /delete-property/ operating-points-v2; +}; + +&a53_3 { + /delete-property/ operating-points-v2; +}; + +&a57_0 { + /delete-property/ operating-points-v2; +}; + +&a57_1 { + /delete-property/ operating-points-v2; +}; + +&a57_2 { + /delete-property/ operating-points-v2; +}; + +&a57_3 { + /delete-property/ operating-points-v2; +}; + &i2c4 { /delete-node/ video-receiver@70; }; diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index b437792a172..2a8c5a96390 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -11,6 +11,8 @@ /delete-node/ &can0; /delete-node/ &can1; /delete-node/ &canfd; +/delete-node/ &cluster0_opp; +/delete-node/ &cluster1_opp; /delete-node/ &csi20; /delete-node/ &csi40; /delete-node/ &drif00; @@ -70,3 +72,27 @@ /delete-node/ imr-lx4@fe890000; }; }; + +&a53_0 { + /delete-property/ operating-points-v2; +}; + +&a53_1 { + /delete-property/ operating-points-v2; +}; + +&a53_2 { + /delete-property/ operating-points-v2; +}; + +&a53_3 { + /delete-property/ operating-points-v2; +}; + +&a57_0 { + /delete-property/ operating-points-v2; +}; + +&a57_1 { + /delete-property/ operating-points-v2; +}; diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index 57382e34912..6eb7bbeed26 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -11,6 +11,7 @@ /delete-node/ &can0; /delete-node/ &can1; /delete-node/ &canfd; +/delete-node/ &cluster0_opp; /delete-node/ &csi20; /delete-node/ &csi40; /delete-node/ &du; @@ -60,3 +61,11 @@ /delete-node/ imr-lx4@fe890000; }; }; + +&a57_0 { + /delete-property/ operating-points-v2; +}; + +&a57_1 { + /delete-property/ operating-points-v2; +}; diff --git a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi index 968cf6684c5..c9f302799f1 100644 --- a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi @@ -7,13 +7,6 @@ #include "r8a779g0-u-boot.dtsi" -&avb0_pins { - pins-vddq18-25-avb { - pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0"; - power-source = <1800>; - }; -}; - /* Page 31 / FAN */ &gpio1 { pwm-fan-hog { @@ -49,36 +42,9 @@ status = "okay"; }; -&pcie0_clkref { - clock-frequency = <100000000>; - status = "okay"; -}; - -&pciec0 { - clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; -}; - -&pcie1_clkref { - clock-frequency = <100000000>; - status = "okay"; -}; - -&pciec1 { - clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; -}; - &rpc { flash@0 { - /* - * EVTA1 is populated with Spansion S25FS512S - * EVTB1 is populated with Winbond W77Q51NW - */ - compatible = "jedec,spi-nor"; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; }; - -&vcc_sdhi { - states = <1800000 0>, <3300000 1>; -}; diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi index 356f633135d..5a76d9740a0 100644 --- a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi @@ -70,9 +70,27 @@ reg = <0 0xb8940000 0 0xf000>; }; + spi@c08c0000 { + compatible = "renesas,r8a78000-rpc-if", + "renesas,rcar-gen5-rpc-if"; + reg = <0 0xc08c0000 0 0x200>, + <0 0x34000000 0 0x04000000>, + <0 0xc08c8000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + clocks = <&dummy_clk_rclk>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + }; + }; + scp@c1340000 { compatible = "renesas,r8a78000-rproc"; reg = <0 0xc1340000 0 0x80000>; + resets = <&mdlc_scp SCP_RESET_DOMAIN_ID_SCP>; }; ram@e9800000 { /* DBSC5 */ diff --git a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi index 299716f96a4..2dc8ad7aa6b 100644 --- a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi @@ -15,6 +15,13 @@ mmc0 = &mmc0; }; + /delete-node/ memory@60600000; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x80000000>; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -32,6 +39,77 @@ regulator-boot-on; regulator-always-on; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* First 518 MiB is reserved for other purposes. */ + firmware@40000000 { + reg = <0x0 0x40000000 0x0 0x20600000>; + no-map; + }; + + /* Parameters set by IPL. */ + parameters@8c100000 { + reg = <0x0 0x8c100000 0x0 0x00008000>; + no-map; + }; + + /* TFA BL31. */ + tfa-bl31@8c200000 { + reg = <0x0 0x8c200000 0x0 0x00080000>; + no-map; + }; + + /* TEE TZ DRAM. */ + tee@8c400000 { + reg = <0x0 0x8c400000 0x0 0x02000000>; + no-map; + }; + + /* DRAM controller inline ECC areas */ + ecc@10cccc0000 { + reg = <0x10 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@12cccc0000 { + reg = <0x12 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@14cccc0000 { + reg = <0x14 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@16cccc0000 { + reg = <0x16 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@18cccc0000 { + reg = <0x18 0xcccc0000 0x0 0x33340000>; + no-map; + }; + + ecc@1a66660000 { + reg = <0x1a 0x66660000 0x0 0x999a0000>; + no-map; + }; + + ecc@1c66660000 { + reg = <0x1c 0x66660000 0x0 0x999a0000>; + no-map; + }; + + ecc@1e66660000 { + reg = <0x1e 0x66660000 0x0 0x999a0000>; + no-map; + }; + }; }; &cpg { diff --git a/arch/arm/dts/r8a78000-u-boot.dtsi b/arch/arm/dts/r8a78000-u-boot.dtsi index df21a9e03a2..67da58f6474 100644 --- a/arch/arm/dts/r8a78000-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-u-boot.dtsi @@ -170,6 +170,14 @@ bootph-all; }; + mdlc_scp: system-controller@c1330000 { + compatible = "renesas,r8a78000-mdlc"; + reg = <0 0xc1330000 0 0x1000>; + #power-domain-cells = <1>; + #reset-cells = <1>; + bootph-all; + }; + i2c0: i2c@c11d0000 { compatible = "renesas,i2c-r8a78000", "renesas,rcar-gen5-i2c"; diff --git a/arch/arm/dts/rk3368-sheep.dts b/arch/arm/dts/rk3368-sheep.dts index 120dec1a3de..723f78b46d5 100644 --- a/arch/arm/dts/rk3368-sheep.dts +++ b/arch/arm/dts/rk3368-sheep.dts @@ -250,7 +250,7 @@ pmic { pmic_sleep: pmic-sleep { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 0 2 &pcfg_pull_none>; }; pmic_int: pmic-int { diff --git a/arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi b/arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi new file mode 100644 index 00000000000..7944610827f --- /dev/null +++ b/arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3568-u-boot.dtsi" + +&gpio0 { + bootph-pre-ram; +}; + +&i2c0 { + bootph-pre-ram; +}; + +&i2c0_xfer { + bootph-pre-ram; +}; + +&i2s1m0_mclk { + bootph-pre-ram; +}; + +&pmic_int_l { + bootph-pre-ram; +}; + +&rk817 { + regulators { + bootph-pre-ram; + }; +}; + +&sdmmc_pwren_l { + bootph-pre-ram; +}; + +&vcc3v3_sd { + bootph-pre-ram; +}; + +&vccio_sd { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi index 64c43374c04..7e24be1a5e7 100644 --- a/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi @@ -12,14 +12,6 @@ /delete-property/ vpcie3v3-supply; }; -&sdhci { - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -}; - &vcc5v0_usb_host { /delete-property/ regulator-always-on; /delete-property/ regulator-boot-on; diff --git a/arch/arm/dts/sc598-som-ezkit-sd.dts b/arch/arm/dts/sc598-som-ezkit-sd.dts new file mode 100644 index 00000000000..9b5f60192d5 --- /dev/null +++ b/arch/arm/dts/sc598-som-ezkit-sd.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2026 - Analog Devices, Inc. + */ + +/dts-v1/; + +#include "sc598-som-ezkit.dtsi" + +&som_gpio_expander { + som-emmc { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-low; + line-name = "som-emmc-en"; + bootph-pre-ram; + }; + + crr-sdcard { + gpio-hog; + gpios = <9 GPIO_ACTIVE_LOW>; + output-high; + line-name = "crr-sdcard-en"; + bootph-pre-ram; + }; +}; + +&mmc0 { + max-frequency = <44000000>; + bus-width = <4>; + no-1-8-v; +}; diff --git a/arch/arm/dts/sc598-som-ezkit.dts b/arch/arm/dts/sc598-som-ezkit.dts index 493d2010e32..40350cff105 100644 --- a/arch/arm/dts/sc598-som-ezkit.dts +++ b/arch/arm/dts/sc598-som-ezkit.dts @@ -1,179 +1,26 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * (C) Copyright 2024 - Analog Devices, Inc. + * (C) Copyright 2026 - Analog Devices, Inc. */ /dts-v1/; -#include "sc598-som-revE.dtsi" +#include "sc598-som-ezkit.dtsi" -/ { - model = "ADI SC598-SOM-EZKIT"; - compatible = "adi,sc598-som-ezkit", "adi,sc59x-64"; -}; - -&i2c2 { - crr_gpio_expander: mcp23017@22 { - compatible = "microchip,mcp23017"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; +&som_gpio_expander { + som-emmc { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-high; + line-name = "som-emmc-en"; bootph-pre-ram; - - eeprom { - gpio-hog; - gpios = <0 GPIO_ACTIVE_LOW>; - output-high; - line-name = "eeprom-en"; - bootph-pre-ram; - }; - - pushbutton { - gpio-hog; - gpios = <1 GPIO_ACTIVE_LOW>; - output-high; - line-name = "pushbutton-en"; - bootph-pre-ram; - }; - - microsd { - gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; - output-low; - line-name = "microsd-spi"; - bootph-pre-ram; - }; - - ftdi { - gpio-hog; - gpios = <3 GPIO_ACTIVE_LOW>; - output-high; - line-name = "ftdi-usb-en"; - bootph-pre-ram; - }; - - can { - gpio-hog; - gpios = <4 GPIO_ACTIVE_LOW>; - output-low; - line-name = "can-en"; - bootph-pre-ram; - }; - - adau1962 { - gpio-hog; - gpios = <6 GPIO_ACTIVE_LOW>; - output-high; - line-name = "adau1962-en"; - bootph-pre-ram; - }; - - adau1979 { - gpio-hog; - gpios = <7 GPIO_ACTIVE_LOW>; - output-high; - line-name = "adau1979-en"; - bootph-pre-ram; - }; - - octal { - gpio-hog; - gpios = <8 GPIO_ACTIVE_LOW>; - output-high; - line-name = "octal-spi-cs-en"; - bootph-pre-ram; - }; - - spdif-dig { - gpio-hog; - gpios = <9 GPIO_ACTIVE_LOW>; - output-low; - line-name = "spdif-digital-en"; - bootph-pre-ram; - }; - - spdif-opt { - gpio-hog; - gpios = <10 GPIO_ACTIVE_LOW>; - output-low; - line-name = "spdif-optical-en"; - bootph-pre-ram; - }; - - audio-jack { - gpio-hog; - gpios = <11 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "audio-jack-sel"; - bootph-pre-ram; - }; - - mlb { - gpio-hog; - gpios = <12 GPIO_ACTIVE_LOW>; - output-low; - line-name = "mlb-en"; - bootph-pre-ram; - }; - - eth1 { - gpio-hog; - gpios = <13 GPIO_ACTIVE_LOW>; - output-high; - line-name = "eth1-en"; - bootph-pre-ram; - }; - - eth1-reset { - gpio-hog; - gpios = <14 GPIO_ACTIVE_LOW>; - /* - * USB0 lines are shared with Eth1 so Eth PHY must be held in reset - * when using the USB - */ - output-high; - line-name = "eth1-reset"; - bootph-pre-ram; - }; - - gige-reset { - gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; - output-high; - line-name = "gige-reset"; - bootph-pre-ram; - }; }; -}; -&ospi { - status = "okay"; - - clocks = <&clk ADSP_SC598_CLK_OSPI_REFCLK>; - - flash0: mx66lm1g45@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor", "mx66lm1g45"; - reg = <0>; - - /* - * This is board dependent to some extent. We've been able to - *set it higher on some boards - */ - spi-max-frequency = <66666666>; - cdns,spi-calib-frequency = <10000000>; - - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - - tshsl-ns = <50>; - tsd2d-ns = <50>; - tchsh-ns = <4>; - tslch-ns = <4>; + crr-sdcard { + gpio-hog; + gpios = <9 GPIO_ACTIVE_LOW>; + output-low; + line-name = "crr-sdcard-en"; bootph-pre-ram; - - cdns,dqs; - cdns,phy; }; }; diff --git a/arch/arm/dts/sc598-som-ezkit.dtsi b/arch/arm/dts/sc598-som-ezkit.dtsi new file mode 100644 index 00000000000..54ba866db4b --- /dev/null +++ b/arch/arm/dts/sc598-som-ezkit.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * (C) Copyright 2024 - Analog Devices, Inc. + */ + +/dts-v1/; + +#include "sc598-som-revE.dtsi" + +/ { + model = "ADI SC598-SOM-EZKIT"; + compatible = "adi,sc598-som-ezkit", "adi,sc59x-64"; +}; + +&i2c2 { + crr_gpio_expander: mcp23017@22 { + compatible = "microchip,mcp23017"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + bootph-pre-ram; + + eeprom { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "eeprom-en"; + bootph-pre-ram; + }; + + pushbutton { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-high; + line-name = "pushbutton-en"; + bootph-pre-ram; + }; + + microsd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + output-low; + line-name = "microsd-spi"; + bootph-pre-ram; + }; + + ftdi { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-high; + line-name = "ftdi-usb-en"; + bootph-pre-ram; + }; + + can { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "can-en"; + bootph-pre-ram; + }; + + adau1962 { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-high; + line-name = "adau1962-en"; + bootph-pre-ram; + }; + + adau1979 { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-high; + line-name = "adau1979-en"; + bootph-pre-ram; + }; + + octal { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-low; + line-name = "octal-spi-cs-en"; + bootph-pre-ram; + }; + + spdif-dig { + gpio-hog; + gpios = <9 GPIO_ACTIVE_LOW>; + output-low; + line-name = "spdif-digital-en"; + bootph-pre-ram; + }; + + spdif-opt { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-low; + line-name = "spdif-optical-en"; + bootph-pre-ram; + }; + + audio-jack { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "audio-jack-sel"; + bootph-pre-ram; + }; + + mlb { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "~mlb-en"; + bootph-pre-ram; + }; + + eth1 { + gpio-hog; + gpios = <13 GPIO_ACTIVE_LOW>; + output-high; + line-name = "eth1-en"; + bootph-pre-ram; + }; + + eth1-reset { + gpio-hog; + gpios = <14 GPIO_ACTIVE_LOW>; + /* + * USB0 lines are shared with Eth1 so Eth PHY must be held in reset + * when using the USB + */ + output-high; + line-name = "eth1-reset"; + bootph-pre-ram; + }; + + gige-reset { + gpio-hog; + gpios = <15 GPIO_ACTIVE_LOW>; + output-high; + line-name = "gige-reset"; + bootph-pre-ram; + }; + }; +}; + +&ospi { + status = "okay"; + + clocks = <&clk ADSP_SC598_CLK_OSPI_REFCLK>; + + flash0: mx66lm1g45@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor", "mx66lm1g45"; + reg = <0>; + + /* + * This is board dependent to some extent. We've been able to + *set it higher on some boards + */ + spi-max-frequency = <66666666>; + cdns,spi-calib-frequency = <10000000>; + + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + bootph-pre-ram; + + cdns,dqs; + cdns,phy; + }; +}; diff --git a/arch/arm/dts/sc598-som-ezlite.dts b/arch/arm/dts/sc598-som-ezlite.dts index 40cabd1db0d..3424a967caa 100644 --- a/arch/arm/dts/sc598-som-ezlite.dts +++ b/arch/arm/dts/sc598-som-ezlite.dts @@ -12,6 +12,24 @@ compatible = "adi,sc598-som-ezlite", "adi,sc59x-64"; }; +&som_gpio_expander { + som-emmc { + gpio-hog; + gpios = <8 GPIO_ACTIVE_LOW>; + output-high; + line-name = "som-emmc-en"; + bootph-pre-ram; + }; + + crr-sdcard { + gpio-hog; + gpios = <9 GPIO_ACTIVE_LOW>; + output-low; + line-name = "crr-sdcard-en"; + bootph-pre-ram; + }; +}; + &i2c2 { crr_gpio_expander: adp5588@30 { compatible = "adi,adp5588"; diff --git a/arch/arm/dts/sc598-som-revD.dtsi b/arch/arm/dts/sc598-som-revD.dtsi index 06d550b8532..0eaadc25c90 100644 --- a/arch/arm/dts/sc598-som-revD.dtsi +++ b/arch/arm/dts/sc598-som-revD.dtsi @@ -73,22 +73,6 @@ line-name = "uart0-flow-en"; bootph-pre-ram; }; - - som-emmc { - gpio-hog; - gpios = <8 GPIO_ACTIVE_LOW>; - output-high; - line-name = "som-emmc-en"; - bootph-pre-ram; - }; - - crr-sdcard { - gpio-hog; - gpios = <9 GPIO_ACTIVE_LOW>; - output-low; - line-name = "crr-sdcard-en"; - bootph-pre-ram; - }; }; }; diff --git a/arch/arm/dts/sc598-som-revE.dtsi b/arch/arm/dts/sc598-som-revE.dtsi index 1f48d52109b..212e8334fd9 100644 --- a/arch/arm/dts/sc598-som-revE.dtsi +++ b/arch/arm/dts/sc598-som-revE.dtsi @@ -47,20 +47,6 @@ line-name = "som-flash-cs-en"; }; - som-emmc { - gpio-hog; - gpios = <8 GPIO_ACTIVE_LOW>; - output-high; - line-name = "som-emmc-en"; - }; - - crr-sdcard { - gpio-hog; - gpios = <9 GPIO_ACTIVE_LOW>; - output-low; - line-name = "crr-sdcard-en"; - }; - led-ds3 { gpio-hog; gpios = <15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index fbf2e6a2b01..55f4f34e1bc 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -47,6 +47,36 @@ #define SRC_MEDIA_RBASE (SRC_IPS_BASE_ADDR + 0x2400) #define SRC_M33P_RBASE (SRC_IPS_BASE_ADDR + 0x2800) +#ifdef CONFIG_IMX94 +#define TCML_BASE_ADDR (0x209C0000UL) +#define TCML_BASE_MCORE_SEC_ADDR (0x1FFC0000UL) +#define TCML_BASE_MCORE_NSEC_ADDR (0x0FFC0000UL) +#define TCML_SIZE (0x40000U) +#define TCMU_BASE_ADDR (0x20A00000UL) +#define TCMU_BASE_MCORE_SEC_ADDR (0x30000000UL) +#define TCMU_BASE_MCORE_NSEC_ADDR (0x20000000UL) +#define TCMU_SIZE (0x40000U) +#else +#define TCML_BASE_ADDR (0x201E0000UL) +#define TCML_BASE_MCORE_SEC_ADDR (0x1FFE0000UL) +#define TCML_BASE_MCORE_NSEC_ADDR (0x0FFE0000UL) +#define TCML_SIZE (0x20000U) +#define TCMU_BASE_ADDR (0x20200000UL) +#define TCMU_BASE_MCORE_SEC_ADDR (0x30000000UL) +#define TCMU_BASE_MCORE_NSEC_ADDR (0x20000000UL) +#define TCMU_SIZE (0x20000U) +#endif + +#define M7_TCML_BASE_ADDR (0x20380000UL) +#define M7_TCML_BASE_MCORE_ADDR (0x0UL) +#define M7_TCML_MAX_SIZE (0x80000U) /* Could configure to 512KB TCML */ +#define M71_TCML_BASE_ADDR (0x20280000UL) +#define M71_TCML_BASE_MCORE_ADDR (0x0UL) +#define M71_TCML_MAX_SIZE (0x80000U) /* Could configure to 512KB TCML */ + +#define FLEXSPI_AHB_ADDR (0x28000000UL) +#define FLEXSPI_AHB_SIZE (0x8000000UL) + #define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0) #define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2) #define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4) diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index d43e54e72aa..bdcc5796e5b 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -28,6 +28,8 @@ int scmi_get_boot_device_offset(unsigned long *img_off); int scmi_get_boot_stage(u8 *stage); u8 scmi_get_imgset_sel(void); +int power_on_mcore(const char *sm_cfgname); + #define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode)) #endif diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 5f7d7e4c66e..c03c4e72101 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -437,6 +437,12 @@ config TARGET_LIBREM5 select IMX8M_LPDDR4 imply OF_UPSTREAM +config TARGET_LIBREM5_DEVKIT + bool "Purism Librem5 Devkit" + select IMX8MQ + select SUPPORT_SPL + select IMX8M_LPDDR4 + endchoice source "board/advantech/imx8mp_rsb3720a1/Kconfig" @@ -469,6 +475,7 @@ source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/polyhex/imx8mp_debix_model_a/Kconfig" source "board/purism/librem5/Kconfig" +source "board/purism/librem5-devkit/Kconfig" source "board/ronetix/imx8mq-cm/Kconfig" source "board/technexion/pico-imx8mq/Kconfig" source "board/variscite/imx8mn_var_som/Kconfig" diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index cbd0078ba2a..1271a3e88e6 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -165,6 +165,14 @@ config TARGET_IMX95_15X15_EVK imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_IMX95_15X15_FRDM + bool "imx95_frdm" + select OF_BOARD_FIXUP + select IMX95 + imply BOOTSTD_FULL + imply BOOTSTD_BOOTCOMMAND + imply OF_UPSTREAM + config TARGET_IMX943_EVK bool "imx943_evk" select OF_BOARD_FIXUP @@ -210,6 +218,7 @@ source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" +source "board/nxp/imx95_frdm/Kconfig" source "board/toradex/aquila-imx95/Kconfig" source "board/toradex/smarc-imx95/Kconfig" source "board/toradex/verdin-imx95/Kconfig" diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c index 73f2e72263d..5b94d71fda5 100644 --- a/arch/arm/mach-imx/imx9/imx_bootaux.c +++ b/arch/arm/mach-imx/imx9/imx_bootaux.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2022 NXP + * Copyright 2022, 2026 NXP */ #include <command.h> @@ -9,12 +9,23 @@ #include <vsprintf.h> #include <linux/arm-smccc.h> #include <linux/errno.h> +#include <asm/mach-imx/ahab.h> +#include <asm/arch/imx-regs.h> +#include <cpu_func.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CORE_CM33 0 +#define CORE_CM7 1 +#define CORE_CM71 7 +#define CORE_CM33S 8 int arch_auxiliary_core_check_up(u32 core_id) { struct arm_smccc_res res; - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, core_id, 0, 0, 0, 0, &res); return res.a0; @@ -26,7 +37,7 @@ int arch_auxiliary_core_down(u32 core_id) printf("## Stopping auxiliary core\n"); - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, core_id, 0, 0, 0, 0, &res); return 0; @@ -36,17 +47,263 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) { struct arm_smccc_res res; - if (!addr) - return -EINVAL; - printf("## Starting auxiliary core addr = 0x%08lX...\n", addr); - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, addr, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, addr, core_id, + 0, 0, 0, 0, &res); + + return 0; +} + +#if IS_ENABLED(CONFIG_SCMI_FIRMWARE) +int arch_auxiliary_core_prepare(u32 core_id) +{ + struct arm_smccc_res res; + + printf("## Preparing auxiliary core: %d\n", core_id); + + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_PREP, 0, core_id, + 0, 0, 0, 0, &res); + + return res.a0; +} + +int arch_auxiliary_core_prepared(u32 core_id) +{ + struct arm_smccc_res res; + + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_PREPED, 0, core_id, 0, 0, 0, 0, &res); + return res.a0; +} +#else +int arch_auxiliary_core_prepare(u32 core_id) +{ return 0; } +bool arch_auxiliary_core_prepared(u32 core_id) +{ + return true; +} +#endif + +static inline bool check_in_ddr(ulong addr) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (gd->dram[i].size) { + if (addr >= gd->dram[i].start && + addr < (gd->dram[i].start + gd->dram[i].size)) + return true; + } + } + + return false; +} + +static inline bool check_in_tcm(u32 core_id, ulong addr, bool mcore_view) +{ + if (mcore_view) { + if (core_id == CORE_CM33 || core_id == CORE_CM33S) { + if ((addr >= TCML_BASE_MCORE_SEC_ADDR && + addr < TCML_BASE_MCORE_SEC_ADDR + TCML_SIZE) || + (addr >= TCMU_BASE_MCORE_SEC_ADDR && + addr < TCMU_BASE_MCORE_SEC_ADDR + TCMU_SIZE)) + return true; + + if ((addr >= TCML_BASE_MCORE_NSEC_ADDR && + addr < TCML_BASE_MCORE_NSEC_ADDR + TCML_SIZE) || + (addr >= TCMU_BASE_MCORE_NSEC_ADDR && + addr < TCMU_BASE_MCORE_NSEC_ADDR + TCMU_SIZE)) + return true; + } else if (core_id == CORE_CM7 || core_id == CORE_CM71) { + if (addr >= M7_TCML_BASE_MCORE_ADDR && + addr < M7_TCML_BASE_MCORE_ADDR + M7_TCML_MAX_SIZE) + return true; + } + } else { + if (core_id == CORE_CM33 || core_id == CORE_CM33S) { + if ((addr >= TCML_BASE_ADDR && + addr < TCML_BASE_ADDR + TCML_SIZE) || + (addr >= TCMU_BASE_ADDR && + addr < TCMU_BASE_ADDR + TCMU_SIZE)) + return true; + } else if (core_id == CORE_CM7) { + if (addr >= M7_TCML_BASE_ADDR && + addr < M7_TCML_BASE_ADDR + M7_TCML_MAX_SIZE) + return true; + } else if (core_id == CORE_CM71) { + if (addr >= M71_TCML_BASE_ADDR && + addr < M71_TCML_BASE_ADDR + M7_TCML_MAX_SIZE) + return true; + } + } + return false; +} + +static inline bool check_in_flexspi(ulong addr) +{ + if (addr >= FLEXSPI_AHB_ADDR && addr < FLEXSPI_AHB_ADDR + FLEXSPI_AHB_SIZE) + return true; + + return false; +} + +#if IS_ENABLED(CONFIG_AHAB_BOOT) +static int authenticate_auxcore_container(u32 core_id, ulong addr, ulong *entry) +{ + struct container_hdr *phdr; + int i, ret = 0; + u16 length; + struct boot_img_t *img; + unsigned long s, e; + + if (addr % 4) { + printf("Error: Image's address is not 4 byte aligned\n"); + return -EINVAL; + } + + if (!check_in_ddr(addr) && !check_in_tcm(core_id, addr, false) && + !check_in_flexspi(addr)) { + printf("Error: Container's address is invalid\n"); + return -EINVAL; + } + + phdr = (struct container_hdr *)addr; + if (!valid_container_hdr(phdr)) { + printf("Error: Wrong container header\n"); + return -EFAULT; + } + + if (!phdr->num_images) { + printf("Error: Wrong container, no image found\n"); + return -EFAULT; + } + + length = phdr->length_lsb + (phdr->length_msb << 8); + + debug("container length %u\n", length); + + phdr = ahab_auth_cntr_hdr(phdr, length); + if (!phdr) { + ret = -EIO; + goto exit; + } + + /* Copy images to dest address */ + for (i = 0; i < phdr->num_images; i++) { + img = (struct boot_img_t *)((ulong)phdr + + sizeof(struct container_hdr) + + i * sizeof(struct boot_img_t)); + + /* Check Core ID of M core */ + if ((img->meta & 0xff) != core_id) { + printf("Error: Wrong Image core ID, meta = 0x%x\n", img->meta); + ret = -EFAULT; + break; + } + + debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n", + i, (uint32_t)img->dst, img->offset + addr, img->size); + + if (check_in_flexspi(img->dst)) { + if (img->dst != img->offset + addr) { + printf("Error: Wrong Image[%u] load address 0x%llx\n", i, img->dst); + ret = -EFAULT; + break; + } + } else { + if (!check_in_ddr(img->dst) && + !check_in_tcm(core_id, img->dst, false)) { + printf("Error: Invalid Image[%u] load address 0x%llx\n", + i, img->dst); + ret = -EFAULT; + break; + } + + memcpy((void *)img->dst, (const void *)(img->offset + addr), img->size); + + s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1); + e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1; + + flush_dcache_range(s, e); + } + + ret = ahab_verify_cntr_image(img, i); + if (ret) + goto exit; + + /* If the image is type of executable, set entry */ + if (entry && (img->hab_flags & 0xf) == 0x3) + *entry = img->entry; + } + +exit: + debug("ahab_auth_release, 0x%x\n", ret); + ahab_auth_release(); + + return ret; +} + +static int do_bootaux_cntr(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + ulong addr, entry; + int ret, up; + u32 core = 0; + u32 stop = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + if (argc > 2) + core = simple_strtoul(argv[2], NULL, 10); + + if (argc > 3) + stop = simple_strtoul(argv[3], NULL, 10); + + up = arch_auxiliary_core_check_up(core); + if (up) { + printf("## Auxiliary core is already up\n"); + return CMD_RET_SUCCESS; + } + + up = arch_auxiliary_core_prepared(core); + if (!up) { + printf("## Not prepared, run 'prepaux [coreid]' first\n"); + return CMD_RET_FAILURE; + } + + addr = simple_strtoul(argv[1], NULL, 16); + + if (!addr) + return CMD_RET_FAILURE; + + printf("Authenticate auxcore container at 0x%lx\n", addr); + + ret = authenticate_auxcore_container(core, addr, &entry); + if (ret) { + printf("Authenticate container failed %d\n", ret); + return CMD_RET_FAILURE; + } + + if (!check_in_ddr(entry) && !check_in_tcm(core, entry, true) && + !check_in_flexspi(entry)) { + printf("Error: Image's entry 0x%lx is invalid\n", entry); + return CMD_RET_FAILURE; + } + + ret = arch_auxiliary_core_up(core, entry); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} +#else + /* * To i.MX6SX and i.MX7D, the image supported by bootaux needs * the reset vector at the head for the image, with SP and PC @@ -83,10 +340,25 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } + up = arch_auxiliary_core_prepared(core); + if (!up) { + printf("## Not prepared, run 'prepaux [coreid]' first\n"); + return CMD_RET_FAILURE; + } + addr = simple_strtoul(argv[1], NULL, 16); - if (!addr) + if ((core != CORE_CM7 && core != CORE_CM71) && !addr) { + printf("Invalid address 0x%lx for core: %d\n", addr, core); return CMD_RET_FAILURE; + } + + if (!check_in_ddr(addr) && !check_in_tcm(core, addr, true) && !check_in_flexspi(addr)) { + printf("Error: Image's address 0x%lx is invalid\n", addr); + printf(" Address should be memory from M core view,\n" + " For example: 0x1ffe0000 for TCML in secure\n"); + return CMD_RET_FAILURE; + } ret = arch_auxiliary_core_up(core, addr); if (ret) @@ -94,19 +366,27 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } +#endif static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int ret, up; + u32 core = 0; - up = arch_auxiliary_core_check_up(0); + if (argc < 2) + return CMD_RET_USAGE; + + if (argc > 2) + core = simple_strtoul(argv[2], NULL, 10); + + up = arch_auxiliary_core_check_up(core); if (!up) { printf("## Auxiliary core is already down\n"); return CMD_RET_SUCCESS; } - ret = arch_auxiliary_core_down(0); + ret = arch_auxiliary_core_down(core); if (ret) return CMD_RET_FAILURE; @@ -119,12 +399,67 @@ U_BOOT_CMD( "<address> [<core>]\n" " - start auxiliary core [<core>] (default 0),\n" " at address <address>\n" + " <core>:\n" + " 0 - CM33\n" + " 1 - CM70\n" + " 7 - CM71\n" + " 8 - CM33 Sync\n" ); +static int do_prepaux(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int ret; + u32 core = 0; + + if (argc != 2) + return CMD_RET_USAGE; + + core = simple_strtoul(argv[1], NULL, 10); + + ret = arch_auxiliary_core_prepare(core); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD( + prepaux, CONFIG_SYS_MAXARGS, 1, do_prepaux, + "prepare auxiliary core", + "[<core>]\n" + " - prep auxiliary core [<core>] (default 0),\n" + " <core>:\n" + " 0 - CM33\n" + " 1 - CM70\n" + " 7 - CM71\n" + " 8 - CM33 Sync\n" +); + +#if IS_ENABLED(CONFIG_AHAB_BOOT) +U_BOOT_CMD( + bootaux_cntr, CONFIG_SYS_MAXARGS, 1, do_bootaux_cntr, + "Start auxiliary core", + "<container_address> [<core>]\n" + " - start auxiliary core [<core>] (default 0),\n" + " with signed container image at address <address> in A core view\n" + " <core>:\n" + " 0 - CM33\n" + " 1 - CM70\n" + " 7 - CM71\n" + " 8 - CM33 Sync\n" +); +#else U_BOOT_CMD( bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux, "Start auxiliary core", "<address> [<core>]\n" " - start auxiliary core [<core>] (default 0),\n" " at address <address> of auxiliary core view\n" + " <core>:\n" + " 0 - CM33\n" + " 1 - CM70\n" + " 7 - CM71\n" + " 8 - CM33 Sync\n" ); +#endif diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 18d00355999..8bb3ce5cad9 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -14,6 +14,7 @@ #include <asm/setup.h> #include <dm/uclass.h> #include <dm/device.h> +#include <dm/ofnode.h> #include <env_internal.h> #include <fuse.h> #include <imx_thermal.h> @@ -58,6 +59,43 @@ uint32_t scmi_get_rom_data(rom_passover_t *rom_data) return 0; } +int scmi_misc_cfginfo(u32 *msel, char *cfgname) +{ + struct scmi_imx_misc_cfg_info_out out = {}; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC, + .message_id = SCMI_IMX_MISC_CFG_INFO, + .in_msg = (u8 *)NULL, + .in_msg_sz = 0, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + struct udevice *dev; + + if (!msel || !cfgname) + return -EINVAL; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + + if (out.status) { + printf("Failed to get cfg name, scmi_err = %d\n", + out.status); + return scmi_to_linux_errno(out.status); + } + + *msel = out.msel; + strcpy(cfgname, (const char *)out.cfgname); + + return 0; +} + int scmi_misc_ddrinfo(u32 ddrc_id, struct scmi_ddr_info_out *out) { u32 in = ddrc_id; @@ -248,7 +286,38 @@ static struct mm_region imx9_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, +#if IS_ENABLED(CONFIG_IMX94) + { + /* M71 TCM */ + .virt = 0x202c0000UL, + .phys = 0x202c0000UL, + .size = 0x80000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* M33S TCM */ + .virt = 0x209c0000UL, + .phys = 0x209c0000UL, + .size = 0x80000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + /* 644K netc ocram for rpmsg buffer */ + { + /* M33S NETC OCRAM */ + .virt = 0x20800000UL, + .phys = 0x20800000UL, + .size = 0xa1000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, +#endif + { /* OCRAM */ .virt = 0x20480000UL, .phys = 0x20480000UL, @@ -593,6 +662,18 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) eth_addr_add(mac, 8); /* enetc1 */ if (dev_id == 2) eth_addr_add(mac, 9); /* enetc2 */ + } else if (is_imx952()) { + /* + * i.MX952 uses the following mac address offset list: + * | No. | Mac address user | + * |-----|----------------------| + * | 0 | enetc mac pf0 | + * | 1 | enetc mac vf0 | + * | 2 | enetc mac pf1 | + * | 3 | enetc mac vf1 | + */ + if (dev_id == 1) + eth_addr_add(mac, 2); } else { if (dev_id == 1) eth_addr_add(mac, 3); @@ -692,22 +773,20 @@ int get_reset_reason(bool sys, bool lm) } if (out.bootflags & MISC_BOOT_FLAG_VLD) { - printf("SYS Boot reason: %s, origin: %ld, errid: %ld\n", - rst[out.bootflags & MISC_BOOT_FLAG_REASON], - out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? - FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, - out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? - FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1 - ); + printf("SYS Boot reason: %s", rst[out.bootflags & MISC_BOOT_FLAG_REASON]); + if (out.bootflags & MISC_BOOT_FLAG_ORG_VLD) + printf(", origin: %ld", FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags)); + if (out.bootflags & MISC_BOOT_FLAG_ERR_VLD) + printf(", errid: %ld", FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags)); + puts("\n"); } if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { - printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n", - rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON], - out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags) : -1, - out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags) : -1 - ); + printf("SYS shutdown reason: %s", rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON]); + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD) + printf(", origin: %ld", FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags)); + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD) + printf(", errid: %ld", FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags)); + puts("\n"); } } @@ -722,23 +801,21 @@ int get_reset_reason(bool sys, bool lm) } if (out.bootflags & MISC_BOOT_FLAG_VLD) { - printf("LM Boot reason: %s, origin: %ld, errid: %ld\n", - rst[out.bootflags & MISC_BOOT_FLAG_REASON], - out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? - FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, - out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? - FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1 - ); + printf("LM Boot reason: %s", rst[out.bootflags & MISC_BOOT_FLAG_REASON]); + if (out.bootflags & MISC_BOOT_FLAG_ORG_VLD) + printf(", origin: %ld", FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags)); + if (out.bootflags & MISC_BOOT_FLAG_ERR_VLD) + printf(", errid: %ld", FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags)); + puts("\n"); } if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { - printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n", - rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON], - out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags) : -1, - out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags) : -1 - ); + printf("LM shutdown reason: %s", rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON]); + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD) + printf(", origin: %ld", FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags)); + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD) + printf(", errid: %ld", FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags)); + puts("\n"); } } @@ -829,6 +906,67 @@ const char *get_cpu_variant_type_name(u32 type) return NULL; } +int power_on_mcore(const char *sm_cfgname) +{ + char cfgname[MISC_MAX_CFGNAME]; + u32 msel; + int ret; + struct udevice *dev; + + ret = scmi_misc_cfginfo(&msel, cfgname); + if (ret) + return ret; + + if (strncmp(cfgname, sm_cfgname, MISC_MAX_CFGNAME)) + return -EINVAL; + + printf("power on mcore for %s\n", sm_cfgname); + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + if (!arch_auxiliary_core_check_up(1)) { + /* Power up M7MIX */ + ret = scmi_pwd_state_set(dev, 0, SCMI_PD(M70), 0); + if (ret) { + printf("Power M7 failed\n"); + return -EIO; + } + + /* In case OEI not init ECC, do it here */ + memset_io((void *)0x203c0000, 0, 0x40000); + memset_io((void *)0x20400000, 0, 0x40000); + } + +#if IS_ENABLED(CONFIG_IMX94) + if (!arch_auxiliary_core_check_up(7)) { + ret = scmi_pwd_state_set(dev, 0, SCMI_PD(M71), 0); + if (ret) { + printf("Power M71 failed\n"); + return -EIO; + } + + memset_io((void *)0x202c0000, 0, 0x40000); + memset_io((void *)0x20300000, 0, 0x40000); + } + + if (!arch_auxiliary_core_check_up(8)) { + ret = scmi_pwd_state_set(dev, 0, SCMI_PD(NETC), 0); + if (ret) { + printf("Power M33S failed\n"); + return -EIO; + } + + memset_io((void *)0x209c0000, 0, 0x40000); + memset_io((void *)0x20A00000, 0, 0x40000); + memset_io((void *)0x20800000, 0, 0xa1000); + } +#endif + + return 0; +} + void build_info(void) { u32 fw_version, sha1, res = 0, status; @@ -922,6 +1060,22 @@ static void gpio_reset(ulong gpio_base) writel(0, gpio_base + 0x1c); } +static int gpio_available(const char *nodes_path) +{ + ofnode gpio_node = ofnode_path(nodes_path); + const char *status; + + if (!ofnode_valid(gpio_node)) + return false; + + status = ofnode_read_string(gpio_node, "status"); + + if (status && !strcmp(status, "disabled")) + return false; + + return true; +} + int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { @@ -937,7 +1091,9 @@ int arch_cpu_init(void) disable_wdog((void __iomem *)base); } - gpio_reset(GPIO2_BASE_ADDR); + if (gpio_available("/soc/gpio@43810000")) + gpio_reset(GPIO2_BASE_ADDR); + gpio_reset(GPIO3_BASE_ADDR); gpio_reset(GPIO4_BASE_ADDR); gpio_reset(GPIO5_BASE_ADDR); diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index a38adfed02b..ffcc05e8683 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -637,6 +637,7 @@ config TARGET_TQMA6UL bool "TQ-Systems TQMa6UL[L]x" depends on MX6UL || MX6ULL select TQ_COMMON_SOM + select TQ_COMMON_SYSINFO select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select OF_SYSTEM_SETUP diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 5a1258e002d..2447698cfe4 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -71,13 +71,13 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl) val_ctrl = readl(reg_ctrl); val_ctrl &= 0xf0000000; - dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0; + dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0x80; dg_dl_abs_offset = dg_tmp_val & 0x7f; dg_hc_del = (dg_tmp_val & 0x780) << 1; val_ctrl |= dg_dl_abs_offset + dg_hc_del; - dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0; + dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0x80; dg_dl_abs_offset = dg_tmp_val & 0x7f; dg_hc_del = (dg_tmp_val & 0x780) << 1; diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index e504c1fd52a..8a858dea518 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -331,6 +331,12 @@ int arch_cpu_init(void) init_snvs(); + /* + * imx_gpcv2_init() needs to do a delay. + * Timer must be initialized before calling a delay function. + */ + timer_init(); + imx_gpcv2_init(); enable_ca7_smp(); diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 96fe2c7c17b..86311d0cc07 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -65,6 +65,9 @@ int timer_init(void) struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; unsigned long val, freq; + if (gd->arch.timer_rate_hz) + return 0; + freq = CFG_SC_TIMER_CLK; asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); @@ -103,8 +106,7 @@ ulong get_timer(ulong base) ulong timer_get_boot_us(void) { - if (!gd->arch.timer_rate_hz) - timer_init(); + timer_init(); return tick_to_time(get_ticks()); } diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index 228b424d3f2..7deae563841 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -414,6 +414,8 @@ static const struct clk_data clk_list[] = { CLK_MUX("pcien_cpts_rclk_mux_out1", pcien_cpts_rclk_mux_out1_parents, 16, 0x108084, 0, 4, 0), CLK_MUX("serdes0_core_refclk_out0", serdes0_core_refclk_out0_parents, 4, 0x108400, 0, 2, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0), + CLK_DIV("usart_programmable_clock_divider_out3", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081cc, 0, 2, 0, 0), CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0), CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0), CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), @@ -604,6 +606,10 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(333, 41, "wiz16b8m4ct3_main_0_ip2_ln3_txfclk"), DEV_CLK(333, 42, "wiz16b8m4ct3_main_0_ip2_ln3_txmclk"), DEV_CLK(333, 43, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(389, 0, "usart_programmable_clock_divider_out2"), + DEV_CLK(389, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(390, 0, "usart_programmable_clock_divider_out3"), + DEV_CLK(390, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(392, 0, "usart_programmable_clock_divider_out5"), DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"), diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c index 2bb1a88ab3b..2281da6a81f 100644 --- a/arch/arm/mach-k3/r5/j784s4/dev-data.c +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -47,13 +47,14 @@ static struct ti_lpsc soc_lpsc_list[] = { [15] = PSC_LPSC(25, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), [16] = PSC_LPSC(29, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]), [17] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL), - [18] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL), - [19] = PSC_LPSC(64, &soc_psc_list[2], &soc_pd_list[4], NULL), - [20] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[5], NULL), - [21] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[20]), - [22] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[20]), - [23] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[8], &soc_lpsc_list[24]), - [24] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[8], NULL), + [18] = PSC_LPSC(44, &soc_psc_list[2], &soc_pd_list[3], NULL), + [19] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL), + [20] = PSC_LPSC(64, &soc_psc_list[2], &soc_pd_list[4], NULL), + [21] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[5], NULL), + [22] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[21]), + [23] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[21]), + [24] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[8], &soc_lpsc_list[25]), + [25] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[8], NULL), }; static struct ti_dev soc_dev_list[] = { @@ -83,14 +84,16 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(140, &soc_lpsc_list[15]), PSC_DEV(333, &soc_lpsc_list[16]), PSC_DEV(146, &soc_lpsc_list[17]), - PSC_DEV(392, &soc_lpsc_list[18]), - PSC_DEV(395, &soc_lpsc_list[18]), - PSC_DEV(404, &soc_lpsc_list[19]), - PSC_DEV(198, &soc_lpsc_list[20]), - PSC_DEV(202, &soc_lpsc_list[21]), - PSC_DEV(203, &soc_lpsc_list[22]), - PSC_DEV(133, &soc_lpsc_list[23]), - PSC_DEV(193, &soc_lpsc_list[24]), + PSC_DEV(389, &soc_lpsc_list[18]), + PSC_DEV(390, &soc_lpsc_list[18]), + PSC_DEV(392, &soc_lpsc_list[19]), + PSC_DEV(395, &soc_lpsc_list[19]), + PSC_DEV(404, &soc_lpsc_list[20]), + PSC_DEV(198, &soc_lpsc_list[21]), + PSC_DEV(202, &soc_lpsc_list[22]), + PSC_DEV(203, &soc_lpsc_list[23]), + PSC_DEV(133, &soc_lpsc_list[24]), + PSC_DEV(193, &soc_lpsc_list[25]), }; const struct ti_k3_pd_platdata j784s4_pd_platdata = { diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c index ff027ed03ef..d12eb5339e9 100644 --- a/arch/arm/mach-mediatek/mt7629/init.c +++ b/arch/arm/mach-mediatek/mt7629/init.c @@ -41,7 +41,7 @@ static int mtk_pll_early_init(void) int ret, i; ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(mtk_clk_apmixedsys), &dev); + DM_DRIVER_GET(mt7629_clk_apmixedsys), &dev); if (ret) return ret; @@ -60,7 +60,7 @@ static int mtk_pll_early_init(void) /* setup mcu bus */ ret = uclass_get_device_by_driver(UCLASS_SYSCON, - DM_DRIVER_GET(mtk_mcucfg), &dev); + DM_DRIVER_GET(mt7629_mcucfg), &dev); if (ret) return ret; diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c index 1108bc19373..b2cdec8c218 100644 --- a/arch/arm/mach-mediatek/mt8188/init.c +++ b/arch/arm/mach-mediatek/mt8188/init.c @@ -33,7 +33,7 @@ void reset_cpu(void) { struct udevice *wdt; - if (IS_ENABLED(CONFIG_PSCI_RESET)) { + if (CONFIG_IS_ENABLED(PSCI_RESET)) { psci_system_reset(); } else { uclass_first_device(UCLASS_WDT, &wdt); diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c index b470910da7f..d9fe8fc8505 100644 --- a/arch/arm/mach-mediatek/mt8516/init.c +++ b/arch/arm/mach-mediatek/mt8516/init.c @@ -44,7 +44,7 @@ static int mtk_pll_early_init(void) int ret, i; ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(mtk_clk_apmixedsys), &dev); + DM_DRIVER_GET(mt8516_clk_apmixedsys), &dev); if (ret) return ret; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 3465ccfc151..1a8dbf2792e 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -238,6 +238,11 @@ config TARGET_X220 bool "Support Allied Telesis x220" select 98DX3336 +config TARGET_X960 + bool "Support Allied Telesis x960" + select ARMADA_8K + imply BOOTSTD_DEFAULTS + config TARGET_DB_XC3_24G4XG bool "Support DB-XC3-24G4XG" select 98DX3336 @@ -323,6 +328,7 @@ config SYS_BOARD default "x250" if TARGET_X250 default "x240" if TARGET_X240 default "x220" if TARGET_X220 + default "x960" if TARGET_X960 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 @@ -349,6 +355,7 @@ config SYS_CONFIG_NAME default "x250" if TARGET_X250 default "x240" if TARGET_X240 default "x220" if TARGET_X220 + default "x960" if TARGET_X960 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 default "mvebu_alleycat-5" if TARGET_MVEBU_ALLEYCAT5 @@ -375,6 +382,7 @@ config SYS_VENDOR default "alliedtelesis" if TARGET_X250 default "alliedtelesis" if TARGET_X240 default "alliedtelesis" if TARGET_X220 + default "alliedtelesis" if TARGET_X960 default "mikrotik" if TARGET_CRS3XX_98DX3236 default "Marvell" if TARGET_MVEBU_ALLEYCAT5 diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index da44727cf4f..a1eb6927c3e 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -276,9 +276,27 @@ int print_cpuinfo(void) case SOC_88F6828_ID: puts("MV88F6828-"); break; + case SOC_98DX3233_ID: + puts("98DX3233-"); + break; + case SOC_98DX3234_ID: + puts("98DX3234-"); + break; + case SOC_98DX3235_ID: + puts("98DX3235-"); + break; case SOC_98DX3236_ID: puts("98DX3236-"); break; + case SOC_98DX3333_ID: + puts("98DX3333-"); + break; + case SOC_98DX3334_ID: + puts("98DX3334-"); + break; + case SOC_98DX3335_ID: + puts("98DX3335-"); + break; case SOC_98DX3336_ID: puts("98DX3336-"); break; @@ -337,7 +355,13 @@ int print_cpuinfo(void) } break; + case SOC_98DX3233_ID: + case SOC_98DX3234_ID: + case SOC_98DX3235_ID: case SOC_98DX3236_ID: + case SOC_98DX3333_ID: + case SOC_98DX3334_ID: + case SOC_98DX3335_ID: case SOC_98DX3336_ID: case SOC_98DX4251_ID: switch (revid) { diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 495530d8452..33fdfd6d6c1 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -21,7 +21,13 @@ #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 #define SOC_88F6828_ID 0x6828 +#define SOC_98DX3233_ID 0xf413 +#define SOC_98DX3234_ID 0xf412 +#define SOC_98DX3235_ID 0xf411 #define SOC_98DX3236_ID 0xf410 +#define SOC_98DX3333_ID 0xf403 +#define SOC_98DX3334_ID 0xf402 +#define SOC_98DX3335_ID 0xf401 #define SOC_98DX3336_ID 0xf400 #define SOC_98DX4251_ID 0xfc00 diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 2e6bb38b923..98c890d3bdc 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -35,7 +35,8 @@ #include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) && \ + IS_ENABLED(CONFIG_PARTITION_TYPE_GUID) #define DFU_ALT_BUF_LEN SZ_1K @@ -193,7 +194,8 @@ int board_late_init(void) { setup_boot_mode(); -#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && IS_ENABLED(CONFIG_EFI_PARTITION) && \ + IS_ENABLED(CONFIG_PARTITION_TYPE_GUID) gpt_capsule_update_setup(); #endif diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 2730220a18e..ec22898137e 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -8,6 +8,12 @@ config TARGET_EVB_RK3568 help RK3568 EVB is a evaluation board for Rockchp RK3568. +config TARGET_ANBERNIC_RG_DS_RK3568 + bool "Anbernic RG DS" + help + Anbernic RG DS gaming device with Rockchip RK3568 and dual + displays. + config TARGET_ANBERNIC_RGXX3_RK3566 bool "Anbernic RGXX3" help @@ -71,6 +77,7 @@ config SYS_SOC default "rk3568" source "board/rockchip/evb_rk3568/Kconfig" +source "board/anbernic/rg-ds_rk3568/Kconfig" source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" source "board/hardkernel/odroid_m1s/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index e3e93f66395..76119cdb1ae 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -9,7 +9,8 @@ #include <misc.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> -#include <asm/arch-rockchip/hardware.h> +#include <asm/io.h> +#include <linux/hw_bitfield.h> #define SYS_GRF_BASE 0x2600A000 #define SYS_GRF_SOC_CON2 0x0008 @@ -21,6 +22,10 @@ #define GPIO0B_PULL_L 0x0024 #define GPIO0B_IE_L 0x002C +#define TOP_IOC_BASE 0x26044000 +#define IOC_MISC_CON 0x00F0 +#define TOP_IOC_FORCE_JTAG BIT(1) + #define SYS_SGRF_BASE 0x26004000 #define SYS_SGRF_SOC_CON14 0x0058 #define SYS_SGRF_SOC_CON15 0x005C @@ -190,6 +195,11 @@ int arch_cpu_init(void) */ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); + /* Disable JTAG exposed on SDMMC pins (GPIO2A2 and GPIO2A3) */ + if (IS_ENABLED(CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG)) + writel(FIELD_PREP_WM16(TOP_IOC_FORCE_JTAG, 0), + TOP_IOC_BASE + IOC_MISC_CON); + /* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */ writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 675f13ab66d..841ae490e85 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -208,6 +208,12 @@ config TARGET_RK3588_NEU6 IO board and Neu6a needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 6B(Neu6B) IO platform. +config TARGET_ROC_PC_RK3588S + bool "Firefly ROC PC RK3588S" + help + ROC-PC-RK3588S is a single board computer from Firefly + using the Rockchip RK3588S. + config TARGET_ROCK5A_RK3588 bool "Radxa ROCK5A RK3588 board" help @@ -421,6 +427,7 @@ config SYS_SOC source "board/armsom/sige7-rk3588/Kconfig" source "board/coolpi/genbook_cm5_rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" +source "board/firefly/roc-pc-rk3588s/Kconfig" source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 42e3735847a..dfbd4f43629 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -67,6 +67,9 @@ enum forced_boot_mode { BOOT_UMS_MMC2 = 0x12, }; +#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) +#define TAMP_FWU_BOOT_IDX_OFFSET 0 + #endif /* @@ -135,9 +138,6 @@ enum forced_boot_mode { /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) -#define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) -#define TAMP_FWU_BOOT_IDX_OFFSET 0 - #ifdef CONFIG_STM32MP15X #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 5ace74567dd..b0c5d3cd903 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -209,6 +209,13 @@ config SUN6I_PRCM Support for the PRCM (Power/Reset/Clock Management) unit available in A31 SoC. +config SUNXI_SYSCON + bool + select SYSCON + help + Enable syscon driver for Allwinner system controllers, which provides + access to the SRAM/system-control node for drivers. + config AXP_PMIC_BUS bool select DM_PMIC if DM_I2C diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 9c79b55abf3..ff475d8fff5 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -10,6 +10,7 @@ obj-y += board.o obj-y += cpu_info.o obj-y += dram_helpers.o obj-$(CONFIG_SUN6I_PRCM) += prcm.o +obj-$(CONFIG_SUNXI_SYSCON) += syscon.o obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o obj-$(CONFIG_MACH_SUNIV) += clock_sun6i.o obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 5f72e809952..6c9937128b9 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -105,35 +105,30 @@ /* * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting - * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. - * The H6 uses PC0, PC2, PC3, PC5, the H616 PC0, PC2, PC3, PC4. + * from SPI Flash, later SoCs are using pins PC0,PC1,PC2,PC3. + * Newer SoCs are all over the place. */ static void spi0_pinmux_setup(unsigned int pin_function) { - /* All chips use PC2. And all chips use PC0, except R528/T113 */ - if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function); - - sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function); - - /* All chips except H6/H616/R528/T113 use PC1. */ - if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) && - !IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function); - - if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) || - IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function); - if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || - IS_ENABLED(CONFIG_MACH_SUN8I_R528)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function); + const u16 spi0_pc_pins[4] = { +#if IS_ENABLED(CONFIG_MACH_SUN8I_R528) + SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(5) +#elif IS_ENABLED(CONFIG_MACH_SUN55I_A523) + SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4), SUNXI_GPC(12) +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H616) + SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(4) +#elif IS_ENABLED(CONFIG_MACH_SUN50I_H6) + SUNXI_GPC(0), SUNXI_GPC(2), SUNXI_GPC(3), SUNXI_GPC(5) +#elif IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || \ + IS_ENABLED(CONFIG_MACH_SUN8I_R40) + SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(23) +#else + SUNXI_GPC(0), SUNXI_GPC(1), SUNXI_GPC(2), SUNXI_GPC(3) +#endif + }; - /* Older generations use PC23 for CS, newer ones use PC3. */ - if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) || - IS_ENABLED(CONFIG_MACH_SUN8I_R40)) - sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); - else - sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); + for (int i = 0; i < 4; i++) + sunxi_gpio_set_cfgpin(spi0_pc_pins[i], pin_function); } static bool is_sun6i_gen_spi(void) @@ -257,7 +252,8 @@ static void spi0_init(void) unsigned int pin_function = SUNXI_GPC_SPI0; if (IS_ENABLED(CONFIG_MACH_SUN50I) || - IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_MACH_SUN55I_A523)) pin_function = SUN50I_GPC_SPI0; else if (IS_ENABLED(CONFIG_MACH_SUNIV) || IS_ENABLED(CONFIG_MACH_SUN8I_R528)) diff --git a/arch/arm/mach-sunxi/syscon.c b/arch/arm/mach-sunxi/syscon.c new file mode 100644 index 00000000000..e27110dfb0d --- /dev/null +++ b/arch/arm/mach-sunxi/syscon.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Junhui Liu <[email protected]> + */ + +#include <dm.h> +#include <syscon.h> + +static const struct udevice_id sunxi_syscon_ids[] = { + { .compatible = "allwinner,sun4i-a10-sram-controller" }, + { .compatible = "allwinner,sun4i-a10-system-control" }, + { .compatible = "allwinner,sun5i-a13-system-control" }, + { .compatible = "allwinner,sun8i-a23-system-control" }, + { .compatible = "allwinner,sun8i-h3-system-control" }, + { .compatible = "allwinner,sun20i-d1-system-control" }, + { .compatible = "allwinner,sun50i-a64-sram-controller" }, + { .compatible = "allwinner,sun50i-a64-system-control" }, + { .compatible = "allwinner,sun50i-h5-system-control" }, + { .compatible = "allwinner,sun50i-h616-system-control" }, + { .compatible = "allwinner,sun55i-a523-system-control" }, + { /* sentinel */ }, +}; + +U_BOOT_DRIVER(sunxi_syscon) = { + .name = "sunxi_syscon", + .id = UCLASS_SYSCON, + .of_match = sunxi_syscon_ids, +}; diff --git a/arch/arm/mach-versal2/Makefile b/arch/arm/mach-versal2/Makefile index 96497b1dfd0..73b3c8a6f35 100644 --- a/arch/arm/mach-versal2/Makefile +++ b/arch/arm/mach-versal2/Makefile @@ -8,3 +8,4 @@ obj-y += clk.o obj-y += cpu.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index 6cc6592b0fc..d72f66f4fba 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -11,6 +11,7 @@ #include <malloc.h> #include <time.h> #include <vsprintf.h> +#include <wait_bit.h> #include <asm/armv8/mmu.h> #include <asm/cache.h> #include <asm/global_data.h> @@ -160,6 +161,45 @@ u8 __weak versal2_get_bootmode(void) return bootmode; } +/* + * Wait for the M-PHY TX/RX config-ready status to settle (all bits cleared) or + * @timeout_us to elapse. The direct-MMIO fallback owns the poll loop, mirroring + * the EEMI backend; the timeout budget is owned by the caller. + */ +int __weak zynqmp_pm_wait_mphy_tx_rx_config_ready(u32 timeout_us) +{ + return wait_for_bit_le32((void *)(uintptr_t)(PMXC_SLCR_BASE_ADDRESS + + PMXC_TX_RX_CFG_RDY), + TX_RX_CFG_RDY_MASK, false, timeout_us / 1000, + false); +} + +int __weak zynqmp_pm_wait_sram_init_done(u32 timeout_us) +{ + return wait_for_bit_le32((void *)(uintptr_t)(PMXC_SLCR_BASE_ADDRESS + + PMXC_SRAM_CSR), + SRAM_CSR_INIT_DONE_MASK, true, timeout_us / 1000, + false); +} + +int __weak zynqmp_pm_set_sram_bypass(void) +{ + u32 sram_csr; + + sram_csr = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); + sram_csr &= ~SRAM_CSR_EXT_LD_DONE_MASK; + sram_csr |= SRAM_CSR_BYPASS_MASK; + writel(sram_csr, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); + + return 0; +} + +int __weak zynqmp_pm_get_ufs_calibration_values(u32 *value) +{ + *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET); + return 0; +} + void versal2_timer_setup(void) { u32 val; diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h index 1bebf20910a..4ff732d660f 100644 --- a/arch/arm/mach-versal2/include/mach/hardware.h +++ b/arch/arm/mach-versal2/include/mach/hardware.h @@ -4,34 +4,6 @@ * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. */ -#ifndef __ASSEMBLY__ -#include <linux/bitops.h> -#endif - -struct crlapb_regs { - u32 reserved0[67]; - u32 cpu_r5_ctrl; - u32 reserved; - u32 iou_switch_ctrl; /* 0x114 */ - u32 reserved1[13]; - u32 timestamp_ref_ctrl; /* 0x14c */ - u32 reserved3[108]; - u32 rst_cpu_r5; - u32 reserved2[17]; - u32 rst_timestamp; /* 0x348 */ -}; - -struct iou_scntrs_regs { - u32 counter_control_register; /* 0x0 */ - u32 reserved0[7]; - u32 base_frequency_id_register; /* 0x20 */ -}; - -struct crp_regs { - u32 reserved0[128]; - u32 boot_mode_usr; /* 0x200 */ -}; - #define VERSAL2_CRL_APB_BASEADDR 0xEB5E0000 #define VERSAL2_CRP_BASEADDR 0xF1260000 #define VERSAL2_IOU_SCNTR_SECURE 0xEC920000 @@ -41,10 +13,6 @@ struct crp_regs { #define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 #define IOU_SCNTRS_CONTROL_EN 1 -#define crlapb_base ((struct crlapb_regs *)VERSAL2_CRL_APB_BASEADDR) -#define crp_base ((struct crp_regs *)VERSAL2_CRP_BASEADDR) -#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL2_IOU_SCNTR_SECURE) - #define PMC_TAP 0xF11A0000 #define PMC_TAP_IDCODE (PMC_TAP + 0) @@ -76,15 +44,6 @@ struct crp_regs { #define PMC_MULTI_BOOT_REG 0xF1110004 #define PMC_MULTI_BOOT_MASK 0x1FFF -enum versal2_platform { - VERSAL2_SILICON = 0, - VERSAL2_SPP = 1, - VERSAL2_EMU = 2, - VERSAL2_QEMU = 3, - VERSAL2_SPP_MMD = 5, - VERSAL2_EMU_MMD = 6, -}; - #define VERSAL2_SLCR_BASEADDR 0xF1060000 #define VERSAL_AXI_MUX_SEL (VERSAL2_SLCR_BASEADDR + 0x504) #define VERSAL_OSPI_LINEAR_MODE BIT(1) @@ -106,5 +65,51 @@ enum versal2_platform { #define PMXC_SRAM_CSR 0x4C #define PMXC_TX_RX_CFG_RDY 0x54 +#define SRAM_CSR_INIT_DONE_MASK BIT(0) +#define SRAM_CSR_EXT_LD_DONE_MASK BIT(1) +#define SRAM_CSR_BYPASS_MASK BIT(2) +#define TX_RX_CFG_RDY_MASK GENMASK(3, 0) + #define PMC_GLOBAL_PGGS3_REG 0xF111005C #define PMC_GLOBAL_PGGS4_REG 0xF1110060 + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> + +struct crlapb_regs { + u32 reserved0[67]; + u32 cpu_r5_ctrl; + u32 reserved; + u32 iou_switch_ctrl; /* 0x114 */ + u32 reserved1[13]; + u32 timestamp_ref_ctrl; /* 0x14c */ + u32 reserved3[108]; + u32 rst_cpu_r5; + u32 reserved2[17]; + u32 rst_timestamp; /* 0x348 */ +}; + +struct iou_scntrs_regs { + u32 counter_control_register; /* 0x0 */ + u32 reserved0[7]; + u32 base_frequency_id_register; /* 0x20 */ +}; + +struct crp_regs { + u32 reserved0[128]; + u32 boot_mode_usr; /* 0x200 */ +}; + +#define crlapb_base ((struct crlapb_regs *)VERSAL2_CRL_APB_BASEADDR) +#define crp_base ((struct crp_regs *)VERSAL2_CRP_BASEADDR) +#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL2_IOU_SCNTR_SECURE) + +enum versal2_platform { + VERSAL2_SILICON = 0, + VERSAL2_SPP = 1, + VERSAL2_EMU = 2, + VERSAL2_QEMU = 3, + VERSAL2_SPP_MMD = 5, + VERSAL2_EMU_MMD = 6, +}; +#endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index b8d12d1dd3b..d678adf9c26 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. */ #ifndef _ASM_ARCH_SYS_PROTO_H @@ -22,4 +22,9 @@ u8 versal2_get_bootmode(void); /* EL3 clock/timer register setup, called from board_early_init_r() */ void versal2_timer_setup(void); +int zynqmp_pm_wait_mphy_tx_rx_config_ready(u32 timeout_us); +int zynqmp_pm_wait_sram_init_done(u32 timeout_us); +int zynqmp_pm_set_sram_bypass(void); +int zynqmp_pm_get_ufs_calibration_values(u32 *value); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-versal2/lowlevel_init.S b/arch/arm/mach-versal2/lowlevel_init.S new file mode 100644 index 00000000000..8bfe50b806e --- /dev/null +++ b/arch/arm/mach-versal2/lowlevel_init.S @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SoC specific lowlevel_init for AMD Versal Gen 2 + * + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> +#include <asm/arch/hardware.h> + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV3) + branch_if_slave x0, 1f + ldr x0, =GICD_BASE + bl gic_init_secure +1: + /* + * Pick the redistributor base for this part. Default to GICR_BASE + * and switch to GICR_BASE_2VM3654 when the PMC TAP IDCODE matches + * the 2VM3654 device. + */ + ldr x0, =GICR_BASE + ldr x1, =PMC_TAP_IDCODE + ldr w1, [x1] + ldr w2, =GICR_IDCODE_2VM3654 + cmp w1, w2 + b.ne 3f + ldr x0, =GICR_BASE_2VM3654 +3: + bl gic_init_secure_percpu +#endif + + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) diff --git a/arch/m68k/cpu/mcf530x/Makefile b/arch/m68k/cpu/mcf530x/Makefile index 6bd7cd3591d..d0956d9d1ba 100644 --- a/arch/m68k/cpu/mcf530x/Makefile +++ b/arch/m68k/cpu/mcf530x/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# (C) Copyright 2014 Angelo Dureghello <[email protected]> +# (C) Copyright 2014 Angelo Dureghello <[email protected]> extra-y = start.o obj-y = interrupts.o cpu.o speed.o cpu_init.o diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c index 92a0ef76895..bff2b485958 100644 --- a/arch/m68k/cpu/mcf530x/cpu.c +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2014 Angelo Dureghello <[email protected]> + * (C) Copyright 2014 Angelo Dureghello <[email protected]> * */ diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c index 8f6e668d103..f06e47f564a 100644 --- a/arch/m68k/cpu/mcf530x/cpu_init.c +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2014 Angelo Dureghello <[email protected]> + * (C) Copyright 2014 Angelo Dureghello <[email protected]> * */ diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c index 99cf8638503..005fce35c93 100644 --- a/arch/m68k/cpu/mcf530x/interrupts.c +++ b/arch/m68k/cpu/mcf530x/interrupts.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2014 Angelo Dureghello <[email protected]> + * (C) Copyright 2014 Angelo Dureghello <[email protected]> * */ diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c index 6542fc43ab1..4e9f4a09274 100644 --- a/arch/m68k/cpu/mcf530x/speed.c +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2014 Angelo Dureghello <[email protected]> + * (C) Copyright 2014 Angelo Dureghello <[email protected]> * */ diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 552e0204b77..76f7065758b 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2015 Angelo Dureghello <[email protected]> + * (C) Copyright 2015 Angelo Dureghello <[email protected]> * Based on code from Bernhard Kuhn <[email protected]> */ diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c index 13eb6ecee10..b0f844de5b2 100644 --- a/arch/m68k/cpu/mcf5445x/dspi.c +++ b/arch/m68k/cpu/mcf5445x/dspi.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2019 - * Angelo Dureghello <[email protected]> + * Angelo Dureghello <[email protected]> * * CPU specific dspi routines */ diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds index 452003ff43c..770c9e990d6 100644 --- a/arch/m68k/cpu/u-boot.lds +++ b/arch/m68k/cpu/u-boot.lds @@ -3,7 +3,7 @@ * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, [email protected]. * (C) Copyright 2015 - * Angelo Dureghello, Sysam Firmware, [email protected] + * Angelo Dureghello, Sysam Firmware, [email protected] */ #include <config.h> diff --git a/arch/m68k/dts/M5208EVBE.dts b/arch/m68k/dts/M5208EVBE.dts index ec203e8b698..cf5bc718cee 100644 --- a/arch/m68k/dts/M5208EVBE.dts +++ b/arch/m68k/dts/M5208EVBE.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5235EVB.dts b/arch/m68k/dts/M5235EVB.dts index e8b22c92166..084197bc3fe 100644 --- a/arch/m68k/dts/M5235EVB.dts +++ b/arch/m68k/dts/M5235EVB.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5235EVB_Flash32.dts b/arch/m68k/dts/M5235EVB_Flash32.dts index 60b28c07f76..fa463e87ed1 100644 --- a/arch/m68k/dts/M5235EVB_Flash32.dts +++ b/arch/m68k/dts/M5235EVB_Flash32.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5249EVB.dts b/arch/m68k/dts/M5249EVB.dts index 84ba4f188b4..32f4431d5fd 100644 --- a/arch/m68k/dts/M5249EVB.dts +++ b/arch/m68k/dts/M5249EVB.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5253DEMO.dts b/arch/m68k/dts/M5253DEMO.dts index a3f070661ea..25faf1ba73c 100644 --- a/arch/m68k/dts/M5253DEMO.dts +++ b/arch/m68k/dts/M5253DEMO.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5272C3.dts b/arch/m68k/dts/M5272C3.dts index a2289379072..1e77b882a94 100644 --- a/arch/m68k/dts/M5272C3.dts +++ b/arch/m68k/dts/M5272C3.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5275EVB.dts b/arch/m68k/dts/M5275EVB.dts index d79f8a78857..2e6a6e45d03 100644 --- a/arch/m68k/dts/M5275EVB.dts +++ b/arch/m68k/dts/M5275EVB.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5282EVB.dts b/arch/m68k/dts/M5282EVB.dts index 51788f9654a..f75a9c30aed 100644 --- a/arch/m68k/dts/M5282EVB.dts +++ b/arch/m68k/dts/M5282EVB.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M53017EVB.dts b/arch/m68k/dts/M53017EVB.dts index 90851dd0af4..d1b2534d4b0 100644 --- a/arch/m68k/dts/M53017EVB.dts +++ b/arch/m68k/dts/M53017EVB.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5329AFEE.dts b/arch/m68k/dts/M5329AFEE.dts index c1cd2845a38..a661b091354 100644 --- a/arch/m68k/dts/M5329AFEE.dts +++ b/arch/m68k/dts/M5329AFEE.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5329BFEE.dts b/arch/m68k/dts/M5329BFEE.dts index 51ec4b5d1aa..1fe0f6e5515 100644 --- a/arch/m68k/dts/M5329BFEE.dts +++ b/arch/m68k/dts/M5329BFEE.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/M5373EVB.dts b/arch/m68k/dts/M5373EVB.dts index 27ce800caeb..1ab63eae703 100644 --- a/arch/m68k/dts/M5373EVB.dts +++ b/arch/m68k/dts/M5373EVB.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/amcore.dts b/arch/m68k/dts/amcore.dts index d43202a3ab4..e9b01c9bb39 100644 --- a/arch/m68k/dts/amcore.dts +++ b/arch/m68k/dts/amcore.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/cobra5272.dts b/arch/m68k/dts/cobra5272.dts index 2b5767d96d1..9166d5726b9 100644 --- a/arch/m68k/dts/cobra5272.dts +++ b/arch/m68k/dts/cobra5272.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/eb_cpu5282.dts b/arch/m68k/dts/eb_cpu5282.dts index 27f33b9f900..6317e00c84e 100644 --- a/arch/m68k/dts/eb_cpu5282.dts +++ b/arch/m68k/dts/eb_cpu5282.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/eb_cpu5282_internal.dts b/arch/m68k/dts/eb_cpu5282_internal.dts index 53a94ea7f75..39fe86da496 100644 --- a/arch/m68k/dts/eb_cpu5282_internal.dts +++ b/arch/m68k/dts/eb_cpu5282_internal.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi index c61dbf35570..df7f4b377cd 100644 --- a/arch/m68k/dts/mcf5208.dtsi +++ b/arch/m68k/dts/mcf5208.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi index cae7b4f8616..5f1708fb0a3 100644 --- a/arch/m68k/dts/mcf523x.dtsi +++ b/arch/m68k/dts/mcf523x.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5249.dtsi b/arch/m68k/dts/mcf5249.dtsi index d45d5532caf..6174f2babe0 100644 --- a/arch/m68k/dts/mcf5249.dtsi +++ b/arch/m68k/dts/mcf5249.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5253.dtsi b/arch/m68k/dts/mcf5253.dtsi index b9816f4754b..45e463059d9 100644 --- a/arch/m68k/dts/mcf5253.dtsi +++ b/arch/m68k/dts/mcf5253.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi index 5acf6994af3..4ab23e9921d 100644 --- a/arch/m68k/dts/mcf5271.dtsi +++ b/arch/m68k/dts/mcf5271.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi index 173baaba3f2..1243ba9c482 100644 --- a/arch/m68k/dts/mcf5272.dtsi +++ b/arch/m68k/dts/mcf5272.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi index 3df17b445c4..f3043992446 100644 --- a/arch/m68k/dts/mcf5275.dtsi +++ b/arch/m68k/dts/mcf5275.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2019 Angelo Dureghello <[email protected]> + * Copyright (C) 2019 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi index 640c1a32e41..8f27756e183 100644 --- a/arch/m68k/dts/mcf5282.dtsi +++ b/arch/m68k/dts/mcf5282.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi index a13afad093a..d9a89cbde5a 100644 --- a/arch/m68k/dts/mcf5301x.dtsi +++ b/arch/m68k/dts/mcf5301x.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5307.dtsi b/arch/m68k/dts/mcf5307.dtsi index d6d386b22e1..a622afc916a 100644 --- a/arch/m68k/dts/mcf5307.dtsi +++ b/arch/m68k/dts/mcf5307.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi index 991985e48cf..58d6aaadf4e 100644 --- a/arch/m68k/dts/mcf5329.dtsi +++ b/arch/m68k/dts/mcf5329.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi index 4fa0f4bc3da..82d88944f3f 100644 --- a/arch/m68k/dts/mcf537x.dtsi +++ b/arch/m68k/dts/mcf537x.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi index 7cd6072d4a5..5c30d9f52cc 100644 --- a/arch/m68k/dts/mcf5441x.dtsi +++ b/arch/m68k/dts/mcf5441x.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/mcf54xx.dtsi b/arch/m68k/dts/mcf54xx.dtsi index e9cebb9f742..c3ade7cc87c 100644 --- a/arch/m68k/dts/mcf54xx.dtsi +++ b/arch/m68k/dts/mcf54xx.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ / { diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts index 8e196fa65ff..9e1ae8214dd 100644 --- a/arch/m68k/dts/stmark2.dts +++ b/arch/m68k/dts/stmark2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2018 Angelo Dureghello <[email protected]> + * Copyright (C) 2018 Angelo Dureghello <[email protected]> */ /dts-v1/; diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h index d96dd146efb..e41a1a9b08e 100644 --- a/arch/m68k/include/asm/immap_5307.h +++ b/arch/m68k/include/asm/immap_5307.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2014 Angelo Dureghello <[email protected]> + * (C) Copyright 2014 Angelo Dureghello <[email protected]> * */ diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h index 67547d2dd9d..223e8e5f27e 100644 --- a/arch/m68k/include/asm/m5307.h +++ b/arch/m68k/include/asm/m5307.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2014 Angelo Dureghello <[email protected]> + * (C) Copyright 2014 Angelo Dureghello <[email protected]> * */ diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ad7589123c6..c1b2890f1f3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -14,9 +14,6 @@ config TARGET_ANDES_AE350 config TARGET_ANDES_VOYAGER bool "Support Andes Voyager Board" -config TARGET_BANANAPI_F3 - bool "Support BananaPi F3 Board" - config TARGET_BEAGLEBOARD_BEAGLEVFIRE bool "Support BeagleBoard BeagleV-Fire Board (based on Microchip MPFS)" @@ -32,6 +29,9 @@ config TARGET_MICROCHIP_GENERIC config TARGET_MILKV_DUO bool "Support Milk-v Duo Board" +config TARGET_MILKV_DUO_256M + bool "Support Milk-V Duo 256M Board" + config TARGET_OPENPITON_RISCV64 bool "Support RISC-V cores on OpenPiton SoC" @@ -50,6 +50,9 @@ config TARGET_SIPEED_MAIX bool "Support Sipeed Maix Board" select SYS_CACHE_SHIFT_6 +config TARGET_SPACEMIT_K1 + bool "Support Spacemit K1 SoC" + config TARGET_STARFIVE_VISIONFIVE2 bool "Support StarFive VisionFive2 Board" select BOARD_LATE_INIT @@ -118,8 +121,9 @@ source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" source "board/sipeed/maix/Kconfig" source "board/sophgo/milkv_duo/Kconfig" +source "board/sophgo/milkv_duo_256m/Kconfig" source "board/sophgo/licheerv_nano/Kconfig" -source "board/spacemit/bananapi-f3/Kconfig" +source "board/spacemit/k1/Kconfig" source "board/starfive/visionfive2/Kconfig" source "board/thead/th1520_lpi4a/Kconfig" source "board/xilinx/mbv/Kconfig" @@ -378,7 +382,7 @@ config DMA_ADDR_T_64BIT default y if 64BIT config RISCV_ACLINT - bool + bool "RISC-V ACLINT support" depends on RISCV_MMODE select REGMAP select SYSCON @@ -387,7 +391,7 @@ config RISCV_ACLINT associated with software and timer interrupts. config SPL_RISCV_ACLINT - bool + bool "RISC-V ACLINT support in SPL" depends on SPL_RISCV_MMODE select SPL_REGMAP select SPL_SYSCON diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index bbadd0c9a46..3bec7c7cb6d 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -638,6 +638,9 @@ int riscv_cpu_setup(void) const char *isa, **exts; struct udevice *dev; + if (!CONFIG_IS_ENABLED(CPU)) + return 0; + uclass_find_first_device(UCLASS_CPU, &dev); if (!dev) { debug("unable to find the RISC-V cpu device\n"); diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig index 14201df80f2..b155535658d 100644 --- a/arch/riscv/cpu/k1/Kconfig +++ b/arch/riscv/cpu/k1/Kconfig @@ -1,12 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-or-later # # Copyright (C) 2024, Kongyang Liu <[email protected]> +# Copyright (C) 2025-2026, RISCstar Ltd. + +if TARGET_SPACEMIT_K1 config SPACEMIT_K1 bool select BINMAN select ARCH_EARLY_INIT_R select SYS_CACHE_SHIFT_6 + select SUPPORT_SPL imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) @@ -17,3 +21,5 @@ config SPACEMIT_K1 imply SPL_CPU imply SPL_OPENSBI imply SPL_LOAD_FIT + +endif diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 8e591cb7aa9..8ba75fdb9f5 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -2,10 +2,10 @@ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb -dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb +dtb-$(CONFIG_TARGET_MILKV_DUO_256M) += sg2002-milkv-duo256m.dtb dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index b518560bb94..84c261c6849 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -93,9 +93,7 @@ configurations { -#ifndef CONFIG_MULTI_DTB_FIT default = "conf-1"; -#endif #if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT) @conf-SEQ { diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi index 6fac247e7ac..8530527aa39 100644 --- a/arch/riscv/dts/cv18xx.dtsi +++ b/arch/riscv/dts/cv18xx.dtsi @@ -205,7 +205,7 @@ status = "disabled"; }; - spif: spi-nor@10000000 { + spif: spi@10000000 { compatible = "sophgo,cv1800b-spif"; reg = <0x10000000 0x10000000>; #address-cells = <1>; diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi new file mode 100644 index 00000000000..7f9443d6951 --- /dev/null +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2026 RISCstar Ltd. + */ + +#include "binman.dtsi" + +/ { + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; +}; + +&uart0 { + bootph-pre-ram; +}; + +&osc_32k { + bootph-pre-ram; +}; + +&vctcxo_1m { + bootph-pre-ram; +}; + +&vctcxo_3m { + bootph-pre-ram; +}; + +&vctcxo_24m { + bootph-pre-ram; +}; + +&syscon_mpmu { + bootph-pre-ram; +}; + +&pll { + bootph-pre-ram; +}; + +&syscon_apmu { + bootph-pre-ram; +}; + +&syscon_apbc { + bootph-pre-ram; +}; + +&i2c2 { + bootph-pre-ram; + resets = <&syscon_apbc RESET_TWSI2>; + + eeprom@50 { + bootph-pre-ram; + }; +}; + +/* + * The kernel pmic@41 nodes use the standard regulator-* properties only; + * U-Boot's regulator framework looks up suppliers by `regulator-name`. + * Carry the U-Boot-specific names (vdd_core / vdd_1v8 / vdd_1v8_mmc) here + * so SPL can program the bucks that DDR training depends on. + */ +&i2c8 { + bootph-pre-ram; + resets = <&syscon_apbc RESET_TWSI8>; + + pmic@41 { + bootph-pre-ram; + + regulators { + buck1 { + regulator-name = "vdd_core"; + bootph-pre-ram; + }; + + buck3 { + regulator-name = "vdd_1v8"; + bootph-pre-ram; + }; + + aldo1 { + regulator-name = "vdd_1v8_mmc"; + bootph-pre-ram; + }; + }; + }; +}; + +&binman { + u-boot-spl-ddr { + type = "section"; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + }; + + ddr-fw { + type = "blob"; + filename = "ddr_fw.bin"; + align = <64>; + }; + + u-boot-any { + type = "section"; + size = <0>; + offset = <0>; + }; + }; +}; diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts deleted file mode 100644 index 6b5b83bcdb9..00000000000 --- a/arch/riscv/dts/k1-bananapi-f3.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2024 Yangyu Chen <[email protected]> - */ - -#include "k1.dtsi" -#include "binman.dtsi" -#include "k1-pinctrl.dtsi" - -/ { - model = "Banana Pi BPI-F3"; - compatible = "bananapi,bpi-f3", "spacemit,k1"; - - chosen { - stdout-path = "serial0"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x80000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; -}; diff --git a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi new file mode 100644 index 00000000000..8a9a2a09de9 --- /dev/null +++ b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2026 RISCstar Ltd. + */ + +#include <dt-bindings/clock/spacemit,k1-syscon.h> +#include "binman.dtsi" + +/ { + aliases { + console = &uart0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x80000000>; + }; +}; + +&syscon_mpmu { + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, + <&pll CLK_PLL1_D4>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", + "pll1_d4"; +}; + +&syscon_apbc { + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, + <&pll CLK_PLL1_D4>, + <&syscon_mpmu CLK_PLL1_31P5>, + <&syscon_apmu CLK_PMUA_ACLK>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", + "pll1_d4", "pll1_d78_31p5", "pmua_aclk"; +}; + +&uart0 { + bootph-pre-ram; +}; + +&osc_32k { + bootph-pre-ram; +}; + +&vctcxo_1m { + bootph-pre-ram; +}; + +&vctcxo_3m { + bootph-pre-ram; +}; + +&vctcxo_24m { + bootph-pre-ram; +}; + +&syscon_mpmu { + bootph-pre-ram; +}; + +&pll { + bootph-pre-ram; +}; + +&syscon_apmu { + bootph-pre-ram; +}; + +&syscon_apbc { + bootph-pre-ram; +}; + +&i2c2 { + bootph-pre-ram; + status = "okay"; + pinctrl-0 = <&i2c2_0_cfg>; + pinctrl-names = "default"; + resets = <&syscon_apbc RESET_TWSI2>; + + eeprom@50 { + bootph-pre-ram; + status = "okay"; + compatible = "atmel,24c02"; + reg = <0x50>; + vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */ + pagesize = <16>; + read-only; + size = <256>; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + mac-address { + #nvmem-cell-cells = <1>; + }; + + num-macs { + }; + + serial-number { + }; + }; + }; +}; + +&i2c8 { + bootph-pre-ram; + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + resets = <&syscon_apbc RESET_TWSI8>; + status = "okay"; + + pmic@41 { + bootph-pre-ram; + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + status = "okay"; + + regulators { + buck1 { + bootph-pre-ram; + regulator-name = "vdd_core"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + bootph-pre-ram; + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + bootph-pre-ram; + regulator-name = "vdd_1v8_mmc"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + +&qspi { + bootph-pre-ram; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + bootph-pre-ram; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + m25p,fast-read; + broken-flash-reset; + status = "okay"; + }; +}; + +&binman { + u-boot-spl-ddr { + type = "section"; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + }; + + ddr-fw { + type = "blob"; + filename = "ddr_fw.bin"; + align = <64>; + }; + + u-boot-any { + type = "section"; + size = <0>; + offset = <0>; + }; + }; +}; diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1-pinctrl.dtsi deleted file mode 100644 index 14e7096fbcf..00000000000 --- a/arch/riscv/dts/k1-pinctrl.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 Spacemit Inc. - * Copyright (C) 2025 Yixun Lan <[email protected]> - */ - -#define K1_PADCONF(pin, func) (((pin) << 16) | (func)) - -&pinctrl { - uart0_2_cfg: uart0-2-cfg { - uart0-2-pins { - pinmux = <K1_PADCONF(68, 2)>, - <K1_PADCONF(69, 2)>; - - bias-pull-up = <0>; - drive-strength = <32>; - }; - }; -}; diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi deleted file mode 100644 index a633e43da32..00000000000 --- a/arch/riscv/dts/k1.dtsi +++ /dev/null @@ -1,480 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2024 Yangyu Chen <[email protected]> - */ - -/dts-v1/; -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "SpacemiT K1"; - compatible = "spacemit,k1"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - serial8 = &uart9; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <24000000>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_0>; - }; - core1 { - cpu = <&cpu_1>; - }; - core2 { - cpu = <&cpu_2>; - }; - core3 { - cpu = <&cpu_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu_4>; - }; - core1 { - cpu = <&cpu_5>; - }; - core2 { - cpu = <&cpu_6>; - }; - core3 { - cpu = <&cpu_7>; - }; - }; - }; - - cpu_0: cpu@0 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <0>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_1: cpu@1 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <1>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_2: cpu@2 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <2>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_3: cpu@3 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <3>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_4: cpu@4 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <4>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu4_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_5: cpu@5 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <5>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu5_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_6: cpu@6 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <6>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu6_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_7: cpu@7 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <7>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu7_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cluster0_l2_cache: l2-cache0 { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-size = <524288>; - cache-sets = <512>; - cache-unified; - }; - - cluster1_l2_cache: l2-cache1 { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-size = <524288>; - cache-sets = <512>; - cache-unified; - }; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <2>; - #size-cells = <2>; - dma-noncoherent; - ranges; - - uart0: serial@d4017000 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017000 0x0 0x100>; - interrupts = <42>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@d4017100 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017100 0x0 0x100>; - interrupts = <44>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@d4017200 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017200 0x0 0x100>; - interrupts = <45>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart4: serial@d4017300 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017300 0x0 0x100>; - interrupts = <46>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart5: serial@d4017400 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017400 0x0 0x100>; - interrupts = <47>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart6: serial@d4017500 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017500 0x0 0x100>; - interrupts = <48>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart7: serial@d4017600 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017600 0x0 0x100>; - interrupts = <49>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart8: serial@d4017700 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017700 0x0 0x100>; - interrupts = <50>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart9: serial@d4017800 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017800 0x0 0x100>; - interrupts = <51>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - plic: interrupt-controller@e0000000 { - compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xe0000000 0x0 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>, - <&cpu5_intc 11>, <&cpu5_intc 9>, - <&cpu6_intc 11>, <&cpu6_intc 9>, - <&cpu7_intc 11>, <&cpu7_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - riscv,ndev = <159>; - }; - - clint: timer@e4000000 { - compatible = "spacemit,k1-clint", "sifive,clint0"; - reg = <0x0 0xe4000000 0x0 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>, - <&cpu4_intc 3>, <&cpu4_intc 7>, - <&cpu5_intc 3>, <&cpu5_intc 7>, - <&cpu6_intc 3>, <&cpu6_intc 7>, - <&cpu7_intc 3>, <&cpu7_intc 7>; - }; - - sec_uart1: serial@f0612000 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xf0612000 0x0 0x100>; - interrupts = <43>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "reserved"; /* for TEE usage */ - }; - - reset: reset-controller@d4050000 { - compatible = "spacemit,k1-reset"; - reg = <0x0 0xd4050000 0x0 0x209c>, - <0x0 0xd4282800 0x0 0x400>, - <0x0 0xd4015000 0x0 0x1000>, - <0x0 0xd4090000 0x0 0x1000>, - <0x0 0xd4282c00 0x0 0x400>, - <0x0 0xd8440000 0x0 0x98>, - <0x0 0xc0000000 0x0 0x4280>, - <0x0 0xf0610000 0x0 0x20>; - reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2"; - #reset-cells = <1>; - status = "disabled"; - }; - - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k1-pinctrl", "pinctrl-single"; - reg = <0x0 0xd401e000 0x0 0x400>; - pinctrl-single,register-width = <32>; - }; - }; -}; diff --git a/arch/riscv/dts/sg2002-milkv-duo256m.dts b/arch/riscv/dts/sg2002-milkv-duo256m.dts new file mode 100644 index 00000000000..4ad86ce39ec --- /dev/null +++ b/arch/riscv/dts/sg2002-milkv-duo256m.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2026 Hiago De Franco <[email protected]> + */ + +/dts-v1/; + +#include "sg2002.dtsi" + +/ { + model = "Milk-V Duo 256M"; + compatible = "milkv,duo256m", "sophgo,sg2002"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +ðernet0 { + status = "okay"; + phy-mode = "rmii"; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&sdhci0 { + status = "okay"; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 31aa30bc7d7..ac5136fa6be 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -149,8 +149,6 @@ __weak int dcache_status(void) __weak void enable_caches(void) { zicbom_block_size = riscv_get_cbom_block_size(); - if (!zicbom_block_size) - log_debug("Zicbom not initialized.\n"); } int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm) diff --git a/arch/sh/include/asm/string.h b/arch/sh/include/asm/string.h index 999febcb6b7..12a9a8f796c 100644 --- a/arch/sh/include/asm/string.h +++ b/arch/sh/include/asm/string.h @@ -8,8 +8,6 @@ * from linux kernel code. */ -#ifdef __KERNEL__ /* only set these up for kernel code */ - #define __HAVE_ARCH_STRCPY static inline char *strcpy(char *__dest, const char *__src) { @@ -81,53 +79,4 @@ static inline int strcmp(const char *__cs, const char *__ct) return __res; } -#undef __HAVE_ARCH_STRNCMP -extern int strncmp(const char *__cs, const char *__ct, size_t __n); - -#undef __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, size_t __count); - -#undef __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, size_t __n); - -#undef __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, size_t __n); - -#undef __HAVE_ARCH_MEMCHR -extern void *memchr(const void *__s, int __c, size_t __n); - -#undef __HAVE_ARCH_STRLEN -extern size_t strlen(const char *); - -/* arch/sh/lib/strcasecmp.c */ -extern int strcasecmp(const char *, const char *); - -#else /* KERNEL */ - -/* - * let user libraries deal with these, - * IMHO the kernel has no place defining these functions for user apps - */ - -#define __HAVE_ARCH_STRCPY 1 -#define __HAVE_ARCH_STRNCPY 1 -#define __HAVE_ARCH_STRCAT 1 -#define __HAVE_ARCH_STRNCAT 1 -#define __HAVE_ARCH_STRCMP 1 -#define __HAVE_ARCH_STRNCMP 1 -#define __HAVE_ARCH_STRNICMP 1 -#define __HAVE_ARCH_STRCHR 1 -#define __HAVE_ARCH_STRRCHR 1 -#define __HAVE_ARCH_STRSTR 1 -#define __HAVE_ARCH_STRLEN 1 -#define __HAVE_ARCH_STRNLEN 1 -#define __HAVE_ARCH_MEMSET 1 -#define __HAVE_ARCH_MEMCPY 1 -#define __HAVE_ARCH_MEMMOVE 1 -#define __HAVE_ARCH_MEMSCAN 1 -#define __HAVE_ARCH_MEMCMP 1 -#define __HAVE_ARCH_MEMCHR 1 -#define __HAVE_ARCH_STRTOK 1 - -#endif /* KERNEL */ #endif /* __ASM_SH_STRING_H */ diff --git a/arch/x86/config.mk b/arch/x86/config.mk index c2bb5549b7c..a62015e1a64 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -25,8 +25,10 @@ endif ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 +PLATFORM_ELFFLAGS += -O elf32-i386 -B i386 else PLATFORM_CPPFLAGS += $(if $(CONFIG_XPL_BUILD),,-fpic) -fno-common -march=core2 -m64 +PLATFORM_ELFFLAGS += -O elf64-x86-64 -B i386:x86-64 ifndef CONFIG_X86_HARDFP PLATFORM_CPPFLAGS += -mno-mmx -mno-sse @@ -38,6 +40,7 @@ PLATFORM_RELFLAGS += -fdata-sections -ffunction-sections -fvisibility=hidden KBUILD_LDFLAGS += -Bsymbolic -Bsymbolic-functions KBUILD_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64) +PLATFORM_ELFLDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64) # This is used in the top-level Makefile which does not include # KBUILD_LDFLAGS |