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-rw-r--r--arch/x86/cpu/i386/cpu.c5
-rw-r--r--arch/x86/cpu/x86_64/cpu.c6
-rw-r--r--arch/x86/include/asm/u-boot-x86.h9
3 files changed, 20 insertions, 0 deletions
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 532f690c874..a51a24498a7 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -501,6 +501,11 @@ int x86_cpu_reinit_f(void)
return 0;
}
+void x86_get_identity_for_timer(void)
+{
+ setup_identity();
+}
+
void x86_enable_caches(void)
{
unsigned long cr0;
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 80eab710315..71bc07f872a 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -75,3 +75,9 @@ void board_debug_uart_init(void)
/* this was already done in SPL */
}
#endif
+
+void x86_get_identity_for_timer(void)
+{
+ /* set the vendor to Intel so that native_calibrate_tsc() works */
+ gd->arch.x86_vendor = X86_VENDOR_INTEL;
+}
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 5cc8f63334e..64139ead190 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -44,6 +44,15 @@ int x86_cpu_reinit_f(void);
int x86_cpu_init_tpl(void);
/**
+ * x86_get_identity_for_timer() - Set up CPU identity for use by the early timer
+ *
+ * The timer can be needed early in board_f if bootstage is enabled. This
+ * function can be called from the TSC timer to make sure that the CPU-identity
+ * info has been set up
+ */
+void x86_get_identity_for_timer(void);
+
+/**
* cpu_reinit_fpu() - Reinit the FPU if something is wrong with it
*
* The FSP-M code can leave registers in use in the FPU. This functions reinits