diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/Kconfig | 8 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/Kconfig (renamed from arch/riscv/cpu/ax25/Kconfig) | 0 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/Makefile (renamed from arch/riscv/cpu/ax25/Makefile) | 0 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/cache.c (renamed from arch/riscv/cpu/ax25/cache.c) | 0 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/cpu.c (renamed from arch/riscv/cpu/ax25/cpu.c) | 0 | ||||
| -rw-r--r-- | arch/riscv/cpu/andesv5/spl.c (renamed from arch/riscv/cpu/ax25/spl.c) | 0 | ||||
| -rw-r--r-- | arch/riscv/dts/Makefile | 2 |
7 files changed, 5 insertions, 5 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ebc4bef220e..48ca4ff4c4e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AX25_AE350 - bool "Support ax25-ae350" +config TARGET_AE350 + bool "Support ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" @@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF Do not enable data cache in SPL. # board-specific options below -source "board/AndesTech/ax25-ae350/Kconfig" +source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" @@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" # platform-specific options below -source "arch/riscv/cpu/ax25/Kconfig" +source "arch/riscv/cpu/andesv5/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/andesv5/Kconfig index 82bb5a2a532..82bb5a2a532 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/andesv5/Kconfig diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/andesv5/Makefile index 35a1a2fb836..35a1a2fb836 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/andesv5/Makefile diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/andesv5/cache.c index 40d77f671c8..40d77f671c8 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/andesv5/cache.c diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index 06e379bcb1f..06e379bcb1f 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/andesv5/spl.c index 413849043b1..413849043b1 100644 --- a/arch/riscv/cpu/ax25/spl.c +++ b/arch/riscv/cpu/andesv5/spl.c diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 5c15a0f303a..c576c55767f 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb |
