diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/cpu/coreboot/Kconfig | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/i386/cpu.c | 2 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 2 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_samus.dts | 2 | ||||
| -rw-r--r-- | arch/x86/include/asm/cb_sysinfo.h | 16 | ||||
| -rw-r--r-- | arch/x86/include/asm/mp.h | 12 | ||||
| -rw-r--r-- | arch/x86/lib/init_helpers.c | 18 | ||||
| -rw-r--r-- | arch/x86/lib/zimage.c | 8 |
8 files changed, 46 insertions, 16 deletions
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 497d6284ac1..b97c2779041 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -1,4 +1,4 @@ -if TARGET_COREBOOT +if VENDOR_COREBOOT config SYS_COREBOOT bool diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index e59215cc20e..c7f6c5a013e 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -423,7 +423,7 @@ static void setup_mtrr(void) u64 mtrr_cap; /* Configure fixed range MTRRs for some legacy regions */ - if (!gd->arch.has_mtrr) + if (!gd->arch.has_mtrr || !ll_boot_init()) return; mtrr_cap = native_read_msr(MTRR_CAP_MSR); diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index c8cb4e21c6d..66c31efb6cd 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -10,7 +10,7 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -#ifdef CONFIG_CHROMEOS_VBOOT +#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE) #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-16mb-rw.dtsi" diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index adaeb1ea355..ad35ab2e3fd 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -11,7 +11,7 @@ #include "smbios.dtsi" -#ifdef CONFIG_CHROMEOS_VBOOT +#if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE) #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-8mb-rw.dtsi" diff --git a/arch/x86/include/asm/cb_sysinfo.h b/arch/x86/include/asm/cb_sysinfo.h index 675eef6f2c9..75901359f98 100644 --- a/arch/x86/include/asm/cb_sysinfo.h +++ b/arch/x86/include/asm/cb_sysinfo.h @@ -215,6 +215,22 @@ struct sysinfo_t { extern struct sysinfo_t lib_sysinfo; +/** + * get_coreboot_info() - parse the coreboot sysinfo table + * + * Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if + * so. + * + * @info: Place to put the parsed information + * @return 0 if OK, -ENOENT if no table found + */ int get_coreboot_info(struct sysinfo_t *info); +/** + * cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo + * + * @return pointer to sysinfo, or NULL if not available + */ +const struct sysinfo_t *cb_get_sysinfo(void); + #endif diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 1a3ae8e3950..e48ba051d92 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -10,18 +10,22 @@ #include <asm/atomic.h> #include <asm/cache.h> +#include <linux/bitops.h> struct udevice; enum { - /* Indicates that the function should run on all CPUs */ - MP_SELECT_ALL = -1, + /* + * Indicates that the function should run on all CPUs. We use a large + * number, above the number of real CPUs we expect to find. + */ + MP_SELECT_ALL = BIT(16), /* Run on boot CPUs */ - MP_SELECT_BSP = -2, + MP_SELECT_BSP, /* Run on non-boot CPUs */ - MP_SELECT_APS = -3, + MP_SELECT_APS, }; typedef int (*mp_callback_t)(struct udevice *cpu, void *arg); diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 67401b9ba79..f33194045f9 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -18,10 +18,20 @@ int init_cache_f_r(void) IS_ENABLED(CONFIG_FSP_VERSION2); int ret; - if (!ll_boot_init()) - return 0; - - do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) && + /* + * Supported configurations: + * + * booting from slimbootloader - in that case the MTRRs are already set + * up + * booting with FSPv1 - MTRRs are already set up + * booting with FSPv2 - MTRRs must be set here + * booting from coreboot - in this case there is no SPL, so we set up + * the MTRRs here + * Note: if there is an SPL, then it has already set up MTRRs so we + * don't need to do that here + */ + do_mtrr &= !IS_ENABLED(CONFIG_SPL) && + !IS_ENABLED(CONFIG_FSP_VERSION1) && !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER); if (do_mtrr) { diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 90fc8a466d7..cf4210cd4ba 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -313,12 +313,12 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, int bootproto = get_boot_protocol(hdr, false); log_debug("Setup E820 entries\n"); - if (ll_boot_init()) { - setup_base->e820_entries = install_e820_map( - ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); - } else if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) { + if (IS_ENABLED(CONFIG_COREBOOT_SYSINFO)) { setup_base->e820_entries = cb_install_e820_map( ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); + } else { + setup_base->e820_entries = install_e820_map( + ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); } if (bootproto == 0x0100) { |