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-rw-r--r--board/freescale/common/arm_sleep.c2
-rw-r--r--board/freescale/common/mpc85xx_sleep.c2
-rw-r--r--board/freescale/ls1012afrdm/ls1012afrdm.c4
-rw-r--r--board/freescale/ls1012aqds/ls1012aqds.c4
-rw-r--r--board/freescale/ls1012ardb/ls1012ardb.c4
-rw-r--r--board/freescale/ls1021aqds/ddr.c2
-rw-r--r--board/freescale/ls1021atsn/ls1021atsn.c2
-rw-r--r--board/freescale/ls1021atwr/ls1021atwr.c2
-rw-r--r--board/freescale/m5208evbe/m5208evbe.c26
-rw-r--r--board/freescale/m5235evb/m5235evb.c8
-rw-r--r--board/freescale/m5249evb/m5249evb.c2
-rw-r--r--board/freescale/m5253demo/m5253demo.c6
-rw-r--r--board/freescale/m5272c3/m5272c3.c2
-rw-r--r--board/freescale/m5275evb/m5275evb.c18
-rw-r--r--board/freescale/m5282evb/m5282evb.c8
-rw-r--r--board/freescale/m53017evb/README2
-rw-r--r--board/freescale/m53017evb/m53017evb.c26
-rw-r--r--board/freescale/m5329evb/m5329evb.c24
-rw-r--r--board/freescale/m5373evb/README2
-rw-r--r--board/freescale/m5373evb/m5373evb.c24
-rw-r--r--board/freescale/mpc837xerdb/mpc837xerdb.c6
-rw-r--r--board/freescale/mx51evk/mx51evk.c2
-rw-r--r--board/freescale/p1_p2_rdb_pc/ddr.c2
23 files changed, 90 insertions, 90 deletions
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index f5bed6c35bb..46ffd817b44 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -61,7 +61,7 @@ static void dp_ddr_restore(void)
/* get the address of ddr date from SPARECR3 */
src = (u64 *)in_le32(&scfg->sparecr[2]);
- dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
+ dst = (u64 *)CFG_SYS_SDRAM_BASE;
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst++ = *src++;
diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c
index 71922aab4ef..d3323b9ec1e 100644
--- a/board/freescale/common/mpc85xx_sleep.c
+++ b/board/freescale/common/mpc85xx_sleep.c
@@ -50,7 +50,7 @@ static void dp_ddr_restore(void)
/* get the address of ddr date from SPARECR3 */
src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
- dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
+ dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst-- = *src--;
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index bc37c553a5b..f2b8750a3f3 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -102,7 +102,7 @@ int dram_init(void)
else
gd->ram_size = SYS_SDRAM_SIZE_512;
#else
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#endif
}
return 0;
@@ -139,7 +139,7 @@ int dram_init(void)
gd->ram_size = SYS_SDRAM_SIZE_512;
}
#else
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#endif
mmdc_init(&mparam);
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 3f70fbc3565..f17a6c186d3 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -66,7 +66,7 @@ int dram_init(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
@@ -90,7 +90,7 @@ int dram_init(void)
};
mmdc_init(&mparam);
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 456609d9932..62c935e4d3e 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -113,7 +113,7 @@ int dram_init(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
@@ -140,7 +140,7 @@ int dram_init(void)
mmdc_init(&mparam);
#endif
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 66fe1519cc6..4e70acc5a0c 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -192,7 +192,7 @@ int fsl_initdram(void)
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index 4325439be95..d144f25c623 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -47,7 +47,7 @@ static void ddrmc_init(void)
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
- out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 33027ad0575..8b74d458237 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -162,7 +162,7 @@ void ddrmc_init(void)
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
- out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */
diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
index 7bfb4557dd5..6125c9e13aa 100644
--- a/board/freescale/m5208evbe/m5208evbe.c
+++ b/board/freescale/m5208evbe/m5208evbe.c
@@ -29,7 +29,7 @@ int dram_init(void)
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,35 +37,35 @@ int dram_init(void)
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CONFIG_SYS_SDRAM_BASE1
- out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+#ifdef CFG_SYS_SDRAM_BASE1
+ out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
#endif
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
asm("nop");
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
asm("nop");
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
asm("nop");
udelay(100);
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index e7c7a94036b..44161a0b0a1 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -44,7 +44,7 @@ int dram_init(void)
GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
GPIO_PAR_SDRAM_SDCS(3));
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -61,7 +61,7 @@ int dram_init(void)
/* Initialize DACR0 */
out_be32(&sdram->dacr0,
- SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+ SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) |
SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
SDRAMC_DARCn_PS_32);
asm("nop");
@@ -80,7 +80,7 @@ int dram_init(void)
}
/* Write to this block to initiate precharge */
- *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
@@ -95,7 +95,7 @@ int dram_init(void)
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
gd->ram_size = dramsize;
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index 48c00791114..efff0551409 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -86,7 +86,7 @@ int dram_init(void)
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 85f5f0c0340..179a2a242a8 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -47,7 +47,7 @@ int dram_init(void)
__asm__("nop");
/* Initialize DMR0 */
- dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
+ dramsize = (CFG_SYS_SDRAM_SIZE << 20);
temp = (dramsize - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, temp | 1);
__asm__("nop");
@@ -57,7 +57,7 @@ int dram_init(void)
__asm__("nop");
/* Write to this block to initiate precharge */
- *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+ *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
mb();
__asm__("nop");
@@ -74,7 +74,7 @@ int dram_init(void)
mbar_readLong(MCFSIM_DACR0) | 0x0040);
__asm__("nop");
- *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+ *(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
mb();
}
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index 9580cf2a039..3c20a23385c 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -30,7 +30,7 @@ int dram_init(void)
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index 1c4fb7232af..00fa35ca5f7 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -35,7 +35,7 @@ int dram_init(void)
out_be16(&gpio_reg->par_sdram, 0x3FF);
/* Set up chip select */
- out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE);
out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
/* Set up timing */
@@ -49,34 +49,34 @@ int dram_init(void)
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
/* Dummy write to start SDRAM */
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
setbits_be32(&sdp->sdmr,
MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
MCF_SDRAMC_SDMR_CMD);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
out_be32(&sdp->sdmr, 0x058d0000);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
out_be32(&sdp->sdmr, 0x018d0000);
- *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+ *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
@@ -91,7 +91,7 @@ int dram_init(void)
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
| MCF_SDRAMC_SDCR_DQS_OE(0x3));
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};
diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index e1ea9b3a58f..53e0f202101 100644
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -21,7 +21,7 @@ int dram_init(void)
{
u32 dramsize, i, dramclk;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -40,7 +40,7 @@ int dram_init(void)
/* Initialize DACR0 */
MCFSDRAMC_DACR0 = (0
- | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
+ | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_32);
@@ -62,7 +62,7 @@ int dram_init(void)
}
/* Write to this block to initiate precharge */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696;
asm("nop");
/* Set RE (bit 15) in DACR */
@@ -79,7 +79,7 @@ int dram_init(void)
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
gd->ram_size = dramsize;
diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README
index 8a7d8cadf02..0de36a7f747 100644
--- a/board/freescale/m53017evb/README
+++ b/board/freescale/m53017evb/README
@@ -106,7 +106,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
index c9f89353ce4..76ebc0ab8dc 100644
--- a/board/freescale/m53017evb/m53017evb.c
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -29,7 +29,7 @@ int dram_init(void)
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,35 +37,35 @@ int dram_init(void)
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
-#ifdef CONFIG_SYS_SDRAM_BASE1
- out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+#ifdef CFG_SYS_SDRAM_BASE1
+ out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
#endif
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
asm("nop");
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
asm("nop");
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
asm("nop");
udelay(100);
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index 7a75b04dd0d..b278dbfb485 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -29,7 +29,7 @@ int dram_init(void)
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,30 +37,30 @@ int dram_init(void)
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README
index bba54202155..bfbcd5dc81d 100644
--- a/board/freescale/m5373evb/README
+++ b/board/freescale/m5373evb/README
@@ -105,7 +105,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
-CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index cfa5ca4a477..0e9eec316c2 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -29,7 +29,7 @@ int dram_init(void)
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
- dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+ dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,30 +37,30 @@ int dram_init(void)
}
i--;
- out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
- out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
- out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
+ out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
- out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
+ out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
- (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
+ (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 2650d300e38..85d43cccd1a 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -97,10 +97,10 @@ int dram_init(void)
int fixed_sdram(void)
{
immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_SDRAM_SIZE;
+ u32 msize = CFG_SYS_SDRAM_SIZE;
u32 msize_log2 = __ilog2(msize);
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
+ im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
@@ -127,7 +127,7 @@ int fixed_sdram(void)
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
udelay(2000);
- return CONFIG_SYS_SDRAM_SIZE >> 20;
+ return CFG_SYS_SDRAM_SIZE >> 20;
}
#endif /*!CONFIG_SYS_SPD_EEPROM */
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 46095acedfd..86364acf8ca 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 038e6736ace..f896fd7ccce 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -244,7 +244,7 @@ phys_size_t fixed_sdram(void)
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freq_ddrbus));
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-15 09:22:44 +0000