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-rw-r--r--board/phytec/phycore_am68x/phycore-am68x.c41
-rw-r--r--board/phytec/phycore_imx8mm/Kconfig65
-rw-r--r--board/phytec/phycore_imx8mm/lpddr4_timing.c1867
-rw-r--r--board/phytec/phycore_imx8mm/lpddr4_timing.h13
-rw-r--r--board/phytec/phycore_imx8mm/phycore-imx8mm.c18
-rw-r--r--board/phytec/phycore_imx8mm/spl.c56
6 files changed, 1100 insertions, 960 deletions
diff --git a/board/phytec/phycore_am68x/phycore-am68x.c b/board/phytec/phycore_am68x/phycore-am68x.c
index 312d7ece23e..9b71a4bdc68 100644
--- a/board/phytec/phycore_am68x/phycore-am68x.c
+++ b/board/phytec/phycore_am68x/phycore-am68x.c
@@ -21,6 +21,7 @@
#include <dm/uclass-internal.h>
#include <dm/root.h>
#include <asm/arch/k3-ddr.h>
+#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -69,6 +70,46 @@ void spl_perform_board_fixups(struct spl_image_info *spl_image)
}
#endif
+#define TPS6594_I2C_WD_ADDR 0x12
+#define WD_THR_CFG_REG 0x09
+#define WD_EN BIT(6)
+
+int tps6594_disable_watchdog(void)
+{
+ struct udevice *i2c_bus, *i2c_dev;
+ int ret;
+ u8 val;
+
+ ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@40b00000", &i2c_bus);
+ if (ret)
+ return ret;
+
+ ret = dm_i2c_probe(i2c_bus, TPS6594_I2C_WD_ADDR, 0, &i2c_dev);
+ if (ret)
+ return ret;
+
+ ret = dm_i2c_reg_read(i2c_dev, WD_THR_CFG_REG);
+ if (ret < 0)
+ return ret;
+
+ val = (u8)ret;
+ val &= ~WD_EN;
+ ret = dm_i2c_reg_write(i2c_dev, WD_THR_CFG_REG, val);
+
+ return ret;
+}
+
+int board_init(void)
+{
+ int ret;
+
+ ret = tps6594_disable_watchdog();
+ if (ret)
+ printf("disabling TPS6594 watchdog failed: %d\n", ret);
+
+ return 0;
+}
+
void spl_board_init(void)
{
struct udevice *dev;
diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig
index 06449128ba8..609c11580ce 100644
--- a/board/phytec/phycore_imx8mm/Kconfig
+++ b/board/phytec/phycore_imx8mm/Kconfig
@@ -12,5 +12,70 @@ config SYS_CONFIG_NAME
config IMX_CONFIG
default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg"
+config PHYCORE_IMX8MM_RAM_SIZE_FIX
+ bool "Set phyCORE-i.MX8MM RAM size fix instead of detecting"
+ default false
+ help
+ RAM size is automatic being detected with the help of
+ the EEPROM introspection data. Set RAM size to a fix value
+ instead.
+
+choice
+ prompt "phyCORE-i.MX8MM RAM size"
+ depends on PHYCORE_IMX8MM_RAM_SIZE_FIX
+ default PHYCORE_IMX8MM_RAM_SIZE_2GB
+ help
+ Select a fixed RAM size instead of EEPROM introspection
+ data.
+
+config PHYCORE_IMX8MM_RAM_SIZE_1GB
+ bool "1GB RAM"
+ help
+ Set RAM size fix to 1GB for phyCORE-i.MX8MM
+ instead of runtime detection from EEPROM.
+
+config PHYCORE_IMX8MM_RAM_SIZE_2GB
+ bool "2GB RAM"
+ help
+ Set RAM size fix to 2GB for phyCORE-i.MX8MM
+ instead of runtime detection from EEPROM.
+
+config PHYCORE_IMX8MM_RAM_SIZE_4GB
+ bool "4GB RAM"
+ help
+ Set RAM size fix to 4GB for phyCORE-i.MX8MM
+ instead of runtime detection from EEPROM.
+
+endchoice
+
+config PHYCORE_IMX8MM_RAM_STATIC_SOM_REV
+ bool "Set static phyCORE-i.MX8MM SoM revision for RAM timing setup"
+ default false
+ help
+ phyCORE-i.MX8MM SoM revision 7 uses a updated set of optimized
+ RAM timings compared to revision 6 and older. Set the SoM
+ revision during compile time instead of being detected.
+
+choice
+ prompt "phyCORE-i.MX8MM RAM timing SoM revision static config"
+ depends on PHYCORE_IMX8MM_RAM_STATIC_SOM_REV
+ default PHYCORE_IMX8MM_USE_SOM_REV_7
+ help
+ Use a fixed revision setting instead of runtime
+ auto detection.
+
+config PHYCORE_IMX8MM_USE_SOM_REV_6
+ bool "RAM Timings for SoM Revisions 6 and older"
+ help
+ Use optimized RAM Timings for phyCORE-i.MX8MM SoM Revisions 6
+ and older instead of autodetecting.
+
+config PHYCORE_IMX8MM_USE_SOM_REV_7
+ bool "RAM Timings for SoM Revision 7"
+ help
+ Use optimized RAM Timings for phyCORE-i.MX8MM SoM Revision 7
+ instead of autodetecting.
+endchoice
+
source "board/phytec/common/Kconfig"
endif
diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.c b/board/phytec/phycore_imx8mm/lpddr4_timing.c
index f5a2f3268b3..162b0209d92 100644
--- a/board/phytec/phycore_imx8mm/lpddr4_timing.c
+++ b/board/phytec/phycore_imx8mm/lpddr4_timing.c
@@ -1,16 +1,17 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2019 NXP
- * Copyright (C) 2023 PHYTEC Messtechnik GmbH
+ * Copyright 2025 NXP
+ * Copyright 2025 PHYTEC Messtechnik GmbH
*
- * Generated code from MX8M_DDR_tool
+ * Code partially generated with DDR Tool v3.6.0_22-aa018543.
+ * DDR PHY FW2017.09
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
+/* Initialize DDRC registers */
static struct dram_cfg_param ddr_ddrc_cfg[] = {
- /** Initialize DDRC registers **/
{0x3d400304, 0x1},
{0x3d400030, 0x1},
{0x3d400000, 0xa1080020},
@@ -20,9 +21,9 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d4000d0, 0xc00305ba},
{0x3d4000d4, 0x940000},
{0x3d4000dc, 0xd4002d},
- {0x3d4000e0, 0x310000},
- {0x3d4000e8, 0x66004d},
- {0x3d4000ec, 0x16004d},
+ {0x3d4000e0, 0xe10000},
+ {0x3d4000e8, 0x54004d},
+ {0x3d4000ec, 0x15004d},
{0x3d400100, 0x191e0c20},
{0x3d400104, 0x60630},
{0x3d40010c, 0xb0b000},
@@ -37,17 +38,17 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400180, 0x2ee0017},
{0x3d400184, 0x2605b8e},
{0x3d400188, 0x0},
- {0x3d400190, 0x497820a},
+ {0x3d400190, 0x49b820a},
{0x3d400194, 0x80303},
- {0x3d4001b4, 0x170a},
+ {0x3d4001b4, 0x1b0a},
{0x3d4001a0, 0xe0400018},
{0x3d4001a4, 0xdf00e4},
{0x3d4001a8, 0x80000000},
{0x3d4001b0, 0x11},
- {0x3d4001c0, 0x1},
+ {0x3d4001c0, 0x7},
{0x3d4001c4, 0x1},
{0x3d4000f4, 0x699},
- {0x3d400108, 0x70e1617},
+ {0x3d400108, 0x7101817},
{0x3d400200, 0x1f},
{0x3d40020c, 0x0},
{0x3d400210, 0x1f1f},
@@ -66,56 +67,6 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400498, 0x620096},
{0x3d40049c, 0x1100e07},
{0x3d4004a0, 0xc8012c},
- {0x3d402020, 0x20},
- {0x3d402024, 0x7d00},
- {0x3d402050, 0x20d040},
- {0x3d402064, 0x6001c},
- {0x3d4020dc, 0x840000},
- {0x3d4020e0, 0x310000},
- {0x3d4020e8, 0x66004d},
- {0x3d4020ec, 0x16004d},
- {0x3d402100, 0xa040105},
- {0x3d402104, 0x30407},
- {0x3d402108, 0x203060b},
- {0x3d40210c, 0x505000},
- {0x3d402110, 0x2040202},
- {0x3d402114, 0x2030202},
- {0x3d402118, 0x1010004},
- {0x3d40211c, 0x302},
- {0x3d402130, 0x20300},
- {0x3d402134, 0xa100002},
- {0x3d402138, 0x1d},
- {0x3d402144, 0x14000a},
- {0x3d402180, 0x640004},
- {0x3d402190, 0x3818200},
- {0x3d402194, 0x80303},
- {0x3d4021b4, 0x100},
- {0x3d4020f4, 0x599},
- {0x3d403020, 0x20},
- {0x3d403024, 0x1f40},
- {0x3d403050, 0x20d040},
- {0x3d403064, 0x30007},
- {0x3d4030dc, 0x840000},
- {0x3d4030e0, 0x310000},
- {0x3d4030e8, 0x66004d},
- {0x3d4030ec, 0x16004d},
- {0x3d403100, 0xa010102},
- {0x3d403104, 0x30404},
- {0x3d403108, 0x203060b},
- {0x3d40310c, 0x505000},
- {0x3d403110, 0x2040202},
- {0x3d403114, 0x2030202},
- {0x3d403118, 0x1010004},
- {0x3d40311c, 0x302},
- {0x3d403130, 0x20300},
- {0x3d403134, 0xa100002},
- {0x3d403138, 0x8},
- {0x3d403144, 0x50003},
- {0x3d403180, 0x190004},
- {0x3d403190, 0x3818200},
- {0x3d403194, 0x80303},
- {0x3d4031b4, 0x100},
- {0x3d4030f4, 0x599},
{0x3d400028, 0x0},
};
@@ -161,22 +112,6 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x1215f, 0x1ff},
{0x1305f, 0x1ff},
{0x1315f, 0x1ff},
- {0x11005f, 0x1ff},
- {0x11015f, 0x1ff},
- {0x11105f, 0x1ff},
- {0x11115f, 0x1ff},
- {0x11205f, 0x1ff},
- {0x11215f, 0x1ff},
- {0x11305f, 0x1ff},
- {0x11315f, 0x1ff},
- {0x21005f, 0x1ff},
- {0x21015f, 0x1ff},
- {0x21105f, 0x1ff},
- {0x21115f, 0x1ff},
- {0x21205f, 0x1ff},
- {0x21215f, 0x1ff},
- {0x21305f, 0x1ff},
- {0x21315f, 0x1ff},
{0x55, 0x1ff},
{0x1055, 0x1ff},
{0x2055, 0x1ff},
@@ -188,87 +123,41 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x8055, 0x1ff},
{0x9055, 0x1ff},
{0x200c5, 0x19},
- {0x1200c5, 0x7},
- {0x2200c5, 0x7},
{0x2002e, 0x2},
- {0x12002e, 0x2},
- {0x22002e, 0x2},
{0x90204, 0x0},
- {0x190204, 0x0},
- {0x290204, 0x0},
{0x20024, 0x1ab},
{0x2003a, 0x0},
- {0x120024, 0x1ab},
- {0x2003a, 0x0},
- {0x220024, 0x1ab},
- {0x2003a, 0x0},
{0x20056, 0x3},
- {0x120056, 0x3},
- {0x220056, 0x3},
- {0x1004d, 0xe00},
- {0x1014d, 0xe00},
- {0x1104d, 0xe00},
- {0x1114d, 0xe00},
- {0x1204d, 0xe00},
- {0x1214d, 0xe00},
- {0x1304d, 0xe00},
- {0x1314d, 0xe00},
- {0x11004d, 0xe00},
- {0x11014d, 0xe00},
- {0x11104d, 0xe00},
- {0x11114d, 0xe00},
- {0x11204d, 0xe00},
- {0x11214d, 0xe00},
- {0x11304d, 0xe00},
- {0x11314d, 0xe00},
- {0x21004d, 0xe00},
- {0x21014d, 0xe00},
- {0x21104d, 0xe00},
- {0x21114d, 0xe00},
- {0x21204d, 0xe00},
- {0x21214d, 0xe00},
- {0x21304d, 0xe00},
- {0x21314d, 0xe00},
- {0x10049, 0xeba},
- {0x10149, 0xeba},
- {0x11049, 0xeba},
- {0x11149, 0xeba},
- {0x12049, 0xeba},
- {0x12149, 0xeba},
- {0x13049, 0xeba},
- {0x13149, 0xeba},
- {0x110049, 0xeba},
- {0x110149, 0xeba},
- {0x111049, 0xeba},
- {0x111149, 0xeba},
- {0x112049, 0xeba},
- {0x112149, 0xeba},
- {0x113049, 0xeba},
- {0x113149, 0xeba},
- {0x210049, 0xeba},
- {0x210149, 0xeba},
- {0x211049, 0xeba},
- {0x211149, 0xeba},
- {0x212049, 0xeba},
- {0x212149, 0xeba},
- {0x213049, 0xeba},
- {0x213149, 0xeba},
- {0x43, 0x63},
- {0x1043, 0x63},
- {0x2043, 0x63},
- {0x3043, 0x63},
- {0x4043, 0x63},
- {0x5043, 0x63},
- {0x6043, 0x63},
- {0x7043, 0x63},
- {0x8043, 0x63},
- {0x9043, 0x63},
+ {0x1004d, 0x680},
+ {0x1014d, 0x680},
+ {0x1104d, 0x680},
+ {0x1114d, 0x680},
+ {0x1204d, 0x680},
+ {0x1214d, 0x680},
+ {0x1304d, 0x680},
+ {0x1314d, 0x680},
+ {0x10049, 0x28a},
+ {0x10149, 0x28a},
+ {0x11049, 0x28a},
+ {0x11149, 0x28a},
+ {0x12049, 0x28a},
+ {0x12149, 0x28a},
+ {0x13049, 0x28a},
+ {0x13149, 0x28a},
+ {0x43, 0x21},
+ {0x1043, 0x21},
+ {0x2043, 0x21},
+ {0x3043, 0x21},
+ {0x4043, 0x21},
+ {0x5043, 0x21},
+ {0x6043, 0x21},
+ {0x7043, 0x21},
+ {0x8043, 0x21},
+ {0x9043, 0x21},
{0x20018, 0x3},
{0x20075, 0x4},
{0x20050, 0x0},
{0x20008, 0x2ee},
- {0x120008, 0x64},
- {0x220008, 0x19},
{0x20088, 0x9},
{0x200b2, 0xdc},
{0x10043, 0x5a1},
@@ -279,618 +168,864 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x12143, 0x5a1},
{0x13043, 0x5a1},
{0x13143, 0x5a1},
- {0x1200b2, 0xdc},
- {0x110043, 0x5a1},
- {0x110143, 0x5a1},
- {0x111043, 0x5a1},
- {0x111143, 0x5a1},
- {0x112043, 0x5a1},
- {0x112143, 0x5a1},
- {0x113043, 0x5a1},
- {0x113143, 0x5a1},
- {0x2200b2, 0xdc},
- {0x210043, 0x5a1},
- {0x210143, 0x5a1},
- {0x211043, 0x5a1},
- {0x211143, 0x5a1},
- {0x212043, 0x5a1},
- {0x212143, 0x5a1},
- {0x213043, 0x5a1},
- {0x213143, 0x5a1},
{0x200fa, 0x1},
- {0x1200fa, 0x1},
- {0x2200fa, 0x1},
{0x20019, 0x1},
- {0x120019, 0x1},
- {0x220019, 0x1},
- {0x200f0, 0x660},
+ {0x200f0, 0x0},
{0x200f1, 0x0},
{0x200f2, 0x4444},
{0x200f3, 0x8888},
- {0x200f4, 0x5665},
+ {0x200f4, 0x5555},
{0x200f5, 0x0},
{0x200f6, 0x0},
{0x200f7, 0xf000},
{0x20025, 0x0},
- {0x2002d, 0x0},
- {0x12002d, 0x0},
- {0x22002d, 0x0},
- {0x200c7, 0x21},
- {0x1200c7, 0x21},
- {0x2200c7, 0x21},
+ {0x2002d, 0x1},
{0x200ca, 0x24},
{0x1200ca, 0x24},
{0x2200ca, 0x24},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
};
-/* ddr phy trained csr */
+/* PHY trained csr */
static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ {0x1005f, 0x0},
+ {0x1015f, 0x0},
+ {0x1105f, 0x0},
+ {0x1115f, 0x0},
+ {0x1205f, 0x0},
+ {0x1215f, 0x0},
+ {0x1305f, 0x0},
+ {0x1315f, 0x0},
+ {0x55, 0x0},
+ {0x1055, 0x0},
+ {0x2055, 0x0},
+ {0x3055, 0x0},
+ {0x4055, 0x0},
+ {0x5055, 0x0},
+ {0x6055, 0x0},
+ {0x7055, 0x0},
+ {0x8055, 0x0},
+ {0x9055, 0x0},
+ {0x200c5, 0x0},
+ {0x2002e, 0x0},
+ {0x90204, 0x0},
+ {0x20024, 0x0},
+ {0x2003a, 0x0},
+ {0x20056, 0x0},
+ {0x1004d, 0x0},
+ {0x1014d, 0x0},
+ {0x1104d, 0x0},
+ {0x1114d, 0x0},
+ {0x1204d, 0x0},
+ {0x1214d, 0x0},
+ {0x1304d, 0x0},
+ {0x1314d, 0x0},
+ {0x10049, 0x0},
+ {0x10149, 0x0},
+ {0x11049, 0x0},
+ {0x11149, 0x0},
+ {0x12049, 0x0},
+ {0x12149, 0x0},
+ {0x13049, 0x0},
+ {0x13149, 0x0},
+ {0x43, 0x0},
+ {0x1043, 0x0},
+ {0x2043, 0x0},
+ {0x3043, 0x0},
+ {0x4043, 0x0},
+ {0x5043, 0x0},
+ {0x6043, 0x0},
+ {0x7043, 0x0},
+ {0x8043, 0x0},
+ {0x9043, 0x0},
+ {0x20018, 0x0},
+ {0x20075, 0x0},
+ {0x20050, 0x0},
+ {0x20008, 0x0},
+ {0x20088, 0x0},
{0x200b2, 0x0},
- {0x1200b2, 0x0},
- {0x2200b2, 0x0},
- {0x200cb, 0x0},
{0x10043, 0x0},
- {0x110043, 0x0},
- {0x210043, 0x0},
{0x10143, 0x0},
- {0x110143, 0x0},
- {0x210143, 0x0},
{0x11043, 0x0},
- {0x111043, 0x0},
- {0x211043, 0x0},
{0x11143, 0x0},
- {0x111143, 0x0},
- {0x211143, 0x0},
{0x12043, 0x0},
- {0x112043, 0x0},
- {0x212043, 0x0},
{0x12143, 0x0},
- {0x112143, 0x0},
- {0x212143, 0x0},
{0x13043, 0x0},
- {0x113043, 0x0},
- {0x213043, 0x0},
{0x13143, 0x0},
- {0x113143, 0x0},
- {0x213143, 0x0},
+ {0x200fa, 0x0},
+ {0x20019, 0x0},
+ {0x200f0, 0x0},
+ {0x200f1, 0x0},
+ {0x200f2, 0x0},
+ {0x200f3, 0x0},
+ {0x200f4, 0x0},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0x0},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0xd0000, 0x0},
+ {0x90000, 0x0},
+ {0x90001, 0x0},
+ {0x90002, 0x0},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x0},
+ {0x90029, 0x0},
+ {0x9002a, 0x0},
+ {0x9002b, 0x0},
+ {0x9002c, 0x0},
+ {0x9002d, 0x0},
+ {0x9002e, 0x0},
+ {0x9002f, 0x0},
+ {0x90030, 0x0},
+ {0x90031, 0x0},
+ {0x90032, 0x0},
+ {0x90033, 0x0},
+ {0x90034, 0x0},
+ {0x90035, 0x0},
+ {0x90036, 0x0},
+ {0x90037, 0x0},
+ {0x90038, 0x0},
+ {0x90039, 0x0},
+ {0x9003a, 0x0},
+ {0x9003b, 0x0},
+ {0x9003c, 0x0},
+ {0x9003d, 0x0},
+ {0x9003e, 0x0},
+ {0x9003f, 0x0},
+ {0x90040, 0x0},
+ {0x90041, 0x0},
+ {0x90042, 0x0},
+ {0x90043, 0x0},
+ {0x90044, 0x0},
+ {0x90045, 0x0},
+ {0x90046, 0x0},
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- {0x110a5, 0x0},
- {0x110a6, 0x0},
- {0x110a7, 0x0},
- {0x120a0, 0x0},
- {0x120a1, 0x0},
- {0x120a2, 0x0},
- {0x120a3, 0x0},
- {0x120a4, 0x0},
- {0x120a5, 0x0},
- {0x120a6, 0x0},
- {0x120a7, 0x0},
{0x130a0, 0x0},
{0x130a1, 0x0},
{0x130a2, 0x0},
@@ -899,306 +1034,108 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x130a5, 0x0},
{0x130a6, 0x0},
{0x130a7, 0x0},
- {0x2007c, 0x0},
- {0x12007c, 0x0},
- {0x22007c, 0x0},
- {0x2007d, 0x0},
- {0x12007d, 0x0},
- {0x22007d, 0x0},
- {0x400fd, 0x0},
- {0x400c0, 0x0},
{0x90201, 0x0},
- {0x190201, 0x0},
- {0x290201, 0x0},
{0x90202, 0x0},
- {0x190202, 0x0},
- {0x290202, 0x0},
{0x90203, 0x0},
- {0x190203, 0x0},
- {0x290203, 0x0},
- {0x90204, 0x0},
- {0x190204, 0x0},
- {0x290204, 0x0},
{0x90205, 0x0},
- {0x190205, 0x0},
- {0x290205, 0x0},
{0x90206, 0x0},
- {0x190206, 0x0},
- {0x290206, 0x0},
{0x90207, 0x0},
- {0x190207, 0x0},
- {0x290207, 0x0},
{0x90208, 0x0},
- {0x190208, 0x0},
- {0x290208, 0x0},
- {0x10062, 0x0},
- {0x10162, 0x0},
- {0x10262, 0x0},
- {0x10362, 0x0},
- {0x10462, 0x0},
- {0x10562, 0x0},
- {0x10662, 0x0},
- {0x10762, 0x0},
- {0x10862, 0x0},
- {0x11062, 0x0},
- {0x11162, 0x0},
- {0x11262, 0x0},
- {0x11362, 0x0},
- {0x11462, 0x0},
- {0x11562, 0x0},
- {0x11662, 0x0},
- {0x11762, 0x0},
- {0x11862, 0x0},
- {0x12062, 0x0},
- {0x12162, 0x0},
- {0x12262, 0x0},
- {0x12362, 0x0},
- {0x12462, 0x0},
- {0x12562, 0x0},
- {0x12662, 0x0},
- {0x12762, 0x0},
- {0x12862, 0x0},
- {0x13062, 0x0},
- {0x13162, 0x0},
- {0x13262, 0x0},
- {0x13362, 0x0},
- {0x13462, 0x0},
- {0x13562, 0x0},
- {0x13662, 0x0},
- {0x13762, 0x0},
- {0x13862, 0x0},
+ {0x2007c, 0x0},
+ {0x2007d, 0x0},
+ {0x20020, 0x0},
+ {0x20072, 0x0},
+ {0x20073, 0x0},
{0x20077, 0x0},
- {0x10001, 0x0},
- {0x11001, 0x0},
- {0x12001, 0x0},
- {0x13001, 0x0},
+ {0x400c0, 0x0},
{0x10040, 0x0},
{0x10140, 0x0},
- {0x10240, 0x0},
- {0x10340, 0x0},
- {0x10440, 0x0},
- {0x10540, 0x0},
- {0x10640, 0x0},
- {0x10740, 0x0},
- {0x10840, 0x0},
- {0x10030, 0x0},
- {0x10130, 0x0},
- {0x10230, 0x0},
- {0x10330, 0x0},
- {0x10430, 0x0},
- {0x10530, 0x0},
- {0x10630, 0x0},
- {0x10730, 0x0},
- {0x10830, 0x0},
{0x11040, 0x0},
{0x11140, 0x0},
- {0x11240, 0x0},
- {0x11340, 0x0},
- {0x11440, 0x0},
- {0x11540, 0x0},
- {0x11640, 0x0},
- {0x11740, 0x0},
- {0x11840, 0x0},
- {0x11030, 0x0},
- {0x11130, 0x0},
- {0x11230, 0x0},
- {0x11330, 0x0},
- {0x11430, 0x0},
- {0x11530, 0x0},
- {0x11630, 0x0},
- {0x11730, 0x0},
- {0x11830, 0x0},
{0x12040, 0x0},
{0x12140, 0x0},
- {0x12240, 0x0},
- {0x12340, 0x0},
- {0x12440, 0x0},
- {0x12540, 0x0},
- {0x12640, 0x0},
- {0x12740, 0x0},
- {0x12840, 0x0},
- {0x12030, 0x0},
- {0x12130, 0x0},
- {0x12230, 0x0},
- {0x12330, 0x0},
- {0x12430, 0x0},
- {0x12530, 0x0},
- {0x12630, 0x0},
- {0x12730, 0x0},
- {0x12830, 0x0},
{0x13040, 0x0},
{0x13140, 0x0},
- {0x13240, 0x0},
- {0x13340, 0x0},
- {0x13440, 0x0},
- {0x13540, 0x0},
- {0x13640, 0x0},
- {0x13740, 0x0},
- {0x13840, 0x0},
- {0x13030, 0x0},
- {0x13130, 0x0},
- {0x13230, 0x0},
- {0x13330, 0x0},
- {0x13430, 0x0},
- {0x13530, 0x0},
- {0x13630, 0x0},
- {0x13730, 0x0},
- {0x13830, 0x0},
};
-/* P0 message block paremeter for training firmware */
-struct dram_cfg_param ddr_fsp0_cfg[] = {
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
{0xd0000, 0x0},
{0x54003, 0xbb8},
{0x54004, 0x2},
- {0x54005, 0x2228},
+ {0x54005, 0x5030},
{0x54006, 0x11},
{0x54008, 0x131f},
{0x54009, 0xc8},
{0x5400b, 0x2},
{0x54012, 0x110},
{0x54019, 0x2dd4},
- {0x5401a, 0x31},
- {0x5401b, 0x4d66},
+ {0x5401a, 0xe1},
+ {0x5401b, 0x4d54},
{0x5401c, 0x4d00},
- {0x5401e, 0x16},
+ {0x5401e, 0x15},
{0x5401f, 0x2dd4},
- {0x54020, 0x31},
- {0x54021, 0x4d66},
+ {0x54020, 0xe1},
+ {0x54021, 0x4d54},
{0x54022, 0x4d00},
- {0x54024, 0x16},
+ {0x54024, 0x15},
{0x5402b, 0x1000},
{0x5402c, 0x1},
{0x54032, 0xd400},
- {0x54033, 0x312d},
- {0x54034, 0x6600},
+ {0x54033, 0xe12d},
+ {0x54034, 0x5400},
{0x54035, 0x4d},
{0x54036, 0x4d},
- {0x54037, 0x1600},
+ {0x54037, 0x1500},
{0x54038, 0xd400},
- {0x54039, 0x312d},
- {0x5403a, 0x6600},
- {0x5403b, 0x4d},
- {0x5403c, 0x4d},
- {0x5403d, 0x1600},
- {0xd0000, 0x1},
-};
-
-/* P1 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp1_cfg[] = {
- {0xd0000, 0x0},
- {0x54002, 0x101},
- {0x54003, 0x190},
- {0x54004, 0x2},
- {0x54005, 0x2228},
- {0x54006, 0x11},
- {0x54008, 0x121f},
- {0x54009, 0xc8},
- {0x5400b, 0x2},
- {0x54012, 0x110},
- {0x54019, 0x84},
- {0x5401a, 0x31},
- {0x5401b, 0x4d66},
- {0x5401c, 0x4d00},
- {0x5401e, 0x16},
- {0x5401f, 0x84},
- {0x54020, 0x31},
- {0x54021, 0x4d66},
- {0x54022, 0x4d00},
- {0x54024, 0x16},
- {0x5402b, 0x1000},
- {0x5402c, 0x1},
- {0x54032, 0x8400},
- {0x54033, 0x3100},
- {0x54034, 0x6600},
- {0x54035, 0x4d},
- {0x54036, 0x4d},
- {0x54037, 0x1600},
- {0x54038, 0x8400},
- {0x54039, 0x3100},
- {0x5403a, 0x6600},
+ {0x54039, 0xe12d},
+ {0x5403a, 0x5400},
{0x5403b, 0x4d},
{0x5403c, 0x4d},
- {0x5403d, 0x1600},
- {0xd0000, 0x1},
+ {0x5403d, 0x1500},
+ {0xd0000, 0x1}
};
-/* P2 message block paremeter for training firmware */
-static struct dram_cfg_param ddr_fsp2_cfg[] = {
- {0xd0000, 0x0},
- {0x54002, 0x102},
- {0x54003, 0x64},
- {0x54004, 0x2},
- {0x54005, 0x2228},
- {0x54006, 0x11},
- {0x54008, 0x121f},
- {0x54009, 0xc8},
- {0x5400b, 0x2},
- {0x54012, 0x110},
- {0x54019, 0x84},
- {0x5401a, 0x31},
- {0x5401b, 0x4d66},
- {0x5401c, 0x4d00},
- {0x5401e, 0x16},
- {0x5401f, 0x84},
- {0x54020, 0x31},
- {0x54021, 0x4d66},
- {0x54022, 0x4d00},
- {0x54024, 0x16},
- {0x5402b, 0x1000},
- {0x5402c, 0x1},
- {0x54032, 0x8400},
- {0x54033, 0x3100},
- {0x54034, 0x6600},
- {0x54035, 0x4d},
- {0x54036, 0x4d},
- {0x54037, 0x1600},
- {0x54038, 0x8400},
- {0x54039, 0x3100},
- {0x5403a, 0x6600},
- {0x5403b, 0x4d},
- {0x5403c, 0x4d},
- {0x5403d, 0x1600},
- {0xd0000, 0x1},
-};
-/* P0 2D message block paremeter for training firmware */
+/* P0 2D message block parameter for training firmware */
static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0xd0000, 0x0},
{0x54003, 0xbb8},
{0x54004, 0x2},
- {0x54005, 0x2228},
+ {0x54005, 0x5030},
{0x54006, 0x11},
{0x54008, 0x61},
{0x54009, 0xc8},
{0x5400b, 0x2},
+ {0x5400d, 0x100},
{0x5400f, 0x100},
{0x54010, 0x1f7f},
{0x54012, 0x110},
{0x54019, 0x2dd4},
- {0x5401a, 0x31},
- {0x5401b, 0x4d66},
+ {0x5401a, 0xe1},
+ {0x5401b, 0x4d54},
{0x5401c, 0x4d00},
- {0x5401e, 0x16},
+ {0x5401e, 0x15},
{0x5401f, 0x2dd4},
- {0x54020, 0x31},
- {0x54021, 0x4d66},
+ {0x54020, 0xe1},
+ {0x54021, 0x4d54},
{0x54022, 0x4d00},
- {0x54024, 0x16},
+ {0x54024, 0x15},
{0x5402b, 0x1000},
{0x5402c, 0x1},
{0x54032, 0xd400},
- {0x54033, 0x312d},
- {0x54034, 0x6600},
+ {0x54033, 0xe12d},
+ {0x54034, 0x5400},
{0x54035, 0x4d},
{0x54036, 0x4d},
- {0x54037, 0x1600},
+ {0x54037, 0x1500},
{0x54038, 0xd400},
- {0x54039, 0x312d},
- {0x5403a, 0x6600},
+ {0x54039, 0xe12d},
+ {0x5403a, 0x5400},
{0x5403b, 0x4d},
{0x5403c, 0x4d},
- {0x5403d, 0x1600},
- {0xd0000, 0x1},
+ {0x5403d, 0x1500},
+ {0xd0000, 0x1}
};
/* DRAM PHY init engine image */
@@ -1691,18 +1628,10 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{0x400d6, 0x20a},
{0x400d7, 0x20b},
{0x2003a, 0x2},
- {0x2000b, 0x34b},
+ {0x2000b, 0x5d},
{0x2000c, 0xbb},
{0x2000d, 0x753},
{0x2000e, 0x2c},
- {0x12000b, 0x70},
- {0x12000c, 0x19},
- {0x12000d, 0xfa},
- {0x12000e, 0x10},
- {0x22000b, 0x1c},
- {0x22000c, 0x6},
- {0x22000d, 0x3e},
- {0x22000e, 0x10},
{0x9000c, 0x0},
{0x9000d, 0x173},
{0x9000e, 0x60},
@@ -1713,28 +1642,12 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{0x90013, 0x6152},
{0x20010, 0x5a},
{0x20011, 0x3},
- {0x120010, 0x5a},
- {0x120011, 0x3},
- {0x220010, 0x5a},
- {0x220011, 0x3},
{0x40080, 0xe0},
{0x40081, 0x12},
{0x40082, 0xe0},
{0x40083, 0x12},
{0x40084, 0xe0},
{0x40085, 0x12},
- {0x140080, 0xe0},
- {0x140081, 0x12},
- {0x140082, 0xe0},
- {0x140083, 0x12},
- {0x140084, 0xe0},
- {0x140085, 0x12},
- {0x240080, 0xe0},
- {0x240081, 0x12},
- {0x240082, 0xe0},
- {0x240083, 0x12},
- {0x240084, 0xe0},
- {0x240085, 0x12},
{0x400fd, 0xf},
{0x10011, 0x1},
{0x10012, 0x1},
@@ -1794,7 +1707,7 @@ static struct dram_cfg_param ddr_phy_pie[] = {
{0x138b4, 0x1},
{0x2003a, 0x2},
{0xc0080, 0x2},
- {0xd0000, 0x1}
+ {0xd0000, 0x1},
};
static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
@@ -1806,20 +1719,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
},
{
- /* P1 400mts 1D */
- .drate = 400,
- .fw_type = FW_1D_IMAGE,
- .fsp_cfg = ddr_fsp1_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
- },
- {
- /* P2 100mts 1D */
- .drate = 100,
- .fw_type = FW_1D_IMAGE,
- .fsp_cfg = ddr_fsp2_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
- },
- {
/* P0 3000mts 2D */
.drate = 3000,
.fw_type = FW_2D_IMAGE,
@@ -1840,5 +1739,55 @@ struct dram_timing_info dram_timing = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100,},
+ .fsp_table = { 3000, },
};
+
+void set_dram_timings_1gb(void)
+{
+ dram_timing.ddrc_cfg[5].val = 0x2d0087;
+ dram_timing.ddrc_cfg[21].val = 0x8d;
+ dram_timing.ddrc_cfg[42].val = 0xf070707;
+}
+
+void set_dram_timings_4gb(void)
+{
+ dram_timing.ddrc_cfg[2].val = 0xa3080020;
+ dram_timing.ddrc_cfg[37].val = 0x17;
+ dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x310;
+ dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x3;
+ dram_timing.fsp_msg[1].fsp_cfg[11].val = 0x310;
+ dram_timing.fsp_msg[1].fsp_cfg[23].val = 0x3;
+}
+
+void set_dram_timings_rev7(void)
+{
+ dram_timing.ddrc_cfg[10].val = 0x55004d;
+ dram_timing.ddrphy_cfg[64].val = 0x618;
+ dram_timing.ddrphy_cfg[65].val = 0x618;
+ dram_timing.ddrphy_cfg[66].val = 0x618;
+ dram_timing.ddrphy_cfg[67].val = 0x618;
+ dram_timing.ddrphy_cfg[68].val = 0x618;
+ dram_timing.ddrphy_cfg[69].val = 0x618;
+ dram_timing.ddrphy_cfg[70].val = 0x618;
+ dram_timing.ddrphy_cfg[71].val = 0x618;
+ dram_timing.ddrphy_cfg[72].val = 0x63;
+ dram_timing.ddrphy_cfg[73].val = 0x63;
+ dram_timing.ddrphy_cfg[74].val = 0x63;
+ dram_timing.ddrphy_cfg[75].val = 0x63;
+ dram_timing.ddrphy_cfg[76].val = 0x63;
+ dram_timing.ddrphy_cfg[77].val = 0x63;
+ dram_timing.ddrphy_cfg[78].val = 0x63;
+ dram_timing.ddrphy_cfg[79].val = 0x63;
+ dram_timing.ddrphy_cfg[80].val = 0x63;
+ dram_timing.ddrphy_cfg[81].val = 0x63;
+ dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x3c30;
+ dram_timing.fsp_msg[0].fsp_cfg[11].val = 0x4d55;
+ dram_timing.fsp_msg[0].fsp_cfg[16].val = 0x4d55;
+ dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x5500;
+ dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x5500;
+ dram_timing.fsp_msg[1].fsp_cfg[3].val = 0x3c30;
+ dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x4d55;
+ dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x4d55;
+ dram_timing.fsp_msg[1].fsp_cfg[26].val = 0x5500;
+ dram_timing.fsp_msg[1].fsp_cfg[32].val = 0x5500;
+}
diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.h b/board/phytec/phycore_imx8mm/lpddr4_timing.h
new file mode 100644
index 00000000000..340fefe01c3
--- /dev/null
+++ b/board/phytec/phycore_imx8mm/lpddr4_timing.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+void set_dram_timings_1gb(void);
+void set_dram_timings_4gb(void);
+void set_dram_timings_rev7(void);
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c
index 9f6a4ec704d..25e51dce739 100644
--- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c
+++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c
@@ -9,6 +9,7 @@
#include <asm/mach-imx/boot_mode.h>
#include <env.h>
#include <miiphy.h>
+#include <init.h>
static int setup_fec(void)
{
@@ -50,3 +51,20 @@ int board_late_init(void)
return 0;
}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ if (!size)
+ return -EINVAL;
+
+ /*
+ * check various RAM sizes (1, 2 and 4 GB) otherwise
+ * return the default of 2GB
+ */
+ *size = get_ram_size((void *)PHYS_SDRAM,
+ (long)PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
+ if (*size == 0)
+ *size = SZ_2G;
+
+ return 0;
+}
diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c
index e688793bc74..a3879881eb7 100644
--- a/board/phytec/phycore_imx8mm/spl.c
+++ b/board/phytec/phycore_imx8mm/spl.c
@@ -16,11 +16,19 @@
#include <log.h>
#include <spl.h>
+#include "lpddr4_timing.h"
#include "../common/imx8m_som_detection.h"
#define EEPROM_ADDR 0x51
#define EEPROM_ADDR_FALLBACK 0x59
+enum phytec_imx8mm_ddr_eeprom_code {
+ INVALID = PHYTEC_EEPROM_INVAL,
+ PHYTEC_IMX8MM_DDR_1GB = 1,
+ PHYTEC_IMX8MM_DDR_2GB = 3,
+ PHYTEC_IMX8MM_DDR_4GB = 5,
+};
+
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
@@ -42,17 +50,63 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
static void spl_dram_init(void)
{
int ret;
+ enum phytec_imx8mm_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL;
+ u8 rev = PHYTEC_EEPROM_INVAL;
ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
EEPROM_ADDR_FALLBACK);
- if (ret)
+ if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_FIX))
goto out;
ret = phytec_imx8m_detect(NULL);
if (!ret)
phytec_print_som_info(NULL);
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_FIX)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_1GB))
+ size = PHYTEC_IMX8MM_DDR_1GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_2GB))
+ size = PHYTEC_IMX8MM_DDR_2GB;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_4GB))
+ size = PHYTEC_IMX8MM_DDR_4GB;
+ } else {
+ size = phytec_get_imx8m_ddr_size(NULL);
+ }
+
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_STATIC_SOM_REV)) {
+ if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_USE_SOM_REV_6))
+ rev = 6;
+ else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_USE_SOM_REV_7))
+ rev = 7;
+ } else {
+ rev = phytec_get_rev(NULL);
+ }
+
+ if (rev >= 7 || rev == PHYTEC_EEPROM_INVAL) {
+ debug("%s: Using rev7 RAM timings.\n", __func__);
+ set_dram_timings_rev7();
+ } else {
+ debug("%s: Using rev6 RAM timings.\n", __func__);
+ }
+
+ switch (size) {
+ case PHYTEC_IMX8MM_DDR_1GB:
+ set_dram_timings_1gb();
+ break;
+ case PHYTEC_IMX8MM_DDR_2GB:
+ break;
+ case PHYTEC_IMX8MM_DDR_4GB:
+ set_dram_timings_4gb();
+ break;
+ default:
+ goto out;
+ }
+ ddr_init(&dram_timing);
+
+ return;
out:
+ puts("Could not detect correct RAM size. Fall back to default.\n");
+ set_dram_timings_rev7();
ddr_init(&dram_timing);
}
generated by cgit v1.3.1 (git 2.54.0) at 2026-09-03 15:22:42 +0000