diff options
Diffstat (limited to 'board')
61 files changed, 1449 insertions, 548 deletions
diff --git a/board/adi/carriers/somcrr_ezkit.c b/board/adi/carriers/somcrr_ezkit.c index 8b4d6a96c18..3cd5a6cd10b 100644 --- a/board/adi/carriers/somcrr_ezkit.c +++ b/board/adi/carriers/somcrr_ezkit.c @@ -13,13 +13,12 @@ void adi_somcrr_enable_ethernet(void) struct gpio_desc *eth1_reset; struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth1-en", ð1); - gpio_hog_lookup_name("eth1-reset", ð1_reset); - gpio_hog_lookup_name("gige-reset", &gige_reset); - - dm_gpio_set_value(eth1, 1); - dm_gpio_set_value(eth1_reset, 0); - dm_gpio_set_value(gige_reset, 0); + if (!gpio_hog_lookup_name("eth1-en", ð1)) + dm_gpio_set_value(eth1, 1); + if (!gpio_hog_lookup_name("eth1-reset", ð1_reset)) + dm_gpio_set_value(eth1_reset, 0); + if (!gpio_hog_lookup_name("gige-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 0); } void adi_somcrr_disable_ethernet(void) @@ -28,11 +27,10 @@ void adi_somcrr_disable_ethernet(void) struct gpio_desc *eth1_reset; struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth1-en", ð1); - gpio_hog_lookup_name("eth1-reset", ð1_reset); - gpio_hog_lookup_name("gige-reset", &gige_reset); - - dm_gpio_set_value(eth1, 0); - dm_gpio_set_value(eth1_reset, 1); - dm_gpio_set_value(gige_reset, 1); + if (!gpio_hog_lookup_name("eth1-en", ð1)) + dm_gpio_set_value(eth1, 0); + if (!gpio_hog_lookup_name("eth1-reset", ð1_reset)) + dm_gpio_set_value(eth1_reset, 1); + if (!gpio_hog_lookup_name("gige-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 1); } diff --git a/board/adi/carriers/somcrr_ezlite.c b/board/adi/carriers/somcrr_ezlite.c index c0655574bab..1f1984cf912 100644 --- a/board/adi/carriers/somcrr_ezlite.c +++ b/board/adi/carriers/somcrr_ezlite.c @@ -11,14 +11,14 @@ void adi_somcrr_enable_ethernet(void) { struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth0-reset", &gige_reset); - dm_gpio_set_value(gige_reset, 0); + if (!gpio_hog_lookup_name("eth0-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 0); } void adi_somcrr_disable_ethernet(void) { struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth0-reset", &gige_reset); - dm_gpio_set_value(gige_reset, 1); + if (!gpio_hog_lookup_name("eth0-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 1); } diff --git a/board/atmel/at91sam9m10g45ek/MAINTAINERS b/board/atmel/at91sam9m10g45ek/MAINTAINERS index 54632c36d6e..4a3dcd402dd 100644 --- a/board/atmel/at91sam9m10g45ek/MAINTAINERS +++ b/board/atmel/at91sam9m10g45ek/MAINTAINERS @@ -1,5 +1,5 @@ AT91SAM9M10G45EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/at91sam9m10g45ek/ F: include/configs/at91sam9m10g45ek.h diff --git a/board/atmel/at91sam9n12ek/MAINTAINERS b/board/atmel/at91sam9n12ek/MAINTAINERS index 0d33340d87a..86781af2e7e 100644 --- a/board/atmel/at91sam9n12ek/MAINTAINERS +++ b/board/atmel/at91sam9n12ek/MAINTAINERS @@ -1,5 +1,5 @@ AT91SAM9N12EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/at91sam9n12ek/ F: include/configs/at91sam9n12ek.h diff --git a/board/atmel/at91sam9x5ek/MAINTAINERS b/board/atmel/at91sam9x5ek/MAINTAINERS index 51d2237ee6c..33c102bf7b3 100644 --- a/board/atmel/at91sam9x5ek/MAINTAINERS +++ b/board/atmel/at91sam9x5ek/MAINTAINERS @@ -1,5 +1,5 @@ AT91SAM9X5EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/at91sam9x5ek/ F: include/configs/at91sam9x5ek.h diff --git a/board/atmel/sam9x60_curiosity/MAINTAINERS b/board/atmel/sam9x60_curiosity/MAINTAINERS index 0d9369e0272..519aca696de 100644 --- a/board/atmel/sam9x60_curiosity/MAINTAINERS +++ b/board/atmel/sam9x60_curiosity/MAINTAINERS @@ -1,6 +1,6 @@ SAM9X60 CURIOSITY BOARD M: Durai Manickam KR <[email protected]> -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sam9x60_curiosity/ F: include/configs/sam9x60_curiosity.h diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS index d209249c2ef..5e9edd2265f 100644 --- a/board/atmel/sam9x60ek/MAINTAINERS +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -1,6 +1,6 @@ SAM9X60EK BOARD M: Sandeep Sheriker M <[email protected]> -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sam9x60ek/ F: include/configs/sam9x60ek.h diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS index ba2f31e6c4d..9f24c578f9e 100644 --- a/board/atmel/sama5d27_som1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D27 SOM1 EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d27_som1_ek/ F: include/configs/sama5d27_som1_ek.h diff --git a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS index ff68cf01a34..ea3b4b27579 100644 --- a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS @@ -1,6 +1,6 @@ SAMA5D27 WLSOM1 EK BOARD M: Nicolas Ferre <[email protected]> -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d27_wlsom1_ek/ F: include/configs/sama5d27_wlsom1_ek.h diff --git a/board/atmel/sama5d2_icp/MAINTAINERS b/board/atmel/sama5d2_icp/MAINTAINERS index 4a65c65ec3b..d668aa26260 100644 --- a/board/atmel/sama5d2_icp/MAINTAINERS +++ b/board/atmel/sama5d2_icp/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D2 ICP BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d2_icp/ F: include/configs/sama5d2_icp.h diff --git a/board/atmel/sama5d2_ptc_ek/MAINTAINERS b/board/atmel/sama5d2_ptc_ek/MAINTAINERS index 9f82d9a3d82..95a57b2a996 100644 --- a/board/atmel/sama5d2_ptc_ek/MAINTAINERS +++ b/board/atmel/sama5d2_ptc_ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D2 PTC EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> M: Ludovic Desroches <[email protected]> S: Maintained F: board/atmel/sama5d2_ptc_ek/ diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS index 88e327f81cd..0c4e74b2dd4 100644 --- a/board/atmel/sama5d2_xplained/MAINTAINERS +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D2 XPLAINED BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d2_xplained/ F: include/configs/sama5d2_xplained.h diff --git a/board/atmel/sama5d3_xplained/MAINTAINERS b/board/atmel/sama5d3_xplained/MAINTAINERS index 69b4ee8a33b..4979545dbc9 100644 --- a/board/atmel/sama5d3_xplained/MAINTAINERS +++ b/board/atmel/sama5d3_xplained/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D3_XPLAINED BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d3_xplained/ F: include/configs/sama5d3_xplained.h diff --git a/board/atmel/sama5d3xek/MAINTAINERS b/board/atmel/sama5d3xek/MAINTAINERS index e8ec275d71d..a1c96bfea84 100644 --- a/board/atmel/sama5d3xek/MAINTAINERS +++ b/board/atmel/sama5d3xek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D3XEK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d3xek/ F: include/configs/sama5d3xek.h diff --git a/board/atmel/sama5d4_xplained/MAINTAINERS b/board/atmel/sama5d4_xplained/MAINTAINERS index 9fd0ad7bc2b..43fc23ef814 100644 --- a/board/atmel/sama5d4_xplained/MAINTAINERS +++ b/board/atmel/sama5d4_xplained/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D4 XPLAINED ULTRA BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d4_xplained/ F: include/configs/sama5d4_xplained.h diff --git a/board/atmel/sama5d4ek/MAINTAINERS b/board/atmel/sama5d4ek/MAINTAINERS index f715af6401b..757be21b96a 100644 --- a/board/atmel/sama5d4ek/MAINTAINERS +++ b/board/atmel/sama5d4ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D4EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d4ek/ F: include/configs/sama5d4ek.h diff --git a/board/atmel/sama7g5ek/MAINTAINERS b/board/atmel/sama7g5ek/MAINTAINERS index eac972968d7..4d1c6f666c0 100644 --- a/board/atmel/sama7g5ek/MAINTAINERS +++ b/board/atmel/sama7g5ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA7G5 EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama7g5ek.c F: include/configs/sama7g5ek.h diff --git a/board/dhelectronics/common/dh_imx.c b/board/dhelectronics/common/dh_imx.c index 3d6487dd0d8..50404a66f9d 100644 --- a/board/dhelectronics/common/dh_imx.c +++ b/board/dhelectronics/common/dh_imx.c @@ -10,13 +10,13 @@ #include <net.h> #include "dh_imx.h" -int dh_imx_get_mac_from_fuse(unsigned char *enetaddr) +int dh_imx_get_mac_from_fuse(unsigned char *enetaddr, int index) { /* * If IIM fuses contain valid MAC address, use it. * The IIM MAC address fuses are NOT programmed by default. */ - imx_get_mac_from_fuse(0, enetaddr); + imx_get_mac_from_fuse(index, enetaddr); if (!is_valid_ethaddr(enetaddr)) return -EINVAL; diff --git a/board/dhelectronics/common/dh_imx.h b/board/dhelectronics/common/dh_imx.h index 284f8637fb8..be2ff5e076c 100644 --- a/board/dhelectronics/common/dh_imx.h +++ b/board/dhelectronics/common/dh_imx.h @@ -7,6 +7,7 @@ * dh_imx_get_mac_from_fuse - Get MAC address from fuse and write it to env * * @enetaddr: buffer where address is to be stored + * @index: index of MAC address in fuse (starts with 0) * Return: 0 if OK, other value on error */ -int dh_imx_get_mac_from_fuse(unsigned char *enetaddr); +int dh_imx_get_mac_from_fuse(unsigned char *enetaddr, int index); diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index 234824b38c2..c9e8107685a 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -94,7 +94,7 @@ int dh_setup_mac_address(struct eeprom_id_page *eip) if (dh_get_mac_is_enabled("ethernet0")) return 0; - if (!dh_imx_get_mac_from_fuse(enetaddr)) + if (!dh_imx_get_mac_from_fuse(enetaddr, 0)) goto out; if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0")) diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 3424be10936..486073392e9 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -47,7 +47,7 @@ static int dh_imx8_setup_ethaddr(struct eeprom_id_page *eip) if (dh_get_mac_is_enabled("ethernet0")) return 0; - if (!dh_imx_get_mac_from_fuse(enetaddr)) + if (!dh_imx_get_mac_from_fuse(enetaddr, 0)) goto out; if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip)) @@ -72,8 +72,8 @@ static int dh_imx8_setup_eth1addr(struct eeprom_id_page *eip) if (dh_get_mac_is_enabled("ethernet1")) return 0; - if (!dh_imx_get_mac_from_fuse(enetaddr)) - goto increment_out; + if (!dh_imx_get_mac_from_fuse(enetaddr, 1)) + goto out; if (!dh_get_value_from_eeprom_buffer(DH_MAC1, enetaddr, sizeof(enetaddr), eip)) goto out; diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c index cfba9300dcb..f3aae9256c1 100644 --- a/board/google/imx8mq_phanbell/spl.c +++ b/board/google/imx8mq_phanbell/spl.c @@ -6,134 +6,21 @@ #include <config.h> #include <hang.h> -#include <asm/global_data.h> -#include <asm/io.h> #include <errno.h> #include <init.h> #include <log.h> -#include <asm/io.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <linux/delay.h> -#include <fsl_esdhc_imx.h> -#include <mmc.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(void) { /* ddr init */ ddr_init(&dram_timing); } -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = 1; - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - return ret; - } - - return 1; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR}, - {USDHC2_BASE_ADDR}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - usdhc_cfg[0].max_bus_width = 8; - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - usdhc_cfg[1].max_bus_width = 4; - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - void spl_board_init(void) { puts("Normal Boot\n"); @@ -153,8 +40,8 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -166,12 +53,9 @@ void board_init_f(ulong dummy) preloader_console_init(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } @@ -180,5 +64,8 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c index bd5981bf694..0396967fe36 100644 --- a/board/kontron/pitx_imx8m/spl.c +++ b/board/kontron/pitx_imx8m/spl.c @@ -2,22 +2,14 @@ #include <config.h> #include <errno.h> -#include <fsl_esdhc_imx.h> #include <hang.h> #include <init.h> #include <log.h> #include <spl.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <linux/delay.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> @@ -26,8 +18,6 @@ extern struct dram_timing_info dram_timing_2gb; extern struct dram_timing_info dram_timing_4gb; -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(void) { struct dram_timing_info *dram_timing; @@ -53,120 +43,6 @@ static void spl_dram_init(void) ddr_init(dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(MMC) -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - /* the eMMC does not have a CD pin */ - return 1; - case USDHC2_BASE_ADDR: - return !gpio_get_value(USDHC2_CD_GPIO); - } - - return 0; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR, 0, 8}, - {USDHC2_BASE_ADDR, 0, 4}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers " - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - const char *spl_board_loader_name(u32 boot_device) { switch (boot_device) { @@ -178,18 +54,14 @@ const char *spl_board_loader_name(u32 boot_device) return NULL; } } -#endif -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 - -static int pfuze_mode_init(struct pmic *p, u32 mode) +static int pfuze_mode_init(struct udevice *dev, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = pmic_reg_read(dev, PFUZE100_DEVICEID); id = id & 0xf; if (id == 0) { @@ -203,14 +75,14 @@ static int pfuze_mode_init(struct pmic *p, u32 mode) return -EINVAL; } - ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -223,46 +95,44 @@ static int pfuze_mode_init(struct pmic *p, u32 mode) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; + int reg; int ret; - unsigned int reg; - - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return -ENODEV; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return -ENODEV; + ret = pmic_get("pmic@8", &dev); + if (ret == -ENODEV) { + puts("No pmic@8\n"); + return 0; + } + if (ret < 0) + return ret; - pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AVOL); if ((reg & 0x3f) != 0x18) { reg &= ~0x3f; reg |= 0x18; - pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + pmic_reg_write(dev, PFUZE100_SW3AVOL, reg); } - ret = pfuze_mode_init(p, APS_PFM); + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; /* set SW3A standby mode to off */ - pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AMODE); reg &= ~0xf; reg |= APS_OFF; - pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + pmic_reg_write(dev, PFUZE100_SW3AMODE, reg); return 0; } -#endif void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -272,26 +142,22 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } - enable_tzc380(); + preloader_console_init(); - setup_i2c(0, 100000, 0x7f, &i2c_pad_info1); + enable_tzc380(); -#if CONFIG_IS_ENABLED(POWER_LEGACY) power_init_board(); -#endif spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS index c342ff24330..37ca35b4dd4 100644 --- a/board/mediatek/MAINTAINERS +++ b/board/mediatek/MAINTAINERS @@ -3,10 +3,14 @@ M: Macpaul Lin <[email protected]> S: Maintained F: arch/arm/dts/mt8371-genio-520-evk-u-boot.dtsi F: arch/arm/dts/mt8371-genio-common-u-boot.dtsi +F: arch/arm/dts/mt8371-genio-common-ufs.dtso F: arch/arm/dts/mt8391-genio-720-evk-u-boot.dtsi +F: configs/mt8189-ufs.config F: configs/mt8189.config F: configs/mt8371_genio_520_evk_defconfig +F: configs/mt8371_genio_520_evk_ufs_defconfig F: configs/mt8391_genio_720_evk_defconfig +F: configs/mt8391_genio_720_evk_ufs_defconfig MT8365 EVK M: Julien Masson <[email protected]> @@ -21,8 +25,10 @@ F: configs/mt8188.config F: configs/mt8370_genio_510_evk_defconfig F: configs/mt8390_genio_700_evk_defconfig -MT8395 +MT8195/MT8395 M: Macpaul Lin <[email protected]> M: Julien Stephan <[email protected]> S: Maintained +F: configs/mt8195.config F: configs/mt8395_genio_1200_evk_defconfig +F: configs/mt8395_genio_1200_evk_ufs_defconfig diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c index 48a783593b6..aca0525c699 100644 --- a/board/mntre/imx8mq_reform2/spl.c +++ b/board/mntre/imx8mq_reform2/spl.c @@ -10,7 +10,6 @@ #include <image.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <errno.h> #include <asm/io.h> @@ -28,8 +27,6 @@ #include <power/pmic.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - extern struct dram_timing_info dram_timing_ch2; static void spl_dram_init(void) @@ -226,9 +223,6 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - arch_cpu_init(); init_uart_clk(0); diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile index ed102ae7bf7..dafd3717948 100644 --- a/board/nxp/common/Makefile +++ b/board/nxp/common/Makefile @@ -57,7 +57,7 @@ obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o endif -obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o +obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o ifneq (,$(filter $(SOC), imx8m imx8ulp imx9)) obj-y += mmc.o diff --git a/board/nxp/common/pfuze.c b/board/nxp/common/pfuze.c index 0d7a94fd232..179cc605da0 100644 --- a/board/nxp/common/pfuze.c +++ b/board/nxp/common/pfuze.c @@ -7,14 +7,14 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> -#ifndef CONFIG_DM_PMIC_PFUZE100 -int pfuze_mode_init(struct pmic *p, u32 mode) +#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) +int pfuze_mode_init(struct udevice *dev, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = pmic_reg_read(dev, PFUZE100_DEVICEID); id = id & 0xf; if (id == 0) { @@ -28,14 +28,14 @@ int pfuze_mode_init(struct pmic *p, u32 mode) return -EINVAL; } - ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -46,58 +46,54 @@ int pfuze_mode_init(struct pmic *p, u32 mode) return ret; } -struct pmic *pfuze_common_init(unsigned char i2cbus) +struct udevice *pfuze_common_init(void) { - struct pmic *p; + struct udevice *dev; int ret; - unsigned int reg; - - ret = power_pfuze100_init(i2cbus); - if (ret) - return NULL; + unsigned int reg, dev_id, rev_id; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) return NULL; - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* Set SW1AB stanby volage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); - return p; + return dev; } -#elif defined(CONFIG_DM_PMIC) -int pfuze_mode_init(struct udevice *dev, u32 mode) +#else +int pfuze_mode_init(struct pmic *p, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - id = pmic_reg_read(dev, PFUZE100_DEVICEID); + pmic_reg_read(p, PFUZE100_DEVICEID, &id); id = id & 0xf; if (id == 0) { @@ -111,14 +107,14 @@ int pfuze_mode_init(struct udevice *dev, u32 mode) return -EINVAL; } - ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -129,44 +125,48 @@ int pfuze_mode_init(struct udevice *dev, u32 mode) return ret; } -struct udevice *pfuze_common_init(void) +struct pmic *pfuze_common_init(unsigned char i2cbus) { - struct udevice *dev; + struct pmic *p; int ret; - unsigned int reg, dev_id, rev_id; + unsigned int reg; - ret = pmic_get("pfuze100@8", &dev); - if (ret == -ENODEV) + ret = power_pfuze100_init(i2cbus); + if (ret) return NULL; - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return NULL; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); /* Set SW1AB stanby volage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); - return dev; + return p; } #endif diff --git a/board/nxp/common/pfuze.h b/board/nxp/common/pfuze.h index 45b49afaeb7..da89853bd20 100644 --- a/board/nxp/common/pfuze.h +++ b/board/nxp/common/pfuze.h @@ -6,7 +6,7 @@ #ifndef __PFUZE_BOARD_HELPER__ #define __PFUZE_BOARD_HELPER__ -#ifdef CONFIG_DM_PMIC_PFUZE100 +#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) struct udevice *pfuze_common_init(void); int pfuze_mode_init(struct udevice *dev, u32 mode); #else diff --git a/board/nxp/imx8mq_evk/spl.c b/board/nxp/imx8mq_evk/spl.c index 5116d806bb6..80322a2ed19 100644 --- a/board/nxp/imx8mq_evk/spl.c +++ b/board/nxp/imx8mq_evk/spl.c @@ -9,23 +9,16 @@ #include <image.h> #include <init.h> #include <log.h> -#include <asm/io.h> #include <errno.h> #include <asm/io.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <fsl_esdhc_imx.h> -#include <fsl_sec.h> -#include <mmc.h> -#include <linux/delay.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include <dm/uclass.h> +#include <dm/device.h> #include <spl.h> #include "../common/pfuze.h" @@ -40,166 +33,52 @@ static void spl_dram_init(void) ddr_init(&dram_timing_b0); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = 1; - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - return ret; - } - - return 1; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR, 0, 8}, - {USDHC2_BASE_ADDR, 0, 4}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 int power_init_board(void) { - struct pmic *p; + struct udevice *dev; + int reg; int ret; - unsigned int reg; - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return -ENODEV; - - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return -ENODEV; + ret = pmic_get("pmic@8", &dev); + if (ret == -ENODEV) { + puts("No pmic@8\n"); + return 0; + } + if (ret < 0) + return ret; - pmic_reg_read(p, PFUZE100_DEVICEID, ®); + reg = pmic_reg_read(dev, PFUZE100_DEVICEID); printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AVOL); if ((reg & 0x3f) != 0x18) { reg &= ~0x3f; reg |= 0x18; - pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + pmic_reg_write(dev, PFUZE100_SW3AVOL, reg); } - ret = pfuze_mode_init(p, APS_PFM); + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; /* set SW3A standby mode to off */ - pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AMODE); reg &= ~0xf; reg |= APS_OFF; - pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + pmic_reg_write(dev, PFUZE100_SW3AMODE, reg); return 0; } -#endif void spl_board_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { - if (sec_init()) - printf("\nsec_init failed!\n"); + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); } puts("Normal Boot\n"); } @@ -218,8 +97,8 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -229,25 +108,22 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } + preloader_console_init(); enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.c b/board/nxp/mx6sabreauto/mx6sabreauto.c index 8ca57e0b2ac..aef8bc0ad90 100644 --- a/board/nxp/mx6sabreauto/mx6sabreauto.c +++ b/board/nxp/mx6sabreauto/mx6sabreauto.c @@ -465,6 +465,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) } #endif +#ifndef CONFIG_XPL_BUILD int power_init_board(void) { struct udevice *dev; @@ -488,6 +489,7 @@ int power_init_board(void) return pfuze_mode_init(dev, APS_PFM); } +#endif #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { diff --git a/board/nxp/mx6sabresd/mx6sabresd.c b/board/nxp/mx6sabresd/mx6sabresd.c index dff3a9c33bf..9404535104c 100644 --- a/board/nxp/mx6sabresd/mx6sabresd.c +++ b/board/nxp/mx6sabresd/mx6sabresd.c @@ -437,6 +437,7 @@ int board_init(void) return 0; } +#ifndef CONFIG_XPL_BUILD int power_init_board(void) { struct udevice *dev; @@ -468,6 +469,7 @@ int power_init_board(void) return 0; } +#endif #ifdef CONFIG_MXC_SPI int board_spi_cs_gpio(unsigned bus, unsigned cs) diff --git a/board/qualcomm/debug-milos.config b/board/qualcomm/debug-milos.config new file mode 100644 index 00000000000..a4cdd13f226 --- /dev/null +++ b/board/qualcomm/debug-milos.config @@ -0,0 +1,5 @@ +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0xa94000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 diff --git a/board/qualcomm/tfa-optee.config b/board/qualcomm/tfa-optee.config new file mode 100644 index 00000000000..1e8364c114f --- /dev/null +++ b/board/qualcomm/tfa-optee.config @@ -0,0 +1,4 @@ +# Enables support for TF-A based OP-TEE as the open +# source TrustZone stack on Qcom platforms +CONFIG_TEE=y +CONFIG_OPTEE=y diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS index a569efa74e3..afc9bf5706c 100644 --- a/board/radxa/rock5a-rk3588s/MAINTAINERS +++ b/board/radxa/rock5a-rk3588s/MAINTAINERS @@ -1,5 +1,5 @@ ROCK5A-RK3588 -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: board/radxa/rock5a-rk3588s diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS index c8a43769105..2910d9bed3d 100644 --- a/board/radxa/rock5b-rk3588/MAINTAINERS +++ b/board/radxa/rock5b-rk3588/MAINTAINERS @@ -1,5 +1,5 @@ ROCK5B-RK3588 -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: board/radxa/rock5b-rk3588 diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c index ee0ad20ced4..200562482af 100644 --- a/board/ronetix/imx8mq-cm/spl.c +++ b/board/ronetix/imx8mq-cm/spl.c @@ -18,8 +18,6 @@ #include <linux/delay.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(void) { /* ddr init */ @@ -135,9 +133,6 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - arch_cpu_init(); init_uart_clk(0); diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c index c9d68b402ae..eed7f70e833 100644 --- a/board/technexion/pico-imx8mq/spl.c +++ b/board/technexion/pico-imx8mq/spl.c @@ -10,7 +10,6 @@ #include <asm/arch/ddr.h> #include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/gpio.h> #include <asm/mach-imx/iomux-v3.h> @@ -24,8 +23,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - #define DDR_DET_1 IMX_GPIO_NR(3, 11) #define DDR_DET_2 IMX_GPIO_NR(3, 12) #define DDR_DET_3 IMX_GPIO_NR(3, 13) @@ -196,9 +193,6 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - arch_cpu_init(); init_uart_clk(0); diff --git a/board/ti/common/cape_detect.c b/board/ti/common/cape_detect.c index 88fa6ae81f0..65bd6ef39ec 100644 --- a/board/ti/common/cape_detect.c +++ b/board/ti/common/cape_detect.c @@ -13,6 +13,44 @@ #include "cape_detect.h" +struct name_mapping { + char part_number[17]; + char version[5]; + char overlay[64]; +}; + +static struct name_mapping extension_mapping[] = { + { + "BB-GREEN-HDMI", + "00A0", + "am335x-bone-hdmi-00a0.dtbo", + } +}; + +static void set_cape_overlay(char *overlay, char *part_number, char *version) +{ + struct name_mapping *mapping; + + for (int i = 0; i < ARRAY_SIZE(extension_mapping); i++) { + mapping = &extension_mapping[i]; + + if (strncmp(mapping->part_number, part_number, + sizeof(mapping->part_number))) + continue; + + if (strncmp(mapping->version, version, + sizeof(mapping->version))) + continue; + + strlcpy(overlay, mapping->overlay, sizeof(mapping->overlay)); + return; + } + + /* Use default name extracted from the EEPROM */ + snprintf(overlay, sizeof(extension_mapping[0].overlay), "%s-%s.dtbo", + part_number, version); +} + static void sanitize_field(char *text, size_t size) { char *c = NULL; @@ -82,8 +120,8 @@ static int ti_extension_board_scan(struct udevice *dev, printf("BeagleBone Cape: %s (0x%x)\n", eeprom_header.board_name, addr); - snprintf(cape.overlay, sizeof(cape.overlay), "%s-%s.dtbo", - process_cape_part_number, process_cape_version); + set_cape_overlay(cape.overlay, process_cape_part_number, + process_cape_version); strlcpy(cape.name, eeprom_header.board_name, sizeof(eeprom_header.board_name)); strlcpy(cape.version, process_cape_version, diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index c8c10742103..896a0d3bd12 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -187,6 +187,9 @@ const struct toradex_som toradex_modules[] = { { OSM_IMX91S_2GB_IT, "OSM iMX91 Solo 2GB IT", TARGET_IS_ENABLED(TORADEX_OSM_IMX91) }, { VERDIN_AM62D_1G_ET_GPU_NODSI, "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, { AQUILA_TDA4O_16GB_IT, "Aquila TDA4 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { VERDIN_IMX95H_4G_WB_IT, "Verdin iMX95 Hexa 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, + { VERDIN_IMX95H_4G_ET, "Verdin iMX95 Hexa 4GB ET", TARGET_IS_ENABLED(VERDIN_IMX95) }, + { VERDIN_IMX95H_16G_IT, "Verdin iMX95 Hexa 16GB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 3022ef615ad..9a96bddfbe1 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -150,6 +150,9 @@ enum { OSM_IMX91S_2GB_IT, /* 220 */ VERDIN_AM62D_1G_ET_GPU_NODSI, AQUILA_TDA4O_16GB_IT = 223, + VERDIN_IMX95H_4G_WB_IT = 226, + VERDIN_IMX95H_4G_ET, + VERDIN_IMX95H_16G_IT, }; enum { diff --git a/board/toradex/verdin-imx95/Kconfig b/board/toradex/verdin-imx95/Kconfig new file mode 100644 index 00000000000..ef4206c343c --- /dev/null +++ b/board/toradex/verdin-imx95/Kconfig @@ -0,0 +1,36 @@ +if TARGET_VERDIN_IMX95 + +config SYS_BOARD + default "verdin-imx95" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "verdin-imx95" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/verdin-imx95/MAINTAINERS b/board/toradex/verdin-imx95/MAINTAINERS new file mode 100644 index 00000000000..d19ee3ebfe5 --- /dev/null +++ b/board/toradex/verdin-imx95/MAINTAINERS @@ -0,0 +1,13 @@ +Verdin iMX95 +F: arch/arm/dts/imx95-verdin.dtsi +F: arch/arm/dts/imx95-verdin-dev.dtsi +F: arch/arm/dts/imx95-verdin-wifi.dtsi +F: arch/arm/dts/imx95-verdin-wifi-dev.dts +F: arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi +F: board/toradex/verdin-imx95/ +F: configs/verdin-imx95_defconfig +F: doc/board/toradex/verdin-imx95.rst +F: include/configs/verdin-imx95.h +M: Francesco Dolcini <[email protected]> +S: Maintained +W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 diff --git a/board/toradex/verdin-imx95/Makefile b/board/toradex/verdin-imx95/Makefile new file mode 100644 index 00000000000..bc1b6811bbe --- /dev/null +++ b/board/toradex/verdin-imx95/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (c) Toradex + +obj-y += verdin-imx95.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/toradex/verdin-imx95/spl.c b/board/toradex/verdin-imx95/spl.c new file mode 100644 index 00000000000..9f501c11c1d --- /dev/null +++ b/board/toradex/verdin-imx95/spl.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/sections.h> +#include <asm/global_data.h> +#include <clk.h> +#include <dm/uclass.h> +#include <hang.h> +#include <i2c.h> +#include <init.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION)) + spl_save_restore_data(); + + timer_init(); + + /* Need dm_init() to run before any SCMI calls */ + spl_early_init(); + + /* Need to enable SCMI drivers and ELE driver before console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* MU not probed, nothing can be outputed, hang */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/board/toradex/verdin-imx95/verdin-imx95.c b/board/toradex/verdin-imx95/verdin-imx95.c new file mode 100644 index 00000000000..60c1dbb5e29 --- /dev/null +++ b/board/toradex/verdin-imx95/verdin-imx95.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <env.h> +#include <errno.h> +#include <fdt_support.h> +#include <init.h> +#include <stdio.h> +#include <string.h> + +#include "../common/tdx-cfg-block.h" +#include "../common/tdx-common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + bool is_wifi = false; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a + * module with Wi-Fi/Bluetooth make sure we use the -wifi + * device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX95H_8G_WIFI_BT_IT) || + (tdx_hw_tag.prodid == VERDIN_IMX95H_4G_WB_IT); + } + + if (is_wifi) + strlcpy(&variant[0], "wifi", sizeof(variant)); + else + strlcpy(&variant[0], "nonwifi", sizeof(variant)); + + if (!env_variant || strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + } +} + +int board_late_init(void) +{ + select_dt_from_module_version(); + + return 0; +} + +static const struct ram_alias_check ram_alias_checks[] = { + { (void *)(PHYS_SDRAM + SZ_8G), (void *)(PHYS_SDRAM), SZ_16G }, + { (void *)(PHYS_SDRAM + SZ_4G), (void *)(PHYS_SDRAM), SZ_8G }, + { (void *)(PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G }, + { (void *)(PHYS_SDRAM + SZ_1G), (void *)(PHYS_SDRAM), SZ_2G }, + { NULL } +}; + +int board_phys_sdram_size(phys_size_t *size) +{ + phys_size_t sz; + + sz = probe_ram_size_by_alias(ram_alias_checks); + if (!sz) { + puts("## WARNING: Less than 2GB RAM detected\n"); + return -EINVAL; + } + + *size = sz - PHYS_SDRAM_FW_RSVD; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif diff --git a/board/toradex/verdin-imx95/verdin-imx95.env b/board/toradex/verdin-imx95/verdin-imx95.env new file mode 100644 index 00000000000..5ca6cb18aaa --- /dev/null +++ b/board/toradex/verdin-imx95/verdin-imx95.env @@ -0,0 +1,20 @@ +boot_scripts=boot.scr +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyLP2 +fdt_board=dev +fdt_addr=0x9c400000 +fdt_addr_r=0x9c400000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x94400000 +kernel_comp_size=0x8000000 +ramdisk_addr_r=0x9c800000 +scriptaddr=0x9c600000 + +update_uboot= + askenv confirm Did you load flash.bin (y/N)?; + if test "$confirm" = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 + ${blkcnt}; + fi diff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS index e6f3dc4da21..b31c5793432 100644 --- a/board/tq/MAINTAINERS +++ b/board/tq/MAINTAINERS @@ -6,3 +6,12 @@ W: https://www.tq-group.com/en/products/tq-embedded/ F: arch/arm/dts/*mba6*.dts* F: arch/arm/dts/*tqma6*.dts* F: configs/tqma6*config + +TQMA7 +M: Alexander Feilke <[email protected]> +S: Maintained +W: https://www.tq-group.com/en/products/tq-embedded/ +F: arch/arm/dts/*mba7*.dts* +F: arch/arm/dts/*tqma7*.dts* +F: configs/tqma7*config diff --git a/board/tq/common/Kconfig b/board/tq/common/Kconfig index a1896929ea3..2fe2ca30072 100644 --- a/board/tq/common/Kconfig +++ b/board/tq/common/Kconfig @@ -11,3 +11,6 @@ config TQ_COMMON_BB config TQ_COMMON_SDMMC bool + +config TQ_COMMON_SOM + bool diff --git a/board/tq/common/Makefile b/board/tq/common/Makefile index ac564a713fd..4af9207da4a 100644 --- a/board/tq/common/Makefile +++ b/board/tq/common/Makefile @@ -6,4 +6,5 @@ # obj-$(CONFIG_TQ_COMMON_BB) += tq_bb.o +obj-$(CONFIG_TQ_COMMON_SOM) += tq_som.o obj-$(CONFIG_TQ_COMMON_SDMMC) += tq_sdmmc.o diff --git a/board/tq/common/tq_som.c b/board/tq/common/tq_som.c new file mode 100644 index 00000000000..6fb4839109b --- /dev/null +++ b/board/tq/common/tq_som.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke, Max Merchel + */ + +#include <init.h> +#include <asm/io.h> +#include <linux/sizes.h> + +#include "tq_som.h" + +void __weak tq_som_ram_init(void) +{ + ; +} + +/* + * checks if the accessible range equals the requested RAM size. + * returns true if successful, false otherwise + */ +bool tq_som_ram_check_size(long ram_size) +{ + long size; + + size = get_ram_size((void *)PHYS_SDRAM, ram_size); + debug("SPL: requested RAM size %lu MiB. accessible %lu MiB\n", + ram_size / (SZ_1M), size / (SZ_1M)); + + return (size == ram_size); +} diff --git a/board/tq/common/tq_som.h b/board/tq/common/tq_som.h new file mode 100644 index 00000000000..0ab01d51f99 --- /dev/null +++ b/board/tq/common/tq_som.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke, Max Merchel + */ + +#ifndef __TQ_SOM_H +#define __TQ_SOM_H + +#include <init.h> +#include <asm/io.h> +#include <linux/iopoll.h> + +void tq_som_ram_init(void); + +/* used as a wrapper to write to specific register addresses */ +static inline void tq_som_init_write_reg(u32 address, u32 value) +{ + writel_relaxed(value, address); +} + +/* + * checks if the accessible range equals the requested ram size. + * returns true if successful, false otherwise + */ +bool tq_som_ram_check_size(long ram_size); + +static inline void tq_som_check_bits_set(u32 address, u32 mask) +{ + u32 val; + readl_poll_timeout(address, val, (val & mask) == mask, 1000); +} + +#endif /* __TQ_SOM_H */ diff --git a/board/tq/tqma7/Kconfig b/board/tq/tqma7/Kconfig new file mode 100644 index 00000000000..477ce3f3d53 --- /dev/null +++ b/board/tq/tqma7/Kconfig @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. +# Author: Markus Niebel, Steffen Doster +# + +if TARGET_TQMA7 + +config SYS_BOARD + default "tqma7" + +config SYS_VENDOR + default "tq" + +config SYS_CONFIG_NAME + default "tqma7" + +choice + prompt "TQMa7x RAM configuration" + default TQMA7_RAM_MULTI + help + Select RAM configuration. Normally use default here but for + specific setup it is possible to use a single RAM size. + +config TQMA7_RAM_MULTI + bool "TQMa7x with 512/1024/2048 MB RAM - Single image" + select TQMA7_RAM_2G + select TQMA7_RAM_1G + select TQMA7_RAM_512M + help + Build a single U-Boot solely for variants + with 512/1024/2048 MB RAM. + +config TQMA7_RAM_SINGLE_2G + bool "TQMa7x with 2 GB RAM" + select TQMA7_RAM_2G + help + Build U-Boot solely for variants + with 2 GB RAM. + +config TQMA7_RAM_SINGLE_1G + bool "TQMa7x with 1 GB RAM" + select TQMA7_RAM_1G + help + Build U-Boot solely for variants + with 1 GB RAM. + +config TQMA7_RAM_SINGLE_512M + bool "TQMa7x with 512 MB RAM" + select TQMA7_RAM_512M + help + Build U-Boot solely for variants + with 512 MB RAM. + +endchoice + +config TQMA7_RAM_2G + bool + +config TQMA7_RAM_1G + bool + +config TQMA7_RAM_512M + bool + +choice + prompt "TQMa7x base board variant" + default MBA7 + help + Select base board + for TQMa7x + +config MBA7 + bool "TQMa7x on MBa7x Starterkit" + select TQ_COMMON_BB + select TQ_COMMON_SOM + select TQ_COMMON_SYSINFO + select I2C_EEPROM + select MISC + imply USB + imply CMD_USB + imply USB_STORAGE + imply PHYLIB + imply CONFIG_PHY_TI_DP83867 + select MXC_UART + select DM_MMC + select DM_SPI + select DM_I2C + select DM_GPIO + imply DM_ETH + help + Select the MBa7x + starterkit. + +endchoice + +config IMX_CONFIG + default "board/tq/tqma7/tqma7.cfg" + +source "board/tq/common/Kconfig" + +endif diff --git a/board/tq/tqma7/Makefile b/board/tq/tqma7/Makefile new file mode 100644 index 00000000000..b1fb270e861 --- /dev/null +++ b/board/tq/tqma7/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. + + +obj-y += tqma7.o +obj-$(CONFIG_MBA7) += tqma7_mba7.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += spl_tqma7_ram.o +obj-$(CONFIG_MBA7) += spl_mba7.o +endif diff --git a/board/tq/tqma7/spl.c b/board/tq/tqma7/spl.c new file mode 100644 index 00000000000..62db30e81f2 --- /dev/null +++ b/board/tq/tqma7/spl.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + */ + +#include <fsl_esdhc_imx.h> +#include <hang.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch-mx7/mx7d_pins.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> + +#include "../common/tq_bb.h" +#include "../common/tq_som.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CMD_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | \ + PAD_CTL_SRE_SLOW | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_STROBE_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM) + +/* eMMC on USDHCI3 always present */ +static const iomux_v3_cfg_t tqma7_usdhc3_pads[] = { + NEW_PAD_CTRL(MX7D_PAD_SD3_CLK__SD3_CLK, USDHC_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_CMD__SD3_CMD, USDHC_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA0__SD3_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA1__SD3_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA2__SD3_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA3__SD3_DATA3, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA4__SD3_DATA4, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA5__SD3_DATA5, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA6__SD3_DATA6, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA7__SD3_DATA7, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_STROBE__SD3_STROBE, USDHC_STROBE_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg tqma7_usdhc3_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 1; + else + ret = tq_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is not WP */ + ret = 0; + else + ret = tq_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma7_usdhc3_pads, + ARRAY_SIZE(tqma7_usdhc3_pads)); + + tqma7_usdhc3_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + if (fsl_esdhc_initialize(bis, &tqma7_usdhc3_cfg)) + puts("Warning: failed to initialize eMMC dev\n"); + + tq_bb_board_mmc_init(bis); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return tq_bb_board_init(); +} + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + timer_init(); + + tq_bb_board_early_init_f(); + + preloader_console_init(); + + /* DDR initialization */ + tq_som_ram_init(); +} + diff --git a/board/tq/tqma7/spl_mba7.c b/board/tq/tqma7/spl_mba7.c new file mode 100644 index 00000000000..13438247731 --- /dev/null +++ b/board/tq/tqma7/spl_mba7.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + */ + +#include <fsl_esdhc_imx.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch-mx7/mx7d_pins.h> + +#include "../common/tq_bb.h" + +#define UART_RX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_PUE | PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +#define UART_TX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_PUE | PAD_CTL_SRE_SLOW) + +#define USDHC_DATA_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CMD_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_STROBE_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_196OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW) +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +static const iomux_v3_cfg_t mba7_uart6_pads[] = { + NEW_PAD_CTRL(MX7D_PAD_EPDC_DATA08__UART6_DCE_RX, UART_RX_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_EPDC_DATA09__UART6_DCE_TX, UART_TX_PAD_CTRL), +}; + +static void mba7_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba7_uart6_pads, ARRAY_SIZE(mba7_uart6_pads)); +} + +static const iomux_v3_cfg_t mba7_usdhc1_pads[] = { + NEW_PAD_CTRL(MX7D_PAD_SD1_CLK__SD1_CLK, USDHC_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_CMD__SD1_CMD, USDHC_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA0__SD1_DATA0, USDHC_DATA_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA1__SD1_DATA1, USDHC_DATA_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA2__SD1_DATA2, USDHC_DATA_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA3__SD1_DATA3, USDHC_DATA_PAD_CTRL), + /* CD */ + NEW_PAD_CTRL(MX7D_PAD_SD1_CD_B__GPIO5_IO0, GPIO_IN_PAD_CTRL), + /* WP */ + NEW_PAD_CTRL(MX7D_PAD_SD1_WP__GPIO5_IO1, GPIO_IN_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC1_WP_GPIO IMX_GPIO_NR(5, 1) + +int tq_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = !gpio_get_value(USDHC1_CD_GPIO); + + return ret; +} + +int tq_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = gpio_get_value(USDHC1_WP_GPIO); + + return ret; +} + +static struct fsl_esdhc_cfg mba7_usdhc_cfg = { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, +}; + +int tq_bb_board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(mba7_usdhc1_pads, + ARRAY_SIZE(mba7_usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1-cd"); + gpio_request(USDHC1_WP_GPIO, "usdhc1-wp"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_direction_input(USDHC1_WP_GPIO); + + mba7_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + if (fsl_esdhc_initialize(bis, &mba7_usdhc_cfg)) + puts("Warning: failed to initialize SD\n"); + + return 0; +} + +int tq_bb_board_early_init_f(void) +{ + /* iomux and setup of uart */ + mba7_setup_iomuxc_uart(); + + return 0; +} + +/* + * This is done per baseboard to allow different implementations + */ +void board_boot_order(u32 *spl_boot_list) +{ + enum boot_device bd; + /* + * try to get sd card slots in order: + * eMMC: on Module + * -> therefore index 0 for bootloader + * index n in kernel (controller instance 3) -> patches needed for + * alias indexing + * SD1: on Mainboard + * index n in kernel (controller instance 1) -> patches needed for + * alias indexing + * we assume to have a kernel patch that will present mmcblk dev + * indexed like controller devs + */ + puts("Boot: "); + + bd = get_boot_device(); + switch (bd) { + case MMC3_BOOT: + puts("USDHC3(eMMC)\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case SD1_BOOT: + puts("USDHC1(SD)\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + case QSPI_BOOT: + puts("QSPI\n"); + spl_boot_list[0] = BOOT_DEVICE_NOR; + break; + case USB_BOOT: + puts("USB\n"); + spl_boot_list[0] = BOOT_DEVICE_BOARD; + break; + default: + /* Default - BOOT_DEVICE_MMC1 */ + puts("WARN: unknown boot device, fallback to eMMC\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + } +} + +int board_fit_config_name_match(const char *name) +{ + char *config = NULL; + + if (is_cpu_type(MXC_CPU_MX7S)) + config = "imx7s-mba7"; + else if (is_cpu_type(MXC_CPU_MX7D)) + config = "imx7d-mba7"; + + if (strcmp(config, name)) + return -EINVAL; + + printf("Device tree: %s\n", name); + + return 0; +} diff --git a/board/tq/tqma7/spl_tqma7_ram.c b/board/tq/tqma7/spl_tqma7_ram.c new file mode 100644 index 00000000000..903df5d9d0f --- /dev/null +++ b/board/tq/tqma7/spl_tqma7_ram.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + */ + +#include <config.h> +#include <hang.h> +#include <asm/arch/imx-regs.h> +#include <asm/mach-imx/iomux-v3.h> +#include <linux/sizes.h> + +#include "../common/tq_som.h" + +#define DDRC_RFSHTMG_512M 0x0020002B +#define DDRC_RFSHTMG_1G 0x00200045 +#define DDRC_RFSHTMG_2G 0x0020005D + +#define DDRC_ADDRMAP1_512M 0x00161616 +#define DDRC_ADDRMAP1_1G 0x00171717 +#define DDRC_ADDRMAP1_2G 0x00181818 + +#define DDRC_ADDRMAP6_512M 0x0F0F0404 +#define DDRC_ADDRMAP6_1G 0x0F040404 +#define DDRC_ADDRMAP6_2G 0x04040404 + +#define DDR_PHY_OFFSET_RD_CON0_512M 0x0B0B0B0B +#define DDR_PHY_OFFSET_RD_CON0_1G 0x0B0B0B0B +#define DDR_PHY_OFFSET_RD_CON0_2G 0x0A0A0A0A + +#define DDR_PHY_OFFSET_WR_CON0_512M 0x06060606 +#define DDR_PHY_OFFSET_WR_CON0_1G 0x06060606 +#define DDR_PHY_OFFSET_WR_CON0_2G 0x04040404 + +static void tqma7_ddr_exit_retention(void) +{ + /* Clear then set bit30 to ensure exit from DDR retention */ + tq_som_init_write_reg(0x30360388, 0x40000000); + tq_som_init_write_reg(0x30360384, 0x40000000); +} + +static void gpr_init(void) +{ + /* reset default and enable GPR OCRAM EPDC */ + tq_som_init_write_reg(0x30340004, 0x4F400005); +} + +static void tqma7_ccgr_init(void) +{ + tq_som_init_write_reg(0x30384130, 0x00000000); /* CCM_CCGR19 */ + tq_som_init_write_reg(0x30340020, 0x00000178); /* IOMUXC_GPR_GPR8 */ + tq_som_init_write_reg(0x30384130, 0x00000002); /* CCM_CCGR19 */ + tq_som_init_write_reg(0x30790018, 0x0000000f); /* DDR_PHY_LP_CON0 */ + + /* wait for auto-ZQ calibration to complete */ + tq_som_check_bits_set(0x307a0004, 0x1); /* DDRC_STAT */ +} + +static void ddr_init_error(const char *msg) +{ + pr_err("%s", msg); + hang(); +} + +#define TQMA7_SELECT_DDR_VALUE(SIZE, NAME) \ + ((SIZE) == SZ_512M ? NAME ## _512M : \ + ((SIZE) == SZ_1G ? NAME ## _1G : \ + ((SIZE) == SZ_2G ? NAME ## _2G : \ + (ddr_init_error("Invalid DDR RAM size detected"), 0)))) + +static void tqma7_init_ddr_controller(u32 size) +{ + gpr_init(); + + /* TQMa7 DDR config */ + /* TQMa7x DRAM Timing REV0201A */ + /* DCD Code i.MX7D/S 528 MHz 512 MByte Samsung K4B2G1646F */ + tq_som_init_write_reg(0x30360070, 0x0070302C); /*CCM_ANALOG_PLL_DDRx*/ + tq_som_init_write_reg(0x30360090, 0x00000000); /*CCM_ANALOG_PLL_NUM*/ + tq_som_init_write_reg(0x30360070, 0x0060302C); /*CCM_ANALOG_PLL_DDRx*/ + + tq_som_check_bits_set(0x30360070, 0x80000000); + + tq_som_init_write_reg(0x30391000, 0x00000002); /*SRC_DDRC_RCR*/ + tq_som_init_write_reg(0x307a0000, 0x01040001); /*DDRC_MSTR*/ + tq_som_init_write_reg(0x307a01a0, 0x80400003); /*DDRC_DFIUPD0*/ + tq_som_init_write_reg(0x307a01a4, 0x00100020); /*DDRC_DFIUPD1*/ + tq_som_init_write_reg(0x307a01a8, 0x80100004); /*DDRC_DFIUPD2*/ + tq_som_init_write_reg(0x307a0064, TQMA7_SELECT_DDR_VALUE(size, DDRC_RFSHTMG)); + tq_som_init_write_reg(0x307a0490, 0x00000001); /*DDRC_MP_PCTRL_0*/ + tq_som_init_write_reg(0x307a00d0, 0x00020081); /*DDRC_INIT0*/ + tq_som_init_write_reg(0x307a00d4, 0x00680000); /*DDRC_INIT1*/ + tq_som_init_write_reg(0x307a00dc, 0x09300004); /*DDRC_INIT3*/ + tq_som_init_write_reg(0x307a00e0, 0x00480000); /*DDRC_INIT4*/ + tq_som_init_write_reg(0x307a00e4, 0x00100004); /*DDRC_INIT5*/ + tq_som_init_write_reg(0x307a00f4, 0x0000033F); /*DDRC_RANKCTL*/ + tq_som_init_write_reg(0x307a0100, 0x090E0809); /*DDRC_DRAMTMG0*/ + tq_som_init_write_reg(0x307a0104, 0x0007020E); /*DDRC_DRAMTMG1*/ + tq_som_init_write_reg(0x307a0108, 0x03040407); /*DDRC_DRAMTMG2*/ + tq_som_init_write_reg(0x307a010c, 0x00002006); /*DDRC_DRAMTMG3*/ + tq_som_init_write_reg(0x307a0110, 0x04020304); /*DDRC_DRAMTMG4*/ + tq_som_init_write_reg(0x307a0114, 0x03030202); /*DDRC_DRAMTMG5*/ + tq_som_init_write_reg(0x307a0120, 0x00000803); /*DDRC_DRAMTMG8*/ + tq_som_init_write_reg(0x307a0180, 0x00800020); /*DDRC_ZQCTL0*/ + tq_som_init_write_reg(0x307a0190, 0x02098204); /*DDRC_DFITMG0*/ + tq_som_init_write_reg(0x307a0194, 0x00030303); /*DDRC_DFITMG1*/ + tq_som_init_write_reg(0x307a0200, 0x0000001F); /*DDRC_ADDRMAP0*/ + tq_som_init_write_reg(0x307a0204, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP1)); + tq_som_init_write_reg(0x307a020C, 0x00000000); /*DDRC_ADDRMAP3*/ + tq_som_init_write_reg(0x307a0210, 0x00000F0F); /*DDRC_ADDRMAP4*/ + tq_som_init_write_reg(0x307a0214, 0x04040404); /*DDRC_ADDRMAP5*/ + tq_som_init_write_reg(0x307a0218, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP6)); + tq_som_init_write_reg(0x307a0240, 0x06000604); /*DDRC_ODTCFG*/ + tq_som_init_write_reg(0x307a0244, 0x00000001); /*DDRC_ODTMAP*/ + tq_som_init_write_reg(0x30391000, 0x00000000); /*SRC_DDRC_RCR*/ + tq_som_init_write_reg(0x30790000, 0x17420F40); /*DDR_PHY_PHY_CON0*/ + tq_som_init_write_reg(0x30790004, 0x10210100); /*DDR_PHY_PHY_CON1*/ + tq_som_init_write_reg(0x30790010, 0x00060807); /*DDR_PHY_PHY_CON4*/ + tq_som_init_write_reg(0x307900b0, 0x1010007E); /*DDR_PHY_MDLL_CON0*/ + tq_som_init_write_reg(0x3079009c, 0x00000924); /*DDR_PHY_DRVDS_CON0*/ + + tq_som_init_write_reg(0x30790020, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_RD_CON0)); + tq_som_init_write_reg(0x30790030, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_WR_CON0)); + tq_som_init_write_reg(0x30790050, 0x01000010); /*DDR_PHY_CMD_SDLL_CON0*/ + tq_som_init_write_reg(0x30790050, 0x00000010); /*DDR_PHY_CMD_SDLL_CON0*/ + + tq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/ + tq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/ + tq_som_init_write_reg(0x307900c0, 0x0C447306); /*DDR_PHY_ZQ_CON0*/ + + tq_som_check_bits_set(0x307900c4, 0x1); /*ZQ Calibration is finished*/ + + tq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/ + tq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/ + + tqma7_ccgr_init(); +} + +void tq_som_ram_init(void) +{ + /* RAM sizes need to be in descending order */ + static const u32 ram_sizes[] = { +#if IS_ENABLED(CONFIG_TQMA7_RAM_2G) + SZ_2G, +#endif +#if IS_ENABLED(CONFIG_TQMA7_RAM_1G) + SZ_1G, +#endif +#if IS_ENABLED(CONFIG_TQMA7_RAM_512M) + SZ_512M, +#endif + }; + int i; + + debug("SPL: tqma7 iomux ....\n"); + tqma7_ddr_exit_retention(); + + for (i = 0; i < ARRAY_SIZE(ram_sizes); i++) { + tqma7_init_ddr_controller(ram_sizes[i]); + if (tq_som_ram_check_size(ram_sizes[i])) + break; + } + + if (i < ARRAY_SIZE(ram_sizes)) { + debug("SPL: tqma7 ddr init done ...\n"); + } else { + pr_err("Error: Invalid DDR RAM size\n"); + hang(); + } +} diff --git a/board/tq/tqma7/tqma7.c b/board/tq/tqma7/tqma7.c new file mode 100644 index 00000000000..30bd155713d --- /dev/null +++ b/board/tq/tqma7/tqma7.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Steffen Doster + */ + +#include <env.h> +#include <fdt_support.h> +#include <mtd_node.h> +#include <spi_flash.h> +#include <asm/bootm.h> +#include <asm/setup.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#include "../common/tq_bb.h" +#include "../common/tq_som.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +#if (!IS_ENABLED(CONFIG_SPL_BUILD)) + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + if (IS_ENABLED(CONFIG_FSL_QSPI)) + set_clk_qspi(); + + return tq_bb_board_init(); +} + +static const char *tqma7_get_boardname(void) +{ + switch (get_cpu_type()) { + case MXC_CPU_MX7S: + return "TQMa7S"; + case MXC_CPU_MX7D: + return "TQMa7D"; + default: + return "??"; + }; +} + +int board_late_init(void) +{ + const char *bname = tqma7_get_boardname(); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + struct tag_serialnr serialnr; + + get_board_serial(&serialnr); + + printf("UID: %08x%08x\n", serialnr.high, serialnr.low); + } + + env_set_runtime("board_name", bname); + + return tq_bb_board_late_init(); +} + +static u32 tqma7_get_board_rev(void) +{ + /* REV.0100 is unsupported */ + return 200; +} + +int checkboard(void) +{ + printf("Board: %s REV.%04u\n", tq_bb_get_boardname(), tqma7_get_board_rev()); + return 0; +} + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + tq_bb_ft_board_setup(blob, bd); + + return 0; +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + +#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */ diff --git a/board/tq/tqma7/tqma7.cfg b/board/tq/tqma7/tqma7.cfg new file mode 100644 index 00000000000..2e807d62348 --- /dev/null +++ b/board/tq/tqma7/tqma7.cfg @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Steffen Doster + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#include <config.h> + +/* + * Set to sd even for QSPI boot on i.MX7, as i.MX7 uses offset 0x400 rather + * than 0x1000 for QSPI + */ +BOOT_FROM sd + +#if IS_ENABLED(CONFIG_IMX_HAB) +CSF CONFIG_CSF_SIZE +#endif diff --git a/board/tq/tqma7/tqma7.env b/board/tq/tqma7/tqma7.env new file mode 100644 index 00000000000..857f16d11bb --- /dev/null +++ b/board/tq/tqma7/tqma7.env @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + * + * TQMa7x environment + */ + +#include <env/tq/tq-imx-shared.env> + +board=tqma7 +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA7_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA7_FDT_ADDRESS +fdtoverlay_addr_r=FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +netdev=eth0 +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA7_INITRD_ADDRESS +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA7_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA7_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA7_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA7_SPI_UBOOT_START +uboot_spi_size=TQMA7_SPI_UBOOT_SIZE + +#ifdef CONFIG_FASTBOOT_UUU_SUPPORT +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV:0 +fastboot_raw_partition_bootloader=TQMA7_MMC_UBOOT_SECTOR_START TQMA7_MMC_UBOOT_SECTOR_COUNT mmcpart 1 +fastbootcmd=fastboot usb 0 +#endif diff --git a/board/tq/tqma7/tqma7_mba7.c b/board/tq/tqma7/tqma7_mba7.c new file mode 100644 index 00000000000..65c6c08771d --- /dev/null +++ b/board/tq/tqma7/tqma7_mba7.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Steffen Doster + */ + +#include <env.h> +#include <errno.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-mx7/imx-regs.h> +#include <asm/mach-imx/boot_mode.h> + +#include "../common/tq_bb.h" + +const char *tq_bb_get_boardname(void) +{ + return "MBa7x"; +} + +#if !IS_ENABLED(CONFIG_SPL_BUILD) + +static int mba7_setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + switch (fec_id) { + case 0: + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 0); + break; + case 1: + /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK, 0); + break; + default: + printf("FEC%d: unsupported\n", fec_id); + return -EINVAL; + } + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + +int tq_bb_board_init(void) +{ + mba7_setup_fec(0); + + if (!is_cpu_type(MXC_CPU_MX7S)) + mba7_setup_fec(1); + + return 0; +} + +int tq_bb_board_late_init(void) +{ + puts("Boot: "); + + if (is_boot_from_usb()) { + puts("USB\n"); + env_set_runtime("boot_dev", "mmc"); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + } else { + /* + * try to get sd card slots in order: + * eMMC: on Module + * -> therefore index 0 for bootloader + * index n in kernel (controller instance 3) -> patches needed for + * alias indexing + * SD1: on Mainboard + * index n in kernel (controller instance 1) -> patches needed for + * alias indexing + * we assume to have a kernel patch that will present mmcblk dev + * indexed like controller devs + */ + enum boot_device bd = get_boot_device(); + + switch (bd) { + case MMC3_BOOT: + puts("USDHC3(eMMC)\n"); + env_set_runtime("boot_dev", "mmc"); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + break; + case SD1_BOOT: + puts("USDHC1(SD)\n"); + env_set_runtime("boot_dev", "mmc"); + env_set_runtime("mmcdev", "1"); + env_set_runtime("mmcblkdev", "1"); + break; + case QSPI_BOOT: + puts("QSPI\n"); + env_set_runtime("boot_dev", "qspi"); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + break; + default: + printf("unhandled boot device %d\n", (int)bd); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + } + } + + if (!env_get("fdtfile")) { + /* provide default setting for fdtfile if nothing in env is set */ + + switch (get_cpu_type()) { + case MXC_CPU_MX7S: + env_set_runtime("fdtfile", "imx7s-mba7.dtb"); + break; + case MXC_CPU_MX7D: + env_set_runtime("fdtfile", "imx7d-mba7.dtb"); + break; + default: + debug("unknown CPU"); + } + } + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + switch (devno) { + case 2: + /* eMMC */ + return 0; + case 0: + /* SD card */ + return 1; + default: + /* Unknown */ + return 0; + } +} + +#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 769e52bcfb5..a1d8ae26673 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -183,6 +183,23 @@ int board_init(void) zynqmppl.name = strdup(name); fpga_init(); fpga_add(fpga_xilinx, &zynqmppl); + + /* + * zu63dr_SE and zu67dr_SE share ID 0x046D7093. + * Register zu63dr_SE as alternate device. + */ + if (!strcmp(name, "zu67dr_SE")) { + xilinx_desc *alt; + + alt = calloc(1, sizeof(*alt)); + if (!alt) { + log_err("Failed to allocate alt FPGA descriptor\n"); + } else { + *alt = zynqmppl; + alt->name = "zu63dr_SE"; + fpga_add(fpga_xilinx, alt); + } + } } } #endif |