diff options
Diffstat (limited to 'board')
424 files changed, 14737 insertions, 5561 deletions
diff --git a/board/CZ.NIC/turris_1x/turris_1x.c b/board/CZ.NIC/turris_1x/turris_1x.c index 2f9557a4170..32535ed6ee0 100644 --- a/board/CZ.NIC/turris_1x/turris_1x.c +++ b/board/CZ.NIC/turris_1x/turris_1x.c @@ -42,9 +42,9 @@ int dram_init_banksize(void) static_assert(CONFIG_NR_DRAM_BANKS >= 3); - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = get_effective_memsize(); - size -= gd->bd->bi_dram[0].size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = get_effective_memsize(); + size -= gd->dram[0].size; /* Note: This address space is not mapped via TLB entries in U-Boot */ @@ -68,16 +68,16 @@ int dram_init_banksize(void) if (size > 0) { /* Free space between PCIe bus 3 MEM and NOR */ - gd->bd->bi_dram[1].start = 0xc0200000; - gd->bd->bi_dram[1].size = min(size, 0xef000000 - gd->bd->bi_dram[1].start); - size -= gd->bd->bi_dram[1].size; + gd->dram[1].start = 0xc0200000; + gd->dram[1].size = min(size, 0xef000000 - gd->dram[1].start); + size -= gd->dram[1].size; } if (size > 0) { /* Free space between NOR and NAND */ - gd->bd->bi_dram[2].start = 0xf0000000; - gd->bd->bi_dram[2].size = min(size, 0xff800000 - gd->bd->bi_dram[2].start); - size -= gd->bd->bi_dram[2].size; + gd->dram[2].start = 0xf0000000; + gd->dram[2].size = min(size, 0xff800000 - gd->dram[2].start); + size -= gd->dram[2].size; } #else puts("\n\n!!! TODO: fix sdcard >2GB RAM\n\n\n"); @@ -231,8 +231,8 @@ void ft_memory_setup(void *blob, struct bd_info *bd) if (!env_get("bootm_low") && !env_get("bootm_size")) { for (count = 0; count < CONFIG_NR_DRAM_BANKS; count++) { - start[count] = gd->bd->bi_dram[count].start; - size[count] = gd->bd->bi_dram[count].size; + start[count] = gd->dram[count].start; + size[count] = gd->dram[count].size; if (!size[count]) break; } @@ -452,13 +452,13 @@ static void recalculate_used_pcie_mem(void) size = gd->ram_size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size -= gd->bd->bi_dram[i].size; + size -= gd->dram[i].size; if (size == 0) return; e = find_law_by_addr_id(CFG_SYS_PCIE3_MEM_PHYS, LAW_TRGT_IF_PCIE_3); - if (e.index < 0 && gd->bd->bi_dram[1].size > 0) { + if (e.index < 0 && gd->dram[1].size > 0) { /* * If there is no LAW for PCIe 3 MEM then 3rd PCIe controller * is inactive, which is the case for Turris 1.0 boards. So @@ -471,8 +471,8 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(bank_size, ""); printf(" of PCIe 3 MEM for DDR RAM\n"); - gd->bd->bi_dram[1].start -= bank_size; - gd->bd->bi_dram[1].size += bank_size; + gd->dram[1].start -= bank_size; + gd->dram[1].size += bank_size; size -= bank_size; if (size == 0) return; @@ -534,9 +534,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size2, ""); printf(" of PCIe 2 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start2; - gd->bd->bi_dram[i].size = min(size, free_size2); - size -= gd->bd->bi_dram[i].start; + gd->dram[i].start = free_start2; + gd->dram[i].size = min(size, free_size2); + size -= gd->dram[i].start; i++; if (size == 0) return; @@ -548,9 +548,9 @@ static void recalculate_used_pcie_mem(void) printf("Reserving unused "); print_size(free_size1, ""); printf(" of PCIe 1 MEM for DDR RAM\n"); - gd->bd->bi_dram[i].start = free_start1; - gd->bd->bi_dram[i].size = min(size, free_size1); - size -= gd->bd->bi_dram[i].size; + gd->dram[i].start = free_start1; + gd->dram[i].size = min(size, free_size1); + size -= gd->dram[i].size; i++; if (size == 0) return; diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 7c3cea22b93..78a6d1094b5 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -111,7 +111,7 @@ void mv_phy_88e1121_init(char *name) /* command to read PHY dev address */ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { printf("Err..%s could not read PHY dev address\n", - __FUNCTION__); + __func__); return; } diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index e44b713f96d..c30fca6cffd 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -102,11 +102,6 @@ static bool is_edpu_plus(void) return false; } -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* adress of boot parameters */ diff --git a/board/Synology/common/Makefile b/board/Synology/common/Makefile index f688b549063..87be53321ee 100644 --- a/board/Synology/common/Makefile +++ b/board/Synology/common/Makefile @@ -2,4 +2,4 @@ # # Copyright (C) 2021 Phil Sutter <[email protected]> -obj-$(SUPPORT_PASSING_ATAGS) += legacy.o +obj-$(CONFIG_SUPPORT_PASSING_ATAGS) += legacy.o diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c index 2e3aa660eaa..5b7d07bc2ee 100644 --- a/board/Synology/common/legacy.c +++ b/board/Synology/common/legacy.c @@ -10,6 +10,7 @@ #include <vsprintf.h> #include <env.h> #include <net.h> +#include <asm/io.h> #include <asm/setup.h> #include "legacy.h" diff --git a/board/adi/carriers/somcrr_ezkit.c b/board/adi/carriers/somcrr_ezkit.c index 8b4d6a96c18..3cd5a6cd10b 100644 --- a/board/adi/carriers/somcrr_ezkit.c +++ b/board/adi/carriers/somcrr_ezkit.c @@ -13,13 +13,12 @@ void adi_somcrr_enable_ethernet(void) struct gpio_desc *eth1_reset; struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth1-en", ð1); - gpio_hog_lookup_name("eth1-reset", ð1_reset); - gpio_hog_lookup_name("gige-reset", &gige_reset); - - dm_gpio_set_value(eth1, 1); - dm_gpio_set_value(eth1_reset, 0); - dm_gpio_set_value(gige_reset, 0); + if (!gpio_hog_lookup_name("eth1-en", ð1)) + dm_gpio_set_value(eth1, 1); + if (!gpio_hog_lookup_name("eth1-reset", ð1_reset)) + dm_gpio_set_value(eth1_reset, 0); + if (!gpio_hog_lookup_name("gige-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 0); } void adi_somcrr_disable_ethernet(void) @@ -28,11 +27,10 @@ void adi_somcrr_disable_ethernet(void) struct gpio_desc *eth1_reset; struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth1-en", ð1); - gpio_hog_lookup_name("eth1-reset", ð1_reset); - gpio_hog_lookup_name("gige-reset", &gige_reset); - - dm_gpio_set_value(eth1, 0); - dm_gpio_set_value(eth1_reset, 1); - dm_gpio_set_value(gige_reset, 1); + if (!gpio_hog_lookup_name("eth1-en", ð1)) + dm_gpio_set_value(eth1, 0); + if (!gpio_hog_lookup_name("eth1-reset", ð1_reset)) + dm_gpio_set_value(eth1_reset, 1); + if (!gpio_hog_lookup_name("gige-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 1); } diff --git a/board/adi/carriers/somcrr_ezlite.c b/board/adi/carriers/somcrr_ezlite.c index c0655574bab..1f1984cf912 100644 --- a/board/adi/carriers/somcrr_ezlite.c +++ b/board/adi/carriers/somcrr_ezlite.c @@ -11,14 +11,14 @@ void adi_somcrr_enable_ethernet(void) { struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth0-reset", &gige_reset); - dm_gpio_set_value(gige_reset, 0); + if (!gpio_hog_lookup_name("eth0-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 0); } void adi_somcrr_disable_ethernet(void) { struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth0-reset", &gige_reset); - dm_gpio_set_value(gige_reset, 1); + if (!gpio_hog_lookup_name("eth0-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 1); } diff --git a/board/adi/sc573-ezkit/sc573-ezkit.env b/board/adi/sc573-ezkit/sc573-ezkit.env deleted file mode 100644 index 8b03a3d5da9..00000000000 --- a/board/adi/sc573-ezkit/sc573-ezkit.env +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later+ */ -/* - * (C) Copyright 2024 - Analog Devices, Inc. - */ - -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc573-ezkit.jffs2 -loadaddr=CONFIG_SC5XX_LOADADDR - -#define USE_NFS -#define USE_SPI -#define USE_RAM -#define USE_MMC - -#include <env/adi/adi_boot.env> diff --git a/board/adi/sc573-ezkit/Kconfig b/board/adi/sc573-ezlite/Kconfig index 328563c1296..f3b848ef0f7 100644 --- a/board/adi/sc573-ezkit/Kconfig +++ b/board/adi/sc573-ezlite/Kconfig @@ -2,19 +2,19 @@ # # (C) Copyright 2024 - Analog Devices, Inc. -if TARGET_SC573_EZKIT +if TARGET_SC573_EZLITE config SYS_BOARD - default "sc573-ezkit" + default "sc573-ezlite" config SYS_CONFIG_NAME - default "sc573-ezkit" + default "sc573-ezlite" config LDR_CPU default "ADSP-SC573-0.0" config DEFAULT_DEVICE_TREE - default "sc573-ezkit" + default "sc573-ezlite" config ADI_IMAGE default "tiny" diff --git a/board/adi/sc573-ezkit/Makefile b/board/adi/sc573-ezlite/Makefile index 0ea725b992b..77c55af6240 100644 --- a/board/adi/sc573-ezkit/Makefile +++ b/board/adi/sc573-ezlite/Makefile @@ -3,4 +3,4 @@ # (C) Copyright 2025 - Analog Devices, Inc. # -obj-y += sc573-ezkit.o +obj-y += sc573-ezlite.o diff --git a/board/adi/sc573-ezkit/sc573-ezkit.c b/board/adi/sc573-ezlite/sc573-ezlite.c index 464142b27a5..464142b27a5 100644 --- a/board/adi/sc573-ezkit/sc573-ezkit.c +++ b/board/adi/sc573-ezlite/sc573-ezlite.c diff --git a/board/adi/sc573-ezlite/sc573-ezlite.env b/board/adi/sc573-ezlite/sc573-ezlite.env new file mode 100644 index 00000000000..bc1fdf293c2 --- /dev/null +++ b/board/adi/sc573-ezlite/sc573-ezlite.env @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later+ */ +/* + * (C) Copyright 2024 - Analog Devices, Inc. + */ + +fdt_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_addr_r=0x84008000 +ramdisk_addr_r=0x85000000 + +#define USE_NFS +#define USE_SPI +#define USE_RAM +#define USE_MMC +#define USE_USB + +#include <env/adi/adi_boot.env> diff --git a/board/adi/sc584-ezkit/sc584-ezkit.env b/board/adi/sc584-ezkit/sc584-ezkit.env index 8a6f7edd5e8..ed25fc599a1 100644 --- a/board/adi/sc584-ezkit/sc584-ezkit.env +++ b/board/adi/sc584-ezkit/sc584-ezkit.env @@ -3,14 +3,13 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc584-ezkit.jffs2 -loadaddr=CONFIG_SC5XX_LOADADDR +fdt_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_addr_r=0x8a308000 +ramdisk_addr_r=0x8b300000 #define USE_NFS #define USE_SPI #define USE_RAM +#define USE_USB #include <env/adi/adi_boot.env> diff --git a/board/adi/sc589-ezkit/sc589-ezkit.env b/board/adi/sc589-ezkit/sc589-ezkit.env index b8206e85179..3a1af951260 100644 --- a/board/adi/sc589-ezkit/sc589-ezkit.env +++ b/board/adi/sc589-ezkit/sc589-ezkit.env @@ -3,15 +3,14 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc589-ezkit.jffs2 -loadaddr=CONFIG_SC5XX_LOADADDR +fdt_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_addr_r=0xc4008000 +ramdisk_addr_r=0xc5000000 #define USE_NFS #define USE_RAM #define USE_MMC #define USE_SPI +#define USE_USB #include <env/adi/adi_boot.env> diff --git a/board/adi/sc589-mini/sc589-mini.env b/board/adi/sc589-mini/sc589-mini.env index f7628b0b335..a21bb4e2200 100644 --- a/board/adi/sc589-mini/sc589-mini.env +++ b/board/adi/sc589-mini/sc589-mini.env @@ -3,15 +3,14 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc589-mini.jffs2 -loadaddr=CONFIG_SC5XX_LOADADDR +fdt_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_addr_r=0xc4008000 +ramdisk_addr_r=0xc5000000 #define USE_NFS #define USE_RAM #define USE_SPI #define USE_MMC +#define USE_USB #include <env/adi/adi_boot.env> diff --git a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env index 069edc717da..a8f6def9f58 100644 --- a/board/adi/sc594-som-ezkit/sc594-som-ezkit.env +++ b/board/adi/sc594-som-ezkit/sc594-som-ezkit.env @@ -3,16 +3,15 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc594-som-ezkit.jffs2 -loadaddr=CONFIG_SC5XX_LOADADDR +fdt_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_addr_r=0xa3008000 +ramdisk_addr_r=0xa8000000 #define USE_NFS #define USE_SPI #define USE_OSPI #define USE_RAM #define USE_MMC +#define USE_USB #include <env/adi/adi_boot.env> diff --git a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env index e5382b67c81..a8f6def9f58 100644 --- a/board/adi/sc594-som-ezlite/sc594-som-ezlite.env +++ b/board/adi/sc594-som-ezlite/sc594-som-ezlite.env @@ -3,16 +3,15 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc594-som-ezlite.jffs2 -loadaddr=CONFIG_SC5XX_LOADADDR +fdt_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_addr_r=0xa3008000 +ramdisk_addr_r=0xa8000000 #define USE_NFS #define USE_SPI #define USE_OSPI #define USE_RAM #define USE_MMC +#define USE_USB #include <env/adi/adi_boot.env> diff --git a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env index 2cb475e1001..da1ff295b0e 100644 --- a/board/adi/sc598-som-ezkit/sc598-som-ezkit.env +++ b/board/adi/sc598-som-ezkit/sc598-som-ezkit.env @@ -3,16 +3,15 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc598-som-ezkit.jffs2 -loadaddr=CONFIG_SC5XX_LOADADDR +fdt_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_addr_r=0x9a200000 +ramdisk_addr_r=0x9c000000 #define USE_NFS #define USE_SPI #define USE_OSPI #define USE_RAM #define USE_MMC +#define USE_USB #include <env/adi/adi_boot.env> diff --git a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env index 1d9ea6d188b..3f65fdabe18 100644 --- a/board/adi/sc598-som-ezlite/sc598-som-ezlite.env +++ b/board/adi/sc598-som-ezlite/sc598-som-ezlite.env @@ -3,10 +3,14 @@ * (C) Copyright 2024 - Analog Devices, Inc. */ -adi_stage2_offset=CONFIG_SC5XX_UBOOT_OFFSET -adi_image_offset=CONFIG_SC5XX_FITIMAGE_OFFSET -adi_rfs_offset=CONFIG_SC5XX_ROOTFS_OFFSET -loadaddr=CONFIG_SC5XX_LOADADDR -jffs2file=adsp-sc5xx-__stringify(CONFIG_ADI_IMAGE)-adsp-sc598-som-ezlite.jffs2 +fdt_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_addr_r=0x9a200000 +ramdisk_addr_r=0x9c000000 + +#define USE_NFS +#define USE_SPI +#define USE_RAM +#define USE_MMC +#define USE_USB #include <env/adi/adi_boot.env> diff --git a/board/alliedtelesis/SBx81LIFKW/Kconfig b/board/alliedtelesis/SBx81LIFKW/Kconfig index 5c2609b7f46..49516b7f007 100644 --- a/board/alliedtelesis/SBx81LIFKW/Kconfig +++ b/board/alliedtelesis/SBx81LIFKW/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "SBx81LIFKW" config SYS_VENDOR - default "alliedtelesis" + default "alliedtelesis" config SYS_CONFIG_NAME default "SBx81LIFKW" diff --git a/board/alliedtelesis/SBx81LIFXCAT/Kconfig b/board/alliedtelesis/SBx81LIFXCAT/Kconfig index 524c2900892..20e02144d3a 100644 --- a/board/alliedtelesis/SBx81LIFXCAT/Kconfig +++ b/board/alliedtelesis/SBx81LIFXCAT/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "SBx81LIFXCAT" config SYS_VENDOR - default "alliedtelesis" + default "alliedtelesis" config SYS_CONFIG_NAME default "SBx81LIFXCAT" diff --git a/board/alliedtelesis/x220/.gitattributes b/board/alliedtelesis/x220/.gitattributes new file mode 100644 index 00000000000..2aeb4eee641 --- /dev/null +++ b/board/alliedtelesis/x220/.gitattributes @@ -0,0 +1 @@ +binary.0 binary diff --git a/board/alliedtelesis/x220/.gitignore b/board/alliedtelesis/x220/.gitignore new file mode 100644 index 00000000000..775b9346b85 --- /dev/null +++ b/board/alliedtelesis/x220/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/alliedtelesis/x220/MAINTAINERS b/board/alliedtelesis/x220/MAINTAINERS new file mode 100644 index 00000000000..63da2725f71 --- /dev/null +++ b/board/alliedtelesis/x220/MAINTAINERS @@ -0,0 +1,8 @@ +x220 BOARD +M: Chris Packham <[email protected]> +S: Maintained +F: board/alliedtelesis/x220 +F: include/configs/x220.h +F: configs/x220_defconfig +F: arch/arm/dts/armada-xp-atl-x220.dts +F: doc/board/alliedtelesis/x220.rst diff --git a/board/alliedtelesis/x220/Makefile b/board/alliedtelesis/x220/Makefile new file mode 100644 index 00000000000..a74f0a76948 --- /dev/null +++ b/board/alliedtelesis/x220/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Allied Telesis Labs + +obj-y := x220.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $@)$(@F) + +SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" +$(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/alliedtelesis/x220/binary.0 b/board/alliedtelesis/x220/binary.0 new file mode 100644 index 00000000000..8dd687286a0 --- /dev/null +++ b/board/alliedtelesis/x220/binary.0 @@ -0,0 +1,11 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. diff --git a/board/alliedtelesis/x220/kwbimage.cfg.in b/board/alliedtelesis/x220/kwbimage.cfg.in new file mode 100644 index 00000000000..8beda907ba4 --- /dev/null +++ b/board/alliedtelesis/x220/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2025 Allied Telesis Labs +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/alliedtelesis/x220/binary.0 0000005b 00000068 diff --git a/board/alliedtelesis/x220/x220.c b/board/alliedtelesis/x220/x220.c new file mode 100644 index 00000000000..7c9a73de9a2 --- /dev/null +++ b/board/alliedtelesis/x220/x220.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Allied Telesis Labs + */ + +#include <i2c.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/gpio.h> +#include <linux/bitops.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define X220_GPP_OUT_ENA_LOW (~(BIT(12) | BIT(17) | BIT(18) | BIT(31))) +#define X220_GPP_OUT_ENA_MID (~(0)) +#define X220_GPP_OUT_VAL_LOW (BIT(12) | BIT(18)) +#define X220_GPP_OUT_VAL_MID 0x0 +#define X220_GPP_POL_LOW 0x0 +#define X220_GPP_POL_MID 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x44042222, MVEBU_MPP_BASE + 0x00); + writel(0x11000004, MVEBU_MPP_BASE + 0x04); + writel(0x44444004, MVEBU_MPP_BASE + 0x08); + writel(0x04444444, MVEBU_MPP_BASE + 0x0c); + writel(0x00000004, MVEBU_MPP_BASE + 0x10); + + /* Set GPP Out value */ + writel(X220_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(X220_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(X220_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(X220_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(X220_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(X220_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + /* Disable MBUS Err Prop - in order to avoid data aborts */ + clrbits_le32(MVEBU_CPU_WIN_BASE + 0x200, (1 << 8)); + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board: Allied Telesis x220\n"); + + return 0; +} +#endif diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index d94c1494d53..2afd283b8dd 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -1,17 +1,24 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ #include <cpu_func.h> +#include <dfu.h> +#include <env.h> +#include <efi_loader.h> #include <fdtdec.h> +#include <fwu.h> #include <init.h> #include <env_internal.h> #include <log.h> #include <malloc.h> +#include <memalign.h> +#include <mmc.h> +#include <mtd.h> #include <time.h> #include <asm/cache.h> #include <asm/global_data.h> @@ -22,10 +29,8 @@ #include <dm/device.h> #include <dm/uclass.h> #include <versalpl.h> -#include <zynqmp_firmware.h> #include "../../xilinx/common/board.h" -#include <linux/bitfield.h> #include <debug_uart.h> #include <generated/dt.h> #include <linux/ioport.h> @@ -54,150 +59,25 @@ int board_init(void) return 0; } -static u32 platform_id, platform_version; - -char *soc_name_decode(void) -{ - char *name, *platform_name; - - switch (platform_id) { - case VERSAL2_SPP: - platform_name = "spp"; - break; - case VERSAL2_EMU: - platform_name = "emu"; - break; - case VERSAL2_SPP_MMD: - platform_name = "spp-mmd"; - break; - case VERSAL2_EMU_MMD: - platform_name = "emu-mmd"; - break; - case VERSAL2_QEMU: - platform_name = "qemu"; - break; - default: - return NULL; - } - - /* - * --rev. are 6 chars - * max platform name is qemu which is 4 chars - * platform version number are 1+1 - * Plus 1 char for \n - */ - name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); - if (!name) - return NULL; - - sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD, - platform_name, platform_version / 10, - platform_version % 10, current_el()); - - return name; -} - -bool soc_detection(void) -{ - u32 version, ps_version; - - version = readl(PMC_TAP_VERSION); - platform_id = FIELD_GET(PLATFORM_MASK, version); - ps_version = FIELD_GET(PS_VERSION_MASK, version); - - debug("idcode %x, version %x, usercode %x\n", - readl(PMC_TAP_IDCODE), version, - readl(PMC_TAP_USERCODE)); - - debug("pmc_ver %lx, ps version %x, rtl version %lx\n", - FIELD_GET(PMC_VERSION_MASK, version), - ps_version, - FIELD_GET(RTL_VERSION_MASK, version)); - - platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); - - debug("Platform id: %d version: %d.%d\n", platform_id, - platform_version / 10, platform_version % 10); - - return true; -} - int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal2_timer_setup(); return 0; } -static u8 versal2_get_bootmode(void) -{ - u8 bootmode; - u32 reg = 0; - - reg = readl(&crp_base->boot_mode_usr); - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; - - return bootmode; -} - static u32 versal2_multi_boot(void) { u8 bootmode = versal2_get_bootmode(); - u32 reg = 0; /* Mostly workaround for QEMU CI pipeline */ if (bootmode == JTAG_MODE) return 0; - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) - reg = zynqmp_pm_get_pmc_multi_boot_reg(); - else - reg = readl(PMC_MULTI_BOOT_REG); - - return reg & PMC_MULTI_BOOT_MASK; + return versal2_pmc_multi_boot(); } static int boot_targets_setup(void) @@ -347,6 +227,10 @@ int board_late_init(void) int ret; u32 multiboot; + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && + !IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE)) + configure_capsule_updates(); + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); return 0; @@ -475,3 +359,148 @@ enum env_location env_get_location(enum env_operation op, int prio) } } #endif + +#define DFU_ALT_BUF_LEN SZ_1K + +#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && \ + !defined(CONFIG_FWU_MULTI_BANK_UPDATE) +static void mtd_found_part(u32 *base, u32 *size) +{ + struct mtd_info *part, *mtd; + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (!IS_ERR_OR_NULL(mtd)) { + list_for_each_entry(part, &mtd->partitions, node) { + debug("0x%012llx-0x%012llx : \"%s\"\n", + part->offset, part->offset + part->size, + part->name); + + if (*base >= part->offset && + *base < part->offset + part->size) { + debug("Found my partition: %d/%s\n", + part->index, part->name); + *base = part->offset; + *size = part->size; + break; + } + } + } +} + +void configure_capsule_updates(void) +{ + int bootseq = 0, len = 0; + u32 multiboot = versal2_multi_boot(); + u32 bootmode = versal2_get_bootmode(); + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + + memset(buf, 0, DFU_ALT_BUF_LEN); + + multiboot = env_get_hex("multiboot", multiboot); + + switch (bootmode) { + case EMMC_MODE: + case SD_MODE: + case SD1_LSHFT_MODE: + case SD_MODE1: + bootseq = mmc_get_env_dev(); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot", + bootseq); + + if (multiboot) + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "%04d", multiboot); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1", + bootseq); + break; + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + case OSPI_MODE: + { + u32 base = multiboot * SZ_32K; + u32 size = 0x1500000; + u32 limit = size; + + mtd_found_part(&base, &limit); + + len += snprintf(buf + len, DFU_ALT_BUF_LEN, + "sf 0:0=boot.bin raw 0x%x 0x%x", + base, limit); + } + break; + default: + return; + } + + update_info.dfu_string = strdup(buf); + debug("Capsule DFU: %s\n", update_info.dfu_string); +} +#endif + +#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) + +/* Generate dfu_alt_info from partitions */ +void set_dfu_alt_info(char *interface, char *devstr) +{ + int ret; + struct mtd_info *mtd; + + /* + * It is called multiple times for every image + * per bank that's why enough to set it up once. + */ + if (env_get("dfu_alt_info")) + return; + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + memset(buf, 0, DFU_ALT_BUF_LEN); + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (IS_ERR_OR_NULL(mtd)) + return; + + ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); + if (ret < 0) { + log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); + return; + } + log_debug("Make dfu_alt_info: '%s'\n", buf); + + env_set("dfu_alt_info", buf); +} +#endif + +int spi_get_env_dev(void) +{ + struct udevice *dev; + const char *name; + int bootseq; + + switch (versal2_get_bootmode()) { + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + name = "spi@f1030000"; + break; + case OSPI_MODE: + name = "spi@f1010000"; + break; + default: + return -1; + } + + if (uclass_get_device_by_name(UCLASS_SPI, name, &dev)) { + debug("SPI driver for %s is not present\n", name); + return -1; + } + + bootseq = dev_seq(dev); + debug("bootseq %d\n", bootseq); + return bootseq; +} diff --git a/board/apple/mac/mac.env b/board/apple/mac/mac.env new file mode 100644 index 00000000000..109379c8c67 --- /dev/null +++ b/board/apple/mac/mac.env @@ -0,0 +1,4 @@ +stdin=serial,usbkbd,spikbd +stdout=vidconsole,serial +stderr=vidconsole,serial +boot_targets=nvme usb diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 8cfac9fbb34..4a2349e165b 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -218,7 +218,7 @@ static void set_gpr_register(void) int board_early_init_f(void) { - select_ldb_di_clock_source(MXC_PLL5_CLK); + select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); set_gpr_register(); /* diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 16d0e679c3e..eb0f9c06849 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -86,8 +86,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index eaf87e3bfe3..6cd24bf25fb 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -137,7 +137,7 @@ int misc_init_r (void) int dram_init (void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -170,7 +170,7 @@ extern void dram_query(void); PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ /* We only have one bank of RAM, set it to whatever was detected */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 12bb6defab2..057e916ab1b 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -89,9 +89,9 @@ void build_mem_map(void) * The first node is for I/O device, start from node 1 for * updating DRAM info. */ - mem_map[i + 1].virt = gd->bd->bi_dram[i].start; - mem_map[i + 1].phys = gd->bd->bi_dram[i].start; - mem_map[i + 1].size = gd->bd->bi_dram[i].size; + mem_map[i + 1].virt = gd->dram[i].start; + mem_map[i + 1].phys = gd->dram[i].start; + mem_map[i + 1].size = gd->dram[i].size; mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE; } diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 3833af59b09..87e53f64e06 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -79,11 +79,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); return 0; diff --git a/board/aspeed/evb_ast2700/Kconfig b/board/aspeed/evb_ast2700/Kconfig new file mode 100644 index 00000000000..ede9eb7fb85 --- /dev/null +++ b/board/aspeed/evb_ast2700/Kconfig @@ -0,0 +1,13 @@ +if TARGET_EVB_AST2700 + +config SYS_BOARD + default "evb_ast2700" + +config SYS_VENDOR + default "aspeed" + +config SYS_CONFIG_NAME + string "board configuration name" + default "evb_ast2700" + +endif diff --git a/board/aspeed/evb_ast2700/Makefile b/board/aspeed/evb_ast2700/Makefile new file mode 100644 index 00000000000..0c29700f5a9 --- /dev/null +++ b/board/aspeed/evb_ast2700/Makefile @@ -0,0 +1 @@ +obj-y += evb_ast2700.o diff --git a/board/aspeed/evb_ast2700/evb_ast2700.c b/board/aspeed/evb_ast2700/evb_ast2700.c new file mode 100644 index 00000000000..b34aa6e1682 --- /dev/null +++ b/board/aspeed/evb_ast2700/evb_ast2700.c @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 48aec652c4a..07fbafba433 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -71,13 +71,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 5d7a18379fa..eb5d98ad566 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -139,13 +139,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { #ifdef CONFIG_AT91SAM9G10EK diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 2b0b01798ea..3b272e3ffa1 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -83,13 +83,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* arch number of AT91SAM9263EK-Board */ diff --git a/board/atmel/at91sam9m10g45ek/MAINTAINERS b/board/atmel/at91sam9m10g45ek/MAINTAINERS index 54632c36d6e..4a3dcd402dd 100644 --- a/board/atmel/at91sam9m10g45ek/MAINTAINERS +++ b/board/atmel/at91sam9m10g45ek/MAINTAINERS @@ -1,5 +1,5 @@ AT91SAM9M10G45EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/at91sam9m10g45ek/ F: include/configs/at91sam9m10g45ek.h diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index d94904366ed..d07b5196bc3 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -155,13 +155,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* arch number of AT91SAM9M10G45EK-Board */ diff --git a/board/atmel/at91sam9n12ek/MAINTAINERS b/board/atmel/at91sam9n12ek/MAINTAINERS index 0d33340d87a..86781af2e7e 100644 --- a/board/atmel/at91sam9n12ek/MAINTAINERS +++ b/board/atmel/at91sam9n12ek/MAINTAINERS @@ -1,5 +1,5 @@ AT91SAM9N12EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/at91sam9n12ek/ F: include/configs/at91sam9n12ek.h diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 2cddc2175ac..6105e51c9ec 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -89,13 +89,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 214e917381e..d21dfea50f3 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -81,13 +81,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* arch number of AT91SAM9RLEK-Board */ diff --git a/board/atmel/at91sam9x5ek/MAINTAINERS b/board/atmel/at91sam9x5ek/MAINTAINERS index 51d2237ee6c..33c102bf7b3 100644 --- a/board/atmel/at91sam9x5ek/MAINTAINERS +++ b/board/atmel/at91sam9x5ek/MAINTAINERS @@ -1,5 +1,5 @@ AT91SAM9X5EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/at91sam9x5ek/ F: include/configs/at91sam9x5ek.h diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 3f41fb1c983..0cbb50a0621 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -102,13 +102,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* arch number of AT91SAM9X5EK-Board */ diff --git a/board/atmel/common/video_display.c b/board/atmel/common/video_display.c index 77188820581..7cb492b2da6 100644 --- a/board/atmel/common/video_display.c +++ b/board/atmel/common/video_display.c @@ -40,7 +40,7 @@ int at91_video_show_board_info(void) dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; + dram_size += gd->dram[i].size; nand_size = 0; #ifdef CONFIG_NAND_ATMEL diff --git a/board/atmel/sam9x60_curiosity/MAINTAINERS b/board/atmel/sam9x60_curiosity/MAINTAINERS index 0d9369e0272..519aca696de 100644 --- a/board/atmel/sam9x60_curiosity/MAINTAINERS +++ b/board/atmel/sam9x60_curiosity/MAINTAINERS @@ -1,6 +1,6 @@ SAM9X60 CURIOSITY BOARD M: Durai Manickam KR <[email protected]> -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sam9x60_curiosity/ F: include/configs/sam9x60_curiosity.h diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index 3393478e4c8..b19ae3b4b03 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -51,11 +51,6 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - #define MAC24AA_MAC_OFFSET 0xfa #ifdef CONFIG_MISC_INIT_R @@ -71,7 +66,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS index d209249c2ef..5e9edd2265f 100644 --- a/board/atmel/sam9x60ek/MAINTAINERS +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -1,6 +1,6 @@ SAM9X60EK BOARD M: Sandeep Sheriker M <[email protected]> -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sam9x60ek/ F: include/configs/sam9x60ek.h diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 2e5073f02b3..64354e5b5fc 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -49,13 +49,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - #define MAC24AA_MAC_OFFSET 0xfa #ifdef CONFIG_MISC_INIT_R diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c index 4e7c5667e21..5c35239a90a 100644 --- a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -42,15 +42,10 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS index ba2f31e6c4d..9f24c578f9e 100644 --- a/board/atmel/sama5d27_som1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D27 SOM1 EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d27_som1_ek/ F: include/configs/sama5d27_som1_ek.h diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index bf54fc33df4..33ae6a76bf7 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -61,17 +61,10 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS index ff68cf01a34..ea3b4b27579 100644 --- a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS @@ -1,6 +1,6 @@ SAMA5D27 WLSOM1 EK BOARD M: Nicolas Ferre <[email protected]> -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d27_wlsom1_ek/ F: include/configs/sama5d27_wlsom1_ek.h diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 897fab58eba..0e2d5592753 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -55,17 +55,10 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c index 8759ff6f01a..1a17db1bd5b 100644 --- a/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c +++ b/board/atmel/sama5d29_curiosity/sama5d29_curiosity.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d2_icp/MAINTAINERS b/board/atmel/sama5d2_icp/MAINTAINERS index 4a65c65ec3b..d668aa26260 100644 --- a/board/atmel/sama5d2_icp/MAINTAINERS +++ b/board/atmel/sama5d2_icp/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D2 ICP BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d2_icp/ F: include/configs/sama5d2_icp.h diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 113bd2feb62..d159ad6f4ca 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -46,11 +46,6 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* address of boot parameters */ diff --git a/board/atmel/sama5d2_ptc_ek/MAINTAINERS b/board/atmel/sama5d2_ptc_ek/MAINTAINERS index 9f82d9a3d82..95a57b2a996 100644 --- a/board/atmel/sama5d2_ptc_ek/MAINTAINERS +++ b/board/atmel/sama5d2_ptc_ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D2 PTC EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> M: Ludovic Desroches <[email protected]> S: Maintained F: board/atmel/sama5d2_ptc_ek/ diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 438829df82d..29fa88ff411 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -105,13 +105,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* address of boot parameters */ diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS index 88e327f81cd..0c4e74b2dd4 100644 --- a/board/atmel/sama5d2_xplained/MAINTAINERS +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D2 XPLAINED BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d2_xplained/ F: include/configs/sama5d2_xplained.h diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index eca5b2bf107..b48e8fe7697 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -60,17 +60,10 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; rgb_leds_init(); diff --git a/board/atmel/sama5d3_xplained/MAINTAINERS b/board/atmel/sama5d3_xplained/MAINTAINERS index 69b4ee8a33b..4979545dbc9 100644 --- a/board/atmel/sama5d3_xplained/MAINTAINERS +++ b/board/atmel/sama5d3_xplained/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D3_XPLAINED BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d3_xplained/ F: include/configs/sama5d3_xplained.h diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 7a813c19ff2..e12f2883cec 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -84,13 +84,6 @@ int board_late_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/sama5d3xek/MAINTAINERS b/board/atmel/sama5d3xek/MAINTAINERS index e8ec275d71d..a1c96bfea84 100644 --- a/board/atmel/sama5d3xek/MAINTAINERS +++ b/board/atmel/sama5d3xek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D3XEK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d3xek/ F: include/configs/sama5d3xek.h diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 555a8c0970b..405c9c50321 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -137,13 +137,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/sama5d4_xplained/MAINTAINERS b/board/atmel/sama5d4_xplained/MAINTAINERS index 9fd0ad7bc2b..43fc23ef814 100644 --- a/board/atmel/sama5d4_xplained/MAINTAINERS +++ b/board/atmel/sama5d4_xplained/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D4 XPLAINED ULTRA BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d4_xplained/ F: include/configs/sama5d4_xplained.h diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index e296b0466aa..5894e7a654d 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -99,13 +99,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - #define AT24MAC_MAC_OFFSET 0x9a #ifdef CONFIG_MISC_INIT_R diff --git a/board/atmel/sama5d4ek/MAINTAINERS b/board/atmel/sama5d4ek/MAINTAINERS index f715af6401b..757be21b96a 100644 --- a/board/atmel/sama5d4ek/MAINTAINERS +++ b/board/atmel/sama5d4ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D4EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d4ek/ F: include/configs/sama5d4ek.h diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index e820605d3b9..7418369c5ba 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -97,13 +97,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c index 713b1b9d959..cdf2793b643 100644 --- a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -49,15 +49,10 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; board_leds_init(); diff --git a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c index b05c9754c96..02543d8e99f 100644 --- a/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c +++ b/board/atmel/sama7g54_curiosity/sama7g54_curiosity.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { // Address of boot parameters - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/atmel/sama7g5ek/MAINTAINERS b/board/atmel/sama7g5ek/MAINTAINERS index eac972968d7..4d1c6f666c0 100644 --- a/board/atmel/sama7g5ek/MAINTAINERS +++ b/board/atmel/sama7g5ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA7G5 EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama7g5ek.c F: include/configs/sama7g5ek.h diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index c07115a2119..5409ed2375d 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -46,11 +46,6 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - #define MAC24AA_MAC_OFFSET 0xfa #if (IS_ENABLED(CONFIG_MISC_INIT_R)) diff --git a/board/axiado/scm3005/Kconfig b/board/axiado/scm3005/Kconfig new file mode 100644 index 00000000000..d6f4f311f55 --- /dev/null +++ b/board/axiado/scm3005/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SCM3005 + +config SYS_BOARD + string + default "scm3005" + +config SYS_VENDOR + string + default "axiado" + +config SYS_CONFIG_NAME + string + default "ax3005-scm3005" + +endif diff --git a/board/axiado/scm3005/Makefile b/board/axiado/scm3005/Makefile new file mode 100644 index 00000000000..3d35713bab9 --- /dev/null +++ b/board/axiado/scm3005/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + +obj-y := scm3005.o diff --git a/board/axiado/scm3005/scm3005.c b/board/axiado/scm3005/scm3005.c new file mode 100644 index 00000000000..b2df6d89cd8 --- /dev/null +++ b/board/axiado/scm3005/scm3005.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates). + */ + +#include <config.h> +#include <dm.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <asm/spin_table.h> +#include <asm/system.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region axiado_ax3005_mem_map[] = { + { /* Peripherals including UART */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x4A000000UL, /* 0 to 0x4A000000: peripherals */ + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + { .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, + { + 0, + } +}; + +struct mm_region *mem_map = axiado_ax3005_mem_map; + +/* + * Accept any FIT configuration name - the board loads a single FIT image + * and the first matching config is used. + */ +int board_fit_config_name_match(const char *name) +{ + return 0; +} + +/* + * ft_board_setup - restore cpu-release-addr after relocation + * + * arch_fixup_fdt() / spin_table_update_dt() overwrites cpu-release-addr + * with U-Boot's relocated address. Restore the pre-relocation physical + * address so secondary cores spin on the correct location. + */ +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int cpus_offset, offset; + const char *prop; + int ret; + u64 cpu_release_addr = (u64)&spin_table_cpu_release_addr - gd->reloc_off; + + cpus_offset = fdt_path_offset(blob, "/cpus"); + if (cpus_offset < 0) + return 0; + + for (offset = fdt_first_subnode(blob, cpus_offset); offset >= 0; + offset = fdt_next_subnode(blob, offset)) { + prop = fdt_getprop(blob, offset, "device_type", NULL); + if (!prop || strcmp(prop, "cpu")) + continue; + + prop = fdt_getprop(blob, offset, "enable-method", NULL); + if (!prop || strcmp(prop, "spin-table")) + continue; + + ret = fdt_setprop_u64(blob, offset, "cpu-release-addr", + cpu_release_addr); + if (ret) { + printf("WARNING: Failed to restore cpu-release-addr\n"); + return ret; + } + } + + return 0; +} + +/* + * dram_init - DDR is initialized by firmware, just setting size + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); + return 0; +} + +/* + * the SOC uses single bank, non-interleaving + */ +int dram_init_banksize(void) +{ + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; + return 0; +} + +/* + * timer_init - enable the AX3005 platform system timer + * + * CNTFRQ_EL0 is already set by arch/arm/cpu/armv8/start.S using + * CONFIG_COUNTER_FREQUENCY from the defconfig. + * + * SYS_TIMER_CTRL (0x48016000) is the AX3005 system timer control + * register — writing SYS_TIMER_ENABLE starts the counter that feeds + * the ARM generic timer. + */ +int timer_init(void) +{ + writel(SYS_TIMER_ENABLE, SYS_TIMER_CTRL); + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + /* For later ARM_PSCI_FW or watchdog reset */ +} diff --git a/board/beacon/imx8mp/imx8mp_beacon.c b/board/beacon/imx8mp/imx8mp_beacon.c index dd74e7c0f75..541a4b00eba 100644 --- a/board/beacon/imx8mp/imx8mp_beacon.c +++ b/board/beacon/imx8mp/imx8mp_beacon.c @@ -14,7 +14,7 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -#if IS_ENABLED(CONFIG_NET) +#if IS_ENABLED(CONFIG_NET_LEGACY) int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) diff --git a/board/beagle/beagleboneai64/Kconfig b/board/beagle/beagleboneai64/Kconfig index 0f21582614d..7d7077e9f28 100644 --- a/board/beagle/beagleboneai64/Kconfig +++ b/board/beagle/beagleboneai64/Kconfig @@ -34,7 +34,7 @@ config SYS_BOARD default "beagleboneai64" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME default "beagleboneai64" @@ -49,7 +49,7 @@ config SYS_BOARD default "beagleboneai64" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME default "beagleboneai64" diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig index 592b53e493c..fcc6a5aa496 100644 --- a/board/beagle/beagleplay/Kconfig +++ b/board/beagle/beagleplay/Kconfig @@ -30,13 +30,13 @@ endchoice if TARGET_AM625_A53_BEAGLEPLAY config SYS_BOARD - default "beagleplay" + default "beagleplay" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME - default "beagleplay" + default "beagleplay" source "board/ti/common/Kconfig" @@ -45,13 +45,13 @@ endif if TARGET_AM625_R5_BEAGLEPLAY config SYS_BOARD - default "beagleplay" + default "beagleplay" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME - default "beagleplay" + default "beagleplay" config SPL_LDSCRIPT default "arch/arm/mach-omap2/u-boot-spl.lds" diff --git a/board/beagle/beagley-ai/Kconfig b/board/beagle/beagley-ai/Kconfig index bf953982151..07aedc2ea3f 100644 --- a/board/beagle/beagley-ai/Kconfig +++ b/board/beagle/beagley-ai/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "beagley-ai" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME default "beagley_ai" diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README index 0b59289e7f0..114f81f1d1a 100644 --- a/board/boundary/nitrogen6x/README +++ b/board/boundary/nitrogen6x/README @@ -17,7 +17,7 @@ and saving the environment to SPI NOR. It does not support 'boot from SD' at offset 0x400 except through the 'bmode' command. - http://lists.denx.de/pipermail/u-boot/2012-August/131151.html + https://patch.msgid.link/[email protected]/ 2. Boots using 6x_bootscript on SATA or SD card ----------------------------------------------- diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 1adee9a461f..e45db109f4f 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -909,8 +909,10 @@ static const struct boot_mode board_boot_modes[] = { int misc_init_r(void) { +#if defined(CONFIG_VIDEO_IPUV3) gpio_request(RGB_BACKLIGHT_GP, "lvds backlight"); gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight"); +#endif gpio_request(GP_USB_OTG_PWR, "usbotg power"); gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset"); gpio_request(IMX_GPIO_NR(2, 2), "back"); diff --git a/board/broadcom/bcmns3/ns3.c b/board/broadcom/bcmns3/ns3.c index bb2f1e4f62a..2683f46f41c 100644 --- a/board/broadcom/bcmns3/ns3.c +++ b/board/broadcom/bcmns3/ns3.c @@ -176,8 +176,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M); - gd->bd->bi_dram[0].size = SZ_16M; + gd->dram[0].start = (BCM_NS3_MEM_END - SZ_16M); + gd->dram[0].size = SZ_16M; return 0; } diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 40047cf6783..5bc4d3248bd 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -666,34 +666,34 @@ int misc_init_r(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[1].start = PHYS_SDRAM_2; switch (gd->ram_size) { case 0x10000000: /* DDR_16BIT_256MB */ - gd->bd->bi_dram[0].size = 0x10000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x10000000; + gd->dram[1].size = 0; break; case 0x20000000: /* DDR_32BIT_512MB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0; break; case 0x40000000: if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */ - gd->bd->bi_dram[0].size = 0x20000000; - gd->bd->bi_dram[1].size = 0x20000000; + gd->dram[0].size = 0x20000000; + gd->dram[1].size = 0x20000000; } else { /* DDR_64BIT_1GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0; } break; case 0x80000000: /* DDR_64BIT_2GB */ - gd->bd->bi_dram[0].size = 0x40000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[0].size = 0x40000000; + gd->dram[1].size = 0x40000000; break; case 0xEFF00000: /* DDR_64BIT_4GB */ - gd->bd->bi_dram[0].size = 0x70000000; - gd->bd->bi_dram[1].size = 0x7FF00000; + gd->dram[0].size = 0x70000000; + gd->dram[1].size = 0x7FF00000; break; } @@ -778,7 +778,7 @@ static int sata_imx_remove(struct udevice *dev) return 0; } -struct ahci_ops sata_imx_ops = { +static const struct ahci_ops sata_imx_ops = { .port_status = dwc_ahsata_port_status, .reset = dwc_ahsata_bus_reset, .scan = dwc_ahsata_scan, diff --git a/board/cortina/common/Kconfig b/board/cortina/common/Kconfig index 00c709e70f0..bf5229abd75 100644 --- a/board/cortina/common/Kconfig +++ b/board/cortina/common/Kconfig @@ -1,6 +1,6 @@ config CORTINA_PLATFORM - bool "Cortina-Access Platform" - default y - help - Select this option for Cortina-Access platforms - to enables selection of CAxxxx drivers + bool "Cortina-Access Platform" + default y + help + Select this option for Cortina-Access platforms + to enables selection of CAxxxx drivers diff --git a/board/cortina/presidio-asic/Kconfig b/board/cortina/presidio-asic/Kconfig index 8e6f6cfa27c..7bf8b78742a 100644 --- a/board/cortina/presidio-asic/Kconfig +++ b/board/cortina/presidio-asic/Kconfig @@ -1,7 +1,7 @@ if TARGET_PRESIDIO_ASIC config BIT64 bool - default y + default y select SOC_CA7774 diff --git a/board/dhelectronics/common/dh_imx.c b/board/dhelectronics/common/dh_imx.c index 3d6487dd0d8..50404a66f9d 100644 --- a/board/dhelectronics/common/dh_imx.c +++ b/board/dhelectronics/common/dh_imx.c @@ -10,13 +10,13 @@ #include <net.h> #include "dh_imx.h" -int dh_imx_get_mac_from_fuse(unsigned char *enetaddr) +int dh_imx_get_mac_from_fuse(unsigned char *enetaddr, int index) { /* * If IIM fuses contain valid MAC address, use it. * The IIM MAC address fuses are NOT programmed by default. */ - imx_get_mac_from_fuse(0, enetaddr); + imx_get_mac_from_fuse(index, enetaddr); if (!is_valid_ethaddr(enetaddr)) return -EINVAL; diff --git a/board/dhelectronics/common/dh_imx.h b/board/dhelectronics/common/dh_imx.h index 284f8637fb8..be2ff5e076c 100644 --- a/board/dhelectronics/common/dh_imx.h +++ b/board/dhelectronics/common/dh_imx.h @@ -7,6 +7,7 @@ * dh_imx_get_mac_from_fuse - Get MAC address from fuse and write it to env * * @enetaddr: buffer where address is to be stored + * @index: index of MAC address in fuse (starts with 0) * Return: 0 if OK, other value on error */ -int dh_imx_get_mac_from_fuse(unsigned char *enetaddr); +int dh_imx_get_mac_from_fuse(unsigned char *enetaddr, int index); diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index 234824b38c2..c9e8107685a 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -94,7 +94,7 @@ int dh_setup_mac_address(struct eeprom_id_page *eip) if (dh_get_mac_is_enabled("ethernet0")) return 0; - if (!dh_imx_get_mac_from_fuse(enetaddr)) + if (!dh_imx_get_mac_from_fuse(enetaddr, 0)) goto out; if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0")) diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 3424be10936..486073392e9 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -47,7 +47,7 @@ static int dh_imx8_setup_ethaddr(struct eeprom_id_page *eip) if (dh_get_mac_is_enabled("ethernet0")) return 0; - if (!dh_imx_get_mac_from_fuse(enetaddr)) + if (!dh_imx_get_mac_from_fuse(enetaddr, 0)) goto out; if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip)) @@ -72,8 +72,8 @@ static int dh_imx8_setup_eth1addr(struct eeprom_id_page *eip) if (dh_get_mac_is_enabled("ethernet1")) return 0; - if (!dh_imx_get_mac_from_fuse(enetaddr)) - goto increment_out; + if (!dh_imx_get_mac_from_fuse(enetaddr, 1)) + goto out; if (!dh_get_value_from_eeprom_buffer(DH_MAC1, enetaddr, sizeof(enetaddr), eip)) goto out; diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS b/board/edgeble/neural-compute-module-6/MAINTAINERS index 42e5df506bf..97d8c96ae62 100644 --- a/board/edgeble/neural-compute-module-6/MAINTAINERS +++ b/board/edgeble/neural-compute-module-6/MAINTAINERS @@ -5,9 +5,5 @@ F: board/edgeble/neural-compute-module-6 F: include/configs/neural-compute-module-6.h F: configs/neu6a-io-rk3588_defconfig F: configs/neu6b-io-rk3588_defconfig -F: arch/arm/dts/rk3588-edgeble-neu6a.dtsi -F: arch/arm/dts/rk3588-edgeble-neu6a-io.dts -F: arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi -F: arch/arm/dts/rk3588-edgeble-neu6b.dtsi -F: arch/arm/dts/rk3588-edgeble-neu6b-io.dts -F: arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi +F: arch/arm/dts/rk3588-edgeble-neu6a-io* +F: arch/arm/dts/rk3588-edgeble-neu6b-io* diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 9fea4f86d5a..33f7ec6d048 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -66,8 +66,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0x60000000; - gd->bd->bi_dram[0].size = 0x8000000; + gd->dram[0].start = 0x60000000; + gd->dram[0].size = 0x8000000; return 0; } diff --git a/board/emulation/qemu-m68k/qemu-m68k.c b/board/emulation/qemu-m68k/qemu-m68k.c index d3527aee112..a19b23a28ce 100644 --- a/board/emulation/qemu-m68k/qemu-m68k.c +++ b/board/emulation/qemu-m68k/qemu-m68k.c @@ -14,9 +14,14 @@ #include <asm/bootinfo.h> #include <asm/global_data.h> #include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> #include <dm/platdata.h> +#include <dm/root.h> #include <linux/errno.h> #include <linux/sizes.h> +#include <virtio_mmio.h> DECLARE_GLOBAL_DATA_PTR; @@ -25,6 +30,38 @@ static struct goldfish_rtc_plat rtc_plat; static struct goldfish_timer_plat timer_plat; static struct qemu_virt_ctrl_plat reset_plat; +#define VIRTIO_MMIO_NUM 128 +#define VIRTIO_MMIO_SZ 0x200 + +static struct virtio_mmio_plat virtio_mmio_plat[VIRTIO_MMIO_NUM]; +static char virtio_mmio_names[VIRTIO_MMIO_NUM][11]; +static phys_addr_t virtio_mmio_base; + +static int create_virtio_mmios(void) +{ + struct driver *drv; + int i, ret; + + if (!virtio_mmio_base) + return -ENODEV; + + drv = lists_driver_lookup_name("virtio-mmio"); + if (!drv) + return -ENOENT; + + for (i = 0; i < VIRTIO_MMIO_NUM; i++) { + virtio_mmio_plat[i].base = virtio_mmio_base + (VIRTIO_MMIO_SZ * i); + sprintf(virtio_mmio_names[i], "virtio-%d", i); + + ret = device_bind(dm_root(), drv, virtio_mmio_names[i], + &virtio_mmio_plat[i], ofnode_null(), NULL); + if (ret) + return ret; + } + + return 0; +} + /* * Theoretical limit derivation: * Max Bootinfo Size (Standard Page) = 4096 bytes @@ -65,6 +102,9 @@ static void parse_bootinfo(void) case BI_VIRT_CTRL_BASE: reset_plat.reg = base; break; + case BI_VIRT_VIRTIO_BASE: + virtio_mmio_base = base; + break; case BI_MEMCHUNK: gd->ram_size = record->data[1]; break; @@ -80,6 +120,11 @@ int board_early_init_f(void) return 0; } +int board_early_init_r(void) +{ + return create_virtio_mmios(); +} + int checkboard(void) { puts("Board: QEMU m68k virt\n"); diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c index 864afa92aee..547cfa3a35f 100644 --- a/board/engicam/imx8mp/icore_mx8mp.c +++ b/board/engicam/imx8mp/icore_mx8mp.c @@ -30,7 +30,7 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP) +#if CONFIG_IS_ENABLED(NET) int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) diff --git a/board/engicam/stm32mp1/spl.c b/board/engicam/stm32mp1/spl.c index bb2bd446aa8..19e5ab0180f 100644 --- a/board/engicam/stm32mp1/spl.c +++ b/board/engicam/stm32mp1/spl.c @@ -15,9 +15,3 @@ void board_vddcore_init(u32 voltage_mv) if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) opp_voltage_mv = voltage_mv; } - -int board_early_init_f(void) -{ - return 0; -} - diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index dce69abdfd1..3d76c936073 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -141,8 +141,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/firefly/roc-pc-rk3399/Kconfig b/board/firefly/roc-pc-rk3399/Kconfig index c211e9d3c79..b800f7d2102 100644 --- a/board/firefly/roc-pc-rk3399/Kconfig +++ b/board/firefly/roc-pc-rk3399/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "roc-pc-rk3399" config SYS_VENDOR - default "firefly" + default "firefly" config SYS_CONFIG_NAME default "roc-pc-rk3399" diff --git a/board/freebox/nbx10g/Kconfig b/board/freebox/nbx10g/Kconfig new file mode 100644 index 00000000000..958c8fdd4c3 --- /dev/null +++ b/board/freebox/nbx10g/Kconfig @@ -0,0 +1,94 @@ +if TARGET_NBX10G + +config SYS_BOARD + default "nbx10g" + +config SYS_VENDOR + default "freebox" + +config SYS_CONFIG_NAME + default "nbx10g" + +config CMD_NBX_EMMCBOOT + bool "emmcboot command" + depends on MMC_SDHCI_XENON + help + Enable the emmcboot command for dual-bank boot from eMMC. + This is a legacy boot format used on this board for many years. + It implements a boot system with two image banks and automatic + fallback on boot failures. The boot order depends on a reboot + tracking counter (nrboot): + - If healthy: try Bank1 (newer) first, then Bank0 (stable) + - If degraded (>= 4 failures): try Bank0 first, then Bank1 + + Requires image_addr and fdt_addr environment variables to be set. + +if CMD_NBX_EMMCBOOT + +config NBX_MMC_PART_NRBOOT_OFFSET + hex "NRBoot counter offset in eMMC" + default 0x802000 + help + Byte offset in eMMC where the reboot tracking counter is stored. + Default: 0x802000 (8MB + 8KB) + +config NBX_MMC_PART_BANK0_OFFSET + hex "Bank0 image offset in eMMC" + default 0x804000 + help + Byte offset in eMMC where the stable (Bank0) boot image starts. + Default: 0x804000 (8MB + 16KB) + +config NBX_MMC_PART_BANK0_SIZE + hex "Bank0 image maximum size" + default 0x10000000 + help + Maximum size of the Bank0 boot image. + Default: 0x10000000 (256MB) + +config NBX_MMC_PART_BANK1_OFFSET + hex "Bank1 image offset in eMMC" + default 0x10804000 + help + Byte offset in eMMC where the newer (Bank1) boot image starts. + Default: 0x10804000 (264MB + 16KB) + +config NBX_MMC_PART_BANK1_SIZE + hex "Bank1 image maximum size" + default 0x10000000 + help + Maximum size of the Bank1 boot image. + Default: 0x10000000 (256MB) + +endif + +config CMD_NBX_FBXSERIAL + bool "fbxserial command" + depends on MMC_SDHCI_XENON + help + Enable the fbxserial command to read and display device + serial information from eMMC. This includes: + - Device serial number (type, version, manufacturer, date, number) + - MAC address (used to set ethaddr environment variables) + - Bundle information (if present) + + The serial info is stored at a fixed offset in the eMMC user area. + + Subcommands: + - fbxserial show: display serial info (default) + - fbxserial init: initialize ethaddr from serial info + + Use CONFIG_PREBOOT="fbxserial init" to auto-initialize at boot. + +if CMD_NBX_FBXSERIAL + +config NBX_MMC_PART_SERIAL_OFFSET + hex "Serial info offset in eMMC" + default 0x800000 + help + Byte offset in eMMC where the serial info structure is stored. + Default: 0x800000 (8MB) + +endif + +endif diff --git a/board/freebox/nbx10g/MAINTAINERS b/board/freebox/nbx10g/MAINTAINERS new file mode 100644 index 00000000000..2e31eed45b9 --- /dev/null +++ b/board/freebox/nbx10g/MAINTAINERS @@ -0,0 +1,6 @@ +NBX10G BOARD +M: Vincent Jardin <[email protected]> +S: Maintained +F: board/freebox/nbx10g/ +F: configs/mvebu_nbx_88f8040_defconfig +F: arch/arm/dts/armada-8040-nbx* diff --git a/board/freebox/nbx10g/Makefile b/board/freebox/nbx10g/Makefile new file mode 100644 index 00000000000..4b70d94e14d --- /dev/null +++ b/board/freebox/nbx10g/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := board.o +obj-$(CONFIG_CMD_NBX_EMMCBOOT) += nbx_emmcboot.o +obj-$(CONFIG_CMD_NBX_FBXSERIAL) += nbx_fbxserial.o diff --git a/board/freebox/nbx10g/board.c b/board/freebox/nbx10g/board.c new file mode 100644 index 00000000000..7d16010ec7e --- /dev/null +++ b/board/freebox/nbx10g/board.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2018 Freebox SA + * Copyright (C) 2026 Free Mobile, Vincent Jardin <[email protected]> + * + * Freebox Nodebox 10G board support + */ + +#include <init.h> +#include <asm/gpio.h> +#include <linux/delay.h> + +/* Management PHY reset GPIO */ +#define NBX_PHY_RESET_GPIO 83 + +/* Nodebox 10G ASCII art logo */ +static const char * const nbx_logo = + " _ _ _ _ __ ___ _____\n" + " | \\ | | | | | | /_ |/ _ \\ / ____|\n" + " | \\| | ___ __| | ___| |__ _____ __ | | | | | | __\n" + " | . ` |/ _ \\ / _` |/ _ \\ '_ \\ / _ \\ \\/ / | | | | | | |_ |\n" + " | |\\ | (_) | (_| | __/ |_) | (_) > < | | |_| | |__| |\n" + " |_| \\_|\\___/ \\__,_|\\___|_.__/ \\___/_/\\_\\ |_|\\___/ \\_____|\n"; + +int checkboard(void) +{ + printf("%s\n", nbx_logo); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + int ret; + + /* Reset the management PHY */ + ret = gpio_request(NBX_PHY_RESET_GPIO, "phy-reset"); + if (ret) { + printf("Failed to request PHY reset GPIO: %d\n", ret); + return 0; + } + + gpio_direction_output(NBX_PHY_RESET_GPIO, 0); + mdelay(100); + gpio_set_value(NBX_PHY_RESET_GPIO, 1); + mdelay(100); + + return 0; +} diff --git a/board/freebox/nbx10g/nbx_emmcboot.c b/board/freebox/nbx10g/nbx_emmcboot.c new file mode 100644 index 00000000000..0bea96fadd9 --- /dev/null +++ b/board/freebox/nbx10g/nbx_emmcboot.c @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nodebox 10G dual-bank eMMC boot command with automatic fallback + * + * Copyright (C) 2026 Free Mobile, Freebox + * + * This implements a dual-bank boot system with automatic fallback: + * - Bank0: Stable/fallback boot image + * - Bank1: Newer/test boot image + * + * The boot order depends on the reboot tracking counter (nrboot): + * - If healthy: try Bank1 first, then Bank0 + * - If degraded (>= 4 failures): try Bank0 first, then Bank1 + */ + +#include <command.h> +#include <env.h> +#include <mmc.h> +#include <malloc.h> +#include <memalign.h> +#include <vsprintf.h> +#include <u-boot/crc.h> +#include <u-boot/schedule.h> +#include <asm/byteorder.h> +#include <linux/errno.h> +#include "nbx_imagetag.h" +#include "nbx_nrboot.h" + +/* Partition offsets defined in Kconfig (CONFIG_NBX_MMC_PART_*) */ + +/* Image Tag Functions */ + +static int mvebu_imagetag_check(struct mvebu_image_tag *tag, + unsigned long maxsize, const char *name) +{ + if (be32_to_cpu(tag->magic) != MVEBU_IMAGE_TAG_MAGIC) { + if (name) + printf("%s: invalid TAG magic: %.8x\n", name, + be32_to_cpu(tag->magic)); + return -EINVAL; + } + + if (be32_to_cpu(tag->version) != MVEBU_IMAGE_TAG_VERSION) { + if (name) + printf("%s: invalid TAG version: %.8x\n", name, + be32_to_cpu(tag->version)); + return -EINVAL; + } + + if (be32_to_cpu(tag->total_size) < sizeof(*tag)) { + if (name) + printf("%s: tag size is too small!\n", name); + return -EINVAL; + } + + if (be32_to_cpu(tag->total_size) > maxsize) { + if (name) + printf("%s: tag size is too big!\n", name); + return -EINVAL; + } + + if (be32_to_cpu(tag->device_tree_offset) < sizeof(*tag) || + be32_to_cpu(tag->device_tree_offset) + + be32_to_cpu(tag->device_tree_size) > maxsize) { + if (name) + printf("%s: bogus device tree offset/size!\n", name); + return -EINVAL; + } + + if (be32_to_cpu(tag->kernel_offset) < sizeof(*tag) || + be32_to_cpu(tag->kernel_offset) + + be32_to_cpu(tag->kernel_size) > maxsize) { + if (name) + printf("%s: bogus kernel offset/size!\n", name); + return -EINVAL; + } + + if (be32_to_cpu(tag->rootfs_offset) < sizeof(*tag) || + be32_to_cpu(tag->rootfs_offset) + + be32_to_cpu(tag->rootfs_size) > maxsize) { + if (name) + printf("%s: bogus rootfs offset/size!\n", name); + return -EINVAL; + } + + if (name) { + /* + * Ensure null-termination within the 32-byte fields + * before printing to avoid displaying garbage. + */ + tag->image_name[sizeof(tag->image_name) - 1] = '\0'; + tag->build_date[sizeof(tag->build_date) - 1] = '\0'; + tag->build_user[sizeof(tag->build_user) - 1] = '\0'; + + printf("%s: Found valid tag: %s / %s / %s\n", name, + tag->image_name, tag->build_date, tag->build_user); + } + + return 0; +} + +static int mvebu_imagetag_crc(struct mvebu_image_tag *tag, const char *name) +{ + u32 crc = ~0; + + crc = crc32(crc, ((unsigned char *)tag) + 4, + be32_to_cpu(tag->total_size) - 4); + + if (be32_to_cpu(tag->crc) != crc) { + if (name) + printf("%s: invalid tag CRC!\n", name); + return -EINVAL; + } + + return 0; +} + +/* NRBoot (Reboot Tracking) Functions */ + +struct mvebu_nrboot { + u16 nrboot; + u16 nrsuccess; +}; + +#define MVEBU_MAX_FAILURE 4 + +static int mvebu_count_bits(u16 val) +{ + int i, found = 0; + + for (i = 0; i < 16; i++) { + if (val & (1 << i)) + found++; + } + return found; +} + +int mvebu_check_nrboot(struct mmc *mmc, unsigned long offset) +{ + struct blk_desc *bd = mmc_get_blk_desc(mmc); + struct mvebu_nrboot *nr; + uint blk_start = ALIGN(offset, bd->blksz) / bd->blksz; + uint blk_cnt = ALIGN(sizeof(*nr), bd->blksz) / bd->blksz; + uint n; + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, blk_cnt * bd->blksz); + nr = (void *)buf; + + n = blk_dread(bd, blk_start, blk_cnt, buf); + if (n != blk_cnt) + return 0; + + printf(" - nr.nrboot = %04x\n", nr->nrboot); + printf(" - nr.nrsuccess = %04x\n", nr->nrsuccess); + + /* Sanity check on values */ + if (mvebu_count_bits(~nr->nrboot + 1) <= 1 && + mvebu_count_bits(~nr->nrsuccess + 1) <= 1) { + int boot, success; + + boot = 16 - mvebu_count_bits(nr->nrboot); + success = 16 - mvebu_count_bits(nr->nrsuccess); + + printf(" - Nrboot: %d / Nrsuccess: %d\n", boot, success); + + if (boot == 16 || boot < success || + boot - success >= MVEBU_MAX_FAILURE) { + printf(" - Nrboot exceeded\n"); + return 0; + } + + /* Increment boot attempt counter */ + boot++; + nr->nrboot = ~((1 << boot) - 1); + + printf(" - Setting Nrboot to %d\n", boot); + + n = blk_dwrite(bd, blk_start, blk_cnt, buf); + if (n != blk_cnt) + return 0; + + return 1; + } + + printf(" - Invalid NR values\n"); + + return 0; +} + +/* emmcboot Command */ + +static void mvebu_try_emmcboot(struct mmc *mmc, unsigned long offset, + unsigned long maxsize, const char *bank) +{ + struct blk_desc *bd = mmc_get_blk_desc(mmc); + struct mvebu_image_tag *tag; + ulong image_addr = 0; + ulong fdt_addr = 0; + ulong tag_addr; + uint tag_blk_start = ALIGN(offset, bd->blksz) / bd->blksz; + uint tag_blk_cnt = ALIGN(sizeof(*tag), bd->blksz) / bd->blksz; + uint n; + + ALLOC_CACHE_ALIGN_BUFFER(char, tag_buf, tag_blk_cnt * bd->blksz); + tag = (void *)tag_buf; + + schedule(); + + printf("## Trying %s boot...\n", bank); + + /* Load tag header */ + n = blk_dread(bd, tag_blk_start, tag_blk_cnt, tag_buf); + if (n != tag_blk_cnt) { + printf("%s: failed to read tag header\n", bank); + return; + } + + if (mvebu_imagetag_check(tag, maxsize, bank) != 0) + return; + + if (tag->rootfs_size != 0) { + printf("%s: rootfs in tag not supported\n", bank); + return; + } + + /* Get image and device tree load addresses from environment */ + image_addr = env_get_ulong("image_addr", 16, 0); + if (!image_addr) { + puts("emmcboot needs image_addr\n"); + return; + } + + fdt_addr = env_get_ulong("fdt_addr", 16, 0); + if (!fdt_addr) { + puts("emmcboot needs fdt_addr\n"); + return; + } + + tag_addr = image_addr; + + /* Load full image, temporarily reuse image_addr for this */ + { + uint data_blk_start = ALIGN(offset, bd->blksz) / bd->blksz; + uint data_blk_cnt = ALIGN(mvebu_imagetag_total_size(tag), + bd->blksz) / bd->blksz; + + n = blk_dread(bd, data_blk_start, data_blk_cnt, (void *)tag_addr); + if (n != data_blk_cnt) { + printf("%s: failed to read full image\n", bank); + return; + } + + if (mvebu_imagetag_crc((void *)tag_addr, bank) != 0) + return; + } + + schedule(); + + /* Copy image and device tree to the right addresses */ + /* We assume that image_addr + tag_size < fdt_addr */ + { + tag = (void *)tag_addr; + memcpy((void *)fdt_addr, + ((void *)tag_addr) + mvebu_imagetag_device_tree_offset(tag), + mvebu_imagetag_device_tree_size(tag)); + memmove((void *)image_addr, + ((void *)tag_addr) + mvebu_imagetag_kernel_offset(tag), + mvebu_imagetag_kernel_size(tag)); + } + + schedule(); + + /* Set bootargs and boot */ + { + char bootargs[256]; + char *console_env; + + console_env = env_get("console"); + if (console_env) + snprintf(bootargs, sizeof(bootargs), "%s bank=%s", + console_env, bank); + else + snprintf(bootargs, sizeof(bootargs), "bank=%s", bank); + + env_set("bootargs", bootargs); + + printf("## Booting kernel from %s...\n", bank); + printf(" Image addr: 0x%lx\n", image_addr); + printf(" FDT addr: 0x%lx\n", fdt_addr); + + /* Build and run booti command */ + { + char cmd[128]; + + snprintf(cmd, sizeof(cmd), "booti 0x%lx - 0x%lx", + image_addr, fdt_addr); + run_command(cmd, 0); + } + } + + printf("## %s boot failed\n", bank); +} + +static int do_emmcboot(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int dev; + struct mmc *mmc; + + dev = 0; + if (argc >= 2) + dev = dectoul(argv[1], NULL); + + mmc = find_mmc_device(dev); + if (!mmc) { + printf("No MMC device %d found\n", dev); + return CMD_RET_FAILURE; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return CMD_RET_FAILURE; + } + + /* Switch to partition 0 (user data area) */ + if (blk_select_hwpart_devnum(UCLASS_MMC, dev, 0)) { + puts("MMC partition switch failed\n"); + return CMD_RET_FAILURE; + } + + if (mvebu_check_nrboot(mmc, CONFIG_NBX_MMC_PART_NRBOOT_OFFSET)) { + /* System is healthy: try newer bank first */ + mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK1_OFFSET, + CONFIG_NBX_MMC_PART_BANK1_SIZE, "bank1"); + mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK0_OFFSET, + CONFIG_NBX_MMC_PART_BANK0_SIZE, "bank0"); + } else { + /* System is degraded: use stable bank first */ + mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK0_OFFSET, + CONFIG_NBX_MMC_PART_BANK0_SIZE, "bank0"); + mvebu_try_emmcboot(mmc, CONFIG_NBX_MMC_PART_BANK1_OFFSET, + CONFIG_NBX_MMC_PART_BANK1_SIZE, "bank1"); + } + + puts("emmcboot: all boot attempts failed\n"); + return CMD_RET_FAILURE; +} + +U_BOOT_CMD( + emmcboot, 2, 0, do_emmcboot, + "boot from MVEBU eMMC image banks", + "[dev]\n" + " - Boot from eMMC device <dev> (default 0)\n" + " - Requires image_addr and fdt_addr environment variables\n" + " - Uses dual-bank boot with automatic fallback\n" + " - Bank selection based on reboot tracking (nrboot)" +); diff --git a/board/freebox/nbx10g/nbx_fbxserial.c b/board/freebox/nbx10g/nbx_fbxserial.c new file mode 100644 index 00000000000..088133a9496 --- /dev/null +++ b/board/freebox/nbx10g/nbx_fbxserial.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NBX Freebox Serial Info Support + * + * Copyright (C) 2025 Free Mobile, Freebox + * + * Reads device serial number and MAC address from eMMC. + * The serial info is stored at a fixed offset in the eMMC user area. + * + * Serial format: TTTT-VV-M-(YY)WW-NN-NNNNN / FLAGS + * Where: + * TTTT = Device type (e.g., 9018) + * VV = Board version + * M = Manufacturer code (ASCII) + * YY = Year (BCD) + * WW = Week (1-53) + * NNNNN = Serial number + * FLAGS = Feature flags + */ + +#include <command.h> +#include <dm/device.h> +#include <env.h> +#include <event.h> +#include <mmc.h> +#include <malloc.h> +#include <memalign.h> +#include <vsprintf.h> +#include <u-boot/crc.h> +#include <asm/byteorder.h> +#include <linux/ctype.h> +#include <linux/errno.h> +#include "nbx_fbxserial.h" + +/* Partition offset defined in Kconfig (CONFIG_NBX_MMC_PART_SERIAL_OFFSET) */ + +/* + * Validate serial info structure + */ +static int nbx_fbx_check_serial(struct nbx_fbx_serial *fs) +{ + unsigned int sum, len; + + /* Check magic first */ + if (be32_to_cpu(fs->magic) != NBX_FBXSERIAL_MAGIC) { + printf("Invalid magic for serial info (%08x != %08x)!\n", + be32_to_cpu(fs->magic), NBX_FBXSERIAL_MAGIC); + return -EINVAL; + } + + /* Check struct version */ + if (be32_to_cpu(fs->struct_version) > NBX_FBXSERIAL_VERSION) { + printf("Version too big for fbxserial info (0x%08x)!\n", + be32_to_cpu(fs->struct_version)); + return -EINVAL; + } + + /* Check for silly len */ + len = be32_to_cpu(fs->len); + if (len > NBX_FBXSERIAL_MAX_SIZE) { + printf("Silly len for serial info (%d)\n", len); + return -EINVAL; + } + + /* Validate CRC (crc32_no_comp: no one's complement) */ + sum = crc32_no_comp(0, (void *)fs + 4, len - 4); + if (be32_to_cpu(fs->crc32) != sum) { + printf("Invalid checksum for serial info (%08x != %08x)\n", + sum, be32_to_cpu(fs->crc32)); + return -EINVAL; + } + + return 0; +} + +int nbx_fbx_read_serial(int dev_num, unsigned long offset, + struct nbx_fbx_serial *fs) +{ + struct mmc *mmc; + struct blk_desc *bd; + uint blk_start, blk_cnt; + uint n; + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, ALIGN(sizeof(*fs), 512)); + mmc = find_mmc_device(dev_num); + if (!mmc) { + printf("No MMC device %d found\n", dev_num); + nbx_fbxserial_set_default(fs); + return -ENODEV; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + nbx_fbxserial_set_default(fs); + return -EIO; + } + + /* Switch to partition 0 (user data area) */ + if (blk_select_hwpart_devnum(UCLASS_MMC, dev_num, 0)) { + puts("MMC partition switch failed\n"); + nbx_fbxserial_set_default(fs); + return -EIO; + } + + bd = mmc_get_blk_desc(mmc); + if (!bd) { + puts("Failed to get MMC block descriptor\n"); + nbx_fbxserial_set_default(fs); + return -EIO; + } + + blk_start = ALIGN(offset, bd->blksz) / bd->blksz; + blk_cnt = ALIGN(sizeof(*fs), bd->blksz) / bd->blksz; + + memset(fs, 0x42, sizeof(*fs)); + + n = blk_dread(bd, blk_start, blk_cnt, buf); + if (n != blk_cnt) { + printf("Failed to read serial info from MMC\n"); + nbx_fbxserial_set_default(fs); + return -EIO; + } + + memcpy(fs, buf, sizeof(*fs)); + + if (nbx_fbx_check_serial(fs) != 0) { + nbx_fbxserial_set_default(fs); + return -EINVAL; + } + + return 0; +} + +void nbx_fbx_dump_serial(struct nbx_fbx_serial *fs) +{ + int i; + + printf("Serial: %04u-%02u-%c-(%02u)%02u-%02u-%05u / %08x\n", + ntohs(fs->type), + fs->version, + isprint(fs->manufacturer) ? fs->manufacturer : '?', + ntohs(fs->year) / 100, + ntohs(fs->year) % 100, + fs->week, + ntohl(fs->number), + ntohl(fs->flags)); + + printf("Mac: %02X:%02X:%02X:%02X:%02X:%02X\n", + fs->mac_addr_base[0], + fs->mac_addr_base[1], + fs->mac_addr_base[2], + fs->mac_addr_base[3], + fs->mac_addr_base[4], + fs->mac_addr_base[5]); + + /* Show bundle info */ + for (i = 0; i < be32_to_cpu(fs->extinfo_count); i++) { + struct nbx_serial_extinfo *p; + + if (i >= NBX_EXTINFO_MAX_COUNT) + break; + + p = &fs->extinfos[i]; + if (be32_to_cpu(p->type) == NBX_EXTINFO_TYPE_EXTDEV && + be32_to_cpu(p->u.extdev.type) == NBX_EXTDEV_TYPE_BUNDLE) { + /* Ensure null termination */ + p->u.extdev.serial[sizeof(p->u.extdev.serial) - 1] = 0; + printf("Bundle: %s\n", p->u.extdev.serial); + } + } + + printf("\n"); +} + +int nbx_fbx_init_ethaddr(int dev_num, unsigned long offset) +{ + struct nbx_fbx_serial fs; + char mac[32]; + int ret; + + ret = nbx_fbx_read_serial(dev_num, offset, &fs); + + /* Even on error, fs has default values set */ + snprintf(mac, sizeof(mac), "%02x:%02x:%02x:%02x:%02x:%02x", + fs.mac_addr_base[0], fs.mac_addr_base[1], + fs.mac_addr_base[2], fs.mac_addr_base[3], + fs.mac_addr_base[4], fs.mac_addr_base[5]); + + nbx_fbx_dump_serial(&fs); + + env_set("ethaddr", mac); + env_set("eth1addr", mac); + env_set("eth2addr", mac); + + return ret; +} + +/* + * fbxserial show - display serial info from eMMC + */ +static int do_fbxserial_show(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct nbx_fbx_serial fs; + int dev = 0; + unsigned long offset = CONFIG_NBX_MMC_PART_SERIAL_OFFSET; + + if (argc >= 1) + dev = dectoul(argv[0], NULL); + + if (argc >= 2) + offset = hextoul(argv[1], NULL); + + if (nbx_fbx_read_serial(dev, offset, &fs) != 0) + printf("Warning: Using default serial info\n"); + + nbx_fbx_dump_serial(&fs); + + return CMD_RET_SUCCESS; +} + +/* + * fbxserial init - initialize ethaddr from serial info + */ +static int do_fbxserial_init(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int dev = 0; + unsigned long offset = CONFIG_NBX_MMC_PART_SERIAL_OFFSET; + + if (argc >= 1) + dev = dectoul(argv[0], NULL); + + if (argc >= 2) + offset = hextoul(argv[1], NULL); + + return nbx_fbx_init_ethaddr(dev, offset); +} + +static struct cmd_tbl cmd_fbxserial_sub[] = { + U_BOOT_CMD_MKENT(show, 3, 0, do_fbxserial_show, "", ""), + U_BOOT_CMD_MKENT(init, 3, 0, do_fbxserial_init, "", ""), +}; + +static int do_fbxserial(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct cmd_tbl *cp; + + /* Default to 'show' if no subcommand */ + if (argc < 2) + return do_fbxserial_show(cmdtp, flag, 0, NULL); + + cp = find_cmd_tbl(argv[1], cmd_fbxserial_sub, + ARRAY_SIZE(cmd_fbxserial_sub)); + + if (!cp) + return CMD_RET_USAGE; + + return cp->cmd(cmdtp, flag, argc - 2, argv + 2); +} + +U_BOOT_CMD( + fbxserial, 5, 0, do_fbxserial, + "NBX serial info and MAC address initialization", + "show [dev] [offset] - display serial info from eMMC\n" + "fbxserial init [dev] [offset] - initialize ethaddr from serial info\n" + " dev - MMC device number (default 0)\n" + " offset - offset in eMMC in hex (default from Kconfig)" +); + +/* + * Early init hook: Set MAC address from eMMC serial info before + * network driver probes. EVT_SETTINGS_R is triggered after MMC + * is available but before initr_net(). + */ +static int nbx_fbx_settings_r(void) +{ + if (!of_machine_is_compatible("nbx,armada8040")) + return 0; + + nbx_fbx_init_ethaddr(0, CONFIG_NBX_MMC_PART_SERIAL_OFFSET); + return 0; +} + +EVENT_SPY_SIMPLE(EVT_SETTINGS_R, nbx_fbx_settings_r); diff --git a/board/freebox/nbx10g/nbx_fbxserial.h b/board/freebox/nbx10g/nbx_fbxserial.h new file mode 100644 index 00000000000..7bcaef09fe3 --- /dev/null +++ b/board/freebox/nbx10g/nbx_fbxserial.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * NBX Freebox Serial Info Support + * + * Copyright (C) 2025 Free Mobile, Freebox + * + * Reads device serial number and MAC address from eMMC. + * Used to identify the board and set network MAC addresses. + */ + +#ifndef NBX_FBXSERIAL_H +#define NBX_FBXSERIAL_H + +#include <linux/types.h> + +/* + * Extended info structure - variable data depending on type + */ +#define NBX_EXTINFO_SIZE 128 +#define NBX_EXTINFO_MAX_COUNT 16 + +/* Extended info types */ +#define NBX_EXTINFO_TYPE_EXTDEV 1 + +/* Extended device types */ +#define NBX_EXTDEV_TYPE_BUNDLE 1 +#define NBX_EXTDEV_TYPE_MAX 2 + +struct nbx_serial_extinfo { + u32 type; + + union { + /* extdev */ + struct { + u32 type; + u32 model; + char serial[64]; + } extdev; + + /* raw access */ + unsigned char data[NBX_EXTINFO_SIZE]; + } u; +} __packed; + +/* + * Master serial structure + */ +#define NBX_FBXSERIAL_VERSION 1 +#define NBX_FBXSERIAL_MAGIC 0x2d9521ab + +#define NBX_MAC_ADDR_SIZE 6 +#define NBX_RANDOM_DATA_SIZE 32 + +/* Maximum size for CRC validation */ +#define NBX_FBXSERIAL_MAX_SIZE 8192 + +struct nbx_fbx_serial { + u32 crc32; + u32 magic; + u32 struct_version; + u32 len; + + /* Board serial */ + u16 type; + u8 version; + u8 manufacturer; + u16 year; + u8 week; + u32 number; + u32 flags; + + /* MAC address base */ + u8 mac_addr_base[NBX_MAC_ADDR_SIZE]; + + /* MAC address count */ + u8 mac_count; + + /* Random data used to derive keys */ + u8 random_data[NBX_RANDOM_DATA_SIZE]; + + /* Last update of data (seconds since epoch) */ + u32 last_modified; + + /* Count of following extinfo tags */ + u32 extinfo_count; + + /* Beginning of extended info */ + struct nbx_serial_extinfo extinfos[NBX_EXTINFO_MAX_COUNT]; +} __packed; + +/** + * nbx_fbxserial_set_default() - Initialize serial structure with defaults + * @serial: Pointer to serial structure to initialize + * + * Sets the serial structure to default values (Freebox OUI, type 9018). + * Used as fallback when serial info cannot be read from eMMC. + */ +static inline void nbx_fbxserial_set_default(struct nbx_fbx_serial *serial) +{ + static const struct nbx_fbx_serial def = { + .crc32 = 0, + .magic = NBX_FBXSERIAL_MAGIC, + .struct_version = NBX_FBXSERIAL_VERSION, + .len = sizeof(struct nbx_fbx_serial), + .type = 9018, + .version = 0, + .manufacturer = '_', + .year = 0, + .week = 0, + .number = 0, + .flags = 0, + .mac_addr_base = { 0x00, 0x07, 0xCB, 0x00, 0x00, 0xFD }, + .mac_count = 1, + .random_data = { 0 }, + .last_modified = 0, + .extinfo_count = 0, + }; + + memcpy(serial, &def, sizeof(def)); +} + +/** + * nbx_fbx_read_serial() - Read serial info from eMMC + * @dev_num: MMC device number + * @offset: Byte offset in eMMC where serial info is stored + * @fs: Pointer to serial structure to fill + * + * Reads and validates the serial info from eMMC. On failure, + * the structure is filled with default values. + * + * Return: 0 on success, negative on error (defaults still set) + */ +int nbx_fbx_read_serial(int dev_num, unsigned long offset, + struct nbx_fbx_serial *fs); + +/** + * nbx_fbx_dump_serial() - Print serial info to console + * @fs: Pointer to serial structure to display + * + * Prints the serial number, MAC address, and bundle info (if present). + */ +void nbx_fbx_dump_serial(struct nbx_fbx_serial *fs); + +/** + * nbx_fbx_init_ethaddr() - Initialize Ethernet addresses from serial info + * @dev_num: MMC device number + * @offset: Byte offset in eMMC where serial info is stored + * + * Reads serial info and sets ethaddr, eth1addr, eth2addr environment + * variables from the MAC address in the serial structure. + * + * Return: 0 on success, negative on error + */ +int nbx_fbx_init_ethaddr(int dev_num, unsigned long offset); + +#endif /* NBX_FBXSERIAL_H */ diff --git a/board/freebox/nbx10g/nbx_imagetag.h b/board/freebox/nbx10g/nbx_imagetag.h new file mode 100644 index 00000000000..999293dd58a --- /dev/null +++ b/board/freebox/nbx10g/nbx_imagetag.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * MVEBU Image Tag header + * + * Copyright (C) 2026 Free Mobile, Freebox + */ + +#ifndef __MVEBU_IMAGETAG_H +#define __MVEBU_IMAGETAG_H + +#include <linux/types.h> + +#define MVEBU_IMAGE_TAG_MAGIC 0x8d7c90bc +#define MVEBU_IMAGE_TAG_VERSION 1 + +/** + * struct mvebu_image_tag - MVEBU boot image tag structure + * + * All multi-byte fields are stored in big-endian format. + */ +struct mvebu_image_tag { + u32 crc; /* CRC32-LE checksum (from offset 4) */ + u32 magic; /* Magic: 0x8d7c90bc */ + u32 version; /* Version: 1 */ + u32 total_size; /* Total image size including tag */ + u32 flags; /* Feature flags (reserved) */ + + u32 device_tree_offset; /* Offset from tag start to DTB */ + u32 device_tree_size; /* DTB size in bytes */ + + u32 kernel_offset; /* Offset from tag start to kernel */ + u32 kernel_size; /* Kernel size in bytes */ + + u32 rootfs_offset; /* Offset from tag start to rootfs */ + u32 rootfs_size; /* Rootfs size (must be 0) */ + + char image_name[32]; /* Image name (null-terminated) */ + char build_user[32]; /* Build user info */ + char build_date[32]; /* Build date info */ +}; + +/* Accessor functions for big-endian fields */ +static inline u32 mvebu_imagetag_device_tree_offset(struct mvebu_image_tag *tag) +{ + return be32_to_cpu(tag->device_tree_offset); +} + +static inline u32 mvebu_imagetag_device_tree_size(struct mvebu_image_tag *tag) +{ + return be32_to_cpu(tag->device_tree_size); +} + +static inline u32 mvebu_imagetag_kernel_offset(struct mvebu_image_tag *tag) +{ + return be32_to_cpu(tag->kernel_offset); +} + +static inline u32 mvebu_imagetag_kernel_size(struct mvebu_image_tag *tag) +{ + return be32_to_cpu(tag->kernel_size); +} + +static inline u32 mvebu_imagetag_rootfs_offset(struct mvebu_image_tag *tag) +{ + return be32_to_cpu(tag->rootfs_offset); +} + +static inline u32 mvebu_imagetag_rootfs_size(struct mvebu_image_tag *tag) +{ + return be32_to_cpu(tag->rootfs_size); +} + +static inline u32 mvebu_imagetag_total_size(struct mvebu_image_tag *tag) +{ + return be32_to_cpu(tag->total_size); +} + +#endif /* __MVEBU_IMAGETAG_H */ diff --git a/board/freebox/nbx10g/nbx_nrboot.h b/board/freebox/nbx10g/nbx_nrboot.h new file mode 100644 index 00000000000..91c9fb2e57b --- /dev/null +++ b/board/freebox/nbx10g/nbx_nrboot.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * MVEBU NRBoot (Number of Reboots) tracking header + * + * Copyright (C) 2026 Free Mobile, Freebox + */ + +#ifndef __MVEBU_NRBOOT_H +#define __MVEBU_NRBOOT_H + +#include <mmc.h> + +/** + * mvebu_check_nrboot() - Check and update reboot tracking counter + * @mmc: MMC device + * @offset: Byte offset in MMC where nrboot data is stored + * + * This function reads the reboot tracking counter, checks if we've + * exceeded the maximum number of failed boots (4), and updates the + * counter for the current boot attempt. + * + * The counter uses a bit-field encoding: + * - nrboot: Running count of boot attempts + * - nrsuccess: Count of successful boots + * + * If boot - success >= MAX_FAILURE (4), the system is considered + * degraded and should use the fallback boot bank. + * + * Return: 1 if system is healthy (try newer bank first), + * 0 if system is degraded (use stable bank first) + */ +int mvebu_check_nrboot(struct mmc *mmc, unsigned long offset); + +#endif /* __MVEBU_NRBOOT_H */ diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index eb10cd5143d..5e560a7f927 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -532,17 +532,17 @@ int dram_init_banksize(void) /* set global data memory */ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100; - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; /* Number of Row: 14 bits */ if ((reg_val >> 28) == 14) - gd->bd->bi_dram[0].size -= 0x20000000; + gd->dram[0].size -= 0x20000000; /* Number of Memory Chips */ if ((reg_val & 0x3) > 1) { - gd->bd->bi_dram[1].start = 0x80000000; - gd->bd->bi_dram[1].size = 0x40000000; + gd->dram[1].start = 0x80000000; + gd->dram[1].size = 0x40000000; } return 0; } diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 6a24f618ae2..aeb401b1210 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -47,7 +47,7 @@ int board_fit_config_name_match(const char *path) return -1; } -#if (IS_ENABLED(CONFIG_NET)) +#if (IS_ENABLED(CONFIG_NET_LEGACY)) int board_phy_config(struct phy_device *phydev) { unsigned short val; @@ -71,7 +71,7 @@ int board_phy_config(struct phy_device *phydev) return 0; } -#endif // IS_ENABLED(CONFIG_NET) +#endif // IS_ENABLED(CONFIG_NET_LEGACY) int board_init(void) { diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index ddb7304d493..f7751fd6fb1 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -320,7 +320,7 @@ int overwrite_console(void) int board_early_init_f(void) { - select_ldb_di_clock_source(MXC_PLL5_CLK); + select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); return 0; } diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index e1d08475e94..9fc5f604a49 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -383,7 +383,7 @@ int board_early_init_f(void) #if defined(CONFIG_VIDEO_IPUV3) /* Set LDB clock to Video PLL */ - select_ldb_di_clock_source(MXC_PLL5_CLK); + select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); #endif return 0; } diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c index cb9b88a1a58..d3a385bf6b7 100644 --- a/board/ge/mx53ppd/mx53ppd.c +++ b/board/ge/mx53ppd/mx53ppd.c @@ -71,11 +71,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index b4053fa097d..2bb54d59bb8 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -293,7 +293,7 @@ static int coral_write_acpi_tables(const struct udevice *dev, return 0; } -struct acpi_ops coral_acpi_ops = { +static const struct acpi_ops __maybe_unused coral_acpi_ops = { .write_tables = coral_write_acpi_tables, .inject_dsdt = chromeos_acpi_gpio_generate, }; diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c index cfba9300dcb..f3aae9256c1 100644 --- a/board/google/imx8mq_phanbell/spl.c +++ b/board/google/imx8mq_phanbell/spl.c @@ -6,134 +6,21 @@ #include <config.h> #include <hang.h> -#include <asm/global_data.h> -#include <asm/io.h> #include <errno.h> #include <init.h> #include <log.h> -#include <asm/io.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <linux/delay.h> -#include <fsl_esdhc_imx.h> -#include <mmc.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(void) { /* ddr init */ ddr_init(&dram_timing); } -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = 1; - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - return ret; - } - - return 1; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR}, - {USDHC2_BASE_ADDR}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - usdhc_cfg[0].max_bus_width = 8; - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - usdhc_cfg[1].max_bus_width = 4; - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - void spl_board_init(void) { puts("Normal Boot\n"); @@ -153,8 +40,8 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -166,12 +53,9 @@ void board_init_f(ulong dummy) preloader_console_init(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } @@ -180,5 +64,8 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/hardkernel/odroid_m1/MAINTAINERS b/board/hardkernel/odroid_m1/MAINTAINERS index 165d2d96741..8686a552d1c 100644 --- a/board/hardkernel/odroid_m1/MAINTAINERS +++ b/board/hardkernel/odroid_m1/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/hardkernel/odroid_m1/ F: include/configs/odroid_m1.h F: configs/odroid-m1-rk3568_defconfig -F: arch/arm/dts/rk3568-odroid-m1.dts -F: arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi +F: arch/arm/dts/rk3568-odroid-m1* diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 5e60ab9d7b7..ba0465cf96f 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -456,23 +456,23 @@ int dram_init_banksize(void) * 0x3e00,0000 - 0x3fff,ffff: OP-TEE */ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = 0x05e00000; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = 0x05e00000; - gd->bd->bi_dram[1].start = 0x05f00000; - gd->bd->bi_dram[1].size = 0x00001000; + gd->dram[1].start = 0x05f00000; + gd->dram[1].size = 0x00001000; - gd->bd->bi_dram[2].start = 0x05f02000; - gd->bd->bi_dram[2].size = 0x00efd000; + gd->dram[2].start = 0x05f02000; + gd->dram[2].size = 0x00efd000; - gd->bd->bi_dram[3].start = 0x06e00000; - gd->bd->bi_dram[3].size = 0x0060f000; + gd->dram[3].start = 0x06e00000; + gd->dram[3].size = 0x0060f000; - gd->bd->bi_dram[4].start = 0x07410000; - gd->bd->bi_dram[4].size = 0x1aaf0000; + gd->dram[4].start = 0x07410000; + gd->dram[4].size = 0x1aaf0000; - gd->bd->bi_dram[5].start = 0x22000000; - gd->bd->bi_dram[5].size = 0x1c000000; + gd->dram[5].start = 0x22000000; + gd->dram[5].size = 0x1c000000; return 0; } diff --git a/board/hisilicon/hikey960/hikey960.c b/board/hisilicon/hikey960/hikey960.c index fb56762fff6..e7908d4c048 100644 --- a/board/hisilicon/hikey960/hikey960.c +++ b/board/hisilicon/hikey960/hikey960.c @@ -74,8 +74,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c index c3ea080ff75..dbab67d6f65 100644 --- a/board/hisilicon/poplar/poplar.c +++ b/board/hisilicon/poplar/poplar.c @@ -87,8 +87,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET; - gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start; + gd->dram[0].start = KERNEL_TEXT_OFFSET; + gd->dram[0].size = gd->ram_size - gd->dram[0].start; return 0; } diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig index 965847d9650..d7d8bfd0a76 100644 --- a/board/imgtec/boston/Kconfig +++ b/board/imgtec/boston/Kconfig @@ -11,7 +11,7 @@ config SYS_CONFIG_NAME config ENV_SOURCE_FILE - default "boston" + default "boston" config TEXT_BASE default 0x9fc00000 if 32BIT diff --git a/board/intel/edison/config.mk b/board/intel/edison/config.mk index 3afebf0f0b1..fff187caa15 100644 --- a/board/intel/edison/config.mk +++ b/board/intel/edison/config.mk @@ -7,8 +7,8 @@ # Add 4096 bytes of zeroes to u-boot.bin quiet_cmd_mkalign_eds = EDSALGN $@ cmd_mkalign_eds = \ - dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \ - mv $@ $^ + dd if=$< of=$@ bs=4k seek=1 2>/dev/null && \ + mv $@ $< INPUTS-y += u-boot-align.bin u-boot-align.bin: u-boot.bin FORCE diff --git a/board/k+p/kp_imx53/kp_imx53.c b/board/k+p/kp_imx53/kp_imx53.c index efb7b49cbe0..07668bae7a9 100644 --- a/board/k+p/kp_imx53/kp_imx53.c +++ b/board/k+p/kp_imx53/kp_imx53.c @@ -39,8 +39,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 51938a1b4d8..e37d4e767db 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -84,8 +84,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/khadas/khadas-edge2-rk3588s/MAINTAINERS b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS index 3f16923b0f2..c43f469589d 100644 --- a/board/khadas/khadas-edge2-rk3588s/MAINTAINERS +++ b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS @@ -3,4 +3,4 @@ M: Jacobe Zang <[email protected]> S: Maintained F: configs/khadas-edge2-rk3588s_defconfig F: include/configs/khadas-edge2-rk3588s.h -F: dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
\ No newline at end of file +F: arch/arm/dts/rk3588s-khadas-edge2* diff --git a/board/kontron/pitx_imx8m/MAINTAINERS b/board/kontron/pitx_imx8m/MAINTAINERS index aad84528e33..8c43526691b 100644 --- a/board/kontron/pitx_imx8m/MAINTAINERS +++ b/board/kontron/pitx_imx8m/MAINTAINERS @@ -1,7 +1,6 @@ Kontron pITX-imx8m Board M: Heiko Thiery <[email protected]> S: Maintained -F: arch/arm/dts/imx8mq-kontron-pitx-imx8m* F: board/kontron/pitx_imx8m/* F: include/configs/kontron_pitx_imx8m.h F: configs/kontron_pitx_imx8m_defconfig diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c index bd5981bf694..0396967fe36 100644 --- a/board/kontron/pitx_imx8m/spl.c +++ b/board/kontron/pitx_imx8m/spl.c @@ -2,22 +2,14 @@ #include <config.h> #include <errno.h> -#include <fsl_esdhc_imx.h> #include <hang.h> #include <init.h> #include <log.h> #include <spl.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <linux/delay.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> @@ -26,8 +18,6 @@ extern struct dram_timing_info dram_timing_2gb; extern struct dram_timing_info dram_timing_4gb; -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(void) { struct dram_timing_info *dram_timing; @@ -53,120 +43,6 @@ static void spl_dram_init(void) ddr_init(dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(MMC) -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - /* the eMMC does not have a CD pin */ - return 1; - case USDHC2_BASE_ADDR: - return !gpio_get_value(USDHC2_CD_GPIO); - } - - return 0; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR, 0, 8}, - {USDHC2_BASE_ADDR, 0, 4}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers " - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - const char *spl_board_loader_name(u32 boot_device) { switch (boot_device) { @@ -178,18 +54,14 @@ const char *spl_board_loader_name(u32 boot_device) return NULL; } } -#endif -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 - -static int pfuze_mode_init(struct pmic *p, u32 mode) +static int pfuze_mode_init(struct udevice *dev, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = pmic_reg_read(dev, PFUZE100_DEVICEID); id = id & 0xf; if (id == 0) { @@ -203,14 +75,14 @@ static int pfuze_mode_init(struct pmic *p, u32 mode) return -EINVAL; } - ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -223,46 +95,44 @@ static int pfuze_mode_init(struct pmic *p, u32 mode) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; + int reg; int ret; - unsigned int reg; - - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return -ENODEV; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return -ENODEV; + ret = pmic_get("pmic@8", &dev); + if (ret == -ENODEV) { + puts("No pmic@8\n"); + return 0; + } + if (ret < 0) + return ret; - pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AVOL); if ((reg & 0x3f) != 0x18) { reg &= ~0x3f; reg |= 0x18; - pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + pmic_reg_write(dev, PFUZE100_SW3AVOL, reg); } - ret = pfuze_mode_init(p, APS_PFM); + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; /* set SW3A standby mode to off */ - pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AMODE); reg &= ~0xf; reg |= APS_OFF; - pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + pmic_reg_write(dev, PFUZE100_SW3AMODE, reg); return 0; } -#endif void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -272,26 +142,22 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } - enable_tzc380(); + preloader_console_init(); - setup_i2c(0, 100000, 0x7f, &i2c_pad_info1); + enable_tzc380(); -#if CONFIG_IS_ENABLED(POWER_LEGACY) power_init_board(); -#endif spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 8a9502037fb..ce778bc0849 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -175,8 +175,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < nbanks; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } fdt_fixup_memory_banks(blob, base, size, nbanks); diff --git a/board/kontron/sl28/spl_atf.c b/board/kontron/sl28/spl_atf.c index 0710316a48b..cc741dea504 100644 --- a/board/kontron/sl28/spl_atf.c +++ b/board/kontron/sl28/spl_atf.c @@ -36,9 +36,9 @@ struct bl_params *bl2_plat_get_bl31_params_v2(uintptr_t bl32_entry, dram_regions_info.num_dram_regions = CONFIG_NR_DRAM_BANKS; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - dram_regions_info.region[i].addr = gd->bd->bi_dram[i].start; - dram_regions_info.region[i].size = gd->bd->bi_dram[i].size; - dram_regions_info.total_dram_size += gd->bd->bi_dram[i].size; + dram_regions_info.region[i].addr = gd->dram[i].start; + dram_regions_info.region[i].size = gd->dram[i].size; + dram_regions_info.total_dram_size += gd->dram[i].size; } bl_params = bl2_plat_get_bl31_params_v2_default(bl32_entry, bl33_entry, diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c index e1ff041c54f..ba922b43064 100644 --- a/board/liebherr/btt/btt.c +++ b/board/liebherr/btt/btt.c @@ -239,7 +239,7 @@ int spl_start_uboot(void) static const char *get_board_name(void) { - if (gd->bd->bi_dram[0].size == SZ_128M) + if (gd->dram[0].size == SZ_128M) return STR_BTTC; return STR_BTT3; diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig index f5e2f58b12b..dfc196124f3 100644 --- a/board/logicpd/imx6/Kconfig +++ b/board/logicpd/imx6/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "imx6" config SYS_VENDOR - default "logicpd" + default "logicpd" config SYS_CONFIG_NAME default "imx6_logic" diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS index c342ff24330..37ca35b4dd4 100644 --- a/board/mediatek/MAINTAINERS +++ b/board/mediatek/MAINTAINERS @@ -3,10 +3,14 @@ M: Macpaul Lin <[email protected]> S: Maintained F: arch/arm/dts/mt8371-genio-520-evk-u-boot.dtsi F: arch/arm/dts/mt8371-genio-common-u-boot.dtsi +F: arch/arm/dts/mt8371-genio-common-ufs.dtso F: arch/arm/dts/mt8391-genio-720-evk-u-boot.dtsi +F: configs/mt8189-ufs.config F: configs/mt8189.config F: configs/mt8371_genio_520_evk_defconfig +F: configs/mt8371_genio_520_evk_ufs_defconfig F: configs/mt8391_genio_720_evk_defconfig +F: configs/mt8391_genio_720_evk_ufs_defconfig MT8365 EVK M: Julien Masson <[email protected]> @@ -21,8 +25,10 @@ F: configs/mt8188.config F: configs/mt8370_genio_510_evk_defconfig F: configs/mt8390_genio_700_evk_defconfig -MT8395 +MT8195/MT8395 M: Macpaul Lin <[email protected]> M: Julien Stephan <[email protected]> S: Maintained +F: configs/mt8195.config F: configs/mt8395_genio_1200_evk_defconfig +F: configs/mt8395_genio_1200_evk_ufs_defconfig diff --git a/board/mediatek/mt7622/MAINTAINERS b/board/mediatek/mt7622/MAINTAINERS index a3e0e75ca07..067f33bb39f 100644 --- a/board/mediatek/mt7622/MAINTAINERS +++ b/board/mediatek/mt7622/MAINTAINERS @@ -2,5 +2,4 @@ MT7622 M: Sam Shih <[email protected]> S: Maintained F: board/mediatek/mt7622 -F: include/configs/mt7622.h F: configs/mt7622_rfb_defconfig diff --git a/board/mediatek/mt7987/MAINTAINERS b/board/mediatek/mt7987/MAINTAINERS index c257d0b09df..b245174b0f7 100644 --- a/board/mediatek/mt7987/MAINTAINERS +++ b/board/mediatek/mt7987/MAINTAINERS @@ -2,7 +2,6 @@ MT7987 M: Sam Shih <[email protected]> S: Maintained F: board/mediatek/mt7987 -F: include/configs/mt7987.h F: configs/mt7987_rfb_defconfig F: configs/mt7987_emmc_rfb_defconfig F: configs/mt7987_sd_rfb_defconfig diff --git a/board/mediatek/mt7988/MAINTAINERS b/board/mediatek/mt7988/MAINTAINERS index a45bfff26ca..c7e30342e5c 100644 --- a/board/mediatek/mt7988/MAINTAINERS +++ b/board/mediatek/mt7988/MAINTAINERS @@ -2,6 +2,5 @@ MT7988 M: Sam Shih <[email protected]> S: Maintained F: board/mediatek/mt7988 -F: include/configs/mt7988.h F: configs/mt7988_rfb_defconfig F: configs/mt7988_sd_rfb_defconfig diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index fc76d5765fa..5e76942783f 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -69,11 +69,11 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = mx53_dram_size[0]; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = mx53_dram_size[1]; return 0; } diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c index 48a783593b6..aca0525c699 100644 --- a/board/mntre/imx8mq_reform2/spl.c +++ b/board/mntre/imx8mq_reform2/spl.c @@ -10,7 +10,6 @@ #include <image.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <errno.h> #include <asm/io.h> @@ -28,8 +27,6 @@ #include <power/pmic.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - extern struct dram_timing_info dram_timing_ch2; static void spl_dram_init(void) @@ -226,9 +223,6 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - arch_cpu_init(); init_uart_clk(0); diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 05c4dd187fe..68d516c7db8 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -57,7 +57,7 @@ int dram_init_banksize(void) { phys_size_t ram_size = gd->ram_size; - gd->bd->bi_dram[0].start = 0; + gd->dram[0].start = 0; #if defined(CONFIG_SYS_MEM_TOP_HIDE) ram_size += CONFIG_SYS_MEM_TOP_HIDE; @@ -69,25 +69,25 @@ int dram_init_banksize(void) case DRAM_1GB_SIZE: case DRAM_2GB_ECC_SIZE: case DRAM_2GB_SIZE: - gd->bd->bi_dram[0].size = ram_size; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = ram_size; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; case DRAM_4GB_ECC_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE - + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE - (DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE); break; case DRAM_4GB_SIZE: - gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; - gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; - gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; + gd->dram[0].size = DRAM_2GB_SIZE; + gd->dram[1].start = DRAM_4GB_SIZE; + gd->dram[1].size = DRAM_2GB_SIZE; break; default: - gd->bd->bi_dram[0].size = DRAM_1GB_SIZE; - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[0].size = DRAM_1GB_SIZE; + gd->dram[1].start = 0; + gd->dram[1].size = 0; break; } diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile index ed102ae7bf7..dafd3717948 100644 --- a/board/nxp/common/Makefile +++ b/board/nxp/common/Makefile @@ -57,7 +57,7 @@ obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o endif -obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o +obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o ifneq (,$(filter $(SOC), imx8m imx8ulp imx9)) obj-y += mmc.o diff --git a/board/nxp/common/i2c_mux.h b/board/nxp/common/i2c_mux.h index 0870c1918e6..ef7ce8e2e51 100644 --- a/board/nxp/common/i2c_mux.h +++ b/board/nxp/common/i2c_mux.h @@ -10,6 +10,11 @@ #ifdef CONFIG_FSL_USE_PCA9547_MUX int select_i2c_ch_pca9547(u8 ch, int bus); +#else +static inline int select_i2c_ch_pca9547(u8 ch, int bus) +{ + return -EOPNOTSUPP; +} #endif #endif diff --git a/board/nxp/common/pfuze.c b/board/nxp/common/pfuze.c index 0d7a94fd232..179cc605da0 100644 --- a/board/nxp/common/pfuze.c +++ b/board/nxp/common/pfuze.c @@ -7,14 +7,14 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> -#ifndef CONFIG_DM_PMIC_PFUZE100 -int pfuze_mode_init(struct pmic *p, u32 mode) +#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) +int pfuze_mode_init(struct udevice *dev, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = pmic_reg_read(dev, PFUZE100_DEVICEID); id = id & 0xf; if (id == 0) { @@ -28,14 +28,14 @@ int pfuze_mode_init(struct pmic *p, u32 mode) return -EINVAL; } - ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -46,58 +46,54 @@ int pfuze_mode_init(struct pmic *p, u32 mode) return ret; } -struct pmic *pfuze_common_init(unsigned char i2cbus) +struct udevice *pfuze_common_init(void) { - struct pmic *p; + struct udevice *dev; int ret; - unsigned int reg; - - ret = power_pfuze100_init(i2cbus); - if (ret) - return NULL; + unsigned int reg, dev_id, rev_id; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) return NULL; - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* Set SW1AB stanby volage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); - return p; + return dev; } -#elif defined(CONFIG_DM_PMIC) -int pfuze_mode_init(struct udevice *dev, u32 mode) +#else +int pfuze_mode_init(struct pmic *p, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - id = pmic_reg_read(dev, PFUZE100_DEVICEID); + pmic_reg_read(p, PFUZE100_DEVICEID, &id); id = id & 0xf; if (id == 0) { @@ -111,14 +107,14 @@ int pfuze_mode_init(struct udevice *dev, u32 mode) return -EINVAL; } - ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -129,44 +125,48 @@ int pfuze_mode_init(struct udevice *dev, u32 mode) return ret; } -struct udevice *pfuze_common_init(void) +struct pmic *pfuze_common_init(unsigned char i2cbus) { - struct udevice *dev; + struct pmic *p; int ret; - unsigned int reg, dev_id, rev_id; + unsigned int reg; - ret = pmic_get("pfuze100@8", &dev); - if (ret == -ENODEV) + ret = power_pfuze100_init(i2cbus); + if (ret) return NULL; - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return NULL; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); /* Set SW1AB stanby volage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); - return dev; + return p; } #endif diff --git a/board/nxp/common/pfuze.h b/board/nxp/common/pfuze.h index 45b49afaeb7..da89853bd20 100644 --- a/board/nxp/common/pfuze.h +++ b/board/nxp/common/pfuze.h @@ -6,7 +6,7 @@ #ifndef __PFUZE_BOARD_HELPER__ #define __PFUZE_BOARD_HELPER__ -#ifdef CONFIG_DM_PMIC_PFUZE100 +#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) struct udevice *pfuze_common_init(void); int pfuze_mode_init(struct udevice *dev, u32 mode); #else diff --git a/board/nxp/common/vid.c b/board/nxp/common/vid.c index 84cb43fad56..70c3b3ecfd8 100644 --- a/board/nxp/common/vid.c +++ b/board/nxp/common/vid.c @@ -11,6 +11,7 @@ #include <i2c.h> #include <irq_func.h> #include <log.h> +#include <pmbus.h> #include <vsprintf.h> #include <asm/io.h> #ifdef CONFIG_FSL_LSCH2 @@ -260,45 +261,38 @@ static int read_voltage_from_IR(int i2caddress) */ #define VOUT_WARNING "VID: VOUT_MODE exponent has resolution worse than 1 V!\n" -/* Checks the PMBus voltage monitor for the format used for voltage values */ -static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) +/* + * Read VOUT_MODE for downstream LINEAR16 decode/encode through the + * tree level <pmbus.h> helpers (pmbus_reg2data_linear16, + * pmbus_data2reg_linear16). Stores the raw VOUT_MODE byte in *mode + * and returns 0 on success, or the negative bus error (a failed read + * must not be decoded: raw 0 aliases Linear mode with exponent 0). + * Emits VOUT_WARNING on Linear mode chips with a non negative + * exponent (resolution >= 1 V is unusable for sub volt SoC rails) + * and an informational note on the unsupported VID format. + */ +static int vid_read_vout_mode(DEVICE_HANDLE_T dev, u8 *mode) { - u8 mode; - int exponent, multiplier, ret; + int ret; - ret = I2C_READ(dev, PMBUS_CMD_VOUT_MODE, &mode, sizeof(mode)); + ret = pmbus_read_byte(dev, PMBUS_VOUT_MODE, mode); if (ret) { printf("VID: unable to determine voltage multiplier\n"); - return 1; + return ret; } - /* Upper 3 bits is mode, lower 5 bits is exponent */ - exponent = (int)mode & 0x1F; - mode >>= 5; - switch (mode) { - case 0: - /* Linear, 5 bit twos component exponent */ - if (exponent & 0x10) { - multiplier = 1 << (16 - (exponent & 0xF)); - } else { - /* If exponent is >= 0, then resolution is 1 V! */ + switch (*mode & PB_VOUT_MODE_MODE_MASK) { + case PB_VOUT_MODE_LINEAR: + if (!(*mode & 0x10)) printf(VOUT_WARNING); - multiplier = 1; - } break; - case 1: - /* VID code identifier */ + case PB_VOUT_MODE_VID: printf("VID: custom VID codes are not supported\n"); - multiplier = MV_PER_V; break; default: - /* Direct, in mV */ - multiplier = MV_PER_V; break; } - - debug("VID: calculated multiplier is %d\n", multiplier); - return multiplier; + return 0; } #endif @@ -306,8 +300,8 @@ static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) defined(CONFIG_VOL_MONITOR_LTC3882_READ) static int read_voltage_from_pmbus(int i2caddress) { - int ret, multiplier, vout; - u8 channel = PWM_CHANNEL0; + int ret, vout; + u8 channel = PWM_CHANNEL0, vout_mode; u16 vcode; DEVICE_HANDLE_T dev; @@ -317,25 +311,33 @@ static int read_voltage_from_pmbus(int i2caddress) return ret; /* Select the right page */ - ret = I2C_WRITE(dev, PMBUS_CMD_PAGE, &channel, sizeof(channel)); + ret = pmbus_write_byte(dev, PMBUS_PAGE, channel); if (ret) { printf("VID: failed to select VDD page %d\n", channel); return ret; } - /* VOUT is little endian */ - ret = I2C_READ(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, sizeof(vcode)); + ret = pmbus_read_word(dev, PMBUS_READ_VOUT, &vcode); if (ret) { printf("VID: failed to read core voltage\n"); return ret; } - /* Scale down to the real mV */ - multiplier = get_pmbus_multiplier(dev); - vout = (int)vcode; - /* Multiplier 1000 (direct mode) requires no change to convert */ - if (multiplier != MV_PER_V) - vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier); + /* + * Decode LINEAR16 via the tree level helper from <pmbus.h>. For + * non Linear VOUT_MODE settings the helper returns 0; fall back + * to the historic mV pass through so existing LSCH boards keep. + */ + ret = vid_read_vout_mode(dev, &vout_mode); + if (ret) + return ret; + if ((vout_mode & PB_VOUT_MODE_MODE_MASK) == PB_VOUT_MODE_LINEAR) { + s64 uv = pmbus_reg2data_linear16(vcode, vout_mode); + + vout = (int)((uv + 500) / 1000); /* round to mV */ + } else { + vout = (int)vcode; + } return vout - board_vdd_drop_compensation(); } #endif @@ -463,11 +465,13 @@ static int set_voltage_to_IR(int i2caddress, int vdd) static int set_voltage_to_pmbus(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; - int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0, multiplier; + int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0; + u8 vout_mode; + u16 raw; unsigned char value; /* The data to be sent with the PMBus command PAGE_PLUS_WRITE */ - u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 0, 0 }; + u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_VOUT_COMMAND, 0, 0 }; DEVICE_HANDLE_T dev; /* Open device handle */ @@ -475,24 +479,32 @@ static int set_voltage_to_pmbus(int i2caddress, int vdd) if (ret) return ret; - /* Scale up to the proper value for the VOUT command, little endian */ - multiplier = get_pmbus_multiplier(dev); + /* + * Encode target mV as LINEAR16 raw via the tree level helper + * from <pmbus.h>. For non Linear VOUT_MODE settings the helper + * returns 0; fall back to the historic mV pass through. A failed + * VOUT_MODE read aborts: never write a voltage code whose + * encoding could not be determined. + */ vdd += board_vdd_drop_compensation(); - if (multiplier != MV_PER_V) - vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V); - buffer[3] = vdd & 0xFF; - buffer[4] = (vdd & 0xFF00) >> 8; + ret = vid_read_vout_mode(dev, &vout_mode); + if (ret) + return ret; + if ((vout_mode & PB_VOUT_MODE_MODE_MASK) == PB_VOUT_MODE_LINEAR) + raw = pmbus_data2reg_linear16((s64)vdd * 1000LL, vout_mode); + else + raw = (u16)vdd; + buffer[3] = raw & 0xFF; + buffer[4] = (raw & 0xFF00) >> 8; /* Check write protect state */ - ret = I2C_READ(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value, - sizeof(value)); + ret = pmbus_read_byte(dev, PMBUS_WRITE_PROTECT, &value); if (ret) goto exit; if (value != EN_WRITE_ALL_CMD) { value = EN_WRITE_ALL_CMD; - ret = I2C_WRITE(dev, PMBUS_CMD_WRITE_PROTECT, - (void *)&value, sizeof(value)); + ret = pmbus_write_byte(dev, PMBUS_WRITE_PROTECT, value); if (ret) goto exit; } diff --git a/board/nxp/common/vid.h b/board/nxp/common/vid.h index b34c080b4ba..72c1c089aa1 100644 --- a/board/nxp/common/vid.h +++ b/board/nxp/common/vid.h @@ -22,8 +22,9 @@ #define IR_VDD_STEP_UP 5 /* LTC3882 */ -#define PMBUS_CMD_WRITE_PROTECT 0x10 /* + * PMBUS_WRITE_PROTECT (10h) provided by <pmbus.h> + * * WRITE_PROTECT command supported values * 0x80: Disable all writes except WRITE_PROTECT, PAGE, * STORE_USER_ALL and MFR_EE_UNLOCK commands. @@ -51,12 +52,14 @@ #define VDD_MV_MAX 925 #endif -/* PM Bus commands code for LTC3882*/ +/* + * PM Bus commands code for LTC3882. PMBUS_PAGE / PMBUS_READ_VOUT / + * PMBUS_VOUT_MODE / PMBUS_VOUT_COMMAND are provided by <pmbus.h>. + * PMBUS_CMD_PAGE_PLUS_WRITE (05h) is the LTC3882 SMBus block write + * transaction not in <pmbus.h>'s standard subset, so keep its + * definition here. + */ #define PWM_CHANNEL0 0x0 -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_VOUT_MODE 0x20 -#define PMBUS_CMD_VOUT_COMMAND 0x21 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.env b/board/nxp/imx8mm_evk/imx8mm_evk.env index d59bd6fd5ed..88eefaa35e5 100644 --- a/board/nxp/imx8mm_evk/imx8mm_evk.env +++ b/board/nxp/imx8mm_evk/imx8mm_evk.env @@ -12,6 +12,8 @@ initrd_addr=0x48080000 image=Image ip_dyn=yes kernel_addr_r=0x42000000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.env b/board/nxp/imx8mn_evk/imx8mn_evk.env index cffa83bf792..fbdf202c573 100644 --- a/board/nxp/imx8mn_evk/imx8mn_evk.env +++ b/board/nxp/imx8mn_evk/imx8mn_evk.env @@ -12,6 +12,8 @@ initrd_addr=0x48080000 image=Image ip_dyn=yes kernel_addr_r=0x42000000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.env b/board/nxp/imx8mp_evk/imx8mp_evk.env index e994b93b168..dfc922e6215 100644 --- a/board/nxp/imx8mp_evk/imx8mp_evk.env +++ b/board/nxp/imx8mp_evk/imx8mp_evk.env @@ -10,6 +10,8 @@ fdt_addr=0x43000000 fdtfile=DEFAULT_FDT_FILE image=Image ip_dyn=yes +kernel_comp_addr_r=0x80000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw diff --git a/board/nxp/imx8mp_evk/spl.c b/board/nxp/imx8mp_evk/spl.c index 27cd82e745a..cd7d79b382d 100644 --- a/board/nxp/imx8mp_evk/spl.c +++ b/board/nxp/imx8mp_evk/spl.c @@ -65,7 +65,7 @@ int power_init_board(void) * Enable DVS control through PMIC_STBY_REQ and * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ - if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) + if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); else pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); diff --git a/board/nxp/imx8mq_evk/imx8mq_evk.env b/board/nxp/imx8mq_evk/imx8mq_evk.env index 6575dd7cb07..dd674afac91 100644 --- a/board/nxp/imx8mq_evk/imx8mq_evk.env +++ b/board/nxp/imx8mq_evk/imx8mq_evk.env @@ -10,6 +10,8 @@ initrd_addr=0x43800000 image=Image ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x80000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mq_evk/spl.c b/board/nxp/imx8mq_evk/spl.c index 5116d806bb6..80322a2ed19 100644 --- a/board/nxp/imx8mq_evk/spl.c +++ b/board/nxp/imx8mq_evk/spl.c @@ -9,23 +9,16 @@ #include <image.h> #include <init.h> #include <log.h> -#include <asm/io.h> #include <errno.h> #include <asm/io.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <fsl_esdhc_imx.h> -#include <fsl_sec.h> -#include <mmc.h> -#include <linux/delay.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include <dm/uclass.h> +#include <dm/device.h> #include <spl.h> #include "../common/pfuze.h" @@ -40,166 +33,52 @@ static void spl_dram_init(void) ddr_init(&dram_timing_b0); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = 1; - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - return ret; - } - - return 1; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR, 0, 8}, - {USDHC2_BASE_ADDR, 0, 4}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 int power_init_board(void) { - struct pmic *p; + struct udevice *dev; + int reg; int ret; - unsigned int reg; - - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return -ENODEV; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return -ENODEV; + ret = pmic_get("pmic@8", &dev); + if (ret == -ENODEV) { + puts("No pmic@8\n"); + return 0; + } + if (ret < 0) + return ret; - pmic_reg_read(p, PFUZE100_DEVICEID, ®); + reg = pmic_reg_read(dev, PFUZE100_DEVICEID); printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AVOL); if ((reg & 0x3f) != 0x18) { reg &= ~0x3f; reg |= 0x18; - pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + pmic_reg_write(dev, PFUZE100_SW3AVOL, reg); } - ret = pfuze_mode_init(p, APS_PFM); + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; /* set SW3A standby mode to off */ - pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AMODE); reg &= ~0xf; reg |= APS_OFF; - pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + pmic_reg_write(dev, PFUZE100_SW3AMODE, reg); return 0; } -#endif void spl_board_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { - if (sec_init()) - printf("\nsec_init failed!\n"); + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); } puts("Normal Boot\n"); } @@ -218,8 +97,8 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -229,25 +108,22 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } + preloader_console_init(); enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/nxp/imx93_evk/imx93_evk.env b/board/nxp/imx93_evk/imx93_evk.env index b2ed1901a2b..76fadc00eeb 100644 --- a/board/nxp/imx93_evk/imx93_evk.env +++ b/board/nxp/imx93_evk/imx93_evk.env @@ -10,13 +10,16 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted -kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} diff --git a/board/nxp/imx93_frdm/Makefile b/board/nxp/imx93_frdm/Makefile index 9612b1fa55b..751ebfc9458 100644 --- a/board/nxp/imx93_frdm/Makefile +++ b/board/nxp/imx93_frdm/Makefile @@ -7,5 +7,5 @@ obj-y += imx93_frdm.o ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o +obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_1cs_2gb_timing.o lpddr4x_2cs_2gb_timing.o endif diff --git a/board/nxp/imx93_frdm/imx93_frdm.env b/board/nxp/imx93_frdm/imx93_frdm.env index 9af3bdfd714..96096bc51a0 100644 --- a/board/nxp/imx93_frdm/imx93_frdm.env +++ b/board/nxp/imx93_frdm/imx93_frdm.env @@ -10,12 +10,15 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=1 mmcpart=1 mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw mmcautodetect=yes mmcargs=setenv bootargs console=${console} root=${mmcroot} -kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} boot_os=booti ${loadaddr} - ${fdt_addr_r} diff --git a/board/nxp/imx93_frdm/lpddr4_timing.h b/board/nxp/imx93_frdm/lpddr4_timing.h index 192bc9e1519..3ff50d8519b 100644 --- a/board/nxp/imx93_frdm/lpddr4_timing.h +++ b/board/nxp/imx93_frdm/lpddr4_timing.h @@ -7,6 +7,7 @@ #define __LPDDR4_TIMING_H__ extern struct dram_timing_info dram_timing_1GB; -extern struct dram_timing_info dram_timing_2GB; +extern struct dram_timing_info dram_timing_1CS_2GB; +extern struct dram_timing_info dram_timing_2CS_2GB; #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c index cd129e12959..5439a039c3d 100644 --- a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c +++ b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c @@ -1978,7 +1978,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2GB = { +struct dram_timing_info dram_timing_1CS_2GB = { .ddrc_cfg = ddr_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), .ddrphy_cfg = ddr_ddrphy_cfg, diff --git a/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c new file mode 100644 index 00000000000..79539941412 --- /dev/null +++ b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c @@ -0,0 +1,2006 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + * + * Generated code from DDR Gear + * + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44104001 }, + { 0x4e301000, 0x0 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000412 }, + { 0x4e300084, 0x80000412 }, + { 0x4e300114, 0x1002 }, + { 0x4e300260, 0x80 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300800, 0x43b30002 }, + { 0x4e300804, 0x1f1f1f1f }, + { 0x4e301240, 0x0 }, + { 0x4e301244, 0x0 }, + { 0x4e301248, 0x0 }, + { 0x4e30124c, 0x0 }, + { 0x4e301250, 0x0 }, + { 0x4e301254, 0x0 }, + { 0x4e301258, 0x0 }, + { 0x4e30125c, 0x0 }, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + { 0x4e300100, 0x24a0321b }, + { 0x4e300104, 0xfaee001b }, + { 0x4e300108, 0x2f2e3233 }, + { 0x4e30010c, 0x5c18b }, + { 0x4e300124, 0x1c790000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x35f00000 }, + { 0x4e300170, 0x8b0b0608 }, + { 0x4e300250, 0x28 }, + { 0x4e300254, 0xfe00fe }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x224f2213 }, + { 0x4e300304, 0xfe2213 }, + { 0x4e300308, 0xa380e3c }, + }, + { + { 0x01, 0xe4 }, + { 0x02, 0x36 }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 0, + }, + { + { + { 0x4e300100, 0x124f2100 }, + { 0x4e300104, 0xf877000e }, + { 0x4e300108, 0x1816e4aa }, + { 0x4e30010c, 0x5101e6 }, + { 0x4e300124, 0xe3c0000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x30900000 }, + { 0x4e300170, 0x8a0a0508 }, + { 0x4e300250, 0x14 }, + { 0x4e300254, 0x7b007b }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + }, + { + { 0x01, 0xb4 }, + { 0x02, 0x1b }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 0, + }, + { + { + { 0x4e300100, 0x51000 }, + { 0x4e300104, 0xf855000a }, + { 0x4e300108, 0x6e620a48 }, + { 0x4e30010c, 0x31010d }, + { 0x4e300124, 0x4c50000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x30000000 }, + { 0x4e300170, 0x89090408 }, + { 0x4e300250, 0x7 }, + { 0x4e300254, 0x240024 }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + }, + { + { 0x01, 0x94 }, + { 0x02, 0x09 }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 1, + }, +}; + +/* Auto Generated by SNPS PHY Init code + * which inlcude PHYINIT, 1D/2D message block + * rerention CSR, PIE + */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { +/* ADDR mapping is from ds file. */ + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, +/* End of ADDR mapping. */ + { 0x1005f, 0x5ff}, + { 0x1015f, 0x5ff}, + { 0x1105f, 0x5ff}, + { 0x1115f, 0x5ff}, + { 0x11005f, 0x5ff}, + { 0x11015f, 0x5ff}, + { 0x11105f, 0x5ff}, + { 0x11115f, 0x5ff}, + { 0x21005f, 0x5ff}, + { 0x21015f, 0x5ff}, + { 0x21105f, 0x5ff}, + { 0x21115f, 0x5ff}, + { 0x55, 0x1ff}, + { 0x1055, 0x1ff}, + { 0x2055, 0x1ff}, + { 0x200c5, 0x19}, + { 0x1200c5, 0xb}, + { 0x2200c5, 0x7}, + { 0x2002e, 0x2}, + { 0x12002e, 0x2}, + { 0x22002e, 0x2}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x20024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x2007d, 0x212}, + { 0x2007c, 0x61}, + { 0x120024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x12007d, 0x212}, + { 0x12007c, 0x61}, + { 0x220024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x22007d, 0x212}, + { 0x22007c, 0x61}, + { 0x20056, 0x3}, + { 0x120056, 0x3}, + { 0x220056, 0x3}, + { 0x1004d, 0x600}, + { 0x1014d, 0x600}, + { 0x1104d, 0x600}, + { 0x1114d, 0x600}, + { 0x11004d, 0x600}, + { 0x11014d, 0x600}, + { 0x11104d, 0x600}, + { 0x11114d, 0x600}, + { 0x21004d, 0x600}, + { 0x21014d, 0x600}, + { 0x21104d, 0x600}, + { 0x21114d, 0x600}, + { 0x10049, 0xe00}, + { 0x10149, 0xe00}, + { 0x11049, 0xe00}, + { 0x11149, 0xe00}, + { 0x110049, 0xe00}, + { 0x110149, 0xe00}, + { 0x111049, 0xe00}, + { 0x111149, 0xe00}, + { 0x210049, 0xe00}, + { 0x210149, 0xe00}, + { 0x211049, 0xe00}, + { 0x211149, 0xe00}, + { 0x43, 0x60}, + { 0x1043, 0x60}, + { 0x2043, 0x60}, + { 0x20018, 0x1}, + { 0x20075, 0x4}, + { 0x20050, 0x0}, + { 0x2009b, 0x2}, + { 0x20008, 0x3a5}, + { 0x120008, 0x1d3}, + { 0x220008, 0x9c}, + { 0x20088, 0x9}, + { 0x200b2, 0x10c}, + { 0x10043, 0x5a1}, + { 0x10143, 0x5a1}, + { 0x11043, 0x5a1}, + { 0x11143, 0x5a1}, + { 0x1200b2, 0x10c}, + { 0x110043, 0x5a1}, + { 0x110143, 0x5a1}, + { 0x111043, 0x5a1}, + { 0x111143, 0x5a1}, + { 0x2200b2, 0x10c}, + { 0x210043, 0x5a1}, + { 0x210143, 0x5a1}, + { 0x211043, 0x5a1}, + { 0x211143, 0x5a1}, + { 0x200fa, 0x2}, + { 0x1200fa, 0x2}, + { 0x2200fa, 0x2}, + { 0x20019, 0x1}, + { 0x120019, 0x1}, + { 0x220019, 0x1}, + { 0x200f0, 0x600}, + { 0x200f1, 0x0}, + { 0x200f2, 0x4444}, + { 0x200f3, 0x8888}, + { 0x200f4, 0x5655}, + { 0x200f5, 0x0}, + { 0x200f6, 0x0}, + { 0x200f7, 0xf000}, + { 0x1004a, 0x500}, + { 0x1104a, 0x500}, + { 0x20025, 0x0}, + { 0x2002d, 0x0}, + { 0x12002d, 0x0}, + { 0x22002d, 0x0}, + { 0x2002c, 0x0}, + /* workaround STAR_3141216 marker */ + { 0x20021, 0x0}, + /* workaround STAR_3975199 marker */ + { 0x200c7, 0x21}, + /* workaround STAR_3975199 marker */ + { 0x200ca, 0x24}, + /* workaround STAR_3975199 marker */ + { 0x1200c7, 0x21}, + /* workaround STAR_3975199 marker */ + { 0x1200ca, 0x24}, +}; + +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x1005f, 0x0}, + { 0x1015f, 0x0}, + { 0x1105f, 0x0}, + { 0x1115f, 0x0}, + { 0x11005f, 0x0}, + { 0x11015f, 0x0}, + { 0x11105f, 0x0}, + { 0x11115f, 0x0}, + { 0x21005f, 0x0}, + { 0x21015f, 0x0}, + { 0x21105f, 0x0}, + { 0x21115f, 0x0}, + { 0x55, 0x0}, + { 0x1055, 0x0}, + { 0x2055, 0x0}, + { 0x200c5, 0x0}, + { 0x1200c5, 0x0}, + { 0x2200c5, 0x0}, + { 0x2002e, 0x0}, + { 0x12002e, 0x0}, + { 0x22002e, 0x0}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x20024, 0x0}, + { 0x2003a, 0x0}, + { 0x2007d, 0x0}, + { 0x2007c, 0x0}, + { 0x120024, 0x0}, + { 0x12007d, 0x0}, + { 0x12007c, 0x0}, + { 0x220024, 0x0}, + { 0x22007d, 0x0}, + { 0x22007c, 0x0}, + { 0x20056, 0x0}, + { 0x120056, 0x0}, + { 0x220056, 0x0}, + { 0x1004d, 0x0}, + { 0x1014d, 0x0}, + { 0x1104d, 0x0}, + { 0x1114d, 0x0}, + { 0x11004d, 0x0}, + { 0x11014d, 0x0}, + { 0x11104d, 0x0}, + { 0x11114d, 0x0}, + { 0x21004d, 0x0}, + { 0x21014d, 0x0}, + { 0x21104d, 0x0}, + { 0x21114d, 0x0}, + { 0x10049, 0x0}, + { 0x10149, 0x0}, + { 0x11049, 0x0}, + { 0x11149, 0x0}, + { 0x110049, 0x0}, + { 0x110149, 0x0}, + { 0x111049, 0x0}, + { 0x111149, 0x0}, + { 0x210049, 0x0}, + { 0x210149, 0x0}, + { 0x211049, 0x0}, + { 0x211149, 0x0}, + { 0x43, 0x0}, + { 0x1043, 0x0}, + { 0x2043, 0x0}, + { 0x20018, 0x0}, + { 0x20075, 0x0}, + { 0x20050, 0x0}, + { 0x2009b, 0x0}, + { 0x20008, 0x0}, + { 0x120008, 0x0}, + { 0x220008, 0x0}, + { 0x20088, 0x0}, + { 0x200b2, 0x0}, + { 0x10043, 0x0}, + { 0x10143, 0x0}, + { 0x11043, 0x0}, + { 0x11143, 0x0}, + { 0x1200b2, 0x0}, + { 0x110043, 0x0}, + { 0x110143, 0x0}, + { 0x111043, 0x0}, + { 0x111143, 0x0}, + { 0x2200b2, 0x0}, + { 0x210043, 0x0}, + { 0x210143, 0x0}, + { 0x211043, 0x0}, + { 0x211143, 0x0}, + { 0x200fa, 0x0}, + { 0x1200fa, 0x0}, + { 0x2200fa, 0x0}, + { 0x20019, 0x0}, + { 0x120019, 0x0}, + { 0x220019, 0x0}, + { 0x200f0, 0x0}, + { 0x200f1, 0x0}, + { 0x200f2, 0x0}, + { 0x200f3, 0x0}, + { 0x200f4, 0x0}, + { 0x200f5, 0x0}, + { 0x200f6, 0x0}, + { 0x200f7, 0x0}, + { 0x1004a, 0x0}, + { 0x1104a, 0x0}, + { 0x20025, 0x0}, + { 0x2002d, 0x0}, + { 0x12002d, 0x0}, + { 0x22002d, 0x0}, + { 0x2002c, 0x0}, + { 0xd0000, 0x0}, + { 0x90000, 0x0}, + { 0x90001, 0x0}, + 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0x0}, + { 0x100a2, 0x0}, + { 0x100a3, 0x0}, + { 0x100a4, 0x0}, + { 0x100a5, 0x0}, + { 0x100a6, 0x0}, + { 0x100a7, 0x0}, + { 0x11068, 0x0}, + { 0x11069, 0x0}, + { 0x11168, 0x0}, + { 0x11169, 0x0}, + { 0x11268, 0x0}, + { 0x11269, 0x0}, + { 0x11368, 0x0}, + { 0x11369, 0x0}, + { 0x11468, 0x0}, + { 0x11469, 0x0}, + { 0x11568, 0x0}, + { 0x11569, 0x0}, + { 0x11668, 0x0}, + { 0x11669, 0x0}, + { 0x11768, 0x0}, + { 0x11769, 0x0}, + { 0x11868, 0x0}, + { 0x11869, 0x0}, + { 0x110aa, 0x0}, + { 0x11062, 0x0}, + { 0x11001, 0x0}, + { 0x110a0, 0x0}, + { 0x110a1, 0x0}, + { 0x110a2, 0x0}, + { 0x110a3, 0x0}, + { 0x110a4, 0x0}, + { 0x110a5, 0x0}, + { 0x110a6, 0x0}, + { 0x110a7, 0x0}, + { 0x80, 0x0}, + { 0x1080, 0x0}, + { 0x2080, 0x0}, + { 0x10020, 0x0}, + { 0x10080, 0x0}, + { 0x10081, 0x0}, + { 0x100d0, 0x0}, + { 0x100d1, 0x0}, + { 0x1008c, 0x0}, + { 0x1008d, 0x0}, + { 0x10180, 0x0}, + { 0x10181, 0x0}, + { 0x101d0, 0x0}, + { 0x101d1, 0x0}, + { 0x1018c, 0x0}, + { 0x1018d, 0x0}, + { 0x100c0, 0x0}, + { 0x100c1, 0x0}, + { 0x101c0, 0x0}, + { 0x101c1, 0x0}, + { 0x102c0, 0x0}, + { 0x102c1, 0x0}, + { 0x103c0, 0x0}, + { 0x103c1, 0x0}, + { 0x104c0, 0x0}, + { 0x104c1, 0x0}, + { 0x105c0, 0x0}, + { 0x105c1, 0x0}, + { 0x106c0, 0x0}, + { 0x106c1, 0x0}, + { 0x107c0, 0x0}, + { 0x107c1, 0x0}, + { 0x108c0, 0x0}, + { 0x108c1, 0x0}, + { 0x100ae, 0x0}, + { 0x100af, 0x0}, + { 0x11020, 0x0}, + { 0x11080, 0x0}, + { 0x11081, 0x0}, + { 0x110d0, 0x0}, + { 0x110d1, 0x0}, + { 0x1108c, 0x0}, + { 0x1108d, 0x0}, + { 0x11180, 0x0}, + { 0x11181, 0x0}, + { 0x111d0, 0x0}, + { 0x111d1, 0x0}, + { 0x1118c, 0x0}, + { 0x1118d, 0x0}, + { 0x110c0, 0x0}, + { 0x110c1, 0x0}, + { 0x111c0, 0x0}, + { 0x111c1, 0x0}, + { 0x112c0, 0x0}, + { 0x112c1, 0x0}, + { 0x113c0, 0x0}, + { 0x113c1, 0x0}, + { 0x114c0, 0x0}, + { 0x114c1, 0x0}, + { 0x115c0, 0x0}, + { 0x115c1, 0x0}, + { 0x116c0, 0x0}, + { 0x116c1, 0x0}, + { 0x117c0, 0x0}, + { 0x117c1, 0x0}, + { 0x118c0, 0x0}, + { 0x118c1, 0x0}, + { 0x110ae, 0x0}, + { 0x110af, 0x0}, + { 0x90201, 0x0}, + { 0x90202, 0x0}, + { 0x90203, 0x0}, + { 0x90205, 0x0}, + { 0x90206, 0x0}, + { 0x90207, 0x0}, + { 0x90208, 0x0}, + { 0x20020, 0x0}, + { 0x100080, 0x0}, + { 0x101080, 0x0}, + { 0x102080, 0x0}, + { 0x110020, 0x0}, + { 0x110080, 0x0}, + { 0x110081, 0x0}, + { 0x1100d0, 0x0}, + { 0x1100d1, 0x0}, + { 0x11008c, 0x0}, + { 0x11008d, 0x0}, + { 0x110180, 0x0}, + { 0x110181, 0x0}, + { 0x1101d0, 0x0}, + { 0x1101d1, 0x0}, + { 0x11018c, 0x0}, + { 0x11018d, 0x0}, + { 0x1100c0, 0x0}, + { 0x1100c1, 0x0}, + { 0x1101c0, 0x0}, + { 0x1101c1, 0x0}, + { 0x1102c0, 0x0}, + { 0x1102c1, 0x0}, + { 0x1103c0, 0x0}, + { 0x1103c1, 0x0}, + { 0x1104c0, 0x0}, + { 0x1104c1, 0x0}, + { 0x1105c0, 0x0}, + { 0x1105c1, 0x0}, + { 0x1106c0, 0x0}, + { 0x1106c1, 0x0}, + { 0x1107c0, 0x0}, + { 0x1107c1, 0x0}, + { 0x1108c0, 0x0}, + { 0x1108c1, 0x0}, + { 0x1100ae, 0x0}, + { 0x1100af, 0x0}, + { 0x111020, 0x0}, + { 0x111080, 0x0}, + { 0x111081, 0x0}, + { 0x1110d0, 0x0}, + { 0x1110d1, 0x0}, + { 0x11108c, 0x0}, + { 0x11108d, 0x0}, + { 0x111180, 0x0}, + { 0x111181, 0x0}, + { 0x1111d0, 0x0}, + { 0x1111d1, 0x0}, + { 0x11118c, 0x0}, + { 0x11118d, 0x0}, + { 0x1110c0, 0x0}, + { 0x1110c1, 0x0}, + { 0x1111c0, 0x0}, + { 0x1111c1, 0x0}, + { 0x1112c0, 0x0}, + { 0x1112c1, 0x0}, + { 0x1113c0, 0x0}, + { 0x1113c1, 0x0}, + { 0x1114c0, 0x0}, + { 0x1114c1, 0x0}, + { 0x1115c0, 0x0}, + { 0x1115c1, 0x0}, + { 0x1116c0, 0x0}, + { 0x1116c1, 0x0}, + { 0x1117c0, 0x0}, + { 0x1117c1, 0x0}, + { 0x1118c0, 0x0}, + { 0x1118c1, 0x0}, + { 0x1110ae, 0x0}, + { 0x1110af, 0x0}, + { 0x190201, 0x0}, + { 0x190202, 0x0}, + { 0x190203, 0x0}, + { 0x190205, 0x0}, + { 0x190206, 0x0}, + { 0x190207, 0x0}, + { 0x190208, 0x0}, + { 0x120020, 0x0}, + { 0x200080, 0x0}, + { 0x201080, 0x0}, + { 0x202080, 0x0}, + { 0x210020, 0x0}, + { 0x210080, 0x0}, + { 0x210081, 0x0}, + { 0x2100d0, 0x0}, + { 0x2100d1, 0x0}, + { 0x21008c, 0x0}, + { 0x21008d, 0x0}, + { 0x210180, 0x0}, + { 0x210181, 0x0}, + { 0x2101d0, 0x0}, + { 0x2101d1, 0x0}, + { 0x21018c, 0x0}, + { 0x21018d, 0x0}, + { 0x2100c0, 0x0}, + { 0x2100c1, 0x0}, + { 0x2101c0, 0x0}, + { 0x2101c1, 0x0}, + { 0x2102c0, 0x0}, + { 0x2102c1, 0x0}, + { 0x2103c0, 0x0}, + { 0x2103c1, 0x0}, + { 0x2104c0, 0x0}, + { 0x2104c1, 0x0}, + { 0x2105c0, 0x0}, + { 0x2105c1, 0x0}, + { 0x2106c0, 0x0}, + { 0x2106c1, 0x0}, + { 0x2107c0, 0x0}, + { 0x2107c1, 0x0}, + { 0x2108c0, 0x0}, + { 0x2108c1, 0x0}, + { 0x2100ae, 0x0}, + { 0x2100af, 0x0}, + { 0x211020, 0x0}, + { 0x211080, 0x0}, + { 0x211081, 0x0}, + { 0x2110d0, 0x0}, + { 0x2110d1, 0x0}, + { 0x21108c, 0x0}, + { 0x21108d, 0x0}, + { 0x211180, 0x0}, + { 0x211181, 0x0}, + { 0x2111d0, 0x0}, + { 0x2111d1, 0x0}, + { 0x21118c, 0x0}, + { 0x21118d, 0x0}, + { 0x2110c0, 0x0}, + { 0x2110c1, 0x0}, + { 0x2111c0, 0x0}, + { 0x2111c1, 0x0}, + { 0x2112c0, 0x0}, + { 0x2112c1, 0x0}, + { 0x2113c0, 0x0}, + { 0x2113c1, 0x0}, + { 0x2114c0, 0x0}, + { 0x2114c1, 0x0}, + { 0x2115c0, 0x0}, + { 0x2115c1, 0x0}, + { 0x2116c0, 0x0}, + { 0x2116c1, 0x0}, + { 0x2117c0, 0x0}, + { 0x2117c1, 0x0}, + { 0x2118c0, 0x0}, + { 0x2118c1, 0x0}, + { 0x2110ae, 0x0}, + { 0x2110af, 0x0}, + { 0x290201, 0x0}, + { 0x290202, 0x0}, + { 0x290203, 0x0}, + { 0x290205, 0x0}, + { 0x290206, 0x0}, + { 0x290207, 0x0}, + { 0x290208, 0x0}, + { 0x220020, 0x0}, + { 0x20077, 0x0}, + { 0x20072, 0x0}, + { 0x20073, 0x0}, + { 0x400c0, 0x0}, + { 0x10040, 0x0}, + { 0x10140, 0x0}, + { 0x10240, 0x0}, + { 0x10340, 0x0}, + { 0x10440, 0x0}, + { 0x10540, 0x0}, + { 0x10640, 0x0}, + { 0x10740, 0x0}, + { 0x10840, 0x0}, + { 0x11040, 0x0}, + { 0x11140, 0x0}, + { 0x11240, 0x0}, + { 0x11340, 0x0}, + { 0x11440, 0x0}, + { 0x11540, 0x0}, + { 0x11640, 0x0}, + { 0x11740, 0x0}, + { 0x11840, 0x0}, +}; + +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0}, + { 0x54003, 0xe94}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x131f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x36e4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x36e4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xe400}, + { 0x54033, 0x3236}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xe400}, + { 0x54039, 0x3236}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0}, + { 0x54002, 0x1}, + { 0x54003, 0x74a}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x121f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x1bb4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x1bb4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xb400}, + { 0x54033, 0x321b}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xb400}, + { 0x54039, 0x321b}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0}, + { 0x54002, 0x102}, + { 0x54003, 0x270}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x121f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x994}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1100}, + { 0x5401e, 0x4}, + { 0x5401f, 0x994}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1100}, + { 0x54024, 0x4}, + { 0x54032, 0x9400}, + { 0x54033, 0x3209}, + { 0x54034, 0x2600}, + { 0x54035, 0x11}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0x9400}, + { 0x54039, 0x3209}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x11}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0}, + { 0x54003, 0xe94}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x61}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54010, 0x2080}, + { 0x54012, 0x310}, + { 0x54019, 0x36e4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x36e4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xe400}, + { 0x54033, 0x3236}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xe400}, + { 0x54039, 0x3236}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0}, + { 0x90000, 0x10}, + { 0x90001, 0x400}, + { 0x90002, 0x10e}, + { 0x90003, 0x0}, + { 0x90004, 0x0}, + { 0x90005, 0x8}, + { 0x90029, 0xb}, + { 0x9002a, 0x480}, + { 0x9002b, 0x109}, + { 0x9002c, 0x8}, + { 0x9002d, 0x448}, + { 0x9002e, 0x139}, + { 0x9002f, 0x8}, + { 0x90030, 0x478}, + { 0x90031, 0x109}, + { 0x90032, 0x0}, + { 0x90033, 0xe8}, + { 0x90034, 0x109}, + { 0x90035, 0x2}, + { 0x90036, 0x10}, + { 0x90037, 0x139}, + { 0x90038, 0xb}, + { 0x90039, 0x7c0}, + { 0x9003a, 0x139}, + { 0x9003b, 0x44}, + { 0x9003c, 0x633}, + { 0x9003d, 0x159}, + { 0x9003e, 0x14f}, + { 0x9003f, 0x630}, + { 0x90040, 0x159}, + { 0x90041, 0x47}, + { 0x90042, 0x633}, + { 0x90043, 0x149}, + { 0x90044, 0x4f}, + { 0x90045, 0x633}, + { 0x90046, 0x179}, + { 0x90047, 0x8}, + { 0x90048, 0xe0}, + { 0x90049, 0x109}, + { 0x9004a, 0x0}, + { 0x9004b, 0x7c8}, + { 0x9004c, 0x109}, + { 0x9004d, 0x0}, + { 0x9004e, 0x1}, + { 0x9004f, 0x8}, + { 0x90050, 0x30}, + { 0x90051, 0x65a}, + { 0x90052, 0x9}, + { 0x90053, 0x0}, + { 0x90054, 0x45a}, + { 0x90055, 0x9}, + { 0x90056, 0x0}, + { 0x90057, 0x448}, + { 0x90058, 0x109}, + { 0x90059, 0x40}, + { 0x9005a, 0x633}, + { 0x9005b, 0x179}, + { 0x9005c, 0x1}, + { 0x9005d, 0x618}, + { 0x9005e, 0x109}, + { 0x9005f, 0x40c0}, + { 0x90060, 0x633}, + { 0x90061, 0x149}, + { 0x90062, 0x8}, + { 0x90063, 0x4}, + { 0x90064, 0x48}, + { 0x90065, 0x4040}, + { 0x90066, 0x633}, + { 0x90067, 0x149}, + { 0x90068, 0x0}, + { 0x90069, 0x4}, + { 0x9006a, 0x48}, + { 0x9006b, 0x40}, + { 0x9006c, 0x633}, + { 0x9006d, 0x149}, + { 0x9006e, 0x0}, + { 0x9006f, 0x658}, + { 0x90070, 0x109}, + { 0x90071, 0x10}, + { 0x90072, 0x4}, + { 0x90073, 0x18}, + { 0x90074, 0x0}, + { 0x90075, 0x4}, + { 0x90076, 0x78}, + { 0x90077, 0x549}, + { 0x90078, 0x633}, + { 0x90079, 0x159}, + { 0x9007a, 0xd49}, + { 0x9007b, 0x633}, + { 0x9007c, 0x159}, + { 0x9007d, 0x94a}, + { 0x9007e, 0x633}, + { 0x9007f, 0x159}, + { 0x90080, 0x441}, + { 0x90081, 0x633}, + { 0x90082, 0x149}, + { 0x90083, 0x42}, + { 0x90084, 0x633}, + { 0x90085, 0x149}, + { 0x90086, 0x1}, + { 0x90087, 0x633}, + { 0x90088, 0x149}, + { 0x90089, 0x0}, + { 0x9008a, 0xe0}, + { 0x9008b, 0x109}, + { 0x9008c, 0xa}, + { 0x9008d, 0x10}, + { 0x9008e, 0x109}, + { 0x9008f, 0x9}, + { 0x90090, 0x3c0}, + { 0x90091, 0x149}, + { 0x90092, 0x9}, + { 0x90093, 0x3c0}, + { 0x90094, 0x159}, + { 0x90095, 0x18}, + { 0x90096, 0x10}, + { 0x90097, 0x109}, + { 0x90098, 0x0}, + { 0x90099, 0x3c0}, + { 0x9009a, 0x109}, + { 0x9009b, 0x18}, + { 0x9009c, 0x4}, + { 0x9009d, 0x48}, + { 0x9009e, 0x18}, + { 0x9009f, 0x4}, + { 0x900a0, 0x58}, + { 0x900a1, 0xb}, + { 0x900a2, 0x10}, + { 0x900a3, 0x109}, + { 0x900a4, 0x1}, + { 0x900a5, 0x10}, + { 0x900a6, 0x109}, + { 0x900a7, 0x5}, + { 0x900a8, 0x7c0}, + { 0x900a9, 0x109}, + { 0x40000, 0x811}, + { 0x40020, 0x880}, + { 0x40040, 0x0}, + { 0x40060, 0x0}, + { 0x40001, 0x4008}, + { 0x40021, 0x83}, + { 0x40041, 0x4f}, + { 0x40061, 0x0}, + { 0x40002, 0x4040}, + { 0x40022, 0x83}, + { 0x40042, 0x51}, + { 0x40062, 0x0}, + { 0x40003, 0x811}, + { 0x40023, 0x880}, + { 0x40043, 0x0}, + { 0x40063, 0x0}, + { 0x40004, 0x720}, + { 0x40024, 0xf}, + { 0x40044, 0x1740}, + { 0x40064, 0x0}, + { 0x40005, 0x16}, + { 0x40025, 0x83}, + { 0x40045, 0x4b}, + { 0x40065, 0x0}, + { 0x40006, 0x716}, + { 0x40026, 0xf}, + { 0x40046, 0x2001}, + { 0x40066, 0x0}, + { 0x40007, 0x716}, + { 0x40027, 0xf}, + { 0x40047, 0x2800}, + { 0x40067, 0x0}, + { 0x40008, 0x716}, + { 0x40028, 0xf}, + { 0x40048, 0xf00}, + { 0x40068, 0x0}, + { 0x40009, 0x720}, + { 0x40029, 0xf}, + { 0x40049, 0x1400}, + { 0x40069, 0x0}, + { 0x4000a, 0xe08}, + { 0x4002a, 0xc15}, + { 0x4004a, 0x0}, + { 0x4006a, 0x0}, + { 0x4000b, 0x625}, + { 0x4002b, 0x15}, + { 0x4004b, 0x0}, + { 0x4006b, 0x0}, + { 0x4000c, 0x4028}, + { 0x4002c, 0x80}, + { 0x4004c, 0x0}, + { 0x4006c, 0x0}, + { 0x4000d, 0xe08}, + { 0x4002d, 0xc1a}, + { 0x4004d, 0x0}, + { 0x4006d, 0x0}, + { 0x4000e, 0x625}, + { 0x4002e, 0x1a}, + { 0x4004e, 0x0}, + { 0x4006e, 0x0}, + { 0x4000f, 0x4040}, + { 0x4002f, 0x80}, + { 0x4004f, 0x0}, + { 0x4006f, 0x0}, + { 0x40010, 0x2604}, + { 0x40030, 0x15}, + { 0x40050, 0x0}, + { 0x40070, 0x0}, + { 0x40011, 0x708}, + { 0x40031, 0x5}, + { 0x40051, 0x0}, + { 0x40071, 0x2002}, + { 0x40012, 0x8}, + { 0x40032, 0x80}, + { 0x40052, 0x0}, + { 0x40072, 0x0}, + { 0x40013, 0x2604}, + { 0x40033, 0x1a}, + { 0x40053, 0x0}, + { 0x40073, 0x0}, + { 0x40014, 0x708}, + { 0x40034, 0xa}, + { 0x40054, 0x0}, + { 0x40074, 0x2002}, + { 0x40015, 0x4040}, + { 0x40035, 0x80}, + { 0x40055, 0x0}, + { 0x40075, 0x0}, + { 0x40016, 0x60a}, + { 0x40036, 0x15}, + { 0x40056, 0x1200}, + { 0x40076, 0x0}, + { 0x40017, 0x61a}, + { 0x40037, 0x15}, + { 0x40057, 0x1300}, + { 0x40077, 0x0}, + { 0x40018, 0x60a}, + { 0x40038, 0x1a}, + { 0x40058, 0x1200}, + { 0x40078, 0x0}, + { 0x40019, 0x642}, + { 0x40039, 0x1a}, + { 0x40059, 0x1300}, + { 0x40079, 0x0}, + { 0x4001a, 0x4808}, + { 0x4003a, 0x880}, + { 0x4005a, 0x0}, + { 0x4007a, 0x0}, + { 0x900aa, 0x0}, + { 0x900ab, 0x790}, + { 0x900ac, 0x11a}, + { 0x900ad, 0x8}, + { 0x900ae, 0x7aa}, + { 0x900af, 0x2a}, + { 0x900b0, 0x10}, + { 0x900b1, 0x7b2}, + { 0x900b2, 0x2a}, + { 0x900b3, 0x0}, + { 0x900b4, 0x7c8}, + { 0x900b5, 0x109}, + { 0x900b6, 0x10}, + { 0x900b7, 0x10}, + { 0x900b8, 0x109}, + { 0x900b9, 0x10}, + { 0x900ba, 0x2a8}, + { 0x900bb, 0x129}, + { 0x900bc, 0x8}, + { 0x900bd, 0x370}, + { 0x900be, 0x129}, + { 0x900bf, 0xa}, + { 0x900c0, 0x3c8}, + { 0x900c1, 0x1a9}, + { 0x900c2, 0xc}, + { 0x900c3, 0x408}, + { 0x900c4, 0x199}, + { 0x900c5, 0x14}, + { 0x900c6, 0x790}, + { 0x900c7, 0x11a}, + { 0x900c8, 0x8}, + { 0x900c9, 0x4}, + { 0x900ca, 0x18}, + { 0x900cb, 0xe}, + { 0x900cc, 0x408}, + { 0x900cd, 0x199}, + { 0x900ce, 0x8}, + { 0x900cf, 0x8568}, + { 0x900d0, 0x108}, + { 0x900d1, 0x18}, + { 0x900d2, 0x790}, + { 0x900d3, 0x16a}, + { 0x900d4, 0x8}, + { 0x900d5, 0x1d8}, + { 0x900d6, 0x169}, + { 0x900d7, 0x10}, + { 0x900d8, 0x8558}, + { 0x900d9, 0x168}, + { 0x900da, 0x1ff8}, + { 0x900db, 0x85a8}, + { 0x900dc, 0x1e8}, + { 0x900dd, 0x50}, + { 0x900de, 0x798}, + { 0x900df, 0x16a}, + { 0x900e0, 0x60}, + { 0x900e1, 0x7a0}, + { 0x900e2, 0x16a}, + { 0x900e3, 0x8}, + { 0x900e4, 0x8310}, + { 0x900e5, 0x168}, + { 0x900e6, 0x8}, + { 0x900e7, 0xa310}, + { 0x900e8, 0x168}, + { 0x900e9, 0xa}, + { 0x900ea, 0x408}, + { 0x900eb, 0x169}, + { 0x900ec, 0x6e}, + { 0x900ed, 0x0}, + { 0x900ee, 0x68}, + { 0x900ef, 0x0}, + { 0x900f0, 0x408}, + { 0x900f1, 0x169}, + { 0x900f2, 0x0}, + { 0x900f3, 0x8310}, + { 0x900f4, 0x168}, + { 0x900f5, 0x0}, + { 0x900f6, 0xa310}, + { 0x900f7, 0x168}, + { 0x900f8, 0x1ff8}, + { 0x900f9, 0x85a8}, + { 0x900fa, 0x1e8}, + { 0x900fb, 0x68}, + { 0x900fc, 0x798}, + { 0x900fd, 0x16a}, + { 0x900fe, 0x78}, + { 0x900ff, 0x7a0}, + { 0x90100, 0x16a}, + { 0x90101, 0x68}, + { 0x90102, 0x790}, + { 0x90103, 0x16a}, + { 0x90104, 0x8}, + { 0x90105, 0x8b10}, + { 0x90106, 0x168}, + { 0x90107, 0x8}, + { 0x90108, 0xab10}, + { 0x90109, 0x168}, + { 0x9010a, 0xa}, + { 0x9010b, 0x408}, + { 0x9010c, 0x169}, + { 0x9010d, 0x58}, + { 0x9010e, 0x0}, + { 0x9010f, 0x68}, + { 0x90110, 0x0}, + { 0x90111, 0x408}, + { 0x90112, 0x169}, + { 0x90113, 0x0}, + { 0x90114, 0x8b10}, + { 0x90115, 0x168}, + { 0x90116, 0x1}, + { 0x90117, 0xab10}, + { 0x90118, 0x168}, + { 0x90119, 0x0}, + { 0x9011a, 0x1d8}, + { 0x9011b, 0x169}, + { 0x9011c, 0x80}, + { 0x9011d, 0x790}, + { 0x9011e, 0x16a}, + { 0x9011f, 0x18}, + { 0x90120, 0x7aa}, + { 0x90121, 0x6a}, + { 0x90122, 0xa}, + { 0x90123, 0x0}, + { 0x90124, 0x1e9}, + { 0x90125, 0x8}, + { 0x90126, 0x8080}, + { 0x90127, 0x108}, + { 0x90128, 0xf}, + { 0x90129, 0x408}, + { 0x9012a, 0x169}, + { 0x9012b, 0xc}, + { 0x9012c, 0x0}, + { 0x9012d, 0x68}, + { 0x9012e, 0x9}, + { 0x9012f, 0x0}, + { 0x90130, 0x1a9}, + { 0x90131, 0x0}, + { 0x90132, 0x408}, + { 0x90133, 0x169}, + { 0x90134, 0x0}, + { 0x90135, 0x8080}, + { 0x90136, 0x108}, + { 0x90137, 0x8}, + { 0x90138, 0x7aa}, + { 0x90139, 0x6a}, + { 0x9013a, 0x0}, + { 0x9013b, 0x8568}, + { 0x9013c, 0x108}, + { 0x9013d, 0xb7}, + { 0x9013e, 0x790}, + { 0x9013f, 0x16a}, + { 0x90140, 0x1f}, + { 0x90141, 0x0}, + { 0x90142, 0x68}, + { 0x90143, 0x8}, + { 0x90144, 0x8558}, + { 0x90145, 0x168}, + { 0x90146, 0xf}, + { 0x90147, 0x408}, + { 0x90148, 0x169}, + { 0x90149, 0xd}, + { 0x9014a, 0x0}, + { 0x9014b, 0x68}, + { 0x9014c, 0x0}, + { 0x9014d, 0x408}, + { 0x9014e, 0x169}, + { 0x9014f, 0x0}, + { 0x90150, 0x8558}, + { 0x90151, 0x168}, + { 0x90152, 0x8}, + { 0x90153, 0x3c8}, + { 0x90154, 0x1a9}, + { 0x90155, 0x3}, + { 0x90156, 0x370}, + { 0x90157, 0x129}, + { 0x90158, 0x20}, + { 0x90159, 0x2aa}, + { 0x9015a, 0x9}, + { 0x9015b, 0x8}, + { 0x9015c, 0xe8}, + { 0x9015d, 0x109}, + { 0x9015e, 0x0}, + { 0x9015f, 0x8140}, + { 0x90160, 0x10c}, + { 0x90161, 0x10}, + { 0x90162, 0x8138}, + { 0x90163, 0x104}, + { 0x90164, 0x8}, + { 0x90165, 0x448}, + { 0x90166, 0x109}, + { 0x90167, 0xf}, + { 0x90168, 0x7c0}, + { 0x90169, 0x109}, + { 0x9016a, 0x0}, + { 0x9016b, 0xe8}, + { 0x9016c, 0x109}, + { 0x9016d, 0x47}, + { 0x9016e, 0x630}, + { 0x9016f, 0x109}, + { 0x90170, 0x8}, + { 0x90171, 0x618}, + { 0x90172, 0x109}, + { 0x90173, 0x8}, + { 0x90174, 0xe0}, + { 0x90175, 0x109}, + { 0x90176, 0x0}, + { 0x90177, 0x7c8}, + { 0x90178, 0x109}, + { 0x90179, 0x8}, + { 0x9017a, 0x8140}, + { 0x9017b, 0x10c}, + { 0x9017c, 0x0}, + { 0x9017d, 0x478}, + { 0x9017e, 0x109}, + { 0x9017f, 0x0}, + { 0x90180, 0x1}, + { 0x90181, 0x8}, + { 0x90182, 0x8}, + { 0x90183, 0x4}, + { 0x90184, 0x0}, + { 0x90006, 0x8}, + { 0x90007, 0x7c8}, + { 0x90008, 0x109}, + { 0x90009, 0x0}, + { 0x9000a, 0x400}, + { 0x9000b, 0x106}, + { 0xd00e7, 0x400}, + { 0x90017, 0x0}, + { 0x9001f, 0x2b}, + { 0x90026, 0x69}, + { 0x400d0, 0x0}, + { 0x400d1, 0x101}, + { 0x400d2, 0x105}, + { 0x400d3, 0x107}, + { 0x400d4, 0x10f}, + { 0x400d5, 0x202}, + { 0x400d6, 0x20a}, + { 0x400d7, 0x20b}, + { 0x2003a, 0x2}, + { 0x200be, 0x3}, + { 0x2000b, 0x75}, + { 0x2000c, 0xe9}, + { 0x2000d, 0x91c}, + { 0x2000e, 0x2c}, + { 0x12000b, 0x3b}, + { 0x12000c, 0x74}, + { 0x12000d, 0x48e}, + { 0x12000e, 0x2c}, + { 0x22000b, 0x14}, + { 0x22000c, 0x27}, + { 0x22000d, 0x186}, + { 0x22000e, 0x10}, + { 0x9000c, 0x0}, + { 0x9000d, 0x173}, + { 0x9000e, 0x60}, + { 0x9000f, 0x6110}, + { 0x90010, 0x2152}, + { 0x90011, 0xdfbd}, + { 0x90012, 0x2060}, + { 0x90013, 0x6152}, + { 0x20010, 0x5a}, + { 0x20011, 0x3}, + { 0x120010, 0x5a}, + { 0x120011, 0x3}, + { 0x40080, 0xe0}, + { 0x40081, 0x12}, + { 0x40082, 0xe0}, + { 0x40083, 0x12}, + { 0x40084, 0xe0}, + { 0x40085, 0x12}, + { 0x140080, 0xe0}, + { 0x140081, 0x12}, + { 0x140082, 0xe0}, + { 0x140083, 0x12}, + { 0x140084, 0xe0}, + { 0x140085, 0x12}, + { 0x240080, 0xe0}, + { 0x240081, 0x12}, + { 0x240082, 0xe0}, + { 0x240083, 0x12}, + { 0x240084, 0xe0}, + { 0x240085, 0x12}, + { 0x400fd, 0xf}, + { 0x400f1, 0xe}, + { 0x10011, 0x1}, + { 0x10012, 0x1}, + { 0x10013, 0x180}, + { 0x10018, 0x1}, + { 0x10002, 0x6209}, + { 0x100b2, 0x1}, + { 0x101b4, 0x1}, + { 0x102b4, 0x1}, + { 0x103b4, 0x1}, + { 0x104b4, 0x1}, + { 0x105b4, 0x1}, + { 0x106b4, 0x1}, + { 0x107b4, 0x1}, + { 0x108b4, 0x1}, + { 0x11011, 0x1}, + { 0x11012, 0x1}, + { 0x11013, 0x180}, + { 0x11018, 0x1}, + { 0x11002, 0x6209}, + { 0x110b2, 0x1}, + { 0x111b4, 0x1}, + { 0x112b4, 0x1}, + { 0x113b4, 0x1}, + { 0x114b4, 0x1}, + { 0x115b4, 0x1}, + { 0x116b4, 0x1}, + { 0x117b4, 0x1}, + { 0x118b4, 0x1}, + { 0x20089, 0x1}, + { 0x20088, 0x19}, + { 0xc0080, 0x0}, + /* workaround STAR_3256585 marker */ + { 0x2000b, 0x41a}, + /* workaround STAR_3256585 marker */ + { 0x12000b, 0x20d}, + /* workaround STAR_3256585 marker */ + { 0x22000b, 0xb0}, + { 0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2CS_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_frdm/spl.c b/board/nxp/imx93_frdm/spl.c index 068091ba0e9..40054ff72d0 100644 --- a/board/nxp/imx93_frdm/spl.c +++ b/board/nxp/imx93_frdm/spl.c @@ -33,9 +33,10 @@ static struct _drams { u8 mr8; struct dram_timing_info *pdram_timing; char *name; -} frdm_drams[2] = { +} frdm_drams[3] = { {0x10, &dram_timing_1GB, "1GB DRAM" }, - {0x18, &dram_timing_2GB, "2GB DRAM" }, + {0x12, &dram_timing_2CS_2GB, "2CS_2GB DRAM" }, + {0x18, &dram_timing_1CS_2GB, "1CS_2GB DRAM" }, }; int spl_board_boot_device(enum boot_device boot_dev_spl) diff --git a/board/nxp/imx93_qsb/imx93_qsb.env b/board/nxp/imx93_qsb/imx93_qsb.env index d669c6e3133..d14a1b6c9bd 100644 --- a/board/nxp/imx93_qsb/imx93_qsb.env +++ b/board/nxp/imx93_qsb/imx93_qsb.env @@ -10,6 +10,10 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw diff --git a/board/nxp/imx94_evk/imx94_evk.c b/board/nxp/imx94_evk/imx94_evk.c index 4731b79b55d..02149afae87 100644 --- a/board/nxp/imx94_evk/imx94_evk.c +++ b/board/nxp/imx94_evk/imx94_evk.c @@ -7,7 +7,7 @@ #include <fdt_support.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/sys_proto.h> +#include <asm/arch/sys_proto.h> int board_init(void) { @@ -26,3 +26,11 @@ int board_late_init(void) return 0; } + +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *fdt) +{ + /* Remove nodes based on fuses. */ + return imx9_uboot_fixup_by_fuse(fdt); +} +#endif diff --git a/board/nxp/imx94_evk/imx94_evk.env b/board/nxp/imx94_evk/imx94_evk.env index 894f5975812..c2006c95529 100644 --- a/board/nxp/imx94_evk/imx94_evk.env +++ b/board/nxp/imx94_evk/imx94_evk.env @@ -19,7 +19,10 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 +ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 image=Image splashimage=0xA0000000 console=ttyLP0,115200 earlycon diff --git a/board/nxp/imx94_evk/spl.c b/board/nxp/imx94_evk/spl.c index 6eb0fff99f4..739a5f1f559 100644 --- a/board/nxp/imx94_evk/spl.c +++ b/board/nxp/imx94_evk/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ #include <hang.h> @@ -14,6 +14,7 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> DECLARE_GLOBAL_DATA_PTR; @@ -44,6 +45,9 @@ void spl_board_init(void) ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); } static void xspi_nor_reset(void) diff --git a/board/nxp/imx952_evk/imx952_evk.c b/board/nxp/imx952_evk/imx952_evk.c index 2a61817939e..b5c2da032a8 100644 --- a/board/nxp/imx952_evk/imx952_evk.c +++ b/board/nxp/imx952_evk/imx952_evk.c @@ -24,3 +24,11 @@ int board_late_init(void) return 0; } + +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *fdt) +{ + /* Remove nodes based on fuses. */ + return imx9_uboot_fixup_by_fuse(fdt); +} +#endif diff --git a/board/nxp/imx952_evk/imx952_evk.env b/board/nxp/imx952_evk/imx952_evk.env index 6ecaf9724c1..07faeb9fc9a 100644 --- a/board/nxp/imx952_evk/imx952_evk.env +++ b/board/nxp/imx952_evk/imx952_evk.env @@ -52,7 +52,10 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 +ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 image=Image splashimage=0xA0000000 console=ttyLP0,115200 earlycon diff --git a/board/nxp/imx952_evk/spl.c b/board/nxp/imx952_evk/spl.c index de9256dc267..615c3b67fb6 100644 --- a/board/nxp/imx952_evk/spl.c +++ b/board/nxp/imx952_evk/spl.c @@ -8,6 +8,7 @@ #include <asm/gpio.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> #include <asm/sections.h> #include <hang.h> #include <init.h> @@ -44,6 +45,9 @@ void spl_board_init(void) ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); } static void xspi_nor_reset(void) diff --git a/board/nxp/imx95_evk/imx95_evk.c b/board/nxp/imx95_evk/imx95_evk.c index 99a37e0593f..394d6fd459c 100644 --- a/board/nxp/imx95_evk/imx95_evk.c +++ b/board/nxp/imx95_evk/imx95_evk.c @@ -5,7 +5,7 @@ #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/sys_proto.h> +#include <asm/arch/sys_proto.h> int board_late_init(void) { @@ -14,3 +14,11 @@ int board_late_init(void) return 0; } + +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *fdt) +{ + /* Remove nodes based on fuses. */ + return imx9_uboot_fixup_by_fuse(fdt); +} +#endif diff --git a/board/nxp/imx95_evk/imx95_evk.env b/board/nxp/imx95_evk/imx95_evk.env index 19f9bd5c16e..1d63a74aefa 100644 --- a/board/nxp/imx95_evk/imx95_evk.env +++ b/board/nxp/imx95_evk/imx95_evk.env @@ -3,8 +3,11 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 -kernel_addr_r=CONFIG_SYS_LOAD_ADDR image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 splashimage=0xA0000000 console=ttyLP0,115200 earlycon fdt_addr_r=0x93000000 diff --git a/board/nxp/imx95_evk/spl.c b/board/nxp/imx95_evk/spl.c index 761a1a4a0f6..2fd69447e1e 100644 --- a/board/nxp/imx95_evk/spl.c +++ b/board/nxp/imx95_evk/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ #include <hang.h> @@ -13,6 +13,7 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +42,9 @@ void spl_board_init(void) ret = ele_start_rng(); if (ret) printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); } void board_init_f(ulong dummy) diff --git a/board/nxp/imxrt1020-evk/imxrt1020-evk.c b/board/nxp/imxrt1020-evk/imxrt1020-evk.c index 11dbef84688..6843b33679d 100644 --- a/board/nxp/imxrt1020-evk/imxrt1020-evk.c +++ b/board/nxp/imxrt1020-evk/imxrt1020-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1050-evk/imxrt1050-evk.c b/board/nxp/imxrt1050-evk/imxrt1050-evk.c index 056489932ac..19d068fc626 100644 --- a/board/nxp/imxrt1050-evk/imxrt1050-evk.c +++ b/board/nxp/imxrt1050-evk/imxrt1050-evk.c @@ -78,7 +78,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/imxrt1170-evk/imxrt1170-evk.c b/board/nxp/imxrt1170-evk/imxrt1170-evk.c index 047aea8181a..3afd5ae2136 100644 --- a/board/nxp/imxrt1170-evk/imxrt1170-evk.c +++ b/board/nxp/imxrt1170-evk/imxrt1170-evk.c @@ -73,7 +73,7 @@ u32 spl_boot_device(void) int board_init(void) { - gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + gd->bd->bi_boot_params = gd->dram[0].start + 0x100; return 0; } diff --git a/board/nxp/ls1012afrdm/eth.c b/board/nxp/ls1012afrdm/eth.c index c431e5e611b..8761ec7845e 100644 --- a/board/nxp/ls1012afrdm/eth.c +++ b/board/nxp/ls1012afrdm/eth.c @@ -7,16 +7,6 @@ #include <dm.h> #include <net.h> #include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <asm/types.h> -#include <fsl_dtsec.h> -#include <asm/arch/soc.h> -#include <asm/arch-fsl-layerscape/config.h> -#include <asm/arch-fsl-layerscape/immap_lsch2.h> -#include <asm/arch/fsl_serdes.h> #include <linux/delay.h> #include <net/pfe_eth/pfe_eth.h> #include <dm/platform_data/pfe_dm_eth.h> diff --git a/board/nxp/ls1012ardb/Kconfig b/board/nxp/ls1012ardb/Kconfig index bbe5ce21109..ff5a57aaa41 100644 --- a/board/nxp/ls1012ardb/Kconfig +++ b/board/nxp/ls1012ardb/Kconfig @@ -63,7 +63,7 @@ config SYS_BOARD default "ls1012ardb" config SYS_VENDOR - default "nxp" + default "nxp" config SYS_SOC default "fsl-layerscape" diff --git a/board/nxp/ls1012ardb/eth.c b/board/nxp/ls1012ardb/eth.c index 71cb2988a56..6a6f4608fd1 100644 --- a/board/nxp/ls1012ardb/eth.c +++ b/board/nxp/ls1012ardb/eth.c @@ -6,18 +6,6 @@ #include <config.h> #include <dm.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <asm/types.h> -#include <fsl_dtsec.h> -#include <asm/arch/soc.h> -#include <asm/arch-fsl-layerscape/config.h> -#include <asm/arch-fsl-layerscape/immap_lsch2.h> -#include <asm/arch/fsl_serdes.h> #include <linux/delay.h> #include <net/pfe_eth/pfe_eth.h> #include <dm/platform_data/pfe_dm_eth.h> diff --git a/board/nxp/ls1021aqds/ddr.c b/board/nxp/ls1021aqds/ddr.c index fd897e832c8..8d07f6110ce 100644 --- a/board/nxp/ls1021aqds/ddr.c +++ b/board/nxp/ls1021aqds/ddr.c @@ -192,8 +192,8 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/nxp/ls1021atsn/ls1021atsn.c b/board/nxp/ls1021atsn/ls1021atsn.c index c92430c0896..277506fdbb8 100644 --- a/board/nxp/ls1021atsn/ls1021atsn.c +++ b/board/nxp/ls1021atsn/ls1021atsn.c @@ -123,11 +123,6 @@ int dram_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; diff --git a/board/nxp/ls1021atwr/ls1021atwr.c b/board/nxp/ls1021atwr/ls1021atwr.c index 0758e5eae25..135497f7c5d 100644 --- a/board/nxp/ls1021atwr/ls1021atwr.c +++ b/board/nxp/ls1021atwr/ls1021atwr.c @@ -239,11 +239,6 @@ int dram_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) static void convert_serdes_mux(int type, int need_reset) { diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c index db94d9c1fa8..e1e83137f4d 100644 --- a/board/nxp/ls1028a/ls1028a.c +++ b/board/nxp/ls1028a/ls1028a.c @@ -26,7 +26,9 @@ #include <fdtdec.h> #include <miiphy.h> #include "../common/qixis.h" +#ifdef CONFIG_FSL_ENETC #include "../drivers/net/fsl_enetc.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -103,11 +105,6 @@ int board_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { @@ -152,7 +149,7 @@ int board_early_init_f(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -205,10 +202,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls1028a/ls1028ardb.env b/board/nxp/ls1028a/ls1028ardb.env new file mode 100644 index 00000000000..dc1cb01e50a --- /dev/null +++ b/board/nxp/ls1028a/ls1028ardb.env @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +board=ls1028ardb +hwconfig=fsl_ddr:bank_intlv=auto +fdtfile=fsl-ls1028a-rdb.dtb +image=Image +extra_bootargs=iommu.passthrough=1 arm-smmu.disable_bypass=0 +othbootargs=video=1920x1080-32@60 cma=640M +ramdisk_addr=0x800000 +ramdisk_size=0x2000000 +bootm_size=0x10000000 +kernel_addr=0x01000000 +scriptaddr=0x80000000 +scripthdraddr=0x80080000 +fdtheader_addr_r=0x80100000 +kernelheader_addr_r=0x80200000 +load_addr=0xa0000000 +kernel_addr_r=0x81000000 +fdt_addr_r=0x90000000 +ramdisk_addr_r=0xa0000000 +kernel_start=0x1000000 +kernelheader_start=0x600000 +kernel_load=0xa0000000 +kernel_size=0x2800000 +kernelheader_size=0x40000 +kernel_addr_sd=0x8000 +kernel_size_sd=0x14000 +kernelhdr_addr_sd=0x3000 +kernelhdr_size_sd=0x20 +console=ttyS0,115200 +console_dbg=earlycon=uart8250,mmio,0x21c0500 +boot_script_hdr=hdr_ls1028ardb_bs.out +xspi_bootcmd=echo Trying load from FlexSPI flash ...;sf probe 0:0 && sf read $load_addr + $kernel_start $kernel_size ; env exists secureboot &&sf read $kernelheader_addr_r + $kernelheader_start $kernelheader_size && esbc_validate ${kernelheader_addr_r}; bootm + $load_addr#$board +xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;sf probe 0:0 && sf read + $load_addr 0x940000 0x30000 && hdp load $load_addr 0x2000 +sd_bootcmd=echo Trying load from SD ...;mmc dev 0;mmcinfo; mmc read $load_addr $kernel_addr_sd + $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd + $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$board +sd_hdploadcmd=echo Trying load HDP firmware from SD..;mmc dev 0;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 +emmc_bootcmd=echo Trying load from EMMC ..;mmc dev 1;mmcinfo; mmc read $load_addr + $kernel_addr_sd $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r + $kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm + $load_addr#$board +emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;mmc dev 1;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 diff --git a/board/nxp/ls1043aqds/Makefile b/board/nxp/ls1043aqds/Makefile index ff830788fd7..98ad49f6f0c 100644 --- a/board/nxp/ls1043aqds/Makefile +++ b/board/nxp/ls1043aqds/Makefile @@ -5,7 +5,4 @@ # obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif obj-y += ls1043aqds.o diff --git a/board/nxp/ls1043aqds/eth.c b/board/nxp/ls1043aqds/eth.c deleted file mode 100644 index 5a8ca27b327..00000000000 --- a/board/nxp/ls1043aqds/eth.c +++ /dev/null @@ -1,501 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - */ - -#include <config.h> -#include <log.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fdt_support.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <fsl_dtsec.h> -#include <linux/libfdt.h> -#include <malloc.h> -#include <asm/arch/fsl_serdes.h> - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1043aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT3 4 -#define EMI1_SLOT4 5 -#define EMI2 6 - -static const char * const mdio_names[] = { - "LS1043AQDS_MDIO_RGMII1", - "LS1043AQDS_MDIO_RGMII2", - "LS1043AQDS_MDIO_SLOT1", - "LS1043AQDS_MDIO_SLOT2", - "LS1043AQDS_MDIO_SLOT3", - "LS1043AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 2, 3, 4}; -#endif - -static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI2) - return NULL; - - name = ls1043aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1043aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1043aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1043aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1043aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1043aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1043aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1043aqds_mdio_read; - bus->write = ls1043aqds_mdio_write; - bus->reset = ls1043aqds_mdio_reset; - strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - if (port == FM1_DTSEC9) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s1-p1"); - } else if (port == FM1_DTSEC2) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s2-p1"); - } else if (port == FM1_DTSEC5) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s3-p1"); - } else if (port == FM1_DTSEC6) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s4-p1"); - } - } else if (fm_info_get_enet_if(port) == - PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (mdio_mux[port]) { - case EMI1_SLOT1: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p4"); - break; - default: - break; - } - break; - case EMI1_SLOT2: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p4"); - break; - default: - break; - } - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - port == FM1_10GEC1) { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1-slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_XGMII: - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x2555: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - break; - case 0x4555: - case 0x4558: - /* QSGMII on lane A, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S1); - break; - case 0x1355: - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x2355: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x3335: - /* SGMII on lane C, MAC 5 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3355: - case 0x3358: - /* SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3555: - case 0x3558: - /* SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x1455: - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2455: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2255: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* 2.5G SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, 2); - break; - case 0x3333: - /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC9, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, - SGMII_CARD_PORT1_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_2500BASEX: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_2500_FM1_DTSEC1 + idx); - } else { - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - } - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c index f043599fbb8..dba93add698 100644 --- a/board/nxp/ls1043aqds/ls1043aqds.c +++ b/board/nxp/ls1043aqds/ls1043aqds.c @@ -542,18 +542,14 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - fdt_fixup_icid(blob); reg = QIXIS_READ(brdcfg[0]); diff --git a/board/nxp/ls1043ardb/Makefile b/board/nxp/ls1043ardb/Makefile index 95745bf3a9c..13e0411c1ba 100644 --- a/board/nxp/ls1043ardb/Makefile +++ b/board/nxp/ls1043ardb/Makefile @@ -5,6 +5,5 @@ obj-y += ddr.o obj-y += ls1043ardb.o ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_NET) += eth.o obj-y += cpld.o endif diff --git a/board/nxp/ls1043ardb/eth.c b/board/nxp/ls1043ardb/eth.c deleted file mode 100644 index cacc49c0584..00000000000 --- a/board/nxp/ls1043ardb/eth.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ -#include <config.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x1455: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/ls1043ardb/ls1043ardb.c b/board/nxp/ls1043ardb/ls1043ardb.c index bba041065b5..678c529cf55 100644 --- a/board/nxp/ls1043ardb/ls1043ardb.c +++ b/board/nxp/ls1043ardb/ls1043ardb.c @@ -305,10 +305,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046afrwy/Makefile b/board/nxp/ls1046afrwy/Makefile index c70f5cda797..8594658d2fb 100644 --- a/board/nxp/ls1046afrwy/Makefile +++ b/board/nxp/ls1046afrwy/Makefile @@ -4,4 +4,4 @@ obj-y += ddr.o obj-y += ls1046afrwy.o -obj-$(CONFIG_NET) += eth.o +obj-$(CONFIG_NET_LEGACY) += eth.o diff --git a/board/nxp/ls1046afrwy/eth.c b/board/nxp/ls1046afrwy/eth.c index 8efc7f68424..d76841c6ab4 100644 --- a/board/nxp/ls1046afrwy/eth.c +++ b/board/nxp/ls1046afrwy/eth.c @@ -4,64 +4,7 @@ */ #include <config.h> #include <fdt_support.h> -#include <net.h> #include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info dtsec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x3040: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(FM1_DTSEC6, dev); - fm_info_set_mdio(FM1_DTSEC5, dev); - fm_info_set_mdio(FM1_DTSEC10, dev); - fm_info_set_mdio(FM1_DTSEC1, dev); - - fm_disable_port(FM1_DTSEC9); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} #ifdef CONFIG_FMAN_ENET int fdt_update_ethernet_dt(void *blob) diff --git a/board/nxp/ls1046afrwy/ls1046afrwy.c b/board/nxp/ls1046afrwy/ls1046afrwy.c index 8889c24f1f0..6c35c0a4347 100644 --- a/board/nxp/ls1046afrwy/ls1046afrwy.c +++ b/board/nxp/ls1046afrwy/ls1046afrwy.c @@ -198,10 +198,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1046aqds/Makefile b/board/nxp/ls1046aqds/Makefile index 365247d92bc..8292726b0e4 100644 --- a/board/nxp/ls1046aqds/Makefile +++ b/board/nxp/ls1046aqds/Makefile @@ -5,7 +5,4 @@ # obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif obj-y += ls1046aqds.o diff --git a/board/nxp/ls1046aqds/eth.c b/board/nxp/ls1046aqds/eth.c deleted file mode 100644 index cd3500c2e96..00000000000 --- a/board/nxp/ls1046aqds/eth.c +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018-2020 NXP - */ - -#include <config.h> -#include <log.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fdt_support.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <fsl_dtsec.h> -#include <malloc.h> -#include <asm/arch/fsl_serdes.h> - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1046aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT4 4 - -static const char * const mdio_names[] = { - "LS1046AQDS_MDIO_RGMII1", - "LS1046AQDS_MDIO_RGMII2", - "LS1046AQDS_MDIO_SLOT1", - "LS1046AQDS_MDIO_SLOT2", - "LS1046AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes 1 & 2 lanes to default slot. */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; -#endif - -static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI1_SLOT4) - return NULL; - - name = ls1046aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1046aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1046aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1046aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1046aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1046aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1046aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1046aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1046aqds_mdio_read; - bus->write = ls1046aqds_mdio_write; - bus->reset = ls1046aqds_mdio_reset; - sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - const char *phyconn; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - switch (port) { - case FM1_DTSEC9: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); - break; - default: - break; - } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII on QDS */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - (port == FM1_10GEC1 || port == FM1_10GEC2)) { - phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", port); - } else { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, - sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "xgmii"); - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1, srds_s2; - u8 brdcfg12; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - srds_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; - srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x3333: - /* SGMII on slot 1, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - case 0x1333: - case 0x2333: - /* SGMII on slot 1, MAC 10 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1133: - case 0x2233: - /* SGMII on slot 1, MAC 5/6 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x1040: - case 0x2040: - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC10, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x3363: - /* SGMII on slot 1, MAC 9/10 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1163: - case 0x2263: - case 0x2223: - /* SGMII on slot 1, MAC 6 */ - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", - srds_s1); - break; - } - - if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) - /* SGMII on slot 4, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - if (i == FM1_DTSEC5) { - /* route lane 2 to slot1 so to have - * one sgmii riser card supports - * MAC5 and MAC6. - */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], - brdcfg12 | 0x80); - } - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else { - /* clear the bit 7 to route lane B on slot2. */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); - - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - lane_to_slot[lane] = 2; - } - - if (i == FM1_DTSEC2) - lane = 5; - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c index 7df12550868..ddd9993986f 100644 --- a/board/nxp/ls1046aqds/ls1046aqds.c +++ b/board/nxp/ls1046aqds/ls1046aqds.c @@ -426,18 +426,14 @@ int ft_board_setup(void *blob, struct bd_info *bd) u8 reg; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - fdt_fixup_icid(blob); reg = QIXIS_READ(brdcfg[0]); diff --git a/board/nxp/ls1046ardb/Makefile b/board/nxp/ls1046ardb/Makefile index 9e5d24f53c8..355ccf59257 100644 --- a/board/nxp/ls1046ardb/Makefile +++ b/board/nxp/ls1046ardb/Makefile @@ -5,6 +5,6 @@ obj-y += ddr.o obj-y += ls1046ardb.o ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_NET) += eth.o +obj-$(CONFIG_NET_LEGACY) += eth.o obj-y += cpld.o endif diff --git a/board/nxp/ls1046ardb/eth.c b/board/nxp/ls1046ardb/eth.c index fee8e0e21d4..ce9b7b81e3d 100644 --- a/board/nxp/ls1046ardb/eth.c +++ b/board/nxp/ls1046ardb/eth.c @@ -4,78 +4,7 @@ */ #include <config.h> #include <fdt_support.h> -#include <net.h> #include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* Set the two on-board SGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); - - /* Set the on-board AQ PHY address */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - - switch (srds_s1) { - case 0x1133: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} #ifdef CONFIG_FMAN_ENET int fdt_update_ethernet_dt(void *blob) diff --git a/board/nxp/ls1046ardb/ls1046ardb.c b/board/nxp/ls1046ardb/ls1046ardb.c index 83b280f7646..6677e271029 100644 --- a/board/nxp/ls1046ardb/ls1046ardb.c +++ b/board/nxp/ls1046ardb/ls1046ardb.c @@ -171,10 +171,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 size[CONFIG_NR_DRAM_BANKS]; /* fixup DT for the two DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c index 51ec055be63..8ea76fe3760 100644 --- a/board/nxp/ls1088a/ls1088a.c +++ b/board/nxp/ls1088a/ls1088a.c @@ -7,6 +7,7 @@ #include <display_options.h> #include <env.h> #include <i2c.h> +#include <pmbus.h> #include <init.h> #include <log.h> #include <malloc.h> @@ -667,13 +668,13 @@ int get_serdes_volt(void) /* Select the PAGE 0 using PMBus commands PAGE for VDD */ #if !CONFIG_IS_ENABLED(DM_I2C) ret = i2c_write(I2C_SVDD_MONITOR_ADDR, - PMBUS_CMD_PAGE, 1, &chan, 1); + PMBUS_PAGE, 1, &chan, 1); #else struct udevice *dev; ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); if (!ret) - ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, + ret = dm_i2c_write(dev, PMBUS_PAGE, &chan, 1); #endif @@ -685,9 +686,9 @@ int get_serdes_volt(void) /* Read the output voltage using PMBus command READ_VOUT */ #if !CONFIG_IS_ENABLED(DM_I2C) ret = i2c_read(I2C_SVDD_MONITOR_ADDR, - PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); + PMBUS_READ_VOUT, 1, (void *)&vcode, 2); #else - dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); + dm_i2c_read(dev, PMBUS_READ_VOUT, (void *)&vcode, 2); #endif if (ret) { printf("VID: failed to read the voltage\n"); @@ -700,7 +701,7 @@ int get_serdes_volt(void) int set_serdes_volt(int svdd) { int ret, vdd_last; - u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, + u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_VOUT_COMMAND, svdd & 0xFF, (svdd & 0xFF00) >> 8}; /* Write the desired voltage code to the SVDD regulator */ @@ -830,7 +831,7 @@ int board_init(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -959,8 +960,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM @@ -974,7 +975,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/ls2080aqds/ls2080aqds.c b/board/nxp/ls2080aqds/ls2080aqds.c index aba0560181a..325dc817aaf 100644 --- a/board/nxp/ls2080aqds/ls2080aqds.c +++ b/board/nxp/ls2080aqds/ls2080aqds.c @@ -253,12 +253,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -302,10 +302,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ diff --git a/board/nxp/ls2080ardb/eth_ls2080rdb.c b/board/nxp/ls2080ardb/eth_ls2080rdb.c index 7d5beb32417..6a8859fd0c5 100644 --- a/board/nxp/ls2080ardb/eth_ls2080rdb.c +++ b/board/nxp/ls2080ardb/eth_ls2080rdb.c @@ -9,25 +9,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ - -#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD) - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c index 6f824f57c47..9dec818280b 100644 --- a/board/nxp/ls2080ardb/ls2080ardb.c +++ b/board/nxp/ls2080ardb/ls2080ardb.c @@ -359,12 +359,12 @@ int misc_init_r(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->dram[2].size) { puts("\nDP-DDR "); - print_size(gd->bd->bi_dram[2].size, ""); + print_size(gd->dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); } #endif @@ -487,10 +487,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) size = calloc(total_memory_banks, sizeof(u64)); /* fixup DT for the two GPP DDR banks */ - base[0] = gd->bd->bi_dram[0].start; - size[0] = gd->bd->bi_dram[0].size; - base[1] = gd->bd->bi_dram[1].start; - size[1] = gd->bd->bi_dram[1].size; + base[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; + base[1] = gd->dram[1].start; + size[1] = gd->dram[1].size; #ifdef CONFIG_RESV_RAM /* reduce size if reserved memory is within this bank */ @@ -503,7 +503,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/lx2160a/eth_lx2160aqds.c b/board/nxp/lx2160a/eth_lx2160aqds.c index 9939bb6f89e..4c16f565b69 100644 --- a/board/nxp/lx2160a/eth_lx2160aqds.c +++ b/board/nxp/lx2160a/eth_lx2160aqds.c @@ -11,24 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/eth_lx2160ardb.c b/board/nxp/lx2160a/eth_lx2160ardb.c index 90e7c9100e1..31bbac6310e 100644 --- a/board/nxp/lx2160a/eth_lx2160ardb.c +++ b/board/nxp/lx2160a/eth_lx2160ardb.c @@ -11,23 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - return pci_eth_init(bis); -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/eth_lx2162aqds.c b/board/nxp/lx2160a/eth_lx2162aqds.c index 805aa705be9..81b81d47978 100644 --- a/board/nxp/lx2160a/eth_lx2162aqds.c +++ b/board/nxp/lx2160a/eth_lx2162aqds.c @@ -11,24 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c index 341f82ce724..10729dfaf24 100644 --- a/board/nxp/lx2160a/lx2160a.c +++ b/board/nxp/lx2160a/lx2160a.c @@ -242,13 +242,17 @@ int init_func_vid(void) return 0; } -#endif EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid); +#endif int checkboard(void) { - enum boot_src src = get_boot_src(); char buf[64]; + + cpu_name(buf); + +#if IS_ENABLED(CONFIG_FSL_QIXIS) + enum boot_src src = get_boot_src(); u8 sw; #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) int clock; @@ -258,7 +262,6 @@ int checkboard(void) "100 separate SSCG"}; #endif - cpu_name(buf); #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) printf("Board: %s-QDS, ", buf); #else @@ -325,7 +328,10 @@ int checkboard(void) clock = sw >> 4; printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); #endif -#endif +#endif /* LX2160ARDB-inside-QIXIS switch */ +#else /* !CONFIG_FSL_QIXIS */ + printf("Board: %s\n", buf); +#endif /* CONFIG_FSL_QIXIS */ return 0; } @@ -554,7 +560,7 @@ int board_init(void) out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); #endif -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) +#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) pci_init(); #endif return 0; @@ -567,7 +573,7 @@ void detail_board_ddr_info(void) puts("\nDDR "); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - ddr_size += gd->bd->bi_dram[i].size; + ddr_size += gd->dram[i].size; print_size(ddr_size, ""); print_ddr_info(0); } @@ -788,7 +794,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); +#if IS_ENABLED(CONFIG_FSL_MC_ENET) fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); +#endif if (mc_memory_base != 0) mc_memory_bank++; @@ -800,8 +808,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the three GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; } #ifdef CONFIG_RESV_RAM @@ -818,7 +826,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/m5253demo/m5253demo.c b/board/nxp/m5253demo/m5253demo.c index 50c5320b55c..7d4b60b283e 100644 --- a/board/nxp/m5253demo/m5253demo.c +++ b/board/nxp/m5253demo/m5253demo.c @@ -133,10 +133,3 @@ void ide_set_reset(int idereset) } } #endif /* CONFIG_IDE */ - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(struct bd_info *bis) -{ - return dm9000_initialize(bis); -} -#endif diff --git a/board/nxp/m53017evb/README b/board/nxp/m53017evb/README index 25831629266..c6dc020af37 100644 --- a/board/nxp/m53017evb/README +++ b/board/nxp/m53017evb/README @@ -90,10 +90,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset CFG_SYS_MBAR -- define MBAR offset diff --git a/board/nxp/m5373evb/README b/board/nxp/m5373evb/README index c7130b32251..7217886fdfa 100644 --- a/board/nxp/m5373evb/README +++ b/board/nxp/m5373evb/README @@ -89,10 +89,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset CFG_SYS_MBAR -- define MBAR offset diff --git a/board/nxp/mx6memcal/Kconfig b/board/nxp/mx6memcal/Kconfig index a6c39d5e4d1..03d8422242f 100644 --- a/board/nxp/mx6memcal/Kconfig +++ b/board/nxp/mx6memcal/Kconfig @@ -35,30 +35,30 @@ choice The choices below reflect the most commonly used options for your UART. - config UART2_EIM_D26_27 - bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)" - depends on SERIAL_CONSOLE_UART2 - help - Choose this configuration if you're using pads - EIM_D26 and D27 for a console on UART2. - This is typical for designs that are based on the - NXP SABRELite. +config UART2_EIM_D26_27 + bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)" + depends on SERIAL_CONSOLE_UART2 + help + Choose this configuration if you're using pads + EIM_D26 and D27 for a console on UART2. + This is typical for designs that are based on the + NXP SABRELite. - config UART1_CSI0_DAT10_11 - bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)" - depends on SERIAL_CONSOLE_UART1 - help - Choose this configuration if you're using pads - CSI0_DAT10 and DAT11 for a console on UART1 as - is done on the i.MX6 Wand board and i.MX6 SabreSD. +config UART1_CSI0_DAT10_11 + bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)" + depends on SERIAL_CONSOLE_UART1 + help + Choose this configuration if you're using pads + CSI0_DAT10 and DAT11 for a console on UART1 as + is done on the i.MX6 Wand board and i.MX6 SabreSD. - config UART1_UART1 - bool "UART1 on UART1 (i.MX6SL EVK, WaRP)" - depends on SERIAL_CONSOLE_UART1 - help - Choose this configuration if you're using pads - UART1_TXD/RXD for a console on UART1 as is done - on most i.MX6SL designs. +config UART1_UART1 + bool "UART1 on UART1 (i.MX6SL EVK, WaRP)" + depends on SERIAL_CONSOLE_UART1 + help + Choose this configuration if you're using pads + UART1_TXD/RXD for a console on UART1 as is done + on most i.MX6SL designs. endchoice @@ -215,12 +215,12 @@ config REFR range 0 7 default 7 help - This selects the number of refreshes (-1) during each period. - i.e.: - 0 == 1 refresh (tRFC) - 7 == 8 refreshes (tRFC*8) - See the description of MDREF[REFR] in the reference manual for - details. + This selects the number of refreshes (-1) during each period. + i.e.: + 0 == 1 refresh (tRFC) + 7 == 8 refreshes (tRFC*8) + See the description of MDREF[REFR] in the reference manual for + details. endmenu diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.c b/board/nxp/mx6sabreauto/mx6sabreauto.c index 8ca57e0b2ac..aef8bc0ad90 100644 --- a/board/nxp/mx6sabreauto/mx6sabreauto.c +++ b/board/nxp/mx6sabreauto/mx6sabreauto.c @@ -465,6 +465,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) } #endif +#ifndef CONFIG_XPL_BUILD int power_init_board(void) { struct udevice *dev; @@ -488,6 +489,7 @@ int power_init_board(void) return pfuze_mode_init(dev, APS_PFM); } +#endif #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.env b/board/nxp/mx6sabreauto/mx6sabreauto.env new file mode 100644 index 00000000000..31a16905ef5 --- /dev/null +++ b/board/nxp/mx6sabreauto/mx6sabreauto.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc3 + +#include <env/nxp/mx6sabre_common.env> diff --git a/board/nxp/mx6sabresd/mx6sabresd.c b/board/nxp/mx6sabresd/mx6sabresd.c index dff3a9c33bf..9404535104c 100644 --- a/board/nxp/mx6sabresd/mx6sabresd.c +++ b/board/nxp/mx6sabresd/mx6sabresd.c @@ -437,6 +437,7 @@ int board_init(void) return 0; } +#ifndef CONFIG_XPL_BUILD int power_init_board(void) { struct udevice *dev; @@ -468,6 +469,7 @@ int power_init_board(void) return 0; } +#endif #ifdef CONFIG_MXC_SPI int board_spi_cs_gpio(unsigned bus, unsigned cs) diff --git a/board/nxp/mx6sabresd/mx6sabresd.env b/board/nxp/mx6sabresd/mx6sabresd.env new file mode 100644 index 00000000000..3608e931665 --- /dev/null +++ b/board/nxp/mx6sabresd/mx6sabresd.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc0 + +#include <env/nxp/mx6sabre_common.env> diff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c index ac91da3f4f6..036deb464b5 100644 --- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c @@ -33,16 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ PAD_CTL_SRE_FAST) @@ -55,48 +45,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const fec2_pads[] = { - MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - - return enable_fec_anatop_clock(1, ENET_125MHZ); -} - -int board_eth_init(struct bd_info *bis) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); - setup_fec(); - - ret = fecmxc_initialize_multi(bis, 1, - CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC%d MXC: %s:failed\n", 1, __func__); - - return ret; -} - int board_phy_config(struct phy_device *phydev) { /* diff --git a/board/nxp/mx6sxsabresd/mx6sxsabresd.c b/board/nxp/mx6sxsabresd/mx6sxsabresd.c index e3353feec68..cab0892affc 100644 --- a/board/nxp/mx6sxsabresd/mx6sxsabresd.c +++ b/board/nxp/mx6sxsabresd/mx6sxsabresd.c @@ -40,16 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) @@ -71,84 +61,16 @@ static iomux_v3_cfg_t const uart1_pads[] = { static iomux_v3_cfg_t const wdog_b_pad = { MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; static iomux_v3_cfg_t const peri_3v3_pads[] = { MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static iomux_v3_cfg_t const phy_control_pads[] = { - /* 25MHz Ethernet PHY Clock */ - MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - - /* ENET PHY Power */ - MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), - - /* AR8031 PHY Reset */ - MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg, ret; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); - - ret = enable_fec_anatop_clock(0, ENET_125MHZ); - if (ret) - return ret; - - imx_iomux_v3_setup_multiple_pads(phy_control_pads, - ARRAY_SIZE(phy_control_pads)); - - /* Enable the ENET power, active low */ - gpio_request(IMX_GPIO_NR(2, 6), "enet_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); - - /* Reset AR8031 PHY */ - gpio_request(IMX_GPIO_NR(2, 7), "phy_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - mdelay(10); - gpio_set_value(IMX_GPIO_NR(2, 7), 1); - - reg = readl(&anatop->pll_enet); - reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; - writel(reg, &anatop->pll_enet); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - setup_fec(); - - return cpu_eth_init(bis); -} - int power_init_board(void) { struct udevice *dev; diff --git a/board/nxp/mx6ullevk/mx6ullevk.env b/board/nxp/mx6ullevk/mx6ullevk.env new file mode 100644 index 00000000000..0fce3aaaa4e --- /dev/null +++ b/board/nxp/mx6ullevk/mx6ullevk.env @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttymxc0 +initrd_high=0xffffffff +fdt_file=undefined +fdt_addr=0x83000000 +boot_fdt=try +ip_dyn=yes +videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdt_file = undefined; then + if test $board_name = ULZ-EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ulz-14x14-evk.dtb; + fi; + if test $board_name = EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ull-14x14-evk.dtb; + fi; + if test $fdt_file = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/board/nxp/mx7ulp_evk/mx7ulp_evk.env b/board/nxp/mx7ulp_evk/mx7ulp_evk.env new file mode 100644 index 00000000000..f5a384a61de --- /dev/null +++ b/board/nxp/mx7ulp_evk/mx7ulp_evk.env @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttyLP0 +initrd_high=0xffffffff +fdt_file=imx7ulp-evk.dtb +fdt_addr=0x63000000 +boot_fdt=try +earlycon=lpuart32,0x402D0010 +ip_dyn=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk0p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + usb start; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/board/nxp/p2041rdb/Makefile b/board/nxp/p2041rdb/Makefile index ebd0982b5db..5512458832d 100644 --- a/board/nxp/p2041rdb/Makefile +++ b/board/nxp/p2041rdb/Makefile @@ -7,4 +7,3 @@ obj-y += p2041rdb.o obj-y += cpld.o obj-y += ddr.o -obj-y += eth.o diff --git a/board/nxp/p2041rdb/README b/board/nxp/p2041rdb/README deleted file mode 100644 index ae770277372..00000000000 --- a/board/nxp/p2041rdb/README +++ /dev/null @@ -1,138 +0,0 @@ -Overview -========= -The P2041 Processor combines four Power Architecture processor cores -with high-performance datapath acceleration architecture(DPAA), CoreNet -fabric infrastructure, as well as network and peripheral bus interfaces -required for networking, telecom/datacom, wireless infrastructure, and -military/aerospace applications. - -P2041RDB board is a quad core platform supporting the P2041 processor -of QorIQ DPAA series. - -Boot from NOR flash -=================== -1. Build image - make P2041RDB_config - make all - -2. Program image - => tftp 1000000 u-boot.bin - => protect off all - => erase eff40000 efffffff - => cp.b 1000000 eff40000 c0000 - -3. Program RCW - => tftp 1000000 rcw.bin - => protect off all - => erase e8000000 e801ffff - => cp.b 1000000 e8000000 50 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => protect off all - => erase eff00000 eff3ffff - => cp.b 1000000 eff00000 2000 - -5. Change DIP-switch - SW1[1-5] = 10110 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SDCard -=================== -1. Build image - make P2041RDB_SDCARD_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SDCard which contains RCW and U-Boot image. - -3. Program the PBL image to SDCard - => tftp 1000000 pbl_sd.bin - => mmcinfo - => mmc write 1000000 8 672 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => mmc write 1000000 690 10 - -5. Change DIP-switch - SW1[1-5] = 01100 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SPI flash -=================== -1. Build image - make P2041RDB_SPIFLASH_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SPI flash which contains RCW and U-Boot image. - -3. Program the PBL image to SPI flash - => tftp 1000000 pbl_spi.bin - => spi probe 0 - => sf erase 0 100000 - => sf write 1000000 0 $filesize - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => sf erase 110000 10000 - => sf write 1000000 110000 $filesize - -5. Change DIP-switch - SW1[1-5] = 10100 - Note: 1 stands for 'on', 0 stands for 'off' - -Device tree support and how to enable it for different configs --------------------------------------------------------------- -Device tree support is available for p2041rdb for below mentioned boot, -1. NOR Boot -2. NAND Boot -3. SD Boot -4. SPIFLASH Boot - -To enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) -2. CONFIG_OF_CONTROL -3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CFG_RESET_VECTOR_ADDRESS - 0xffc - -CPLD command -============ -The CPLD is used to control the power sequence and some serdes lane -mux function. - -cpld reset - hard reset to default bank -cpld reset altbank - reset to alternate bank -cpld lane_mux <lane> <mux_value> - set multiplexed lane pin - lane 6: 0 -> slot1 (Default) - 1 -> SGMII - lane a: 0 -> slot2 (Default) - 1 -> AURORA - lane c: 0 -> slot2 (Default) - 1 -> SATA0 - lane d: 0 -> slot2 (Default) - 1 -> SATA1 - -Using the Device Tree Source File -================================= -To create the DTB (Device Tree Binary) image file, use a command -similar to this: - dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb - -Or use the following command: - {linux-2.6}/make p2041rdb.dtb ARCH=powerpc - -then the dtb file will be generated under the following directory: - {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb - -Booting Linux -============= -Place a linux uImage in the TFTP disk area. - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp 3000000 p2041rdb.dtb - bootm 1000000 2000000 3000000 diff --git a/board/nxp/p2041rdb/README.rst b/board/nxp/p2041rdb/README.rst new file mode 100644 index 00000000000..8b8214adc57 --- /dev/null +++ b/board/nxp/p2041rdb/README.rst @@ -0,0 +1,147 @@ +.. SPDX-License-Identifier: GPL-2.0 + +P2041-RDB Board Overview +======================== + +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== + +1. Build image:: + + make P2041RDB_config + make all + +2. Program image:: + + => tftp 1000000 u-boot.bin + => protect off all + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 + +3. Program RCW:: + + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => protect off all + => erase eff00000 eff3ffff + => cp.b 1000000 eff00000 2000 + +5. Change DIP-switch to SW1[1-5] = 10110. Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +================ + +1. Build image:: + + make P2041RDB_SDCARD_config + make all + +2. Program the PBL image to SDCard:: + + => tftp 1000000 u-boot.pbl + => mmc info + => mmc write 1000000 8 672 + +3. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => mmc write 1000000 690 10 + +4. Change DIP-switch to SW1[1-5] = 01100. Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== + +1. Build image:: + + make P2041RDB_SPIFLASH_config + make all + +2. Program the PBL image to SPI flash:: + + => tftp 1000000 u-boot.pbl + => sf probe 0 + => sf update $fileaddr 0 $filesize + +3. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => sf update $fileaddr 110000 $filesize + +4. Change DIP-switch SW1[1-5] = 10100. Note: 1 stands for 'on', 0 stands for 'off' + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- + +Device tree support is available for p2041rdb for below mentioned boot, + +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, + +1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CFG_RESET_VECTOR_ADDRESS - 0xffc + +CPLD command +============ + +The CPLD is used to control the power sequence and some serdes lane +mux function:: + + cpld reset - hard reset to default bank + cpld reset altbank - reset to alternate bank + cpld lane_mux <lane> <mux_value> - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this:: + + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command:: + + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory:: + + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= + +Place a linux uImage in the TFTP disk area:: + + => tftp 1000000 uImage + => tftp 2000000 rootfs.ext2.gz.uboot + => tftp 3000000 p2041rdb.dtb + => bootm 1000000 2000000 3000000 diff --git a/board/nxp/p2041rdb/eth.c b/board/nxp/p2041rdb/eth.c deleted file mode 100644 index 65850866777..00000000000 --- a/board/nxp/p2041rdb/eth.c +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Author: Mingkai Hu <[email protected]> - */ - -/* - * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs - * are provided by the three on-board PHY or by the standard Freescale - * four-port SGMII riser card. We need to change the phy-handle in the - * kernel dts file to point to the correct PHY according to serdes mux - * and serdes protocol selection. - */ - -#include <config.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fsl_dtsec.h> - -#include "cpld.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0 -}; - -static int riser_phy_addr[] = { - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, -}; - -/* - * Initialize the lane_to_slot[] array. - * - * On the P2040RDB board the mapping is controlled by CPLD register. - */ -static void initialize_lane_to_slot(void) -{ - u8 mux = CPLD_READ(serdes_mux); - - lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; - lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; - lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; - lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - phy_interface_t intf = fm_info_get_enet_if(port); - char phy[16]; - int lane; - u8 slot; - - switch (intf) { - /* The RGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); - fdt_set_phy_handle(fdt, compat, addr, phy); - break; - /* The SGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); - if (lane < 0) - return; - slot = lane_to_slot[lane]; - if (slot) { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } else { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - case PHY_INTERFACE_MODE_XGMII: - /* XAUI */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - /* The XAUI PHY is identified by the slot */ - sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - default: - break; - } -} -#endif /* #ifdef CONFIG_FMAN_ENET */ - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* - * Program the three on-board SGMII PHY addresses. If the SGMII Riser - * card used, we'll override the PHY address later. For any DTSEC that - * is RGMII, we'll also override its PHY address later. We assume that - * DTSEC4 and DTSEC5 are used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(i, riser_phy_addr[i]); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ - fm_info_set_phy_address(i, i == FM1_DTSEC5 ? - CFG_SYS_FM1_DTSEC5_PHY_ADDR : - CFG_SYS_FM1_DTSEC4_PHY_ADDR); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - break; - } - - fm_info_set_mdio(i, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(FM1_10GEC1, - CFG_SYS_FM1_10GEC1_PHY_ADDR); - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg new file mode 100644 index 00000000000..f22f3335e73 --- /dev/null +++ b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P2041RDB. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +12600000 00000000 241C0000 00000000 +649FA0C1 C3C02000 68000000 40000000 +00000000 00000000 00000000 D0030F07 +00000000 00000000 00000000 00000000 diff --git a/board/nxp/p2041rdb/rcw_p2041rdb.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg index 8df19dd3fe4..8df19dd3fe4 100644 --- a/board/nxp/p2041rdb/rcw_p2041rdb.cfg +++ b/board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg diff --git a/board/nxp/t102xrdb/Makefile b/board/nxp/t102xrdb/Makefile index b0f27c47191..2a360227418 100644 --- a/board/nxp/t102xrdb/Makefile +++ b/board/nxp/t102xrdb/Makefile @@ -9,7 +9,6 @@ obj-y += spl.o else obj-y += t102xrdb.o obj-$(CONFIG_TARGET_T1024RDB) += cpld.o -obj-y += eth_t102xrdb.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/nxp/t102xrdb/eth_t102xrdb.c b/board/nxp/t102xrdb/eth_t102xrdb.c deleted file mode 100644 index 7185a0abd52..00000000000 --- a/board/nxp/t102xrdb/eth_t102xrdb.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Shengzhou Liu <[email protected]> - */ - -#include <config.h> -#include <command.h> -#include <fdt_support.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fsl_dtsec.h> -#include <asm/fsl_serdes.h> -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); - - switch (srds_s1) { -#ifdef CONFIG_TARGET_T1024RDB - case 0x95: - /* set the on-board RGMII2 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); - - /* set 10GBase-R with Aquantia AQR105 PHY */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - break; -#endif - case 0x6a: - case 0x6b: - case 0x77: - case 0x135: - /* set the on-board 2.5G SGMII AQR105 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); -#ifdef CONFIG_TARGET_T1023RDB - /* set the on-board 1G SGMII RTL8211F PHY */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); -#endif - break; - default: - printf("SerDes protocol 0x%x is not supported on T102xRDB\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_SGMII: -#if defined(CONFIG_TARGET_T1023RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); -#elif defined(CONFIG_TARGET_T1024RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); -#endif - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_2500BASEX: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ -#if defined(CONFIG_TARGET_T1024RDB) - if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || - (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && - (port == FM1_DTSEC3)) { - fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); - } -#endif -} - -void fdt_fixup_board_enet(void *fdt) -{ -} diff --git a/board/nxp/t102xrdb/t102xrdb.c b/board/nxp/t102xrdb/t102xrdb.c index 0a29e27b42c..02223497dd3 100644 --- a/board/nxp/t102xrdb/t102xrdb.c +++ b/board/nxp/t102xrdb/t102xrdb.c @@ -207,7 +207,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif #ifdef CONFIG_TARGET_T1023RDB diff --git a/board/nxp/t102xrdb/t102xrdb.h b/board/nxp/t102xrdb/t102xrdb.h index 33df0f24df8..71e2cfea22e 100644 --- a/board/nxp/t102xrdb/t102xrdb.h +++ b/board/nxp/t102xrdb/t102xrdb.h @@ -6,7 +6,6 @@ #ifndef __T1024_RDB_H__ #define __T1024_RDB_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #ifdef CONFIG_TARGET_T1023RDB static u32 t1023rdb_ctrl(u32 ctrl_type); diff --git a/board/nxp/t104xrdb/Makefile b/board/nxp/t104xrdb/Makefile index 9bca1a1fbcc..cee574aabb9 100644 --- a/board/nxp/t104xrdb/Makefile +++ b/board/nxp/t104xrdb/Makefile @@ -7,7 +7,6 @@ obj-y += spl.o else obj-y += t104xrdb.o obj-y += cpld.o -obj-y += eth.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/nxp/t104xrdb/eth.c b/board/nxp/t104xrdb/eth.c deleted file mode 100644 index c35ec368a45..00000000000 --- a/board/nxp/t104xrdb/eth.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <config.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <asm/immap_85xx.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fsl_dtsec.h> -#include <vsc9953.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info memac_mdio_info; - unsigned int i; - int phy_addr = 0; - - printf("Initializing Fman\n"); - - memac_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fm_memac_mdio_init(bis, &memac_mdio_info); - - /* - * Program on board RGMII, SGMII PHY addresses. - */ - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_TARGET_T1042D4RDB - case PHY_INTERFACE_MODE_SGMII: - /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 - * & DTSEC3 - */ - if (FM1_DTSEC1 == i) - phy_addr = CFG_SYS_SGMII1_PHY_ADDR; - if (FM1_DTSEC2 == i) - phy_addr = CFG_SYS_SGMII2_PHY_ADDR; - if (FM1_DTSEC3 == i) - phy_addr = CFG_SYS_SGMII3_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; -#endif - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (FM1_DTSEC4 == i) - phy_addr = CFG_SYS_RGMII1_PHY_ADDR; - if (FM1_DTSEC5 == i) - phy_addr = CFG_SYS_RGMII2_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; - case PHY_INTERFACE_MODE_QSGMII: - fm_info_set_phy_address(i, 0); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII || - fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA) - fm_info_set_mdio(i, NULL); - else - fm_info_set_mdio(i, - miiphy_get_dev_by_name( - DEFAULT_FM_MDIO_NAME)); - } - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/t104xrdb/t104xrdb.h b/board/nxp/t104xrdb/t104xrdb.h index 678724c7e2b..5825e69cdb4 100644 --- a/board/nxp/t104xrdb/t104xrdb.h +++ b/board/nxp/t104xrdb/t104xrdb.h @@ -6,7 +6,6 @@ #ifndef __T104x_RDB_H__ #define __T104x_RDB_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/nxp/t208xqds/Makefile b/board/nxp/t208xqds/Makefile index eb99d921b4a..4bfd2b50d8f 100644 --- a/board/nxp/t208xqds/Makefile +++ b/board/nxp/t208xqds/Makefile @@ -7,7 +7,7 @@ ifdef CONFIG_XPL_BUILD obj-y += spl.o else -obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o +obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o endif obj-y += ddr.o diff --git a/board/nxp/t208xqds/eth_t208xqds.c b/board/nxp/t208xqds/eth_t208xqds.c deleted file mode 100644 index b55078c8fe1..00000000000 --- a/board/nxp/t208xqds/eth_t208xqds.c +++ /dev/null @@ -1,723 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - * - * Shengzhou Liu <[email protected]> - */ - -#include <config.h> -#include <command.h> -#include <fdt_support.h> -#include <log.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fsl_dtsec.h> -#include <asm/fsl_serdes.h> -#include <hwconfig.h> -#include "../common/qixis.h" -#include "../common/fman.h" -#include "t208xqds_qixis.h" -#include <linux/libfdt.h> - -#define EMI_NONE 0xFFFFFFFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#if defined(CONFIG_TARGET_T2080QDS) -#define EMI1_SLOT2 6 -#define EMI1_SLOT3 3 -#define EMI1_SLOT4 4 -#define EMI1_SLOT5 5 -#define EMI2 7 -#endif - -#define PCCR1_SGMIIA_KX_MASK 0x00008000 -#define PCCR1_SGMIIB_KX_MASK 0x00004000 -#define PCCR1_SGMIIC_KX_MASK 0x00002000 -#define PCCR1_SGMIID_KX_MASK 0x00001000 -#define PCCR1_SGMIIE_KX_MASK 0x00000800 -#define PCCR1_SGMIIF_KX_MASK 0x00000400 -#define PCCR1_SGMIIG_KX_MASK 0x00000200 -#define PCCR1_SGMIIH_KX_MASK 0x00000100 - -static int mdio_mux[NUM_FM_PORTS]; - -static const char * const mdio_names[] = { -#if defined(CONFIG_TARGET_T2080QDS) - "T2080QDS_MDIO_RGMII1", - "T2080QDS_MDIO_RGMII2", - "T2080QDS_MDIO_SLOT1", - "T2080QDS_MDIO_SLOT3", - "T2080QDS_MDIO_SLOT4", - "T2080QDS_MDIO_SLOT5", - "T2080QDS_MDIO_SLOT2", - "T2080QDS_MDIO_10GC", -#endif -}; - -/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ -#if defined(CONFIG_TARGET_T2080QDS) -static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; -#endif - -static const char *t208xqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name = t208xqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -struct t208xqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void t208xqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - if (muxval < 8) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int t208xqds_mdio_reset(struct mii_dev *bus) -{ - struct t208xqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int t208xqds_mdio_init(char *realbusname, u8 muxval) -{ - struct t208xqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate t208xqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate t208xqds private data\n"); - free(bus); - return -1; - } - - bus->read = t208xqds_mdio_read; - bus->write = t208xqds_mdio_write; - bus->reset = t208xqds_mdio_reset; - strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - int phy; - char alias[20]; - char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; - char buf[32] = "serdes-1,"; - struct fixed_link f_link; - int media_type = 0; - const char *phyconn; - int off; - - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_TARGET_T2080QDS - serdes_corenet_t *srds_regs = - (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; - u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); -#endif - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - phy = fm_info_get_phy_address(port); - switch (port) { -#if defined(CONFIG_TARGET_T2080QDS) - case FM1_DTSEC1: - if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx1"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIH_KX_MASK); - break; - } - case FM1_DTSEC2: - if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx2"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIG_KX_MASK); - break; - } - case FM1_DTSEC9: - if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx9"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIE_KX_MASK); - break; - } - case FM1_DTSEC10: - if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx10"); - fdt_status_okay_by_alias(fdt, - "1gkx_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIF_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } else if (mdio_mux[port] == EMI1_SLOT3) { - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - } - break; - case FM1_DTSEC5: - if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx5"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); - strcat(buf, "lane-g,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIC_KX_MASK); - break; - } - case FM1_DTSEC6: - if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx6"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); - strcat(buf, "lane-h,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIID_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT1) { - sprintf(alias, "phy_sgmii_s1_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot1"); - } else if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } - break; -#endif - default: - break; - } - if (media_type) { - /* set property for 1000BASE-KX in dtb */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, "lane-instance", buf); - } - - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { - switch (srds_s1) { - case 0x66: /* 10GBase-R interface */ - case 0x6b: - case 0x6c: - case 0x6d: - case 0x71: - /* - * Check hwconfig to see what is the media type, there - * are two types, fiber or copper, fix the dtb - * accordingly. - */ - switch (port) { - case FM1_10GEC1: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { - /* it's MAC9 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi9"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC2: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { - /* it's MAC10 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi10"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC3: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { - /* it's MAC1 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi1"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC4: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { - /* it's MAC2 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi2"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - default: - return; - } - - if (!media_type) { - phyconn = fdt_getprop(fdt, offset, - "phy-connection-type", - NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", - port); - } else { - /* fixed-link for 10GBase-R fiber cable */ - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", - &f_link, sizeof(f_link)); - } - } else { - /* set property for copper cable */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, - "lane-instance", buf); - } - break; - default: - break; - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -/* - * This function reads RCW to check if Serdes1{A:H} is configured - * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly - */ -static void initialize_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - switch (srds_s1) { -#if defined(CONFIG_TARGET_T2080QDS) - case 0x51: - case 0x5f: - case 0x65: - case 0x6b: - case 0x71: - lane_to_slot[5] = 2; - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - case 0xd3: - case 0xd9: - case 0xcb: - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xda: - lane_to_slot[4] = 3; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; -#endif - default: - break; - } -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 rcwsr13 = in_be32(&gur->rcwsr[13]); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - initialize_lane_to_slot(); - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); -#if defined(CONFIG_TARGET_T2080QDS) - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); -#endif - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == - FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - else - fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x1b: - case 0x1c: - case 0x95: - case 0xa2: - case 0x94: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x50: - case 0x51: - case 0x5e: - case 0x5f: - case 0x64: - case 0x65: - /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x66: - case 0x67: - /* - * 10GBase-R does not need a PHY to work, but to avoid U-Boot - * use default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to 10GBase-R - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the 10GBase-R MAC, which will cause - * error. - */ - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - break; - case 0x6a: - case 0x6b: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0x6c: - case 0x6d: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x70: - case 0x71: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa4: - case 0x96: - case 0x8a: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; -#if defined(CONFIG_TARGET_T2080QDS) - case 0xd9: - case 0xd3: - case 0xcb: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; -#endif - case 0xf2: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4 || FM1_DTSEC10) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - idx = i - FM1_10GEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - if (srds_s1 == 0x51) { - lane = serdes_get_first_lane(FSL_SRDS_1, - XAUI_FM1_MAC9 + idx); - } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { - lane = serdes_get_first_lane(FSL_SRDS_1, - HIGIG_FM1_MAC9 + idx); - } else { - if (i == FM1_10GEC1 || i == FM1_10GEC2) - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC9 + idx); - else - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC1 + idx); - } - - if (lane < 0) - break; - mdio_mux[i] = EMI2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - - if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || - (srds_s1 == 0x6a) || (srds_s1 == 0x70) || - (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || - (srds_s1 == 0x71)) { - /* As 10GBase-R is in cage intead of a slot, so - * ensure doesn't disable the corresponding port - */ - break; - } - - slot = lane_to_slot[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/nxp/t208xqds/t208xqds.c b/board/nxp/t208xqds/t208xqds.c index 5e71da0e163..329cf59793f 100644 --- a/board/nxp/t208xqds/t208xqds.c +++ b/board/nxp/t208xqds/t208xqds.c @@ -419,7 +419,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif return 0; diff --git a/board/nxp/t208xqds/t208xqds.h b/board/nxp/t208xqds/t208xqds.h index 50ebb6f6f98..4086f8c010a 100644 --- a/board/nxp/t208xqds/t208xqds.h +++ b/board/nxp/t208xqds/t208xqds.h @@ -6,7 +6,6 @@ #ifndef __CORENET_DS_H__ #define __CORENET_DS_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/nxp/t208xrdb/eth_t208xrdb.c b/board/nxp/t208xrdb/eth_t208xrdb.c index 5223eccb280..c9e415bc446 100644 --- a/board/nxp/t208xrdb/eth_t208xrdb.c +++ b/board/nxp/t208xrdb/eth_t208xrdb.c @@ -93,8 +93,3 @@ void fdt_fixup_board_phy(void *fdt) printf("Unable to rename node ethernet-phy@1: %s\n", fdt_strerror(ret)); } - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} diff --git a/board/nxp/t208xrdb/t208xrdb.c b/board/nxp/t208xrdb/t208xrdb.c index d93edf007ad..d47ec91e7d0 100644 --- a/board/nxp/t208xrdb/t208xrdb.c +++ b/board/nxp/t208xrdb/t208xrdb.c @@ -160,7 +160,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_board_fman_ethernet(blob); - fdt_fixup_board_enet(blob); fdt_fixup_board_phy(blob); #endif diff --git a/board/nxp/t208xrdb/t208xrdb.h b/board/nxp/t208xrdb/t208xrdb.h index 26998898e82..e800270a0e2 100644 --- a/board/nxp/t208xrdb/t208xrdb.h +++ b/board/nxp/t208xrdb/t208xrdb.h @@ -10,7 +10,6 @@ #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000 -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); void fdt_fixup_board_fman_ethernet(void *blob); void fdt_fixup_board_phy(void *blob); diff --git a/board/nxp/t4rdb/Makefile b/board/nxp/t4rdb/Makefile index 8d94faaba1c..6d9b8df2fc1 100644 --- a/board/nxp/t4rdb/Makefile +++ b/board/nxp/t4rdb/Makefile @@ -9,7 +9,6 @@ obj-y += spl.o else obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o obj-y += cpld.o -obj-y += eth.o endif obj-y += ddr.o diff --git a/board/nxp/t4rdb/eth.c b/board/nxp/t4rdb/eth.c deleted file mode 100644 index e7646365d7d..00000000000 --- a/board/nxp/t4rdb/eth.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Chunhe Lan <[email protected]> - */ - -#include <config.h> -#include <command.h> -#include <fdt_support.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fsl_dtsec.h> -#include <asm/fsl_serdes.h> -#include <hwconfig.h> - -#include "../common/fman.h" -#include "t4rdb.h" - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { - /* SGMII */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); - fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); - } else { - puts("Invalid SerDes1 protocol for T4240RDB\n"); - } - - fm_disable_port(FM1_DTSEC5); - fm_disable_port(FM1_DTSEC6); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - -#if (CFG_SYS_NUM_FMAN == 2) - if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { - /* SGMII && 10GBase-R */ - fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); - fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); - fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); - } else { - puts("Invalid SerDes2 protocol for T4240RDB\n"); - } - - fm_disable_port(FM2_DTSEC5); - fm_disable_port(FM2_DTSEC6); - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } -#endif /* CFG_SYS_NUM_FMAN */ - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/nxp/t4rdb/t4240rdb.c b/board/nxp/t4rdb/t4240rdb.c index 5cacfd27380..11e2c0f78b7 100644 --- a/board/nxp/t4rdb/t4240rdb.c +++ b/board/nxp/t4rdb/t4240rdb.c @@ -128,7 +128,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif return 0; diff --git a/board/nxp/t4rdb/t4rdb.h b/board/nxp/t4rdb/t4rdb.h index bb3ce216d7d..9ec190c03cb 100644 --- a/board/nxp/t4rdb/t4rdb.h +++ b/board/nxp/t4rdb/t4rdb.h @@ -14,7 +14,6 @@ #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/out4/o4-imx6ull-nano/Kconfig b/board/out4/o4-imx6ull-nano/Kconfig index e2ab80b6d4d..1b948fdc9ff 100644 --- a/board/out4/o4-imx6ull-nano/Kconfig +++ b/board/out4/o4-imx6ull-nano/Kconfig @@ -13,21 +13,21 @@ choice prompt "Memory model" default K4B4G1646D_BCMA help - Memory type setup. + Memory type setup. Please choose correct memory model here. config K4B4G1646D_BCMA bool "K4B4G1646D-BCMA 256Mx16 (512 MiB/chip)" help - Samsung DDR3 SDRAM - K4B4G1646D-BCMA + Samsung DDR3 SDRAM + K4B4G1646D-BCMA config MT41K256M16HA_125E bool "MT41K256M16HA-125:E 256Mx16 (512 MiB/chip)" help - Micron DDR3L SDRAM - MT41K256M16HA-125:E + Micron DDR3L SDRAM + MT41K256M16HA-125:E endchoice @@ -35,21 +35,21 @@ choice prompt "Mainboard model" default O4_IMX_NANO help - Mainboard setup. + Mainboard setup. Please choose correct main board model here. config O4_IMX_NANO bool "O4-iMX-NANO" help - A baseboard for EV-iMX280-NANO module: - https://out4.ru/products/board/18-o4-imx-nano.html + A baseboard for EV-iMX280-NANO module: + https://out4.ru/products/board/18-o4-imx-nano.html config EV_IMX280_NANO_X_MB bool "EV-IMX280-NANO-X-MB" help - A simple baseboard for EV-iMX280-NANO module: - http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html + A simple baseboard for EV-iMX280-NANO module: + http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html endchoice diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 6afd03086f7..87fa70632e5 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -2,14 +2,14 @@ config PHYTEC_SOM_DETECTION bool "Support SoM detection for PHYTEC platforms" select SPL_CRC8 if SPL help - Support of I2C EEPROM based SoM detection. + Support of I2C EEPROM based SoM detection. config PHYTEC_SOM_DETECTION_BLOCKS bool "Extend SoM detection with block support" depends on PHYTEC_SOM_DETECTION help - Extend the I2C EEPROM based SoM detection with API v3. This API - introduces blocks with different payloads. + Extend the I2C EEPROM based SoM detection with API v3. This API + introduces blocks with different payloads. config PHYTEC_IMX8M_SOM_DETECTION bool "Support SoM detection for i.MX8M PHYTEC platforms" @@ -35,8 +35,8 @@ config PHYTEC_AM62_SOM_DETECTION depends on SPL_I2C && DM_I2C default y help - Support of I2C EEPROM based SoM detection. Supported - for PHYTEC AM62x boards. + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC AM62x boards. config PHYTEC_AM62A_SOM_DETECTION bool "Support SoM detection for AM62Ax PHYTEC platforms" @@ -46,8 +46,8 @@ config PHYTEC_AM62A_SOM_DETECTION depends on SPL_I2C && DM_I2C default y help - Support of I2C EEPROM based SoM detection. Supported - for PHYTEC AM62Ax boards. + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC AM62Ax boards. config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" @@ -57,8 +57,8 @@ config PHYTEC_AM64_SOM_DETECTION depends on SPL_I2C && DM_I2C default y help - Support of I2C EEPROM based SoM detection. Supported - for PHYTEC AM64x boards. + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC AM64x boards. config PHYTEC_EEPROM_BUS int "Board EEPROM's I2C bus number" diff --git a/board/phytec/common/k3/Kconfig b/board/phytec/common/k3/Kconfig index 282f4b79742..4bbe1a5ec3c 100644 --- a/board/phytec/common/k3/Kconfig +++ b/board/phytec/common/k3/Kconfig @@ -1,5 +1,5 @@ config PHYTEC_K3_DDR_PATCH bool "Patch DDR timings on PHYTEC K3 SoMs" help - Allow to override default DDR timings prior to - DDRSS driver probing. + Allow to override default DDR timings prior to + DDRSS driver probing. diff --git a/board/phytec/phycore_am62ax/Kconfig b/board/phytec/phycore_am62ax/Kconfig index 516dc8e2020..e7943c51dbc 100644 --- a/board/phytec/phycore_am62ax/Kconfig +++ b/board/phytec/phycore_am62ax/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "phycore_am62ax" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am62ax" @@ -24,7 +24,7 @@ config SYS_BOARD default "phycore_am62ax" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am62ax" diff --git a/board/phytec/phycore_am62ax/phycore-am62ax.c b/board/phytec/phycore_am62ax/phycore-am62ax.c index 3e1c4102cc1..b22ffe9072f 100644 --- a/board/phytec/phycore_am62ax/phycore-am62ax.c +++ b/board/phytec/phycore_am62ax/phycore-am62ax.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <spl.h> #include <fdt_support.h> +#include <image.h> #include "../common/am6_som_detection.h" @@ -57,3 +58,8 @@ void spl_board_init(void) dram_init_banksize(); } #endif + +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig index ecee5873c0c..feacc3d6d40 100644 --- a/board/phytec/phycore_am62x/Kconfig +++ b/board/phytec/phycore_am62x/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "phycore_am62x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am62x" @@ -24,7 +24,7 @@ config SYS_BOARD default "phycore_am62x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am62x" @@ -38,31 +38,31 @@ source "board/phytec/common/k3/Kconfig" endif config PHYCORE_AM62X_RAM_SIZE_FIX - bool "Set phyCORE-AM62x RAM size fix instead of detecting" - default false - help - RAM size is automatic being detected with the help of - the EEPROM introspection data. Set RAM size to a fix value - instead. + bool "Set phyCORE-AM62x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. choice - prompt "phyCORE-AM62x RAM size" - depends on PHYCORE_AM62X_RAM_SIZE_FIX - default PHYCORE_AM62X_RAM_SIZE_2GB + prompt "phyCORE-AM62x RAM size" + depends on PHYCORE_AM62X_RAM_SIZE_FIX + default PHYCORE_AM62X_RAM_SIZE_2GB config PHYCORE_AM62X_RAM_SIZE_1GB - bool "1GB RAM" - help - Set RAM size fix to 1GB for phyCORE-AM62x. + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM62x. config PHYCORE_AM62X_RAM_SIZE_2GB - bool "2GB RAM" - help - Set RAM size fix to 2GB for phyCORE-AM62x. + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM62x. config PHYCORE_AM62X_RAM_SIZE_4GB - bool "4GB RAM" - help - Set RAM size fix to 4GB for phyCORE-AM62x. + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-AM62x. endchoice diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 3cdcbf2ecc9..376379767cf 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -9,6 +9,7 @@ #include <spl.h> #include <asm/arch/k3-ddr.h> #include <fdt_support.h> +#include <image.h> #include "phycore-ddr-data.h" #include "../common/k3/k3_ddrss_patch.h" @@ -93,7 +94,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -101,34 +102,34 @@ int dram_init_banksize(void) ram_size = phytec_get_am62_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; case EEPROM_RAM_SIZE_4GB: /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR upper region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x80000000; + gd->dram[1].start = 0x880000000; + gd->dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -186,8 +187,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } ret = fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); @@ -237,3 +238,8 @@ void spl_board_init(void) MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); } #endif + +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} diff --git a/board/phytec/phycore_am62x/tifs-rm-cfg.yaml b/board/phytec/phycore_am62x/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..8510fe9526e --- /dev/null +++ b/board/phytec/phycore_am62x/tifs-rm-cfg.yaml @@ -0,0 +1,867 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62X +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 824 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 18 + type: 1677 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1677 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1677 + host_id: 128 + reserved: 0 + - + start_resource: 54 + num_resource: 18 + type: 1678 + host_id: 12 + reserved: 0 + - + start_resource: 72 + num_resource: 6 + type: 1678 + host_id: 35 + reserved: 0 + - + start_resource: 72 + num_resource: 6 + type: 1678 + host_id: 36 + reserved: 0 + - + start_resource: 78 + num_resource: 2 + type: 1678 + host_id: 30 + reserved: 0 + - + start_resource: 80 + num_resource: 2 + type: 1678 + host_id: 128 + reserved: 0 + - + start_resource: 32 + num_resource: 12 + type: 1679 + host_id: 12 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 35 + reserved: 0 + - + start_resource: 44 + num_resource: 6 + type: 1679 + host_id: 36 + reserved: 0 + - + start_resource: 50 + num_resource: 2 + type: 1679 + host_id: 30 + reserved: 0 + - + start_resource: 52 + num_resource: 2 + type: 1679 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 18 + type: 1696 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1696 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1696 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1696 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1696 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 18 + type: 1697 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1697 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1697 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1697 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 2 + type: 1697 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 12 + type: 1698 + host_id: 12 + reserved: 0 + - + start_resource: 12 + num_resource: 6 + type: 1698 + host_id: 35 + reserved: 0 + - + start_resource: 12 + num_resource: 6 + type: 1698 + host_id: 36 + reserved: 0 + - + start_resource: 18 + num_resource: 2 + type: 1698 + host_id: 30 + reserved: 0 + - + start_resource: 20 + num_resource: 2 + type: 1698 + host_id: 128 + reserved: 0 + - + start_resource: 5 + num_resource: 35 + type: 1802 + host_id: 12 + reserved: 0 + - + start_resource: 44 + num_resource: 35 + type: 1802 + host_id: 35 + reserved: 0 + - + start_resource: 44 + num_resource: 35 + type: 1802 + host_id: 36 + reserved: 0 + - + start_resource: 168 + num_resource: 7 + type: 1802 + host_id: 30 + reserved: 0 + - + start_resource: 0 + num_resource: 1024 + type: 1807 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 29 + type: 1808 + host_id: 128 + reserved: 0 + - + start_resource: 4608 + num_resource: 99 + type: 1809 + host_id: 128 + reserved: 0 + - + start_resource: 5120 + num_resource: 24 + type: 1810 + host_id: 128 + reserved: 0 + - + start_resource: 5632 + num_resource: 51 + type: 1811 + host_id: 128 + reserved: 0 + - + start_resource: 6144 + num_resource: 51 + type: 1812 + host_id: 128 + reserved: 0 + - + start_resource: 6656 + num_resource: 51 + type: 1813 + host_id: 128 + reserved: 0 + - + start_resource: 8192 + num_resource: 32 + type: 1814 + host_id: 128 + reserved: 0 + - + start_resource: 8704 + num_resource: 32 + type: 1815 + host_id: 128 + reserved: 0 + - + start_resource: 9216 + num_resource: 32 + type: 1816 + host_id: 128 + reserved: 0 + - + start_resource: 9728 + num_resource: 22 + type: 1817 + host_id: 128 + reserved: 0 + - + start_resource: 10240 + num_resource: 22 + type: 1818 + host_id: 128 + reserved: 0 + - + start_resource: 10752 + num_resource: 22 + type: 1819 + host_id: 128 + reserved: 0 + - + start_resource: 11264 + num_resource: 28 + type: 1820 + host_id: 128 + reserved: 0 + - + start_resource: 11776 + num_resource: 28 + type: 1821 + host_id: 128 + reserved: 0 + - + start_resource: 12288 + num_resource: 28 + type: 1822 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1936 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1936 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1936 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1936 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1936 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 64 + type: 1937 + host_id: 36 + reserved: 0 + - + start_resource: 83 + num_resource: 8 + type: 1938 + host_id: 12 + reserved: 0 + - + start_resource: 91 + num_resource: 8 + type: 1939 + host_id: 12 + reserved: 0 + - + start_resource: 99 + num_resource: 10 + type: 1942 + host_id: 12 + reserved: 0 + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 35 + reserved: 0 + - + start_resource: 109 + num_resource: 3 + type: 1942 + host_id: 36 + reserved: 0 + - + start_resource: 112 + num_resource: 3 + type: 1942 + host_id: 30 + reserved: 0 + - + start_resource: 115 + num_resource: 3 + type: 1942 + host_id: 128 + reserved: 0 + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 12 + reserved: 0 + - + start_resource: 118 + num_resource: 16 + type: 1943 + host_id: 36 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1944 + host_id: 12 + reserved: 0 + - + start_resource: 134 + num_resource: 8 + type: 1945 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1946 + host_id: 12 + reserved: 0 + - + start_resource: 142 + num_resource: 8 + type: 1947 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1955 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1955 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1955 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1955 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 8 + type: 1956 + host_id: 36 + reserved: 0 + - + start_resource: 27 + num_resource: 1 + type: 1957 + host_id: 12 + reserved: 0 + - + start_resource: 28 + num_resource: 1 + type: 1958 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1961 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1961 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1961 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1961 + host_id: 128 + reserved: 0 + - + start_resource: 0 + num_resource: 10 + type: 1962 + host_id: 12 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 35 + reserved: 0 + - + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 36 + reserved: 0 + - + start_resource: 13 + num_resource: 3 + type: 1962 + host_id: 30 + reserved: 0 + - + start_resource: 16 + num_resource: 3 + type: 1962 + host_id: 128 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 36 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 12 + reserved: 0 + - + start_resource: 19 + num_resource: 16 + type: 1964 + host_id: 36 + reserved: 0 + - + start_resource: 20 + num_resource: 1 + type: 1965 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1966 + host_id: 12 + reserved: 0 + - + start_resource: 21 + num_resource: 1 + type: 1967 + host_id: 12 + reserved: 0 + - + start_resource: 35 + num_resource: 8 + type: 1968 + host_id: 12 + reserved: 0 + - + start_resource: 22 + num_resource: 1 + type: 1969 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1970 + host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 + - + start_resource: 43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 + - + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 + - + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 diff --git a/board/phytec/phycore_am64x/Kconfig b/board/phytec/phycore_am64x/Kconfig index a709b71ba4d..a4d25b84b96 100644 --- a/board/phytec/phycore_am64x/Kconfig +++ b/board/phytec/phycore_am64x/Kconfig @@ -12,7 +12,7 @@ config SYS_BOARD default "phycore_am64x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am64x" @@ -27,7 +27,7 @@ config SYS_BOARD default "phycore_am64x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am64x" @@ -37,26 +37,26 @@ source "board/phytec/common/Kconfig" endif config PHYCORE_AM64X_RAM_SIZE_FIX - bool "Set phyCORE-AM64x RAM size fix instead of detecting" - default false - help - RAM size is automatic being detected with the help of - the EEPROM introspection data. Set RAM size to a fix value - instead. + bool "Set phyCORE-AM64x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. choice - prompt "phyCORE-AM64x RAM size" - depends on PHYCORE_AM64X_RAM_SIZE_FIX - default PHYCORE_AM64X_RAM_SIZE_2GB + prompt "phyCORE-AM64x RAM size" + depends on PHYCORE_AM64X_RAM_SIZE_FIX + default PHYCORE_AM64X_RAM_SIZE_2GB config PHYCORE_AM64X_RAM_SIZE_1GB - bool "1GB RAM" - help - Set RAM size fix to 1GB for phyCORE-AM64x. + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM64x. config PHYCORE_AM64X_RAM_SIZE_2GB - bool "2GB RAM" - help - Set RAM size fix to 2GB for phyCORE-AM64x. + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM64x. endchoice diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index 114aa217023..5e077872152 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -66,7 +66,7 @@ int dram_init_banksize(void) { u8 ram_size; - memset(gd->bd->bi_dram, 0, sizeof(gd->bd->bi_dram[0]) * CONFIG_NR_DRAM_BANKS); + memset(gd->dram, 0, sizeof(gd->dram[0]) * CONFIG_NR_DRAM_BANKS); if (!IS_ENABLED(CONFIG_CPU_V7R)) return fdtdec_setup_memory_banksize(); @@ -74,21 +74,21 @@ int dram_init_banksize(void) ram_size = phytec_get_am64_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x40000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x40000000; gd->ram_size = 0x40000000; break; case EEPROM_RAM_SIZE_2GB: - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; break; default: /* Continue with default 2GB setup */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = 0x80000000; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = 0x80000000; gd->ram_size = 0x80000000; printf("DDR size %d is not supported\n", ram_size); } @@ -109,8 +109,8 @@ int do_board_detect(void) dram_init_banksize(); for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; + start[bank] = gd->dram[bank].start; + size[bank] = gd->dram[bank].size; } return fdt_fixup_memory_banks(fdt, start, size, CONFIG_NR_DRAM_BANKS); diff --git a/board/phytec/phycore_am68x/Kconfig b/board/phytec/phycore_am68x/Kconfig index 37912fb4ed3..d82cdaf819b 100644 --- a/board/phytec/phycore_am68x/Kconfig +++ b/board/phytec/phycore_am68x/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "phycore_am68x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am68x" @@ -27,7 +27,7 @@ config SYS_BOARD default "phycore_am68x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am68x" diff --git a/board/phytec/phycore_am68x/rm-cfg.yaml b/board/phytec/phycore_am68x/rm-cfg.yaml index 8796463129d..728bfe241a4 100644 --- a/board/phytec/phycore_am68x/rm-cfg.yaml +++ b/board/phytec/phycore_am68x/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J721S2 # @@ -429,24 +429,24 @@ rm-cfg: reserved: 0 - start_resource: 10 - num_resource: 100 + num_resource: 98 type: 14528 host_id: 12 reserved: 0 - - start_resource: 110 + start_resource: 108 num_resource: 32 type: 14528 host_id: 13 reserved: 0 - - start_resource: 142 + start_resource: 140 num_resource: 21 type: 14528 host_id: 21 reserved: 0 - - start_resource: 163 + start_resource: 161 num_resource: 21 type: 14528 host_id: 23 @@ -1431,7 +1431,7 @@ rm-cfg: reserved: 0 - start_resource: 236 - num_resource: 20 + num_resource: 18 type: 16970 host_id: 128 reserved: 0 @@ -1497,7 +1497,7 @@ rm-cfg: reserved: 0 - start_resource: 3426 - num_resource: 1182 + num_resource: 1180 type: 16973 host_id: 128 reserved: 0 diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 9fc63febdac..a738e3542e2 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -31,8 +31,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index 6824454cdf4..421e193e730 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -44,8 +44,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 37b8c1eb78b..955cb5de030 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -9,26 +9,11 @@ F: configs/quartz64-b-rk3566_defconfig F: configs/soquartz-blade-rk3566_defconfig F: configs/soquartz-cm4-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig -F: arch/arm/dts/rk3566-quartz64-a.dts -F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -F: arch/arm/dts/rk3566-quartz64-b.dts -F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz.dtsi -F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz-blade.dts -F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz-cm4.dts -F: arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz-model-a.dts -F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi +F: arch/arm/dts/rk3566-quartz64* +F: arch/arm/dts/rk3566-soquartz* PINETAB2-RK3566 M: Jonas Karlman <[email protected]> S: Maintained F: configs/pinetab2-rk3566_defconfig -F: arch/arm/dts/rk3566-pinetab2.dtsi -F: arch/arm/dts/rk3566-pinetab2-u-boot.dtsi -F: arch/arm/dts/rk3566-pinetab2-v0.1.dts -F: arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi -F: arch/arm/dts/rk3566-pinetab2-v2.0.dts -F: arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi +F: arch/arm/dts/rk3566-pinetab2* diff --git a/board/pine64/quartzpro64-rk3588/MAINTAINERS b/board/pine64/quartzpro64-rk3588/MAINTAINERS index a7e944b7478..ff3500a32fc 100644 --- a/board/pine64/quartzpro64-rk3588/MAINTAINERS +++ b/board/pine64/quartzpro64-rk3588/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/pine64/quartzpro64-rk3588 F: include/configs/quartzpro64-rk3588.h F: configs/quartzpro64-rk3588_defconfig -F: arch/arm/dts/rk3588-quartzpro64.dts -F: arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi +F: arch/arm/dts/rk3588-quartzpro64* diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c index 7f0925074fa..23d24140ca7 100644 --- a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -26,7 +26,7 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP) +#if CONFIG_IS_ENABLED(NET) int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) diff --git a/board/purism/librem5/MAINTAINERS b/board/purism/librem5/MAINTAINERS index 09e7f20e33c..818e1850302 100644 --- a/board/purism/librem5/MAINTAINERS +++ b/board/purism/librem5/MAINTAINERS @@ -2,7 +2,6 @@ PURISM LIBREM5 PHONE M: Angus Ainslie <[email protected]> S: Supported -F: arch/arm/dts/imx8mq-librem5* F: board/purism/librem5/ F: configs/librem5_defconfig F: include/configs/librem5.h diff --git a/board/qualcomm/debug-milos.config b/board/qualcomm/debug-milos.config new file mode 100644 index 00000000000..a4cdd13f226 --- /dev/null +++ b/board/qualcomm/debug-milos.config @@ -0,0 +1,5 @@ +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0xa94000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config index 3fd064924a1..cf334d7ee20 100644 --- a/board/qualcomm/dragonboard410c/configs/chainloaded.config +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config @@ -4,4 +4,4 @@ CONFIG_TEXT_BASE=0x0 # CONFIG_REMAKE_ELF is not set CONFIG_POSITION_INDEPENDENT=y CONFIG_INIT_SP_RELATIVE=y -CONFIG_SYS_INIT_SP_BSS_OFFSET=524288 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x80000 diff --git a/board/qualcomm/qcom-phone.config b/board/qualcomm/qcom-phone.config index d24094eefdd..1387aa1dfa2 100644 --- a/board/qualcomm/qcom-phone.config +++ b/board/qualcomm/qcom-phone.config @@ -13,6 +13,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x1A000000 CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_USB_FUNCTION_ACM=y CONFIG_CMD_UMS_ABORT_KEYED=y +CONFIG_CMD_FASTBOOT_ABORT_KEYED=y # Record all console output and let it be dumped via fastboot CONFIG_CONSOLE_RECORD=y diff --git a/board/qualcomm/qcom-phone.env b/board/qualcomm/qcom-phone.env index e91ae3ecdfb..5eaa2ceada8 100644 --- a/board/qualcomm/qcom-phone.env +++ b/board/qualcomm/qcom-phone.env @@ -32,14 +32,15 @@ menucmd=setenv bootcmd run menucmd; bootmenu -1 bootmenu_0=Boot=bootefi bootmgr; pause bootmenu_1=Enable serial console gadget=run serial_gadget bootmenu_2=Enable USB mass storage=echo "Press any key to exit UMS mode"; ums 0 scsi 0 -bootmenu_3=Enable fastboot mode=run fastboot +bootmenu_3=Enable fastboot mode=echo "Press any key to exit fastboot mode"; run fastboot # Disabling bootretry means we'll just drop the shell bootmenu_4=Drop to shell=setenv bootretry -1 bootmenu_5=Reset device=reset bootmenu_6=Dump clocks=clk dump; pause bootmenu_7=Dump environment=printenv; pause bootmenu_8=Board info=bdinfo; pause -bootmenu_9=Dump bootargs=fdt print /chosen bootargs; pause +bootmenu_9=Dump bootargs=fdt addr $fdt_addr_r; fdt print /chosen bootargs; pause +bootmenu_10=Power off=poweroff # Allow holding the volume down button while U-Boot loads to enter # the boot menu diff --git a/board/qualcomm/tfa-optee.config b/board/qualcomm/tfa-optee.config new file mode 100644 index 00000000000..1e8364c114f --- /dev/null +++ b/board/qualcomm/tfa-optee.config @@ -0,0 +1,4 @@ +# Enables support for TF-A based OP-TEE as the open +# source TrustZone stack on Qcom platforms +CONFIG_TEE=y +CONFIG_OPTEE=y diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS index a569efa74e3..d4cd82139d5 100644 --- a/board/radxa/rock5a-rk3588s/MAINTAINERS +++ b/board/radxa/rock5a-rk3588s/MAINTAINERS @@ -1,9 +1,8 @@ ROCK5A-RK3588 -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: board/radxa/rock5a-rk3588s F: include/configs/rock5a-rk3588s.h F: configs/rock5a-rk3588s_defconfig -F: arch/arm/dts/rk3588s-rock-5a.dts -F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +F: arch/arm/dts/rk3588s-rock-5a* diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS index c8a43769105..2910d9bed3d 100644 --- a/board/radxa/rock5b-rk3588/MAINTAINERS +++ b/board/radxa/rock5b-rk3588/MAINTAINERS @@ -1,5 +1,5 @@ ROCK5B-RK3588 -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: board/radxa/rock5b-rk3588 diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index b0a1484c0fa..1da5df92351 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; */ unsigned long __section(".data") fw_dtb_pointer; +static phys_addr_t discovered_ram_size; + /* TODO([email protected]): Move these to the msg.c file */ struct msg_get_arm_mem { struct bcm2835_mbox_hdr hdr; @@ -335,10 +337,16 @@ int dram_init(void) * the u-boot's memory setup. */ gd->ram_size &= ~MMU_SECTION_SIZE; + discovered_ram_size = gd->ram_size; return 0; } +phys_size_t get_effective_memsize(void) +{ + return discovered_ram_size; +} + #ifdef CONFIG_OF_BOARD int dram_init_banksize(void) { @@ -356,9 +364,9 @@ int dram_init_banksize(void) /* Update gd->ram_size to reflect total RAM across all banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (gd->bd->bi_dram[i].size == 0) + if (gd->dram[i].size == 0) break; - total_size += gd->bd->bi_dram[i].size; + total_size += gd->dram[i].size; } gd->ram_size = total_size; diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 889de8ea9ac..16902d216f6 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -45,9 +45,13 @@ endif endif ifdef CONFIG_RCAR_GEN5 +ifdef CONFIG_RCAR_64_RSIP +obj-y += gen5-cm33.o +else obj-y += gen5-common.o endif endif +endif endif endif diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c index e4c1190eac7..5a0b0ebe115 100644 --- a/board/renesas/common/gen4-spl.c +++ b/board/renesas/common/gen4-spl.c @@ -18,6 +18,12 @@ #include <mapmem.h> #include <spl.h> +#define APMU_BASE 0xe6170000U +#define CL0GRP3_BIT BIT(3) +#define CL1GRP3_BIT BIT(7) +#define RTGRP3_BIT BIT(19) +#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) + #define CNTCR_EN BIT(0) #ifdef CONFIG_SPL_BUILD @@ -47,6 +53,18 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + init_generic_timer(); + + /* Define for Work Around of APMU */ + writel(0x00ff00ff, APMU_BASE + 0x10); + writel(0x00ff00ff, APMU_BASE + 0x14); + writel(0x00ff00ff, APMU_BASE + 0x18); + writel(0x00ff00ff, APMU_BASE + 0x1c); + clrbits_le32(APMU_BASE + 0x68, BIT(29)); + if (CONFIG_IS_ENABLED(OF_CONTROL)) { ret = spl_early_init(); if (ret) { @@ -76,29 +94,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0); } -#define APMU_BASE 0xe6170000U -#define CL0GRP3_BIT BIT(3) -#define CL1GRP3_BIT BIT(7) -#define RTGRP3_BIT BIT(19) -#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) - -int mach_cpu_init(void) -{ - /* Unlock CPG access */ - writel(0x5A5AFFFF, CPGWPR); - writel(0xA5A50000, CPGWPCR); - init_generic_timer(); - - /* Define for Work Around of APMU */ - writel(0x00ff00ff, APMU_BASE + 0x10); - writel(0x00ff00ff, APMU_BASE + 0x14); - writel(0x00ff00ff, APMU_BASE + 0x18); - writel(0x00ff00ff, APMU_BASE + 0x1c); - clrbits_le32(APMU_BASE + 0x68, BIT(29)); - - return 0; -} - void reset_cpu(void) { } diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c new file mode 100644 index 00000000000..b2f6087a943 --- /dev/null +++ b/board/renesas/common/gen5-cm33.c @@ -0,0 +1,1455 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include <asm/arch/renesas.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <dm/uclass.h> +#include <hang.h> +#include <linux/bitfield.h> +#include <linux/errno.h> +#include <linux/iopoll.h> +#include <lmb.h> + +#include "gen5-cm33.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define PKC_PROT_LOCK 0xa5a5a500 +#define PKC_PROT_UNLOCK 0xa5a5a501 + +#define RSIP_BASE 0xe0000000 +#define RSIP_NVIC_ISER_00 (RSIP_BASE + 0xe100) +#define RSIP_NVIC_ISER_00_SETENA_INTIWDTA0 BIT(16) +#define RSIP_NVIC_ICER_00 (RSIP_BASE + 0xe180) +#define RSIP_NVIC_ICER_01 (RSIP_BASE + 0xe184) +#define RSIP_NVIC_ICER_02 (RSIP_BASE + 0xe188) +#define RSIP_NVIC_ICER_03 (RSIP_BASE + 0xe18c) +#define RSIP_NVIC_ICER_04 (RSIP_BASE + 0xe190) +#define RSIP_NVIC_ICER_05 (RSIP_BASE + 0xe194) +#define RSIP_NVIC_ICER_06 (RSIP_BASE + 0xe198) +#define RSIP_NVIC_ICER_07 (RSIP_BASE + 0xe19c) +#define RSIP_NVIC_ICER_08 (RSIP_BASE + 0xe1a0) +#define RSIP_NVIC_ICER_09 (RSIP_BASE + 0xe1a4) +#define RSIP_NVIC_ICER_10 (RSIP_BASE + 0xe1a8) +#define RSIP_NVIC_ICER_11 (RSIP_BASE + 0xe1ac) +#define RSIP_NVIC_ICER_12 (RSIP_BASE + 0xe1b0) +#define RSIP_NVIC_ICER_13 (RSIP_BASE + 0xe1b4) +#define RSIP_NVIC_ICER_14 (RSIP_BASE + 0xe1b8) +#define RSIP_NVIC_ICER_15 (RSIP_BASE + 0xe1bc) +#define RSIP_SHCSR (RSIP_BASE + 0xed24) +#define RSIP_SHCSR_USGFAULTENA BIT(18) +#define RSIP_SHCSR_BUSFAULTENA BIT(17) +#define RSIP_SHCSR_MEMFAULTENA BIT(16) + +#define RSIP_CTL_BASE 0x5fffd000 +#define RSIP_CTL_CFG4 (RSIP_CTL_BASE + 0xb0) +#define RSIP_CTL_CFG4_OPWDEN BIT(3) +#define RSIP_CTL_CFG4_OPWDVAC BIT(5) +#define RSIP_CTL_ESICREMAP0 (RSIP_CTL_BASE + 0x70) +#define RSIP_CTL_PROT0PCMD (RSIP_CTL_BASE + 0x840) +#define RSIP_CTL_PROT0PCMD_WREN 0xa5 +#define RSIP_CTL_PROT0PS (RSIP_CTL_BASE + 0x844) +#define RSIP_CTL_PROT0PS_ERR BIT(0) + +#define SYSSS_BASE 0xc1320000 +#define SYSSS_MODE1 (SYSSS_BASE + 0x1010) +#define SYSSS_MODE1_MASK GENMASK(11, 0) +#define SYSSS_MODE1_BAUDRATE_MASK GENMASK(10, 9) +#define SYSSS_MODE1_BAUDRATE_921600 1 +#define SYSSS_MODE1_BAUDRATE_1843200 2 +#define SYSSS_MODE1_BAUDRATE_3250000 3 +#define SYSSS_MODE1_BOOTMODE_MASK GENMASK(20, 18) +#define SYSSS_MODE1_BOOTMODE_HF_DMA 2 +#define SYSSS_MODE1_BOOTMODE_QSPI 4 +#define SYSSS_MODE1_BOOTMODE_UFS 6 + +#define CLK_CONTROL_TOP_BASE 0xc6480000 +#define CLK_CONTROL_SCP_BASE 0xc1330000 +#define CLK_CONTROL_PERE_BASE 0xc08f0000 + +#define CLK_CONTROL_PLL01_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1108) +#define CLK_CONTROL_PLL01_1_CR0 (CLK_CONTROL_TOP_BASE + 0x1114) +#define CLK_CONTROL_PLL02_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1120) +#define CLK_CONTROL_PLL02_1_CR0 (CLK_CONTROL_TOP_BASE + 0x112c) +#define CLK_CONTROL_PLL02_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1138) +#define CLK_CONTROL_PLL02_3_CR0 (CLK_CONTROL_TOP_BASE + 0x1144) +#define CLK_CONTROL_PLL02_4_CR0 (CLK_CONTROL_TOP_BASE + 0x1150) +#define CLK_CONTROL_PLL02_5_CR0 (CLK_CONTROL_TOP_BASE + 0x115c) +#define CLK_CONTROL_PLL02_6_CR0 (CLK_CONTROL_TOP_BASE + 0x1168) +#define CLK_CONTROL_PLL02_7_CR0 (CLK_CONTROL_TOP_BASE + 0x1174) +#define CLK_CONTROL_PLL03_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1180) +#define CLK_CONTROL_PLL03_1_CR0 (CLK_CONTROL_TOP_BASE + 0x118c) +#define CLK_CONTROL_PLL03_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1198) +#define CLK_CONTROL_PLL03_3_CR0 (CLK_CONTROL_TOP_BASE + 0x11a4) +#define CLK_CONTROL_PLL06_CR0 (CLK_CONTROL_TOP_BASE + 0x11c8) +#define CLK_CONTROL_PLL07_CR0 (CLK_CONTROL_TOP_BASE + 0x11d4) +#define CLK_CONTROL_PLL12_CR0 (CLK_CONTROL_TOP_BASE + 0x121c) +#define CLK_CONTROL_PLL13_CR0 (CLK_CONTROL_SCP_BASE + 0x1228) +#define CLK_CONTROL_PLL14_CR0 (CLK_CONTROL_TOP_BASE + 0x1234) +#define CLK_CONTROL_PLL15_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1240) +#define CLK_CONTROL_PLL15_1_CR0 (CLK_CONTROL_TOP_BASE + 0x124c) +#define CLK_CONTROL_PLL15_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1258) +#define CLK_CONTROL_PLL15_3_CR0 (CLK_CONTROL_TOP_BASE + 0x1264) +#define CLK_CONTROL_PLL01_0_CR1 (CLK_CONTROL_TOP_BASE + 0x110c) +#define CLK_CONTROL_PLL01_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1118) +#define CLK_CONTROL_PLL02_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1124) +#define CLK_CONTROL_PLL02_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1130) +#define CLK_CONTROL_PLL02_2_CR1 (CLK_CONTROL_TOP_BASE + 0x113c) +#define CLK_CONTROL_PLL02_3_CR1 (CLK_CONTROL_TOP_BASE + 0x1148) +#define CLK_CONTROL_PLL02_4_CR1 (CLK_CONTROL_TOP_BASE + 0x1154) +#define CLK_CONTROL_PLL02_5_CR1 (CLK_CONTROL_TOP_BASE + 0x1160) +#define CLK_CONTROL_PLL02_6_CR1 (CLK_CONTROL_TOP_BASE + 0x116c) +#define CLK_CONTROL_PLL02_7_CR1 (CLK_CONTROL_TOP_BASE + 0x1178) +#define CLK_CONTROL_PLL03_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1184) +#define CLK_CONTROL_PLL03_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1190) +#define CLK_CONTROL_PLL03_2_CR1 (CLK_CONTROL_TOP_BASE + 0x119c) +#define CLK_CONTROL_PLL03_3_CR1 (CLK_CONTROL_TOP_BASE + 0x11a8) +#define CLK_CONTROL_PLL06_CR1 (CLK_CONTROL_TOP_BASE + 0x11cc) +#define CLK_CONTROL_PLL07_CR1 (CLK_CONTROL_TOP_BASE + 0x11d8) +#define CLK_CONTROL_PLL12_CR1 (CLK_CONTROL_TOP_BASE + 0x1220) +#define CLK_CONTROL_PLL13_CR1 (CLK_CONTROL_SCP_BASE + 0x122c) +#define CLK_CONTROL_PLL14_CR1 (CLK_CONTROL_TOP_BASE + 0x1238) +#define CLK_CONTROL_PLL15_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1244) +#define CLK_CONTROL_PLL15_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1250) +#define CLK_CONTROL_PLL15_2_CR1 (CLK_CONTROL_TOP_BASE + 0x125c) +#define CLK_CONTROL_PLL15_3_CR1 (CLK_CONTROL_TOP_BASE + 0x1268) +#define CLK_CONTROL_PLL01_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1110) +#define CLK_CONTROL_PLL01_1_CR2 (CLK_CONTROL_TOP_BASE + 0x111c) +#define CLK_CONTROL_PLL02_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1128) +#define CLK_CONTROL_PLL02_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1134) +#define CLK_CONTROL_PLL02_2_CR2 (CLK_CONTROL_TOP_BASE + 0x1140) +#define CLK_CONTROL_PLL02_3_CR2 (CLK_CONTROL_TOP_BASE + 0x114c) +#define CLK_CONTROL_PLL02_4_CR2 (CLK_CONTROL_TOP_BASE + 0x1158) +#define CLK_CONTROL_PLL02_5_CR2 (CLK_CONTROL_TOP_BASE + 0x1164) +#define CLK_CONTROL_PLL02_6_CR2 (CLK_CONTROL_TOP_BASE + 0x1170) +#define CLK_CONTROL_PLL02_7_CR2 (CLK_CONTROL_TOP_BASE + 0x117c) +#define CLK_CONTROL_PLL03_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1188) +#define CLK_CONTROL_PLL03_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1194) +#define CLK_CONTROL_PLL03_2_CR2 (CLK_CONTROL_TOP_BASE + 0x11a0) +#define CLK_CONTROL_PLL03_3_CR2 (CLK_CONTROL_TOP_BASE + 0x11ac) +#define CLK_CONTROL_PLL06_CR2 (CLK_CONTROL_TOP_BASE + 0x11d0) +#define CLK_CONTROL_PLL07_CR2 (CLK_CONTROL_TOP_BASE + 0x11dc) +#define CLK_CONTROL_PLL12_CR2 (CLK_CONTROL_TOP_BASE + 0x1224) +#define CLK_CONTROL_PLL13_CR2 (CLK_CONTROL_SCP_BASE + 0x1230) +#define CLK_CONTROL_PLL14_CR2 (CLK_CONTROL_TOP_BASE + 0x123c) +#define CLK_CONTROL_PLL15_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1248) +#define CLK_CONTROL_PLL15_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1254) +#define CLK_CONTROL_PLL15_2_CR2 (CLK_CONTROL_TOP_BASE + 0x1260) +#define CLK_CONTROL_PLL15_3_CR2 (CLK_CONTROL_TOP_BASE + 0x126c) +#define CLK_CONTROL_PLL01_0_SCR (CLK_CONTROL_TOP_BASE + 0x1270) +#define CLK_CONTROL_PLL01_1_SCR (CLK_CONTROL_TOP_BASE + 0x1278) +#define CLK_CONTROL_PLL02_0_SCR (CLK_CONTROL_TOP_BASE + 0x1280) +#define CLK_CONTROL_PLL02_1_SCR (CLK_CONTROL_TOP_BASE + 0x1288) +#define CLK_CONTROL_PLL02_2_SCR (CLK_CONTROL_TOP_BASE + 0x1290) +#define CLK_CONTROL_PLL02_3_SCR (CLK_CONTROL_TOP_BASE + 0x1298) +#define CLK_CONTROL_PLL02_4_SCR (CLK_CONTROL_TOP_BASE + 0x12a0) +#define CLK_CONTROL_PLL02_5_SCR (CLK_CONTROL_TOP_BASE + 0x12a8) +#define CLK_CONTROL_PLL02_6_SCR (CLK_CONTROL_TOP_BASE + 0x12b0) +#define CLK_CONTROL_PLL02_7_SCR (CLK_CONTROL_TOP_BASE + 0x12b8) +#define CLK_CONTROL_PLL03_0_SCR (CLK_CONTROL_TOP_BASE + 0x12c0) +#define CLK_CONTROL_PLL03_1_SCR (CLK_CONTROL_TOP_BASE + 0x12c8) +#define CLK_CONTROL_PLL03_2_SCR (CLK_CONTROL_TOP_BASE + 0x12d0) +#define CLK_CONTROL_PLL03_3_SCR (CLK_CONTROL_TOP_BASE + 0x12d8) +#define CLK_CONTROL_PLL06_SCR (CLK_CONTROL_TOP_BASE + 0x12f0) +#define CLK_CONTROL_PLL07_SCR (CLK_CONTROL_TOP_BASE + 0x12f8) +#define CLK_CONTROL_PLL12_SCR (CLK_CONTROL_TOP_BASE + 0x1328) +#define CLK_CONTROL_PLL13_SCR (CLK_CONTROL_SCP_BASE + 0x1330) +#define CLK_CONTROL_PLL14_SCR (CLK_CONTROL_TOP_BASE + 0x1338) +#define CLK_CONTROL_PLL15_0_SCR (CLK_CONTROL_TOP_BASE + 0x1340) +#define CLK_CONTROL_PLL15_1_SCR (CLK_CONTROL_TOP_BASE + 0x1348) +#define CLK_CONTROL_PLL15_2_SCR (CLK_CONTROL_TOP_BASE + 0x1350) +#define CLK_CONTROL_PLL15_3_SCR (CLK_CONTROL_TOP_BASE + 0x1358) +#define CLK_CONTROL_PLL01_0_DCR (CLK_CONTROL_TOP_BASE + 0x1274) +#define CLK_CONTROL_PLL01_1_DCR (CLK_CONTROL_TOP_BASE + 0x127c) +#define CLK_CONTROL_PLL02_0_DCR (CLK_CONTROL_TOP_BASE + 0x1284) +#define CLK_CONTROL_PLL02_1_DCR (CLK_CONTROL_TOP_BASE + 0x128c) +#define CLK_CONTROL_PLL02_2_DCR (CLK_CONTROL_TOP_BASE + 0x1294) +#define CLK_CONTROL_PLL02_3_DCR (CLK_CONTROL_TOP_BASE + 0x129c) +#define CLK_CONTROL_PLL02_4_DCR (CLK_CONTROL_TOP_BASE + 0x12a4) +#define CLK_CONTROL_PLL02_5_DCR (CLK_CONTROL_TOP_BASE + 0x12ac) +#define CLK_CONTROL_PLL02_6_DCR (CLK_CONTROL_TOP_BASE + 0x12b4) +#define CLK_CONTROL_PLL02_7_DCR (CLK_CONTROL_TOP_BASE + 0x12bc) +#define CLK_CONTROL_PLL03_0_DCR (CLK_CONTROL_TOP_BASE + 0x12c4) +#define CLK_CONTROL_PLL03_1_DCR (CLK_CONTROL_TOP_BASE + 0x12cc) +#define CLK_CONTROL_PLL03_2_DCR (CLK_CONTROL_TOP_BASE + 0x12d4) +#define CLK_CONTROL_PLL03_3_DCR (CLK_CONTROL_TOP_BASE + 0x12dc) +#define CLK_CONTROL_PLL06_DCR (CLK_CONTROL_TOP_BASE + 0x12f4) +#define CLK_CONTROL_PLL07_DCR (CLK_CONTROL_TOP_BASE + 0x12fc) +#define CLK_CONTROL_PLL12_DCR (CLK_CONTROL_TOP_BASE + 0x132c) +#define CLK_CONTROL_PLL13_DCR (CLK_CONTROL_SCP_BASE + 0x1334) +#define CLK_CONTROL_PLL14_DCR (CLK_CONTROL_TOP_BASE + 0x133c) +#define CLK_CONTROL_PLL15_0_DCR (CLK_CONTROL_TOP_BASE + 0x1344) +#define CLK_CONTROL_PLL15_1_DCR (CLK_CONTROL_TOP_BASE + 0x134c) +#define CLK_CONTROL_PLL15_2_DCR (CLK_CONTROL_TOP_BASE + 0x1354) +#define CLK_CONTROL_PLL15_3_DCR (CLK_CONTROL_TOP_BASE + 0x135c) +#define CLK_CONTROL_RPCCKCR (CLK_CONTROL_PERE_BASE + 0x1030) +#define CLK_CONTROL_RPCCKCR_CKSTP1 BIT(8) +#define CLK_CONTROL_RPCCKCR_RPCFC_MASK GENMASK(4, 0) +#define CLK_CONTROL_PROT_REG_MASK 0xffff +#define CLK_CONTROL_PROT_REG 0x1370 + +#define CLK_CONTROL_PLL_CR2_PLLCLKSTAB BIT(31) +#define CLK_CONTROL_PLL_CR2_PLLDISTRG BIT(29) +#define CLK_CONTROL_PLL_CR2_PLLENTRG BIT(28) +#define CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC BIT(0) +#define CLK_CONTROL_PLL_SCR_SELACT_MASK BIT(16) +#define CLK_CONTROL_PLL_DCR_PLLDIVSYNC BIT(16) + +/** + * sysss_read_modemr() - Read MODE Register 1 + * @return: MD[11:0] pin state + */ +static u32 sysss_read_modemr(void) +{ + return readl(SYSSS_MODE1) & SYSSS_MODE1_MASK; +} + +/** + * clk_control_poll_cr2() - Poll CR2 until PLL is stable + * @cr2: PLL CR2 register address + */ +static void clk_control_poll_cr2(const u32 cr2) +{ + u32 val; + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(cr2); + if (val & CLK_CONTROL_PLL_CR2_PLLCLKSTAB) + break; + } +} + +/** + * clk_control_write_cr() - Write protected clock controller register + * @reg: Register address + * @val: Value to be written + */ +static void clk_control_write_cr(const u32 reg, const u32 val) +{ + const u32 protreg = (reg & ~CLK_CONTROL_PROT_REG_MASK) | CLK_CONTROL_PROT_REG; + + writel(PKC_PROT_UNLOCK, protreg); + writel(val, reg); + writel(PKC_PROT_LOCK, protreg); +} + +/** + * clk_control_write_and_poll_dcr() - Write and poll DCR + * @dcr: DCR register address + * @val: Value to be written + */ +static void clk_control_write_and_poll_dcr(const u32 dcr, const u32 val) +{ + u32 tmp; + + clk_control_write_cr(dcr, val); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + tmp = readl(dcr); + if (tmp & CLK_CONTROL_PLL_DCR_PLLDIVSYNC) + break; + } +} + +/** + * clk_control_switch_from_iosc_to_pll() - Switch clock from internal oscillator to PLL + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + */ +static void clk_control_switch_from_iosc_to_pll(const u32 cr2, const u32 scr) +{ + u32 val; + + clk_control_poll_cr2(cr2); + + /* Switch from internal oscillator to PLL. */ + val = readl(scr); + val &= ~CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC; + clk_control_write_cr(scr, val); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(scr); + if (!(val & CLK_CONTROL_PLL_SCR_SELACT_MASK)) + break; + } +} + +/** + * clk_control_switch_from_pll_to_iosc() - Switch clock from PLL to internal oscillator + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + */ +static void clk_control_switch_from_pll_to_iosc(const u32 cr2, const u32 scr) +{ + u32 val; + + clk_control_poll_cr2(cr2); + + /* Switch from PLL to internal oscillator. */ + clk_control_write_cr(scr, CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(scr); + if (val & CLK_CONTROL_PLL_SCR_SELACT_MASK) + break; + } +} + +/** + * clk_control_set_pll_freq() - Set PLL frequency + * @cr0: PLL CR0 register address + * @cr1: PLL CR1 register address + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + * @dcr: PLL DCR register address + * @cr0_val: PLL CR0 register value + * @cr1_val: PLL CR1 register value + * @dcr_val: PLL DCR register value + */ +static void clk_control_set_pll_freq(const u32 cr0, const u32 cr1, const u32 cr2, + const u32 scr, const u32 dcr, const u32 cr0_val, + const u32 cr1_val, const u32 dcr_val) +{ + u32 val; + + clk_control_switch_from_pll_to_iosc(cr2, scr); + + /* Disable PLL trigger and wait until it unlocks */ + clk_control_write_cr(cr2, CLK_CONTROL_PLL_CR2_PLLDISTRG); + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(cr2); + if (!(val & CLK_CONTROL_PLL_CR2_PLLCLKSTAB)) + break; + } + + clk_control_write_cr(cr0, cr0_val); + clk_control_write_cr(cr1, cr1_val); + clk_control_write_cr(dcr, dcr_val); + + /* Enable PLL */ + clk_control_write_cr(cr2, CLK_CONTROL_PLL_CR2_PLLENTRG); +} + +/** + * clk_control_set_pll() - Load configuration into PLLs + */ +static void clk_control_set_pll(void) +{ + /* Switch PLLs to internal oscillator and configure dividers. */ + clk_control_set_pll_freq(CLK_CONTROL_PLL01_0_CR0, CLK_CONTROL_PLL01_0_CR1, + CLK_CONTROL_PLL01_0_CR2, CLK_CONTROL_PLL01_0_SCR, + CLK_CONTROL_PLL01_0_DCR, 0x06500000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL01_1_CR0, CLK_CONTROL_PLL01_1_CR1, + CLK_CONTROL_PLL01_1_CR2, CLK_CONTROL_PLL01_1_SCR, + CLK_CONTROL_PLL01_1_DCR, 0x04c00000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL02_0_CR0, CLK_CONTROL_PLL02_0_CR1, + CLK_CONTROL_PLL02_0_CR2, CLK_CONTROL_PLL02_0_SCR, + CLK_CONTROL_PLL02_0_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_1_CR0, CLK_CONTROL_PLL02_1_CR1, + CLK_CONTROL_PLL02_1_CR2, CLK_CONTROL_PLL02_1_SCR, + CLK_CONTROL_PLL02_1_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_2_CR0, CLK_CONTROL_PLL02_2_CR1, + CLK_CONTROL_PLL02_2_CR2, CLK_CONTROL_PLL02_2_SCR, + CLK_CONTROL_PLL02_2_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_3_CR0, CLK_CONTROL_PLL02_3_CR1, + CLK_CONTROL_PLL02_3_CR2, CLK_CONTROL_PLL02_3_SCR, + CLK_CONTROL_PLL02_3_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_4_CR0, CLK_CONTROL_PLL02_4_CR1, + CLK_CONTROL_PLL02_4_CR2, CLK_CONTROL_PLL02_4_SCR, + CLK_CONTROL_PLL02_4_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_5_CR0, CLK_CONTROL_PLL02_5_CR1, + CLK_CONTROL_PLL02_5_CR2, CLK_CONTROL_PLL02_5_SCR, + CLK_CONTROL_PLL02_5_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_6_CR0, CLK_CONTROL_PLL02_6_CR1, + CLK_CONTROL_PLL02_6_CR2, CLK_CONTROL_PLL02_6_SCR, + CLK_CONTROL_PLL02_6_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_7_CR0, CLK_CONTROL_PLL02_7_CR1, + CLK_CONTROL_PLL02_7_CR2, CLK_CONTROL_PLL02_7_SCR, + CLK_CONTROL_PLL02_7_DCR, 0x08900000, 0x04000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL03_0_CR0, CLK_CONTROL_PLL03_0_CR1, + CLK_CONTROL_PLL03_0_CR2, CLK_CONTROL_PLL03_0_SCR, + CLK_CONTROL_PLL03_0_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_1_CR0, CLK_CONTROL_PLL03_1_CR1, + CLK_CONTROL_PLL03_1_CR2, CLK_CONTROL_PLL03_1_SCR, + CLK_CONTROL_PLL03_1_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_2_CR0, CLK_CONTROL_PLL03_2_CR1, + CLK_CONTROL_PLL03_2_CR2, CLK_CONTROL_PLL03_2_SCR, + CLK_CONTROL_PLL03_2_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_3_CR0, CLK_CONTROL_PLL03_3_CR1, + CLK_CONTROL_PLL03_3_CR2, CLK_CONTROL_PLL03_3_SCR, + CLK_CONTROL_PLL03_3_DCR, 0x05f00000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL06_CR0, CLK_CONTROL_PLL06_CR1, + CLK_CONTROL_PLL06_CR2, CLK_CONTROL_PLL06_SCR, + CLK_CONTROL_PLL06_DCR, 0x0a700000, 0x0c000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL07_CR0, CLK_CONTROL_PLL07_CR1, + CLK_CONTROL_PLL07_CR2, CLK_CONTROL_PLL07_SCR, + CLK_CONTROL_PLL07_DCR, 0x09500000, 0x08000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL12_CR0, CLK_CONTROL_PLL12_CR1, + CLK_CONTROL_PLL12_CR2, CLK_CONTROL_PLL12_SCR, + CLK_CONTROL_PLL12_DCR, 0x0a400000, 0x0c000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL13_CR0, CLK_CONTROL_PLL13_CR1, + CLK_CONTROL_PLL13_CR2, CLK_CONTROL_PLL13_SCR, + CLK_CONTROL_PLL13_DCR, 0x08f00000, 0x08000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL14_CR0, CLK_CONTROL_PLL14_CR1, + CLK_CONTROL_PLL14_CR2, CLK_CONTROL_PLL14_SCR, + CLK_CONTROL_PLL14_DCR, 0x04700000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL15_0_CR0, CLK_CONTROL_PLL15_0_CR1, + CLK_CONTROL_PLL15_0_CR2, CLK_CONTROL_PLL15_0_SCR, + CLK_CONTROL_PLL15_0_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_1_CR0, CLK_CONTROL_PLL15_1_CR1, + CLK_CONTROL_PLL15_1_CR2, CLK_CONTROL_PLL15_1_SCR, + CLK_CONTROL_PLL15_1_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_2_CR0, CLK_CONTROL_PLL15_2_CR1, + CLK_CONTROL_PLL15_2_CR2, CLK_CONTROL_PLL15_2_SCR, + CLK_CONTROL_PLL15_2_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_3_CR0, CLK_CONTROL_PLL15_3_CR1, + CLK_CONTROL_PLL15_3_CR2, CLK_CONTROL_PLL15_3_SCR, + CLK_CONTROL_PLL15_3_DCR, 0x07700000, 0x04000000, 0x18); + + /* Switch PLLs back and wait for them to stabilize. */ + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_0_CR2, CLK_CONTROL_PLL01_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_1_CR2, CLK_CONTROL_PLL01_1_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_0_CR2, CLK_CONTROL_PLL02_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_1_CR2, CLK_CONTROL_PLL02_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_2_CR2, CLK_CONTROL_PLL02_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_3_CR2, CLK_CONTROL_PLL02_3_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_4_CR2, CLK_CONTROL_PLL02_4_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_5_CR2, CLK_CONTROL_PLL02_5_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_6_CR2, CLK_CONTROL_PLL02_6_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_7_CR2, CLK_CONTROL_PLL02_7_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_0_CR2, CLK_CONTROL_PLL03_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_1_CR2, CLK_CONTROL_PLL03_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_2_CR2, CLK_CONTROL_PLL03_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_3_CR2, CLK_CONTROL_PLL03_3_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL06_CR2, CLK_CONTROL_PLL06_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL07_CR2, CLK_CONTROL_PLL07_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL12_CR2, CLK_CONTROL_PLL12_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL13_CR2, CLK_CONTROL_PLL13_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL14_CR2, CLK_CONTROL_PLL14_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_0_CR2, CLK_CONTROL_PLL15_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_1_CR2, CLK_CONTROL_PLL15_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_2_CR2, CLK_CONTROL_PLL15_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_3_CR2, CLK_CONTROL_PLL15_3_SCR); + + /* Write second-stage DCR */ + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_1_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_3_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_4_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_5_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_6_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_7_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_3_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL06_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL07_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL12_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL13_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL14_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_3_DCR, 0x10); + + udelay(25); + + /* Write third-stage DCR */ + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_1_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_3_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_4_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_5_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_6_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_7_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_3_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL06_DCR, 0x10); /* 1/2 */ + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL07_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL12_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL13_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL14_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_3_DCR, 0x00); + + udelay(25); +} + +#define MDLC_PERW_BASE 0xc05d0000 +#define MDLC_PERE_BASE 0xc08f0000 +#define MDLC_HSCN_BASE 0xc9c90000 +/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ +#define MDLC_RT_BASE 0xb9440000 +#define MDLC_SCP_BASE 0xc1330000 + +#define MDLC_SCP_MSRES02 (MDLC_SCP_BASE + 0x908) +#define MDLC_SCP_MSRESS02 (MDLC_SCP_BASE + 0x968) +#define MDLC_SCP_MSRES02_SCP_MASK GENMASK(1, 0) +#define MDLC_SCP_PKCPROT1 (MDLC_SCP_BASE + 0xcf4) + +#define MDLC_PERW_MSRES05 (MDLC_PERW_BASE + 0x914) +#define MDLC_PERW_MSRESS05 (MDLC_PERW_BASE + 0x974) +#define MDLC_PERW_MSRES05_HSCIF0_MASK GENMASK(9, 8) +#define MDLC_PERW_MSRES05_HSCIF1_MASK GENMASK(11, 10) +#define MDLC_MSRESS_STANDBY 0 +#define MDLC_MSRESS_RESET 1 +#define MDLC_MSRESS_STOP 2 +#define MDLC_MSRESS_RUN 3 +#define MDLC_PERW_PKCPROT1 (MDLC_PERW_BASE + 0xcf4) + +#define MDLC_MPG_GATING 0 +#define MDLC_MPG_RESET 1 +#define MDLC_MPG_RUN 3 + +#define MDLC_PERE_MPIER (MDLC_PERE_BASE + 0x110) +#define MDLC_PERE_MPIMR (MDLC_PERE_BASE + 0x120) +#define MDLC_PERE_MPDG00 (MDLC_PERE_BASE + 0x200) +#define MDLC_PERE_MPDG01 (MDLC_PERE_BASE + 0x204) +#define MDLC_PERE_MPDGS00 (MDLC_PERE_BASE + 0x300) +#define MDLC_PERE_MPDGS01 (MDLC_PERE_BASE + 0x304) +#define MDLC_PERE_MSRES06 (MDLC_PERE_BASE + 0x918) +#define MDLC_PERE_MSRESS06 (MDLC_PERE_BASE + 0x978) +#define MDLC_PERE_PKCPROT0 (MDLC_PERE_BASE + 0xcf0) +#define MDLC_PERE_PKCPROT1 (MDLC_PERE_BASE + 0xcf4) +#define MDLC_PERE_MSRES06_UFS0_MASK GENMASK(1, 0) +#define MDLC_PERE_MSRES06_UFS1_MASK GENMASK(3, 2) + +#define MDLC_HSCN_MPIER (MDLC_HSCN_BASE + 0x110) +#define MDLC_HSCN_MPIMR (MDLC_HSCN_BASE + 0x120) +#define MDLC_HSCN_MPDG00 (MDLC_HSCN_BASE + 0x200) +#define MDLC_HSCN_MPDG01 (MDLC_HSCN_BASE + 0x204) +#define MDLC_HSCN_MPDG02 (MDLC_HSCN_BASE + 0x208) +#define MDLC_HSCN_MPDG03 (MDLC_HSCN_BASE + 0x20c) +#define MDLC_HSCN_MPDG04 (MDLC_HSCN_BASE + 0x210) +#define MDLC_HSCN_MPDG05 (MDLC_HSCN_BASE + 0x214) +#define MDLC_HSCN_MPDG06 (MDLC_HSCN_BASE + 0x218) +#define MDLC_HSCN_MPDGS00 (MDLC_HSCN_BASE + 0x300) +#define MDLC_HSCN_MPDGS01 (MDLC_HSCN_BASE + 0x304) +#define MDLC_HSCN_MPDGS02 (MDLC_HSCN_BASE + 0x308) +#define MDLC_HSCN_MPDGS03 (MDLC_HSCN_BASE + 0x30c) +#define MDLC_HSCN_MPDGS04 (MDLC_HSCN_BASE + 0x310) +#define MDLC_HSCN_MPDGS05 (MDLC_HSCN_BASE + 0x314) +#define MDLC_HSCN_MPDGS06 (MDLC_HSCN_BASE + 0x318) +#define MDLC_HSCN_PKCPROT0 (MDLC_HSCN_BASE + 0xcf0) + +#define MDLC_RT_MPIER (MDLC_RT_BASE + 0x110) +#define MDLC_RT_MPIMR (MDLC_RT_BASE + 0x120) +#define MDLC_RT_MPDG00 (MDLC_RT_BASE + 0x200) +#define MDLC_RT_MPDG01 (MDLC_RT_BASE + 0x204) +#define MDLC_RT_MPDG02 (MDLC_RT_BASE + 0x208) +#define MDLC_RT_MPDG03 (MDLC_RT_BASE + 0x20c) +#define MDLC_RT_MPDG04 (MDLC_RT_BASE + 0x210) +#define MDLC_RT_MPDG05 (MDLC_RT_BASE + 0x214) +#define MDLC_RT_MPDG06 (MDLC_RT_BASE + 0x218) +#define MDLC_RT_MPDG07 (MDLC_RT_BASE + 0x21c) +#define MDLC_RT_MPDG08 (MDLC_RT_BASE + 0x220) +#define MDLC_RT_MPDG09 (MDLC_RT_BASE + 0x224) +#define MDLC_RT_MPDG10 (MDLC_RT_BASE + 0x228) +#define MDLC_RT_MPDG11 (MDLC_RT_BASE + 0x22c) +#define MDLC_RT_MPDGS00 (MDLC_RT_BASE + 0x300) +#define MDLC_RT_MPDGS01 (MDLC_RT_BASE + 0x304) +#define MDLC_RT_MPDGS02 (MDLC_RT_BASE + 0x308) +#define MDLC_RT_MPDGS03 (MDLC_RT_BASE + 0x30c) +#define MDLC_RT_MPDGS04 (MDLC_RT_BASE + 0x310) +#define MDLC_RT_MPDGS05 (MDLC_RT_BASE + 0x314) +#define MDLC_RT_MPDGS06 (MDLC_RT_BASE + 0x318) +#define MDLC_RT_MPDGS07 (MDLC_RT_BASE + 0x31c) +#define MDLC_RT_MPDGS08 (MDLC_RT_BASE + 0x320) +#define MDLC_RT_MPDGS09 (MDLC_RT_BASE + 0x324) +#define MDLC_RT_MPDGS10 (MDLC_RT_BASE + 0x328) +#define MDLC_RT_MPDGS11 (MDLC_RT_BASE + 0x32c) +#define MDLC_RT_MSRES02 (MDLC_RT_BASE + 0x908) +#define MDLC_RT_MSRESS02 (MDLC_RT_BASE + 0x968) +#define MDLC_RT_MSRES03 (MDLC_RT_BASE + 0x90c) +#define MDLC_RT_MSRESS03 (MDLC_RT_BASE + 0x96c) +#define MDLC_RT_MSRES15 (MDLC_RT_BASE + 0x93c) +#define MDLC_RT_MSRESS15 (MDLC_RT_BASE + 0x99c) +#define MDLC_RT_MSRES15_INTAP0_MASK GENMASK(9, 8) +#define MDLC_RT_MSRES15_INTTP_MASK GENMASK(11, 10) +#define MDLC_RT_MSRES15_INTAP1_MASK GENMASK(13, 12) +#define MDLC_RT_PKCPROT0 (MDLC_RT_BASE + 0xcf0) +#define MDLC_RT_PKCPROT1 (MDLC_RT_BASE + 0xcf4) + +/* + * mdlc_wait_for_reset() - Wait for MDLC reset register and reset status register to align + * @res: Reset register + * @stat: Reset status register + */ +static void mdlc_wait_for_reset(const u32 res, const u32 stat) +{ + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (; readl(res) != readl(stat);) + ; +} + +/** + * mdlc_write_msres() - Write MSRES register to release IP from reset + * @prot: Protect register + * @res: Reset register + * @val: Value to set in the masked out bits + */ +static void mdlc_write_msres(const u32 prot, const u32 res, const int val) +{ + writel(PKC_PROT_UNLOCK, prot); + writel(val, res); + writel(PKC_PROT_LOCK, prot); +} + +/** + * mdlc_rmw_msres() - Read-modify-write MSRES register to release IP from reset + * @prot: Protect register + * @res: Reset register + * @mask: Mask in the register to clear + * @val: Value to set in the masked out bits + */ +static void mdlc_rmw_msres(const u32 prot, const u32 res, const u32 mask, const int val) +{ + u32 reg; + + reg = readl(res); + reg &= ~mask; + reg |= field_prep(mask, val); + + mdlc_write_msres(prot, res, reg); +} + +/** + * mdlc_set_reset() - Set IP into reset + * @prot: Protect register + * @res: Reset register + * @stat: Reset register + * @mask: Mask in the register to clear + */ +static void mdlc_set_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) +{ + u32 status; + + mdlc_wait_for_reset(res, stat); + + status = field_get(mask, readl(stat)); + if (status == MDLC_MSRESS_STOP) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_STANDBY); + mdlc_wait_for_reset(res, stat); + status = field_get(mask, readl(stat)); + } + + if (status == MDLC_MSRESS_STANDBY || status == MDLC_MSRESS_RUN) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); + mdlc_wait_for_reset(res, stat); + } +} + +/** + * mdlc_release_reset() - Release IP from reset + * @prot: Protect register + * @res: Reset register + * @stat: Reset register + * @mask: Mask in the register to clear + */ +static void mdlc_release_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) +{ + u32 status; + + mdlc_wait_for_reset(res, stat); + + status = field_get(mask, readl(stat)); + if (status == MDLC_MSRESS_STANDBY) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); + mdlc_wait_for_reset(res, stat); + status = field_get(mask, readl(stat)); + } + + if (status == MDLC_MSRESS_RESET || status == MDLC_MSRESS_STOP) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RUN); + mdlc_wait_for_reset(res, stat); + } +} + +/** + * mldc_mpg_module_run() - Release MPG module from gating + * @prot: Protect register + * @res: Reset register + * @stat: Reset status register + * @ier: Interrupt enable register + * @imr: Interrupt mask register + */ +static void mldc_mpg_module_run(const u32 prot, const u32 res, const u32 stat, + const u32 ier, const u32 imr) +{ + u32 val; + + mdlc_wait_for_reset(res, stat); + + val = readl(stat); + if (val == MDLC_MPG_GATING) { + writel(0, ier); + writel(0, imr); + mdlc_write_msres(prot, res, MDLC_MPG_RESET); + mdlc_wait_for_reset(res, stat); + val = readl(stat); + } + + if (val == MDLC_MPG_RESET || val == MDLC_MPG_RUN) { + writel(0, ier); + writel(0, imr); + mdlc_write_msres(prot, res, MDLC_MPG_RUN); + mdlc_wait_for_reset(res, stat); + val = readl(stat); + } +} + +/** + * mdlc_mpg_start() - Configure MPG module state + */ +static void mdlc_mpg_start(void) +{ + mldc_mpg_module_run(MDLC_PERE_PKCPROT0, MDLC_PERE_MPDG01, MDLC_PERE_MPDGS01, + MDLC_PERE_MPIER, MDLC_PERE_MPIMR); + mldc_mpg_module_run(MDLC_PERE_PKCPROT0, MDLC_PERE_MPDG00, MDLC_PERE_MPDGS00, + MDLC_PERE_MPIER, MDLC_PERE_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG11, MDLC_RT_MPDGS11, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG10, MDLC_RT_MPDGS10, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG09, MDLC_RT_MPDGS09, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG08, MDLC_RT_MPDGS08, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG07, MDLC_RT_MPDGS07, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG06, MDLC_RT_MPDGS06, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG05, MDLC_RT_MPDGS05, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG04, MDLC_RT_MPDGS04, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG03, MDLC_RT_MPDGS03, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG02, MDLC_RT_MPDGS02, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG01, MDLC_RT_MPDGS01, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG00, MDLC_RT_MPDGS00, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + /* Power on RSwitch */ + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG06, MDLC_HSCN_MPDGS06, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG05, MDLC_HSCN_MPDGS05, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG04, MDLC_HSCN_MPDGS04, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG03, MDLC_HSCN_MPDGS03, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG02, MDLC_HSCN_MPDGS02, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG01, MDLC_HSCN_MPDGS01, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG00, MDLC_HSCN_MPDGS00, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); +} + +#define PFC_GP2_BASE 0xc1081000 +#define PFC_GP2_GPSR (PFC_GP2_BASE + 0x40) +#define PFC_GP2_IOINTSEL (PFC_GP2_BASE + 0x110) +#define PFC_GP2_INOUTSEL (PFC_GP2_BASE + 0x114) +#define PFC_GP2_OUTDT (PFC_GP2_BASE + 0x118) +#define PFC_GP2_POSNEG (PFC_GP2_BASE + 0x1a0) +#define PFC_GP2_PIN_AVS0 BIT(21) +#define PFC_GP2_PIN_AVS1 BIT(22) +#define PFC_GP2_PIN_AVS \ + (PFC_GP2_PIN_AVS0 | PFC_GP2_PIN_AVS1) + +#define PFC_GP3_BASE 0xc0800000 +#define PFC_GP3_PULLEN (PFC_GP3_BASE + 0xc0) +#define PFC_GP3_PUDSEL (PFC_GP3_BASE + 0xc4) + +#define PFC_GP5_BASE 0xc0400000 +#define PFC_GROUP_ADDR_MASK GENMASK(31, 11) +#define PFC_GP5_GPSR (PFC_GP5_BASE + 0x40) +#define PFC_GP5_ALTSEL0 (PFC_GP5_BASE + 0x60) +#define PFC_GP5_ALTSEL1 (PFC_GP5_BASE + 0x64) +#define PFC_GP5_ALTSEL2 (PFC_GP5_BASE + 0x68) +#define PFC_GP5_ALTSEL3 (PFC_GP5_BASE + 0x6c) +#define PFC_GP5_PIN_HTX0 BIT(0) +#define PFC_GP5_PIN_HRX0 BIT(1) +#define PFC_GP5_PIN_SCIF_CLK BIT(5) +#define PFC_GP5_PIN_HTX1 BIT(6) +#define PFC_GP5_PIN_HRX1 BIT(7) +#define PFC_GP5_PIN_HSCIF0_HSCIF1 \ + (PFC_GP5_PIN_HTX0 | PFC_GP5_PIN_HRX0 | \ + PFC_GP5_PIN_HTX1 | PFC_GP5_PIN_HRX1) +#define PFC_GP5_ALTSEL_HSCIF0_HSCIF1 \ + (PFC_GP5_PIN_HSCIF0_HSCIF1 | PFC_GP5_PIN_SCIF_CLK) + +/** + * pfc_rmw_reg() - Read-modify-write PFC register + * @reg: Register to write + * @mask: Mask in the register to clear + * @val: Value to set in the masked out bits + */ +static void pfc_rmw_reg(const u32 reg, const u32 mask, const u32 val) +{ + u32 pmmr = reg & PFC_GROUP_ADDR_MASK; + u32 tmp; + + tmp = readl(reg); + tmp &= ~mask; + tmp |= val; + + writel(~tmp, pmmr); + writel(tmp, reg); +} + +/** + * pfc_set_hscif0_hscif1_pinmux() - Set HSCIF0 and HSCIF1 pinmux + * @bd3250k: Set to TRUE if HSCIF configured for 3.25 MBdps + * + * This function configures both HSCIF0 and HSCIF1 pin multiplexing, + * HSCIF0 is used for follow up stages, HSCIF1 is used for IPL console. + */ +static void pfc_set_hscif0_hscif1_pinmux(bool bd3250k) +{ + u32 gpsr_mask = PFC_GP5_PIN_HSCIF0_HSCIF1; + + if (bd3250k) + gpsr_mask |= PFC_GP5_PIN_SCIF_CLK; + + pfc_rmw_reg(PFC_GP5_ALTSEL0, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL1, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL2, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL3, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_GPSR, gpsr_mask, gpsr_mask); +} + +/** + * pfc_set_avs_pinmux() - Set AVS pinmux + */ +static void pfc_set_avs_pinmux(void) +{ + clrbits_le32(PFC_GP2_POSNEG, PFC_GP2_PIN_AVS); + clrbits_le32(PFC_GP2_IOINTSEL, PFC_GP2_PIN_AVS); + setbits_le32(PFC_GP2_OUTDT, PFC_GP2_PIN_AVS); + setbits_le32(PFC_GP2_INOUTSEL, PFC_GP2_PIN_AVS); + pfc_rmw_reg(PFC_GP2_GPSR, PFC_GP2_PIN_AVS, 0); +} + +/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ +#define MFIS_BASE 0xb89e0000 +#define MFIS_WPCNTR (MFIS_BASE + 0x900) +#define MFIS_CODEVALUE 0xacce0000 + +/** + * mfis_unprotect() - Remove MFIS register write protection + */ +static void mfis_unprotect(void) +{ + writel(MFIS_CODEVALUE, MFIS_WPCNTR); +} + +/** + * rsip_write_reg() - Write RSIP control register + * @reg: Register to write + * @val: Value to set in the register + */ +static void rsip_write_reg(const u32 reg, const int val) +{ + for (;;) { + writel(RSIP_CTL_PROT0PCMD_WREN, RSIP_CTL_PROT0PCMD); + writel(val, reg); + writel(~val, reg); + writel(val, reg); + + if (readl(RSIP_CTL_PROT0PS) != RSIP_CTL_PROT0PS_ERR) + break; + } +} + +/** + * rsip_irq_setup() - Configure RSIP interrupts + */ +static void rsip_irq_setup(void) +{ + asm volatile("cpsid i"); + + setbits_le32(RSIP_SHCSR, RSIP_SHCSR_USGFAULTENA | RSIP_SHCSR_BUSFAULTENA | + RSIP_SHCSR_MEMFAULTENA); + + writel(0xffffffff, RSIP_NVIC_ICER_00); + writel(0xffffffff, RSIP_NVIC_ICER_01); + writel(0xffffffff, RSIP_NVIC_ICER_02); + writel(0xffffffff, RSIP_NVIC_ICER_03); + writel(0xffffffff, RSIP_NVIC_ICER_04); + writel(0xffffffff, RSIP_NVIC_ICER_05); + writel(0xffffffff, RSIP_NVIC_ICER_06); + writel(0xffffffff, RSIP_NVIC_ICER_07); + writel(0xffffffff, RSIP_NVIC_ICER_08); + writel(0xffffffff, RSIP_NVIC_ICER_09); + writel(0xffffffff, RSIP_NVIC_ICER_10); + writel(0xffffffff, RSIP_NVIC_ICER_11); + writel(0xffffffff, RSIP_NVIC_ICER_12); + writel(0xffffffff, RSIP_NVIC_ICER_13); + writel(0xffffffff, RSIP_NVIC_ICER_14); + writel(0xffffffff, RSIP_NVIC_ICER_15); + + /* WDT IRQ */ + writel(RSIP_NVIC_ISER_00_SETENA_INTIWDTA0, RSIP_NVIC_ISER_00); + + asm volatile("cpsid i"); +} + +#define RPC_BASE 0xc08c0000 +#define RPC_CMNSR (RPC_BASE + 0x48) +#define RPC_PHYCNT (RPC_BASE + 0x7c) +#define RPC_CMNCR (RPC_BASE + 0x00) +#define RPC_SSLDR (RPC_BASE + 0x04) +#define RPC_DRCR (RPC_BASE + 0x0c) +#define RPC_DRCMR (RPC_BASE + 0x10) +#define RPC_DREAR (RPC_BASE + 0x14) +#define RPC_DROPR (RPC_BASE + 0x18) +#define RPC_DRENR (RPC_BASE + 0x1c) +#define RPC_SMCR (RPC_BASE + 0x20) +#define RPC_SMCMR (RPC_BASE + 0x24) +#define RPC_SMADR (RPC_BASE + 0x28) +#define RPC_SMENR (RPC_BASE + 0x30) +#define RPC_SMWDR0 (RPC_BASE + 0x40) +#define RPC_DRDMCR (RPC_BASE + 0x58) +#define RPC_DRDRENR (RPC_BASE + 0x5c) +#define RPC_PHYOFFSET1 (RPC_BASE + 0x80) +#define RPC_PHYINT (RPC_BASE + 0x88) +#define RPC_SEC_CONF (RPC_BASE + 0xb8) + +#define RPC_CMNSR_TEND BIT(0) + +#define RPC_CMNCR_MD BIT(31) +#define RPC_CMNCR_MOIIO3(n) FIELD_PREP(GENMASK(23, 22), (n)) +#define RPC_CMNCR_MOIIO2(n) FIELD_PREP(GENMASK(21, 20), (n)) +#define RPC_CMNCR_MOIIO1(n) FIELD_PREP(GENMASK(19, 18), (n)) +#define RPC_CMNCR_MOIIO0(n) FIELD_PREP(GENMASK(17, 16), (n)) +#define RPC_CMNCR_IO0FV(n) FIELD_PREP(GENMASK(9, 8), (n)) +#define RPC_CMNCR_BSZ(n) FIELD_PREP(GENMASK(1, 0), (n)) + +#define RPC_SSLDR_SPNDL_MASK GENMASK(18, 16) +#define RPC_SSLDR_SPNDL_SPCLK_2_CYCLES FIELD_PREP(RPC_SSLDR_SPNDL_MASK, 1) +#define RPC_SSLDR_SLNDL_MASK GENMASK(10, 8) +#define RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES FIELD_PREP(RPC_SSLDR_SLNDL_MASK, 4) +#define RPC_SSLDR_SCKDL_MASK GENMASK(2, 0) +#define RPC_SSLDR_SCKDL_SPCLK_2_CYCLES FIELD_PREP(RPC_SSLDR_SCKDL_MASK, 1) + +#define RPC_DRCR_SSLN BIT(24) +#define RPC_DRCR_RBURST_MASK GENMASK(20, 16) +#define RPC_DRCR_RCF_READ_CACHE_CLEARE BIT(9) +#define RPC_DRCR_RBE BIT(8) + +#define RPC_DRCMR_CMD_MASK GENMASK(23, 16) +#define RPC_DRCMR_CMD_HYPERFLASH_READ FIELD_PREP(RPC_DRCMR_CMD_MASK, 0xA0) + +#define RPC_DREAR_EAV_MASK GENMASK(23, 16) +#define RPC_DREAR_EAC_MASK GENMASK(2, 0) + +#define RPC_DRENR_DME BIT(15) +#define RPC_DRENR_CDE BIT(14) +#define RPC_DRENR_OCDE BIT(12) +#define RPC_DRENR_ADE_MASK GENMASK(11, 8) +#define RPC_DRENR_ADE_HYPERFLASH FIELD_PREP(RPC_DRENR_ADE_MASK, 4) +#define RPC_DRENR_OPDE_MASK GENMASK(7, 4) + +#define RPC_DRDMCR_DMCYC_MASK GENMASK(4, 0) +#define RPC_DRDMCR_DMCYC_15_CYCLE FIELD_PREP(RPC_DRDMCR_DMCYC_MASK, 0xe) + +#define RPC_DRDRENR_HYPE_MASK GENMASK(14, 12) +#define RPC_DRDRENR_HYPE_HYPERFLASH FIELD_PREP(RPC_DRDRENR_HYPE_MASK, 5) +#define RPC_DRDRENR_ADDRE BIT(8) +#define RPC_DRDRENR_OPDRE BIT(4) +#define RPC_DRDRENR_DRDRE BIT(0) + +#define RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK 0x08038000 + +#define RPC_PHYCNT_HS BIT(18) +#define RPC_PHYCNT_PHYMEM_MASK GENMASK(1, 0) +#define RPC_PHYCNT_PHYMEM_HYPERFLASH FIELD_PREP(RPC_PHYCNT_PHYMEM_MASK, 3) + +/** + * rpc_safe_setup() - Configure RPC with safe static settings + */ +static void rpc_safe_setup(void) +{ + writel(RPC_CMNCR_MOIIO3(2) | RPC_CMNCR_MOIIO2(2) | RPC_CMNCR_MOIIO1(2) | + RPC_CMNCR_MOIIO0(2) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(1) | + 0x01007000, RPC_CMNCR); + writel(RPC_SSLDR_SPNDL_SPCLK_2_CYCLES | RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES | + RPC_SSLDR_SCKDL_SPCLK_2_CYCLES, RPC_SSLDR); + writel(RPC_DRCR_RBURST_MASK | RPC_DRCR_RBE, RPC_DRCR); + writel(RPC_DRCMR_CMD_HYPERFLASH_READ, RPC_DRCMR); + writel(0, RPC_DREAR); + writel(RPC_DRENR_ADE_HYPERFLASH | 0xa222d000, RPC_DRENR); + writel(0, RPC_SMCR); + writel(0, RPC_SMCMR); + writel(0, RPC_SMADR); + writel(BIT(14), RPC_SMENR); + writel(0, RPC_SMWDR0); + writel(RPC_CMNSR_TEND, RPC_CMNSR); + writel(RPC_DRDMCR_DMCYC_15_CYCLE, RPC_DRDMCR); + writel(RPC_DRDRENR_HYPE_HYPERFLASH | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE, + RPC_DRDRENR); + writel(0x08078263, RPC_PHYCNT); + writel(0x21511144, RPC_PHYOFFSET1); + writel(0x07070002, RPC_PHYINT); + writel(0x00000155, RPC_SEC_CONF); + writel(0x11, CLK_CONTROL_RPCCKCR); + writel(0x10100, PFC_GP3_PULLEN); + writel(0x10100, PFC_GP3_PUDSEL); +} + +/** + * rpc_boot_setup() - Configure RPC after boot from HF + */ +static void rpc_boot_setup(void) +{ + clrsetbits_le32(RPC_PHYCNT, + RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK | RPC_PHYCNT_HS | + RPC_PHYCNT_PHYMEM_MASK, + RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK | + RPC_PHYCNT_HS | RPC_PHYCNT_PHYMEM_HYPERFLASH); + + clrsetbits_le32(RPC_CMNCR, + RPC_CMNCR_MD | + RPC_CMNCR_MOIIO3(3) | RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO1(3) | + RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(3), + RPC_CMNCR_MOIIO3(2) | RPC_CMNCR_MOIIO2(2) | RPC_CMNCR_MOIIO1(2) | + RPC_CMNCR_MOIIO0(2) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(1)); + + clrsetbits_le32(RPC_SSLDR, + RPC_SSLDR_SPNDL_MASK | RPC_SSLDR_SLNDL_MASK | RPC_SSLDR_SCKDL_MASK, + RPC_SSLDR_SPNDL_SPCLK_2_CYCLES | RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES | + RPC_SSLDR_SCKDL_SPCLK_2_CYCLES); + + clrsetbits_le32(RPC_DRCR, + RPC_DRCR_SSLN | RPC_DRCR_RBURST_MASK | RPC_DRCR_RBE, + RPC_DRCR_SSLN | RPC_DRCR_RBURST_MASK | + RPC_DRCR_RCF_READ_CACHE_CLEARE | RPC_DRCR_RBE); + readl(RPC_DRCR); /* Dummy readback */ + + clrsetbits_le32(RPC_DRCMR, RPC_DRCMR_CMD_MASK, RPC_DRCMR_CMD_HYPERFLASH_READ); + + clrbits_le32(RPC_DREAR, RPC_DREAR_EAV_MASK | RPC_DREAR_EAC_MASK); + + writel(0, RPC_DROPR); + + clrsetbits_le32(RPC_DRENR, + RPC_DRENR_DME | RPC_DRENR_CDE | RPC_DRENR_OCDE | + RPC_DRENR_ADE_MASK | RPC_DRENR_OPDE_MASK, + RPC_DRENR_DME | RPC_DRENR_CDE | RPC_DRENR_OCDE | + RPC_DRENR_ADE_HYPERFLASH); + + clrsetbits_le32(RPC_DRDMCR, RPC_DRDMCR_DMCYC_MASK, RPC_DRDMCR_DMCYC_15_CYCLE); + + clrsetbits_le32(RPC_DRDRENR, + RPC_DRDRENR_HYPE_MASK | RPC_DRDRENR_ADDRE | + RPC_DRDRENR_OPDRE | RPC_DRDRENR_DRDRE, + RPC_DRDRENR_HYPE_HYPERFLASH | RPC_DRDRENR_ADDRE | + RPC_DRDRENR_DRDRE); +} + +/** + * rpc_setup() - Configure RPC + */ +static void rpc_setup(void) +{ + const u32 boot = field_get(SYSSS_MODE1_BOOTMODE_MASK, sysss_read_modemr()); + + if (boot != SYSSS_MODE1_BOOTMODE_HF_DMA) { + /* Not booted from HF, this may be SCIF loader, use safe setup. */ + rpc_safe_setup(); + return; + } + + /* Wait for any outstanding transfer to end. */ + /* This can not use readl_poll_timeout(), timer is not available yet. */ + while (!(readl(RPC_CMNSR) & RPC_CMNSR_TEND)) + ; + + /* Tristate IO */ + setbits_le32(RPC_CMNCR, RPC_CMNCR_MOIIO3(3) | RPC_CMNCR_MOIIO2(3) | + RPC_CMNCR_MOIIO1(3) | RPC_CMNCR_MOIIO0(3)); + + /* Set 160 MHz RPC HF clock */ + clrsetbits_le32(CLK_CONTROL_RPCCKCR, + CLK_CONTROL_RPCCKCR_CKSTP1 | CLK_CONTROL_RPCCKCR_RPCFC_MASK, + 0x11); + + rpc_boot_setup(); +} + +#define AXMM10_ADSPLCR0_CTRL 0xe9a07100 +#define AXMM10_ADSPLCR1_CTRL 0xe9a07104 +#define AXMM11_ADSPLCR0_CTRL 0xe9a07150 +#define AXMM11_ADSPLCR1_CTRL 0xe9a07154 + +/** + * axi_qos_init() - Configure AXI bus QoS + */ +static void axi_qos_init(void) +{ + writel(0x00011d0c, AXMM10_ADSPLCR0_CTRL); + writel(0x0000ffff, AXMM10_ADSPLCR1_CTRL); + writel(0x00011d0c, AXMM11_ADSPLCR0_CTRL); + writel(0x0000ffff, AXMM11_ADSPLCR1_CTRL); + dsb(); +} + +/** + * load_perm_table() - Load shared table into SRAM and hardware + * @dstaddr: SRAM destination address + * @dstsize: SRAM destination area size + * @listtable: Table of registers to write at offset 2i + * @listsize: Size of table of registers + * @listval: Value to write at offset 2i+1 + */ +static void load_perm_table(const u32 dstaddr, const u32 dstsize, + const u32 *listtable, const u32 listsize, + const u32 listval) +{ + /* + * The addresses in range 0x08000000..0x1fffffff are + * incremented by 0xa0000000 . + */ + u32 *dmabuf = (u32 *)(dstaddr + 0xa0000000); + u32 reg, rv; + int i; + + /* Place shared bus access permissions configuration table into SRAM */ + for (i = 0; i < dstsize / (2 * sizeof(u32)); i++) { + if (i >= listsize) { + dmabuf[2 * i] = 0; + dmabuf[(2 * i) + 1] = 0; + continue; + } + + dmabuf[2 * i] = listtable[i]; + dmabuf[(2 * i) + 1] = listval; + + /* + * The addresses in range 0x08000000..0x1fffffff are + * incremented by 0xa0000000 . + */ + reg = listtable[i]; + if (reg > 0x08000000 && reg < 0x20000000) + reg += 0xa0000000; + writel(listval, reg); + } + + /* Validate hardware write. */ + for (i = 0; i < listsize; i++) { + reg = listtable[i]; + if (reg > 0x08000000 && reg < 0x20000000) + reg += 0xa0000000; + rv = readl(reg); + if (rv == listval) + continue; + printf("RG[%d] = 0x%x / expected 0x%x\n", i, rv, listval); + } +} + +/** + * load_perm_tables() - Load shared tables into SRAM and hardware + */ +static void load_perm_tables(void) +{ + load_perm_table(RGIDM_SHARED_ADDR, RGIDM_SHARED_SIZE, + rgidm_register_list, ARRAY_SIZE(rgidm_register_list), 0); + load_perm_table(SEC_MODID_SHARED_ADDR, SEC_MODID_SHARED_SIZE, + sec_modid_register_list, ARRAY_SIZE(sec_modid_register_list), 0xffff); + load_perm_table(RGIDR_SHARED_ADDR, RGIDR_SHARED_SIZE, + rgidr_register_list, ARRAY_SIZE(rgidr_register_list), 1); + load_perm_table(RGIDW_SHARED_ADDR, RGIDW_SHARED_SIZE, + rgidw_register_list, ARRAY_SIZE(rgidw_register_list), 1); + + /* Override Region ID secure group settings */ + writel(0xffffffff, 0xc0983820); + writel(0xffffffff, 0xc0983828); + + writel(0xffffffff, 0xec603828); + writel(0xffffffff, 0xec60382c); + writel(0xffffffff, 0xec603830); + writel(0xffffffff, 0xec603834); + writel(0xffffffff, 0xec603838); + writel(0xffffffff, 0xec60383c); + + writel(0xffffffff, 0xc9d03880); + writel(0xffffffff, 0xc9d03884); + + /* + * The addresses in range 0x08000000..0x1fffffff + * are incremented by 0xa0000000 + */ + writel(0xffffffff, 0xba80383c); + writel(0xffffffff, 0xba803840); + writel(0xffffffff, 0xba803848); + writel(0xffffffff, 0xba80384c); + writel(0xffffffff, 0xba803974); + + writel(0xffffffff, 0xde803804); + writel(0xffffffff, 0xde803808); + writel(0xffffffff, 0xde803810); + writel(0xffffffff, 0xde803814); + writel(0xffffffff, 0xde803838); + writel(0xffffffff, 0xde80383c); + writel(0xffffffff, 0xde803840); + writel(0xffffffff, 0xde803844); + + writel(0xffffffff, 0xc1283808); + + writel(0xffffffff, 0xe9a08000); + writel(0xffffffff, 0xe9a081fc); + writel(0xffffffff, 0xe9a08200); + writel(0xffffffff, 0xe9a081fc); +} + +#define SCP_STCM_BASE 0xc1000000 +#define SCP_BASE 0xc1340000 +#define SCP_CFGVECTABLE (SCP_BASE + 0x0) +#define SCP_CFGNSSTCALIB (SCP_BASE + 0x10) +#define SCP_CPUWAIT (SCP_BASE + 0x30) +#define SCP_CFGNSSTCALIB_13_3MHZ 0x010040f0 +#define SCP_CPUWAIT_WAIT BIT(0) + +/** + * scp_initialize() - Initialize SCP + * + * Put SCP into reset, configure SCP entry point address and systick timer, + * release SCP from reset, and zero out SCP STCM regions. + */ +static void scp_initialize(void) +{ + u32 addr; + + mdlc_set_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, + MDLC_SCP_MSRES02_SCP_MASK); + + writel(SCP_STCM_BASE, SCP_CFGVECTABLE); + writel(SCP_CFGNSSTCALIB_13_3MHZ, SCP_CFGNSSTCALIB); + setbits_le32(SCP_CPUWAIT, SCP_CPUWAIT_WAIT); + + mdlc_release_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, + MDLC_SCP_MSRES02_SCP_MASK); + + /* Fill zero to SCP STCM regions 0 ... 27 */ + for (addr = SCP_STCM_BASE; addr < 0xc1061b00; addr += 8) + writeq(0, addr); + + asm volatile("dsb sy"); +} + +#define GIC720AE_GICR_PWRR(cpu) \ + (GICR_BASE + 0x24 + ((cpu) * 0x40000)) + +#define GIC720AE_GICD_IVIEWR(num) \ + (GICD_BASE + 0xf600 + ((num) * 0x4)) +#define GIC720AE_GICD_IVIEWRE(num) \ + (GICD_BASE + 0xf800 + ((num) * 0x4)) +#define GIC720AE_GICR_TYPER(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x8) +#define GIC720AE_GICR_VIEWR(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x2c) +#define GIC720AE_GICR_MPIDR(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x100) +#define GIC720AE_GICR_TYPER_AFF_MASK GENMASK_ULL(63, 32) + +#define CA_CORE_MAX 32 + +/** + * gic720ae_init() - GIC720AE initialization + */ +static void gic720ae_init(void) +{ + u64 val; + int i; + + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTAP0_MASK); + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTTP_MASK); + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTAP1_MASK); + + for (i = 0; i < CA_CORE_MAX; i++) + writel(BIT(1), GIC720AE_GICR_PWRR(i)); + + for (i = 0; i < CA_CORE_MAX; i++) { + val = readq(GIC720AE_GICR_TYPER(i)) & GIC720AE_GICR_TYPER_AFF_MASK; + writel((u32)(val >> 32U), GIC720AE_GICR_MPIDR(i)); + } + + writel(0x3f, GICD_BASE); /* CTRL register */ + + for (i = 2; i <= 61; i++) /* From IVIEWR min..max */ + writel(0x55555555, GIC720AE_GICD_IVIEWR(i)); + + for (i = 0; i <= 63; i++) /* From IVIEWRE min..max */ + writel(0x55555555, GIC720AE_GICD_IVIEWRE(i)); + + for (i = 0; i < CA_CORE_MAX; i++) + writel(1, GIC720AE_GICR_VIEWR(i)); /* View 1 */ +} + +/** + * mach_cpu_init() - Initialize hardware and start other cores + */ +int mach_cpu_init(void) +{ + mfis_unprotect(); + pfc_set_avs_pinmux(); + mdlc_mpg_start(); + clk_control_set_pll(); + rsip_irq_setup(); + rpc_setup(); + axi_qos_init(); + load_perm_tables(); + gic720ae_init(); + + /* Release SCP from reset */ + scp_initialize(); + + return 0; +} + +int board_early_init_r(void) +{ + u32 remaptmp = readl(RSIP_CTL_ESICREMAP0); + struct udevice *dev; + int ret; + + /* Remap DDR PHY during DRAM init. */ + rsip_write_reg(RSIP_CTL_ESICREMAP0, 0xe0000000); + + /* Start DBSC5 */ + ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e9800000", &dev); + if (ret) + printf("DBSC5 init failed: %d\n", ret); + + /* Restore remapping. */ + rsip_write_reg(RSIP_CTL_ESICREMAP0, remaptmp); + + return 0; +} + +/** + * board_debug_uart_init() - Initialize all HSCIF + */ +void board_debug_uart_init(void) +{ + const u32 baud = field_get(SYSSS_MODE1_BAUDRATE_MASK, sysss_read_modemr()); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_0_CR2, + CLK_CONTROL_PLL01_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_1_CR2, + CLK_CONTROL_PLL01_1_SCR); + + mdlc_release_reset(MDLC_PERW_PKCPROT1, MDLC_PERW_MSRES05, MDLC_PERW_MSRESS05, + MDLC_PERW_MSRES05_HSCIF0_MASK); + mdlc_release_reset(MDLC_PERW_PKCPROT1, MDLC_PERW_MSRES05, MDLC_PERW_MSRESS05, + MDLC_PERW_MSRES05_HSCIF1_MASK); + + pfc_set_hscif0_hscif1_pinmux(baud == SYSSS_MODE1_BAUDRATE_3250000); +} + +/** + * board_init() - Board specific initialization + */ +int board_init(void) +{ + /* Allow WDT reset */ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK); + + return 0; +} + +/** + * arm_reserve_mmu() - Reserve space for MMU tables + */ +int arm_reserve_mmu(void) +{ + /* Reserve space for MMU tables just above stack in STCM */ + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = CONFIG_CUSTOM_SYS_INIT_SP_ADDR; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + return 0; +} + +/** + * reset_cpu() - Reset this CPU core + */ +void __weak reset_cpu(void) +{ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + writel(0x1, RST_SWSRES1A); +} + +/** + * lmb_arch_add_memory() - Add memory to LMB + * + * Add the window to a subset of 32bit DRAM are into LMB, + * to make it possible to TFTP into it. + */ +void lmb_arch_add_memory(void) +{ + lmb_add(0x60000000, 0x40000000); +} diff --git a/board/renesas/common/gen5-cm33.h b/board/renesas/common/gen5-cm33.h new file mode 100644 index 00000000000..2dfb0b06cf7 --- /dev/null +++ b/board/renesas/common/gen5-cm33.h @@ -0,0 +1,2001 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +#ifndef __GEN5_CM33_H__ +#define __GEN5_CM33_H__ + +#define RGIDM_SHARED_ADDR 0x1001c000 +#define RGIDM_SHARED_SIZE 0x1000 +#define SEC_MODID_SHARED_ADDR 0x1001d000 +#define SEC_MODID_SHARED_SIZE 0x3000 +#define RGIDR_SHARED_ADDR 0x10020000 +#define RGIDR_SHARED_SIZE 0x8000 +#define RGIDW_SHARED_ADDR 0x10028000 +#define RGIDW_SHARED_SIZE 0x8000 + +static const u32 rgidm_register_list[] = { + 0xec601000, 0xcbf01000, 0xcbf01004, 0xcbf01008, + 0xcbf0100c, 0xcbf01010, 0xcbf01014, 0xcbf01018, + 0xcbf0101c, 0xcbf01020, 0xcbf01024, 0xcbf01028, + 0xcbf0102c, 0xcbf01030, 0xcbf01034, 0xcbf01038, + 0xcbf0103c, 0xcbf01040, 0xcbf01044, 0xcbf01048, + 0xcbf0104c, 0xcbf01050, 0xcbf01054, 0xcbf01058, + 0xcbf0105c, 0xcbf01060, 0xcbf01064, 0xcbf01068, + 0xcbf0106c, 0xcbf01070, 0xcbf01074, 0xcbf01078, + 0xcbf0107c, 0xcbf01080, 0xc9d01000, 0xc9d01004, + 0xc9d01008, 0xc9d0100c, 0xc9d01010, 0xc9d01014, + 0xc9d01018, 0xc9d0101c, 0xc9d01020, 0xc9d01024, + 0xc9d01028, 0xc9d0102c, 0xc9d01030, 0xc9d01034, + 0xc9d01038, 0xc9d0103c, 0xc9d01040, 0xde801000, + 0xde801004, 0xc1a01000, 0xc1a01004, 0xc1a01008, + 0xc1a0100c, 0xc1a01010, 0xc1a01014, 0xc1a01018, + 0xc1a0101c, 0xc1a01020, 0xc1a01024, 0xc1e01000, + 0xc1e01004, 0xc1e01008, 0xc1e0100c, 0xc1e01010, + 0xc1e01014, 0xc1e01018, 0xc1e0101c, 0xc1e01020, + 0xc1e01024, 0xe9a01000, 0xe9a01004, 0xe9a01008, + 0xe9a0100c, 0xd2f01000, 0xd2f01004, 0xd2f01008, + 0xd2f0100c, 0xd2f01010, 0xd2f01014, 0xd2f01018, + 0xd2f0101c, 0xd2f01020, 0xd2f01024, 0xd2f01028, + 0xd2f0102c, 0xd2f01030, 0xd2f01034, 0xd2f01038, + 0xd6f01000, 0xd6f01004, 0xd6f01008, 0xd6f0100c, + 0xd6f01010, 0xd6f01014, 0xd6f01018, 0xd6f0101c, + 0xd6f01020, 0xd6f01024, 0xd6f01028, 0xd6f0102c, + 0xd6f01030, 0xd6f01034, 0xd6f01038, 0xc0981000, + 0xc0981004, 0xc0981008, 0xc098100c, 0xc0581000, + 0xcb401000, 0xcb401004, 0xcb401008, 0xcb40100c, + 0xcb401010, 0xcb401014, 0x1a801000, 0x1a801004, + 0x1a801008, 0x1a80100c, 0x1a801010, 0x1a801014, + 0x1a801018, 0x1a80101c, 0x1a801020, 0x1a801024, + 0x1a801028, 0x1a80102c, 0x1a801030, 0x1a801034, + 0x1a801038, 0x1a80103c, 0x1a801040, 0x1a801044, + 0x1a801048, 0x1a80104c, 0x1a801050, 0x1a801054, + 0x1a801058, 0x1a80105c, 0x1a801060, 0x1a801064, + 0x1a801068, 0x1a80106c, 0x1a801070, 0x1a801074, + 0x1a801078, 0x1a80107c, 0x1a801080, 0x1a801084, + 0x1a801088, 0x1a80108c, 0x1a801090, 0x1a801094, + 0x18b41000, 0x18b41004, 0x18b41008, 0x18b4100c, + 0xc1281000, 0xc1281004, 0xc1281008, 0xc128100c, + 0xc1281010, 0xc1281014, 0xc5801000, 0xc5801004, + 0xc5801008, 0xc580100c, 0xc5801010, 0xc5801014, + 0xc5801018, 0xc580101c, 0xc5801020, 0xc5801024, + 0xc5801028, 0xc580102c, 0xc5801030, 0xc5801034, + 0xc5801038, 0xc580103c, 0xc5801040, 0xc5801044, + 0xc5801048, 0xc580104c, 0xc5801050, 0xc5801054, + 0xc5801058, 0xc580105c, 0xc5801060, 0xc5801064, + 0xc5801068, 0xc580106c, 0xc5801070, 0xc5801074, + 0xc5801078, 0xc580107c, 0xc5801080, 0xc5801084, + 0xc5801088, 0xc580108c, 0xc5801090, 0xc5801094, + 0xc5801098, 0xc580109c, 0xc58010a0, 0xc58010a4, + 0xc58010a8, 0xc58010ac, 0xc58010b0, 0xc58010b4, + 0xc58010b8, 0xc58010bc, 0xc58010c0, 0xc58010c4, + 0xc58010c8, 0xc58010cc, 0xc58010d0, 0xc58010d4, + 0xc58010d8, 0xc58010dc, 0xc58010e0, 0xc3021000, + 0xc3021004, 0xc3021008, 0xc302100c, 0xc3021010, + 0xc3021014, 0xc3421000, 0xc3421004, 0xc3421008, + 0xc342100c, 0xc3421010, 0xc3421014 +}; + +static const u32 rgidr_register_list[] = { + 0xe8022000, 0xe8022004, 0xe8022008, 0xe802200c, + 0xe8022010, 0xe8022014, 0xe8022018, 0xe802201c, + 0xe8022020, 0xe8022024, 0xe8022028, 0xe802202c, + 0xe8022030, 0xe8022034, 0xe8022038, 0xe802203c, + 0xe8022040, 0xe8022044, 0xe8022048, 0xe802204c, + 0xe80a2000, 0xe80a2004, 0xe80a2008, 0xe80a200c, + 0xe80a2010, 0xe80a2014, 0xe80a2018, 0xe80a201c, + 0xe80a2020, 0xe80a2024, 0xe80a2028, 0xe80a202c, + 0xe80a2030, 0xe80a2034, 0xe80a2038, 0xe80a203c, + 0xe80a2040, 0xe80a2044, 0xe80a2048, 0xe80a204c, + 0xe8122000, 0xe8122004, 0xe8122008, 0xe812200c, + 0xe8122010, 0xe8122014, 0xe8122018, 0xe812201c, + 0xe8122020, 0xe8122024, 0xe8122028, 0xe812202c, + 0xe8122030, 0xe8122034, 0xe8122038, 0xe812203c, + 0xe8122040, 0xe8122044, 0xe8122048, 0xe812204c, + 0xe81a2000, 0xe81a2004, 0xe81a2008, 0xe81a200c, + 0xe81a2010, 0xe81a2014, 0xe81a2018, 0xe81a201c, + 0xe81a2020, 0xe81a2024, 0xe81a2028, 0xe81a202c, + 0xe81a2030, 0xe81a2034, 0xe81a2038, 0xe81a203c, + 0xe81a2040, 0xe81a2044, 0xe81a2048, 0xe81a204c, + 0xe8222000, 0xe8222004, 0xe8222008, 0xe822200c, + 0xe8222010, 0xe8222014, 0xe8222018, 0xe822201c, + 0xe8222020, 0xe8222024, 0xe8222028, 0xe822202c, + 0xe8222030, 0xe8222034, 0xe8222038, 0xe822203c, + 0xe8222040, 0xe8222044, 0xe8222048, 0xe822204c, + 0xe82a2000, 0xe82a2004, 0xe82a2008, 0xe82a200c, + 0xe82a2010, 0xe82a2014, 0xe82a2018, 0xe82a201c, + 0xe82a2020, 0xe82a2024, 0xe82a2028, 0xe82a202c, + 0xe82a2030, 0xe82a2034, 0xe82a2038, 0xe82a203c, + 0xe82a2040, 0xe82a2044, 0xe82a2048, 0xe82a204c, + 0xe8322000, 0xe8322004, 0xe8322008, 0xe832200c, + 0xe8322010, 0xe8322014, 0xe8322018, 0xe832201c, + 0xe8322020, 0xe8322024, 0xe8322028, 0xe832202c, + 0xe8322030, 0xe8322034, 0xe8322038, 0xe832203c, + 0xe8322040, 0xe8322044, 0xe8322048, 0xe832204c, + 0xe83a2000, 0xe83a2004, 0xe83a2008, 0xe83a200c, + 0xe83a2010, 0xe83a2014, 0xe83a2018, 0xe83a201c, + 0xe83a2020, 0xe83a2024, 0xe83a2028, 0xe83a202c, + 0xe83a2030, 0xe83a2034, 0xe83a2038, 0xe83a203c, + 0xe83a2040, 0xe83a2044, 0xe83a2048, 0xe83a204c, + 0xc0622000, 0xc0622004, 0xc0622008, 0xc062200c, + 0xc0622010, 0xc0622014, 0xc0622018, 0xc062201c, + 0xc0622020, 0xc0622024, 0xc0622028, 0xc062202c, + 0xc0622030, 0xc0622034, 0xc0622038, 0xc062203c, + 0xc0622040, 0xc0622044, 0xc0622048, 0xc062204c, + 0xc0622050, 0xc0622054, 0xc0762000, 0xc0762004, + 0xc0762008, 0xc076200c, 0xc0762010, 0xc0762014, + 0xc0762018, 0xc076201c, 0xc0762020, 0xc0762024, + 0xc0762028, 0xc076202c, 0xc0762030, 0xc0762034, + 0xc0762038, 0xc076203c, 0xc0762040, 0xc0762044, + 0xc0762048, 0xc076204c, 0xc0762050, 0xc0762054, + 0xc0762058, 0xc076205c, 0xc0762060, 0xc0762064, + 0xc0762068, 0xc076206c, 0xc0762070, 0xc0762074, + 0xc0762078, 0xc076207c, 0xc0762080, 0xc0762084, + 0xc0762088, 0xc076208c, 0xc0762090, 0xc0762094, + 0xc0762098, 0xc076209c, 0xc07620a0, 0xc07620a4, + 0xc07620a8, 0xc07620ac, 0xc07620b0, 0xc07620b4, + 0xc07620b8, 0xc07620bc, 0xc07620c0, 0xc07620c4, + 0xc07620c8, 0xc07620cc, 0xc07620d0, 0xc07620d4, + 0xc07620d8, 0xc07620dc, 0xc07a2000, 0xc07a2004, + 0xc07a2008, 0xc07a200c, 0xc07a2010, 0xc07a2014, + 0xc07a2018, 0xc07a201c, 0xc07a2020, 0xc07a2024, + 0xc07a2028, 0xc07a202c, 0xc07a2030, 0xc07a2034, + 0xc07a2038, 0xc07a203c, 0xc07a2040, 0xc07a2044, + 0xc07a2048, 0xc07a204c, 0xc07a2050, 0xc07a2054, + 0xc07a2058, 0x1d002000, 0x1d002004, 0x1d002008, + 0x1d00200c, 0x1d002010, 0x1d002014, 0x1d002018, + 0x1d00201c, 0x1d002020, 0x1d002024, 0x1d002028, + 0x1d00202c, 0x1d002030, 0x1d002034, 0x1d002038, + 0x1d00203c, 0x1d002040, 0x1d002044, 0x1d002048, + 0x1d00204c, 0x1d002050, 0x1d002054, 0x1d002058, + 0x1d00205c, 0x1d002060, 0x1d002064, 0x1d002068, + 0x1d00206c, 0x1d002070, 0x1d002074, 0x1d002078, + 0x1d00207c, 0x1d002080, 0x1d002084, 0x1d002088, + 0x1d00208c, 0x1d002090, 0x1d002094, 0x1d002098, + 0x1d00209c, 0x1d0020a0, 0x1d0020a4, 0x1d0020a8, + 0x1d0020ac, 0x1d0020b0, 0x1d0020b4, 0x1d0020b8, + 0xc6702000, 0xc6702004, 0xc6702008, 0xc670200c, + 0xc6702010, 0xc6702014, 0xc6702018, 0xc670201c, + 0xc6702020, 0xc6702024, 0xc6702028, 0xc670202c, + 0xc6702030, 0xc6702034, 0xc6702038, 0xc670203c, + 0xc6702040, 0xc6702044, 0xc6702048, 0xc670204c, + 0xc6702050, 0xc6702054, 0xc6702058, 0xc670205c, + 0xc6702060, 0xc6702064, 0xc6702068, 0xc670206c, + 0xc6702070, 0xc6702074, 0xc6702078, 0xc670207c, + 0xc6702080, 0xc6702084, 0xc6702088, 0xc670208c, + 0xc6702090, 0xc6702094, 0xc6702098, 0xc670209c, + 0xc67020a0, 0xc67020a4, 0xc67020a8, 0xc1742000, + 0xc1742004, 0xc1742008, 0xc174200c, 0xc1742010, + 0xc1742014, 0xc1742018, 0xc174201c, 0xc1742020, + 0xc1742024, 0xc1742028, 0xc174202c, 0xc1742030, + 0xc1742034, 0xc1742038, 0xc174203c, 0xc1742040, + 0xc1742044, 0xc1742048, 0xc174204c, 0xc1742050, + 0xc1742054, 0xec602000, 0xec602004, 0xec602008, + 0xec60200c, 0xec602010, 0xec602014, 0xec602018, + 0xec60201c, 0xec602020, 0xec602024, 0xec602028, + 0xec60202c, 0xec602030, 0xec602034, 0xec602038, + 0xec60203c, 0xec602040, 0xec602044, 0xec602048, + 0xec60204c, 0xec602050, 0xec602054, 0xec602058, + 0xec60205c, 0xec602060, 0xec602064, 0xec602068, + 0xec60206c, 0xec602070, 0xec602074, 0xec602078, + 0xec60207c, 0xec602080, 0xec602084, 0xec602088, + 0xec60208c, 0xec602090, 0xec602094, 0xec602098, + 0xec60209c, 0xec6020a0, 0xec6020a4, 0xec6020a8, + 0xec6020ac, 0xec6020b0, 0xec6020b4, 0xec6020b8, + 0xec6020bc, 0xec6020c0, 0xec6020c4, 0xec6020c8, + 0xec6020cc, 0xec6020d0, 0xec6020d4, 0xec6020d8, + 0xec6020dc, 0xec6020e0, 0xec6020e4, 0xec6020e8, + 0xec6020ec, 0xec6020f0, 0xec6020f4, 0xec6020f8, + 0xec6020fc, 0xec602100, 0xec602104, 0xec602108, + 0xec60210c, 0xec602110, 0xec602114, 0xec602118, + 0xec60211c, 0xec602120, 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0xc68020c8, 0xc68020cc, + 0xc5802000, 0xc5802004, 0xc5802008, 0xc580200c, + 0xc5802010, 0xc5802014, 0xc5802018, 0xc580201c, + 0xc5802020, 0xc5802024, 0xc5802028, 0xc580202c, + 0xc5802030, 0xc5802034, 0xc5802038, 0xc580203c, + 0xc5802040, 0xc5802044, 0xc5802048, 0xc580204c, + 0xc5802050, 0xc5802054, 0xc5802058, 0xc580205c, + 0xc5802060, 0xc5802064, 0xc5802068, 0xc580206c, + 0xc5802070, 0xc5802074, 0xc5802078, 0xc580207c, + 0xc5802080, 0xc5802084, 0xc5802088, 0xc580208c, + 0xc5802090, 0xc5802094, 0xc5802098, 0xc580209c, + 0xc58020a0, 0xc58020a4, 0xc58020a8, 0xc58020ac, + 0xc58020b0, 0xc58020b4, 0xc58020b8, 0xc58020bc, + 0xc58020c0, 0xc58020c4, 0xc58020c8, 0xc58020cc, + 0xc58020d0, 0xc58020d4, 0xc58020d8, 0xc58020dc, + 0xc58020e0, 0xc58020e4, 0xc58020e8, 0xc58020ec, + 0xc58020f0, 0xc58020f4, 0xc58020f8, 0xc58020fc, + 0xc5802100, 0xc5802104, 0xc5802108, 0xc580210c, + 0xc5802110, 0xc5802114, 0xc5802118, 0xc580211c, + 0xc5802120, 0xc5802124, 0xc5802128, 0xc580212c, + 0xc5802130, 0xc5802134, 0xc5802138, 0xc580213c, + 0xc5802140, 0xc5802144, 0xc5802148, 0xc580214c, + 0xc5802150, 0xc5802154, 0xc5802158, 0xc580215c, + 0xc5802160, 0xc5802164, 0xc5802168, 0xc580216c, + 0xc5802170, 0xc5802174, 0xc5802178, 0xc580217c, + 0xc5802180, 0xc5802184, 0xc5802188, 0xc580218c, + 0xc5802190, 0xc5802194, 0xc5802198, 0xc580219c, + 0xc58021a0, 0xc58021a4, 0xc58021a8, 0xc58021ac, + 0xc58021b0, 0xc58021b4, 0xc58021b8, 0xc58021bc, + 0xc58021c0, 0xc58021c4, 0xc58021c8, 0xc58021cc, + 0xc58021d0, 0xc58021d4, 0xc58021d8, 0xc58021dc, + 0xc58021e0, 0xc58021e4, 0xc58021e8, 0xc58021ec, + 0xc58021f0, 0xc58021f4, 0xc58021f8, 0xc58021fc, + 0xc5802200, 0xc5802204, 0xc5802208, 0xc580220c, + 0xc5802210, 0xc5802214, 0xc5802218, 0xc580221c, + 0xc5802220, 0xc5802224, 0xc5802228, 0xc580222c, + 0xc5802230, 0xc5802234, 0xc5802238, 0xc580223c, + 0xc5802240, 0xc5802244, 0xc5802248, 0xc580224c, + 0xc5802250, 0xc5802254, 0xc5802258, 0xc580225c, + 0xc5802260, 0xc5802264, 0xc5802268, 0xc580226c, + 0xc5802270, 0xc5802274, 0xc5802278, 0xc580227c, + 0xc5802280, 0xc5802284, 0xc5802288, 0xc580228c, + 0xc5802290, 0xc5802294, 0xc5802298, 0xc580229c, + 0xc58022a0, 0xc58022a4, 0xc58022a8, 0xc58022ac, + 0xc58022b0, 0xc58022b4, 0xc58022b8, 0xc58022bc, + 0xc58022c0, 0xc58022c4, 0xc58022c8, 0xc58022cc, + 0xc58022d0, 0xc58022d4, 0xc58022d8, 0xc58022dc, + 0xc58022e0, 0xc58022e4, 0xc58022e8, 0xc58022ec, + 0xc58022f0, 0xc58022f4, 0xc58022f8, 0xc58022fc, + 0xc5802300, 0xc5802304, 0xc5802308, 0xc580230c, + 0xc3022000, 0xc3022004, 0xc3022008, 0xc302200c, + 0xc3022010, 0xc3022014, 0xc3022018, 0xc302201c, + 0xc3022020, 0xc3022024, 0xc3022028, 0xc302202c, + 0xc3022030, 0xc3022034, 0xc3022038, 0xc302203c, + 0xc3022040, 0xc3022044, 0xc3022048, 0xc302204c, + 0xc3022050, 0xc3022054, 0xc3022058, 0xc302205c, + 0xc3022060, 0xc3022064, 0xc3022068, 0xc302206c, + 0xc3022070, 0xc3022074, 0xc3022078, 0xc302207c, + 0xc3022080, 0xc3022084, 0xc3022088, 0xc302208c, + 0xc3022090, 0xc3022094, 0xc3022098, 0xc302209c, + 0xc30220a0, 0xc30220a4, 0xc30220a8, 0xc30220ac, + 0xc30220b0, 0xc3422000, 0xc3422004, 0xc3422008, + 0xc342200c, 0xc3422010, 0xc3422014, 0xc3422018, + 0xc342201c, 0xc3422020, 0xc3422024, 0xc3422028, + 0xc342202c, 0xc3422030, 0xc3422034, 0xc3422038, + 0xc342203c, 0xc3422040, 0xc3422044, 0xc3422048, + 0xc342204c, 0xc3422050, 0xc3422054, 0xc3422058, + 0xc342205c, 0xc3422060, 0xc3422064, 0xc3422068, + 0xc342206c, 0xc3422070, 0xc3422074, 0xc3422078, + 0xc342207c, 0xc3422080, 0xc3422084, 0xc3422088, + 0xc342208c, 0xc3422090, 0xc3422094, 0xc3422098, + 0xc342209c, 0xc34220a0, 0xc34220a4, 0xc34220a8, + 0xc34220ac, 0xc34220b0 +}; + +static const u32 rgidw_register_list[] = { + 0xe8026000, 0xe8026004, 0xe8026008, 0xe802600c, + 0xe8026010, 0xe8026014, 0xe8026018, 0xe802601c, + 0xe8026020, 0xe8026024, 0xe8026028, 0xe802602c, + 0xe8026030, 0xe8026034, 0xe8026038, 0xe802603c, + 0xe8026040, 0xe8026044, 0xe8026048, 0xe802604c, + 0xe80a6000, 0xe80a6004, 0xe80a6008, 0xe80a600c, + 0xe80a6010, 0xe80a6014, 0xe80a6018, 0xe80a601c, + 0xe80a6020, 0xe80a6024, 0xe80a6028, 0xe80a602c, + 0xe80a6030, 0xe80a6034, 0xe80a6038, 0xe80a603c, + 0xe80a6040, 0xe80a6044, 0xe80a6048, 0xe80a604c, + 0xe8126000, 0xe8126004, 0xe8126008, 0xe812600c, + 0xe8126010, 0xe8126014, 0xe8126018, 0xe812601c, + 0xe8126020, 0xe8126024, 0xe8126028, 0xe812602c, + 0xe8126030, 0xe8126034, 0xe8126038, 0xe812603c, + 0xe8126040, 0xe8126044, 0xe8126048, 0xe812604c, + 0xe81a6000, 0xe81a6004, 0xe81a6008, 0xe81a600c, + 0xe81a6010, 0xe81a6014, 0xe81a6018, 0xe81a601c, + 0xe81a6020, 0xe81a6024, 0xe81a6028, 0xe81a602c, + 0xe81a6030, 0xe81a6034, 0xe81a6038, 0xe81a603c, + 0xe81a6040, 0xe81a6044, 0xe81a6048, 0xe81a604c, + 0xe8226000, 0xe8226004, 0xe8226008, 0xe822600c, + 0xe8226010, 0xe8226014, 0xe8226018, 0xe822601c, + 0xe8226020, 0xe8226024, 0xe8226028, 0xe822602c, + 0xe8226030, 0xe8226034, 0xe8226038, 0xe822603c, + 0xe8226040, 0xe8226044, 0xe8226048, 0xe822604c, + 0xe82a6000, 0xe82a6004, 0xe82a6008, 0xe82a600c, + 0xe82a6010, 0xe82a6014, 0xe82a6018, 0xe82a601c, + 0xe82a6020, 0xe82a6024, 0xe82a6028, 0xe82a602c, + 0xe82a6030, 0xe82a6034, 0xe82a6038, 0xe82a603c, + 0xe82a6040, 0xe82a6044, 0xe82a6048, 0xe82a604c, + 0xe8326000, 0xe8326004, 0xe8326008, 0xe832600c, + 0xe8326010, 0xe8326014, 0xe8326018, 0xe832601c, + 0xe8326020, 0xe8326024, 0xe8326028, 0xe832602c, + 0xe8326030, 0xe8326034, 0xe8326038, 0xe832603c, + 0xe8326040, 0xe8326044, 0xe8326048, 0xe832604c, + 0xe83a6000, 0xe83a6004, 0xe83a6008, 0xe83a600c, + 0xe83a6010, 0xe83a6014, 0xe83a6018, 0xe83a601c, + 0xe83a6020, 0xe83a6024, 0xe83a6028, 0xe83a602c, + 0xe83a6030, 0xe83a6034, 0xe83a6038, 0xe83a603c, + 0xe83a6040, 0xe83a6044, 0xe83a6048, 0xe83a604c, + 0xc0626000, 0xc0626004, 0xc0626008, 0xc062600c, + 0xc0626010, 0xc0626014, 0xc0626018, 0xc062601c, + 0xc0626020, 0xc0626024, 0xc0626028, 0xc062602c, + 0xc0626030, 0xc0626034, 0xc0626038, 0xc062603c, + 0xc0626040, 0xc0626044, 0xc0626048, 0xc062604c, + 0xc0626050, 0xc0626054, 0xc0766000, 0xc0766004, + 0xc0766008, 0xc076600c, 0xc0766010, 0xc0766014, + 0xc0766018, 0xc076601c, 0xc0766020, 0xc0766024, + 0xc0766028, 0xc076602c, 0xc0766030, 0xc0766034, + 0xc0766038, 0xc076603c, 0xc0766040, 0xc0766044, + 0xc0766048, 0xc076604c, 0xc0766050, 0xc0766054, + 0xc0766058, 0xc076605c, 0xc0766060, 0xc0766064, + 0xc0766068, 0xc076606c, 0xc0766070, 0xc0766074, + 0xc0766078, 0xc076607c, 0xc0766080, 0xc0766084, + 0xc0766088, 0xc076608c, 0xc0766090, 0xc0766094, + 0xc0766098, 0xc076609c, 0xc07660a0, 0xc07660a4, + 0xc07660a8, 0xc07660ac, 0xc07660b0, 0xc07660b4, + 0xc07660b8, 0xc07660bc, 0xc07660c0, 0xc07660c4, + 0xc07660c8, 0xc07660cc, 0xc07660d0, 0xc07660d4, + 0xc07660d8, 0xc07660dc, 0xc07a6000, 0xc07a6004, + 0xc07a6008, 0xc07a600c, 0xc07a6010, 0xc07a6014, + 0xc07a6018, 0xc07a601c, 0xc07a6020, 0xc07a6024, + 0xc07a6028, 0xc07a602c, 0xc07a6030, 0xc07a6034, + 0xc07a6038, 0xc07a603c, 0xc07a6040, 0xc07a6044, + 0xc07a6048, 0xc07a604c, 0xc07a6050, 0xc07a6054, + 0xc07a6058, 0x1d006000, 0x1d006004, 0x1d006008, + 0x1d00600c, 0x1d006010, 0x1d006014, 0x1d006018, + 0x1d00601c, 0x1d006020, 0x1d006024, 0x1d006028, + 0x1d00602c, 0x1d006030, 0x1d006034, 0x1d006038, + 0x1d00603c, 0x1d006040, 0x1d006044, 0x1d006048, + 0x1d00604c, 0x1d006050, 0x1d006054, 0x1d006058, + 0x1d00605c, 0x1d006060, 0x1d006064, 0x1d006068, + 0x1d00606c, 0x1d006070, 0x1d006074, 0x1d006078, + 0x1d00607c, 0x1d006080, 0x1d006084, 0x1d006088, + 0x1d00608c, 0x1d006090, 0x1d006094, 0x1d006098, + 0x1d00609c, 0x1d0060a0, 0x1d0060a4, 0x1d0060a8, + 0x1d0060ac, 0x1d0060b0, 0x1d0060b4, 0x1d0060b8, + 0xc6706000, 0xc6706004, 0xc6706008, 0xc670600c, + 0xc6706010, 0xc6706014, 0xc6706018, 0xc670601c, + 0xc6706020, 0xc6706024, 0xc6706028, 0xc670602c, + 0xc6706030, 0xc6706034, 0xc6706038, 0xc670603c, + 0xc6706040, 0xc6706044, 0xc6706048, 0xc670604c, + 0xc6706050, 0xc6706054, 0xc6706058, 0xc670605c, + 0xc6706060, 0xc6706064, 0xc6706068, 0xc670606c, + 0xc6706070, 0xc6706074, 0xc6706078, 0xc670607c, + 0xc6706080, 0xc6706084, 0xc6706088, 0xc670608c, + 0xc6706090, 0xc6706094, 0xc6706098, 0xc670609c, + 0xc67060a0, 0xc67060a4, 0xc67060a8, 0xc1746000, + 0xc1746004, 0xc1746008, 0xc174600c, 0xc1746010, + 0xc1746014, 0xc1746018, 0xc174601c, 0xc1746020, + 0xc1746024, 0xc1746028, 0xc174602c, 0xc1746030, + 0xc1746034, 0xc1746038, 0xc174603c, 0xc1746040, + 0xc1746044, 0xc1746048, 0xc174604c, 0xc1746050, + 0xc1746054, 0xec606000, 0xec606004, 0xec606008, + 0xec60600c, 0xec606010, 0xec606014, 0xec606018, + 0xec60601c, 0xec606020, 0xec606024, 0xec606028, + 0xec60602c, 0xec606030, 0xec606034, 0xec606038, + 0xec60603c, 0xec606040, 0xec606044, 0xec606048, + 0xec60604c, 0xec606050, 0xec606054, 0xec606058, + 0xec60605c, 0xec606060, 0xec606064, 0xec606068, + 0xec60606c, 0xec606070, 0xec606074, 0xec606078, + 0xec60607c, 0xec606080, 0xec606084, 0xec606088, + 0xec60608c, 0xec606090, 0xec606094, 0xec606098, + 0xec60609c, 0xec6060a0, 0xec6060a4, 0xec6060a8, + 0xec6060ac, 0xec6060b0, 0xec6060b4, 0xec6060b8, + 0xec6060bc, 0xec6060c0, 0xec6060c4, 0xec6060c8, + 0xec6060cc, 0xec6060d0, 0xec6060d4, 0xec6060d8, + 0xec6060dc, 0xec6060e0, 0xec6060e4, 0xec6060e8, + 0xec6060ec, 0xec6060f0, 0xec6060f4, 0xec6060f8, + 0xec6060fc, 0xec606100, 0xec606104, 0xec606108, + 0xec60610c, 0xec606110, 0xec606114, 0xec606118, + 0xec60611c, 0xec606120, 0xec606124, 0xec606128, + 0xec60612c, 0xec606130, 0xec606134, 0xec606138, + 0xec60613c, 0xec606140, 0xec606144, 0xec606148, + 0xec60614c, 0xec606150, 0xec606154, 0xec606158, + 0xec60615c, 0xec606160, 0xec606164, 0xec606168, + 0xec60616c, 0xec606170, 0xec606174, 0xec606178, + 0xec60617c, 0xec606180, 0xec606184, 0xec606188, + 0xec60618c, 0xec606190, 0xec606194, 0xec606198, + 0xec60619c, 0xec6061a0, 0xec6061a4, 0xec6061a8, + 0xec6061ac, 0xec6061b0, 0xec6061b4, 0xec6061b8, + 0xec6061bc, 0xec6061c0, 0xec6061c4, 0xec6061c8, + 0xec6061cc, 0xec6061d0, 0xec6061d4, 0xec6061d8, + 0xec6061dc, 0xec6061e0, 0xec6061e4, 0xec6061e8, + 0xec6061ec, 0xec6061f0, 0xec6061f4, 0xec6061f8, + 0xec6061fc, 0xec606200, 0xec606204, 0xec606208, + 0xec60620c, 0xec606210, 0xec606214, 0xec606218, + 0xec60621c, 0xec606220, 0xec606224, 0xec606228, + 0xec60622c, 0xec606230, 0xec606234, 0xec606238, + 0xec60623c, 0xec606240, 0xec606244, 0xec606248, + 0xec60624c, 0xec606250, 0xec606254, 0xec606258, + 0xec60625c, 0xec606260, 0xec606264, 0xec606268, + 0xec60626c, 0xec606270, 0xec606274, 0xec606278, + 0xec60627c, 0xec606280, 0xec606284, 0xec606288, + 0xec60628c, 0xec606290, 0xec606294, 0xec606298, + 0xec60629c, 0xec6062a0, 0xec6062a4, 0xec6062a8, + 0xec6062ac, 0xec6062b0, 0xec6062b4, 0xec6062b8, + 0xec6062bc, 0xec6062c0, 0xec6062c4, 0xec6062c8, + 0xec6062cc, 0xec6062d0, 0xec6062d4, 0xec6062d8, + 0xec6062dc, 0xec6062e0, 0xec6062e4, 0xec6062e8, + 0xec6062ec, 0xec6062f0, 0xec6062f4, 0xec6062f8, + 0xec6062fc, 0xec606300, 0xec606304, 0xec606308, + 0xec60630c, 0xec606310, 0xec606314, 0xec606318, + 0xec60631c, 0xec606320, 0xec606324, 0xec606328, + 0xec60632c, 0xec606330, 0xec606334, 0xec606338, + 0xec60633c, 0xec606340, 0xec606344, 0xec606348, + 0xec60634c, 0xec606350, 0xec606354, 0xec606358, + 0xec60635c, 0xec606360, 0xec606364, 0xec606368, + 0xec60636c, 0xec606370, 0xec606374, 0xec606378, + 0xec60637c, 0xec606380, 0xec606384, 0xec606388, + 0xec60638c, 0xec606390, 0xec606394, 0xec606398, + 0xec60639c, 0xec6063a0, 0xec6063a4, 0xec6063a8, + 0xec6063ac, 0xec6063b0, 0xec6063b4, 0xec6063b8, + 0xec6063bc, 0xec6063c0, 0xec6063c4, 0xec6063c8, + 0xec6063cc, 0xec6063d0, 0xec6063d4, 0xec6063d8, + 0xec6063dc, 0xec6063e0, 0xec6063e4, 0xec6063e8, + 0xec6063ec, 0xec6063f0, 0xec6063f4, 0xec6063f8, + 0xec6063fc, 0xec606400, 0xec606404, 0xec606408, + 0xec60640c, 0xec606410, 0xec606414, 0xec606418, + 0xec60641c, 0xec606420, 0xec606424, 0xec606428, + 0xec60642c, 0xec606430, 0xec606434, 0xec606438, + 0xec60643c, 0xec606440, 0xec606444, 0xec606448, + 0xec60644c, 0xec606450, 0xec606454, 0xec606458, + 0xec60645c, 0xec606460, 0xec606464, 0xec606468, + 0xec60646c, 0xec606470, 0xec606474, 0xec606478, + 0xec60647c, 0xec606480, 0xec606484, 0xec606488, + 0xec60648c, 0xec606490, 0xec606494, 0xec606498, + 0xec60649c, 0xec6064a0, 0xec6064a4, 0xec6064a8, + 0xec6064ac, 0xec6064b0, 0xec6064b4, 0xec6064b8, + 0xec6064bc, 0xec6064c0, 0xec6064c4, 0xec6064c8, + 0xec6064cc, 0xec6064d0, 0xec6064d4, 0xec6064d8, + 0xec6064dc, 0xec6064e0, 0xec6064e4, 0xec6064e8, + 0xec6064ec, 0xec6064f0, 0xec6064f4, 0xec6064f8, + 0xec6064fc, 0xec606500, 0xec606504, 0xec606508, + 0xec60650c, 0xec606510, 0xec606514, 0xec606518, + 0xec60651c, 0xec606520, 0xec606524, 0xec606528, + 0xec60652c, 0xec606530, 0xec606534, 0xec606538, + 0xec60653c, 0xec606540, 0xec606544, 0xec606548, + 0xec60654c, 0xec606550, 0xec606554, 0xec606558, + 0xec60655c, 0xec606560, 0xec606564, 0xec606568, + 0xec60656c, 0xec606570, 0xec606574, 0xec606578, + 0xec60657c, 0xec606580, 0xec606584, 0xec606588, + 0xec60658c, 0xec606590, 0xec606594, 0xec606598, + 0xec60659c, 0xec6065a0, 0xec6065a4, 0xec6065a8, + 0xec6065ac, 0xec6065b0, 0xec6065b4, 0xec6065b8, + 0xec6065bc, 0xec6065c0, 0xec6065c4, 0xec6065c8, + 0xec6065cc, 0xec6065d0, 0xec6065d4, 0xec6065d8, + 0xec6065dc, 0xec6065e0, 0xec6065e4, 0xec6065e8, + 0xec6065ec, 0xec6065f0, 0xec6065f4, 0xec6065f8, + 0xec6065fc, 0xec606600, 0xec606604, 0xec606608, + 0xec60660c, 0xec606610, 0xec606614, 0xec606618, + 0xec60661c, 0xec606620, 0xec606624, 0xec606628, + 0xec60662c, 0xec606630, 0xec606634, 0xec606638, + 0xec60663c, 0xec606640, 0xec606644, 0xec606648, + 0xec60664c, 0xec606650, 0xec606654, 0xec606658, + 0xec60665c, 0xec606660, 0xec606664, 0xec606668, + 0xec60666c, 0xec606670, 0xec606674, 0xec606678, + 0xec60667c, 0xec606680, 0xec606684, 0xec606688, + 0xec60668c, 0xec606690, 0xec606694, 0xec606698, + 0xec60669c, 0xec6066a0, 0xec6066a4, 0xec6066a8, + 0xec6066ac, 0xec6066b0, 0xec6066b4, 0xec6066b8, + 0xec6066bc, 0xec6066c0, 0xec6066c4, 0xec6066c8, + 0xec6066cc, 0xec6066d0, 0xec6066d4, 0xec6066d8, + 0xec6066dc, 0xec6066e0, 0xec6066e4, 0xec6066e8, + 0xec6066ec, 0xec6066f0, 0xec6066f4, 0xec6066f8, + 0xec6066fc, 0xec606700, 0xec606704, 0xec606708, + 0xec60670c, 0xec606710, 0xec606714, 0xec606718, + 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0x1a80628c, 0x1a806290, 0x1a806294, 0x1a806298, + 0x1a80629c, 0x1a8062a0, 0x1a8062a4, 0x1a8062a8, + 0x1a8062ac, 0x1a8062b0, 0x1a8062b4, 0x1a8062b8, + 0x1a8062bc, 0x1a8062c0, 0x1a8062c4, 0x1a8062c8, + 0x1a8062cc, 0x1a8062d0, 0x1a8062d4, 0x1a8062d8, + 0x1a8062dc, 0x1a8062e0, 0x1a8062e4, 0x1a8062e8, + 0x1a8062ec, 0x1a8062f0, 0x1a8062f4, 0x1a8062f8, + 0x1a8062fc, 0x1a806300, 0x1a806304, 0x1a806308, + 0x1a80630c, 0x1a806310, 0x1a806314, 0x1a806318, + 0x1a80631c, 0x1a806320, 0x1a806324, 0x1a806328, + 0x1a80632c, 0x1a806330, 0x1a806334, 0x1a806338, + 0x1a80633c, 0x1a806340, 0x1a806344, 0x1a806348, + 0x1a80634c, 0x1a806350, 0x1a806354, 0x1a806358, + 0x1a80635c, 0x1a806360, 0x1a806364, 0x1a806368, + 0x1a80636c, 0x1a806370, 0x1a806374, 0x1a806378, + 0x1a80637c, 0x1a806380, 0x1a806384, 0x1a806388, + 0x1a80638c, 0x1a806390, 0x1a806394, 0x1a806398, + 0x1a80639c, 0x1a8063a0, 0x1a8063a4, 0x1a8063a8, + 0x1a8063ac, 0x1a8063b0, 0x1a8063b4, 0x1a8063b8, + 0x1a8063bc, 0x1a8063c0, 0x1a8063c4, 0x1a8063c8, + 0x1a8063cc, 0x1a8063d0, 0x1a8063d4, 0x1a8063d8, + 0x1a8063dc, 0x1a8063e0, 0x1a8063e4, 0x1a8063e8, + 0x1a8063ec, 0x1a8063f0, 0x1a8063f4, 0x1a8063f8, + 0x1a8063fc, 0x1a806400, 0x1a806404, 0x1a806408, + 0x1a80640c, 0x1a806410, 0x1a806414, 0x1a806418, + 0x1a80641c, 0x1a806420, 0x1a806424, 0x1a806428, + 0x1a80642c, 0x1a806430, 0x1a806434, 0x1a806438, + 0x1a80643c, 0x1a806440, 0x1a806444, 0x1a806448, + 0x1a80644c, 0x1a806450, 0x1a806454, 0x1a806458, + 0x1a80645c, 0x1a806460, 0x1a806464, 0x1a806468, + 0x1a80646c, 0x1a806470, 0x1a806474, 0x1a806478, + 0x1a80647c, 0x1a806480, 0x1a806484, 0x1a806488, + 0x1a80648c, 0x1a806490, 0x1a806494, 0x1a806498, + 0x1a80649c, 0x1a8064a0, 0x1a8064a4, 0x1a8064a8, + 0x1a8064ac, 0x1a8064b0, 0x1a8064b4, 0x1a8064b8, + 0x1a8064bc, 0x1a8064c0, 0x1a8064c4, 0x1a8064c8, + 0x1a8064cc, 0x1a8064d0, 0x1a8064d4, 0x1a8064d8, + 0x1a8064dc, 0x1a8064e0, 0x1a8064e4, 0x1a8064e8, + 0x1a8064ec, 0x1a8064f0, 0x1a8064f4, 0x1a8064f8, + 0x1a8064fc, 0x1a806500, 0x1a806504, 0x1a806508, + 0x1a80650c, 0x1a806510, 0x1a806514, 0x1a806518, + 0x1a80651c, 0x1a806520, 0x1a806524, 0x1a806528, + 0x1a80652c, 0x1a806530, 0x1a806534, 0x1a806538, + 0x1a80653c, 0x1a806540, 0x1a806544, 0x1a806548, + 0x1a80654c, 0x1a806550, 0x1a806554, 0x1a806558, + 0x1a80655c, 0x1a806560, 0x1a806564, 0x1a806568, + 0x1a80656c, 0x1a806570, 0x1a806574, 0x1a806578, + 0x1a80657c, 0x1a806580, 0x1a806584, 0x1a806588, + 0x1a80658c, 0x1a806590, 0x1a806594, 0x1a806598, + 0x1a80659c, 0x1a8065a0, 0x1a8065a4, 0x1a8065a8, + 0x1a8065ac, 0x1a8065b0, 0x1a8065b4, 0x1a8065b8, + 0x1a8065bc, 0x1a8065c0, 0x1a8065c4, 0x1a8065c8, + 0x1a8065cc, 0x1a8065d0, 0x1a8065d4, 0x1a8065d8, + 0x18b46000, 0x18b46004, 0x18b46008, 0x18b4600c, + 0x18b46010, 0x18b46014, 0x18b46018, 0x18b4601c, + 0x18b46020, 0x18b46024, 0x18b46028, 0x18b4602c, + 0x18b46030, 0x18b46034, 0x18b46038, 0x18b4603c, + 0x18b46040, 0x18b46044, 0x18b46048, 0x18b4604c, + 0x18b46050, 0x18b46054, 0x18b46058, 0x18b4605c, + 0x18b46060, 0x18b46064, 0x18b46068, 0x18b4606c, + 0x18b46070, 0x18b46074, 0x18b46078, 0x18b4607c, + 0x18b46080, 0x18b46084, 0x18b46088, 0x18b4608c, + 0x18b46090, 0x18b46094, 0x18b46098, 0x18b4609c, + 0x18b460a0, 0x18b460a4, 0x18b460a8, 0x18b460ac, + 0x18b460b0, 0x18b460b4, 0x18b460b8, 0x18b460bc, + 0x18b460c0, 0x18b460c4, 0x18b460c8, 0x18b460cc, + 0x18b460d0, 0x18b460d4, 0x18b460d8, 0x18b460dc, + 0x18b460e0, 0x18b460e4, 0x18b460e8, 0x18b460ec, + 0x18b460f0, 0x18b460f4, 0x18b460f8, 0x18b460fc, + 0x18b46100, 0x18b46104, 0x18b46108, 0x18b4610c, + 0x18b46110, 0x18b46114, 0x18b46118, 0x18b4611c, + 0x18b46120, 0x18b46124, 0x18b46128, 0x18b4612c, + 0x18b46130, 0x18b46134, 0x18b46138, 0x18b4613c, + 0x18b46140, 0x18b46144, 0x18b46148, 0x18b4614c, + 0x18b46150, 0x18b46154, 0x18b46158, 0x18b4615c, + 0x18b46160, 0x18b46164, 0x18b46168, 0x18b4616c, + 0x18b46170, 0x18b46174, 0x18b46178, 0x18b4617c, + 0x18b46180, 0x18b46184, 0x18b46188, 0x18b4618c, + 0x18b46190, 0x18b46194, 0x18b46198, 0x18b4619c, + 0x18b461a0, 0x18b461a4, 0x18b461a8, 0x18b461ac, + 0x18b461b0, 0x18b461b4, 0x18b461b8, 0x18b461bc, + 0x18b461c0, 0x18b461c4, 0x18b461c8, 0x18b461cc, + 0x18b461d0, 0x18b461d4, 0x18b461d8, 0x18b461dc, + 0x18b461e0, 0x18b461e4, 0x18b461e8, 0x18b461ec, + 0x18b461f0, 0x18b461f4, 0x18b461f8, 0x18b461fc, + 0x18b46200, 0x18b46204, 0x18b46208, 0x18b4620c, + 0x18b46210, 0x18b46214, 0x18b46218, 0x18b4621c, + 0x18b46220, 0x18b46224, 0x18b46228, 0x18b4622c, + 0x18b46230, 0xc1286000, 0xc1286004, 0xc1286008, + 0xc128600c, 0xc1286010, 0xc1286014, 0xc1286018, + 0xc128601c, 0xc1286020, 0xc1286024, 0xc1286028, + 0xc128602c, 0xc1286030, 0xc1286034, 0xc1286038, + 0xc128603c, 0xc1286040, 0xc1286044, 0xc1286048, + 0xc128604c, 0xc1286050, 0xc1286054, 0xc1286058, + 0xc128605c, 0xc1286060, 0xc1286064, 0xc1286068, + 0xc128606c, 0xc1286070, 0xc1286074, 0xc1286078, + 0xc128607c, 0xc1286080, 0xc1286084, 0xc1286088, + 0xc128608c, 0xc1286090, 0xc1286094, 0xc1286098, + 0xc128609c, 0xc12860a0, 0xc12860a4, 0xc12860a8, + 0xc12860ac, 0xc12860b0, 0xc12860b4, 0xc12860b8, + 0xc12860bc, 0xc12860c0, 0xc12860c4, 0xc12860c8, + 0xc12860cc, 0xc12860d0, 0xc12860d4, 0xc12860d8, + 0xc12860dc, 0xc12860e0, 0xc12860e4, 0xc12860e8, + 0xc12860ec, 0xc12860f0, 0xc12860f4, 0xc12860f8, + 0xc12860fc, 0xc1286100, 0xc1286104, 0xc1286108, + 0xc128610c, 0xc1286110, 0xc1286114, 0xc1286118, + 0xc128611c, 0xc1286120, 0xc1286124, 0xc1286128, + 0xc128612c, 0xc1286130, 0xc1286134, 0xc1286138, + 0xc128613c, 0xc1286140, 0xc1286144, 0xc1286148, + 0xc128614c, 0xc1286150, 0xc1286154, 0xc1286158, + 0xc128615c, 0xc1286160, 0xc1286164, 0xc1286168, + 0xc128616c, 0xc1286170, 0xc1286174, 0xc1286178, + 0xc128617c, 0xc1286180, 0xc1286184, 0xc1286188, + 0xc128618c, 0xc1286190, 0xc1286194, 0xc1286198, + 0xc128619c, 0xc12861a0, 0xc12861a4, 0xc12861a8, + 0xc12861ac, 0xc12861b0, 0xc12861b4, 0xc12861b8, + 0xc12861bc, 0xc12861c0, 0xc12861c4, 0xc12861c8, + 0xc12861cc, 0xc12861d0, 0xc12861d4, 0xc12861d8, + 0xc12861dc, 0xc12861e0, 0xc12861e4, 0xc12861e8, + 0xc12861ec, 0xc12861f0, 0xc12861f4, 0xc12861f8, + 0xc12861fc, 0xc1286200, 0xc1286204, 0xc1286208, + 0xc128620c, 0xc1286210, 0xc1286214, 0xc1286218, + 0xc128621c, 0xc1286220, 0xc1286224, 0xc1286228, + 0xc128622c, 0xc1286230, 0xc1286234, 0xc1286238, + 0xc128623c, 0xc1286240, 0xc1286244, 0xc1286248, + 0xc128624c, 0xc1286250, 0xc1286254, 0xc1286258, + 0xc128625c, 0xc1286260, 0xc1286264, 0xc1286268, + 0xc128626c, 0xc1286270, 0xc1286274, 0xc1286278, + 0xc128627c, 0xc1286280, 0xc1286284, 0xc1286288, + 0xc128628c, 0xc1286290, 0xc1286294, 0xc1286298, + 0xc128629c, 0xc12862a0, 0xc12862a4, 0xc12862a8, + 0xc12862ac, 0xc12862b0, 0xc12862b4, 0xc12862b8, + 0xc6806000, 0xc6806004, 0xc6806008, 0xc680600c, + 0xc6806010, 0xc6806014, 0xc6806018, 0xc680601c, + 0xc6806020, 0xc6806024, 0xc6806028, 0xc680602c, + 0xc6806030, 0xc6806034, 0xc6806038, 0xc680603c, + 0xc6806040, 0xc6806044, 0xc6806048, 0xc680604c, + 0xc6806050, 0xc6806054, 0xc6806058, 0xc680605c, + 0xc6806060, 0xc6806064, 0xc6806068, 0xc680606c, + 0xc6806070, 0xc6806074, 0xc6806078, 0xc680607c, + 0xc6806080, 0xc6806084, 0xc6806088, 0xc680608c, + 0xc6806090, 0xc6806094, 0xc6806098, 0xc680609c, + 0xc68060a0, 0xc68060a4, 0xc68060a8, 0xc68060ac, + 0xc68060b0, 0xc68060b4, 0xc68060b8, 0xc68060bc, + 0xc68060c0, 0xc68060c4, 0xc68060c8, 0xc68060cc, + 0xc5806000, 0xc5806004, 0xc5806008, 0xc580600c, + 0xc5806010, 0xc5806014, 0xc5806018, 0xc580601c, + 0xc5806020, 0xc5806024, 0xc5806028, 0xc580602c, + 0xc5806030, 0xc5806034, 0xc5806038, 0xc580603c, + 0xc5806040, 0xc5806044, 0xc5806048, 0xc580604c, + 0xc5806050, 0xc5806054, 0xc5806058, 0xc580605c, + 0xc5806060, 0xc5806064, 0xc5806068, 0xc580606c, + 0xc5806070, 0xc5806074, 0xc5806078, 0xc580607c, + 0xc5806080, 0xc5806084, 0xc5806088, 0xc580608c, + 0xc5806090, 0xc5806094, 0xc5806098, 0xc580609c, + 0xc58060a0, 0xc58060a4, 0xc58060a8, 0xc58060ac, + 0xc58060b0, 0xc58060b4, 0xc58060b8, 0xc58060bc, + 0xc58060c0, 0xc58060c4, 0xc58060c8, 0xc58060cc, + 0xc58060d0, 0xc58060d4, 0xc58060d8, 0xc58060dc, + 0xc58060e0, 0xc58060e4, 0xc58060e8, 0xc58060ec, + 0xc58060f0, 0xc58060f4, 0xc58060f8, 0xc58060fc, + 0xc5806100, 0xc5806104, 0xc5806108, 0xc580610c, + 0xc5806110, 0xc5806114, 0xc5806118, 0xc580611c, + 0xc5806120, 0xc5806124, 0xc5806128, 0xc580612c, + 0xc5806130, 0xc5806134, 0xc5806138, 0xc580613c, + 0xc5806140, 0xc5806144, 0xc5806148, 0xc580614c, + 0xc5806150, 0xc5806154, 0xc5806158, 0xc580615c, + 0xc5806160, 0xc5806164, 0xc5806168, 0xc580616c, + 0xc5806170, 0xc5806174, 0xc5806178, 0xc580617c, + 0xc5806180, 0xc5806184, 0xc5806188, 0xc580618c, + 0xc5806190, 0xc5806194, 0xc5806198, 0xc580619c, + 0xc58061a0, 0xc58061a4, 0xc58061a8, 0xc58061ac, + 0xc58061b0, 0xc58061b4, 0xc58061b8, 0xc58061bc, + 0xc58061c0, 0xc58061c4, 0xc58061c8, 0xc58061cc, + 0xc58061d0, 0xc58061d4, 0xc58061d8, 0xc58061dc, + 0xc58061e0, 0xc58061e4, 0xc58061e8, 0xc58061ec, + 0xc58061f0, 0xc58061f4, 0xc58061f8, 0xc58061fc, + 0xc5806200, 0xc5806204, 0xc5806208, 0xc580620c, + 0xc5806210, 0xc5806214, 0xc5806218, 0xc580621c, + 0xc5806220, 0xc5806224, 0xc5806228, 0xc580622c, + 0xc5806230, 0xc5806234, 0xc5806238, 0xc580623c, + 0xc5806240, 0xc5806244, 0xc5806248, 0xc580624c, + 0xc5806250, 0xc5806254, 0xc5806258, 0xc580625c, + 0xc5806260, 0xc5806264, 0xc5806268, 0xc580626c, + 0xc5806270, 0xc5806274, 0xc5806278, 0xc580627c, + 0xc5806280, 0xc5806284, 0xc5806288, 0xc580628c, + 0xc5806290, 0xc5806294, 0xc5806298, 0xc580629c, + 0xc58062a0, 0xc58062a4, 0xc58062a8, 0xc58062ac, + 0xc58062b0, 0xc58062b4, 0xc58062b8, 0xc58062bc, + 0xc58062c0, 0xc58062c4, 0xc58062c8, 0xc58062cc, + 0xc58062d0, 0xc58062d4, 0xc58062d8, 0xc58062dc, + 0xc58062e0, 0xc58062e4, 0xc58062e8, 0xc58062ec, + 0xc58062f0, 0xc58062f4, 0xc58062f8, 0xc58062fc, + 0xc5806300, 0xc5806304, 0xc5806308, 0xc580630c, + 0xc3026000, 0xc3026004, 0xc3026008, 0xc302600c, + 0xc3026010, 0xc3026014, 0xc3026018, 0xc302601c, + 0xc3026020, 0xc3026024, 0xc3026028, 0xc302602c, + 0xc3026030, 0xc3026034, 0xc3026038, 0xc302603c, + 0xc3026040, 0xc3026044, 0xc3026048, 0xc302604c, + 0xc3026050, 0xc3026054, 0xc3026058, 0xc302605c, + 0xc3026060, 0xc3026064, 0xc3026068, 0xc302606c, + 0xc3026070, 0xc3026074, 0xc3026078, 0xc302607c, + 0xc3026080, 0xc3026084, 0xc3026088, 0xc302608c, + 0xc3026090, 0xc3026094, 0xc3026098, 0xc302609c, + 0xc30260a0, 0xc30260a4, 0xc30260a8, 0xc30260ac, + 0xc30260b0, 0xc3426000, 0xc3426004, 0xc3426008, + 0xc342600c, 0xc3426010, 0xc3426014, 0xc3426018, + 0xc342601c, 0xc3426020, 0xc3426024, 0xc3426028, + 0xc342602c, 0xc3426030, 0xc3426034, 0xc3426038, + 0xc342603c, 0xc3426040, 0xc3426044, 0xc3426048, + 0xc342604c, 0xc3426050, 0xc3426054, 0xc3426058, + 0xc342605c, 0xc3426060, 0xc3426064, 0xc3426068, + 0xc342606c, 0xc3426070, 0xc3426074, 0xc3426078, + 0xc342607c, 0xc3426080, 0xc3426084, 0xc3426088, + 0xc342608c, 0xc3426090, 0xc3426094, 0xc3426098, + 0xc342609c, 0xc34260a0, 0xc34260a4, 0xc34260a8, + 0xc34260ac, 0xc34260b0 +}; + +static const u32 sec_modid_register_list[] = { + 0xe8023800, 0xe8023804, 0xe8023808, 0xe802380c, + 0xe8023810, 0xe8023814, 0xe80a3800, 0xe80a3804, + 0xe80a3808, 0xe80a380c, 0xe80a3810, 0xe80a3814, + 0xe8123800, 0xe8123804, 0xe8123808, 0xe812380c, + 0xe8123810, 0xe8123814, 0xe81a3800, 0xe81a3804, + 0xe81a3808, 0xe81a380c, 0xe81a3810, 0xe81a3814, + 0xe8223800, 0xe8223804, 0xe8223808, 0xe822380c, + 0xe8223810, 0xe8223814, 0xe82a3800, 0xe82a3804, + 0xe82a3808, 0xe82a380c, 0xe82a3810, 0xe82a3814, + 0xe8323800, 0xe8323804, 0xe8323808, 0xe832380c, + 0xe8323810, 0xe8323814, 0xe83a3800, 0xe83a3804, + 0xe83a3808, 0xe83a380c, 0xe83a3810, 0xe83a3814, + 0xc0623800, 0xc0623804, 0xc0623808, 0xc062380c, + 0xc0623810, 0xc0623814, 0xc0623818, 0xc062381c, + 0xc0623820, 0xc0623824, 0xc0623828, 0xc0763800, + 0xc0763804, 0xc0763808, 0xc076380c, 0xc0763810, + 0xc0763814, 0xc0763818, 0xc076381c, 0xc0763820, + 0xc0763824, 0xc0763828, 0xc076382c, 0xc0763830, + 0xc0763834, 0xc0763838, 0xc076383c, 0xc0763840, + 0xc0763844, 0xc0763848, 0xc076384c, 0xc0763850, + 0xc0763854, 0xc0763858, 0xc076385c, 0xc0763860, + 0xc0763864, 0xc0763868, 0xc076386c, 0xc0763870, + 0xc0763874, 0xc0763878, 0xc076387c, 0xc0763880, + 0xc0763884, 0xc0763888, 0xc076388c, 0xc0763890, + 0xc0763894, 0xc0763898, 0xc076389c, 0xc07638a0, + 0xc07638a4, 0xc07638a8, 0xc07638ac, 0xc07638b0, + 0xc07a3800, 0xc07a3804, 0xc07a3808, 0xc07a380c, + 0xc07a3810, 0xc07a3814, 0xc07a3818, 0xc07a381c, + 0xc07a3820, 0xc07a3824, 0xc07a3828, 0xc07a382c, + 0x1d003800, 0x1d003804, 0x1d003808, 0x1d00380c, + 0x1d003810, 0x1d003814, 0x1d003818, 0x1d00381c, + 0x1d003820, 0x1d003824, 0x1d003828, 0x1d00382c, + 0x1d003830, 0x1d003834, 0x1d003838, 0x1d00383c, + 0x1d003840, 0x1d003844, 0x1d003848, 0x1d00384c, + 0x1d003850, 0x1d003854, 0x1d003858, 0x1d00385c, + 0x1d003860, 0x1d003864, 0x1d003868, 0x1d00386c, + 0x1d003870, 0x1d003874, 0x1d003878, 0x1d00387c, + 0x1d003880, 0x1d003884, 0xc6703800, 0xc6703804, + 0xc6703808, 0xc670380c, 0xc6703810, 0xc6703814, + 0xc6703818, 0xc670381c, 0xc6703820, 0xc6703824, + 0xc6703828, 0xc670382c, 0xc6703830, 0xc6703834, + 0xc6703838, 0xc670383c, 0xc6703840, 0xc6703844, + 0xc6703848, 0xc1743800, 0xc1743804, 0xc1743808, + 0xc174380c, 0xc1743810, 0xc1743814, 0xc1743818, + 0xc174381c, 0xc1743820, 0xc1743824, 0xc1743828, + 0xec603800, 0xec603804, 0xec603808, 0xec60380c, + 0xec603810, 0xec603814, 0xec603818, 0xec60381c, + 0xec603820, 0xec603824, 0xec603828, 0xec60382c, + 0xec603830, 0xec603834, 0xec603838, 0xec60383c, + 0xec603840, 0xec603844, 0xec603848, 0xec60384c, + 0xec603850, 0xec603854, 0xec603858, 0xec60385c, + 0xec603860, 0xec603864, 0xec603868, 0xec60386c, + 0xec603870, 0xec603874, 0xec603878, 0xec60387c, + 0xec603880, 0xec603884, 0xec603888, 0xec60388c, + 0xec603890, 0xec603894, 0xec603898, 0xec60389c, + 0xec6038a0, 0xec6038a4, 0xec6038a8, 0xec6038ac, + 0xec6038b0, 0xe9e23800, 0xe9e23804, 0xe9e23808, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0xca443800, + 0xca443804, 0xca443808, 0xca44380c, 0xca443810, + 0xca443814, 0xca443818, 0xca44381c, 0xca443820, + 0xca443824, 0xca543800, 0xca543804, 0xca543808, + 0xca54380c, 0xca543810, 0xca543814, 0xca543818, + 0xca54381c, 0xca543820, 0xcbf03800, 0xcbf03804, + 0xcbf03808, 0xcbf0380c, 0xcbf03810, 0xcbf03814, + 0xcbf03818, 0xcbf0381c, 0xcbf03820, 0xcbf03824, + 0xcbf03828, 0xcbf0382c, 0xcbf03830, 0xcbf03834, + 0xcbf03838, 0xcbf0383c, 0xcbf03840, 0xcbf03844, + 0xcbf03848, 0xcbf0384c, 0xcbf03850, 0xcbf03854, + 0xcbf03858, 0xcbf0385c, 0xcbf03860, 0xcbf03864, + 0xcbf03868, 0xcbf0386c, 0xcbf03870, 0xcbf03874, + 0xcbf03878, 0xcbf0387c, 0xcbf03880, 0xcbf03884, + 0xcbf03888, 0xcbf0388c, 0xcbf03890, 0xcbf03894, + 0xcbf03898, 0xcbf0389c, 0xcbf038a0, 0xcbf038a4, + 0xcbf038a8, 0xcbf038ac, 0xc9d03800, 0xc9d03804, + 0xc9d03808, 0xc9d0380c, 0xc9d03810, 0xc9d03814, + 0xc9d03818, 0xc9d0381c, 0xc9d03820, 0xc9d03824, + 0xc9d03828, 0xc9d0382c, 0xc9d03830, 0xc9d03834, + 0xc9d03838, 0xc9d0383c, 0xc9d03840, 0xc9d03844, + 0xc9d03848, 0xc9d0384c, 0xc9d03850, 0xc9d03854, + 0xc9d03858, 0xc9d0385c, 0xc9d03860, 0xc9d03864, + 0xc9d03868, 0xc9d0386c, 0xc9d03870, 0xc9d03874, + 0xc9d03878, 0xc9d0387c, 0xc9d03880, 0xc9d03884, + 0xc9d03888, 0xc9d0388c, 0xc9d03890, 0xc9d03894, + 0xc9d03898, 0xc9d0389c, 0xc9d038a0, 0xc9d038a4, + 0xc9d038a8, 0xc9d038ac, 0xc9d038b0, 0xc9d038b4, + 0xc9d038b8, 0xc9d038bc, 0xc9d038c0, 0xc9d038c4, + 0xc9d038c8, 0xc9d038cc, 0xde803800, 0xde803804, + 0xde803808, 0xde80380c, 0xde803810, 0xde803814, + 0xde803818, 0xde80381c, 0xde803820, 0xde803824, + 0xde803828, 0xde80382c, 0xde803830, 0xde803834, + 0xde803838, 0xde80383c, 0xde803840, 0xde803844, + 0xde803848, 0xde80384c, 0xde803850, 0xde803854, + 0xde803858, 0xc1a03800, 0xc1a03804, 0xc1a03808, + 0xc1a0380c, 0xc1a03810, 0xc1a03814, 0xc1a03818, + 0xc1a0381c, 0xc1a03820, 0xc1a03824, 0xc1a03828, + 0xc1a0382c, 0xc1a03830, 0xc1e03800, 0xc1e03804, + 0xc1e03808, 0xc1e0380c, 0xc1e03810, 0xc1e03814, + 0xc1e03818, 0xc1e0381c, 0xc1e03820, 0xc1e03824, + 0xc1e03828, 0xc1e0382c, 0xc1e03830, 0xe9a03800, + 0xe9a03804, 0xe9a03808, 0xe9a0380c, 0xe9a03810, + 0xe9a03814, 0xe9a03818, 0xe9a0381c, 0xe9a03820, + 0xe9a03824, 0xe9a03828, 0xe9a0382c, 0xe9a03830, + 0xe9a03834, 0xe9a03838, 0xe9a0383c, 0xe9a03840, + 0xe9a03844, 0xe9a03848, 0xe9a0384c, 0xe9a03850, + 0xe9a03854, 0xe9a03858, 0xe9a0385c, 0xe9a03860, + 0xe9a03864, 0xe9a03868, 0xe9a0386c, 0xe9a03870, + 0xe9a03874, 0xe9a03878, 0xe9a0387c, 0xe9a03880, + 0xe9a03884, 0xe9a03888, 0xe9a0388c, 0xe9a03890, + 0xe9a03894, 0xe9a03898, 0xe9a0389c, 0xe9a038a0, + 0xe9a038a4, 0xe9a038a8, 0xe9a038ac, 0xe9a038b0, + 0xe9a038b4, 0xe9a038b8, 0xe9a038bc, 0xe9a038c0, + 0xe9a038c4, 0xe9a038c8, 0xe9a038cc, 0xe9a038d0, + 0xe9a038d4, 0xe9a038d8, 0xe9a038dc, 0xe9a038e0, + 0xe9a038e4, 0xe9a038e8, 0xe9a038ec, 0xe9a038f0, + 0xe9a038f4, 0xe9a038f8, 0xe9a038fc, 0xe9a03900, + 0xe9a03904, 0xe9a03908, 0xe9a0390c, 0xe9a03910, + 0xe9a03914, 0xe9a03918, 0xe9a0391c, 0xe9a03920, + 0xe9a03924, 0xe9a03928, 0xe9a0392c, 0xe9a03930, + 0xe9a03934, 0xe9a03938, 0xe9a0393c, 0xe9a03940, + 0xe9a03944, 0xe9a03948, 0xe9a0394c, 0xe9a03950, + 0xe9a03954, 0xe9a03958, 0xd2f03800, 0xd2f03804, + 0xd2f03808, 0xd2f0380c, 0xd2f03810, 0xd2f03814, + 0xd2f03818, 0xd2f0381c, 0xd2f03820, 0xd2f03824, + 0xd2f03828, 0xd2f0382c, 0xd2f03830, 0xd2f03834, + 0xd2f03838, 0xd2f0383c, 0xd2f03840, 0xd2f03844, + 0xd2f03848, 0xd2f0384c, 0xd2f03850, 0xd6f03800, + 0xd6f03804, 0xd6f03808, 0xd6f0380c, 0xd6f03810, + 0xd6f03814, 0xd6f03818, 0xd6f0381c, 0xd6f03820, + 0xd6f03824, 0xd6f03828, 0xd6f0382c, 0xd6f03830, + 0xd6f03834, 0xd6f03838, 0xd6f0383c, 0xd6f03840, + 0xd6f03844, 0xd6f03848, 0xd6f0384c, 0xd6f03850, + 0xc0983800, 0xc0983804, 0xc0983808, 0xc098380c, + 0xc0983810, 0xc0983814, 0xc0983818, 0xc098381c, + 0xc0983820, 0xc0983824, 0xc0983828, 0xc098382c, + 0xc0983830, 0xc0983834, 0xc0983838, 0xc098383c, + 0xc0983840, 0xc0583800, 0xc0583804, 0xc0583808, + 0xc058380c, 0xc0583810, 0xc0583814, 0xc0583818, + 0xc058381c, 0xc0583820, 0xc0583824, 0xc0583828, + 0xc058382c, 0xc0583830, 0xc0583834, 0xc0583838, + 0xc058383c, 0xc0583840, 0xc0583844, 0xc0583848, + 0xc058384c, 0xc0583850, 0xc0583854, 0xc0583858, + 0xc058385c, 0xc0583860, 0xc0583864, 0xc0583868, + 0xc058386c, 0xc0583870, 0xc0583874, 0xc0583878, + 0xc058387c, 0xc0583880, 0xc0583884, 0xc0583888, + 0xc058388c, 0xc0583890, 0xc0583894, 0xc0583898, + 0xc058389c, 0xc05838a0, 0xc05838a4, 0xc05838a8, + 0xc05838ac, 0xc05838b0, 0xc05838b4, 0xc05838b8, + 0xc05838bc, 0xc05838c0, 0xc05838c4, 0xc05838c8, + 0xc05838cc, 0xc05838d0, 0xc05838d4, 0xc05838d8, + 0xc05838dc, 0xc05838e0, 0xc05838e4, 0xc05838e8, + 0xc05838ec, 0xc05838f0, 0xc05838f4, 0xc05838f8, + 0xc05838fc, 0xc0583900, 0xc0583904, 0xc0583908, + 0xc058390c, 0xc0583910, 0xcb403800, 0xcb403804, + 0xcb403808, 0xcb40380c, 0xcb403810, 0xcb403814, + 0xcb403818, 0xcb40381c, 0xcb403820, 0xcb403824, + 0xcb403828, 0x1a803800, 0x1a803804, 0x1a803808, + 0x1a80380c, 0x1a803810, 0x1a803814, 0x1a803818, + 0x1a80381c, 0x1a803820, 0x1a803824, 0x1a803828, + 0x1a80382c, 0x1a803830, 0x1a803834, 0x1a803838, + 0x1a80383c, 0x1a803840, 0x1a803844, 0x1a803848, + 0x1a80384c, 0x1a803850, 0x1a803854, 0x1a803858, + 0x1a80385c, 0x1a803860, 0x1a803864, 0x1a803868, + 0x1a80386c, 0x1a803870, 0x1a803874, 0x1a803878, + 0x1a80387c, 0x1a803880, 0x1a803884, 0x1a803888, + 0x1a80388c, 0x1a803890, 0x1a803894, 0x1a803898, + 0x1a80389c, 0x1a8038a0, 0x1a8038a4, 0x1a8038a8, + 0x1a8038ac, 0x1a8038b0, 0x1a8038b4, 0x1a8038b8, + 0x1a8038bc, 0x1a8038c0, 0x1a8038c4, 0x1a8038c8, + 0x1a8038cc, 0x1a8038d0, 0x1a8038d4, 0x1a8038d8, + 0x1a8038dc, 0x1a8038e0, 0x1a8038e4, 0x1a8038e8, + 0x1a8038ec, 0x1a8038f0, 0x1a8038f4, 0x1a8038f8, + 0x1a8038fc, 0x1a803900, 0x1a803904, 0x1a803908, + 0x1a80390c, 0x1a803910, 0x1a803914, 0x1a803918, + 0x1a80391c, 0x1a803920, 0x1a803924, 0x1a803928, + 0x1a80392c, 0x1a803930, 0x1a803934, 0x1a803938, + 0x1a80393c, 0x1a803940, 0x1a803944, 0x1a803948, + 0x1a80394c, 0x1a803950, 0x1a803954, 0x1a803958, + 0x1a80395c, 0x1a803960, 0x1a803964, 0x1a803968, + 0x1a80396c, 0x1a803970, 0x1a803974, 0x1a803978, + 0x1a80397c, 0x1a803980, 0x1a803984, 0x1a803988, + 0x1a80398c, 0x1a803990, 0x1a803994, 0x18b43800, + 0x18b43804, 0x18b43808, 0x18b4380c, 0x18b43810, + 0x18b43814, 0x18b43818, 0x18b4381c, 0x18b43820, + 0x18b43824, 0x18b43828, 0x18b4382c, 0x18b43830, + 0x18b43834, 0x18b43838, 0x18b4383c, 0x18b43840, + 0x18b43844, 0x18b43848, 0x18b4384c, 0x18b43850, + 0x18b43854, 0x18b43858, 0x18b4385c, 0x18b43860, + 0x18b43864, 0x18b43868, 0x18b4386c, 0x18b43870, + 0x18b43874, 0x18b43878, 0x18b4387c, 0x18b43880, + 0x18b43884, 0x18b43888, 0x18b4388c, 0x18b43890, + 0x18b43894, 0x18b43898, 0x18b4389c, 0x18b438a0, + 0x18b438a4, 0x18b438a8, 0x18b438ac, 0x18b438b0, + 0x18b438b4, 0xc1283800, 0xc1283804, 0xc1283808, + 0xc128380c, 0xc1283810, 0xc1283814, 0xc1283818, + 0xc128381c, 0xc1283820, 0xc1283824, 0xc1283828, + 0xc128382c, 0xc1283830, 0xc1283834, 0xc1283838, + 0xc128383c, 0xc1283840, 0xc1283844, 0xc1283848, + 0xc128384c, 0xc1283850, 0xc1283854, 0xc1283858, + 0xc128385c, 0xc1283860, 0xc1283864, 0xc1283868, + 0xc128386c, 0xc1283870, 0xc1283874, 0xc1283878, + 0xc128387c, 0xc1283880, 0xc1283884, 0xc1283888, + 0xc128388c, 0xc1283890, 0xc1283894, 0xc1283898, + 0xc128389c, 0xc12838a0, 0xc12838a4, 0xc12838a8, + 0xc12838ac, 0xc12838b0, 0xc12838b4, 0xc12838b8, + 0xc12838bc, 0xc12838c0, 0xc12838c4, 0xc12838c8, + 0xc12838cc, 0xc12838d0, 0xc12838d4, 0xc12838d8, + 0xc12838dc, 0xc12838e0, 0xc12838e4, 0xc12838e8, + 0xc12838ec, 0xc12838f0, 0xc12838f4, 0xc12838f8, + 0xc6803800, 0xc6803804, 0xc6803808, 0xc680380c, + 0xc6803810, 0xc6803814, 0xc6803818, 0xc680381c, + 0xc6803820, 0xc6803824, 0xc6803828, 0xc680382c, + 0xc6803830, 0xc5803800, 0xc5803804, 0xc5803808, + 0xc580380c, 0xc5803810, 0xc5803814, 0xc5803818, + 0xc580381c, 0xc5803820, 0xc5803824, 0xc5803828, + 0xc580382c, 0xc5803830, 0xc5803834, 0xc5803838, + 0xc580383c, 0xc5803840, 0xc5803844, 0xc5803848, + 0xc580384c, 0xc5803850, 0xc5803854, 0xc5803858, + 0xc580385c, 0xc5803860, 0xc5803864, 0xc5803868, + 0xc580386c, 0xc5803870, 0xc5803874, 0xc5803878, + 0xc580387c, 0xc5803880, 0xc5803884, 0xc5803888, + 0xc580388c, 0xc5803890, 0xc5803894, 0xc5803898, + 0xc580389c, 0xc58038a0, 0xc58038a4, 0xc58038a8, + 0xc58038ac, 0xc58038b0, 0xc58038b4, 0xc58038b8, + 0xc58038bc, 0xc58038c0, 0xc58038c4, 0xc58038c8, + 0xc58038cc, 0xc58038d0, 0xc58038d4, 0xc58038d8, + 0xc58038dc, 0xc58038e0, 0xc58038e4, 0xc58038e8, + 0xc58038ec, 0xc58038f0, 0xc58038f4, 0xc58038f8, + 0xc58038fc, 0xc5803900, 0xc5803904, 0xc5803908, + 0xc580390c, 0xc5803910, 0xc5803914, 0xc5803918, + 0xc580391c, 0xc5803920, 0xc5803924, 0xc5803928, + 0xc580392c, 0xc5803930, 0xc5803934, 0xc5803938, + 0xc580393c, 0xc5803940, 0xc5803944, 0xc5803948, + 0xc580394c, 0xc5803950, 0xc5803954, 0xc5803958, + 0xc580395c, 0xc5803960, 0xc5803964, 0xc5803968, + 0xc580396c, 0xc5803970, 0xc5803974, 0xc5803978, + 0xc580397c, 0xc5803980, 0xc5803984, 0xc5803988, + 0xc580398c, 0xc5803990, 0xc5803994, 0xc5803998, + 0xc580399c, 0xc58039a0, 0xc58039a4, 0xc58039a8, + 0xc58039ac, 0xc58039b0, 0xc58039b4, 0xc58039b8, + 0xc58039bc, 0xc58039c0, 0xc58039c4, 0xc58039c8, + 0xc58039cc, 0xc58039d0, 0xc58039d4, 0xc58039d8, + 0xc58039dc, 0xc58039e0, 0xc58039e4, 0xc58039e8, + 0xc58039ec, 0xc58039f0, 0xc58039f4, 0xc58039f8, + 0xc58039fc, 0xc5803a00, 0xc5803a04, 0xc5803a08, + 0xc5803a0c, 0xc5803a10, 0xc5803a14, 0xc5803a18, + 0xc5803a1c, 0xc5803a20, 0xc5803a24, 0xc5803a28, + 0xc5803a2c, 0xc5803a30, 0xc5803a34, 0xc5803a38, + 0xc5803a3c, 0xc5803a40, 0xc5803a44, 0xc5803a48, + 0xc5803a4c, 0xc5803a50, 0xc5803a54, 0xc5803a58, + 0xc5803a5c, 0xc5803a60, 0xc5803a64, 0xc5803a68, + 0xc5803a6c, 0xc5803a70, 0xc5803a74, 0xc5803a78, + 0xc5803a7c, 0xc5803a80, 0xc5803a84, 0xc5803a88, + 0xc5803a8c, 0xc5803a90, 0xc5803a94, 0xc5803a98, + 0xc5803a9c, 0xc5803aa0, 0xc5803aa4, 0xc5803aa8, + 0xc5803aac, 0xc5803ab0, 0xc5803ab4, 0xc5803ab8, + 0xc5803abc, 0xc5803ac0, 0xc3023800, 0xc3023804, + 0xc3023808, 0xc302380c, 0xc3023810, 0xc3023814, + 0xc3023818, 0xc302381c, 0xc3023820, 0xc3023824, + 0xc3023828, 0xc302382c, 0xc3023830, 0xc3023834, + 0xc3023838, 0xc302383c, 0xc3023840, 0xc3423800, + 0xc3423804, 0xc3423808, 0xc342380c, 0xc3423810, + 0xc3423814, 0xc3423818, 0xc342381c, 0xc3423820, + 0xc3423824, 0xc3423828, 0xc342382c, 0xc3423830, + 0xc3423834, 0xc3423838, 0xc342383c, 0xc3423840, +}; + +#endif /* __GEN5_CM33_H__ */ diff --git a/board/renesas/common/rcar64-common.c b/board/renesas/common/rcar64-common.c index 3d537be4d02..09667d46d99 100644 --- a/board/renesas/common/rcar64-common.c +++ b/board/renesas/common/rcar64-common.c @@ -49,15 +49,15 @@ int dram_init_banksize(void) return 0; for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start != 0x48000000) + if (gd->dram[bank].start != 0x48000000) continue; /* * If this U-Boot runs in EL3, make the bottom 128 MiB * available for loading of follow up firmware blobs. */ - gd->bd->bi_dram[bank].start -= 0x8000000; - gd->bd->bi_dram[bank].size += 0x8000000; + gd->dram[bank].start -= 0x8000000; + gd->dram[bank].size += 0x8000000; break; } diff --git a/board/renesas/geist/Kconfig b/board/renesas/geist/Kconfig new file mode 100644 index 00000000000..da36be0942f --- /dev/null +++ b/board/renesas/geist/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GEIST + +config SYS_SOC + default "renesas" + +config SYS_BOARD + default "geist" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "geist" + +endif diff --git a/board/renesas/geist/Makefile b/board/renesas/geist/Makefile new file mode 100644 index 00000000000..3e33c91e9e7 --- /dev/null +++ b/board/renesas/geist/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2025-2026 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0-only +# + +ifndef CONFIG_XPL_BUILD +obj-y += geist.o +endif diff --git a/board/renesas/geist/geist.c b/board/renesas/geist/geist.c new file mode 100644 index 00000000000..09241aed14c --- /dev/null +++ b/board/renesas/geist/geist.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This file is Geist board support. + * + * Copyright (C) 2025-2026 Renesas Electronics Corporation + */ + +#include <asm/io.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/renesas.h> +#include <init.h> + +#define HSUSB_MSTP704 BIT(4) /* HSUSB */ + +/* HSUSB block registers */ +#define HSUSB_REG_LPSTS 0xE6590102 +#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) +#define HSUSB_REG_UGCTRL2 0xE6590184 +#define HSUSB_REG_UGCTRL2_USB0SEL 0x30 +#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 + +int board_init(void) +{ + /* USB1 pull-up */ + setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); + + /* Configure the HSUSB block */ + mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); + /* Choice USB0SEL */ + clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, + HSUSB_REG_UGCTRL2_USB0SEL_EHCI); + /* low power status */ + setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); + + return 0; +} diff --git a/board/renesas/genmai/genmai.c b/board/renesas/genmai/genmai.c index 8153aed15e3..9245bf348f8 100644 --- a/board/renesas/genmai/genmai.c +++ b/board/renesas/genmai/genmai.c @@ -43,7 +43,7 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = gd->ram_base; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = gd->ram_base; + gd->dram[0].size = gd->ram_size; return 0; } diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index f5b1a5614b1..1503de675d5 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -5,7 +5,7 @@ #include <asm/io.h> #include <compiler.h> -#include <dbsc5.h> +#include <r8a779g0-dbsc5.h> #include <spi.h> #include <spi_flash.h> #include <spl.h> @@ -261,10 +261,10 @@ void renesas_dram_init_banksize(void) /* 16 GiB device, adjust memory map. */ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (gd->bd->bi_dram[bank].start == 0x480000000ULL) - gd->bd->bi_dram[bank].size = 0x180000000ULL; - else if (gd->bd->bi_dram[bank].start == 0x600000000ULL) - gd->bd->bi_dram[bank].size = 0x200000000ULL; + if (gd->dram[bank].start == 0x480000000ULL) + gd->dram[bank].size = 0x180000000ULL; + else if (gd->dram[bank].start == 0x600000000ULL) + gd->dram[bank].size = 0x200000000ULL; } } diff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS index 4de97dbb0a4..7758ee9b930 100644 --- a/board/rockchip/evb_rk3229/MAINTAINERS +++ b/board/rockchip/evb_rk3229/MAINTAINERS @@ -1,7 +1,6 @@ EVB-RK3229 M: Kever Yang <[email protected]> S: Maintained -F: arch/arm/dts/rk3229-evb.dts F: arch/arm/dts/rk3229-evb-u-boot.dtsi F: board/rockchip/evb_rk3229 F: include/configs/evb_rk3229.h diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 8c9b42fe2bb..d8748c1c2a2 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,8 +4,7 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig -F: arch/arm/dts/rk3328-evb.dts -F: arch/arm/dts/rk3328-evb-u-boot.dtsi +F: arch/arm/dts/rk3328-evb* GENERIC-RK3328 M: Jonas Karlman <[email protected]> @@ -17,14 +16,12 @@ NANOPI-R2C-RK3328 M: Tianling Shen <[email protected]> S: Maintained F: configs/nanopi-r2c-rk3328_defconfig -F: arch/arm/dts/rk3328-nanopi-r2c.dts F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi NANOPI-R2C-PLUS-RK3328 M: Tianling Shen <[email protected]> S: Maintained F: configs/nanopi-r2c-plus-rk3328_defconfig -F: arch/arm/dts/rk3328-nanopi-r2c-plus.dts F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi NANOPI-R2S-RK3328 @@ -32,7 +29,6 @@ M: David Bauer <[email protected]> S: Maintained F: configs/nanopi-r2s-rk3328_defconfig F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi -F: arch/arm/dts/rk3328-nanopi-r2s.dts NANOPI-R2S-PLUS-RK3328 M: Jonas Karlman <[email protected]> @@ -44,14 +40,12 @@ ORANGEPI-R1-PLUS-RK3328 M: Tianling Shen <[email protected]> S: Maintained F: configs/orangepi-r1-plus-rk3328_defconfig -F: arch/arm/dts/rk3328-orangepi-r1-plus.dts F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi ORANGEPI-R1-PLUS-LTS-RK3328 M: Tianling Shen <[email protected]> S: Maintained F: configs/orangepi-r1-plus-lts-rk3328_defconfig -F: arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi ROC-RK3328-CC @@ -60,16 +54,14 @@ M: Chen-Yu Tsai <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/roc-cc-rk3328_defconfig -F: arch/arm/dts/rk3328-roc-cc.dts -F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +F: arch/arm/dts/rk3328-roc-cc* ROCK64-RK3328 M: Matwey V. Kornilov <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/rock64-rk3328_defconfig -F: arch/arm/dts/rk3328-rock64.dts -F: arch/arm/dts/rk3328-rock64-u-boot.dtsi +F: arch/arm/dts/rk3328-rock64* ROCKPIE-RK3328 M: Banglang Huang <[email protected]> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 8319db2e976..860dd028759 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -24,9 +24,7 @@ KHADAS-EDGE M: Nick Xie <[email protected]> S: Maintained F: configs/khadas-edge-rk3399_defconfig -F: arch/arm/dts/rk3399-khadas-edge.dts -F: arch/arm/dts/rk3399-khadas-edge.dtsi -F: arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi +F: arch/arm/dts/rk3399-khadas-edge* KHADAS-EDGE-CAPTAIN M: Nick Xie <[email protected]> @@ -56,8 +54,7 @@ NANOPI-M4 M: Jagan Teki <[email protected]> S: Maintained F: configs/nanopi-m4-rk3399_defconfig -F: arch/arm/dts/rk3399-nanopi-m4.dts -F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi +F: arch/arm/dts/rk3399-nanopi-m4* NANOPI-M4-2GB M: Jagan Teki <[email protected]> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 030cdbe6f3d..3e2d864901f 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -1,9 +1,18 @@ +9TRIPOD-X3568-V4 +M: Coia Prant <[email protected]> +S: Maintained +F: configs/9tripod-x3568-v4-rk3568_defconfig + BANANAPI-BPI-R2-PRO M: Frank Wunderlich <[email protected]> S: Maintained F: configs/bpi-r2-pro-rk3568_defconfig -F: arch/arm/dts/rk3568-bpi-r2-pro.dts -F: arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi +F: arch/arm/dts/rk3568-bpi-r2-pro* + +EASEPI-R1 +M: Liangbin Lian <[email protected]> +S: Maintained +F: configs/easepi-r1-rk3568_defconfig EVB-RK3568 M: Joseph Chen <[email protected]> @@ -11,78 +20,67 @@ S: Maintained F: board/rockchip/evb_rk3568 F: include/configs/evb_rk3568.h F: configs/evb-rk3568_defconfig -F: arch/arm/dts/rk3568-evb-u-boot.dtsi -F: arch/arm/dts/rk3568-evb.dts +F: arch/arm/dts/rk3568-evb* FASTRHINO-R66S-RK3568 M: Tianling Shen <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/fastrhino-r66s-rk3568_defconfig -F: arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi +F: arch/arm/dts/rk3568-fastrhino-r66s* GENERIC-RK3568 M: Jonas Karlman <[email protected]> S: Maintained F: configs/generic-rk3568_defconfig -F: arch/arm/dts/rk3568-generic.dts -F: arch/arm/dts/rk3568-generic-u-boot.dtsi +F: arch/arm/dts/rk3568-generic* LUBANCAT-2 M: Andy Yan <[email protected]> S: Maintained F: configs/lubancat-2-rk3568_defconfig -F: arch/arm/dts/rk3568-lubancat-2.dts -F: arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi +F: arch/arm/dts/rk3568-lubancat-2* NANOPI-R3S M: Tianling Shen <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/nanopi-r3s-rk3566_defconfig -F: arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi +F: arch/arm/dts/rk3566-nanopi-r3s* NANOPI-R5C M: Tianling Shen <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/nanopi-r5c-rk3568_defconfig -F: arch/arm/dts/rk3568-nanopi-r5c.dts -F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi +F: arch/arm/dts/rk3568-nanopi-r5c* NANOPI-R5S M: Tianling Shen <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/nanopi-r5s-rk3568_defconfig -F: arch/arm/dts/rk3568-nanopi-r5s.dts -F: arch/arm/dts/rk3568-nanopi-r5s.dtsi -F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +F: arch/arm/dts/rk3568-nanopi-r5s* RADXA-CM3-IO M: Jagan Teki <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/radxa-cm3-io-rk3566_defconfig -F: arch/arm/dts/rk3566-radxa-cm3.dtsi -F: arch/arm/dts/rk3566-radxa-cm3-io.dts -F: arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +F: arch/arm/dts/rk3566-radxa-cm3-io* RADXA-E25 M: Jonas Karlman <[email protected]> S: Maintained F: configs/radxa-e25-rk3568_defconfig -F: arch/arm/dts/rk3568-radxa-cm3i.dtsi -F: arch/arm/dts/rk3568-radxa-e25.dts -F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi +F: arch/arm/dts/rk3568-radxa-e25* ROCK-3A M: Akash Gajjar <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/rock-3a-rk3568_defconfig -F: arch/arm/dts/rk3568-rock-3a.dts -F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +F: arch/arm/dts/rk3568-rock-3a* ROCK-3B M: Jonas Karlman <[email protected]> @@ -94,11 +92,11 @@ ROCK-3C M: Jonas Karlman <[email protected]> M: Maxim Moskalets <[email protected]> S: Maintained -F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi +F: arch/arm/dts/rk3566-rock-3c* F: configs/rock-3c-rk3566_defconfig LCKFB-TaishanPi M: Jiehui He <[email protected]> S: Maintained F: configs/lckfb-tspi-rk3566_defconfig -F: arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi +F: arch/arm/dts/rk3566-lckfb-tspi* diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 8b11db43f5f..b64dd4947ee 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -2,16 +2,13 @@ COOLPI-4B-RK3588S M: Andy Yan <[email protected]> S: Maintained F: configs/coolpi-4b-rk3588s_defconfig -F: arch/arm/dts/rk3588s-coolpi-4b.dts -F: arch/arm/dts/rk3588s-coolpi-u-boot.dtsi +F: arch/arm/dts/rk3588s-coolpi-4b* COOLPI-CM5-EVB-RK3588 M: Andy Yan <[email protected]> S: Maintained F: configs/coolpi-cm5-evb-rk3588_defconfig -F: arch/arm/dts/rk3588-coolpi-cm5.dtsi -F: arch/arm/dts/rk3588-coolpi-cm5-evb.dts -F: arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi +F: arch/arm/dts/rk3588-coolpi-cm5-evb* EVB-RK3588 M: Kever Yang <[email protected]> @@ -19,15 +16,13 @@ S: Maintained F: board/rockchip/evb_rk3588 F: include/configs/evb_rk3588.h F: configs/evb-rk3588_defconfig -F: arch/arm/dts/rk3588-evb1-v10.dts -F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi +F: arch/arm/dts/rk3588-evb1-v10* GENERIC-RK3588 M: Jonas Karlman <[email protected]> S: Maintained F: configs/generic-rk3588_defconfig -F: arch/arm/dts/rk3588-generic.dts -F: arch/arm/dts/rk3588-generic-u-boot.dtsi +F: arch/arm/dts/rk3588-generic* MNT-REFORM2-RK3588 M: Peter Robinson <[email protected]> @@ -38,24 +33,22 @@ ORANGEPI-5-RK3588 M: Jonas Karlman <[email protected]> S: Maintained F: configs/orangepi-5-rk3588s_defconfig -F: arch/arm/dts/rk3588s-orangepi-5.dts F: arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi ORANGEPI-5-MAX-RK3588 M: Ilya Katsnelson <[email protected]> S: Maintained F: configs/orangepi-5-max-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi +F: arch/arm/dts/rk3588-orangepi-5-max* ORANGEPI-5-PLUS-RK3588 M: Jonas Karlman <[email protected]> S: Maintained F: configs/orangepi-5-plus-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-plus.dts -F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi +F: arch/arm/dts/rk3588-orangepi-5-plus* ORANGEPI-5-RK3588-ULTRA M: Niu Zhihong <[email protected]> S: Maintained F: configs/orangepi-5-ultra-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi +F: arch/arm/dts/rk3588-orangepi-5-ultra* diff --git a/board/rockchip/toybrick_rk3588/MAINTAINERS b/board/rockchip/toybrick_rk3588/MAINTAINERS index cd4401c24f3..e2c76f80e9b 100644 --- a/board/rockchip/toybrick_rk3588/MAINTAINERS +++ b/board/rockchip/toybrick_rk3588/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/rockchip/toybrick_rk3588 F: include/configs/toybrick_rk3588.h F: configs/toybrick-rk3588_defconfig -F: arch/arm/dts/rk3588-toybrick-x0.dts -F: arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi +F: arch/arm/dts/rk3588-toybrick-x0* diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c index ee0ad20ced4..200562482af 100644 --- a/board/ronetix/imx8mq-cm/spl.c +++ b/board/ronetix/imx8mq-cm/spl.c @@ -18,8 +18,6 @@ #include <linux/delay.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(void) { /* ddr init */ @@ -135,9 +133,6 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - arch_cpu_init(); init_uart_clk(0); diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index ee578749bce..7a0a93c1afe 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -76,11 +76,6 @@ static void pm9261_nand_hw_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* arch number of PM9261-Board */ @@ -108,8 +103,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 8125f064cf1..0ff49dceb9e 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -70,11 +70,6 @@ static void pm9263_nand_hw_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* arch number of PM9263 Board */ @@ -102,8 +97,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->dram[0].start = PHYS_SDRAM; + gd->dram[0].size = PHYS_SDRAM_SIZE; return 0; } diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 5d5edd9f253..b5664296a81 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -150,8 +150,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index e70b4a82687..130136e8596 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -67,8 +67,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig index 64a4ffa7e67..d98da0ecab5 100644 --- a/board/samsung/axy17lte/Kconfig +++ b/board/samsung/axy17lte/Kconfig @@ -11,8 +11,8 @@ config SYS_CONFIG_NAME default "exynos78x0-common" config EXYNOS7880 - bool "Exynos 7880 SOC support" - default y + bool "Exynos 7880 SOC support" + default y endif if TARGET_A7Y17LTE @@ -28,8 +28,8 @@ config SYS_CONFIG_NAME default "exynos78x0-common" config EXYNOS7880 - bool "Exynos 7880 SOC support" - default y + bool "Exynos 7880 SOC support" + default y endif if TARGET_A3Y17LTE @@ -45,6 +45,6 @@ config SYS_CONFIG_NAME default "exynos78x0-common" config EXYNOS7870 - bool "Exynos 7870 SOC support" - default y + bool "Exynos 7870 SOC support" + default y endif diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index eed1c2450fa..da3510023c4 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -115,7 +115,7 @@ int board_init(void) ulong size = CONFIG_SYS_MEM_TOP_HIDE; gd->ram_size -= size; - gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; + gd->dram[CONFIG_NR_DRAM_BANKS - 1].size -= size; #endif exynos_init(); @@ -143,8 +143,8 @@ int dram_init_banksize(void) addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); - gd->bd->bi_dram[i].start = addr; - gd->bd->bi_dram[i].size = size; + gd->dram[i].start = addr; + gd->dram[i].size = size; } return 0; diff --git a/board/samsung/exynos-mobile/exynos-mobile.c b/board/samsung/exynos-mobile/exynos-mobile.c index 6b2b1523663..d91e2e7d3f2 100644 --- a/board/samsung/exynos-mobile/exynos-mobile.c +++ b/board/samsung/exynos-mobile/exynos-mobile.c @@ -346,8 +346,8 @@ int dram_init_banksize(void) unsigned int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = mem_map[i + 1].phys; - gd->bd->bi_dram[i].size = mem_map[i + 1].size; + gd->dram[i].start = mem_map[i + 1].phys; + gd->dram[i].size = mem_map[i + 1].size; } return 0; diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index a1047f3fd2a..96a411233d1 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -43,12 +43,12 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = PHYS_SDRAM_2_SIZE; + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = PHYS_SDRAM_3_SIZE; return 0; } diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 7d0b0fcb0ae..7e992c23a1b 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -56,8 +56,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index 5a4874b29cd..f013893b465 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -57,17 +57,17 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, + gd->dram[1].start = PHYS_SDRAM_2; + gd->dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); - gd->bd->bi_dram[2].start = PHYS_SDRAM_3; - gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, + gd->dram[2].start = PHYS_SDRAM_3; + gd->dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE); - gd->bd->bi_dram[3].start = PHYS_SDRAM_4; - gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, + gd->dram[3].start = PHYS_SDRAM_4; + gd->dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); return 0; diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig index 9d45c4239be..3f2e75b03fe 100644 --- a/board/siemens/draco/Kconfig +++ b/board/siemens/draco/Kconfig @@ -33,10 +33,10 @@ endif if TARGET_ETAMIN config SYS_BOARD - default "draco" + default "draco" config SYS_VENDOR - default "siemens" + default "siemens" config SYS_SOC default "am33xx" diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index c75f4a0d084..69d3b9d61d3 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -232,7 +232,7 @@ void set_board_info_env(void) env_set("seboot_version", buf); env_set("fw_version", PLAIN_VERSION); - if (IS_ENABLED(CONFIG_NET)) { + if (IS_ENABLED(CONFIG_NET_LEGACY)) { int mac_cnt; mac_cnt = sysinfo_get_item_count(sysinfo, SYSID_BOARD_MAC_ADDR); @@ -397,20 +397,20 @@ int dram_init_banksize(void) if (gd->ram_size > SZ_2G) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = SZ_2G; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = SZ_2G; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; - gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + gd->dram[1].start = CFG_SYS_SDRAM_BASE1; + gd->dram[1].size = gd->ram_size - SZ_2G; } else { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = gd->ram_size; /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0; - gd->bd->bi_dram[1].size = 0; + gd->dram[1].start = 0; + gd->dram[1].size = 0; } return 0; diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig index c181d26a44a..1b1c9181bad 100644 --- a/board/socionext/developerbox/Kconfig +++ b/board/socionext/developerbox/Kconfig @@ -11,10 +11,10 @@ config TARGET_DEVELOPERBOX select SYS_DISABLE_DCACHE_OPS select OF_BOARD_SETUP help - Choose this option if you build the U-Boot for the DeveloperBox - 96boards Enterprise Edition. - This board will booted from SCP firmware and it enables SMMU, thus - the dcache is updated automatically when DMA operation is executed. + Choose this option if you build the U-Boot for the DeveloperBox + 96boards Enterprise Edition. + This board will booted from SCP firmware and it enables SMMU, thus + the dcache is updated automatically when DMA operation is executed. endchoice config SYS_SOC diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 556a9ed527e..a7bd08f69ad 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -170,11 +170,11 @@ int dram_init_banksize(void) struct draminfo_entry *ent = synquacer_draminfo->entry; int i; - for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + for (i = 0; i < ARRAY_SIZE(gd->dram); i++) { if (i < synquacer_draminfo->nr_regions) { debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); - gd->bd->bi_dram[i].start = ent[i].base; - gd->bd->bi_dram[i].size = ent[i].size; + gd->dram[i].start = ent[i].base; + gd->dram[i].size = ent[i].size; } } diff --git a/board/socrates/nand.c b/board/socrates/nand.c index b8e6e2cd76e..fc0c04efdd1 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -135,7 +135,7 @@ static void sc_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ct break; default: - printf("%s: unknown ctrl %#x\n", __FUNCTION__, ctrl); + printf("%s: unknown ctrl %#x\n", __func__, ctrl); } if (ctrl & NAND_NCE) diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile index d0525eba853..18ada7d72ff 100644 --- a/board/sophgo/milkv_duo/Makefile +++ b/board/sophgo/milkv_duo/Makefile @@ -3,4 +3,4 @@ # Copyright (c) 2024, Kongyang Liu <[email protected]> obj-y += board.o -obj-$(CONFIG_NET) += ethernet.o +obj-$(CONFIG_NET_LEGACY) += ethernet.o diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c index 9adbb08f5ce..f0944859b58 100644 --- a/board/sophgo/milkv_duo/board.c +++ b/board/sophgo/milkv_duo/board.c @@ -12,7 +12,7 @@ int board_init(void) if (IS_ENABLED(CONFIG_SYSRESET_CV1800B)) device_bind_driver(gd->dm_root, "cv1800b_sysreset", "sysreset", NULL); - if (IS_ENABLED(CONFIG_NET)) + if (IS_ENABLED(CONFIG_NET_LEGACY)) cv1800b_ephy_init(); return 0; diff --git a/board/spacemit/bananapi-f3/MAINTAINERS b/board/spacemit/bananapi-f3/MAINTAINERS deleted file mode 100644 index 131bad03181..00000000000 --- a/board/spacemit/bananapi-f3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BananaPi F3 -M: Huan Zhou <pericycle.cc@@gmail.com> -S: Maintained -F: board/spacemit/bananapi-f3/ -F: configs/bananapi-f3_defconfig -F: doc/board/spacemit/bananapi-f3.rst diff --git a/board/spacemit/bananapi-f3/Makefile b/board/spacemit/bananapi-f3/Makefile deleted file mode 100644 index 2168698402b..00000000000 --- a/board/spacemit/bananapi-f3/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# Copyright (c) 2024, Kongyang Liu <[email protected]> - -obj-y := board.o diff --git a/board/spacemit/bananapi-f3/Kconfig b/board/spacemit/k1/Kconfig index f89fa9af2c7..1c615f89b64 100644 --- a/board/spacemit/bananapi-f3/Kconfig +++ b/board/spacemit/k1/Kconfig @@ -1,7 +1,7 @@ -if TARGET_BANANAPI_F3 +if TARGET_SPACEMIT_K1 config SYS_BOARD - default "bananapi-f3" + default "k1" config SYS_VENDOR default "spacemit" @@ -10,7 +10,7 @@ config SYS_CPU default "k1" config SYS_CONFIG_NAME - default "bananapi-f3" + default "k1" config TEXT_BASE default 0x00200000 diff --git a/board/spacemit/k1/MAINTAINERS b/board/spacemit/k1/MAINTAINERS new file mode 100644 index 00000000000..32d47ecc8f1 --- /dev/null +++ b/board/spacemit/k1/MAINTAINERS @@ -0,0 +1,14 @@ +BananaPi F3 +M: Huan Zhou <[email protected]> +M: Guodong Xu <[email protected]> +S: Maintained +F: arch/riscv/dts/k1-*-u-boot.dtsi +F: board/spacemit/k1/ +F: configs/spacemit_k1_defconfig +F: doc/board/spacemit/bananapi-f3.rst +F: drivers/gpio/spacemit_gpio.c +F: drivers/i2c/k1_i2c.c +F: drivers/pinctrl/spacemit/ +F: drivers/power/pmic/pmic_spacemit_p1.c +F: drivers/power/regulator/spacemit_p1_regulator.c diff --git a/board/spacemit/k1/Makefile b/board/spacemit/k1/Makefile new file mode 100644 index 00000000000..a57af2e1f08 --- /dev/null +++ b/board/spacemit/k1/Makefile @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu <[email protected]> +# Copyright (c) 2025-2026, RISCstar Ltd. + +obj-y := board.o +obj-$(CONFIG_SPL_BUILD) += spl.o + +DDR_FW_SRC ?= $(DDR_FW_FILE) +FW_TARGET = $(objtree)/ddr_fw.bin + +$(obj)/spl.o: $(FW_TARGET) + +$(FW_TARGET): FORCE + @if [ -n "$(DDR_FW_SRC)" ] && [ -f "$(DDR_FW_SRC)" ]; then \ + if ! cmp -s "$(DDR_FW_SRC)" $@ 2>/dev/null; then \ + echo " Copying DDR firmware from: $(DDR_FW_SRC)"; \ + cp "$(DDR_FW_SRC)" $@; \ + fi; \ + elif [ -s $@ ]; then \ + : ; \ + else \ + echo " Note: No DDR firmware found, creating empty placeholder"; \ + echo " (Set DDR_FW_FILE to specify firmware location)"; \ + touch $@; \ + fi + +clean-files += $(FW_TARGET) diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/k1/board.c index ea416621544..ea416621544 100644 --- a/board/spacemit/bananapi-f3/board.c +++ b/board/spacemit/k1/board.c diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c new file mode 100644 index 00000000000..d749e21a2d5 --- /dev/null +++ b/board/spacemit/k1/spl.c @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025-2026, RISCstar Ltd. + */ + +#include <asm/io.h> +#include <binman.h> +#include <binman_sym.h> +#include <clk.h> +#include <clk-uclass.h> +#include <cpu_func.h> +#include <configs/k1.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <i2c.h> +#include <linux/ctype.h> +#include <linux/delay.h> +#include <log.h> +#include <power/regulator.h> +#include <spi_flash.h> +#include <spl.h> +#include <tlv_eeprom.h> +#include "tlv_codes.h" + +#define MUX_MODE4 4 +#define EDGE_NONE BIT(6) +#define PULL_UP (6 << 13) /* bit[15:13] 110 */ +#define PAD_DS_MEDIUM BIT(12) +#define PAD_1V8_DS2 PAD_DS_MEDIUM +#define I2C_PIN_CONFIG(x) ((x) | EDGE_NONE | PULL_UP | PAD_1V8_DS2) +#define I2C_BUF_SIZE 64 + +#define MFP_GPIO_84 0xd401e154 +#define MFP_GPIO_85 0xd401e158 + +#define DDR_FIRMWARE_BASE 0xc082d000 + +#define DDR_DEFAULT_CS_NUM 2 +#define DDR_DEFAULT_TYPE "LPDDR4X" +#define DDR_DEFAULT_TX_ODT 80 +#define DDR_DEFAULT_DATA_RATE 2400 + +#define MAGIC_NUM 0xaa55aa55 + +typedef void (*puts_func_t)(const char *s); +typedef int (*ddr_init_func_t)(u64 ddr_base, u32 cs_num, u32 data_rate, + puts_func_t puts); + +struct ddr_cfg { + u32 data_rate; + u32 cs_num; + u32 tx_odt; + u8 type[I2C_BUF_SIZE]; +}; + +binman_sym_declare(ulong, ddr_fw, image_pos); +binman_sym_declare(ulong, ddr_fw, size); + +char product_name[I2C_BUF_SIZE] = "k1"; + +static void i2c_early_init(void) +{ + struct udevice *bus; + + // eeprom: I2C2, pin group(GPIO_84, GPIO_85) + writel(I2C_PIN_CONFIG(MUX_MODE4), (void __iomem *)MFP_GPIO_84); + writel(I2C_PIN_CONFIG(MUX_MODE4), (void __iomem *)MFP_GPIO_85); + udelay(100); + uclass_first_device(UCLASS_I2C, &bus); + while (bus) { + uclass_next_device(&bus); + if (!bus) + break; + } +} + +int read_product_name(char *name, int size) +{ + u8 eeprom_data[TLV_TOTAL_LEN_MAX], *p; + struct tlvinfo_header *tlv_hdr; + struct tlvinfo_tlv *tlv_entry; + int ret, i = 0; + u32 entry_size; + + if (!name || size <= 0) + return -EINVAL; + ret = read_tlvinfo_tlv_eeprom(eeprom_data, &tlv_hdr, + &tlv_entry, i); + if (ret) + return ret; + p = (u8 *)tlv_entry; + for (i = 0; i < tlv_hdr->totallen; ) { + if (tlv_entry->type == TLV_CODE_PRODUCT_NAME) { + if (tlv_entry->length < size) + size = tlv_entry->length; + memset(name, 0, size); + memcpy(name, &tlv_entry->value[0], size); + return 0; + } + if (tlv_entry->type == TLV_CODE_CRC_32) + return -ENOENT; + entry_size = tlv_entry->length + sizeof(struct tlvinfo_tlv); + i += entry_size; + p += entry_size; + tlv_entry = (struct tlvinfo_tlv *)p; + } + return -ENOENT; +} + +static void clk_early_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@d4090000", &dev); + if (ret) + panic("Fail to detect clock-controller@d4090000\n"); + ret = uclass_get_device_by_name(UCLASS_CLK, "system-controller@d4050000", &dev); + if (ret) + panic("Fail to detect system-controller@d4050000\n"); + ret = uclass_get_device_by_name(UCLASS_CLK, "system-controller@d4282800", &dev); + if (ret) + panic("Fail to detect system-controller@d4282800\n"); + ret = uclass_get_device_by_name(UCLASS_CLK, "system-controller@d4015000", &dev); + if (ret) + panic("Fail to detect system-controller@d4015000\n"); + + if (device_active(dev)) + log_debug("clk: device is active\n"); + else + log_debug("clk: device not active, probing...\n"); +} + +void serial_early_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_SERIAL, 0, &dev); + if (ret) + panic("Serial uclass init failed: %d\n", ret); +} + +static void set_vdd_core(void) +{ + struct udevice *dev; + int ret; + + ret = regulator_get_by_platname("vdd_core", &dev); + if (ret) + panic("Fail to detect vdd_core (%d)\n", ret); + ret = regulator_set_enable(dev, true); + if (ret) + log_warning("Fail to enable vdd_core (%d)\n", ret); + ret = regulator_get_value(dev); + if (ret < 0) + log_warning("Fail to read vdd_core (%d)\n", ret); + log_info("vdd_core, value:%d\n", ret); +} + +static void set_vdd_1v8(void) +{ + struct udevice *dev; + int ret; + + ret = regulator_get_by_platname("vdd_1v8", &dev); + if (ret) + panic("Fail to detect vdd_1v8 (%d)\n", ret); + ret = regulator_set_value(dev, 1800000); + if (ret) + log_warning("Fail to set vdd_1v8 as 1800000 (%d)\n", ret); + ret = regulator_set_enable(dev, true); + if (ret) + log_warning("Fail to enable vdd_1v8 (%d)\n", ret); + ret = regulator_get_value(dev); + if (ret < 0) + log_warning("Fail to read vdd_1v8 (%d)\n", ret); + log_info("vdd_1v8, value:%d\n", ret); +} + +static void set_vdd_mmc(void) +{ + struct udevice *dev; + int ret; + + ret = regulator_get_by_platname("vdd_1v8_mmc", &dev); + if (ret) + panic("Fail to detect vdd_1v8_mmc (%d)\n", ret); + ret = regulator_set_value(dev, 1800000); + if (ret) + log_warning("Fail to set vdd_1v8_mmc as 1800000 (%d)\n", ret); + ret = regulator_set_enable(dev, true); + if (ret) + log_warning("Fail to enable vdd_1v8_mmc (%d)\n", ret); + ret = regulator_get_value(dev); + if (ret < 0) + log_warning("Fail to read vdd_1v8_mmc (%d)\n", ret); + log_info("vdd_1v8_mmc, value:%d\n", ret); +} + +void pmic_init(void) +{ + struct udevice *pmic_dev; + int ret; + + ret = uclass_get_device(UCLASS_PMIC, 0, &pmic_dev); + if (ret) + panic("Fail to detect PMIC (%d)\n", ret); + set_vdd_core(); + set_vdd_1v8(); + set_vdd_mmc(); +} + +/* Set default value for DDR chips */ +static void ddr_cfg_init(struct ddr_cfg *cfg) +{ + memset(cfg, 0, sizeof(struct ddr_cfg)); + cfg->data_rate = DDR_DEFAULT_DATA_RATE; + cfg->cs_num = DDR_DEFAULT_CS_NUM; + cfg->tx_odt = DDR_DEFAULT_TX_ODT; + strcpy(cfg->type, DDR_DEFAULT_TYPE); +} + +int read_ddr_info(struct ddr_cfg *cfg) +{ + u8 eeprom_data[TLV_TOTAL_LEN_MAX], *p; + struct tlvinfo_header *tlv_hdr; + struct tlvinfo_tlv *tlv_entry; + u32 size, entry_size; + int ret, i; + bool found = false; + + if (!cfg) + return -EINVAL; + ddr_cfg_init(cfg); + ret = read_tlvinfo_tlv_eeprom(eeprom_data, &tlv_hdr, + &tlv_entry, i); + if (ret) + return ret; + p = (u8 *)tlv_entry; + for (i = 0; i < tlv_hdr->totallen; ) { + switch (tlv_entry->type) { + case TLV_CODE_DDR_CSNUM: + memcpy(&cfg->cs_num, &tlv_entry->value[0], 1); + found = true; + break; + case TLV_CODE_DDR_TYPE: + size = min((u32)tlv_entry->length, (u32)I2C_BUF_SIZE); + memcpy(&cfg->type[0], &tlv_entry->value[0], size); + found = true; + break; + case TLV_CODE_DDR_DATARATE: + memcpy(&cfg->data_rate, &tlv_entry->value[0], 2); + found = true; + break; + case TLV_CODE_DDR_TX_ODT: + memcpy(&cfg->tx_odt, &tlv_entry->value[0], 1); + found = true; + break; + case TLV_CODE_CRC_32: + if (!found) + return -ENOENT; + return 0; + } + entry_size = tlv_entry->length + sizeof(struct tlvinfo_tlv); + i += entry_size; + p += entry_size; + tlv_entry = (struct tlvinfo_tlv *)p; + } + if (!found) + return -ENOENT; + return 0; +} + +void ddr_early_init(void) +{ + void __iomem *src, *dst; + ulong pos, size; + struct ddr_cfg cfg; + ddr_init_func_t ddr_init; + + pos = binman_sym(ulong, ddr_fw, image_pos); + size = binman_sym(ulong, ddr_fw, size); + src = (void __iomem *)pos; + dst = (void __iomem *)(DDR_FIRMWARE_BASE); + log_info("DDR firmware: [0x%lx]:0x%x, size:0x%lx\n", pos, readl(src), size); + memcpy((u8 *)dst, (u8 *)src, size); + size = round_up(size, 64); + /* + * Ensure the just-written DDR firmware bytes are observable in the + * instruction stream. RISC-V's fence.i alone is sufficient for the + * single-hart SPL case; skip flush_dcache_range as cbo.flush may + * trap on our current privilege state. + */ + asm volatile ("fence.i" ::: "memory"); + + read_ddr_info(&cfg); + ddr_init = (ddr_init_func_t)DDR_FIRMWARE_BASE; +#ifdef DEBUG + ddr_init(0xc0000000, cfg.cs_num, cfg.data_rate, puts); +#else + ddr_init(0xc0000000, cfg.cs_num, cfg.data_rate, NULL); +#endif + writel(MAGIC_NUM, (void __iomem *)0x00000000); + flush_dcache_range(0, 64); + invalidate_dcache_range(0, 64); + if (readl((void __iomem *)0x00000000) == MAGIC_NUM) + log_info("DDR is ready\n"); + else + log_info("DDR is not ready\n"); +} + +void nor_early_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_SPI, 0, &dev); + if (ret) + panic("Fail to detect spi controller.\n"); + udelay(10); + ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev); + if (ret) + log_info("Fail to detect spi nor flash.\n"); + udelay(10); +} + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed:%d\n", ret); + + riscv_cpu_setup(); + + clk_early_init(); + serial_early_init(); + + preloader_console_init(); + + i2c_early_init(); + ret = read_product_name(product_name, I2C_BUF_SIZE); + if (ret) + log_info("Fail to detect board:%d\n", ret); + else + log_info("Get board name:%s\n", product_name); + pmic_init(); + + ddr_early_init(); + nor_early_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_SPI; +} + +void spl_board_init(void) +{ +} + +int board_fit_config_name_match(const char *name) +{ + char fdt_name[I2C_BUF_SIZE]; + int i; + + memset(fdt_name, 0, I2C_BUF_SIZE); + if (!strncmp(product_name, "k1-x_", 5)) { + snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1", + &product_name[5]); + } + if (fdt_name[0] == '\0') { + /* set default board name */ + sprintf(fdt_name, "k1-musepi-pro"); + } + for (i = 0; i < I2C_BUF_SIZE; i++) { + if (fdt_name[i] == '\0') + break; + fdt_name[i] = tolower(fdt_name[i]); + } + if (!strcmp(name, fdt_name)) + return 0; + return -ENOENT; +} + +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS; +} diff --git a/board/spacemit/k1/tlv_codes.h b/board/spacemit/k1/tlv_codes.h new file mode 100644 index 00000000000..e40fbdcee6d --- /dev/null +++ b/board/spacemit/k1/tlv_codes.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +#ifndef __TLV_CODES_H +#define __TLV_CODES_H + +#define TLV_CODE_SDK_VERSION 0x40 +#define TLV_CODE_DDR_CSNUM 0x41 +#define TLV_CODE_DDR_TYPE 0x42 +#define TLV_CODE_DDR_DATARATE 0x43 +#define TLV_CODE_DDR_TX_ODT 0x44 + +#define TLV_CODE_WIFI_MAC_ADDR 0x60 +#define TLV_CODE_BLUETOOTH_ADDR 0x61 + +#define TLV_CODE_PMIC_TYPE 0x80 +#define TLV_CODE_EEPROM_I2C_INDEX 0x81 +#define TLV_CODE_EEPROM_PIN_GROUP 0x82 + +#endif /* __TLV_CODES_H */ diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig index 3d00f3f3331..aafbffbf6db 100644 --- a/board/st/common/Kconfig +++ b/board/st/common/Kconfig @@ -14,7 +14,7 @@ config DFU_ALT_RAM0 This defines the partitions of ram used to build dfu dynamically. config TYPEC_STUSB160X - tristate "STMicroelectronics STUSB160X Type-C controller driver" + bool "STMicroelectronics STUSB160X Type-C controller driver" depends on DM_I2C help Say Y if your system has STMicroelectronics STUSB160X Type-C port diff --git a/board/st/common/MAINTAINERS b/board/st/common/MAINTAINERS index 0c6db547725..e87284c6a8b 100644 --- a/board/st/common/MAINTAINERS +++ b/board/st/common/MAINTAINERS @@ -1,6 +1,6 @@ ST BOARDS M: Patrick Delaunay <[email protected]> L: [email protected] (moderated for non-subscribers) -T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-stm.git S: Maintained F: board/st/common/ diff --git a/board/st/common/Makefile b/board/st/common/Makefile index 122b13c3aa8..36dfaddfa0e 100644 --- a/board/st/common/Makefile +++ b/board/st/common/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o ifeq ($(CONFIG_ARCH_STM32MP),y) obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o obj-$(CONFIG_$(PHASE_)DFU_VIRT) += stm32mp_dfu_virt.o +obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += stm32mp_fwu.o endif obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o diff --git a/board/st/common/stm32mp_fwu.c b/board/st/common/stm32mp_fwu.c new file mode 100644 index 00000000000..ac7ca6bdca2 --- /dev/null +++ b/board/st/common/stm32mp_fwu.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <[email protected]> + */ + +#include <fwu.h> +#include <part_efi.h> +#include <asm/io.h> +/** + * fwu_plat_get_bootidx() - Get the value of the boot index + * @boot_idx: Boot index value + * + * Get the value of the bank(partition) from which the platform + * has booted. This value is passed to U-Boot from the earlier + * stage bootloader which loads and boots all the relevant + * firmware images + * + */ +void fwu_plat_get_bootidx(uint *boot_idx) +{ + *boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >> + TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; +} + +int fwu_platform_hook(struct udevice *dev, struct fwu_data *data) +{ + uint boot_idx; + efi_guid_t boot_uuid, root_uuid; + const efi_guid_t boot_type_guid = PARTITION_XBOOTLDR; + const efi_guid_t root_type_guid = + PARTITION_LINUX_FILE_SYSTEM_DATA_GUID; + char uuidbuf[UUID_STR_LEN + 1]; + int retb, retr; + + fwu_plat_get_bootidx(&boot_idx); + + retb = fwu_mdata_get_image_guid(&boot_uuid, &boot_type_guid, boot_idx); + retr = fwu_mdata_get_image_guid(&root_uuid, &root_type_guid, boot_idx); + + if (!retb && !retr) { + uuid_bin_to_str(boot_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID); + env_set("boot_partuuid", uuidbuf); + + uuid_bin_to_str(root_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID); + env_set("root_partuuid", uuidbuf); + } else if (!retb && retr) { + log_warning("%s: found boot GUID but missing root GUID (%d)\n", + __func__, retr); + } else if (!retr && retb) { + log_warning("%s: found root GUID but missing boot GUID (%d)\n", + __func__, retb); + } + + return 0; +} diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index f5174720434..a1b0265d5ac 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -18,8 +18,8 @@ int dram_init(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->dram[0].start = PHYS_SDRAM_1; + gd->dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 244bb5eefb3..8b1b2333779 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -32,11 +32,6 @@ int dram_init_banksize(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - int board_late_init(void) { return 0; diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index f924e61b3c0..f488361ab47 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -2,7 +2,7 @@ STM32MP1 BOARD M: Patrick Delaunay <[email protected]> M: Patrice Chotard <[email protected]> L: [email protected] (moderated for non-subscribers) -T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-stm.git S: Maintained F: arch/arm/dts/stm32mp13* F: arch/arm/dts/stm32mp15* diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 5f7c6822116..9b933a2ba0b 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -326,8 +326,8 @@ static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV) static int board_check_usb_power(void) { ofnode node; - int max_uV = 0; - int min_uV = USB_START_HIGH_THRESHOLD_UV; + int max_uV; + int min_uV; int adc_count, ret; u32 nb_blink; u8 i; @@ -358,6 +358,9 @@ static int board_check_usb_power(void) /* perform maximum of 2 ADC measurements to detect power supply current */ for (i = 0; i < 2; i++) { + max_uV = 0; + min_uV = USB_START_HIGH_THRESHOLD_UV; + ret = adc_measurement(node, adc_count, &min_uV, &max_uV); if (ret) return ret; @@ -834,24 +837,3 @@ static void board_copro_image_process(ulong fw_image, size_t fw_size) } U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); - -#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) - -#include <fwu.h> - -/** - * fwu_plat_get_bootidx() - Get the value of the boot index - * @boot_idx: Boot index value - * - * Get the value of the bank(partition) from which the platform - * has booted. This value is passed to U-Boot from the earlier - * stage bootloader which loads and boots all the relevant - * firmware images - * - */ -void fwu_plat_get_bootidx(uint *boot_idx) -{ - *boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >> - TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; -} -#endif /* CONFIG_FWU_MULTI_BANK_UPDATE */ diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c index 43bc583378e..7bc7d2a608f 100644 --- a/board/st/stm32mp2/stm32mp2.c +++ b/board/st/stm32mp2/stm32mp2.c @@ -188,24 +188,3 @@ void board_quiesce_devices(void) { led_boot_off(); } - -#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) - -#include <fwu.h> - -/** - * fwu_plat_get_bootidx() - Get the value of the boot index - * @boot_idx: Boot index value - * - * Get the value of the bank(partition) from which the platform - * has booted. This value is passed to U-Boot from the earlier - * stage bootloader which loads and boots all the relevant - * firmware images - * - */ -void fwu_plat_get_bootidx(uint *boot_idx) -{ - *boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >> - TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; -} -#endif /* CONFIG_FWU_MULTI_BANK_UPDATE */ diff --git a/board/ste/stemmy/stemmy.c b/board/ste/stemmy/stemmy.c index 826c002907d..66330184af8 100644 --- a/board/ste/stemmy/stemmy.c +++ b/board/ste/stemmy/stemmy.c @@ -70,8 +70,8 @@ int dram_init_banksize(void) if (t->hdr.tag != ATAG_MEM) continue; - gd->bd->bi_dram[bank].start = t->u.mem.start; - gd->bd->bi_dram[bank].size = t->u.mem.size; + gd->dram[bank].start = t->u.mem.start; + gd->dram[bank].size = t->u.mem.size; if (++bank == CONFIG_NR_DRAM_BANKS) break; } diff --git a/board/sunxi/board.c b/board/sunxi/board.c index d7722d1858a..3d1afec7c66 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -563,8 +563,8 @@ static void sunxi_spl_store_dram_size(phys_addr_t dram_size) static void status_led_init(void) { #if CONFIG_IS_ENABLED(SUNXI_LED_STATUS) - unsigned int state = CONFIG_SPL_SUNXI_LED_STATUS_STATE; - unsigned int gpio = CONFIG_SPL_SUNXI_LED_STATUS_BIT; + unsigned int state = IS_ENABLED(CONFIG_SPL_SUNXI_LED_STATUS_ACTIVE_HIGH); + unsigned int gpio = CONFIG_SPL_SUNXI_LED_STATUS_GPIO; gpio_request(gpio, "gpio_led"); gpio_direction_output(gpio, state); diff --git a/board/sysam/amcore/Kconfig b/board/sysam/amcore/Kconfig index b5c81dda237..7efd857dc32 100644 --- a/board/sysam/amcore/Kconfig +++ b/board/sysam/amcore/Kconfig @@ -4,13 +4,13 @@ config SYS_CPU default "mcf530x" config SYS_BOARD - default "amcore" + default "amcore" config SYS_VENDOR - default "sysam" + default "sysam" config SYS_CONFIG_NAME - default "amcore" + default "amcore" endif diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c index c9d68b402ae..eed7f70e833 100644 --- a/board/technexion/pico-imx8mq/spl.c +++ b/board/technexion/pico-imx8mq/spl.c @@ -10,7 +10,6 @@ #include <asm/arch/ddr.h> #include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/gpio.h> #include <asm/mach-imx/iomux-v3.h> @@ -24,8 +23,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - #define DDR_DET_1 IMX_GPIO_NR(3, 11) #define DDR_DET_2 IMX_GPIO_NR(3, 12) #define DDR_DET_3 IMX_GPIO_NR(3, 13) @@ -196,9 +193,6 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - arch_cpu_init(); init_uart_clk(0); diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 2f5ad769b9b..e5c78e9c064 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -20,7 +20,7 @@ #include <asm/arch/soc.h> #include <linux/delay.h> #include <linux/mbus.h> -#ifdef CONFIG_NET +#ifdef CONFIG_NET_LEGACY #include <netdev.h> #endif #include <u-boot/crc.h> @@ -244,7 +244,7 @@ int checkboard(void) return 0; } -#ifdef CONFIG_NET +#ifdef CONFIG_NET_LEGACY int board_eth_init(struct bd_info *bis) { cpu_eth_init(bis); /* Built in controller(s) come first */ diff --git a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c index 3f484646701..5177aa9d6e8 100644 --- a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c +++ b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c @@ -54,6 +54,8 @@ int rockchip_early_misc_init_r(void) #define GPIO0B7_PU_EN BIT(15) +#define M2_NVME_PERSTN 24 /* GPIO0_D0, PERSTN signal to the M.2 NVMe slot */ + void spl_board_init(void) { /* @@ -67,6 +69,24 @@ void spl_board_init(void) * pull-up. */ struct rk3588_pmu2_ioc * const ioc = (void *)PMU2_IOC_BASE; + int ret; + /* TODO: once we have a U-Boot TPL, move this to tpl_board_init() */ rk_setreg(&ioc->gpio0b_p, GPIO0B7_PU_EN); + + /* + * Set the M.2 NVMe slot PERSTN to a defined low + * state as early as possible + */ + ret = gpio_request(M2_NVME_PERSTN, "M2_NVME_PERSTN"); + if (ret) { + log_err("M2_NVME_PERSTN: gpio request failed: %d\n", ret); + return; + } + + ret = gpio_direction_output(M2_NVME_PERSTN, 0); + if (ret) { + log_err("M2_NVME_PERSTN: gpio direction set failed: %d\n", ret); + return; + } } diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 90e37a8d913..4a2d7655d2a 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -28,6 +28,7 @@ #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> +#include <asm/arch/mux.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/emif.h> @@ -72,6 +73,12 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024) #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024) +static __maybe_unused struct module_pin_mux rmii1_mdio_pin_mux[] = { + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {-1}, +}; + /* * Read header information from EEPROM into global structure. */ @@ -779,6 +786,9 @@ int board_init(void) hang(); } + if (!eth0_is_mii) + configure_module_pin_mux(rmii1_mdio_pin_mux); + prueth_is_mii = eth0_is_mii; /* disable rising edge IRQs */ @@ -911,7 +921,7 @@ int board_late_init(void) #endif /* CPSW plat */ -#if (CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP)) && \ +#if CONFIG_IS_ENABLED(NET) && \ !CONFIG_IS_ENABLED(OF_CONTROL) struct cpsw_slave_data slave_data[] = { { diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index d2d87c304f6..36d849d2119 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -190,8 +190,6 @@ static struct module_pin_mux mii1_pin_mux[] = { }; static struct module_pin_mux rmii1_pin_mux[] = { - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */ {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */ diff --git a/board/ti/am57xx/am57xx.env b/board/ti/am57xx/am57xx.env index a7cbbced099..4f712c5575a 100644 --- a/board/ti/am57xx/am57xx.env +++ b/board/ti/am57xx/am57xx.env @@ -2,6 +2,7 @@ #include <env/ti/mmc.env> #include <env/ti/dfu.env> +bootm_size=0x10000000 bootpart=0:2 bootdir=/boot get_name_kern= diff --git a/board/ti/am62ax/Kconfig b/board/ti/am62ax/Kconfig index 51e7b3e0eab..a80ea9149b1 100644 --- a/board/ti/am62ax/Kconfig +++ b/board/ti/am62ax/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "am62ax" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am62ax_evm" diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index 4916eec3b2b..adb784e69a8 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -6,6 +6,7 @@ * */ +#include <image.h> #include <asm/arch/hardware.h> #include <asm/io.h> #include <dm/uclass.h> @@ -17,6 +18,11 @@ #include "../common/fdt_ops.h" #include "../common/k3_32k_lfosc.h" +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} + #if defined(CONFIG_XPL_BUILD) void spl_perform_board_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/am62ax/rm-cfg.yaml b/board/ti/am62ax/rm-cfg.yaml index 4e238883b96..36b0049f43a 100644 --- a/board/ti/am62ax/rm-cfg.yaml +++ b/board/ti/am62ax/rm-cfg.yaml @@ -244,7 +244,7 @@ rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 1064 + resasg_entries_size: 1176 reserved: 0 resasg_entries: - @@ -705,13 +705,25 @@ rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 64 + num_resource: 32 type: 1937 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 64 + num_resource: 32 + type: 1937 + host_id: 36 + reserved: 0 + - + start_resource: 51 + num_resource: 32 + type: 1937 + host_id: 12 + reserved: 0 + - + start_resource: 51 + num_resource: 32 type: 1937 host_id: 30 reserved: 0 @@ -759,13 +771,25 @@ rm-cfg: reserved: 0 - start_resource: 118 - num_resource: 16 + num_resource: 6 type: 1943 host_id: 12 reserved: 0 - start_resource: 118 - num_resource: 16 + num_resource: 6 + type: 1943 + host_id: 36 + reserved: 0 + - + start_resource: 124 + num_resource: 10 + type: 1943 + host_id: 12 + reserved: 0 + - + start_resource: 124 + num_resource: 10 type: 1943 host_id: 30 reserved: 0 @@ -825,13 +849,25 @@ rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 8 + num_resource: 4 type: 1956 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 8 + num_resource: 4 + type: 1956 + host_id: 36 + reserved: 0 + - + start_resource: 23 + num_resource: 4 + type: 1956 + host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 4 type: 1956 host_id: 30 reserved: 0 @@ -917,17 +953,29 @@ rm-cfg: start_resource: 19 num_resource: 1 type: 1963 - host_id: 30 + host_id: 36 reserved: 0 - start_resource: 19 - num_resource: 16 + num_resource: 6 type: 1964 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 16 + num_resource: 6 + type: 1964 + host_id: 36 + reserved: 0 + - + start_resource: 25 + num_resource: 10 + type: 1964 + host_id: 12 + reserved: 0 + - + start_resource: 25 + num_resource: 10 type: 1964 host_id: 30 reserved: 0 @@ -1012,22 +1060,58 @@ rm-cfg: - start_resource: 0 num_resource: 6 + type: 12750 + host_id: 36 + reserved: 0 + - + start_resource: 0 + num_resource: 6 type: 12769 host_id: 12 reserved: 0 - start_resource: 0 - num_resource: 8 + num_resource: 6 + type: 12769 + host_id: 36 + reserved: 0 + - + start_resource: 0 + num_resource: 5 type: 12810 host_id: 12 reserved: 0 - + start_resource: 5 + num_resource: 3 + type: 12810 + host_id: 35 + reserved: 0 + - + start_resource: 5 + num_resource: 3 + type: 12810 + host_id: 36 + reserved: 0 + - start_resource: 12288 - num_resource: 128 + num_resource: 64 type: 12813 host_id: 12 reserved: 0 - + start_resource: 12352 + num_resource: 64 + type: 12813 + host_id: 35 + reserved: 0 + - + start_resource: 12352 + num_resource: 64 + type: 12813 + host_id: 36 + reserved: 0 + - start_resource: 3072 num_resource: 6 type: 12828 diff --git a/board/ti/am62ax/tifs-rm-cfg.yaml b/board/ti/am62ax/tifs-rm-cfg.yaml index 78bbab38bb6..3706fac8664 100644 --- a/board/ti/am62ax/tifs-rm-cfg.yaml +++ b/board/ti/am62ax/tifs-rm-cfg.yaml @@ -244,7 +244,7 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 880 + resasg_entries_size: 976 reserved: 0 resasg_entries: - @@ -585,13 +585,25 @@ tifs-rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 64 + num_resource: 32 type: 1937 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 64 + num_resource: 32 + type: 1937 + host_id: 36 + reserved: 0 + - + start_resource: 51 + num_resource: 32 + type: 1937 + host_id: 12 + reserved: 0 + - + start_resource: 51 + num_resource: 32 type: 1937 host_id: 30 reserved: 0 @@ -639,13 +651,25 @@ tifs-rm-cfg: reserved: 0 - start_resource: 118 - num_resource: 16 + num_resource: 6 type: 1943 host_id: 12 reserved: 0 - start_resource: 118 - num_resource: 16 + num_resource: 6 + type: 1943 + host_id: 36 + reserved: 0 + - + start_resource: 124 + num_resource: 10 + type: 1943 + host_id: 12 + reserved: 0 + - + start_resource: 124 + num_resource: 10 type: 1943 host_id: 30 reserved: 0 @@ -705,13 +729,25 @@ tifs-rm-cfg: reserved: 0 - start_resource: 19 - num_resource: 8 + num_resource: 4 type: 1956 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 8 + num_resource: 4 + type: 1956 + host_id: 36 + reserved: 0 + - + start_resource: 23 + num_resource: 4 + type: 1956 + host_id: 12 + reserved: 0 + - + start_resource: 23 + num_resource: 4 type: 1956 host_id: 30 reserved: 0 @@ -797,17 +833,29 @@ tifs-rm-cfg: start_resource: 19 num_resource: 1 type: 1963 - host_id: 30 + host_id: 36 reserved: 0 - start_resource: 19 - num_resource: 16 + num_resource: 6 type: 1964 host_id: 12 reserved: 0 - start_resource: 19 - num_resource: 16 + num_resource: 6 + type: 1964 + host_id: 36 + reserved: 0 + - + start_resource: 25 + num_resource: 10 + type: 1964 + host_id: 12 + reserved: 0 + - + start_resource: 25 + num_resource: 10 type: 1964 host_id: 30 reserved: 0 @@ -880,16 +928,40 @@ tifs-rm-cfg: - start_resource: 0 num_resource: 6 + type: 12750 + host_id: 36 + reserved: 0 + - + start_resource: 0 + num_resource: 6 type: 12769 host_id: 12 reserved: 0 - start_resource: 0 - num_resource: 8 + num_resource: 6 + type: 12769 + host_id: 36 + reserved: 0 + - + start_resource: 0 + num_resource: 5 type: 12810 host_id: 12 reserved: 0 - + start_resource: 5 + num_resource: 3 + type: 12810 + host_id: 35 + reserved: 0 + - + start_resource: 5 + num_resource: 3 + type: 12810 + host_id: 36 + reserved: 0 + - start_resource: 3072 num_resource: 6 type: 12828 diff --git a/board/ti/am62px/Kconfig b/board/ti/am62px/Kconfig index 9d95ffd9b29..1011b89d75f 100644 --- a/board/ti/am62px/Kconfig +++ b/board/ti/am62px/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "am62px" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am62px_evm" diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 8fde47fb1be..9fa0a1c9f72 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -7,6 +7,7 @@ */ #include <efi_loader.h> +#include <image.h> #include <asm/arch/hardware.h> #include <asm/io.h> #include <cpu_func.h> @@ -43,6 +44,11 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} + #if IS_ENABLED(CONFIG_SPL_BUILD) void spl_board_init(void) { diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig index 610dacfdc08..eb54154d1ce 100644 --- a/board/ti/am62x/Kconfig +++ b/board/ti/am62x/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "am62x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am62x_evm" @@ -24,7 +24,7 @@ config SYS_BOARD default "am62x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am62x_evm" diff --git a/board/ti/am62x/am6254atl.env b/board/ti/am62x/am6254atl.env index ea5a33d8cc3..a9187c2b1aa 100644 --- a/board/ti/am62x/am6254atl.env +++ b/board/ti/am62x/am6254atl.env @@ -27,10 +27,6 @@ splashimage=0x82180000 splashpos=m,m splashsource=sf -dfu_alt_info_ram= - tispl.bin ram 0x82000000 0x200000; - u-boot.img ram 0x82f80000 0x400000 - #if CONFIG_BOOTMETH_ANDROID #include <env/ti/android.env> adtb_idx=0 diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 49e58ad6d6c..90beed341b6 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -18,6 +18,7 @@ #include <fdt_support.h> #include <fdt_simplefb.h> #include <asm/io.h> +#include <image.h> #include <asm/arch/hardware.h> #include <dm/uclass.h> #include <asm/arch/k3-ddr.h> @@ -135,6 +136,11 @@ int board_late_init(void) } #endif +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} + #if defined(CONFIG_XPL_BUILD) void spl_board_init(void) { diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig index b873476a9d5..c727b7f8c16 100644 --- a/board/ti/am64x/Kconfig +++ b/board/ti/am64x/Kconfig @@ -8,7 +8,7 @@ config SYS_BOARD default "am64x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am64x_evm" @@ -23,7 +23,7 @@ config SYS_BOARD default "am64x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am64x_evm" diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index eb47a25c70a..fe3fa13dc4b 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "am65x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am65x_evm" @@ -24,7 +24,7 @@ config SYS_BOARD default "am65x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am65x_evm" diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 149909093b3..6762d08d400 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -1,8 +1,8 @@ config TI_I2C_BOARD_DETECT bool "Support for Board detection for TI platforms" help - Support for detection board information on Texas Instrument's - Evaluation Boards which have I2C based EEPROM detection + Support for detection board information on Texas Instrument's + Evaluation Boards which have I2C based EEPROM detection config EEPROM_BUS_ADDRESS int "Board EEPROM's I2C bus address" diff --git a/board/ti/common/cape_detect.c b/board/ti/common/cape_detect.c index 88fa6ae81f0..65bd6ef39ec 100644 --- a/board/ti/common/cape_detect.c +++ b/board/ti/common/cape_detect.c @@ -13,6 +13,44 @@ #include "cape_detect.h" +struct name_mapping { + char part_number[17]; + char version[5]; + char overlay[64]; +}; + +static struct name_mapping extension_mapping[] = { + { + "BB-GREEN-HDMI", + "00A0", + "am335x-bone-hdmi-00a0.dtbo", + } +}; + +static void set_cape_overlay(char *overlay, char *part_number, char *version) +{ + struct name_mapping *mapping; + + for (int i = 0; i < ARRAY_SIZE(extension_mapping); i++) { + mapping = &extension_mapping[i]; + + if (strncmp(mapping->part_number, part_number, + sizeof(mapping->part_number))) + continue; + + if (strncmp(mapping->version, version, + sizeof(mapping->version))) + continue; + + strlcpy(overlay, mapping->overlay, sizeof(mapping->overlay)); + return; + } + + /* Use default name extracted from the EEPROM */ + snprintf(overlay, sizeof(extension_mapping[0].overlay), "%s-%s.dtbo", + part_number, version); +} + static void sanitize_field(char *text, size_t size) { char *c = NULL; @@ -82,8 +120,8 @@ static int ti_extension_board_scan(struct udevice *dev, printf("BeagleBone Cape: %s (0x%x)\n", eeprom_header.board_name, addr); - snprintf(cape.overlay, sizeof(cape.overlay), "%s-%s.dtbo", - process_cape_part_number, process_cape_version); + set_cape_overlay(cape.overlay, process_cape_part_number, + process_cape_version); strlcpy(cape.name, eeprom_header.board_name, sizeof(eeprom_header.board_name)); strlcpy(cape.version, process_cape_version, diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 0966db2bb62..6f1fed43e36 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -643,11 +643,11 @@ int dram_init_banksize(void) ram_size = board_ti_get_emif_size(); - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); if (ram_size > CFG_MAX_MEM_MAPPED) { - gd->bd->bi_dram[1].start = 0x200000000; - gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; + gd->dram[1].start = 0x200000000; + gd->dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; } return 0; diff --git a/board/ti/j7200/Kconfig b/board/ti/j7200/Kconfig index 093d23e7bf8..38edbe12968 100644 --- a/board/ti/j7200/Kconfig +++ b/board/ti/j7200/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j7200" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721e_evm" @@ -27,7 +27,7 @@ config SYS_BOARD default "j7200" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721e_evm" diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index 7c7e23988d8..d85056e65bb 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j721e" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721e_evm" @@ -27,7 +27,7 @@ config SYS_BOARD default "j721e" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721e_evm" diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig index 40853a8fd66..34a3e6ef187 100644 --- a/board/ti/j721s2/Kconfig +++ b/board/ti/j721s2/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j721s2" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721s2_evm" @@ -27,7 +27,7 @@ config SYS_BOARD default "j721s2" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721s2_evm" diff --git a/board/ti/j722s/Kconfig b/board/ti/j722s/Kconfig index 68c214e473b..e819ba2f554 100644 --- a/board/ti/j722s/Kconfig +++ b/board/ti/j722s/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j722s" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j722s_evm" diff --git a/board/ti/j722s/sec-cfg.yaml b/board/ti/j722s/sec-cfg.yaml index e9a9d526cfb..b68b305b6bb 100644 --- a/board/ti/j722s/sec-cfg.yaml +++ b/board/ti/j722s/sec-cfg.yaml @@ -16,9 +16,9 @@ sec-cfg: size: 164 proc_acl_entries: - - processor_id: 0 - proc_access_master: 0 - proc_access_secondary: [0, 0, 0] + processor_id: 0x1 + proc_access_master: 0x23 + proc_access_secondary: [0xC, 0, 0] - processor_id: 0 proc_access_master: 0 diff --git a/board/ti/j784s4/Kconfig b/board/ti/j784s4/Kconfig index de95ac575d7..40c4913aea1 100644 --- a/board/ti/j784s4/Kconfig +++ b/board/ti/j784s4/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j784s4" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j784s4_evm" @@ -24,7 +24,7 @@ config SYS_BOARD default "j784s4" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j784s4_evm" @@ -42,7 +42,7 @@ config SYS_BOARD default "j784s4" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j784s4_evm" @@ -57,7 +57,7 @@ config SYS_BOARD default "j784s4" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j784s4_evm" diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index a92aa5cfc67..43330993955 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -117,8 +117,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) } nbanks = 1; - start[0] = bd->bi_dram[0].start; - size[0] = bd->bi_dram[0].size; + start[0] = gd->dram[0].start; + size[0] = gd->dram[0].size; /* adjust memory start address for LPAE */ if (lpae) { diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig index c6ff387351c..fc4cbe3323c 100644 --- a/board/toradex/apalis_imx6/Kconfig +++ b/board/toradex/apalis_imx6/Kconfig @@ -35,7 +35,7 @@ config TDX_CMD_IMX_MFGR bool "Enable factory testing commands for Toradex iMX 6 modules" help This adds the commands - pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 + pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 If executed on already fused modules it doesn't change any fuse setting. default y @@ -43,11 +43,11 @@ config TDX_APALIS_IMX6_V1_0 bool "Apalis iMX6 V1.0 HW" help Apalis iMX6 V1.0 HW has a different pinout for the UART. - The UARTs must be used in DCE mode, RTS/CTS are swapped and - thus unusable on standard carrier boards. - This option configures DCE mode unconditionally. Whithout this - option the config block stating V1.0 HW selects DCE mode, - otherwise the UARTs are configuered in DTE mode. + The UARTs must be used in DCE mode, RTS/CTS are swapped and + thus unusable on standard carrier boards. + This option configures DCE mode unconditionally. Whithout this + option the config block stating V1.0 HW selects DCE mode, + otherwise the UARTs are configuered in DTE mode. source "board/toradex/common/Kconfig" diff --git a/board/toradex/aquila-am69/Kconfig b/board/toradex/aquila-am69/Kconfig index 6afa97e2c82..b44b9247603 100644 --- a/board/toradex/aquila-am69/Kconfig +++ b/board/toradex/aquila-am69/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "aquila-am69" config SYS_VENDOR - default "toradex" + default "toradex" config SYS_CONFIG_NAME default "aquila-am69" @@ -48,7 +48,7 @@ config SYS_BOARD default "aquila-am69" config SYS_VENDOR - default "toradex" + default "toradex" config SYS_CONFIG_NAME default "aquila-am69" diff --git a/board/toradex/aquila-am69/MAINTAINERS b/board/toradex/aquila-am69/MAINTAINERS index f629ba4a019..014e7e99b0b 100644 --- a/board/toradex/aquila-am69/MAINTAINERS +++ b/board/toradex/aquila-am69/MAINTAINERS @@ -3,9 +3,7 @@ M: Francesco Dolcini <[email protected]> W: https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 S: Maintained F: arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi -F: arch/arm/dts/k3-am69-aquila-dev.dts F: arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi -F: arch/arm/dts/k3-am69-aquila.dtsi F: arch/arm/dts/k3-am69-r5-aquila-dev.dts F: board/toradex/aquila-am69 F: configs/aquila-am69_a72_defconfig diff --git a/board/toradex/aquila-am69/aquila-am69.c b/board/toradex/aquila-am69/aquila-am69.c index 0c7123a059e..45fba1bbfe8 100644 --- a/board/toradex/aquila-am69/aquila-am69.c +++ b/board/toradex/aquila-am69/aquila-am69.c @@ -15,6 +15,7 @@ #include <i2c.h> #include <linux/sizes.h> #include <spl.h> +#include <asm/arch/k3-ddr.h> #include "../common/tdx-common.h" #include "aquila_ddrs.h" @@ -30,46 +31,24 @@ #define HW_CFG_MEM_CFG_MASK 0x03 DECLARE_GLOBAL_DATA_PTR; -static u8 hw_cfg; -static u8 aquila_am69_memory_cfg(void) -{ - return hw_cfg & HW_CFG_MEM_CFG_MASK; -} - -static u64 aquila_am69_memory_size(void) -{ - switch (aquila_am69_memory_cfg()) { - case HW_CFG_MEM_SZ_32GB: - return SZ_32G; - case HW_CFG_MEM_SZ_16GB_RANK_2: - case HW_CFG_MEM_SZ_16GB: - return SZ_16G; - case HW_CFG_MEM_SZ_8GB: - return SZ_8G; - default: - puts("Invalid memory size configuration\n"); - return -EINVAL; - } -} - -static void read_hw_cfg(void) +static u8 get_hw_cfg(void) { struct gpio_desc gpio_hw_cfg; char gpio_name[20]; + u8 hw_cfg = 0; int i; - printf("HW CFG: "); for (i = 0; i < 5; i++) { sprintf(gpio_name, "gpio@42110000_%d", 82 + i); if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) { printf("Lookup named gpio error\n"); - return; + return 0; } if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) { printf("gpio request error\n"); - return; + return 0; } if (dm_gpio_get_value(&gpio_hw_cfg) == 1) @@ -77,15 +56,34 @@ static void read_hw_cfg(void) dm_gpio_free(NULL, &gpio_hw_cfg); } - printf("0x%02x\n", hw_cfg); + return hw_cfg; } -static void update_ddr_timings(void) +static u64 aquila_am69_memory_size(void) +{ + u8 hw_cfg = get_hw_cfg(); + + switch (hw_cfg & HW_CFG_MEM_CFG_MASK) { + case HW_CFG_MEM_SZ_32GB: + return SZ_32G; + case HW_CFG_MEM_SZ_16GB_RANK_2: + case HW_CFG_MEM_SZ_16GB: + return SZ_16G; + case HW_CFG_MEM_SZ_8GB: + return SZ_8G; + default: + puts("Invalid memory size configuration\n"); + return -EINVAL; + } +} + +#if defined(CONFIG_TARGET_AQUILA_AM69_R5) +static void update_ddr_timings(u8 hw_cfg) { int ret = 0; void *fdt = (void *)gd->fdt_blob; - switch (aquila_am69_memory_cfg()) { + switch (hw_cfg & HW_CFG_MEM_CFG_MASK) { case HW_CFG_MEM_SZ_8GB: ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB, MULTI_DDR_CFG_INTRLV_SIZE_8GB); @@ -103,6 +101,7 @@ static void update_ddr_timings(void) if (ret) printf("Applying DDR patch error: %d\n", ret); } +#endif static int aquila_am69_fdt_fixup_memory_size(u64 total_sz) { @@ -121,21 +120,33 @@ static int aquila_am69_fdt_fixup_memory_size(u64 total_sz) return fdt_fixup_memory_banks(blob, s, e, CONFIG_NR_DRAM_BANKS); } +#if defined(CONFIG_TARGET_AQUILA_AM69_R5) void do_board_detect(void) { + u8 hw_cfg; + /* MCU_ADC1 pins used as General Purpose Inputs */ writel(readl(CTRL_MMR_CFG0_MCU_ADC1_CTRL) | BIT(16), CTRL_MMR_CFG0_MCU_ADC1_CTRL); - read_hw_cfg(); + hw_cfg = get_hw_cfg(); + printf("HW CFG: 0x%02x\n", hw_cfg); if (IS_ENABLED(CONFIG_K3_DDRSS)) - update_ddr_timings(); + update_ddr_timings(hw_cfg); } +#endif + +#if defined(CONFIG_XPL_BUILD) +void spl_perform_board_fixups(struct spl_image_info *spl_image) +{ + fixup_memory_node(spl_image); +} +#endif int dram_init(void) { - s32 ret; + int ret; ret = fdtdec_setup_mem_size_base_lowest(); if (ret) @@ -146,11 +157,18 @@ int dram_init(void) int dram_init_banksize(void) { - s32 ret; + int ret; - ret = aquila_am69_fdt_fixup_memory_size(aquila_am69_memory_size()); - if (ret) - printf("Error setting memory size. %d\n", ret); + if (IS_ENABLED(CONFIG_SPL_BUILD) && + IS_ENABLED(CONFIG_TARGET_AQUILA_AM69_A72)) { + u64 mem_sz = aquila_am69_memory_size(); + + ret = aquila_am69_fdt_fixup_memory_size(mem_sz); + if (ret) + printf("Error setting memory size. %d\n", ret); + } else { + fdtdec_setup_mem_size_base(); + } ret = fdtdec_setup_memory_banksize(); if (ret) diff --git a/board/toradex/aquila-am69/aquila-am69.env b/board/toradex/aquila-am69/aquila-am69.env index f8b7363dcf5..5371f7c5410 100644 --- a/board/toradex/aquila-am69/aquila-am69.env +++ b/board/toradex/aquila-am69/aquila-am69.env @@ -1,3 +1,5 @@ +#include <env/ti/k3_rproc.env> + #define CFG_RAMDISK_ADDR_R 0x90300000 #define CFG_SCRIPTADDR 0x90280000 @@ -21,21 +23,40 @@ dfu_alt_info_ram= update_tiboot3= askenv confirm Did you load tiboot3.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; fi update_tispl= askenv confirm Did you load tispl.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt}; fi update_uboot= askenv confirm Did you load u-boot.img (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt}; fi + +rprocsemmcboot= + env set boot mmc; + env set bootpart 0:2; + rproc init; + run boot_rprocs_mmc; + env set bootpart; + +rproc_fw_binaries= \ + 2 /lib/firmware/j784s4-main-r5f0_0-fw \ + 3 /lib/firmware/j784s4-main-r5f0_1-fw \ + 4 /lib/firmware/j784s4-main-r5f1_0-fw \ + 5 /lib/firmware/j784s4-main-r5f1_1-fw \ + 6 /lib/firmware/j784s4-main-r5f2_0-fw \ + 7 /lib/firmware/j784s4-main-r5f2_1-fw \ + 8 /lib/firmware/j784s4-c71_0-fw \ + 9 /lib/firmware/j784s4-c71_1-fw \ + 10 /lib/firmware/j784s4-c71_2-fw \ + 11 /lib/firmware/j784s4-c71_3-fw diff --git a/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c index c24e22b620b..66e800ef7c8 100644 --- a/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c +++ b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c @@ -14,7 +14,7 @@ #include <linux/kernel.h> #include "ddrs_patch.h" -#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FHS_CNT 5 #define DDRSS_CTL_268_DATA 0x01010000 #define DDRSS_CTL_270_DATA 0x00000FFF diff --git a/board/toradex/aquila-am69/rm-cfg.yaml b/board/toradex/aquila-am69/rm-cfg.yaml index 02a753a0a9f..a3cf5643dc5 100644 --- a/board/toradex/aquila-am69/rm-cfg.yaml +++ b/board/toradex/aquila-am69/rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J784S4 # @@ -453,36 +453,36 @@ rm-cfg: reserved: 0 - start_resource: 16 - num_resource: 80 + num_resource: 78 type: 18112 host_id: 12 reserved: 0 - - start_resource: 96 + start_resource: 94 num_resource: 14 type: 18112 host_id: 13 reserved: 0 - - start_resource: 110 + start_resource: 108 num_resource: 21 type: 18112 host_id: 21 reserved: 0 - - start_resource: 131 + start_resource: 129 num_resource: 21 type: 18112 host_id: 23 reserved: 0 - - start_resource: 152 + start_resource: 150 num_resource: 12 type: 18112 host_id: 25 reserved: 0 - - start_resource: 164 + start_resource: 162 num_resource: 12 type: 18112 host_id: 27 @@ -1719,72 +1719,72 @@ rm-cfg: reserved: 0 - start_resource: 56 - num_resource: 56 + num_resource: 54 type: 20554 host_id: 12 reserved: 0 - - start_resource: 112 + start_resource: 110 num_resource: 24 type: 20554 host_id: 13 reserved: 0 - - start_resource: 136 + start_resource: 134 num_resource: 12 type: 20554 host_id: 21 reserved: 0 - - start_resource: 148 + start_resource: 146 num_resource: 12 type: 20554 host_id: 23 reserved: 0 - - start_resource: 160 + start_resource: 158 num_resource: 10 type: 20554 host_id: 25 reserved: 0 - - start_resource: 170 + start_resource: 168 num_resource: 10 type: 20554 host_id: 27 reserved: 0 - - start_resource: 180 + start_resource: 178 num_resource: 28 type: 20554 host_id: 35 reserved: 0 - - start_resource: 208 + start_resource: 206 num_resource: 8 type: 20554 host_id: 37 reserved: 0 - - start_resource: 216 + start_resource: 214 num_resource: 12 type: 20554 host_id: 40 reserved: 0 - - start_resource: 228 + start_resource: 226 num_resource: 8 type: 20554 host_id: 42 reserved: 0 - - start_resource: 236 + start_resource: 234 num_resource: 10 type: 20554 host_id: 45 reserved: 0 - - start_resource: 246 + start_resource: 244 num_resource: 10 type: 20554 host_id: 47 @@ -1875,7 +1875,7 @@ rm-cfg: reserved: 0 - start_resource: 4472 - num_resource: 136 + num_resource: 134 type: 20557 host_id: 128 reserved: 0 diff --git a/board/toradex/aquila-am69/tifs-rm-cfg.yaml b/board/toradex/aquila-am69/tifs-rm-cfg.yaml index 2889baacf82..964d9e47e66 100644 --- a/board/toradex/aquila-am69/tifs-rm-cfg.yaml +++ b/board/toradex/aquila-am69/tifs-rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for J784S4 # @@ -1455,72 +1455,72 @@ tifs-rm-cfg: reserved: 0 - start_resource: 56 - num_resource: 56 + num_resource: 54 type: 20554 host_id: 12 reserved: 0 - - start_resource: 112 + start_resource: 110 num_resource: 24 type: 20554 host_id: 13 reserved: 0 - - start_resource: 136 + start_resource: 134 num_resource: 12 type: 20554 host_id: 21 reserved: 0 - - start_resource: 148 + start_resource: 146 num_resource: 12 type: 20554 host_id: 23 reserved: 0 - - start_resource: 160 + start_resource: 158 num_resource: 10 type: 20554 host_id: 25 reserved: 0 - - start_resource: 170 + start_resource: 168 num_resource: 10 type: 20554 host_id: 27 reserved: 0 - - start_resource: 180 + start_resource: 178 num_resource: 28 type: 20554 host_id: 35 reserved: 0 - - start_resource: 208 + start_resource: 206 num_resource: 8 type: 20554 host_id: 37 reserved: 0 - - start_resource: 216 + start_resource: 214 num_resource: 12 type: 20554 host_id: 40 reserved: 0 - - start_resource: 228 + start_resource: 226 num_resource: 8 type: 20554 host_id: 42 reserved: 0 - - start_resource: 236 + start_resource: 234 num_resource: 10 type: 20554 host_id: 45 reserved: 0 - - start_resource: 246 + start_resource: 244 num_resource: 10 type: 20554 host_id: 47 diff --git a/board/toradex/aquila-imx95/Kconfig b/board/toradex/aquila-imx95/Kconfig new file mode 100644 index 00000000000..5936946e1af --- /dev/null +++ b/board/toradex/aquila-imx95/Kconfig @@ -0,0 +1,36 @@ +if TARGET_AQUILA_IMX95 + +config SYS_BOARD + default "aquila-imx95" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "aquila-imx95" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/aquila-imx95/MAINTAINERS b/board/toradex/aquila-imx95/MAINTAINERS new file mode 100644 index 00000000000..d2a74a53f5e --- /dev/null +++ b/board/toradex/aquila-imx95/MAINTAINERS @@ -0,0 +1,11 @@ +Aquila iMX95 +F: arch/arm/dts/imx95-aquila.dtsi +F: arch/arm/dts/imx95-aquila-dev.dts +F: arch/arm/dts/imx95-aquila-dev-u-boot.dtsi +F: board/toradex/aquila-imx95/ +F: configs/aquila-imx95_defconfig +F: doc/board/toradex/aquila-imx95.rst +F: include/configs/aquila-imx95.h +M: Francesco Dolcini <[email protected]> +S: Maintained +W: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 diff --git a/board/toradex/aquila-imx95/Makefile b/board/toradex/aquila-imx95/Makefile new file mode 100644 index 00000000000..caaf09465c8 --- /dev/null +++ b/board/toradex/aquila-imx95/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (c) Toradex + +obj-y += aquila-imx95.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.c b/board/toradex/aquila-imx95/aquila-imx95.c new file mode 100644 index 00000000000..0c6473e4b3a --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <fdt_support.h> +#include <init.h> + +#include "../common/tdx-cfg-block.h" + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.env b/board/toradex/aquila-imx95/aquila-imx95.env new file mode 100644 index 00000000000..5ca6cb18aaa --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.env @@ -0,0 +1,20 @@ +boot_scripts=boot.scr +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyLP2 +fdt_board=dev +fdt_addr=0x9c400000 +fdt_addr_r=0x9c400000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x94400000 +kernel_comp_size=0x8000000 +ramdisk_addr_r=0x9c800000 +scriptaddr=0x9c600000 + +update_uboot= + askenv confirm Did you load flash.bin (y/N)?; + if test "$confirm" = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 + ${blkcnt}; + fi diff --git a/board/toradex/aquila-imx95/spl.c b/board/toradex/aquila-imx95/spl.c new file mode 100644 index 00000000000..9f501c11c1d --- /dev/null +++ b/board/toradex/aquila-imx95/spl.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/sections.h> +#include <asm/global_data.h> +#include <clk.h> +#include <dm/uclass.h> +#include <hang.h> +#include <i2c.h> +#include <init.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION)) + spl_save_restore_data(); + + timer_init(); + + /* Need dm_init() to run before any SCMI calls */ + spl_early_init(); + + /* Need to enable SCMI drivers and ELE driver before console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* MU not probed, nothing can be outputed, hang */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig index d2ad1ce2a03..53d3469d439 100644 --- a/board/toradex/colibri_imx6/Kconfig +++ b/board/toradex/colibri_imx6/Kconfig @@ -35,7 +35,7 @@ config TDX_CMD_IMX_MFGR bool "Enable factory testing commands for Toradex iMX 6 modules" help This adds the commands - pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 + pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 If executed on already fused modules it doesn't change any fuse setting. default y diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 69a8a18d3a7..c63812bd966 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -288,13 +288,13 @@ int ft_board_setup(void *blob, struct bd_info *bd) * Reserve 1MB of memory for M4 (1MiB is also the minimum * alignment for Linux due to MMU section size restrictions). */ - start[0] = gd->bd->bi_dram[0].start; + start[0] = gd->dram[0].start; size[0] = SZ_256M - SZ_1M; /* If needed, create a second entry for memory beyond 256M */ - if (gd->bd->bi_dram[0].size > SZ_256M) { - start[1] = gd->bd->bi_dram[0].start + SZ_256M; - size[1] = gd->bd->bi_dram[0].size - SZ_256M; + if (gd->dram[0].size > SZ_256M) { + start[1] = gd->dram[0].start + SZ_256M; + size[1] = gd->dram[0].size - SZ_256M; areas = 2; } diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index c8c10742103..896a0d3bd12 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -187,6 +187,9 @@ const struct toradex_som toradex_modules[] = { { OSM_IMX91S_2GB_IT, "OSM iMX91 Solo 2GB IT", TARGET_IS_ENABLED(TORADEX_OSM_IMX91) }, { VERDIN_AM62D_1G_ET_GPU_NODSI, "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, { AQUILA_TDA4O_16GB_IT, "Aquila TDA4 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { VERDIN_IMX95H_4G_WB_IT, "Verdin iMX95 Hexa 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, + { VERDIN_IMX95H_4G_ET, "Verdin iMX95 Hexa 4GB ET", TARGET_IS_ENABLED(VERDIN_IMX95) }, + { VERDIN_IMX95H_16G_IT, "Verdin iMX95 Hexa 16GB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 3022ef615ad..9a96bddfbe1 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -150,6 +150,9 @@ enum { OSM_IMX91S_2GB_IT, /* 220 */ VERDIN_AM62D_1G_ET_GPU_NODSI, AQUILA_TDA4O_16GB_IT = 223, + VERDIN_IMX95H_4G_WB_IT = 226, + VERDIN_IMX95H_4G_ET, + VERDIN_IMX95H_16G_IT, }; enum { diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.env b/board/toradex/smarc-imx8mp/smarc-imx8mp.env index 58f152e6b51..1480db8e5fc 100644 --- a/board/toradex/smarc-imx8mp/smarc-imx8mp.env +++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.env @@ -13,7 +13,7 @@ scriptaddr=0x50280000 update_uboot= askenv confirm Did you load flash.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; diff --git a/board/toradex/smarc-imx95/smarc-imx95.env b/board/toradex/smarc-imx95/smarc-imx95.env index b94250bbc52..35d26b7cfba 100644 --- a/board/toradex/smarc-imx95/smarc-imx95.env +++ b/board/toradex/smarc-imx95/smarc-imx95.env @@ -13,7 +13,7 @@ scriptaddr=0x9c600000 update_uboot= askenv confirm Did you load flash.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; diff --git a/board/toradex/verdin-am62/tifs-rm-cfg.yaml b/board/toradex/verdin-am62/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..8510fe9526e --- /dev/null +++ b/board/toradex/verdin-am62/tifs-rm-cfg.yaml @@ -0,0 +1,867 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62X +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + 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host_id: 12 + reserved: 0 diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 19ac2ae9313..a174cc43ade 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -12,6 +12,7 @@ #include <dm/uclass.h> #include <env.h> #include <fdt_support.h> +#include <image.h> #include <init.h> #include <k3-ddrss.h> #include <spl.h> @@ -44,7 +45,7 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } @@ -57,12 +58,10 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return 0x9C000000; } -#if defined(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { - return 0; + return k3_fit_config_match_security_state(name); } -#endif #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/toradex/verdin-am62p/Kconfig b/board/toradex/verdin-am62p/Kconfig index a65caf3c26d..4f5968bca2e 100644 --- a/board/toradex/verdin-am62p/Kconfig +++ b/board/toradex/verdin-am62p/Kconfig @@ -8,22 +8,22 @@ choice optional config TARGET_VERDIN_AM62P_A53 - bool "Toradex Verdin AM62P running on A53" - select ARM64 - select BINMAN - select OF_SYSTEM_SETUP - imply OF_UPSTREAM + bool "Toradex Verdin AM62P running on A53" + select ARM64 + select BINMAN + select OF_SYSTEM_SETUP + imply OF_UPSTREAM config TARGET_VERDIN_AM62P_R5 - bool "Toradex Verdin AM62P running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF + bool "Toradex Verdin AM62P running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF endchoice diff --git a/board/toradex/verdin-am62p/tifs-rm-cfg.yaml b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml index 80269748057..73efceafc75 100644 --- a/board/toradex/verdin-am62p/tifs-rm-cfg.yaml +++ b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# Copyright (C) 2022-2026 Texas Instruments Incorporated - https://www.ti.com/ # # Resource management configuration for AM62P # @@ -9,231 +9,231 @@ tifs-rm-cfg: rm_boardcfg: rev: - boardcfg_abi_maj : 0x0 - boardcfg_abi_min : 0x1 + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 host_cfg: subhdr: magic: 0x4C41 - size : 356 + size: 356 host_cfg_entries: - - #1 + - # 1 host_id: 12 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #2 + - # 2 host_id: 30 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #3 + - # 3 host_id: 36 allowed_atype: 0x2A allowed_qos: 0xAAAA allowed_orderid: 0xAAAAAAAA allowed_priority: 0xAAAA allowed_sched_priority: 0xAA - - #4 + - # 4 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #5 + - # 5 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #6 + - # 6 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #7 + - # 7 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #8 + - # 8 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #9 + - # 9 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #10 + - # 10 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #11 + - # 11 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #12 + - # 12 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #13 + - # 13 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #14 + - # 14 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #15 + - # 15 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #16 + - # 16 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #17 + - # 17 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #18 + - # 18 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #19 + - # 19 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #20 + - # 20 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #21 + - # 21 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #22 + - # 22 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #23 + - # 23 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #24 + - # 24 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #25 + - # 25 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #26 + - # 26 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #27 + - # 27 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #28 + - # 28 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #29 + - # 29 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #30 + - # 30 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #31 + - # 31 host_id: 0 allowed_atype: 0 allowed_qos: 0 allowed_orderid: 0 allowed_priority: 0 allowed_sched_priority: 0 - - #32 + - # 32 host_id: 0 allowed_atype: 0 allowed_qos: 0 @@ -244,684 +244,732 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 - resasg_entries_size: 904 + resasg_entries_size: 968 reserved: 0 resasg_entries: - - start_resource: 0 - num_resource: 18 - type: 1677 - host_id: 12 - reserved: 0 + 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start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 35 + reserved: 0 - - start_resource: 10 - num_resource: 3 - type: 1962 - host_id: 36 - reserved: 0 + start_resource: 10 + num_resource: 3 + type: 1962 + host_id: 36 + reserved: 0 - - start_resource: 13 - num_resource: 3 - type: 1962 - host_id: 30 - reserved: 0 + start_resource: 13 + num_resource: 3 + type: 1962 + host_id: 30 + reserved: 0 - - start_resource: 16 - num_resource: 3 - type: 1962 - host_id: 128 - reserved: 0 + start_resource: 16 + num_resource: 3 + type: 1962 + host_id: 128 + reserved: 0 - - start_resource: 19 - num_resource: 1 - type: 1963 - host_id: 12 - reserved: 0 + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 12 + reserved: 0 - - start_resource: 19 - num_resource: 1 - type: 1963 - host_id: 36 - reserved: 0 + start_resource: 19 + num_resource: 1 + type: 1963 + host_id: 36 + reserved: 0 - - start_resource: 19 - num_resource: 6 - type: 1964 - host_id: 12 - reserved: 0 + start_resource: 19 + num_resource: 6 + type: 1964 + host_id: 12 + reserved: 0 - - start_resource: 19 - num_resource: 6 - type: 1964 - host_id: 36 - reserved: 0 + start_resource: 19 + num_resource: 6 + type: 1964 + host_id: 36 + reserved: 0 - - start_resource: 25 - num_resource: 10 - type: 1964 - host_id: 12 - reserved: 0 + start_resource: 25 + num_resource: 10 + type: 1964 + host_id: 12 + reserved: 0 - - start_resource: 25 - num_resource: 10 - type: 1964 - host_id: 30 - reserved: 0 + start_resource: 25 + num_resource: 10 + type: 1964 + host_id: 30 + reserved: 0 - - start_resource: 20 - num_resource: 1 - type: 1965 - host_id: 12 - reserved: 0 + start_resource: 20 + num_resource: 1 + type: 1965 + host_id: 12 + reserved: 0 - - start_resource: 35 - num_resource: 8 - type: 1966 - host_id: 12 - reserved: 0 + start_resource: 35 + num_resource: 8 + type: 1966 + host_id: 12 + reserved: 0 - - start_resource: 21 - num_resource: 1 - type: 1967 - host_id: 12 - reserved: 0 + start_resource: 21 + num_resource: 1 + type: 1967 + host_id: 12 + reserved: 0 - - start_resource: 35 - num_resource: 8 - type: 1968 - host_id: 12 - reserved: 0 + start_resource: 35 + num_resource: 8 + type: 1968 + host_id: 12 + reserved: 0 - - start_resource: 22 - num_resource: 1 - type: 1969 - host_id: 12 - reserved: 0 + start_resource: 22 + num_resource: 1 + type: 1969 + host_id: 12 + reserved: 0 - - start_resource: 43 - num_resource: 8 - type: 1970 - host_id: 12 - reserved: 0 + start_resource: 43 + num_resource: 8 + type: 1970 + host_id: 12 + reserved: 0 - - start_resource: 23 - num_resource: 1 - type: 1971 - host_id: 12 - reserved: 0 + start_resource: 23 + num_resource: 1 + type: 1971 + host_id: 12 + reserved: 0 - - start_resource: 43 - num_resource: 8 - type: 1972 - host_id: 12 - reserved: 0 + start_resource: 43 + num_resource: 8 + type: 1972 + host_id: 12 + reserved: 0 - - start_resource: 0 - num_resource: 1 - type: 2112 - host_id: 128 - reserved: 0 + start_resource: 0 + num_resource: 1 + type: 2112 + host_id: 128 + reserved: 0 - - start_resource: 2 - num_resource: 2 - type: 2122 - host_id: 12 - reserved: 0 + start_resource: 2 + num_resource: 2 + type: 2122 + host_id: 12 + reserved: 0 - - start_resource: 0 - num_resource: 6 - type: 12750 - host_id: 12 - reserved: 0 + start_resource: 0 + num_resource: 6 + type: 12750 + host_id: 12 + reserved: 0 - - start_resource: 0 - num_resource: 6 - type: 12769 - host_id: 12 - reserved: 0 + start_resource: 0 + num_resource: 6 + type: 12769 + host_id: 12 + reserved: 0 - - start_resource: 0 - num_resource: 8 - type: 12810 - host_id: 12 - reserved: 0 + start_resource: 0 + num_resource: 8 + type: 12810 + host_id: 12 + reserved: 0 - - start_resource: 3072 - num_resource: 6 - type: 12826 - host_id: 128 - reserved: 0 + start_resource: 3072 + num_resource: 6 + type: 12826 + host_id: 128 + reserved: 0 - - start_resource: 3584 - num_resource: 6 - type: 12827 - host_id: 128 - reserved: 0 + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 - - start_resource: 4096 - num_resource: 6 - type: 12828 - host_id: 128 - reserved: 0 + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c index 1234b3887c6..1e7fcc9fd9d 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.c +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -14,6 +14,7 @@ #include <dm/uclass.h> #include <env.h> #include <fdt_support.h> +#include <image.h> #include <init.h> #include <k3-ddrss.h> #include <spl.h> @@ -78,17 +79,15 @@ int dram_init_banksize(void) printf("Error setting up memory banksize. %d\n", ret); /* Use the detected RAM size, we only support 1 bank right now. */ - gd->bd->bi_dram[0].size = gd->ram_size; + gd->dram[0].size = gd->ram_size; return ret; } -#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { - return 0; + return k3_fit_config_match_security_state(name); } -#endif #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/toradex/verdin-am62p/verdin-am62p.env b/board/toradex/verdin-am62p/verdin-am62p.env index f8b7363dcf5..ac2828e0b58 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.env +++ b/board/toradex/verdin-am62p/verdin-am62p.env @@ -21,21 +21,21 @@ dfu_alt_info_ram= update_tiboot3= askenv confirm Did you load tiboot3.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; fi update_tispl= askenv confirm Did you load tispl.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt}; fi update_uboot= askenv confirm Did you load u-boot.img (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt}; fi diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 59b4607f065..69c3408fbba 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -46,7 +46,7 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -#if IS_ENABLED(CONFIG_NET) +#if IS_ENABLED(CONFIG_NET_LEGACY) int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) diff --git a/board/toradex/verdin-imx95/Kconfig b/board/toradex/verdin-imx95/Kconfig new file mode 100644 index 00000000000..ef4206c343c --- /dev/null +++ b/board/toradex/verdin-imx95/Kconfig @@ -0,0 +1,36 @@ +if TARGET_VERDIN_IMX95 + +config SYS_BOARD + default "verdin-imx95" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "verdin-imx95" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/verdin-imx95/MAINTAINERS b/board/toradex/verdin-imx95/MAINTAINERS new file mode 100644 index 00000000000..d19ee3ebfe5 --- /dev/null +++ b/board/toradex/verdin-imx95/MAINTAINERS @@ -0,0 +1,13 @@ +Verdin iMX95 +F: arch/arm/dts/imx95-verdin.dtsi +F: arch/arm/dts/imx95-verdin-dev.dtsi +F: arch/arm/dts/imx95-verdin-wifi.dtsi +F: arch/arm/dts/imx95-verdin-wifi-dev.dts +F: arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi +F: board/toradex/verdin-imx95/ +F: configs/verdin-imx95_defconfig +F: doc/board/toradex/verdin-imx95.rst +F: include/configs/verdin-imx95.h +M: Francesco Dolcini <[email protected]> +S: Maintained +W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 diff --git a/board/toradex/verdin-imx95/Makefile b/board/toradex/verdin-imx95/Makefile new file mode 100644 index 00000000000..bc1b6811bbe --- /dev/null +++ b/board/toradex/verdin-imx95/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (c) Toradex + +obj-y += verdin-imx95.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/toradex/verdin-imx95/spl.c b/board/toradex/verdin-imx95/spl.c new file mode 100644 index 00000000000..9f501c11c1d --- /dev/null +++ b/board/toradex/verdin-imx95/spl.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/sections.h> +#include <asm/global_data.h> +#include <clk.h> +#include <dm/uclass.h> +#include <hang.h> +#include <i2c.h> +#include <init.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION)) + spl_save_restore_data(); + + timer_init(); + + /* Need dm_init() to run before any SCMI calls */ + spl_early_init(); + + /* Need to enable SCMI drivers and ELE driver before console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* MU not probed, nothing can be outputed, hang */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/board/toradex/verdin-imx95/verdin-imx95.c b/board/toradex/verdin-imx95/verdin-imx95.c new file mode 100644 index 00000000000..7c0804c1d1c --- /dev/null +++ b/board/toradex/verdin-imx95/verdin-imx95.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <env.h> +#include <errno.h> +#include <fdt_support.h> +#include <init.h> +#include <stdio.h> +#include <string.h> + +#include "../common/tdx-cfg-block.h" +#include "../common/tdx-common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + bool is_wifi = false; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a + * module with Wi-Fi/Bluetooth make sure we use the -wifi + * device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX95H_8G_WIFI_BT_IT) || + (tdx_hw_tag.prodid == VERDIN_IMX95H_4G_WB_IT); + } + + if (is_wifi) + strlcpy(&variant[0], "wifi", sizeof(variant)); + else + strlcpy(&variant[0], "nonwifi", sizeof(variant)); + + if (!env_variant || strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + } +} + +int board_late_init(void) +{ + select_dt_from_module_version(); + + return 0; +} + +static const struct ram_alias_check ram_alias_checks[] = { + { (void *)((uintptr_t)PHYS_SDRAM + SZ_8G), (void *)(PHYS_SDRAM), SZ_16G }, + { (void *)((uintptr_t)PHYS_SDRAM + SZ_4G), (void *)(PHYS_SDRAM), SZ_8G }, + { (void *)((uintptr_t)PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G }, + { (void *)((uintptr_t)PHYS_SDRAM + SZ_1G), (void *)(PHYS_SDRAM), SZ_2G }, + { NULL } +}; + +int board_phys_sdram_size(phys_size_t *size) +{ + phys_size_t sz; + + sz = probe_ram_size_by_alias(ram_alias_checks); + if (!sz) { + puts("## WARNING: Less than 2GB RAM detected\n"); + return -EINVAL; + } + + *size = sz - PHYS_SDRAM_FW_RSVD; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif diff --git a/board/toradex/verdin-imx95/verdin-imx95.env b/board/toradex/verdin-imx95/verdin-imx95.env new file mode 100644 index 00000000000..5ca6cb18aaa --- /dev/null +++ b/board/toradex/verdin-imx95/verdin-imx95.env @@ -0,0 +1,20 @@ +boot_scripts=boot.scr +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyLP2 +fdt_board=dev +fdt_addr=0x9c400000 +fdt_addr_r=0x9c400000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x94400000 +kernel_comp_size=0x8000000 +ramdisk_addr_r=0x9c800000 +scriptaddr=0x9c600000 + +update_uboot= + askenv confirm Did you load flash.bin (y/N)?; + if test "$confirm" = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 + ${blkcnt}; + fi diff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS index e6f3dc4da21..a04a36ba415 100644 --- a/board/tq/MAINTAINERS +++ b/board/tq/MAINTAINERS @@ -1,4 +1,4 @@ -TQMA6 +TQMA6 / TQMA6UL / TQMA6ULxL / TQMA6ULL / TQMA6ULLxL M: Max Merchel <[email protected]> S: Maintained @@ -6,3 +6,12 @@ W: https://www.tq-group.com/en/products/tq-embedded/ F: arch/arm/dts/*mba6*.dts* F: arch/arm/dts/*tqma6*.dts* F: configs/tqma6*config + +TQMA7 +M: Alexander Feilke <[email protected]> +S: Maintained +W: https://www.tq-group.com/en/products/tq-embedded/ +F: arch/arm/dts/*mba7*.dts* +F: arch/arm/dts/*tqma7*.dts* +F: configs/tqma7*config diff --git a/board/tq/common/Kconfig b/board/tq/common/Kconfig index a1896929ea3..567b6e2380a 100644 --- a/board/tq/common/Kconfig +++ b/board/tq/common/Kconfig @@ -11,3 +11,11 @@ config TQ_COMMON_BB config TQ_COMMON_SDMMC bool + +config TQ_COMMON_SOM + bool + +config TQ_COMMON_SYSINFO + bool + select SYSINFO + imply SYSINFO_TQ_EEPROM diff --git a/board/tq/common/Makefile b/board/tq/common/Makefile index ac564a713fd..6cb39a1925e 100644 --- a/board/tq/common/Makefile +++ b/board/tq/common/Makefile @@ -6,4 +6,6 @@ # obj-$(CONFIG_TQ_COMMON_BB) += tq_bb.o +obj-$(CONFIG_TQ_COMMON_SOM) += tq_som.o obj-$(CONFIG_TQ_COMMON_SDMMC) += tq_sdmmc.o +obj-$(CONFIG_$(PHASE_)TQ_COMMON_SYSINFO) += tq_sysinfo.o diff --git a/board/tq/common/tq_som.c b/board/tq/common/tq_som.c new file mode 100644 index 00000000000..6fb4839109b --- /dev/null +++ b/board/tq/common/tq_som.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke, Max Merchel + */ + +#include <init.h> +#include <asm/io.h> +#include <linux/sizes.h> + +#include "tq_som.h" + +void __weak tq_som_ram_init(void) +{ + ; +} + +/* + * checks if the accessible range equals the requested RAM size. + * returns true if successful, false otherwise + */ +bool tq_som_ram_check_size(long ram_size) +{ + long size; + + size = get_ram_size((void *)PHYS_SDRAM, ram_size); + debug("SPL: requested RAM size %lu MiB. accessible %lu MiB\n", + ram_size / (SZ_1M), size / (SZ_1M)); + + return (size == ram_size); +} diff --git a/board/tq/common/tq_som.h b/board/tq/common/tq_som.h new file mode 100644 index 00000000000..0ab01d51f99 --- /dev/null +++ b/board/tq/common/tq_som.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke, Max Merchel + */ + +#ifndef __TQ_SOM_H +#define __TQ_SOM_H + +#include <init.h> +#include <asm/io.h> +#include <linux/iopoll.h> + +void tq_som_ram_init(void); + +/* used as a wrapper to write to specific register addresses */ +static inline void tq_som_init_write_reg(u32 address, u32 value) +{ + writel_relaxed(value, address); +} + +/* + * checks if the accessible range equals the requested ram size. + * returns true if successful, false otherwise + */ +bool tq_som_ram_check_size(long ram_size); + +static inline void tq_som_check_bits_set(u32 address, u32 mask) +{ + u32 val; + readl_poll_timeout(address, val, (val & mask) == mask, 1000); +} + +#endif /* __TQ_SOM_H */ diff --git a/board/tq/common/tq_sysinfo.c b/board/tq/common/tq_sysinfo.c new file mode 100644 index 00000000000..8d21d1e97c6 --- /dev/null +++ b/board/tq/common/tq_sysinfo.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Common sysinfo helpers for TQ-Systems SOMs + * + * Copyright (c) 2020-2026 TQ-Systems GmbH <[email protected]> + * D-82229 Seefeld, Germany. + * Author: Nora Schiffer + */ + +#include <env.h> +#include <log.h> +#include <sysinfo/tq_eeprom.h> + +#include "tq_sysinfo.h" + +#define MAX_NAME_LENGTH 80 + +int tq_common_sysinfo_setup(void) +{ + struct udevice *sysinfo; + char buf[MAX_NAME_LENGTH]; + int ret; + + ret = sysinfo_get_and_detect(&sysinfo); + if (ret) { + log_debug("Failed to get sysinfo data: %d\n", ret); + return ret; + } + + if (!sysinfo_get_str(sysinfo, SYSID_TQ_MODEL, sizeof(buf), buf)) + env_set_runtime("boardtype", buf); + + if (!sysinfo_get_str(sysinfo, SYSID_TQ_SERIAL, sizeof(buf), buf)) + env_set_runtime("serial#", buf); + + return 0; +} diff --git a/board/tq/common/tq_sysinfo.h b/board/tq/common/tq_sysinfo.h new file mode 100644 index 00000000000..d73b00eb8d7 --- /dev/null +++ b/board/tq/common/tq_sysinfo.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Common sysinfo helpers for TQ-Systems SOMs + * + * Copyright (c) 2025-2026 TQ-Systems GmbH <[email protected]> + * D-82229 Seefeld, Germany. + * Author: Nora Schiffer + */ + +#ifndef __TQ_SYSINFO_H +#define __TQ_SYSINFO_H + +int tq_common_sysinfo_setup(void); + +#endif /* __TQ_SYSINFO_H */ diff --git a/board/tq/tqma6ul/Kconfig b/board/tq/tqma6ul/Kconfig new file mode 100644 index 00000000000..5d85c68b359 --- /dev/null +++ b/board/tq/tqma6ul/Kconfig @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. +# Author: Marco Felsch, Markus Niebel, Max Merchel +# + +if TARGET_TQMA6UL + +config SYS_BOARD + default "tqma6ul" + +config SYS_VENDOR + default "tq" + +config SYS_CONFIG_NAME + default "tqma6ul_mba6ul" if MBA6UL + +choice + prompt "TQMa6UL module variant" + default TQMA6UL_VARIANT_STANDARD + help + Select the variant of the TQMa6UL SoM module being used. + By default, the variant with board-to-board connectors is used. + +config TQMA6UL_VARIANT_STANDARD + bool "standard module with board connector" + help + Select for SoM variant connector + with board to board connectors + +config TQMA6UL_VARIANT_LGA + bool "LGA module with solder balls" + help + Select for SoM variant LGA + with solder balls + +endchoice + +config TQMA6UL_RAM_256M + bool + +config TQMA6UL_RAM_512M + bool + +choice + prompt "TQMa6UL RAM configuration" + default TQMA6UL_RAM_MULTI + help + Select RAM configuration. Normally use default here but for + specific setup it is possible to use a single RAM size. + +config TQMA6UL_RAM_MULTI + bool "TQMa6ULx with 256/512 MB RAM - Single image" + select TQMA6UL_RAM_256M + select TQMA6UL_RAM_512M + help + Build a single U-Boot solely for variants + with 256/512 MB RAM. + +config TQMA6UL_RAM_SINGLE_256M + bool "TQMa6UL with 256 MB RAM" + select TQMA6UL_RAM_256M + help + Build U-Boot solely for variants + with 256 MB RAM. + +config TQMA6UL_RAM_SINGLE_512M + bool "TQMa6UL with 512 MB RAM" + select TQMA6UL_RAM_512M + help + Build U-Boot solely for variants + with 512 MB RAM. + +endchoice + +choice + prompt "TQMa6UL base board variant" + default MBA6UL + help + Select the baseboard variant for the TQMa6UL module. + By default the MBA6UL starterkit is used. + +config MBA6UL + bool "TQMa6UL on MBa6ULx Starterkit" + select TQ_COMMON_BB + select TQ_COMMON_SDMMC + select SYSINFO + select SYSINFO_TQ_EEPROM + select I2C_EEPROM + select MISC + select MXC_UART + imply DM_ETH + imply DM_GPIO + imply DM_MMC + imply DM_SERIAL + imply DM_SPI + imply OF_UPSTREAM + imply PHYLIB + imply PHY_SMSC + imply USB + imply USB_STORAGE + help + Select the MBa6ULx starterkit. + This is the default base board. + +endchoice + +config IMX_CONFIG + default "board/tq/tqma6ul/tqma6ul.cfg" + +source "board/tq/common/Kconfig" + +endif diff --git a/board/tq/tqma6ul/Makefile b/board/tq/tqma6ul/Makefile new file mode 100644 index 00000000000..f45ed4a15f6 --- /dev/null +++ b/board/tq/tqma6ul/Makefile @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2021-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. +# Author: Markus Niebel, Matthias Schiffer, Max Merchel +# + +obj-y := tqma6ul.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += spl_tqma6ul_ram.o +obj-$(CONFIG_MBA6UL) += spl_mba6ul.o +else +obj-$(CONFIG_MBA6UL) += tqma6ul_mba6ul.o +endif diff --git a/board/tq/tqma6ul/spl.c b/board/tq/tqma6ul/spl.c new file mode 100644 index 00000000000..71c5134c4f6 --- /dev/null +++ b/board/tq/tqma6ul/spl.c @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include <fsl_esdhc_imx.h> +#include <hang.h> +#include <init.h> +#include <mmc.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6ul_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm-generic/sections.h> +#include <linux/sizes.h> + +#include "../common/tq_bb.h" +#include "../common/tq_som.h" + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +/* eMMC on USDHC2 */ +static const iomux_v3_cfg_t tqma6ul_usdhc2_pads[] = { + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg tqma6ul_usdhc2_cfg = { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + /* eMMC/uSDHC2 is always present */ + ret = 1; + else + ret = tq_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + /* eMMC/uSDHC2 is never WP */ + ret = 0; + else + ret = tq_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma6ul_usdhc2_pads, + ARRAY_SIZE(tqma6ul_usdhc2_pads)); + tqma6ul_usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + if (fsl_esdhc_initialize(bis, &tqma6ul_usdhc2_cfg)) + printf("Warning: failed to initialize eMMC dev\n"); + + tq_bb_board_mmc_init(bis); + + return 0; +} + +void board_init_f(ulong dummy) +{ + /* setup clock gating */ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* setup AXI */ + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + tq_som_ram_init(); +} diff --git a/board/tq/tqma6ul/spl_mba6ul.c b/board/tq/tqma6ul/spl_mba6ul.c new file mode 100644 index 00000000000..55beeac8fc9 --- /dev/null +++ b/board/tq/tqma6ul/spl_mba6ul.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include <errno.h> +#include <fsl_esdhc_imx.h> +#include <malloc.h> +#include <spl.h> +#include <spl_gpio.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6ul_pins.h> +#include <asm/mach-imx/sys_proto.h> + +#include "../common/tq_bb.h" +#include "tqma6ul.h" + +#define GPIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static const iomux_v3_cfg_t mba6ul_uart_pads[] = { + NEW_PAD_CTRL(MX6_PAD_UART1_TX_DATA__UART1_DCE_TX, UART_PAD_CTRL), + NEW_PAD_CTRL(MX6_PAD_UART1_RX_DATA__UART1_DCE_RX, UART_PAD_CTRL), +}; + +static void mba6ul_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba6ul_uart_pads, + ARRAY_SIZE(mba6ul_uart_pads)); +} + +/* SD card on USDHC1 */ +static const iomux_v3_cfg_t mba6ul_usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* WP */ + MX6_PAD_UART1_CTS_B__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC1_WP_GPIO IMX_GPIO_NR(1, 18) + +static struct fsl_esdhc_cfg mba6ul_usdhc1_cfg = { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, +}; + +int tq_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = !gpio_get_value(USDHC1_CD_GPIO); + + return ret; +} + +int tq_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = gpio_get_value(USDHC1_WP_GPIO); + + return ret; +} + +int tq_bb_board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(mba6ul_usdhc1_pads, + ARRAY_SIZE(mba6ul_usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1-cd"); + gpio_request(USDHC1_WP_GPIO, "usdhc1-wp"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_direction_input(USDHC1_WP_GPIO); + + mba6ul_usdhc1_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + if (fsl_esdhc_initialize(bis, &mba6ul_usdhc1_cfg)) + puts("Warning: failed to initialize SD card\n"); + + return 0; +} + +int board_early_init_f(void) +{ + tq_bb_board_early_init_f(); + + mba6ul_setup_iomuxc_uart(); + + return 0; +} + +/* + * This is done per baseboard to allow different implementations + */ +void board_boot_order(u32 *spl_boot_list) +{ + u32 bmode = imx6_src_get_boot_mode(); + u8 imx6_bmode = (bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT; + + /* USB boot */ + if (spl_boot_device() == BOOT_DEVICE_BOARD) { + printf("USB\n"); + spl_boot_list[0] = BOOT_DEVICE_BOARD; + return; + } + + switch (imx6_bmode) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + /* SD/eSD - BOOT_DEVICE_MMC2 */ + printf("SD\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + /* MMC/eMMC - BOOT_DEVICE_MMC1 */ + printf("eMMC\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case IMX6_BMODE_QSPI: + /* QSPI - BOOT_DEVICE_SPI */ + printf("QSPI\n"); + spl_boot_list[0] = BOOT_DEVICE_NOR; + break; + case IMX6_BMODE_SERIAL_ROM: + /* SERIAL_ROM - BOOT_DEVICE_BOARD */ + printf("Serial ROM\n"); + spl_boot_list[0] = BOOT_DEVICE_BOARD; + break; + default: + printf("WARNING: unknown boot device, fallback to eMMC\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + } +} + +int board_fit_config_name_match(const char *name) +{ + /* Longest FDT name */ + char dt[] = "imx6ull-tqma6ull2l-mba6ulx"; + enum tqma6ul_som_type somtype; + + somtype = set_tqma6ul_dt_name(dt, sizeof(dt), "mba6ulx"); + if (somtype == tqma6ul_som_type_unknown) + return -EINVAL; + + if (!strcmp(name, dt)) + return -EINVAL; + + printf("Device tree: %s\n", name); + return 0; +} diff --git a/board/tq/tqma6ul/spl_tqma6ul_ram.c b/board/tq/tqma6ul/spl_tqma6ul_ram.c new file mode 100644 index 00000000000..c5d50890702 --- /dev/null +++ b/board/tq/tqma6ul/spl_tqma6ul_ram.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +#include <config.h> +#include <hang.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6ul-ddr.h> +#include <asm/arch/sys_proto.h> +#include <linux/sizes.h> + +#include "../common/tq_som.h" + +static void tqma6ul_init_ddr_controller(u32 size) +{ + /* TQMa6ul DDR config */ + + /* reset DDR via Chip Select 0*/ + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x03180000); + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000); + + debug("SPL: tqma6ul ddr iomux ....\n"); + + /* DDR IO TYPE: */ + tq_som_init_write_reg(MX6_IOM_GRP_DDR_TYPE, 0x000C0000); + tq_som_init_write_reg(MX6_IOM_GRP_DDRPKE, 0x00000000); + /* CLOCK: */ + tq_som_init_write_reg(MX6_IOM_DRAM_SDCLK_0, 0x00000030); + /* Control: */ + tq_som_init_write_reg(MX6_IOM_DRAM_CAS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_RAS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_GRP_ADDDS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_RESET, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_SDBA2, 0x00000000); + tq_som_init_write_reg(MX6_IOM_DRAM_SDODT0, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_SDODT1, 0x00000030); + tq_som_init_write_reg(MX6_IOM_GRP_CTLDS, 0x00000030); + /* Data Strobes: */ + tq_som_init_write_reg(MX6_IOM_DDRMODE_CTL, 0x00020000); + tq_som_init_write_reg(MX6_IOM_DRAM_SDQS0, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_SDQS1, 0x00000030); + /* Data: */ + tq_som_init_write_reg(MX6_IOM_GRP_DDRMODE, 0x00020000); + tq_som_init_write_reg(MX6_IOM_GRP_B0DS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_GRP_B1DS, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_DQM0, 0x00000030); + tq_som_init_write_reg(MX6_IOM_DRAM_DQM1, 0x00000030); + + debug("tqma6ul ddr controller registers ....\n"); + + /* MMDC_MDSCR - MMDC Core Special Command Register */ + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000); + + debug("tqma6ul ddr calibrations ....\n"); + + /* DDR_PHY_P0_MPZQHWCTRL , enable both one-time & periodic HW ZQ calibration. */ + tq_som_init_write_reg(MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003); + + switch (size) { + case SZ_512M: + if (IS_ENABLED(CONFIG_MX6UL)) { + debug("tqma6ul ddr calibration standard variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41580150); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E52); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4A); + + } else if (IS_ENABLED(CONFIG_MX6ULL)) { + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) { + debug("tqma6ull ddr calibration standard variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00090009); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x4140013C); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E26); + + } else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) { + debug("tqma6ull ddr calibration lga variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00050009); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41340130); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40403A3E); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40402E28); + + } else { + pr_err("invalid/unsupported SoM variant ....\n"); + hang(); + } /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */ + } else { + pr_err("ERROR: invalid/unsupported CPU variant ....\n"); + hang(); + } /* IS_ENABLED(CONFIG_MX6UL) */ + break; + case SZ_256M: + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) { + debug("tqma6ul ddr calibration standard variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00000000); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41480144); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40404E54); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E48); + + } else if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) { + debug("tqma6ul ddr calibration lga variant ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MPWLDECTRL0, 0x00130003); + tq_som_init_write_reg(MX6_MMDC_P0_MPDGCTRL0, 0x41540154); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDLCTL, 0x40405050); + tq_som_init_write_reg(MX6_MMDC_P0_MPWRDLCTL, 0x40404E4C); + + } else { + pr_err("ERROR: invalid/unsupported SoM variant ....\n"); + hang(); + } /* IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD) */ + break; + default: + pr_err("ERROR: invalid/unsupported RAM size ....\n"); + hang(); + break; + } + + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333); + tq_som_init_write_reg(MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333); + + tq_som_init_write_reg(0x021B082C, 0xf3333333); /* MMDC_MPWRDQBY0DL */ + tq_som_init_write_reg(0x021B0830, 0xf3333333); /* MMDC_MPWRDQBY1DL */ + tq_som_init_write_reg(0x021B08C0, 0x00921012); /* MMDC_MPDCCR */ + + /* + * Complete calibration by forced measurement: + */ + tq_som_init_write_reg(MX6_MMDC_P0_MPMUR0, 0x00000800); + tq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002002D); + + debug("tqma6ul ddr mmdc ....\n"); + + tq_som_init_write_reg(MX6_MMDC_P0_MDOTC, 0x00333030); + tq_som_init_write_reg(MX6_MMDC_P0_MDCFG0, 0x676B52F3); + tq_som_init_write_reg(MX6_MMDC_P0_MDCFG1, 0xB66D8B63); + tq_som_init_write_reg(MX6_MMDC_P0_MDCFG2, 0x01FF00DB); + tq_som_init_write_reg(MX6_MMDC_P0_MDMISC, 0x00201740); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008000); + tq_som_init_write_reg(MX6_MMDC_P0_MDRWD, 0x000026D2); + tq_som_init_write_reg(MX6_MMDC_P0_MDOR, 0x006B1023); + + switch (size) { + case SZ_512M: + tq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x0000004F); + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x84180000); + break; + case SZ_256M: + tq_som_init_write_reg(MX6_MMDC_P0_MDASP, 0x00000047); + tq_som_init_write_reg(MX6_MMDC_P0_MDCTL, 0x83180000); + break; + default: + hang(); + break; + } + + debug("tqma6ul ddr cs0 ....\n"); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x02008032); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00008033); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00048031); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x15208030); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x04008040); + tq_som_init_write_reg(MX6_MMDC_P0_MDREF, 0x00000800); + tq_som_init_write_reg(MX6_MMDC_P0_MPODTCTRL, 0x00000227); + tq_som_init_write_reg(MX6_MMDC_P0_MDPDC, 0x0002552D); + tq_som_init_write_reg(MX6_MMDC_P0_MAPSR, 0x00011006); + tq_som_init_write_reg(MX6_MMDC_P0_MDSCR, 0x00000000); +} + +void tq_som_ram_init(void) +{ + int i; + /* RAM sizes need to be in descending order */ + static const u32 ram_sizes[] = { +#if IS_ENABLED(CONFIG_TQMA6UL_RAM_512M) + SZ_512M, +#endif +#if IS_ENABLED(CONFIG_TQMA6UL_RAM_256M) + SZ_256M, +#endif + }; + + if (!is_mx6ul() && !is_mx6ull()) { + pr_err("ERROR: Not running on TQMa6UL[L]\n"); + hang(); + } + + for (i = 0; i < ARRAY_SIZE(ram_sizes); i++) { + tqma6ul_init_ddr_controller(ram_sizes[i]); + if (tq_som_ram_check_size(ram_sizes[i])) + break; + } + + if (i < ARRAY_SIZE(ram_sizes)) { + debug("SPL: tqma6ul ddr init done ...\n"); + } else { + pr_err("ERROR: Invalid DDR RAM size\n"); + hang(); + } +} diff --git a/board/tq/tqma6ul/tqma6ul.c b/board/tq/tqma6ul/tqma6ul.c new file mode 100644 index 00000000000..999396f573d --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Marco Felsch, Nora Schiffer + * + */ + +#include <env.h> +#include <fdt_support.h> +#include <mmc.h> +#include <mtd_node.h> +#include <spi_flash.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> + +#include "../common/tq_bb.h" +#include "tqma6ul.h" + +int tq_bb_board_early_init_f(void) +{ + if (CONFIG_IS_ENABLED(FSL_QSPI)) + enable_qspi_clk(0); + + return 0; +} + +/** + * Checks if CPU (imx6ul or ima6ull) matches the one set for the image. + */ +static const char *check_cpu_variant(void) +{ + const char *cpu; + + if (is_mx6ul()) { + cpu = "ul"; + if (!IS_ENABLED(CONFIG_MX6UL)) + printf("*** ERROR: image not compiled for i.MX6UL!\n"); + } else if (is_mx6ull()) { + cpu = "ull"; + if (!IS_ENABLED(CONFIG_MX6ULL)) + printf("*** ERROR: image not compiled for i.MX6ULL!\n"); + } else { + printf("unknown CPU\n"); + return NULL; + } + + return cpu; +} + +/** + * Checks configuration for TQMa6UL SoM module variant. + */ +enum tqma6ul_som_type check_tqma6ul_variant(void) +{ + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) + return tqma6ul_som_type_ca; + + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) + return tqma6ul_som_type_lga; + + printf("unknown SoM variant\n"); + + return tqma6ul_som_type_unknown; +} + +/** + * Adjusts device tree name based on CPU variant. + */ +enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb) +{ + const char *tqma6ul_cpu, *tqma6ul_variant; + enum tqma6ul_som_type somtype; + u8 mx6ul_variant; + + tqma6ul_cpu = check_cpu_variant(); + if (!tqma6ul_cpu) + return tqma6ul_som_type_unknown; + + /* MX6UL1 vs MX6UL2 */ + mx6ul_variant = check_module_fused(MODULE_ENET2) ? 1 : 2; + + somtype = check_tqma6ul_variant(); + switch (somtype) { + case tqma6ul_som_type_ca: + tqma6ul_variant = ""; + break; + case tqma6ul_som_type_lga: + tqma6ul_variant = "l"; + break; + default: + return tqma6ul_som_type_unknown; + } + + snprintf(dt, dtsize, "imx6%s-tqma6%s%u%s-%s", + tqma6ul_cpu, tqma6ul_cpu, mx6ul_variant, tqma6ul_variant, mb); + + return somtype; +} + +#if !IS_ENABLED(CONFIG_SPL_BUILD) +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +const char *tq_som_get_modulename(void) +{ + if (is_mx6ul()) { + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) + return "TQMa6ULx"; + + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) + return "TQMa6ULxL"; + } + + if (is_mx6ull()) { + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_STANDARD)) + return "TQMa6ULLx"; + + if (IS_ENABLED(CONFIG_TQMA6UL_VARIANT_LGA)) + return "TQMa6ULLxL"; + } + + return "Unknown"; +} + +int checkboard(void) +{ + printf("Board: %s on %s\n", tq_som_get_modulename(), + tq_bb_get_boardname()); + + return tq_bb_checkboard(); +} + +#if IS_ENABLED(CONFIG_CMD_BMODE) +static const struct boot_mode tqma6ul_board_boot_modes[] = { + /* 4 bit bus width */ + {"sd", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int tq_bb_board_late_init(void) +{ + if (IS_ENABLED(CONFIG_CMD_BMODE)) + add_board_boot_modes(tqma6ul_board_boot_modes); + + env_set_runtime("board_name", tq_som_get_modulename()); + + return 0; +} + +int tq_bb_checkboard(void) +{ + if (is_mx6ul()) { + if (!IS_ENABLED(CONFIG_MX6UL)) + printf("*** ERROR: image not compiled for i.MX6UL!\n"); + } else if (is_mx6ull()) { + if (!IS_ENABLED(CONFIG_MX6ULL)) + printf("*** ERROR: image not compiled for i.MX6ULL!\n"); + } else { + printf("*** ERROR: unknown CPU variant!\n"); + } + + return 0; +} + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int tq_bb_ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ + +#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */ diff --git a/board/tq/tqma6ul/tqma6ul.cfg b/board/tq/tqma6ul/tqma6ul.cfg new file mode 100644 index 00000000000..42821ae5c7a --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.cfg @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + */ + +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +#if IS_ENABLED(CONFIG_QSPI_BOOT) +BOOT_FROM qspi +#else +BOOT_FROM sd +#endif + +#if IS_ENABLED(CONFIG_IMX_HAB) +CSF CONFIG_CSF_SIZE +#endif diff --git a/board/tq/tqma6ul/tqma6ul.env b/board/tq/tqma6ul/tqma6ul.env new file mode 100644 index 00000000000..fa172caca23 --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * TQMa6UL environment + */ + +#include <env/tq/tq-imx-shared.env> + +board=tqma6ul +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA6UL_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA6UL_FDT_ADDRESS +fdtoverlay_addr_r=TQMA6UL_FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +mmcautodetect=yes +mmcblkdev=0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +netdev=eth1 +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA6UL_INITRD_ADDRESS +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA6UL_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA6UL_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA6UL_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA6UL_SPI_UBOOT_START +uboot_spi_size=TQMA6UL_SPI_UBOOT_SIZE + +#ifdef CONFIG_USB_FUNCTION_FASTBOOT + +/* 0=user 1=boot1 2=boot2 */ +fastboot_mmc_boot_partition = 1 + +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0 + +fastboot_raw_partition_bootloader= + TQMA6UL_MMC_UBOOT_SECTOR_START TQMA6UL_MMC_UBOOT_SECTOR_COUNT mmcpart + "${fastboot_mmc_boot_partition}" + +fastbootcmd=fastboot usb 0 + +#endif /* CONFIG_USB_FUNCTION_FASTBOOT */ diff --git a/board/tq/tqma6ul/tqma6ul.h b/board/tq/tqma6ul/tqma6ul.h new file mode 100644 index 00000000000..595edc89e19 --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + */ + +enum tqma6ul_som_type { + /* unknown */ + tqma6ul_som_type_unknown, + /* connector module */ + tqma6ul_som_type_ca, + /* LGA Variant */ + tqma6ul_som_type_lga, +}; + +/** + * Checks configuration for TQMa6UL SoM module variant + */ +enum tqma6ul_som_type check_tqma6ul_variant(void); + +/** + * Adjusts device tree name based on CPU variant. + */ +enum tqma6ul_som_type set_tqma6ul_dt_name(char *dt, size_t dtsize, const char *mb); diff --git a/board/tq/tqma6ul/tqma6ul_mba6ul.c b/board/tq/tqma6ul/tqma6ul_mba6ul.c new file mode 100644 index 00000000000..be78060cbda --- /dev/null +++ b/board/tq/tqma6ul/tqma6ul_mba6ul.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Marco Felsch, Nora Schiffer + */ + +#include <env.h> +#include <malloc.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/mach-imx/sys_proto.h> + +#include "../common/tq_bb.h" +#include "tqma6ul.h" + +const char *tq_bb_get_boardname(void) +{ + return "MBa6ULx"; +} + +int board_early_init_f(void) +{ + return tq_bb_board_early_init_f(); +} + +static void mba6ul_setup_eth(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (check_module_fused(MODULE_ENET1)) { + printf("FEC1: disabled by fuses\n"); + } else { + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + enable_fec_anatop_clock(0, ENET_50MHZ); + } + + if (check_module_fused(MODULE_ENET2)) { + printf("FEC2: disabled by fuses\n"); + } else { + /* + * Use 50M anatop loopback REF_CLK1 for ENET2, + * clear gpr1[14], set gpr1[18] + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + enable_fec_anatop_clock(1, ENET_50MHZ); + } + + enable_enet_clk(1); +} + +int board_init(void) +{ + return 0; +} + +static void mba6ul_set_fdt_file(void) +{ + /* Longest FDT name */ + char dt[] = "imx6ull-tqma6ull2l-mba6ulx.dtb"; + enum tqma6ul_som_type somtype; + + if (!env_get("fdtfile")) { + somtype = set_tqma6ul_dt_name(dt, sizeof(dt), "mba6ulx.dtb"); + if (somtype == tqma6ul_som_type_unknown) + return; + + env_set_runtime("fdtfile", dt); + } +} + +int board_late_init(void) +{ + unsigned int bmode = + (imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT; + + tq_bb_board_late_init(); + + printf("Boot: "); + + switch (bmode) { + case IMX6_BMODE_MMC: + case IMX6_BMODE_EMMC: + printf("eMMC\n"); + env_set_runtime("boot_dev", "mmc"); + board_late_mmc_env_init(); + break; + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + printf("SD\n"); + env_set_runtime("boot_dev", "mmc"); + board_late_mmc_env_init(); + break; + case IMX6_BMODE_QSPI: + case IMX6_BMODE_NOR: + printf("QSPI\n"); + env_set_runtime("boot_dev", "qspi"); + break; + default: + printf("unhandled boot device %u\n", bmode); + } + + mba6ul_set_fdt_file(); + mba6ul_setup_eth(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + unsigned int port = (imx6_src_get_boot_mode() >> 11) & 0x3; + + switch (port) { + case 0: + /* SDHC1 - SD card on MBa6ULx */ + return 1; + + default: + /* Return eMMC device otherwise */ + return 0; + } +} + +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return tq_bb_ft_board_setup(blob, bd); +} +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/tqma7/Kconfig b/board/tq/tqma7/Kconfig new file mode 100644 index 00000000000..477ce3f3d53 --- /dev/null +++ b/board/tq/tqma7/Kconfig @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. +# Author: Markus Niebel, Steffen Doster +# + +if TARGET_TQMA7 + +config SYS_BOARD + default "tqma7" + +config SYS_VENDOR + default "tq" + +config SYS_CONFIG_NAME + default "tqma7" + +choice + prompt "TQMa7x RAM configuration" + default TQMA7_RAM_MULTI + help + Select RAM configuration. Normally use default here but for + specific setup it is possible to use a single RAM size. + +config TQMA7_RAM_MULTI + bool "TQMa7x with 512/1024/2048 MB RAM - Single image" + select TQMA7_RAM_2G + select TQMA7_RAM_1G + select TQMA7_RAM_512M + help + Build a single U-Boot solely for variants + with 512/1024/2048 MB RAM. + +config TQMA7_RAM_SINGLE_2G + bool "TQMa7x with 2 GB RAM" + select TQMA7_RAM_2G + help + Build U-Boot solely for variants + with 2 GB RAM. + +config TQMA7_RAM_SINGLE_1G + bool "TQMa7x with 1 GB RAM" + select TQMA7_RAM_1G + help + Build U-Boot solely for variants + with 1 GB RAM. + +config TQMA7_RAM_SINGLE_512M + bool "TQMa7x with 512 MB RAM" + select TQMA7_RAM_512M + help + Build U-Boot solely for variants + with 512 MB RAM. + +endchoice + +config TQMA7_RAM_2G + bool + +config TQMA7_RAM_1G + bool + +config TQMA7_RAM_512M + bool + +choice + prompt "TQMa7x base board variant" + default MBA7 + help + Select base board + for TQMa7x + +config MBA7 + bool "TQMa7x on MBa7x Starterkit" + select TQ_COMMON_BB + select TQ_COMMON_SOM + select TQ_COMMON_SYSINFO + select I2C_EEPROM + select MISC + imply USB + imply CMD_USB + imply USB_STORAGE + imply PHYLIB + imply CONFIG_PHY_TI_DP83867 + select MXC_UART + select DM_MMC + select DM_SPI + select DM_I2C + select DM_GPIO + imply DM_ETH + help + Select the MBa7x + starterkit. + +endchoice + +config IMX_CONFIG + default "board/tq/tqma7/tqma7.cfg" + +source "board/tq/common/Kconfig" + +endif diff --git a/board/tq/tqma7/Makefile b/board/tq/tqma7/Makefile new file mode 100644 index 00000000000..b1fb270e861 --- /dev/null +++ b/board/tq/tqma7/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. + + +obj-y += tqma7.o +obj-$(CONFIG_MBA7) += tqma7_mba7.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += spl_tqma7_ram.o +obj-$(CONFIG_MBA7) += spl_mba7.o +endif diff --git a/board/tq/tqma7/spl.c b/board/tq/tqma7/spl.c new file mode 100644 index 00000000000..62db30e81f2 --- /dev/null +++ b/board/tq/tqma7/spl.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + */ + +#include <fsl_esdhc_imx.h> +#include <hang.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch-mx7/mx7d_pins.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> + +#include "../common/tq_bb.h" +#include "../common/tq_som.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CMD_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | \ + PAD_CTL_SRE_SLOW | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_STROBE_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM) + +/* eMMC on USDHCI3 always present */ +static const iomux_v3_cfg_t tqma7_usdhc3_pads[] = { + NEW_PAD_CTRL(MX7D_PAD_SD3_CLK__SD3_CLK, USDHC_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_CMD__SD3_CMD, USDHC_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA0__SD3_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA1__SD3_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA2__SD3_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA3__SD3_DATA3, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA4__SD3_DATA4, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA5__SD3_DATA5, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA6__SD3_DATA6, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA7__SD3_DATA7, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_STROBE__SD3_STROBE, USDHC_STROBE_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg tqma7_usdhc3_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 1; + else + ret = tq_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is not WP */ + ret = 0; + else + ret = tq_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma7_usdhc3_pads, + ARRAY_SIZE(tqma7_usdhc3_pads)); + + tqma7_usdhc3_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + if (fsl_esdhc_initialize(bis, &tqma7_usdhc3_cfg)) + puts("Warning: failed to initialize eMMC dev\n"); + + tq_bb_board_mmc_init(bis); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return tq_bb_board_init(); +} + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + timer_init(); + + tq_bb_board_early_init_f(); + + preloader_console_init(); + + /* DDR initialization */ + tq_som_ram_init(); +} + diff --git a/board/tq/tqma7/spl_mba7.c b/board/tq/tqma7/spl_mba7.c new file mode 100644 index 00000000000..13438247731 --- /dev/null +++ b/board/tq/tqma7/spl_mba7.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + */ + +#include <fsl_esdhc_imx.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch-mx7/mx7d_pins.h> + +#include "../common/tq_bb.h" + +#define UART_RX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_PUE | PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +#define UART_TX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_PUE | PAD_CTL_SRE_SLOW) + +#define USDHC_DATA_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CMD_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_STROBE_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_196OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW) +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +static const iomux_v3_cfg_t mba7_uart6_pads[] = { + NEW_PAD_CTRL(MX7D_PAD_EPDC_DATA08__UART6_DCE_RX, UART_RX_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_EPDC_DATA09__UART6_DCE_TX, UART_TX_PAD_CTRL), +}; + +static void mba7_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba7_uart6_pads, ARRAY_SIZE(mba7_uart6_pads)); +} + +static const iomux_v3_cfg_t mba7_usdhc1_pads[] = { + NEW_PAD_CTRL(MX7D_PAD_SD1_CLK__SD1_CLK, USDHC_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_CMD__SD1_CMD, USDHC_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA0__SD1_DATA0, USDHC_DATA_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA1__SD1_DATA1, USDHC_DATA_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA2__SD1_DATA2, USDHC_DATA_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA3__SD1_DATA3, USDHC_DATA_PAD_CTRL), + /* CD */ + NEW_PAD_CTRL(MX7D_PAD_SD1_CD_B__GPIO5_IO0, GPIO_IN_PAD_CTRL), + /* WP */ + NEW_PAD_CTRL(MX7D_PAD_SD1_WP__GPIO5_IO1, GPIO_IN_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC1_WP_GPIO IMX_GPIO_NR(5, 1) + +int tq_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = !gpio_get_value(USDHC1_CD_GPIO); + + return ret; +} + +int tq_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = gpio_get_value(USDHC1_WP_GPIO); + + return ret; +} + +static struct fsl_esdhc_cfg mba7_usdhc_cfg = { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, +}; + +int tq_bb_board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(mba7_usdhc1_pads, + ARRAY_SIZE(mba7_usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1-cd"); + gpio_request(USDHC1_WP_GPIO, "usdhc1-wp"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_direction_input(USDHC1_WP_GPIO); + + mba7_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + if (fsl_esdhc_initialize(bis, &mba7_usdhc_cfg)) + puts("Warning: failed to initialize SD\n"); + + return 0; +} + +int tq_bb_board_early_init_f(void) +{ + /* iomux and setup of uart */ + mba7_setup_iomuxc_uart(); + + return 0; +} + +/* + * This is done per baseboard to allow different implementations + */ +void board_boot_order(u32 *spl_boot_list) +{ + enum boot_device bd; + /* + * try to get sd card slots in order: + * eMMC: on Module + * -> therefore index 0 for bootloader + * index n in kernel (controller instance 3) -> patches needed for + * alias indexing + * SD1: on Mainboard + * index n in kernel (controller instance 1) -> patches needed for + * alias indexing + * we assume to have a kernel patch that will present mmcblk dev + * indexed like controller devs + */ + puts("Boot: "); + + bd = get_boot_device(); + switch (bd) { + case MMC3_BOOT: + puts("USDHC3(eMMC)\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case SD1_BOOT: + puts("USDHC1(SD)\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + case QSPI_BOOT: + puts("QSPI\n"); + spl_boot_list[0] = BOOT_DEVICE_NOR; + break; + case USB_BOOT: + puts("USB\n"); + spl_boot_list[0] = BOOT_DEVICE_BOARD; + break; + default: + /* Default - BOOT_DEVICE_MMC1 */ + puts("WARN: unknown boot device, fallback to eMMC\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + } +} + +int board_fit_config_name_match(const char *name) +{ + char *config = NULL; + + if (is_cpu_type(MXC_CPU_MX7S)) + config = "imx7s-mba7"; + else if (is_cpu_type(MXC_CPU_MX7D)) + config = "imx7d-mba7"; + + if (strcmp(config, name)) + return -EINVAL; + + printf("Device tree: %s\n", name); + + return 0; +} diff --git a/board/tq/tqma7/spl_tqma7_ram.c b/board/tq/tqma7/spl_tqma7_ram.c new file mode 100644 index 00000000000..903df5d9d0f --- /dev/null +++ b/board/tq/tqma7/spl_tqma7_ram.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + */ + +#include <config.h> +#include <hang.h> +#include <asm/arch/imx-regs.h> +#include <asm/mach-imx/iomux-v3.h> +#include <linux/sizes.h> + +#include "../common/tq_som.h" + +#define DDRC_RFSHTMG_512M 0x0020002B +#define DDRC_RFSHTMG_1G 0x00200045 +#define DDRC_RFSHTMG_2G 0x0020005D + +#define DDRC_ADDRMAP1_512M 0x00161616 +#define DDRC_ADDRMAP1_1G 0x00171717 +#define DDRC_ADDRMAP1_2G 0x00181818 + +#define DDRC_ADDRMAP6_512M 0x0F0F0404 +#define DDRC_ADDRMAP6_1G 0x0F040404 +#define DDRC_ADDRMAP6_2G 0x04040404 + +#define DDR_PHY_OFFSET_RD_CON0_512M 0x0B0B0B0B +#define DDR_PHY_OFFSET_RD_CON0_1G 0x0B0B0B0B +#define DDR_PHY_OFFSET_RD_CON0_2G 0x0A0A0A0A + +#define DDR_PHY_OFFSET_WR_CON0_512M 0x06060606 +#define DDR_PHY_OFFSET_WR_CON0_1G 0x06060606 +#define DDR_PHY_OFFSET_WR_CON0_2G 0x04040404 + +static void tqma7_ddr_exit_retention(void) +{ + /* Clear then set bit30 to ensure exit from DDR retention */ + tq_som_init_write_reg(0x30360388, 0x40000000); + tq_som_init_write_reg(0x30360384, 0x40000000); +} + +static void gpr_init(void) +{ + /* reset default and enable GPR OCRAM EPDC */ + tq_som_init_write_reg(0x30340004, 0x4F400005); +} + +static void tqma7_ccgr_init(void) +{ + tq_som_init_write_reg(0x30384130, 0x00000000); /* CCM_CCGR19 */ + tq_som_init_write_reg(0x30340020, 0x00000178); /* IOMUXC_GPR_GPR8 */ + tq_som_init_write_reg(0x30384130, 0x00000002); /* CCM_CCGR19 */ + tq_som_init_write_reg(0x30790018, 0x0000000f); /* DDR_PHY_LP_CON0 */ + + /* wait for auto-ZQ calibration to complete */ + tq_som_check_bits_set(0x307a0004, 0x1); /* DDRC_STAT */ +} + +static void ddr_init_error(const char *msg) +{ + pr_err("%s", msg); + hang(); +} + +#define TQMA7_SELECT_DDR_VALUE(SIZE, NAME) \ + ((SIZE) == SZ_512M ? NAME ## _512M : \ + ((SIZE) == SZ_1G ? NAME ## _1G : \ + ((SIZE) == SZ_2G ? NAME ## _2G : \ + (ddr_init_error("Invalid DDR RAM size detected"), 0)))) + +static void tqma7_init_ddr_controller(u32 size) +{ + gpr_init(); + + /* TQMa7 DDR config */ + /* TQMa7x DRAM Timing REV0201A */ + /* DCD Code i.MX7D/S 528 MHz 512 MByte Samsung K4B2G1646F */ + tq_som_init_write_reg(0x30360070, 0x0070302C); /*CCM_ANALOG_PLL_DDRx*/ + tq_som_init_write_reg(0x30360090, 0x00000000); /*CCM_ANALOG_PLL_NUM*/ + tq_som_init_write_reg(0x30360070, 0x0060302C); /*CCM_ANALOG_PLL_DDRx*/ + + tq_som_check_bits_set(0x30360070, 0x80000000); + + tq_som_init_write_reg(0x30391000, 0x00000002); /*SRC_DDRC_RCR*/ + tq_som_init_write_reg(0x307a0000, 0x01040001); /*DDRC_MSTR*/ + tq_som_init_write_reg(0x307a01a0, 0x80400003); /*DDRC_DFIUPD0*/ + tq_som_init_write_reg(0x307a01a4, 0x00100020); /*DDRC_DFIUPD1*/ + tq_som_init_write_reg(0x307a01a8, 0x80100004); /*DDRC_DFIUPD2*/ + tq_som_init_write_reg(0x307a0064, TQMA7_SELECT_DDR_VALUE(size, DDRC_RFSHTMG)); + tq_som_init_write_reg(0x307a0490, 0x00000001); /*DDRC_MP_PCTRL_0*/ + tq_som_init_write_reg(0x307a00d0, 0x00020081); /*DDRC_INIT0*/ + tq_som_init_write_reg(0x307a00d4, 0x00680000); /*DDRC_INIT1*/ + tq_som_init_write_reg(0x307a00dc, 0x09300004); /*DDRC_INIT3*/ + tq_som_init_write_reg(0x307a00e0, 0x00480000); /*DDRC_INIT4*/ + tq_som_init_write_reg(0x307a00e4, 0x00100004); /*DDRC_INIT5*/ + tq_som_init_write_reg(0x307a00f4, 0x0000033F); /*DDRC_RANKCTL*/ + tq_som_init_write_reg(0x307a0100, 0x090E0809); /*DDRC_DRAMTMG0*/ + tq_som_init_write_reg(0x307a0104, 0x0007020E); /*DDRC_DRAMTMG1*/ + tq_som_init_write_reg(0x307a0108, 0x03040407); /*DDRC_DRAMTMG2*/ + tq_som_init_write_reg(0x307a010c, 0x00002006); /*DDRC_DRAMTMG3*/ + tq_som_init_write_reg(0x307a0110, 0x04020304); /*DDRC_DRAMTMG4*/ + tq_som_init_write_reg(0x307a0114, 0x03030202); /*DDRC_DRAMTMG5*/ + tq_som_init_write_reg(0x307a0120, 0x00000803); /*DDRC_DRAMTMG8*/ + tq_som_init_write_reg(0x307a0180, 0x00800020); /*DDRC_ZQCTL0*/ + tq_som_init_write_reg(0x307a0190, 0x02098204); /*DDRC_DFITMG0*/ + tq_som_init_write_reg(0x307a0194, 0x00030303); /*DDRC_DFITMG1*/ + tq_som_init_write_reg(0x307a0200, 0x0000001F); /*DDRC_ADDRMAP0*/ + tq_som_init_write_reg(0x307a0204, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP1)); + tq_som_init_write_reg(0x307a020C, 0x00000000); /*DDRC_ADDRMAP3*/ + tq_som_init_write_reg(0x307a0210, 0x00000F0F); /*DDRC_ADDRMAP4*/ + tq_som_init_write_reg(0x307a0214, 0x04040404); /*DDRC_ADDRMAP5*/ + tq_som_init_write_reg(0x307a0218, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP6)); + tq_som_init_write_reg(0x307a0240, 0x06000604); /*DDRC_ODTCFG*/ + tq_som_init_write_reg(0x307a0244, 0x00000001); /*DDRC_ODTMAP*/ + tq_som_init_write_reg(0x30391000, 0x00000000); /*SRC_DDRC_RCR*/ + tq_som_init_write_reg(0x30790000, 0x17420F40); /*DDR_PHY_PHY_CON0*/ + tq_som_init_write_reg(0x30790004, 0x10210100); /*DDR_PHY_PHY_CON1*/ + tq_som_init_write_reg(0x30790010, 0x00060807); /*DDR_PHY_PHY_CON4*/ + tq_som_init_write_reg(0x307900b0, 0x1010007E); /*DDR_PHY_MDLL_CON0*/ + tq_som_init_write_reg(0x3079009c, 0x00000924); /*DDR_PHY_DRVDS_CON0*/ + + tq_som_init_write_reg(0x30790020, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_RD_CON0)); + tq_som_init_write_reg(0x30790030, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_WR_CON0)); + tq_som_init_write_reg(0x30790050, 0x01000010); /*DDR_PHY_CMD_SDLL_CON0*/ + tq_som_init_write_reg(0x30790050, 0x00000010); /*DDR_PHY_CMD_SDLL_CON0*/ + + tq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/ + tq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/ + tq_som_init_write_reg(0x307900c0, 0x0C447306); /*DDR_PHY_ZQ_CON0*/ + + tq_som_check_bits_set(0x307900c4, 0x1); /*ZQ Calibration is finished*/ + + tq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/ + tq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/ + + tqma7_ccgr_init(); +} + +void tq_som_ram_init(void) +{ + /* RAM sizes need to be in descending order */ + static const u32 ram_sizes[] = { +#if IS_ENABLED(CONFIG_TQMA7_RAM_2G) + SZ_2G, +#endif +#if IS_ENABLED(CONFIG_TQMA7_RAM_1G) + SZ_1G, +#endif +#if IS_ENABLED(CONFIG_TQMA7_RAM_512M) + SZ_512M, +#endif + }; + int i; + + debug("SPL: tqma7 iomux ....\n"); + tqma7_ddr_exit_retention(); + + for (i = 0; i < ARRAY_SIZE(ram_sizes); i++) { + tqma7_init_ddr_controller(ram_sizes[i]); + if (tq_som_ram_check_size(ram_sizes[i])) + break; + } + + if (i < ARRAY_SIZE(ram_sizes)) { + debug("SPL: tqma7 ddr init done ...\n"); + } else { + pr_err("Error: Invalid DDR RAM size\n"); + hang(); + } +} diff --git a/board/tq/tqma7/tqma7.c b/board/tq/tqma7/tqma7.c new file mode 100644 index 00000000000..ccf805d5461 --- /dev/null +++ b/board/tq/tqma7/tqma7.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Steffen Doster + */ + +#include <env.h> +#include <fdt_support.h> +#include <mtd_node.h> +#include <spi_flash.h> +#include <asm/bootm.h> +#include <asm/setup.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#include "../common/tq_bb.h" +#include "../common/tq_som.h" +#include "../common/tq_sysinfo.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +#if (!IS_ENABLED(CONFIG_SPL_BUILD)) + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + if (IS_ENABLED(CONFIG_FSL_QSPI)) + set_clk_qspi(); + + return tq_bb_board_init(); +} + +static const char *tqma7_get_boardname(void) +{ + switch (get_cpu_type()) { + case MXC_CPU_MX7S: + return "TQMa7S"; + case MXC_CPU_MX7D: + return "TQMa7D"; + default: + return "??"; + }; +} + +int board_late_init(void) +{ + const char *bname = tqma7_get_boardname(); + int ret; + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + struct tag_serialnr serialnr; + + get_board_serial(&serialnr); + + printf("UID: %08x%08x\n", serialnr.high, serialnr.low); + } + + env_set_runtime("board_name", bname); + + ret = tq_common_sysinfo_setup(); + if (ret) + log_err("Sysinfo setup failed: %d\n", ret); + + return tq_bb_board_late_init(); +} + +static u32 tqma7_get_board_rev(void) +{ + /* REV.0100 is unsupported */ + return 200; +} + +int checkboard(void) +{ + printf("Board: %s REV.%04u\n", tq_bb_get_boardname(), tqma7_get_board_rev()); + return 0; +} + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + tq_bb_ft_board_setup(blob, bd); + + return 0; +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + +#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */ diff --git a/board/tq/tqma7/tqma7.cfg b/board/tq/tqma7/tqma7.cfg new file mode 100644 index 00000000000..2e807d62348 --- /dev/null +++ b/board/tq/tqma7/tqma7.cfg @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Steffen Doster + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#include <config.h> + +/* + * Set to sd even for QSPI boot on i.MX7, as i.MX7 uses offset 0x400 rather + * than 0x1000 for QSPI + */ +BOOT_FROM sd + +#if IS_ENABLED(CONFIG_IMX_HAB) +CSF CONFIG_CSF_SIZE +#endif diff --git a/board/tq/tqma7/tqma7.env b/board/tq/tqma7/tqma7.env new file mode 100644 index 00000000000..05035078869 --- /dev/null +++ b/board/tq/tqma7/tqma7.env @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + * + * TQMa7x environment + */ + +#include <env/tq/tq-imx-shared.env> + +board=tqma7 +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA7_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA7_FDT_ADDRESS +fdtoverlay_addr_r=FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +netdev=eth0 +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA7_INITRD_ADDRESS +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA7_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA7_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA7_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA7_SPI_UBOOT_START +uboot_spi_size=TQMA7_SPI_UBOOT_SIZE + +#ifdef CONFIG_USB_FUNCTION_FASTBOOT + +/* 0=user 1=boot1 2=boot2 */ +fastboot_mmc_boot_partition = 1 + +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV:0 +fastboot_raw_partition_bootloader= + TQMA7_MMC_UBOOT_SECTOR_START TQMA7_MMC_UBOOT_SECTOR_COUNT mmcpart + "${fastboot_mmc_boot_partition}" +fastbootcmd=fastboot usb 0 + +#endif diff --git a/board/tq/tqma7/tqma7_mba7.c b/board/tq/tqma7/tqma7_mba7.c new file mode 100644 index 00000000000..65c6c08771d --- /dev/null +++ b/board/tq/tqma7/tqma7_mba7.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Steffen Doster + */ + +#include <env.h> +#include <errno.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-mx7/imx-regs.h> +#include <asm/mach-imx/boot_mode.h> + +#include "../common/tq_bb.h" + +const char *tq_bb_get_boardname(void) +{ + return "MBa7x"; +} + +#if !IS_ENABLED(CONFIG_SPL_BUILD) + +static int mba7_setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + switch (fec_id) { + case 0: + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 0); + break; + case 1: + /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK, 0); + break; + default: + printf("FEC%d: unsupported\n", fec_id); + return -EINVAL; + } + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + +int tq_bb_board_init(void) +{ + mba7_setup_fec(0); + + if (!is_cpu_type(MXC_CPU_MX7S)) + mba7_setup_fec(1); + + return 0; +} + +int tq_bb_board_late_init(void) +{ + puts("Boot: "); + + if (is_boot_from_usb()) { + puts("USB\n"); + env_set_runtime("boot_dev", "mmc"); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + } else { + /* + * try to get sd card slots in order: + * eMMC: on Module + * -> therefore index 0 for bootloader + * index n in kernel (controller instance 3) -> patches needed for + * alias indexing + * SD1: on Mainboard + * index n in kernel (controller instance 1) -> patches needed for + * alias indexing + * we assume to have a kernel patch that will present mmcblk dev + * indexed like controller devs + */ + enum boot_device bd = get_boot_device(); + + switch (bd) { + case MMC3_BOOT: + puts("USDHC3(eMMC)\n"); + env_set_runtime("boot_dev", "mmc"); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + break; + case SD1_BOOT: + puts("USDHC1(SD)\n"); + env_set_runtime("boot_dev", "mmc"); + env_set_runtime("mmcdev", "1"); + env_set_runtime("mmcblkdev", "1"); + break; + case QSPI_BOOT: + puts("QSPI\n"); + env_set_runtime("boot_dev", "qspi"); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + break; + default: + printf("unhandled boot device %d\n", (int)bd); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + } + } + + if (!env_get("fdtfile")) { + /* provide default setting for fdtfile if nothing in env is set */ + + switch (get_cpu_type()) { + case MXC_CPU_MX7S: + env_set_runtime("fdtfile", "imx7s-mba7.dtb"); + break; + case MXC_CPU_MX7D: + env_set_runtime("fdtfile", "imx7d-mba7.dtb"); + break; + default: + debug("unknown CPU"); + } + } + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + switch (devno) { + case 2: + /* eMMC */ + return 0; + case 0: + /* SD card */ + return 1; + default: + /* Unknown */ + return 0; + } +} + +#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */ diff --git a/board/traverse/common/Kconfig b/board/traverse/common/Kconfig index d34832bd0d3..96b2566b697 100644 --- a/board/traverse/common/Kconfig +++ b/board/traverse/common/Kconfig @@ -2,5 +2,5 @@ config TEN64_CONTROLLER bool "Enable Ten64 board controller driver" depends on TARGET_TEN64 help - Support for the board microcontroller on the Traverse - Ten64 family of boards. + Support for the board microcontroller on the Traverse + Ten64 family of boards. diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index d41bd2e9dee..5c45f9932c5 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -148,7 +148,7 @@ int fsl_initdram(void) void detail_board_ddr_info(void) { puts("\nDDR "); - print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); + print_size(gd->dram[0].size + gd->dram[1].size, ""); print_ddr_info(0); } @@ -186,6 +186,58 @@ void fdt_fixup_board_enet(void *fdt) fdt_status_fail(fdt, offset); } +/* The onboard USB hub driver (microchip,usb5744) + * can cause a disconnect-reconnect loop if the operating system + * attempts to re-initialise the hub after U-Boot has already done it. + * (This process only needs to be done once per system RESET cycle) + * + * To avoid this condition, make the hub topology invisible + * to the operating system. + * It is also required to remove the hub on boards + * without it (RevD). + * + * The USB hub fixup may fail for legitimate reasons: + * 1. FDT has already been fixed. For example, the control + * FDT previously modified by board_fix_fdt is + * re-used for bootflow. + * 2. The FDT blob is based on an older version + * without the hub topology, such as older OpenWrt + * FIT images with their own device tree. + */ +int fdt_fixup_usb_hub(void *fdt) +{ + int usb1_hub2744_offset, usb1_hub5744_offset; + int i2c_usb5744_offset; + int err; + + usb1_hub2744_offset = fdt_path_offset(fdt, "/soc/usb@3110000/hub@1"); + + if (usb1_hub2744_offset < 0) + return usb1_hub2744_offset; + + err = fdt_del_node(fdt, usb1_hub2744_offset); + if (err) + return err; + + usb1_hub5744_offset = fdt_path_offset(fdt, "/soc/usb@3110000/hub@2"); + if (usb1_hub5744_offset < 0) + return usb1_hub5744_offset; + + err = fdt_del_node(fdt, usb1_hub5744_offset); + if (err) + return err; + + i2c_usb5744_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/usb-hub@2d"); + if (i2c_usb5744_offset < 0) + return i2c_usb5744_offset; + + err = fdt_setprop_string(fdt, i2c_usb5744_offset, "status", "disabled"); + if (err) + return err; + + return 0; +} + /* Called after SoC board_late_init in fsl-layerscape/soc.c */ int fsl_board_late_init(void) { @@ -225,15 +277,15 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* fixup DT for the two GPP DDR banks */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - base[i] = gd->bd->bi_dram[i].start; - size[i] = gd->bd->bi_dram[i].size; + base[i] = gd->dram[i].start; + size[i] = gd->dram[i].size; /* reduce size if reserved memory is within this bank */ if (IS_ENABLED(CONFIG_RESV_RAM) && RESV_MEM_IN_BANK(i)) size[i] = gd->arch.resv_ram - base[i]; } if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; @@ -251,6 +303,24 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_icid(blob); + /* This fixup may fail for legitimate + * reasons (see comments for fdt_fixup_usb_hub). + * Hence, errors with it are silently ignored. + */ + fdt_fixup_usb_hub(blob); + return 0; +} + +/* board_fix_fdt: fixup function for internal (U-Boot) FDT */ +int board_fix_fdt(void *fdt) +{ + u32 board_rev = ten64_get_board_rev(); + + /* Delete USB Hub references in U-Boot's FDT on + * boards without one. + */ + if (board_rev == TEN64_BOARD_REV_D) + fdt_fixup_usb_hub(fdt); return 0; } diff --git a/board/turing/turing-rk1-rk3588/MAINTAINERS b/board/turing/turing-rk1-rk3588/MAINTAINERS index 4f313732fa1..973ac68836c 100644 --- a/board/turing/turing-rk1-rk3588/MAINTAINERS +++ b/board/turing/turing-rk1-rk3588/MAINTAINERS @@ -4,6 +4,4 @@ S: Maintained F: board/turing/turing-rk1-rk3588 F: include/configs/turing-rk1-rk3588.h F: configs/turing-rk1-rk3588_defconfig -F: arch/arm/dts/rk3588-turing-rk1.dts -F: arch/arm/dts/rk3588-turing-rk1.dtsi -F: arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi +F: arch/arm/dts/rk3588-turing-rk1* diff --git a/board/variscite/omap4_var_som/Kconfig b/board/variscite/omap4_var_som/Kconfig new file mode 100644 index 00000000000..dc943b3366e --- /dev/null +++ b/board/variscite/omap4_var_som/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP4_VAR_SOM + +config SYS_BOARD + default "omap4_var_som" + +config SYS_VENDOR + default "variscite" + +config SYS_CONFIG_NAME + default "ti_omap4_common" + +endif diff --git a/board/variscite/omap4_var_som/MAINTAINERS b/board/variscite/omap4_var_som/MAINTAINERS new file mode 100644 index 00000000000..a8680bc75d3 --- /dev/null +++ b/board/variscite/omap4_var_som/MAINTAINERS @@ -0,0 +1,4 @@ +ARM OMAP4 VARISCITE VAR-SOM-OM44 MODULE +M: Bastien Curutchet <[email protected]> +S: Maintained +N: omap4_var_som diff --git a/board/variscite/omap4_var_som/Makefile b/board/variscite/omap4_var_som/Makefile new file mode 100644 index 00000000000..c88ab3cac7b --- /dev/null +++ b/board/variscite/omap4_var_som/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, [email protected]. + +obj-y := omap4_var_som.o diff --git a/board/variscite/omap4_var_som/omap4_var_som.c b/board/variscite/omap4_var_som/omap4_var_som.c new file mode 100644 index 00000000000..f2fc790dd4b --- /dev/null +++ b/board/variscite/omap4_var_som/omap4_var_som.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/emif.h> +#include <asm/global_data.h> +#include <asm/mach-types.h> +#include <asm-generic/gpio.h> +#include <env.h> +#include <init.h> +#include <linux/delay.h> +#include <log.h> +#include <serial.h> + +#include "omap4_var_som_mux.h" + +#define VAR_SOM_REV_GPIO 52 + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: OMAP4 VAR-SOM-OM44\n" +}; + +struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000; + +/** + * @brief board_init + * + * Return: 0 + */ +int board_init(void) +{ + gpmc_init(); + + gd->bd->bi_arch_number = MACH_TYPE_OMAP4_VAR_SOM; + gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ + + return 0; +} + +static const struct emif_regs emif_regs_hynix_kdpm_400_mhz_1cs = { + .sdram_config_init = 0x80000eb2, + .sdram_config = 0x80001ab2, + .ref_ctrl = 0x000005cd, + .sdram_tim1 = 0x10cb0622, + .sdram_tim2 = 0x20350d52, + .sdram_tim3 = 0x00b1431f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0x500b3214, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +const struct emif_regs emif_regs_hynix_kdpm_400_mhz_2cs = { + .sdram_config_init = 0x80000eb9, + .sdram_config = 0x80001ab9, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0xd00b3214, + .temp_alert_config = 0xd8016893, + .emif_ddr_phy_ctlr_1_init = 0x049ffff5, + .emif_ddr_phy_ctlr_1 = 0x049ff418 +}; + +/* + * emif_get_reg_dump() - emif_get_reg_dump strong function + * + * @emif_nr - emif base + * @regs - reg dump of timing values + * + * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c + */ +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + u32 rev; + + gpio_direction_input(VAR_SOM_REV_GPIO); + rev = gpio_get_value(VAR_SOM_REV_GPIO); + + if (rev == 1) + *regs = &emif_regs_hynix_kdpm_400_mhz_1cs; + else + *regs = &emif_regs_hynix_kdpm_400_mhz_2cs; +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs + **dmm_lisa_regs) +{ + u32 omap_rev = omap_revision(); + + if (omap_rev == OMAP4430_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; + else if (omap_rev == OMAP4430_ES2_3) + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else if (omap_rev < OMAP4460_ES1_0) + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else + *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; +} + +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings) +{ + /* Identical devices on EMIF1 & EMIF2 */ + *cs0_device_timings = &elpida_2G_S4_timings; + *cs1_device_timings = NULL; +} + +/** + * @brief misc_init_r() - VAR-SOM configuration + * + * Configure VAR-SOM board specific configurations such as power configurations. + * + * Return: 0 + */ +int misc_init_r(void) +{ + u32 auxclk, altclksrc; + + auxclk = readl(&scrm->auxclk3); + /* Select sys_clk */ + auxclk &= ~AUXCLK_SRCSELECT_MASK; + auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; + /* Set the divisor to 2 */ + auxclk &= ~AUXCLK_CLKDIV_MASK; + auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; + /* Request auxilary clock #3 */ + auxclk |= AUXCLK_ENABLE_MASK; + + writel(auxclk, &scrm->auxclk3); + + altclksrc = readl(&scrm->altclksrc); + + /* Activate alternate system clock supplier */ + altclksrc &= ~ALTCLKSRC_MODE_MASK; + altclksrc |= ALTCLKSRC_MODE_ACTIVE; + + /* enable clocks */ + altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK; + + writel(altclksrc, &scrm->altclksrc); + + return 0; +} + +void set_muxconf_regs(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + do_set_mux((*ctrl)->control_padconf_core_base, + core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux((*ctrl)->control_padconf_wkup_base, + wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + } +} + +int board_mmc_init(struct bd_info *bis) +{ + if (IS_ENABLED(CONFIG_MMC)) + return omap_mmc_init(0, 0, 0, -1, -1); +} diff --git a/board/variscite/omap4_var_som/omap4_var_som_mux.h b/board/variscite/omap4_var_som/omap4_var_som_mux.h new file mode 100644 index 00000000000..fe0b99daf75 --- /dev/null +++ b/board/variscite/omap4_var_som/omap4_var_som_mux.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _VAR_SOM_OM44_MUX_DATA_H_ +#define _VAR_SOM_OM44_MUX_DATA_H_ + +#include <asm/arch/mux_omap4.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +{GPMC_NCS2, (PTD | IEN | M3)}, /* gpio52 som rev */ +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ +{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ +{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +{UART3_TX_IRTX, (M0)}, /* uart3_tx */ +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { +{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ +{PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ +{PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ +{PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ +{PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ +{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ +{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ +{PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ +}; + +#endif /* _VAR_SOM_OM44_MUX_DATA_H_ */ diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 5c3240da073..07fc8da1b71 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -67,7 +67,7 @@ config BOOT_SCRIPT_OFFSET default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0 if TARGET_XILINX_MBV help - Specifies distro boot script offset in NAND/QSPI/NOR flash. + Specifies distro boot script offset in NAND/QSPI/NOR flash. config CMD_FRU bool "FRU information for product" diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index d022308f943..52a2e8767d8 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -14,8 +14,12 @@ #include <init.h> #include <jffs2/load_kernel.h> #include <log.h> +#include <asm/io.h> #include <asm/global_data.h> #include <asm/sections.h> +#if defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL2) +#include <asm/arch/hardware.h> +#endif #include <dm/uclass.h> #include <i2c.h> #include <linux/sizes.h> @@ -30,6 +34,8 @@ #include <rng.h> #include <slre.h> #include <soc.h> +#include <zynqmp_firmware.h> +#include <linux/bitfield.h> #include <linux/ctype.h> #include <linux/kernel.h> #include <u-boot/uuid.h> @@ -508,8 +514,7 @@ int board_late_init_xilinx(void) ret |= env_set_by_index("uuid", id, uuid); } - if (!(CONFIG_IS_ENABLED(NET) || - CONFIG_IS_ENABLED(NET_LWIP))) + if (!CONFIG_IS_ENABLED(NET)) continue; for (i = 0; i < EEPROM_HDR_NO_OF_MAC_ADDR; i++) { @@ -719,7 +724,74 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return reg + size; } +#endif + +#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) + +#if defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL2) +/* + * The Versal and Versal Gen 2 PMC Global pggs4 register contains below + * information in each byte as: + * + * Byte[3]: Magic number + * Byte[2]: Boot counter value + * Byte[1]: Boot partition value - boot index + * Byte[0]: Rollback counter value + */ + +#define MAGIC_NUM 0x1D +#define MAGIC_MASK GENMASK(31, 24) +#define BOOTINDEX_MASK GENMASK(15, 8) + +static int plat_get_boot_index(void) +{ + u32 val; + + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) + val = zynqmp_pm_get_pmc_global_pggs_reg(PMC_GLOBAL_PGGS4_REG); + else + val = readl(PMC_GLOBAL_PGGS4_REG); + + if (FIELD_GET(MAGIC_MASK, val) != MAGIC_NUM) { + log_err("FWU requires PMC magic number 0x%x\n", MAGIC_NUM); + return -EINVAL; + } + + return FIELD_GET(BOOTINDEX_MASK, val); +} +#endif + +int fwu_plat_get_alt_num(struct udevice __always_unused *dev, + efi_guid_t *image_id, u8 *alt_num) +{ + int ret; + + ret = fwu_mtd_get_alt_num(image_id, alt_num, "nor0"); + debug("%s: return %d\n", __func__, ret); + + return ret; +} +void fwu_plat_get_bootidx(uint *boot_idx) +{ + int ret; + u32 active_idx; + + ret = fwu_get_active_index(&active_idx); + if (ret < 0) + printf("%s: failed to read active index\n", __func__); + + ret = plat_get_boot_index(); + if (ret < 0) { + *boot_idx = 0; + printf("%s: failed and setup boot index to 0\n", __func__); + } else { + *boot_idx = ret; + } + + debug("%s: boot_idx: %d, active_idx: %d\n", + __func__, *boot_idx, active_idx); +} #endif #if IS_ENABLED(CONFIG_BOARD_RNG_SEED) diff --git a/board/xilinx/microblaze-generic/MAINTAINERS b/board/xilinx/microblaze-generic/MAINTAINERS index 29ed32f78f9..5220a51a5ea 100644 --- a/board/xilinx/microblaze-generic/MAINTAINERS +++ b/board/xilinx/microblaze-generic/MAINTAINERS @@ -1,7 +1,7 @@ MICROBLAZE-GENERIC BOARD M: Michal Simek <[email protected]> S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git F: board/xilinx/microblaze-generic/ F: include/configs/microblaze-generic.h F: configs/microblaze-generic_defconfig diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 65b2a451ad7..ddac92660df 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -12,6 +12,7 @@ #include <env_internal.h> #include <log.h> #include <malloc.h> +#include <mmc.h> #include <spi.h> #include <time.h> #include <asm/cache.h> @@ -21,11 +22,9 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> -#include <zynqmp_firmware.h> #include <versalpl.h> #include "../common/board.h" -#include <linux/bitfield.h> #include <debug_uart.h> #include <generated/dt.h> @@ -49,92 +48,6 @@ int board_init(void) return 0; } -static u32 platform_id, platform_version; - -char *soc_name_decode(void) -{ - char *name, *platform_name; - - switch (platform_id) { - case VERSAL_NET_SPP: - platform_name = "ipp"; - break; - case VERSAL_NET_EMU: - platform_name = "emu"; - break; - case VERSAL_NET_QEMU: - platform_name = "qemu"; - break; - default: - return NULL; - } - - /* - * --rev. are 6 chars - * max platform name is qemu which is 4 chars - * platform version number are 1+1 - * Plus 1 char for \n - */ - name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); - if (!name) - return NULL; - - sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD, - platform_name, platform_version / 10, - platform_version % 10); - - return name; -} - -bool soc_detection(void) -{ - u32 version, ps_version; - - version = readl(PMC_TAP_VERSION); - platform_id = FIELD_GET(PLATFORM_MASK, version); - ps_version = FIELD_GET(PS_VERSION_MASK, version); - - debug("idcode %x, version %x, usercode %x\n", - readl(PMC_TAP_IDCODE), version, - readl(PMC_TAP_USERCODE)); - - debug("pmc_ver %lx, ps version %x, rtl version %lx\n", - FIELD_GET(PMC_VERSION_MASK, version), - ps_version, - FIELD_GET(RTL_VERSION_MASK, version)); - - platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); - - if (platform_id == VERSAL_NET_SPP || - platform_id == VERSAL_NET_EMU) { - if (ps_version == PS_VERSION_PRODUCTION) { - /* - * ES1 version ends at 1.9 version where there was +9 - * used because of IPP/SPP conversion. Production - * version have platform_version started from 0 again - * that's why adding +20 to continue with the same line. - * It means the last ES1 version ends at 1.9 version and - * new PRODUCTION line starts at 2.0. - */ - platform_version += 20; - } else { - /* - * 9 is diff for - * 0 means 0.9 version - * 1 means 1.0 version - * 2 means 1.1 version - * etc, - */ - platform_version += 9; - } - } - - debug("Platform id: %d version: %d.%d\n", platform_id, - platform_version / 10, platform_version % 10); - - return true; -} - int board_early_init_f(void) { if (IS_ENABLED(CONFIG_DEBUG_UART)) { @@ -148,118 +61,103 @@ int board_early_init_f(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal_net_timer_setup(); return 0; } -static u8 versal_net_get_bootmode(void) +static int spi_get_bootseq(u8 bootmode, const char **modename) { - u8 bootmode; - u32 reg = 0; + struct udevice *dev; + const char *name; + int bootseq; - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { - reg = zynqmp_pm_get_bootmode_reg(); - } else { - reg = readl(&crp_base->boot_mode_usr); + switch (bootmode) { + case QSPI_MODE_24BIT: + if (modename) + *modename = "QSPI_MODE_24\n"; + name = "spi@f1030000"; + break; + case QSPI_MODE_32BIT: + if (modename) + *modename = "QSPI_MODE_32\n"; + name = "spi@f1030000"; + break; + case OSPI_MODE: + if (modename) + *modename = "OSPI_MODE\n"; + name = "spi@f1010000"; + break; + default: + return -1; } - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; + if (uclass_get_device_by_name(UCLASS_SPI, name, &dev)) { + debug("SPI driver for %s is not present\n", name); + return -1; + } - bootmode = reg & BOOT_MODES_MASK; + bootseq = dev_seq(dev); + debug("bootseq %d\n", bootseq); - return bootmode; + return bootseq; } int spi_get_env_dev(void) { + return spi_get_bootseq(versal_net_get_bootmode(), NULL); +} + +static int mmc_get_bootseq(u8 bootmode, const char **modename) +{ struct udevice *dev; - int bootseq = -1; + const char *name; - switch (versal_net_get_bootmode()) { - case QSPI_MODE_24BIT: - puts("QSPI_MODE_24\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - bootseq = dev_seq(dev); + switch (bootmode) { + case SD_MODE: + if (modename) + *modename = "SD_MODE\n"; + name = "mmc@f1040000"; break; - case QSPI_MODE_32BIT: - puts("QSPI_MODE_32\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - bootseq = dev_seq(dev); + case EMMC_MODE: + if (modename) + *modename = "EMMC_MODE\n"; + name = "mmc@f1050000"; break; - case OSPI_MODE: - puts("OSPI_MODE\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1010000", &dev)) { - debug("OSPI driver for OSPI device is not present\n"); - break; - } - bootseq = dev_seq(dev); + case SD_MODE1: + case SD1_LSHFT_MODE: + if (modename) + *modename = "SD_MODE1\n"; + name = "mmc@f1050000"; break; default: - break; + return -1; } - debug("bootseq %d\n", bootseq); - return bootseq; + if (uclass_get_device_by_name(UCLASS_MMC, name, &dev)) { + debug("MMC driver for %s is not present\n", name); + return -1; + } + + return dev_seq(dev); +} + +int mmc_get_env_dev(void) +{ + return mmc_get_bootseq(versal_net_get_bootmode(), NULL); } static int boot_targets_setup(void) { u8 bootmode; - struct udevice *dev; int bootseq = -1; int bootseq_len = 0; int env_targets_len = 0; const char *mode = NULL; + const char *modename = NULL; char *new_targets; char *env_targets; @@ -276,69 +174,28 @@ static int boot_targets_setup(void) mode = "jtag pxe dhcp"; break; case QSPI_MODE_24BIT: - puts("QSPI_MODE_24\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - mode = "xspi"; - bootseq = dev_seq(dev); - break; case QSPI_MODE_32BIT: - puts("QSPI_MODE_32\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - mode = "xspi"; - bootseq = dev_seq(dev); - break; case OSPI_MODE: - puts("OSPI_MODE\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1010000", &dev)) { - debug("OSPI driver for OSPI device is not present\n"); - break; - } - mode = "xspi"; - bootseq = dev_seq(dev); - break; - case EMMC_MODE: - puts("EMMC_MODE\n"); - mode = "mmc"; - bootseq = dev_seq(dev); + bootseq = spi_get_bootseq(bootmode, &modename); + if (modename) + puts(modename); + if (bootseq >= 0) + mode = "xspi"; break; case SELECTMAP_MODE: puts("SELECTMAP_MODE\n"); break; - case SD_MODE: - puts("SD_MODE\n"); - if (uclass_get_device_by_name(UCLASS_MMC, - "mmc@f1040000", &dev)) { - debug("SD0 driver for SD0 device is not present\n"); - break; - } - debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev)); - - mode = "mmc"; - bootseq = dev_seq(dev); - break; case SD1_LSHFT_MODE: puts("LVL_SHFT_"); fallthrough; + case SD_MODE: + case EMMC_MODE: case SD_MODE1: - puts("SD_MODE1\n"); - if (uclass_get_device_by_name(UCLASS_MMC, - "mmc@f1050000", &dev)) { - debug("SD1 driver for SD1 device is not present\n"); - break; - } - debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev)); - - mode = "mmc"; - bootseq = dev_seq(dev); + bootseq = mmc_get_bootseq(bootmode, &modename); + if (modename) + puts(modename); + if (bootseq >= 0) + mode = "mmc"; break; default: printf("Invalid Boot Mode:0x%x\n", bootmode); diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS index a13b6566164..07173ee916f 100644 --- a/board/xilinx/versal/MAINTAINERS +++ b/board/xilinx/versal/MAINTAINERS @@ -1,7 +1,7 @@ XILINX_VERSAL BOARDS M: Michal Simek <[email protected]> S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git F: arch/arm/dts/versal* F: board/xilinx/versal/ F: include/configs/xilinx_versal* diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 9371c30ea27..0537517b1b2 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -10,6 +10,7 @@ #include <env.h> #include <efi_loader.h> #include <fdtdec.h> +#include <fwu.h> #include <init.h> #include <env_internal.h> #include <log.h> @@ -27,7 +28,6 @@ #include <dm/device.h> #include <dm/uclass.h> #include <versalpl.h> -#include <zynqmp_firmware.h> #include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -39,40 +39,15 @@ static xilinx_desc versalpl = { }; #endif -static u8 versal_get_bootmode(void) -{ - u8 bootmode; - u32 reg = 0; - - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { - reg = zynqmp_pm_get_bootmode_reg(); - } else { - reg = readl(&crp_base->boot_mode_usr); - } - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; - - return bootmode; -} - static u32 versal_multi_boot(void) { u8 bootmode = versal_get_bootmode(); - u32 reg = 0; /* Mostly workaround for QEMU CI pipeline */ if (bootmode == JTAG_MODE) return 0; - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) - reg = zynqmp_pm_get_pmc_multi_boot_reg(); - else - reg = readl(PMC_MULTI_BOOT_REG); - - return reg & PMC_MULTI_BOOT_MASK; + return versal_pmc_multi_boot(); } int board_init(void) @@ -93,46 +68,10 @@ int board_init(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal_timer_setup(); return 0; } @@ -293,7 +232,8 @@ int board_late_init(void) { int ret; - if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) + if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && + !IS_ENABLED(CONFIG_FWU_MULTI_BANK_UPDATE)) configure_capsule_updates(); if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { @@ -374,6 +314,8 @@ enum env_location env_get_location(enum env_operation op, int prio) #define DFU_ALT_BUF_LEN SZ_1K +#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && \ + !defined(CONFIG_FWU_MULTI_BANK_UPDATE) static void mtd_found_part(u32 *base, u32 *size) { struct mtd_info *part, *mtd; @@ -450,3 +392,39 @@ void configure_capsule_updates(void) update_info.dfu_string = strdup(buf); debug("Capsule DFU: %s\n", update_info.dfu_string); } +#endif + +#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) + +/* Generate dfu_alt_info from partitions */ +void set_dfu_alt_info(char *interface, char *devstr) +{ + int ret; + struct mtd_info *mtd; + + /* + * It is called multiple times for every image + * per bank that's why enough to set it up once. + */ + if (env_get("dfu_alt_info")) + return; + + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + memset(buf, 0, DFU_ALT_BUF_LEN); + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (IS_ERR_OR_NULL(mtd)) + return; + + ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); + if (ret < 0) { + log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); + return; + } + log_debug("Make dfu_alt_info: '%s'\n", buf); + + env_set("dfu_alt_info", buf); +} +#endif diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS index b5b9e2fe40a..3eb1a451b58 100644 --- a/board/xilinx/zynq/MAINTAINERS +++ b/board/xilinx/zynq/MAINTAINERS @@ -1,7 +1,7 @@ ZYNQ BOARD M: Michal Simek <[email protected]> S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git F: arch/arm/dts/zynq-* F: board/xilinx/zynq/ F: include/configs/zynq*.h diff --git a/board/xilinx/zynq/cmds.c b/board/xilinx/zynq/cmds.c index 05ecb75406b..d8eff203a56 100644 --- a/board/xilinx/zynq/cmds.c +++ b/board/xilinx/zynq/cmds.c @@ -347,10 +347,10 @@ static int zynq_verify_image(u32 src_ptr) * This validation is just for PS DDR. * TODO: Update this for PL DDR check as well. */ - if (part_load_addr < gd->bd->bi_dram[0].start && + if (part_load_addr < gd->dram[0].start && ((part_load_addr + part_data_len) > - (gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size))) { + (gd->dram[0].start + + gd->dram[0].size))) { printf("INVALID_LOAD_ADDRESS_FAIL\n"); return -1; } diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index a4527f8959a..3db240782f4 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -1,7 +1,7 @@ XILINX_ZYNQMP BOARDS M: Michal Simek <[email protected]> S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git F: arch/arm/dts/zynqmp-* F: arch/arm/dts/avnet-ultra96* F: board/xilinx/common/ diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 769e52bcfb5..5d13881f3ec 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -24,7 +24,6 @@ #include <malloc.h> #include <memalign.h> #include <wdt.h> -#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/arch/psu_init_gpl.h> @@ -183,6 +182,23 @@ int board_init(void) zynqmppl.name = strdup(name); fpga_init(); fpga_add(fpga_xilinx, &zynqmppl); + + /* + * zu63dr_SE and zu67dr_SE share ID 0x046D7093. + * Register zu63dr_SE as alternate device. + */ + if (!strcmp(name, "zu67dr_SE")) { + xilinx_desc *alt; + + alt = calloc(1, sizeof(*alt)); + if (!alt) { + log_err("Failed to allocate alt FPGA descriptor\n"); + } else { + *alt = zynqmppl; + alt->name = "zu63dr_SE"; + fpga_add(fpga_xilinx, alt); + } + } } } #endif @@ -197,26 +213,11 @@ int board_init(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - val = readl(&crlapb_base->timestamp_ref_ctrl); - val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + zynqmp_timer_setup(); - if (!val) { - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - /* Program freq register in System counter */ - writel(zynqmp_get_system_timer_freq(), - &iou_scntr_secure->base_frequency_id_register); - /* And enable system counter */ - writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, - &iou_scntr_secure->counter_control_register); - } return 0; } @@ -262,8 +263,8 @@ int dram_init(void) #else int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = get_effective_memsize(); + gd->dram[0].start = CFG_SYS_SDRAM_BASE; + gd->dram[0].size = get_effective_memsize(); mem_map_fill(); @@ -524,10 +525,6 @@ int board_late_init(void) { int ret, multiboot; -#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD) - usb_ether_init(); -#endif - if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)) configure_capsule_updates(); diff --git a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS index be9c93f6b9d..79981aa43f1 100644 --- a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS +++ b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS @@ -3,4 +3,4 @@ M: Niu Zhihong <[email protected]> S: Maintained F: board/xunlong/orangepi-5-rk3588-ultra F: configs/orangepi-5-ultra-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-ultra.dts +F: arch/arm/dts/rk3588-orangepi-5-ultra* diff --git a/board/zyxel/nsa325/nsa325.c b/board/zyxel/nsa325/nsa325.c index 38340b33c8b..894c2ef293c 100644 --- a/board/zyxel/nsa325/nsa325.c +++ b/board/zyxel/nsa325/nsa325.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014-2023 Tony Dinh <[email protected]> + * Copyright (C) 2014-2025 Tony Dinh <[email protected]> * * Based on * Copyright (C) 2014 Jason Plum <[email protected]> @@ -51,11 +51,10 @@ DECLARE_GLOBAL_DATA_PTR; #define HDD1_GREEN_LED BIT(9) #define HDD1_RED_LED BIT(10) #define HDD2_POWER BIT(15) -#define WATCHDOG_SIGNAL BIT(14) #define NSA325_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \ - HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL)) -#define NSA325_VAL_HIGH (WATCHDOG_SIGNAL | HDD2_POWER) + HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER)) +#define NSA325_VAL_HIGH (HDD2_POWER) #define BTN_POWER 46 #define BTN_RESET 36 |