diff options
Diffstat (limited to 'board')
190 files changed, 5403 insertions, 3835 deletions
diff --git a/board/adi/carriers/somcrr_ezkit.c b/board/adi/carriers/somcrr_ezkit.c index 8b4d6a96c18..3cd5a6cd10b 100644 --- a/board/adi/carriers/somcrr_ezkit.c +++ b/board/adi/carriers/somcrr_ezkit.c @@ -13,13 +13,12 @@ void adi_somcrr_enable_ethernet(void) struct gpio_desc *eth1_reset; struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth1-en", ð1); - gpio_hog_lookup_name("eth1-reset", ð1_reset); - gpio_hog_lookup_name("gige-reset", &gige_reset); - - dm_gpio_set_value(eth1, 1); - dm_gpio_set_value(eth1_reset, 0); - dm_gpio_set_value(gige_reset, 0); + if (!gpio_hog_lookup_name("eth1-en", ð1)) + dm_gpio_set_value(eth1, 1); + if (!gpio_hog_lookup_name("eth1-reset", ð1_reset)) + dm_gpio_set_value(eth1_reset, 0); + if (!gpio_hog_lookup_name("gige-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 0); } void adi_somcrr_disable_ethernet(void) @@ -28,11 +27,10 @@ void adi_somcrr_disable_ethernet(void) struct gpio_desc *eth1_reset; struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth1-en", ð1); - gpio_hog_lookup_name("eth1-reset", ð1_reset); - gpio_hog_lookup_name("gige-reset", &gige_reset); - - dm_gpio_set_value(eth1, 0); - dm_gpio_set_value(eth1_reset, 1); - dm_gpio_set_value(gige_reset, 1); + if (!gpio_hog_lookup_name("eth1-en", ð1)) + dm_gpio_set_value(eth1, 0); + if (!gpio_hog_lookup_name("eth1-reset", ð1_reset)) + dm_gpio_set_value(eth1_reset, 1); + if (!gpio_hog_lookup_name("gige-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 1); } diff --git a/board/adi/carriers/somcrr_ezlite.c b/board/adi/carriers/somcrr_ezlite.c index c0655574bab..1f1984cf912 100644 --- a/board/adi/carriers/somcrr_ezlite.c +++ b/board/adi/carriers/somcrr_ezlite.c @@ -11,14 +11,14 @@ void adi_somcrr_enable_ethernet(void) { struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth0-reset", &gige_reset); - dm_gpio_set_value(gige_reset, 0); + if (!gpio_hog_lookup_name("eth0-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 0); } void adi_somcrr_disable_ethernet(void) { struct gpio_desc *gige_reset; - gpio_hog_lookup_name("eth0-reset", &gige_reset); - dm_gpio_set_value(gige_reset, 1); + if (!gpio_hog_lookup_name("eth0-reset", &gige_reset)) + dm_gpio_set_value(gige_reset, 1); } diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index d94c1494d53..81daba1c5ef 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -81,12 +81,13 @@ char *soc_name_decode(void) } /* - * --rev. are 6 chars - * max platform name is qemu which is 4 chars + * --rev.-el are 9 chars + * max platform name is emu-mmd which is 7 chars * platform version number are 1+1 - * Plus 1 char for \n + * el is 1 char + * Plus 1 char for NULL byte */ - name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20); if (!name) return NULL; diff --git a/board/apple/mac/mac.env b/board/apple/mac/mac.env new file mode 100644 index 00000000000..109379c8c67 --- /dev/null +++ b/board/apple/mac/mac.env @@ -0,0 +1,4 @@ +stdin=serial,usbkbd,spikbd +stdout=vidconsole,serial +stderr=vidconsole,serial +boot_targets=nvme usb diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 48aec652c4a..07fbafba433 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -71,13 +71,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 5d7a18379fa..eb5d98ad566 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -139,13 +139,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { #ifdef CONFIG_AT91SAM9G10EK diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 2b0b01798ea..3b272e3ffa1 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -83,13 +83,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* arch number of AT91SAM9263EK-Board */ diff --git a/board/atmel/at91sam9m10g45ek/MAINTAINERS b/board/atmel/at91sam9m10g45ek/MAINTAINERS index 54632c36d6e..4a3dcd402dd 100644 --- a/board/atmel/at91sam9m10g45ek/MAINTAINERS +++ b/board/atmel/at91sam9m10g45ek/MAINTAINERS @@ -1,5 +1,5 @@ AT91SAM9M10G45EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/at91sam9m10g45ek/ F: include/configs/at91sam9m10g45ek.h diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index d94904366ed..d07b5196bc3 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -155,13 +155,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* arch number of AT91SAM9M10G45EK-Board */ diff --git a/board/atmel/at91sam9n12ek/MAINTAINERS b/board/atmel/at91sam9n12ek/MAINTAINERS index 0d33340d87a..86781af2e7e 100644 --- a/board/atmel/at91sam9n12ek/MAINTAINERS +++ b/board/atmel/at91sam9n12ek/MAINTAINERS @@ -1,5 +1,5 @@ AT91SAM9N12EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/at91sam9n12ek/ F: include/configs/at91sam9n12ek.h diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 2cddc2175ac..6105e51c9ec 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -89,13 +89,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 214e917381e..d21dfea50f3 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -81,13 +81,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* arch number of AT91SAM9RLEK-Board */ diff --git a/board/atmel/at91sam9x5ek/MAINTAINERS b/board/atmel/at91sam9x5ek/MAINTAINERS index 51d2237ee6c..33c102bf7b3 100644 --- a/board/atmel/at91sam9x5ek/MAINTAINERS +++ b/board/atmel/at91sam9x5ek/MAINTAINERS @@ -1,5 +1,5 @@ AT91SAM9X5EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/at91sam9x5ek/ F: include/configs/at91sam9x5ek.h diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 3f41fb1c983..0cbb50a0621 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -102,13 +102,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* arch number of AT91SAM9X5EK-Board */ diff --git a/board/atmel/sam9x60_curiosity/MAINTAINERS b/board/atmel/sam9x60_curiosity/MAINTAINERS index 0d9369e0272..519aca696de 100644 --- a/board/atmel/sam9x60_curiosity/MAINTAINERS +++ b/board/atmel/sam9x60_curiosity/MAINTAINERS @@ -1,6 +1,6 @@ SAM9X60 CURIOSITY BOARD M: Durai Manickam KR <[email protected]> -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sam9x60_curiosity/ F: include/configs/sam9x60_curiosity.h diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index 3393478e4c8..43797d625e9 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -51,11 +51,6 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - #define MAC24AA_MAC_OFFSET 0xfa #ifdef CONFIG_MISC_INIT_R diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS index d209249c2ef..5e9edd2265f 100644 --- a/board/atmel/sam9x60ek/MAINTAINERS +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -1,6 +1,6 @@ SAM9X60EK BOARD M: Sandeep Sheriker M <[email protected]> -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sam9x60ek/ F: include/configs/sam9x60ek.h diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 2e5073f02b3..64354e5b5fc 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -49,13 +49,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - #define MAC24AA_MAC_OFFSET 0xfa #ifdef CONFIG_MISC_INIT_R diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c index 4e7c5667e21..364b6a3e24b 100644 --- a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -42,11 +42,6 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* address of boot parameters */ diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS index ba2f31e6c4d..9f24c578f9e 100644 --- a/board/atmel/sama5d27_som1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D27 SOM1 EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d27_som1_ek/ F: include/configs/sama5d27_som1_ek.h diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index bf54fc33df4..858061bf9f9 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -61,13 +61,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* address of boot parameters */ diff --git a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS index ff68cf01a34..ea3b4b27579 100644 --- a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS @@ -1,6 +1,6 @@ SAMA5D27 WLSOM1 EK BOARD M: Nicolas Ferre <[email protected]> -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d27_wlsom1_ek/ F: include/configs/sama5d27_wlsom1_ek.h diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 897fab58eba..19341d325bd 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -55,13 +55,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* address of boot parameters */ diff --git a/board/atmel/sama5d2_icp/MAINTAINERS b/board/atmel/sama5d2_icp/MAINTAINERS index 4a65c65ec3b..d668aa26260 100644 --- a/board/atmel/sama5d2_icp/MAINTAINERS +++ b/board/atmel/sama5d2_icp/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D2 ICP BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d2_icp/ F: include/configs/sama5d2_icp.h diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 113bd2feb62..d159ad6f4ca 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -46,11 +46,6 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* address of boot parameters */ diff --git a/board/atmel/sama5d2_ptc_ek/MAINTAINERS b/board/atmel/sama5d2_ptc_ek/MAINTAINERS index 9f82d9a3d82..95a57b2a996 100644 --- a/board/atmel/sama5d2_ptc_ek/MAINTAINERS +++ b/board/atmel/sama5d2_ptc_ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D2 PTC EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> M: Ludovic Desroches <[email protected]> S: Maintained F: board/atmel/sama5d2_ptc_ek/ diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 438829df82d..29fa88ff411 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -105,13 +105,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* address of boot parameters */ diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS index 88e327f81cd..0c4e74b2dd4 100644 --- a/board/atmel/sama5d2_xplained/MAINTAINERS +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D2 XPLAINED BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d2_xplained/ F: include/configs/sama5d2_xplained.h diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index eca5b2bf107..c0862f58606 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -60,13 +60,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* address of boot parameters */ diff --git a/board/atmel/sama5d3_xplained/MAINTAINERS b/board/atmel/sama5d3_xplained/MAINTAINERS index 69b4ee8a33b..4979545dbc9 100644 --- a/board/atmel/sama5d3_xplained/MAINTAINERS +++ b/board/atmel/sama5d3_xplained/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D3_XPLAINED BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d3_xplained/ F: include/configs/sama5d3_xplained.h diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 7a813c19ff2..e12f2883cec 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -84,13 +84,6 @@ int board_late_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/sama5d3xek/MAINTAINERS b/board/atmel/sama5d3xek/MAINTAINERS index e8ec275d71d..a1c96bfea84 100644 --- a/board/atmel/sama5d3xek/MAINTAINERS +++ b/board/atmel/sama5d3xek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D3XEK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d3xek/ F: include/configs/sama5d3xek.h diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 555a8c0970b..405c9c50321 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -137,13 +137,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/sama5d4_xplained/MAINTAINERS b/board/atmel/sama5d4_xplained/MAINTAINERS index 9fd0ad7bc2b..43fc23ef814 100644 --- a/board/atmel/sama5d4_xplained/MAINTAINERS +++ b/board/atmel/sama5d4_xplained/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D4 XPLAINED ULTRA BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d4_xplained/ F: include/configs/sama5d4_xplained.h diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index e296b0466aa..5894e7a654d 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -99,13 +99,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - #define AT24MAC_MAC_OFFSET 0x9a #ifdef CONFIG_MISC_INIT_R diff --git a/board/atmel/sama5d4ek/MAINTAINERS b/board/atmel/sama5d4ek/MAINTAINERS index f715af6401b..757be21b96a 100644 --- a/board/atmel/sama5d4ek/MAINTAINERS +++ b/board/atmel/sama5d4ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA5D4EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama5d4ek/ F: include/configs/sama5d4ek.h diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index e820605d3b9..7418369c5ba 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -97,13 +97,6 @@ void board_debug_uart_init(void) } #endif -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - return 0; -} -#endif - int board_init(void) { /* adress of boot parameters */ diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c index 713b1b9d959..764c8f035c9 100644 --- a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -49,11 +49,6 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* address of boot parameters */ diff --git a/board/atmel/sama7g5ek/MAINTAINERS b/board/atmel/sama7g5ek/MAINTAINERS index eac972968d7..4d1c6f666c0 100644 --- a/board/atmel/sama7g5ek/MAINTAINERS +++ b/board/atmel/sama7g5ek/MAINTAINERS @@ -1,5 +1,5 @@ SAMA7G5 EK BOARD -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> S: Maintained F: board/atmel/sama7g5ek.c F: include/configs/sama7g5ek.h diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index c07115a2119..5409ed2375d 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -46,11 +46,6 @@ void board_debug_uart_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - #define MAC24AA_MAC_OFFSET 0xfa #if (IS_ENABLED(CONFIG_MISC_INIT_R)) diff --git a/board/beacon/imx8mp/imx8mp_beacon.c b/board/beacon/imx8mp/imx8mp_beacon.c index dd74e7c0f75..541a4b00eba 100644 --- a/board/beacon/imx8mp/imx8mp_beacon.c +++ b/board/beacon/imx8mp/imx8mp_beacon.c @@ -14,7 +14,7 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -#if IS_ENABLED(CONFIG_NET) +#if IS_ENABLED(CONFIG_NET_LEGACY) int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) diff --git a/board/dhelectronics/common/dh_imx.c b/board/dhelectronics/common/dh_imx.c index 3d6487dd0d8..50404a66f9d 100644 --- a/board/dhelectronics/common/dh_imx.c +++ b/board/dhelectronics/common/dh_imx.c @@ -10,13 +10,13 @@ #include <net.h> #include "dh_imx.h" -int dh_imx_get_mac_from_fuse(unsigned char *enetaddr) +int dh_imx_get_mac_from_fuse(unsigned char *enetaddr, int index) { /* * If IIM fuses contain valid MAC address, use it. * The IIM MAC address fuses are NOT programmed by default. */ - imx_get_mac_from_fuse(0, enetaddr); + imx_get_mac_from_fuse(index, enetaddr); if (!is_valid_ethaddr(enetaddr)) return -EINVAL; diff --git a/board/dhelectronics/common/dh_imx.h b/board/dhelectronics/common/dh_imx.h index 284f8637fb8..be2ff5e076c 100644 --- a/board/dhelectronics/common/dh_imx.h +++ b/board/dhelectronics/common/dh_imx.h @@ -7,6 +7,7 @@ * dh_imx_get_mac_from_fuse - Get MAC address from fuse and write it to env * * @enetaddr: buffer where address is to be stored + * @index: index of MAC address in fuse (starts with 0) * Return: 0 if OK, other value on error */ -int dh_imx_get_mac_from_fuse(unsigned char *enetaddr); +int dh_imx_get_mac_from_fuse(unsigned char *enetaddr, int index); diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c index 234824b38c2..c9e8107685a 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6.c +++ b/board/dhelectronics/dh_imx6/dh_imx6.c @@ -94,7 +94,7 @@ int dh_setup_mac_address(struct eeprom_id_page *eip) if (dh_get_mac_is_enabled("ethernet0")) return 0; - if (!dh_imx_get_mac_from_fuse(enetaddr)) + if (!dh_imx_get_mac_from_fuse(enetaddr, 0)) goto out; if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0")) diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 3424be10936..486073392e9 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -47,7 +47,7 @@ static int dh_imx8_setup_ethaddr(struct eeprom_id_page *eip) if (dh_get_mac_is_enabled("ethernet0")) return 0; - if (!dh_imx_get_mac_from_fuse(enetaddr)) + if (!dh_imx_get_mac_from_fuse(enetaddr, 0)) goto out; if (!dh_get_value_from_eeprom_buffer(DH_MAC0, enetaddr, sizeof(enetaddr), eip)) @@ -72,8 +72,8 @@ static int dh_imx8_setup_eth1addr(struct eeprom_id_page *eip) if (dh_get_mac_is_enabled("ethernet1")) return 0; - if (!dh_imx_get_mac_from_fuse(enetaddr)) - goto increment_out; + if (!dh_imx_get_mac_from_fuse(enetaddr, 1)) + goto out; if (!dh_get_value_from_eeprom_buffer(DH_MAC1, enetaddr, sizeof(enetaddr), eip)) goto out; diff --git a/board/edgeble/neural-compute-module-6/MAINTAINERS b/board/edgeble/neural-compute-module-6/MAINTAINERS index 42e5df506bf..97d8c96ae62 100644 --- a/board/edgeble/neural-compute-module-6/MAINTAINERS +++ b/board/edgeble/neural-compute-module-6/MAINTAINERS @@ -5,9 +5,5 @@ F: board/edgeble/neural-compute-module-6 F: include/configs/neural-compute-module-6.h F: configs/neu6a-io-rk3588_defconfig F: configs/neu6b-io-rk3588_defconfig -F: arch/arm/dts/rk3588-edgeble-neu6a.dtsi -F: arch/arm/dts/rk3588-edgeble-neu6a-io.dts -F: arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi -F: arch/arm/dts/rk3588-edgeble-neu6b.dtsi -F: arch/arm/dts/rk3588-edgeble-neu6b-io.dts -F: arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi +F: arch/arm/dts/rk3588-edgeble-neu6a-io* +F: arch/arm/dts/rk3588-edgeble-neu6b-io* diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c index 864afa92aee..547cfa3a35f 100644 --- a/board/engicam/imx8mp/icore_mx8mp.c +++ b/board/engicam/imx8mp/icore_mx8mp.c @@ -30,7 +30,7 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP) +#if CONFIG_IS_ENABLED(NET) int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) diff --git a/board/engicam/stm32mp1/spl.c b/board/engicam/stm32mp1/spl.c index bb2bd446aa8..19e5ab0180f 100644 --- a/board/engicam/stm32mp1/spl.c +++ b/board/engicam/stm32mp1/spl.c @@ -15,9 +15,3 @@ void board_vddcore_init(u32 voltage_mv) if (IS_ENABLED(CONFIG_PMIC_STPMIC1) && CONFIG_IS_ENABLED(POWER)) opp_voltage_mv = voltage_mv; } - -int board_early_init_f(void) -{ - return 0; -} - diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 6a24f618ae2..aeb401b1210 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -47,7 +47,7 @@ int board_fit_config_name_match(const char *path) return -1; } -#if (IS_ENABLED(CONFIG_NET)) +#if (IS_ENABLED(CONFIG_NET_LEGACY)) int board_phy_config(struct phy_device *phydev) { unsigned short val; @@ -71,7 +71,7 @@ int board_phy_config(struct phy_device *phydev) return 0; } -#endif // IS_ENABLED(CONFIG_NET) +#endif // IS_ENABLED(CONFIG_NET_LEGACY) int board_init(void) { diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c index cfba9300dcb..f3aae9256c1 100644 --- a/board/google/imx8mq_phanbell/spl.c +++ b/board/google/imx8mq_phanbell/spl.c @@ -6,134 +6,21 @@ #include <config.h> #include <hang.h> -#include <asm/global_data.h> -#include <asm/io.h> #include <errno.h> #include <init.h> #include <log.h> -#include <asm/io.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <linux/delay.h> -#include <fsl_esdhc_imx.h> -#include <mmc.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(void) { /* ddr init */ ddr_init(&dram_timing); } -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = 1; - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - return ret; - } - - return 1; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR}, - {USDHC2_BASE_ADDR}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - usdhc_cfg[0].max_bus_width = 8; - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - usdhc_cfg[1].max_bus_width = 4; - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - void spl_board_init(void) { puts("Normal Boot\n"); @@ -153,8 +40,8 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -166,12 +53,9 @@ void board_init_f(ulong dummy) preloader_console_init(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } @@ -180,5 +64,8 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/hardkernel/odroid_m1/MAINTAINERS b/board/hardkernel/odroid_m1/MAINTAINERS index 165d2d96741..8686a552d1c 100644 --- a/board/hardkernel/odroid_m1/MAINTAINERS +++ b/board/hardkernel/odroid_m1/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/hardkernel/odroid_m1/ F: include/configs/odroid_m1.h F: configs/odroid-m1-rk3568_defconfig -F: arch/arm/dts/rk3568-odroid-m1.dts -F: arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi +F: arch/arm/dts/rk3568-odroid-m1* diff --git a/board/khadas/khadas-edge2-rk3588s/MAINTAINERS b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS index 3f16923b0f2..c43f469589d 100644 --- a/board/khadas/khadas-edge2-rk3588s/MAINTAINERS +++ b/board/khadas/khadas-edge2-rk3588s/MAINTAINERS @@ -3,4 +3,4 @@ M: Jacobe Zang <[email protected]> S: Maintained F: configs/khadas-edge2-rk3588s_defconfig F: include/configs/khadas-edge2-rk3588s.h -F: dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts
\ No newline at end of file +F: arch/arm/dts/rk3588s-khadas-edge2* diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c index bd5981bf694..0396967fe36 100644 --- a/board/kontron/pitx_imx8m/spl.c +++ b/board/kontron/pitx_imx8m/spl.c @@ -2,22 +2,14 @@ #include <config.h> #include <errno.h> -#include <fsl_esdhc_imx.h> #include <hang.h> #include <init.h> #include <log.h> #include <spl.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <linux/delay.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> @@ -26,8 +18,6 @@ extern struct dram_timing_info dram_timing_2gb; extern struct dram_timing_info dram_timing_4gb; -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(void) { struct dram_timing_info *dram_timing; @@ -53,120 +43,6 @@ static void spl_dram_init(void) ddr_init(dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(MMC) -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - /* the eMMC does not have a CD pin */ - return 1; - case USDHC2_BASE_ADDR: - return !gpio_get_value(USDHC2_CD_GPIO); - } - - return 0; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR, 0, 8}, - {USDHC2_BASE_ADDR, 0, 4}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers " - "(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - const char *spl_board_loader_name(u32 boot_device) { switch (boot_device) { @@ -178,18 +54,14 @@ const char *spl_board_loader_name(u32 boot_device) return NULL; } } -#endif -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 - -static int pfuze_mode_init(struct pmic *p, u32 mode) +static int pfuze_mode_init(struct udevice *dev, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = pmic_reg_read(dev, PFUZE100_DEVICEID); id = id & 0xf; if (id == 0) { @@ -203,14 +75,14 @@ static int pfuze_mode_init(struct pmic *p, u32 mode) return -EINVAL; } - ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -223,46 +95,44 @@ static int pfuze_mode_init(struct pmic *p, u32 mode) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; + int reg; int ret; - unsigned int reg; - - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return -ENODEV; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return -ENODEV; + ret = pmic_get("pmic@8", &dev); + if (ret == -ENODEV) { + puts("No pmic@8\n"); + return 0; + } + if (ret < 0) + return ret; - pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AVOL); if ((reg & 0x3f) != 0x18) { reg &= ~0x3f; reg |= 0x18; - pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + pmic_reg_write(dev, PFUZE100_SW3AVOL, reg); } - ret = pfuze_mode_init(p, APS_PFM); + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; /* set SW3A standby mode to off */ - pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AMODE); reg &= ~0xf; reg |= APS_OFF; - pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + pmic_reg_write(dev, PFUZE100_SW3AMODE, reg); return 0; } -#endif void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -272,26 +142,22 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } - enable_tzc380(); + preloader_console_init(); - setup_i2c(0, 100000, 0x7f, &i2c_pad_info1); + enable_tzc380(); -#if CONFIG_IS_ENABLED(POWER_LEGACY) power_init_board(); -#endif spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS index c342ff24330..37ca35b4dd4 100644 --- a/board/mediatek/MAINTAINERS +++ b/board/mediatek/MAINTAINERS @@ -3,10 +3,14 @@ M: Macpaul Lin <[email protected]> S: Maintained F: arch/arm/dts/mt8371-genio-520-evk-u-boot.dtsi F: arch/arm/dts/mt8371-genio-common-u-boot.dtsi +F: arch/arm/dts/mt8371-genio-common-ufs.dtso F: arch/arm/dts/mt8391-genio-720-evk-u-boot.dtsi +F: configs/mt8189-ufs.config F: configs/mt8189.config F: configs/mt8371_genio_520_evk_defconfig +F: configs/mt8371_genio_520_evk_ufs_defconfig F: configs/mt8391_genio_720_evk_defconfig +F: configs/mt8391_genio_720_evk_ufs_defconfig MT8365 EVK M: Julien Masson <[email protected]> @@ -21,8 +25,10 @@ F: configs/mt8188.config F: configs/mt8370_genio_510_evk_defconfig F: configs/mt8390_genio_700_evk_defconfig -MT8395 +MT8195/MT8395 M: Macpaul Lin <[email protected]> M: Julien Stephan <[email protected]> S: Maintained +F: configs/mt8195.config F: configs/mt8395_genio_1200_evk_defconfig +F: configs/mt8395_genio_1200_evk_ufs_defconfig diff --git a/board/mediatek/mt7622/MAINTAINERS b/board/mediatek/mt7622/MAINTAINERS index a3e0e75ca07..067f33bb39f 100644 --- a/board/mediatek/mt7622/MAINTAINERS +++ b/board/mediatek/mt7622/MAINTAINERS @@ -2,5 +2,4 @@ MT7622 M: Sam Shih <[email protected]> S: Maintained F: board/mediatek/mt7622 -F: include/configs/mt7622.h F: configs/mt7622_rfb_defconfig diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c index 48a783593b6..aca0525c699 100644 --- a/board/mntre/imx8mq_reform2/spl.c +++ b/board/mntre/imx8mq_reform2/spl.c @@ -10,7 +10,6 @@ #include <image.h> #include <init.h> #include <log.h> -#include <asm/global_data.h> #include <asm/io.h> #include <errno.h> #include <asm/io.h> @@ -28,8 +27,6 @@ #include <power/pmic.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - extern struct dram_timing_info dram_timing_ch2; static void spl_dram_init(void) @@ -226,9 +223,6 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - arch_cpu_init(); init_uart_clk(0); diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile index ed102ae7bf7..dafd3717948 100644 --- a/board/nxp/common/Makefile +++ b/board/nxp/common/Makefile @@ -57,7 +57,7 @@ obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o endif -obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o +obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o ifneq (,$(filter $(SOC), imx8m imx8ulp imx9)) obj-y += mmc.o diff --git a/board/nxp/common/i2c_mux.h b/board/nxp/common/i2c_mux.h index 0870c1918e6..ef7ce8e2e51 100644 --- a/board/nxp/common/i2c_mux.h +++ b/board/nxp/common/i2c_mux.h @@ -10,6 +10,11 @@ #ifdef CONFIG_FSL_USE_PCA9547_MUX int select_i2c_ch_pca9547(u8 ch, int bus); +#else +static inline int select_i2c_ch_pca9547(u8 ch, int bus) +{ + return -EOPNOTSUPP; +} #endif #endif diff --git a/board/nxp/common/pfuze.c b/board/nxp/common/pfuze.c index 0d7a94fd232..179cc605da0 100644 --- a/board/nxp/common/pfuze.c +++ b/board/nxp/common/pfuze.c @@ -7,14 +7,14 @@ #include <power/pmic.h> #include <power/pfuze100_pmic.h> -#ifndef CONFIG_DM_PMIC_PFUZE100 -int pfuze_mode_init(struct pmic *p, u32 mode) +#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) +int pfuze_mode_init(struct udevice *dev, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = pmic_reg_read(dev, PFUZE100_DEVICEID); id = id & 0xf; if (id == 0) { @@ -28,14 +28,14 @@ int pfuze_mode_init(struct pmic *p, u32 mode) return -EINVAL; } - ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -46,58 +46,54 @@ int pfuze_mode_init(struct pmic *p, u32 mode) return ret; } -struct pmic *pfuze_common_init(unsigned char i2cbus) +struct udevice *pfuze_common_init(void) { - struct pmic *p; + struct udevice *dev; int ret; - unsigned int reg; - - ret = power_pfuze100_init(i2cbus); - if (ret) - return NULL; + unsigned int reg, dev_id, rev_id; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) return NULL; - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* Set SW1AB stanby volage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ - pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); - return p; + return dev; } -#elif defined(CONFIG_DM_PMIC) -int pfuze_mode_init(struct udevice *dev, u32 mode) +#else +int pfuze_mode_init(struct pmic *p, u32 mode) { unsigned char offset, i, switch_num; u32 id; int ret; - id = pmic_reg_read(dev, PFUZE100_DEVICEID); + pmic_reg_read(p, PFUZE100_DEVICEID, &id); id = id & 0xf; if (id == 0) { @@ -111,14 +107,14 @@ int pfuze_mode_init(struct udevice *dev, u32 mode) return -EINVAL; } - ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); + ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); if (ret < 0) { printf("Set SW1AB mode error!\n"); return ret; } for (i = 0; i < switch_num - 1; i++) { - ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); + ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); if (ret < 0) { printf("Set switch 0x%x mode error!\n", offset + i * SWITCH_SIZE); @@ -129,44 +125,48 @@ int pfuze_mode_init(struct udevice *dev, u32 mode) return ret; } -struct udevice *pfuze_common_init(void) +struct pmic *pfuze_common_init(unsigned char i2cbus) { - struct udevice *dev; + struct pmic *p; int ret; - unsigned int reg, dev_id, rev_id; + unsigned int reg; - ret = pmic_get("pfuze100@8", &dev); - if (ret == -ENODEV) + ret = power_pfuze100_init(i2cbus); + if (ret) return NULL; - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return NULL; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); /* Set SW1AB stanby volage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); /* Set SW1C standby voltage to 0.975V */ - reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); reg &= ~SW1x_STBY_MASK; reg |= SW1x_0_975V; - pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ - reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); reg &= ~SW1xCONF_DVSSPEED_MASK; reg |= SW1xCONF_DVSSPEED_4US; - pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); - return dev; + return p; } #endif diff --git a/board/nxp/common/pfuze.h b/board/nxp/common/pfuze.h index 45b49afaeb7..da89853bd20 100644 --- a/board/nxp/common/pfuze.h +++ b/board/nxp/common/pfuze.h @@ -6,7 +6,7 @@ #ifndef __PFUZE_BOARD_HELPER__ #define __PFUZE_BOARD_HELPER__ -#ifdef CONFIG_DM_PMIC_PFUZE100 +#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) struct udevice *pfuze_common_init(void); int pfuze_mode_init(struct udevice *dev, u32 mode); #else diff --git a/board/nxp/imx8mq_evk/spl.c b/board/nxp/imx8mq_evk/spl.c index 5116d806bb6..80322a2ed19 100644 --- a/board/nxp/imx8mq_evk/spl.c +++ b/board/nxp/imx8mq_evk/spl.c @@ -9,23 +9,16 @@ #include <image.h> #include <init.h> #include <log.h> -#include <asm/io.h> #include <errno.h> #include <asm/io.h> #include <asm/arch/ddr.h> -#include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> -#include <fsl_esdhc_imx.h> -#include <fsl_sec.h> -#include <mmc.h> -#include <linux/delay.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include <dm/uclass.h> +#include <dm/device.h> #include <spl.h> #include "../common/pfuze.h" @@ -40,166 +33,52 @@ static void spl_dram_init(void) ddr_init(&dram_timing_b0); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) -#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) -#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = 1; - break; - case USDHC2_BASE_ADDR: - ret = !gpio_get_value(USDHC2_CD_GPIO); - return ret; - } - - return 1; -} - -#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ - PAD_CTL_FSEL2) -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) - -static iomux_v3_cfg_t const usdhc1_pads[] = { - IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const usdhc2_pads[] = { - IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ - IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ - IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), - IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), -}; - -static struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR, 0, 8}, - {USDHC2_BASE_ADDR, 0, 4}, -}; - -int board_mmc_init(struct bd_info *bis) -{ - int i, ret; - /* - * According to the board_mmc_init() the following map is done: - * (U-Boot device node) (Physical Port) - * mmc0 USDHC1 - * mmc1 USDHC2 - */ - for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, - ARRAY_SIZE(usdhc1_pads)); - gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); - gpio_direction_output(USDHC1_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC1_PWR_GPIO, 1); - break; - case 1: - init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); - imx_iomux_v3_setup_multiple_pads(usdhc2_pads, - ARRAY_SIZE(usdhc2_pads)); - gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); - gpio_direction_output(USDHC2_PWR_GPIO, 0); - udelay(500); - gpio_direction_output(USDHC2_PWR_GPIO, 1); - break; - default: - printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -} - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 int power_init_board(void) { - struct pmic *p; + struct udevice *dev; + int reg; int ret; - unsigned int reg; - - ret = power_pfuze100_init(I2C_PMIC); - if (ret) - return -ENODEV; - p = pmic_get("PFUZE100"); - ret = pmic_probe(p); - if (ret) - return -ENODEV; + ret = pmic_get("pmic@8", &dev); + if (ret == -ENODEV) { + puts("No pmic@8\n"); + return 0; + } + if (ret < 0) + return ret; - pmic_reg_read(p, PFUZE100_DEVICEID, ®); + reg = pmic_reg_read(dev, PFUZE100_DEVICEID); printf("PMIC: PFUZE100 ID=0x%02x\n", reg); - pmic_reg_read(p, PFUZE100_SW3AVOL, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AVOL); if ((reg & 0x3f) != 0x18) { reg &= ~0x3f; reg |= 0x18; - pmic_reg_write(p, PFUZE100_SW3AVOL, reg); + pmic_reg_write(dev, PFUZE100_SW3AVOL, reg); } - ret = pfuze_mode_init(p, APS_PFM); + ret = pfuze_mode_init(dev, APS_PFM); if (ret < 0) return ret; /* set SW3A standby mode to off */ - pmic_reg_read(p, PFUZE100_SW3AMODE, ®); + reg = pmic_reg_read(dev, PFUZE100_SW3AMODE); reg &= ~0xf; reg |= APS_OFF; - pmic_reg_write(p, PFUZE100_SW3AMODE, reg); + pmic_reg_write(dev, PFUZE100_SW3AMODE, reg); return 0; } -#endif void spl_board_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { - if (sec_init()) - printf("\nsec_init failed!\n"); + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); + if (ret) + printf("Failed to initialize caam_jr: %d\n", ret); } puts("Normal Boot\n"); } @@ -218,8 +97,8 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -229,25 +108,22 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } + preloader_console_init(); enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ spl_dram_init(); + init_clk_usdhc(0); + init_clk_usdhc(1); + board_init_r(NULL, 0); } diff --git a/board/nxp/ls1012afrdm/eth.c b/board/nxp/ls1012afrdm/eth.c index c431e5e611b..8761ec7845e 100644 --- a/board/nxp/ls1012afrdm/eth.c +++ b/board/nxp/ls1012afrdm/eth.c @@ -7,16 +7,6 @@ #include <dm.h> #include <net.h> #include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <asm/types.h> -#include <fsl_dtsec.h> -#include <asm/arch/soc.h> -#include <asm/arch-fsl-layerscape/config.h> -#include <asm/arch-fsl-layerscape/immap_lsch2.h> -#include <asm/arch/fsl_serdes.h> #include <linux/delay.h> #include <net/pfe_eth/pfe_eth.h> #include <dm/platform_data/pfe_dm_eth.h> diff --git a/board/nxp/ls1012ardb/eth.c b/board/nxp/ls1012ardb/eth.c index 71cb2988a56..6a6f4608fd1 100644 --- a/board/nxp/ls1012ardb/eth.c +++ b/board/nxp/ls1012ardb/eth.c @@ -6,18 +6,6 @@ #include <config.h> #include <dm.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <asm/types.h> -#include <fsl_dtsec.h> -#include <asm/arch/soc.h> -#include <asm/arch-fsl-layerscape/config.h> -#include <asm/arch-fsl-layerscape/immap_lsch2.h> -#include <asm/arch/fsl_serdes.h> #include <linux/delay.h> #include <net/pfe_eth/pfe_eth.h> #include <dm/platform_data/pfe_dm_eth.h> diff --git a/board/nxp/ls1021atsn/ls1021atsn.c b/board/nxp/ls1021atsn/ls1021atsn.c index c92430c0896..277506fdbb8 100644 --- a/board/nxp/ls1021atsn/ls1021atsn.c +++ b/board/nxp/ls1021atsn/ls1021atsn.c @@ -123,11 +123,6 @@ int dram_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; diff --git a/board/nxp/ls1021atwr/ls1021atwr.c b/board/nxp/ls1021atwr/ls1021atwr.c index 0758e5eae25..135497f7c5d 100644 --- a/board/nxp/ls1021atwr/ls1021atwr.c +++ b/board/nxp/ls1021atwr/ls1021atwr.c @@ -239,11 +239,6 @@ int dram_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) static void convert_serdes_mux(int type, int need_reset) { diff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c index db94d9c1fa8..007125358bd 100644 --- a/board/nxp/ls1028a/ls1028a.c +++ b/board/nxp/ls1028a/ls1028a.c @@ -103,11 +103,6 @@ int board_init(void) return 0; } -int board_eth_init(struct bd_info *bis) -{ - return pci_eth_init(bis); -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/nxp/ls1043aqds/Makefile b/board/nxp/ls1043aqds/Makefile index ff830788fd7..98ad49f6f0c 100644 --- a/board/nxp/ls1043aqds/Makefile +++ b/board/nxp/ls1043aqds/Makefile @@ -5,7 +5,4 @@ # obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif obj-y += ls1043aqds.o diff --git a/board/nxp/ls1043aqds/eth.c b/board/nxp/ls1043aqds/eth.c deleted file mode 100644 index 5a8ca27b327..00000000000 --- a/board/nxp/ls1043aqds/eth.c +++ /dev/null @@ -1,501 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - */ - -#include <config.h> -#include <log.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fdt_support.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <fsl_dtsec.h> -#include <linux/libfdt.h> -#include <malloc.h> -#include <asm/arch/fsl_serdes.h> - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1043aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT3 4 -#define EMI1_SLOT4 5 -#define EMI2 6 - -static const char * const mdio_names[] = { - "LS1043AQDS_MDIO_RGMII1", - "LS1043AQDS_MDIO_RGMII2", - "LS1043AQDS_MDIO_SLOT1", - "LS1043AQDS_MDIO_SLOT2", - "LS1043AQDS_MDIO_SLOT3", - "LS1043AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 2, 3, 4}; -#endif - -static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI2) - return NULL; - - name = ls1043aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1043aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1043aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - ls1043aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1043aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1043aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1043aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1043aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1043aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1043aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1043aqds_mdio_read; - bus->write = ls1043aqds_mdio_write; - bus->reset = ls1043aqds_mdio_reset; - strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - if (port == FM1_DTSEC9) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s1-p1"); - } else if (port == FM1_DTSEC2) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s2-p1"); - } else if (port == FM1_DTSEC5) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s3-p1"); - } else if (port == FM1_DTSEC6) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii-riser-s4-p1"); - } - } else if (fm_info_get_enet_if(port) == - PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (mdio_mux[port]) { - case EMI1_SLOT1: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s1-p4"); - break; - default: - break; - } - break; - case EMI1_SLOT2: - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, - "qsgmii-s2-p4"); - break; - default: - break; - } - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - port == FM1_10GEC1) { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1-slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_XGMII: - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x2555: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - break; - case 0x4555: - case 0x4558: - /* QSGMII on lane A, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S1); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S1); - break; - case 0x1355: - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x2355: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* SGMII on lane B, MAC 2*/ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x3335: - /* SGMII on lane C, MAC 5 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3355: - case 0x3358: - /* SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - case 0x3555: - case 0x3558: - /* SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x1455: - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2455: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC2, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x2255: - /* 2.5G SGMII on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, 9); - /* 2.5G SGMII on lane B, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, 2); - break; - case 0x3333: - /* SGMII on lane A/B/C/D, MAC 9/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC9, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, - SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, - SGMII_CARD_PORT1_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_2500BASEX: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else if (interface == PHY_INTERFACE_MODE_2500BASEX) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_2500_FM1_DTSEC1 + idx); - } else { - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - } - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1043aqds/ls1043aqds.c b/board/nxp/ls1043aqds/ls1043aqds.c index f043599fbb8..0f115c16232 100644 --- a/board/nxp/ls1043aqds/ls1043aqds.c +++ b/board/nxp/ls1043aqds/ls1043aqds.c @@ -550,10 +550,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - fdt_fixup_icid(blob); reg = QIXIS_READ(brdcfg[0]); diff --git a/board/nxp/ls1043ardb/Makefile b/board/nxp/ls1043ardb/Makefile index 95745bf3a9c..13e0411c1ba 100644 --- a/board/nxp/ls1043ardb/Makefile +++ b/board/nxp/ls1043ardb/Makefile @@ -5,6 +5,5 @@ obj-y += ddr.o obj-y += ls1043ardb.o ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_NET) += eth.o obj-y += cpld.o endif diff --git a/board/nxp/ls1043ardb/eth.c b/board/nxp/ls1043ardb/eth.c deleted file mode 100644 index cacc49c0584..00000000000 --- a/board/nxp/ls1043ardb/eth.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ -#include <config.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* QSGMII on lane B, MAC 1/2/5/6 */ - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x1455: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/ls1046afrwy/Makefile b/board/nxp/ls1046afrwy/Makefile index c70f5cda797..8594658d2fb 100644 --- a/board/nxp/ls1046afrwy/Makefile +++ b/board/nxp/ls1046afrwy/Makefile @@ -4,4 +4,4 @@ obj-y += ddr.o obj-y += ls1046afrwy.o -obj-$(CONFIG_NET) += eth.o +obj-$(CONFIG_NET_LEGACY) += eth.o diff --git a/board/nxp/ls1046afrwy/eth.c b/board/nxp/ls1046afrwy/eth.c index 8efc7f68424..d76841c6ab4 100644 --- a/board/nxp/ls1046afrwy/eth.c +++ b/board/nxp/ls1046afrwy/eth.c @@ -4,64 +4,7 @@ */ #include <config.h> #include <fdt_support.h> -#include <net.h> #include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info dtsec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR); - - switch (srds_s1) { - case 0x3040: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(FM1_DTSEC6, dev); - fm_info_set_mdio(FM1_DTSEC5, dev); - fm_info_set_mdio(FM1_DTSEC10, dev); - fm_info_set_mdio(FM1_DTSEC1, dev); - - fm_disable_port(FM1_DTSEC9); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} #ifdef CONFIG_FMAN_ENET int fdt_update_ethernet_dt(void *blob) diff --git a/board/nxp/ls1046aqds/Makefile b/board/nxp/ls1046aqds/Makefile index 365247d92bc..8292726b0e4 100644 --- a/board/nxp/ls1046aqds/Makefile +++ b/board/nxp/ls1046aqds/Makefile @@ -5,7 +5,4 @@ # obj-y += ddr.o -ifndef CONFIG_XPL_BUILD -obj-y += eth.o -endif obj-y += ls1046aqds.o diff --git a/board/nxp/ls1046aqds/eth.c b/board/nxp/ls1046aqds/eth.c deleted file mode 100644 index cd3500c2e96..00000000000 --- a/board/nxp/ls1046aqds/eth.c +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2018-2020 NXP - */ - -#include <config.h> -#include <log.h> -#include <net.h> -#include <asm/io.h> -#include <netdev.h> -#include <fdt_support.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <fsl_dtsec.h> -#include <malloc.h> -#include <asm/arch/fsl_serdes.h> - -#include "../common/qixis.h" -#include "../common/fman.h" -#include "ls1046aqds_qixis.h" - -#define EMI_NONE 0xFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT4 4 - -static const char * const mdio_names[] = { - "LS1046AQDS_MDIO_RGMII1", - "LS1046AQDS_MDIO_RGMII2", - "LS1046AQDS_MDIO_SLOT1", - "LS1046AQDS_MDIO_SLOT2", - "LS1046AQDS_MDIO_SLOT4", - "NULL", -}; - -/* Map SerDes 1 & 2 lanes to default slot. */ -#ifdef CONFIG_FMAN_ENET -static int mdio_mux[NUM_FM_PORTS]; - -static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; -#endif - -static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI1_SLOT4) - return NULL; - - name = ls1046aqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -#ifdef CONFIG_FMAN_ENET -struct ls1046aqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void ls1046aqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - ls1046aqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, - regnum, value); -} - -static int ls1046aqds_mdio_reset(struct mii_dev *bus) -{ - struct ls1046aqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int ls1046aqds_mdio_init(char *realbusname, u8 muxval) -{ - struct ls1046aqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate ls1046aqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate ls1046aqds private data\n"); - free(bus); - return -1; - } - - bus->read = ls1046aqds_mdio_read; - bus->write = ls1046aqds_mdio_write; - bus->reset = ls1046aqds_mdio_reset; - sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - const char *phyconn; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - switch (port) { - case FM1_DTSEC9: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1"); - break; - default: - break; - } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) { - /* 2.5G SGMII interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(1000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 2.5G SGMII on QDS */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4"); - break; - case FM1_DTSEC5: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2"); - break; - case FM1_DTSEC6: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1"); - break; - case FM1_DTSEC10: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3"); - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && - (port == FM1_10GEC1 || port == FM1_10GEC2)) { - phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", port); - } else { - /* 10GBase-R interface */ - f_link.phy_id = cpu_to_fdt32(port); - f_link.duplex = cpu_to_fdt32(1); - f_link.link_speed = cpu_to_fdt32(10000); - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for 10GBase-R */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, - sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "xgmii"); - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1-slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1-slot2"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1-slot4"); - break; - default: - break; - } - break; - default: - break; - } - } -} - -int board_eth_init(struct bd_info *bis) -{ - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - u32 srds_s1, srds_s2; - u8 brdcfg12; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - srds_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; - srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x3333: - /* SGMII on slot 1, MAC 9 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - case 0x1333: - case 0x2333: - /* SGMII on slot 1, MAC 10 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1133: - case 0x2233: - /* SGMII on slot 1, MAC 5/6 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x1040: - case 0x2040: - /* QSGMII on lane B, MAC 6/5/10/1 */ - fm_info_set_phy_address(FM1_DTSEC6, - QSGMII_CARD_PORT1_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC5, - QSGMII_CARD_PORT2_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC10, - QSGMII_CARD_PORT3_PHY_ADDR_S2); - fm_info_set_phy_address(FM1_DTSEC1, - QSGMII_CARD_PORT4_PHY_ADDR_S2); - break; - case 0x3363: - /* SGMII on slot 1, MAC 9/10 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - case 0x1163: - case 0x2263: - case 0x2223: - /* SGMII on slot 1, MAC 6 */ - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", - srds_s1); - break; - } - - if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) - /* SGMII on slot 4, MAC 2 */ - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - if (i == FM1_DTSEC5) { - /* route lane 2 to slot1 so to have - * one sgmii riser card supports - * MAC5 and MAC6. - */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], - brdcfg12 | 0x80); - } - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else { - /* clear the bit 7 to route lane B on slot2. */ - brdcfg12 = QIXIS_READ(brdcfg[12]); - QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); - - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - lane_to_slot[lane] = 2; - } - - if (i == FM1_DTSEC2) - lane = 5; - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); - - return pci_eth_init(bis); -} -#endif /* CONFIG_FMAN_ENET */ diff --git a/board/nxp/ls1046aqds/ls1046aqds.c b/board/nxp/ls1046aqds/ls1046aqds.c index 7df12550868..679b0b2235f 100644 --- a/board/nxp/ls1046aqds/ls1046aqds.c +++ b/board/nxp/ls1046aqds/ls1046aqds.c @@ -434,10 +434,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory_banks(blob, base, size, 2); ft_cpu_setup(blob, bd); -#ifdef CONFIG_FMAN_ENET - fdt_fixup_board_enet(blob); -#endif - fdt_fixup_icid(blob); reg = QIXIS_READ(brdcfg[0]); diff --git a/board/nxp/ls1046ardb/Makefile b/board/nxp/ls1046ardb/Makefile index 9e5d24f53c8..355ccf59257 100644 --- a/board/nxp/ls1046ardb/Makefile +++ b/board/nxp/ls1046ardb/Makefile @@ -5,6 +5,6 @@ obj-y += ddr.o obj-y += ls1046ardb.o ifndef CONFIG_XPL_BUILD -obj-$(CONFIG_NET) += eth.o +obj-$(CONFIG_NET_LEGACY) += eth.o obj-y += cpld.o endif diff --git a/board/nxp/ls1046ardb/eth.c b/board/nxp/ls1046ardb/eth.c index fee8e0e21d4..ce9b7b81e3d 100644 --- a/board/nxp/ls1046ardb/eth.c +++ b/board/nxp/ls1046ardb/eth.c @@ -4,78 +4,7 @@ */ #include <config.h> #include <fdt_support.h> -#include <net.h> #include <asm/io.h> -#include <netdev.h> -#include <fm_eth.h> -#include <fsl_dtsec.h> -#include <fsl_mdio.h> -#include <malloc.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - int i; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - u32 srds_s1; - struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; - srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - - /* Set the two on-board SGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); - - /* Set the on-board AQ PHY address */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - - switch (srds_s1) { - case 0x1133: - break; - default: - printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", - srds_s1); - break; - } - - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) - fm_info_set_mdio(i, dev); - - /* 10GBase-R on lane A, MAC 9 */ - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(FM1_10GEC1, dev); - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} #ifdef CONFIG_FMAN_ENET int fdt_update_ethernet_dt(void *blob) diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c index 51ec055be63..5783dd8a403 100644 --- a/board/nxp/ls1088a/ls1088a.c +++ b/board/nxp/ls1088a/ls1088a.c @@ -974,7 +974,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/ls2080ardb/eth_ls2080rdb.c b/board/nxp/ls2080ardb/eth_ls2080rdb.c index 7d5beb32417..6a8859fd0c5 100644 --- a/board/nxp/ls2080ardb/eth_ls2080rdb.c +++ b/board/nxp/ls2080ardb/eth_ls2080rdb.c @@ -9,25 +9,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ - -#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD) - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/ls2080ardb/ls2080ardb.c b/board/nxp/ls2080ardb/ls2080ardb.c index 6f824f57c47..d08598d1c62 100644 --- a/board/nxp/ls2080ardb/ls2080ardb.c +++ b/board/nxp/ls2080ardb/ls2080ardb.c @@ -503,7 +503,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/lx2160a/eth_lx2160aqds.c b/board/nxp/lx2160a/eth_lx2160aqds.c index 9939bb6f89e..4c16f565b69 100644 --- a/board/nxp/lx2160a/eth_lx2160aqds.c +++ b/board/nxp/lx2160a/eth_lx2160aqds.c @@ -11,24 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/eth_lx2160ardb.c b/board/nxp/lx2160a/eth_lx2160ardb.c index 90e7c9100e1..31bbac6310e 100644 --- a/board/nxp/lx2160a/eth_lx2160ardb.c +++ b/board/nxp/lx2160a/eth_lx2160ardb.c @@ -11,23 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - return pci_eth_init(bis); -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/eth_lx2162aqds.c b/board/nxp/lx2160a/eth_lx2162aqds.c index 805aa705be9..81b81d47978 100644 --- a/board/nxp/lx2160a/eth_lx2162aqds.c +++ b/board/nxp/lx2160a/eth_lx2162aqds.c @@ -11,24 +11,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_PHY_AQUANTIA - /* - * Export functions to be used by AQ firmware - * upload application - */ - gd->jt->strcpy = strcpy; - gd->jt->mdelay = mdelay; - gd->jt->mdio_get_current_dev = mdio_get_current_dev; - gd->jt->phy_find_by_mask = phy_find_by_mask; - gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; - gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; -#endif - - return 0; -} - #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) { diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c index 341f82ce724..b7a6ccf46aa 100644 --- a/board/nxp/lx2160a/lx2160a.c +++ b/board/nxp/lx2160a/lx2160a.c @@ -242,13 +242,17 @@ int init_func_vid(void) return 0; } -#endif EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid); +#endif int checkboard(void) { - enum boot_src src = get_boot_src(); char buf[64]; + + cpu_name(buf); + +#if IS_ENABLED(CONFIG_FSL_QIXIS) + enum boot_src src = get_boot_src(); u8 sw; #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) int clock; @@ -258,7 +262,6 @@ int checkboard(void) "100 separate SSCG"}; #endif - cpu_name(buf); #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) printf("Board: %s-QDS, ", buf); #else @@ -325,7 +328,10 @@ int checkboard(void) clock = sw >> 4; printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); #endif -#endif +#endif /* LX2160ARDB-inside-QIXIS switch */ +#else /* !CONFIG_FSL_QIXIS */ + printf("Board: %s\n", buf); +#endif /* CONFIG_FSL_QIXIS */ return 0; } @@ -554,7 +560,7 @@ int board_init(void) out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); #endif -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) +#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) pci_init(); #endif return 0; @@ -788,7 +794,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); +#if IS_ENABLED(CONFIG_FSL_MC_ENET) fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); +#endif if (mc_memory_base != 0) mc_memory_bank++; @@ -818,7 +826,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; diff --git a/board/nxp/m5253demo/m5253demo.c b/board/nxp/m5253demo/m5253demo.c index 50c5320b55c..7d4b60b283e 100644 --- a/board/nxp/m5253demo/m5253demo.c +++ b/board/nxp/m5253demo/m5253demo.c @@ -133,10 +133,3 @@ void ide_set_reset(int idereset) } } #endif /* CONFIG_IDE */ - -#ifdef CONFIG_DRIVER_DM9000 -int board_eth_init(struct bd_info *bis) -{ - return dm9000_initialize(bis); -} -#endif diff --git a/board/nxp/m53017evb/README b/board/nxp/m53017evb/README index 25831629266..c6dc020af37 100644 --- a/board/nxp/m53017evb/README +++ b/board/nxp/m53017evb/README @@ -90,10 +90,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset CFG_SYS_MBAR -- define MBAR offset diff --git a/board/nxp/m5373evb/README b/board/nxp/m5373evb/README index c7130b32251..7217886fdfa 100644 --- a/board/nxp/m5373evb/README +++ b/board/nxp/m5373evb/README @@ -89,10 +89,6 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver -CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged -CONFIG_SYS_I2C_SPEED -- define for I2C speed -CONFIG_SYS_I2C_SLAVE -- define for I2C slave address -CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset CFG_SYS_MBAR -- define MBAR offset diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.c b/board/nxp/mx6sabreauto/mx6sabreauto.c index 8ca57e0b2ac..aef8bc0ad90 100644 --- a/board/nxp/mx6sabreauto/mx6sabreauto.c +++ b/board/nxp/mx6sabreauto/mx6sabreauto.c @@ -465,6 +465,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) } #endif +#ifndef CONFIG_XPL_BUILD int power_init_board(void) { struct udevice *dev; @@ -488,6 +489,7 @@ int power_init_board(void) return pfuze_mode_init(dev, APS_PFM); } +#endif #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { diff --git a/board/nxp/mx6sabresd/mx6sabresd.c b/board/nxp/mx6sabresd/mx6sabresd.c index dff3a9c33bf..9404535104c 100644 --- a/board/nxp/mx6sabresd/mx6sabresd.c +++ b/board/nxp/mx6sabresd/mx6sabresd.c @@ -437,6 +437,7 @@ int board_init(void) return 0; } +#ifndef CONFIG_XPL_BUILD int power_init_board(void) { struct udevice *dev; @@ -468,6 +469,7 @@ int power_init_board(void) return 0; } +#endif #ifdef CONFIG_MXC_SPI int board_spi_cs_gpio(unsigned bus, unsigned cs) diff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c index ac91da3f4f6..036deb464b5 100644 --- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c @@ -33,16 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ PAD_CTL_SRE_FAST) @@ -55,48 +45,6 @@ int dram_init(void) return 0; } -static iomux_v3_cfg_t const fec2_pads[] = { - MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - - return enable_fec_anatop_clock(1, ENET_125MHZ); -} - -int board_eth_init(struct bd_info *bis) -{ - int ret; - - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); - setup_fec(); - - ret = fecmxc_initialize_multi(bis, 1, - CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC%d MXC: %s:failed\n", 1, __func__); - - return ret; -} - int board_phy_config(struct phy_device *phydev) { /* diff --git a/board/nxp/mx6sxsabresd/mx6sxsabresd.c b/board/nxp/mx6sxsabresd/mx6sxsabresd.c index e3353feec68..cab0892affc 100644 --- a/board/nxp/mx6sxsabresd/mx6sxsabresd.c +++ b/board/nxp/mx6sxsabresd/mx6sxsabresd.c @@ -40,16 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) - -#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) - -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) @@ -71,84 +61,16 @@ static iomux_v3_cfg_t const uart1_pads[] = { static iomux_v3_cfg_t const wdog_b_pad = { MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; static iomux_v3_cfg_t const peri_3v3_pads[] = { MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static iomux_v3_cfg_t const phy_control_pads[] = { - /* 25MHz Ethernet PHY Clock */ - MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), - - /* ENET PHY Power */ - MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL), - - /* AR8031 PHY Reset */ - MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static int setup_fec(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int reg, ret; - - /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); - - ret = enable_fec_anatop_clock(0, ENET_125MHZ); - if (ret) - return ret; - - imx_iomux_v3_setup_multiple_pads(phy_control_pads, - ARRAY_SIZE(phy_control_pads)); - - /* Enable the ENET power, active low */ - gpio_request(IMX_GPIO_NR(2, 6), "enet_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); - - /* Reset AR8031 PHY */ - gpio_request(IMX_GPIO_NR(2, 7), "phy_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); - mdelay(10); - gpio_set_value(IMX_GPIO_NR(2, 7), 1); - - reg = readl(&anatop->pll_enet); - reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; - writel(reg, &anatop->pll_enet); - - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - setup_fec(); - - return cpu_eth_init(bis); -} - int power_init_board(void) { struct udevice *dev; diff --git a/board/nxp/p2041rdb/Makefile b/board/nxp/p2041rdb/Makefile index ebd0982b5db..5512458832d 100644 --- a/board/nxp/p2041rdb/Makefile +++ b/board/nxp/p2041rdb/Makefile @@ -7,4 +7,3 @@ obj-y += p2041rdb.o obj-y += cpld.o obj-y += ddr.o -obj-y += eth.o diff --git a/board/nxp/p2041rdb/README b/board/nxp/p2041rdb/README deleted file mode 100644 index ae770277372..00000000000 --- a/board/nxp/p2041rdb/README +++ /dev/null @@ -1,138 +0,0 @@ -Overview -========= -The P2041 Processor combines four Power Architecture processor cores -with high-performance datapath acceleration architecture(DPAA), CoreNet -fabric infrastructure, as well as network and peripheral bus interfaces -required for networking, telecom/datacom, wireless infrastructure, and -military/aerospace applications. - -P2041RDB board is a quad core platform supporting the P2041 processor -of QorIQ DPAA series. - -Boot from NOR flash -=================== -1. Build image - make P2041RDB_config - make all - -2. Program image - => tftp 1000000 u-boot.bin - => protect off all - => erase eff40000 efffffff - => cp.b 1000000 eff40000 c0000 - -3. Program RCW - => tftp 1000000 rcw.bin - => protect off all - => erase e8000000 e801ffff - => cp.b 1000000 e8000000 50 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => protect off all - => erase eff00000 eff3ffff - => cp.b 1000000 eff00000 2000 - -5. Change DIP-switch - SW1[1-5] = 10110 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SDCard -=================== -1. Build image - make P2041RDB_SDCARD_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SDCard which contains RCW and U-Boot image. - -3. Program the PBL image to SDCard - => tftp 1000000 pbl_sd.bin - => mmcinfo - => mmc write 1000000 8 672 - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => mmc write 1000000 690 10 - -5. Change DIP-switch - SW1[1-5] = 01100 - Note: 1 stands for 'on', 0 stands for 'off' - -Boot from SPI flash -=================== -1. Build image - make P2041RDB_SPIFLASH_config - make all - -2. Generate PBL imge - Use PE tool to produce a image used to be programed to - SPI flash which contains RCW and U-Boot image. - -3. Program the PBL image to SPI flash - => tftp 1000000 pbl_spi.bin - => spi probe 0 - => sf erase 0 100000 - => sf write 1000000 0 $filesize - -4. Program FMAN Firmware ucode - => tftp 1000000 ucode.bin - => sf erase 110000 10000 - => sf write 1000000 110000 $filesize - -5. Change DIP-switch - SW1[1-5] = 10100 - Note: 1 stands for 'on', 0 stands for 'off' - -Device tree support and how to enable it for different configs --------------------------------------------------------------- -Device tree support is available for p2041rdb for below mentioned boot, -1. NOR Boot -2. NAND Boot -3. SD Boot -4. SPIFLASH Boot - -To enable device tree support for other boot, below configs need to be -enabled in relative defconfig file, -1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) -2. CONFIG_OF_CONTROL -3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CFG_RESET_VECTOR_ADDRESS - 0xffc - -CPLD command -============ -The CPLD is used to control the power sequence and some serdes lane -mux function. - -cpld reset - hard reset to default bank -cpld reset altbank - reset to alternate bank -cpld lane_mux <lane> <mux_value> - set multiplexed lane pin - lane 6: 0 -> slot1 (Default) - 1 -> SGMII - lane a: 0 -> slot2 (Default) - 1 -> AURORA - lane c: 0 -> slot2 (Default) - 1 -> SATA0 - lane d: 0 -> slot2 (Default) - 1 -> SATA1 - -Using the Device Tree Source File -================================= -To create the DTB (Device Tree Binary) image file, use a command -similar to this: - dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb - -Or use the following command: - {linux-2.6}/make p2041rdb.dtb ARCH=powerpc - -then the dtb file will be generated under the following directory: - {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb - -Booting Linux -============= -Place a linux uImage in the TFTP disk area. - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp 3000000 p2041rdb.dtb - bootm 1000000 2000000 3000000 diff --git a/board/nxp/p2041rdb/README.rst b/board/nxp/p2041rdb/README.rst new file mode 100644 index 00000000000..8b8214adc57 --- /dev/null +++ b/board/nxp/p2041rdb/README.rst @@ -0,0 +1,147 @@ +.. SPDX-License-Identifier: GPL-2.0 + +P2041-RDB Board Overview +======================== + +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== + +1. Build image:: + + make P2041RDB_config + make all + +2. Program image:: + + => tftp 1000000 u-boot.bin + => protect off all + => erase eff40000 efffffff + => cp.b 1000000 eff40000 c0000 + +3. Program RCW:: + + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => protect off all + => erase eff00000 eff3ffff + => cp.b 1000000 eff00000 2000 + +5. Change DIP-switch to SW1[1-5] = 10110. Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +================ + +1. Build image:: + + make P2041RDB_SDCARD_config + make all + +2. Program the PBL image to SDCard:: + + => tftp 1000000 u-boot.pbl + => mmc info + => mmc write 1000000 8 672 + +3. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => mmc write 1000000 690 10 + +4. Change DIP-switch to SW1[1-5] = 01100. Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== + +1. Build image:: + + make P2041RDB_SPIFLASH_config + make all + +2. Program the PBL image to SPI flash:: + + => tftp 1000000 u-boot.pbl + => sf probe 0 + => sf update $fileaddr 0 $filesize + +3. Program FMAN Firmware ucode:: + + => tftp 1000000 ucode.bin + => sf update $fileaddr 110000 $filesize + +4. Change DIP-switch SW1[1-5] = 10100. Note: 1 stands for 'on', 0 stands for 'off' + +Device tree support and how to enable it for different configs +-------------------------------------------------------------- + +Device tree support is available for p2041rdb for below mentioned boot, + +1. NOR Boot +2. NAND Boot +3. SD Boot +4. SPIFLASH Boot + +To enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, + +1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) +2. CONFIG_OF_CONTROL +3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at + CFG_RESET_VECTOR_ADDRESS - 0xffc + +CPLD command +============ + +The CPLD is used to control the power sequence and some serdes lane +mux function:: + + cpld reset - hard reset to default bank + cpld reset altbank - reset to alternate bank + cpld lane_mux <lane> <mux_value> - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this:: + + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command:: + + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory:: + + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= + +Place a linux uImage in the TFTP disk area:: + + => tftp 1000000 uImage + => tftp 2000000 rootfs.ext2.gz.uboot + => tftp 3000000 p2041rdb.dtb + => bootm 1000000 2000000 3000000 diff --git a/board/nxp/p2041rdb/eth.c b/board/nxp/p2041rdb/eth.c deleted file mode 100644 index 65850866777..00000000000 --- a/board/nxp/p2041rdb/eth.c +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * Author: Mingkai Hu <[email protected]> - */ - -/* - * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs - * are provided by the three on-board PHY or by the standard Freescale - * four-port SGMII riser card. We need to change the phy-handle in the - * kernel dts file to point to the correct PHY according to serdes mux - * and serdes protocol selection. - */ - -#include <config.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fsl_dtsec.h> - -#include "cpld.h" -#include "../common/fman.h" - -#ifdef CONFIG_FMAN_ENET -/* - * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0 -}; - -static int riser_phy_addr[] = { - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, - CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, -}; - -/* - * Initialize the lane_to_slot[] array. - * - * On the P2040RDB board the mapping is controlled by CPLD register. - */ -static void initialize_lane_to_slot(void) -{ - u8 mux = CPLD_READ(serdes_mux); - - lane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1; - lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; - lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; - lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - phy_interface_t intf = fm_info_get_enet_if(port); - char phy[16]; - int lane; - u8 slot; - - switch (intf) { - /* The RGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1); - fdt_set_phy_handle(fdt, compat, addr, phy); - break; - /* The SGMII PHY is identified by the MAC connected to it */ - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); - if (lane < 0) - return; - slot = lane_to_slot[lane]; - if (slot) { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } else { - sprintf(phy, "phy_sgmii_%x", - CFG_SYS_FM1_DTSEC1_PHY_ADDR - + (port - FM1_DTSEC1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - case PHY_INTERFACE_MODE_XGMII: - /* XAUI */ - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - /* The XAUI PHY is identified by the slot */ - sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - break; - default: - break; - } -} -#endif /* #ifdef CONFIG_FMAN_ENET */ - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct fsl_pq_mdio_info dtsec_mdio_info; - struct tgec_mdio_info tgec_mdio_info; - unsigned int i, slot; - int lane; - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_tgec_mdio_init(bis, &tgec_mdio_info); - - /* - * Program the three on-board SGMII PHY addresses. If the SGMII Riser - * card used, we'll override the PHY address later. For any DTSEC that - * is RGMII, we'll also override its PHY address later. We assume that - * DTSEC4 and DTSEC5 are used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(i, riser_phy_addr[i]); - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ - fm_info_set_phy_address(i, i == FM1_DTSEC5 ? - CFG_SYS_FM1_DTSEC5_PHY_ADDR : - CFG_SYS_FM1_DTSEC4_PHY_ADDR); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - break; - } - - fm_info_set_mdio(i, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - } - - lane = serdes_get_first_lane(XAUI_FM1); - if (lane >= 0) { - slot = lane_to_slot[lane]; - if (slot) - fm_info_set_phy_address(FM1_10GEC1, - CFG_SYS_FM1_10GEC1_PHY_ADDR); - } - - fm_info_set_mdio(FM1_10GEC1, - miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg new file mode 100644 index 00000000000..f22f3335e73 --- /dev/null +++ b/board/nxp/p2041rdb/p2041rdb_rcw_sd.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P2041RDB. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +12600000 00000000 241C0000 00000000 +649FA0C1 C3C02000 68000000 40000000 +00000000 00000000 00000000 D0030F07 +00000000 00000000 00000000 00000000 diff --git a/board/nxp/p2041rdb/rcw_p2041rdb.cfg b/board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg index 8df19dd3fe4..8df19dd3fe4 100644 --- a/board/nxp/p2041rdb/rcw_p2041rdb.cfg +++ b/board/nxp/p2041rdb/p2041rdb_rcw_spi.cfg diff --git a/board/nxp/t102xrdb/Makefile b/board/nxp/t102xrdb/Makefile index b0f27c47191..2a360227418 100644 --- a/board/nxp/t102xrdb/Makefile +++ b/board/nxp/t102xrdb/Makefile @@ -9,7 +9,6 @@ obj-y += spl.o else obj-y += t102xrdb.o obj-$(CONFIG_TARGET_T1024RDB) += cpld.o -obj-y += eth_t102xrdb.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/nxp/t102xrdb/eth_t102xrdb.c b/board/nxp/t102xrdb/eth_t102xrdb.c deleted file mode 100644 index 7185a0abd52..00000000000 --- a/board/nxp/t102xrdb/eth_t102xrdb.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Shengzhou Liu <[email protected]> - */ - -#include <config.h> -#include <command.h> -#include <fdt_support.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fsl_dtsec.h> -#include <asm/fsl_serdes.h> -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Set the on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); - - switch (srds_s1) { -#ifdef CONFIG_TARGET_T1024RDB - case 0x95: - /* set the on-board RGMII2 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); - - /* set 10GBase-R with Aquantia AQR105 PHY */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - break; -#endif - case 0x6a: - case 0x6b: - case 0x77: - case 0x135: - /* set the on-board 2.5G SGMII AQR105 PHY */ - fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); -#ifdef CONFIG_TARGET_T1023RDB - /* set the on-board 1G SGMII RTL8211F PHY */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); -#endif - break; - default: - printf("SerDes protocol 0x%x is not supported on T102xRDB\n", - srds_s1); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_SGMII: -#if defined(CONFIG_TARGET_T1023RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); -#elif defined(CONFIG_TARGET_T1024RDB) - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); -#endif - fm_info_set_mdio(i, dev); - break; - case PHY_INTERFACE_MODE_2500BASEX: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ -#if defined(CONFIG_TARGET_T1024RDB) - if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_2500BASEX) || - (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) && - (port == FM1_DTSEC3)) { - fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "2500base-x"); - fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3"); - } -#endif -} - -void fdt_fixup_board_enet(void *fdt) -{ -} diff --git a/board/nxp/t102xrdb/t102xrdb.c b/board/nxp/t102xrdb/t102xrdb.c index 0a29e27b42c..02223497dd3 100644 --- a/board/nxp/t102xrdb/t102xrdb.c +++ b/board/nxp/t102xrdb/t102xrdb.c @@ -207,7 +207,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif #ifdef CONFIG_TARGET_T1023RDB diff --git a/board/nxp/t102xrdb/t102xrdb.h b/board/nxp/t102xrdb/t102xrdb.h index 33df0f24df8..71e2cfea22e 100644 --- a/board/nxp/t102xrdb/t102xrdb.h +++ b/board/nxp/t102xrdb/t102xrdb.h @@ -6,7 +6,6 @@ #ifndef __T1024_RDB_H__ #define __T1024_RDB_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #ifdef CONFIG_TARGET_T1023RDB static u32 t1023rdb_ctrl(u32 ctrl_type); diff --git a/board/nxp/t104xrdb/Makefile b/board/nxp/t104xrdb/Makefile index 9bca1a1fbcc..cee574aabb9 100644 --- a/board/nxp/t104xrdb/Makefile +++ b/board/nxp/t104xrdb/Makefile @@ -7,7 +7,6 @@ obj-y += spl.o else obj-y += t104xrdb.o obj-y += cpld.o -obj-y += eth.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/nxp/t104xrdb/eth.c b/board/nxp/t104xrdb/eth.c deleted file mode 100644 index c35ec368a45..00000000000 --- a/board/nxp/t104xrdb/eth.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <config.h> -#include <net.h> -#include <netdev.h> -#include <asm/fsl_serdes.h> -#include <asm/immap_85xx.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <malloc.h> -#include <fsl_dtsec.h> -#include <vsc9953.h> - -#include "../common/fman.h" - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info memac_mdio_info; - unsigned int i; - int phy_addr = 0; - - printf("Initializing Fman\n"); - - memac_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fm_memac_mdio_init(bis, &memac_mdio_info); - - /* - * Program on board RGMII, SGMII PHY addresses. - */ - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_TARGET_T1042D4RDB - case PHY_INTERFACE_MODE_SGMII: - /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 - * & DTSEC3 - */ - if (FM1_DTSEC1 == i) - phy_addr = CFG_SYS_SGMII1_PHY_ADDR; - if (FM1_DTSEC2 == i) - phy_addr = CFG_SYS_SGMII2_PHY_ADDR; - if (FM1_DTSEC3 == i) - phy_addr = CFG_SYS_SGMII3_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; -#endif - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (FM1_DTSEC4 == i) - phy_addr = CFG_SYS_RGMII1_PHY_ADDR; - if (FM1_DTSEC5 == i) - phy_addr = CFG_SYS_RGMII2_PHY_ADDR; - fm_info_set_phy_address(i, phy_addr); - break; - case PHY_INTERFACE_MODE_QSGMII: - fm_info_set_phy_address(i, 0); - break; - case PHY_INTERFACE_MODE_NA: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII || - fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA) - fm_info_set_mdio(i, NULL); - else - fm_info_set_mdio(i, - miiphy_get_dev_by_name( - DEFAULT_FM_MDIO_NAME)); - } - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/nxp/t104xrdb/t104xrdb.h b/board/nxp/t104xrdb/t104xrdb.h index 678724c7e2b..5825e69cdb4 100644 --- a/board/nxp/t104xrdb/t104xrdb.h +++ b/board/nxp/t104xrdb/t104xrdb.h @@ -6,7 +6,6 @@ #ifndef __T104x_RDB_H__ #define __T104x_RDB_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/nxp/t208xqds/Makefile b/board/nxp/t208xqds/Makefile index eb99d921b4a..4bfd2b50d8f 100644 --- a/board/nxp/t208xqds/Makefile +++ b/board/nxp/t208xqds/Makefile @@ -7,7 +7,7 @@ ifdef CONFIG_XPL_BUILD obj-y += spl.o else -obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o +obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o endif obj-y += ddr.o diff --git a/board/nxp/t208xqds/eth_t208xqds.c b/board/nxp/t208xqds/eth_t208xqds.c deleted file mode 100644 index b55078c8fe1..00000000000 --- a/board/nxp/t208xqds/eth_t208xqds.c +++ /dev/null @@ -1,723 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - * - * Shengzhou Liu <[email protected]> - */ - -#include <config.h> -#include <command.h> -#include <fdt_support.h> -#include <log.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fsl_dtsec.h> -#include <asm/fsl_serdes.h> -#include <hwconfig.h> -#include "../common/qixis.h" -#include "../common/fman.h" -#include "t208xqds_qixis.h" -#include <linux/libfdt.h> - -#define EMI_NONE 0xFFFFFFFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#if defined(CONFIG_TARGET_T2080QDS) -#define EMI1_SLOT2 6 -#define EMI1_SLOT3 3 -#define EMI1_SLOT4 4 -#define EMI1_SLOT5 5 -#define EMI2 7 -#endif - -#define PCCR1_SGMIIA_KX_MASK 0x00008000 -#define PCCR1_SGMIIB_KX_MASK 0x00004000 -#define PCCR1_SGMIIC_KX_MASK 0x00002000 -#define PCCR1_SGMIID_KX_MASK 0x00001000 -#define PCCR1_SGMIIE_KX_MASK 0x00000800 -#define PCCR1_SGMIIF_KX_MASK 0x00000400 -#define PCCR1_SGMIIG_KX_MASK 0x00000200 -#define PCCR1_SGMIIH_KX_MASK 0x00000100 - -static int mdio_mux[NUM_FM_PORTS]; - -static const char * const mdio_names[] = { -#if defined(CONFIG_TARGET_T2080QDS) - "T2080QDS_MDIO_RGMII1", - "T2080QDS_MDIO_RGMII2", - "T2080QDS_MDIO_SLOT1", - "T2080QDS_MDIO_SLOT3", - "T2080QDS_MDIO_SLOT4", - "T2080QDS_MDIO_SLOT5", - "T2080QDS_MDIO_SLOT2", - "T2080QDS_MDIO_10GC", -#endif -}; - -/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ -#if defined(CONFIG_TARGET_T2080QDS) -static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; -#endif - -static const char *t208xqds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name = t208xqds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -struct t208xqds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void t208xqds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - if (muxval < 8) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct t208xqds_mdio *priv = bus->priv; - - t208xqds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int t208xqds_mdio_reset(struct mii_dev *bus) -{ - struct t208xqds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int t208xqds_mdio_init(char *realbusname, u8 muxval) -{ - struct t208xqds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate t208xqds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate t208xqds private data\n"); - free(bus); - return -1; - } - - bus->read = t208xqds_mdio_read; - bus->write = t208xqds_mdio_write; - bus->reset = t208xqds_mdio_reset; - strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - int phy; - char alias[20]; - char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; - char buf[32] = "serdes-1,"; - struct fixed_link f_link; - int media_type = 0; - const char *phyconn; - int off; - - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); -#ifdef CONFIG_TARGET_T2080QDS - serdes_corenet_t *srds_regs = - (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; - u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); -#endif - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - phy = fm_info_get_phy_address(port); - switch (port) { -#if defined(CONFIG_TARGET_T2080QDS) - case FM1_DTSEC1: - if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx1"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIH_KX_MASK); - break; - } - case FM1_DTSEC2: - if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx2"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIG_KX_MASK); - break; - } - case FM1_DTSEC9: - if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx9"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIE_KX_MASK); - break; - } - case FM1_DTSEC10: - if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx10"); - fdt_status_okay_by_alias(fdt, - "1gkx_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIF_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } else if (mdio_mux[port] == EMI1_SLOT3) { - sprintf(alias, "phy_sgmii_s3_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - } - break; - case FM1_DTSEC5: - if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx5"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); - strcat(buf, "lane-g,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIIC_KX_MASK); - break; - } - case FM1_DTSEC6: - if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_1gkx6"); - fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); - strcat(buf, "lane-h,"); - strcat(buf, (char *)lane_mode[0]); - out_be32(&srds_regs->srdspccr1, srds1_pccr1 | - PCCR1_SGMIID_KX_MASK); - break; - } - if (mdio_mux[port] == EMI1_SLOT1) { - sprintf(alias, "phy_sgmii_s1_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot1"); - } else if (mdio_mux[port] == EMI1_SLOT2) { - sprintf(alias, "phy_sgmii_s2_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } - break; -#endif - default: - break; - } - if (media_type) { - /* set property for 1000BASE-KX in dtb */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, "lane-instance", buf); - } - - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { - switch (srds_s1) { - case 0x66: /* 10GBase-R interface */ - case 0x6b: - case 0x6c: - case 0x6d: - case 0x71: - /* - * Check hwconfig to see what is the media type, there - * are two types, fiber or copper, fix the dtb - * accordingly. - */ - switch (port) { - case FM1_10GEC1: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { - /* it's MAC9 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi9"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); - strcat(buf, "lane-a,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC2: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { - /* it's MAC10 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi10"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); - strcat(buf, "lane-b,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC3: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { - /* it's MAC1 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi1"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); - strcat(buf, "lane-c,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - case FM1_10GEC4: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { - /* it's MAC2 */ - media_type = 1; - fdt_set_phy_handle(fdt, compat, addr, - "phy_xfi2"); - fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); - strcat(buf, "lane-d,"); - strcat(buf, (char *)lane_mode[1]); - } - break; - default: - return; - } - - if (!media_type) { - phyconn = fdt_getprop(fdt, offset, - "phy-connection-type", - NULL); - if (is_backplane_mode(phyconn)) { - /* Backplane KR mode: skip fixups */ - printf("Interface %d in backplane KR mode\n", - port); - } else { - /* fixed-link for 10GBase-R fiber cable */ - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", - &f_link, sizeof(f_link)); - } - } else { - /* set property for copper cable */ - off = fdt_node_offset_by_compat_reg(fdt, - "fsl,fman-memac-mdio", addr + 0x1000); - fdt_setprop_string(fdt, off, - "lane-instance", buf); - } - break; - default: - break; - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -/* - * This function reads RCW to check if Serdes1{A:H} is configured - * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly - */ -static void initialize_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - switch (srds_s1) { -#if defined(CONFIG_TARGET_T2080QDS) - case 0x51: - case 0x5f: - case 0x65: - case 0x6b: - case 0x71: - lane_to_slot[5] = 2; - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - case 0xd3: - case 0xd9: - case 0xcb: - lane_to_slot[6] = 2; - lane_to_slot[7] = 2; - break; - case 0xda: - lane_to_slot[4] = 3; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; -#endif - default: - break; - } -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 rcwsr13 = in_be32(&gur->rcwsr[13]); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - initialize_lane_to_slot(); - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); -#if defined(CONFIG_TARGET_T2080QDS) - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); -#endif - t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); - if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == - FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); - else - fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); - - switch (srds_s1) { - case 0x1b: - case 0x1c: - case 0x95: - case 0xa2: - case 0x94: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x50: - case 0x51: - case 0x5e: - case 0x5f: - case 0x64: - case 0x65: - /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x66: - case 0x67: - /* - * 10GBase-R does not need a PHY to work, but to avoid U-Boot - * use default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to 10GBase-R - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the 10GBase-R MAC, which will cause - * error. - */ - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - break; - case 0x6a: - case 0x6b: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - fm_info_set_phy_address(FM1_10GEC3, 6); - fm_info_set_phy_address(FM1_10GEC4, 7); - /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0x6c: - case 0x6d: - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_10GEC2, 5); - /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; - case 0x70: - case 0x71: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa6: - case 0x8e: - case 0x8f: - case 0x82: - case 0x83: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; - case 0xa4: - case 0x96: - case 0x8a: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - break; -#if defined(CONFIG_TARGET_T2080QDS) - case 0xd9: - case 0xd3: - case 0xcb: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); - /* SGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - break; -#endif - case 0xf2: - /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); - break; - default: - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII1; - else if (i == FM1_DTSEC4 || FM1_DTSEC10) - mdio_mux[i] = EMI1_RGMII2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - idx = i - FM1_10GEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - if (srds_s1 == 0x51) { - lane = serdes_get_first_lane(FSL_SRDS_1, - XAUI_FM1_MAC9 + idx); - } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { - lane = serdes_get_first_lane(FSL_SRDS_1, - HIGIG_FM1_MAC9 + idx); - } else { - if (i == FM1_10GEC1 || i == FM1_10GEC2) - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC9 + idx); - else - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC1 + idx); - } - - if (lane < 0) - break; - mdio_mux[i] = EMI2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - - if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || - (srds_s1 == 0x6a) || (srds_s1 == 0x70) || - (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || - (srds_s1 == 0x71)) { - /* As 10GBase-R is in cage intead of a slot, so - * ensure doesn't disable the corresponding port - */ - break; - } - - slot = lane_to_slot[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/nxp/t208xqds/t208xqds.c b/board/nxp/t208xqds/t208xqds.c index 5e71da0e163..329cf59793f 100644 --- a/board/nxp/t208xqds/t208xqds.c +++ b/board/nxp/t208xqds/t208xqds.c @@ -419,7 +419,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif return 0; diff --git a/board/nxp/t208xqds/t208xqds.h b/board/nxp/t208xqds/t208xqds.h index 50ebb6f6f98..4086f8c010a 100644 --- a/board/nxp/t208xqds/t208xqds.h +++ b/board/nxp/t208xqds/t208xqds.h @@ -6,7 +6,6 @@ #ifndef __CORENET_DS_H__ #define __CORENET_DS_H__ -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/nxp/t208xrdb/eth_t208xrdb.c b/board/nxp/t208xrdb/eth_t208xrdb.c index 5223eccb280..c9e415bc446 100644 --- a/board/nxp/t208xrdb/eth_t208xrdb.c +++ b/board/nxp/t208xrdb/eth_t208xrdb.c @@ -93,8 +93,3 @@ void fdt_fixup_board_phy(void *fdt) printf("Unable to rename node ethernet-phy@1: %s\n", fdt_strerror(ret)); } - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} diff --git a/board/nxp/t208xrdb/t208xrdb.c b/board/nxp/t208xrdb/t208xrdb.c index d93edf007ad..d47ec91e7d0 100644 --- a/board/nxp/t208xrdb/t208xrdb.c +++ b/board/nxp/t208xrdb/t208xrdb.c @@ -160,7 +160,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_board_fman_ethernet(blob); - fdt_fixup_board_enet(blob); fdt_fixup_board_phy(blob); #endif diff --git a/board/nxp/t208xrdb/t208xrdb.h b/board/nxp/t208xrdb/t208xrdb.h index 26998898e82..e800270a0e2 100644 --- a/board/nxp/t208xrdb/t208xrdb.h +++ b/board/nxp/t208xrdb/t208xrdb.h @@ -10,7 +10,6 @@ #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000 -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); void fdt_fixup_board_fman_ethernet(void *blob); void fdt_fixup_board_phy(void *blob); diff --git a/board/nxp/t4rdb/Makefile b/board/nxp/t4rdb/Makefile index 8d94faaba1c..6d9b8df2fc1 100644 --- a/board/nxp/t4rdb/Makefile +++ b/board/nxp/t4rdb/Makefile @@ -9,7 +9,6 @@ obj-y += spl.o else obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o obj-y += cpld.o -obj-y += eth.o endif obj-y += ddr.o diff --git a/board/nxp/t4rdb/eth.c b/board/nxp/t4rdb/eth.c deleted file mode 100644 index e7646365d7d..00000000000 --- a/board/nxp/t4rdb/eth.c +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Chunhe Lan <[email protected]> - */ - -#include <config.h> -#include <command.h> -#include <fdt_support.h> -#include <net.h> -#include <netdev.h> -#include <asm/mmu.h> -#include <asm/processor.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_law.h> -#include <fsl_ddr_sdram.h> -#include <asm/fsl_serdes.h> -#include <asm/fsl_portals.h> -#include <asm/fsl_liodn.h> -#include <malloc.h> -#include <fm_eth.h> -#include <fsl_mdio.h> -#include <miiphy.h> -#include <phy.h> -#include <fsl_dtsec.h> -#include <asm/fsl_serdes.h> -#include <hwconfig.h> - -#include "../common/fman.h" -#include "t4rdb.h" - -void fdt_fixup_board_enet(void *fdt) -{ - return; -} - -int board_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) { - /* SGMII */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); - fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); - } else { - puts("Invalid SerDes1 protocol for T4240RDB\n"); - } - - fm_disable_port(FM1_DTSEC5); - fm_disable_port(FM1_DTSEC6); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - -#if (CFG_SYS_NUM_FMAN == 2) - if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { - /* SGMII && 10GBase-R */ - fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); - fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); - fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); - } else { - puts("Invalid SerDes2 protocol for T4240RDB\n"); - } - - fm_disable_port(FM2_DTSEC5); - fm_disable_port(FM2_DTSEC6); - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) { - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); - fm_info_set_mdio(i, dev); - break; - default: - break; - } - } -#endif /* CFG_SYS_NUM_FMAN */ - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/nxp/t4rdb/t4240rdb.c b/board/nxp/t4rdb/t4240rdb.c index 5cacfd27380..11e2c0f78b7 100644 --- a/board/nxp/t4rdb/t4240rdb.c +++ b/board/nxp/t4rdb/t4240rdb.c @@ -128,7 +128,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); #endif - fdt_fixup_board_enet(blob); #endif return 0; diff --git a/board/nxp/t4rdb/t4rdb.h b/board/nxp/t4rdb/t4rdb.h index bb3ce216d7d..9ec190c03cb 100644 --- a/board/nxp/t4rdb/t4rdb.h +++ b/board/nxp/t4rdb/t4rdb.h @@ -14,7 +14,6 @@ #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 -void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); #endif diff --git a/board/pine64/quartz64_rk3566/MAINTAINERS b/board/pine64/quartz64_rk3566/MAINTAINERS index 37b8c1eb78b..955cb5de030 100644 --- a/board/pine64/quartz64_rk3566/MAINTAINERS +++ b/board/pine64/quartz64_rk3566/MAINTAINERS @@ -9,26 +9,11 @@ F: configs/quartz64-b-rk3566_defconfig F: configs/soquartz-blade-rk3566_defconfig F: configs/soquartz-cm4-rk3566_defconfig F: configs/soquartz-model-a-rk3566_defconfig -F: arch/arm/dts/rk3566-quartz64-a.dts -F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -F: arch/arm/dts/rk3566-quartz64-b.dts -F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz.dtsi -F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz-blade.dts -F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz-cm4.dts -F: arch/arm/dts/rk3566-soquartz-cm4-u-boot.dtsi -F: arch/arm/dts/rk3566-soquartz-model-a.dts -F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi +F: arch/arm/dts/rk3566-quartz64* +F: arch/arm/dts/rk3566-soquartz* PINETAB2-RK3566 M: Jonas Karlman <[email protected]> S: Maintained F: configs/pinetab2-rk3566_defconfig -F: arch/arm/dts/rk3566-pinetab2.dtsi -F: arch/arm/dts/rk3566-pinetab2-u-boot.dtsi -F: arch/arm/dts/rk3566-pinetab2-v0.1.dts -F: arch/arm/dts/rk3566-pinetab2-v0.1-u-boot.dtsi -F: arch/arm/dts/rk3566-pinetab2-v2.0.dts -F: arch/arm/dts/rk3566-pinetab2-v2.0-u-boot.dtsi +F: arch/arm/dts/rk3566-pinetab2* diff --git a/board/pine64/quartzpro64-rk3588/MAINTAINERS b/board/pine64/quartzpro64-rk3588/MAINTAINERS index a7e944b7478..ff3500a32fc 100644 --- a/board/pine64/quartzpro64-rk3588/MAINTAINERS +++ b/board/pine64/quartzpro64-rk3588/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/pine64/quartzpro64-rk3588 F: include/configs/quartzpro64-rk3588.h F: configs/quartzpro64-rk3588_defconfig -F: arch/arm/dts/rk3588-quartzpro64.dts -F: arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi +F: arch/arm/dts/rk3588-quartzpro64* diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c index 7f0925074fa..23d24140ca7 100644 --- a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -26,7 +26,7 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -#if CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP) +#if CONFIG_IS_ENABLED(NET) int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) diff --git a/board/qualcomm/debug-milos.config b/board/qualcomm/debug-milos.config new file mode 100644 index 00000000000..a4cdd13f226 --- /dev/null +++ b/board/qualcomm/debug-milos.config @@ -0,0 +1,5 @@ +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_BASE=0xa94000 +CONFIG_DEBUG_UART_MSM_GENI=y +CONFIG_DEBUG_UART_CLOCK=14745600 diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config index 3fd064924a1..cf334d7ee20 100644 --- a/board/qualcomm/dragonboard410c/configs/chainloaded.config +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config @@ -4,4 +4,4 @@ CONFIG_TEXT_BASE=0x0 # CONFIG_REMAKE_ELF is not set CONFIG_POSITION_INDEPENDENT=y CONFIG_INIT_SP_RELATIVE=y -CONFIG_SYS_INIT_SP_BSS_OFFSET=524288 +CONFIG_SYS_INIT_SP_BSS_OFFSET=0x80000 diff --git a/board/qualcomm/qcom-phone.env b/board/qualcomm/qcom-phone.env index e91ae3ecdfb..d1c586bd3fb 100644 --- a/board/qualcomm/qcom-phone.env +++ b/board/qualcomm/qcom-phone.env @@ -39,7 +39,7 @@ bootmenu_5=Reset device=reset bootmenu_6=Dump clocks=clk dump; pause bootmenu_7=Dump environment=printenv; pause bootmenu_8=Board info=bdinfo; pause -bootmenu_9=Dump bootargs=fdt print /chosen bootargs; pause +bootmenu_9=Dump bootargs=fdt addr $fdt_addr_r; fdt print /chosen bootargs; pause # Allow holding the volume down button while U-Boot loads to enter # the boot menu diff --git a/board/qualcomm/tfa-optee.config b/board/qualcomm/tfa-optee.config new file mode 100644 index 00000000000..1e8364c114f --- /dev/null +++ b/board/qualcomm/tfa-optee.config @@ -0,0 +1,4 @@ +# Enables support for TF-A based OP-TEE as the open +# source TrustZone stack on Qcom platforms +CONFIG_TEE=y +CONFIG_OPTEE=y diff --git a/board/radxa/rock5a-rk3588s/MAINTAINERS b/board/radxa/rock5a-rk3588s/MAINTAINERS index a569efa74e3..d4cd82139d5 100644 --- a/board/radxa/rock5a-rk3588s/MAINTAINERS +++ b/board/radxa/rock5a-rk3588s/MAINTAINERS @@ -1,9 +1,8 @@ ROCK5A-RK3588 -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: board/radxa/rock5a-rk3588s F: include/configs/rock5a-rk3588s.h F: configs/rock5a-rk3588s_defconfig -F: arch/arm/dts/rk3588s-rock-5a.dts -F: arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi +F: arch/arm/dts/rk3588s-rock-5a* diff --git a/board/radxa/rock5b-rk3588/MAINTAINERS b/board/radxa/rock5b-rk3588/MAINTAINERS index c8a43769105..2910d9bed3d 100644 --- a/board/radxa/rock5b-rk3588/MAINTAINERS +++ b/board/radxa/rock5b-rk3588/MAINTAINERS @@ -1,5 +1,5 @@ ROCK5B-RK3588 -M: Eugen Hristev <[email protected]> +M: Eugen Hristev <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: board/radxa/rock5b-rk3588 diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 889de8ea9ac..16902d216f6 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -45,9 +45,13 @@ endif endif ifdef CONFIG_RCAR_GEN5 +ifdef CONFIG_RCAR_64_RSIP +obj-y += gen5-cm33.o +else obj-y += gen5-common.o endif endif +endif endif endif diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c index e4c1190eac7..5a0b0ebe115 100644 --- a/board/renesas/common/gen4-spl.c +++ b/board/renesas/common/gen4-spl.c @@ -18,6 +18,12 @@ #include <mapmem.h> #include <spl.h> +#define APMU_BASE 0xe6170000U +#define CL0GRP3_BIT BIT(3) +#define CL1GRP3_BIT BIT(7) +#define RTGRP3_BIT BIT(19) +#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) + #define CNTCR_EN BIT(0) #ifdef CONFIG_SPL_BUILD @@ -47,6 +53,18 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; + /* Unlock CPG access */ + writel(0x5A5AFFFF, CPGWPR); + writel(0xA5A50000, CPGWPCR); + init_generic_timer(); + + /* Define for Work Around of APMU */ + writel(0x00ff00ff, APMU_BASE + 0x10); + writel(0x00ff00ff, APMU_BASE + 0x14); + writel(0x00ff00ff, APMU_BASE + 0x18); + writel(0x00ff00ff, APMU_BASE + 0x1c); + clrbits_le32(APMU_BASE + 0x68, BIT(29)); + if (CONFIG_IS_ENABLED(OF_CONTROL)) { ret = spl_early_init(); if (ret) { @@ -76,29 +94,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0); } -#define APMU_BASE 0xe6170000U -#define CL0GRP3_BIT BIT(3) -#define CL1GRP3_BIT BIT(7) -#define RTGRP3_BIT BIT(19) -#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) - -int mach_cpu_init(void) -{ - /* Unlock CPG access */ - writel(0x5A5AFFFF, CPGWPR); - writel(0xA5A50000, CPGWPCR); - init_generic_timer(); - - /* Define for Work Around of APMU */ - writel(0x00ff00ff, APMU_BASE + 0x10); - writel(0x00ff00ff, APMU_BASE + 0x14); - writel(0x00ff00ff, APMU_BASE + 0x18); - writel(0x00ff00ff, APMU_BASE + 0x1c); - clrbits_le32(APMU_BASE + 0x68, BIT(29)); - - return 0; -} - void reset_cpu(void) { } diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c new file mode 100644 index 00000000000..e07db9817f2 --- /dev/null +++ b/board/renesas/common/gen5-cm33.c @@ -0,0 +1,1409 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include <asm/arch/renesas.h> +#include <asm/arch/sys_proto.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/processor.h> +#include <asm/system.h> +#include <dm/uclass.h> +#include <hang.h> +#include <linux/bitfield.h> +#include <linux/errno.h> +#include <linux/iopoll.h> +#include <lmb.h> + +#include "gen5-cm33.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +#define PKC_PROT_LOCK 0xa5a5a500 +#define PKC_PROT_UNLOCK 0xa5a5a501 + +#define RSIP_BASE 0xe0000000 +#define RSIP_NVIC_ISER_00 (RSIP_BASE + 0xe100) +#define RSIP_NVIC_ISER_00_SETENA_INTIWDTA0 BIT(16) +#define RSIP_NVIC_ICER_00 (RSIP_BASE + 0xe180) +#define RSIP_NVIC_ICER_01 (RSIP_BASE + 0xe184) +#define RSIP_NVIC_ICER_02 (RSIP_BASE + 0xe188) +#define RSIP_NVIC_ICER_03 (RSIP_BASE + 0xe18c) +#define RSIP_NVIC_ICER_04 (RSIP_BASE + 0xe190) +#define RSIP_NVIC_ICER_05 (RSIP_BASE + 0xe194) +#define RSIP_NVIC_ICER_06 (RSIP_BASE + 0xe198) +#define RSIP_NVIC_ICER_07 (RSIP_BASE + 0xe19c) +#define RSIP_NVIC_ICER_08 (RSIP_BASE + 0xe1a0) +#define RSIP_NVIC_ICER_09 (RSIP_BASE + 0xe1a4) +#define RSIP_NVIC_ICER_10 (RSIP_BASE + 0xe1a8) +#define RSIP_NVIC_ICER_11 (RSIP_BASE + 0xe1ac) +#define RSIP_NVIC_ICER_12 (RSIP_BASE + 0xe1b0) +#define RSIP_NVIC_ICER_13 (RSIP_BASE + 0xe1b4) +#define RSIP_NVIC_ICER_14 (RSIP_BASE + 0xe1b8) +#define RSIP_NVIC_ICER_15 (RSIP_BASE + 0xe1bc) +#define RSIP_SHCSR (RSIP_BASE + 0xed24) +#define RSIP_SHCSR_USGFAULTENA BIT(18) +#define RSIP_SHCSR_BUSFAULTENA BIT(17) +#define RSIP_SHCSR_MEMFAULTENA BIT(16) + +#define RSIP_CTL_BASE 0x5fffd000 +#define RSIP_CTL_CFG4 (RSIP_CTL_BASE + 0xb0) +#define RSIP_CTL_CFG4_OPWDEN BIT(3) +#define RSIP_CTL_CFG4_OPWDVAC BIT(5) +#define RSIP_CTL_ESICREMAP0 (RSIP_CTL_BASE + 0x70) +#define RSIP_CTL_PROT0PCMD (RSIP_CTL_BASE + 0x840) +#define RSIP_CTL_PROT0PCMD_WREN 0xa5 +#define RSIP_CTL_PROT0PS (RSIP_CTL_BASE + 0x844) +#define RSIP_CTL_PROT0PS_ERR BIT(0) + +#define SYSSS_BASE 0xc1320000 +#define SYSSS_MODE1 (SYSSS_BASE + 0x1010) +#define SYSSS_MODE1_MASK GENMASK(11, 0) +#define SYSSS_MODE1_BAUDRATE_MASK GENMASK(10, 9) +#define SYSSS_MODE1_BAUDRATE_921600 1 +#define SYSSS_MODE1_BAUDRATE_1843200 2 +#define SYSSS_MODE1_BAUDRATE_3250000 3 +#define SYSSS_MODE1_BOOTMODE_MASK GENMASK(20, 18) +#define SYSSS_MODE1_BOOTMODE_HF_DMA 2 +#define SYSSS_MODE1_BOOTMODE_QSPI 4 +#define SYSSS_MODE1_BOOTMODE_UFS 6 + +#define CLK_CONTROL_TOP_BASE 0xc6480000 +#define CLK_CONTROL_SCP_BASE 0xc1330000 +#define CLK_CONTROL_PERE_BASE 0xc08f0000 + +#define CLK_CONTROL_PLL01_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1108) +#define CLK_CONTROL_PLL01_1_CR0 (CLK_CONTROL_TOP_BASE + 0x1114) +#define CLK_CONTROL_PLL02_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1120) +#define CLK_CONTROL_PLL02_1_CR0 (CLK_CONTROL_TOP_BASE + 0x112c) +#define CLK_CONTROL_PLL02_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1138) +#define CLK_CONTROL_PLL02_3_CR0 (CLK_CONTROL_TOP_BASE + 0x1144) +#define CLK_CONTROL_PLL02_4_CR0 (CLK_CONTROL_TOP_BASE + 0x1150) +#define CLK_CONTROL_PLL02_5_CR0 (CLK_CONTROL_TOP_BASE + 0x115c) +#define CLK_CONTROL_PLL02_6_CR0 (CLK_CONTROL_TOP_BASE + 0x1168) +#define CLK_CONTROL_PLL02_7_CR0 (CLK_CONTROL_TOP_BASE + 0x1174) +#define CLK_CONTROL_PLL03_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1180) +#define CLK_CONTROL_PLL03_1_CR0 (CLK_CONTROL_TOP_BASE + 0x118c) +#define CLK_CONTROL_PLL03_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1198) +#define CLK_CONTROL_PLL03_3_CR0 (CLK_CONTROL_TOP_BASE + 0x11a4) +#define CLK_CONTROL_PLL06_CR0 (CLK_CONTROL_TOP_BASE + 0x11c8) +#define CLK_CONTROL_PLL07_CR0 (CLK_CONTROL_TOP_BASE + 0x11d4) +#define CLK_CONTROL_PLL12_CR0 (CLK_CONTROL_TOP_BASE + 0x121c) +#define CLK_CONTROL_PLL13_CR0 (CLK_CONTROL_SCP_BASE + 0x1228) +#define CLK_CONTROL_PLL14_CR0 (CLK_CONTROL_TOP_BASE + 0x1234) +#define CLK_CONTROL_PLL15_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1240) +#define CLK_CONTROL_PLL15_1_CR0 (CLK_CONTROL_TOP_BASE + 0x124c) +#define CLK_CONTROL_PLL15_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1258) +#define CLK_CONTROL_PLL15_3_CR0 (CLK_CONTROL_TOP_BASE + 0x1264) +#define CLK_CONTROL_PLL01_0_CR1 (CLK_CONTROL_TOP_BASE + 0x110c) +#define CLK_CONTROL_PLL01_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1118) +#define CLK_CONTROL_PLL02_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1124) +#define CLK_CONTROL_PLL02_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1130) +#define CLK_CONTROL_PLL02_2_CR1 (CLK_CONTROL_TOP_BASE + 0x113c) +#define CLK_CONTROL_PLL02_3_CR1 (CLK_CONTROL_TOP_BASE + 0x1148) +#define CLK_CONTROL_PLL02_4_CR1 (CLK_CONTROL_TOP_BASE + 0x1154) +#define CLK_CONTROL_PLL02_5_CR1 (CLK_CONTROL_TOP_BASE + 0x1160) +#define CLK_CONTROL_PLL02_6_CR1 (CLK_CONTROL_TOP_BASE + 0x116c) +#define CLK_CONTROL_PLL02_7_CR1 (CLK_CONTROL_TOP_BASE + 0x1178) +#define CLK_CONTROL_PLL03_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1184) +#define CLK_CONTROL_PLL03_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1190) +#define CLK_CONTROL_PLL03_2_CR1 (CLK_CONTROL_TOP_BASE + 0x119c) +#define CLK_CONTROL_PLL03_3_CR1 (CLK_CONTROL_TOP_BASE + 0x11a8) +#define CLK_CONTROL_PLL06_CR1 (CLK_CONTROL_TOP_BASE + 0x11cc) +#define CLK_CONTROL_PLL07_CR1 (CLK_CONTROL_TOP_BASE + 0x11d8) +#define CLK_CONTROL_PLL12_CR1 (CLK_CONTROL_TOP_BASE + 0x1220) +#define CLK_CONTROL_PLL13_CR1 (CLK_CONTROL_SCP_BASE + 0x122c) +#define CLK_CONTROL_PLL14_CR1 (CLK_CONTROL_TOP_BASE + 0x1238) +#define CLK_CONTROL_PLL15_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1244) +#define CLK_CONTROL_PLL15_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1250) +#define CLK_CONTROL_PLL15_2_CR1 (CLK_CONTROL_TOP_BASE + 0x125c) +#define CLK_CONTROL_PLL15_3_CR1 (CLK_CONTROL_TOP_BASE + 0x1268) +#define CLK_CONTROL_PLL01_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1110) +#define CLK_CONTROL_PLL01_1_CR2 (CLK_CONTROL_TOP_BASE + 0x111c) +#define CLK_CONTROL_PLL02_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1128) +#define CLK_CONTROL_PLL02_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1134) +#define CLK_CONTROL_PLL02_2_CR2 (CLK_CONTROL_TOP_BASE + 0x1140) +#define CLK_CONTROL_PLL02_3_CR2 (CLK_CONTROL_TOP_BASE + 0x114c) +#define CLK_CONTROL_PLL02_4_CR2 (CLK_CONTROL_TOP_BASE + 0x1158) +#define CLK_CONTROL_PLL02_5_CR2 (CLK_CONTROL_TOP_BASE + 0x1164) +#define CLK_CONTROL_PLL02_6_CR2 (CLK_CONTROL_TOP_BASE + 0x1170) +#define CLK_CONTROL_PLL02_7_CR2 (CLK_CONTROL_TOP_BASE + 0x117c) +#define CLK_CONTROL_PLL03_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1188) +#define CLK_CONTROL_PLL03_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1194) +#define CLK_CONTROL_PLL03_2_CR2 (CLK_CONTROL_TOP_BASE + 0x11a0) +#define CLK_CONTROL_PLL03_3_CR2 (CLK_CONTROL_TOP_BASE + 0x11ac) +#define CLK_CONTROL_PLL06_CR2 (CLK_CONTROL_TOP_BASE + 0x11d0) +#define CLK_CONTROL_PLL07_CR2 (CLK_CONTROL_TOP_BASE + 0x11dc) +#define CLK_CONTROL_PLL12_CR2 (CLK_CONTROL_TOP_BASE + 0x1224) +#define CLK_CONTROL_PLL13_CR2 (CLK_CONTROL_SCP_BASE + 0x1230) +#define CLK_CONTROL_PLL14_CR2 (CLK_CONTROL_TOP_BASE + 0x123c) +#define CLK_CONTROL_PLL15_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1248) +#define CLK_CONTROL_PLL15_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1254) +#define CLK_CONTROL_PLL15_2_CR2 (CLK_CONTROL_TOP_BASE + 0x1260) +#define CLK_CONTROL_PLL15_3_CR2 (CLK_CONTROL_TOP_BASE + 0x126c) +#define CLK_CONTROL_PLL01_0_SCR (CLK_CONTROL_TOP_BASE + 0x1270) +#define CLK_CONTROL_PLL01_1_SCR (CLK_CONTROL_TOP_BASE + 0x1278) +#define CLK_CONTROL_PLL02_0_SCR (CLK_CONTROL_TOP_BASE + 0x1280) +#define CLK_CONTROL_PLL02_1_SCR (CLK_CONTROL_TOP_BASE + 0x1288) +#define CLK_CONTROL_PLL02_2_SCR (CLK_CONTROL_TOP_BASE + 0x1290) +#define CLK_CONTROL_PLL02_3_SCR (CLK_CONTROL_TOP_BASE + 0x1298) +#define CLK_CONTROL_PLL02_4_SCR (CLK_CONTROL_TOP_BASE + 0x12a0) +#define CLK_CONTROL_PLL02_5_SCR (CLK_CONTROL_TOP_BASE + 0x12a8) +#define CLK_CONTROL_PLL02_6_SCR (CLK_CONTROL_TOP_BASE + 0x12b0) +#define CLK_CONTROL_PLL02_7_SCR (CLK_CONTROL_TOP_BASE + 0x12b8) +#define CLK_CONTROL_PLL03_0_SCR (CLK_CONTROL_TOP_BASE + 0x12c0) +#define CLK_CONTROL_PLL03_1_SCR (CLK_CONTROL_TOP_BASE + 0x12c8) +#define CLK_CONTROL_PLL03_2_SCR (CLK_CONTROL_TOP_BASE + 0x12d0) +#define CLK_CONTROL_PLL03_3_SCR (CLK_CONTROL_TOP_BASE + 0x12d8) +#define CLK_CONTROL_PLL06_SCR (CLK_CONTROL_TOP_BASE + 0x12f0) +#define CLK_CONTROL_PLL07_SCR (CLK_CONTROL_TOP_BASE + 0x12f8) +#define CLK_CONTROL_PLL12_SCR (CLK_CONTROL_TOP_BASE + 0x1328) +#define CLK_CONTROL_PLL13_SCR (CLK_CONTROL_SCP_BASE + 0x1330) +#define CLK_CONTROL_PLL14_SCR (CLK_CONTROL_TOP_BASE + 0x1338) +#define CLK_CONTROL_PLL15_0_SCR (CLK_CONTROL_TOP_BASE + 0x1340) +#define CLK_CONTROL_PLL15_1_SCR (CLK_CONTROL_TOP_BASE + 0x1348) +#define CLK_CONTROL_PLL15_2_SCR (CLK_CONTROL_TOP_BASE + 0x1350) +#define CLK_CONTROL_PLL15_3_SCR (CLK_CONTROL_TOP_BASE + 0x1358) +#define CLK_CONTROL_PLL01_0_DCR (CLK_CONTROL_TOP_BASE + 0x1274) +#define CLK_CONTROL_PLL01_1_DCR (CLK_CONTROL_TOP_BASE + 0x127c) +#define CLK_CONTROL_PLL02_0_DCR (CLK_CONTROL_TOP_BASE + 0x1284) +#define CLK_CONTROL_PLL02_1_DCR (CLK_CONTROL_TOP_BASE + 0x128c) +#define CLK_CONTROL_PLL02_2_DCR (CLK_CONTROL_TOP_BASE + 0x1294) +#define CLK_CONTROL_PLL02_3_DCR (CLK_CONTROL_TOP_BASE + 0x129c) +#define CLK_CONTROL_PLL02_4_DCR (CLK_CONTROL_TOP_BASE + 0x12a4) +#define CLK_CONTROL_PLL02_5_DCR (CLK_CONTROL_TOP_BASE + 0x12ac) +#define CLK_CONTROL_PLL02_6_DCR (CLK_CONTROL_TOP_BASE + 0x12b4) +#define CLK_CONTROL_PLL02_7_DCR (CLK_CONTROL_TOP_BASE + 0x12bc) +#define CLK_CONTROL_PLL03_0_DCR (CLK_CONTROL_TOP_BASE + 0x12c4) +#define CLK_CONTROL_PLL03_1_DCR (CLK_CONTROL_TOP_BASE + 0x12cc) +#define CLK_CONTROL_PLL03_2_DCR (CLK_CONTROL_TOP_BASE + 0x12d4) +#define CLK_CONTROL_PLL03_3_DCR (CLK_CONTROL_TOP_BASE + 0x12dc) +#define CLK_CONTROL_PLL06_DCR (CLK_CONTROL_TOP_BASE + 0x12f4) +#define CLK_CONTROL_PLL07_DCR (CLK_CONTROL_TOP_BASE + 0x12fc) +#define CLK_CONTROL_PLL12_DCR (CLK_CONTROL_TOP_BASE + 0x132c) +#define CLK_CONTROL_PLL13_DCR (CLK_CONTROL_SCP_BASE + 0x1334) +#define CLK_CONTROL_PLL14_DCR (CLK_CONTROL_TOP_BASE + 0x133c) +#define CLK_CONTROL_PLL15_0_DCR (CLK_CONTROL_TOP_BASE + 0x1344) +#define CLK_CONTROL_PLL15_1_DCR (CLK_CONTROL_TOP_BASE + 0x134c) +#define CLK_CONTROL_PLL15_2_DCR (CLK_CONTROL_TOP_BASE + 0x1354) +#define CLK_CONTROL_PLL15_3_DCR (CLK_CONTROL_TOP_BASE + 0x135c) +#define CLK_CONTROL_RPCCKCR (CLK_CONTROL_PERE_BASE + 0x1030) +#define CLK_CONTROL_RPCCKCR_CKSTP1 BIT(8) +#define CLK_CONTROL_RPCCKCR_RPCFC_MASK GENMASK(4, 0) +#define CLK_CONTROL_PROT_REG_MASK 0xffff +#define CLK_CONTROL_PROT_REG 0x1370 + +#define CLK_CONTROL_PLL_CR2_PLLCLKSTAB BIT(31) +#define CLK_CONTROL_PLL_CR2_PLLDISTRG BIT(29) +#define CLK_CONTROL_PLL_CR2_PLLENTRG BIT(28) +#define CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC BIT(0) +#define CLK_CONTROL_PLL_SCR_SELACT_MASK BIT(16) +#define CLK_CONTROL_PLL_DCR_PLLDIVSYNC BIT(16) + +/** + * sysss_read_modemr() - Read MODE Register 1 + * @return: MD[11:0] pin state + */ +static u32 sysss_read_modemr(void) +{ + return readl(SYSSS_MODE1) & SYSSS_MODE1_MASK; +} + +/** + * clk_control_poll_cr2() - Poll CR2 until PLL is stable + * @cr2: PLL CR2 register address + */ +static void clk_control_poll_cr2(const u32 cr2) +{ + u32 val; + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(cr2); + if (val & CLK_CONTROL_PLL_CR2_PLLCLKSTAB) + break; + } +} + +/** + * clk_control_write_cr() - Write protected clock controller register + * @reg: Register address + * @val: Value to be written + */ +static void clk_control_write_cr(const u32 reg, const u32 val) +{ + const u32 protreg = (reg & ~CLK_CONTROL_PROT_REG_MASK) | CLK_CONTROL_PROT_REG; + + writel(PKC_PROT_UNLOCK, protreg); + writel(val, reg); + writel(PKC_PROT_LOCK, protreg); +} + +/** + * clk_control_write_and_poll_dcr() - Write and poll DCR + * @dcr: DCR register address + * @val: Value to be written + */ +static void clk_control_write_and_poll_dcr(const u32 dcr, const u32 val) +{ + u32 tmp; + + clk_control_write_cr(dcr, val); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + tmp = readl(dcr); + if (tmp & CLK_CONTROL_PLL_DCR_PLLDIVSYNC) + break; + } +} + +/** + * clk_control_switch_from_iosc_to_pll() - Switch clock from internal oscillator to PLL + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + */ +static void clk_control_switch_from_iosc_to_pll(const u32 cr2, const u32 scr) +{ + u32 val; + + clk_control_poll_cr2(cr2); + + /* Switch from internal oscillator to PLL. */ + val = readl(scr); + val &= ~CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC; + clk_control_write_cr(scr, val); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(scr); + if (!(val & CLK_CONTROL_PLL_SCR_SELACT_MASK)) + break; + } +} + +/** + * clk_control_switch_from_pll_to_iosc() - Switch clock from PLL to internal oscillator + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + */ +static void clk_control_switch_from_pll_to_iosc(const u32 cr2, const u32 scr) +{ + u32 val; + + clk_control_poll_cr2(cr2); + + /* Switch from PLL to internal oscillator. */ + clk_control_write_cr(scr, CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(scr); + if (val & CLK_CONTROL_PLL_SCR_SELACT_MASK) + break; + } +} + +/** + * clk_control_set_pll_freq() - Set PLL frequency + * @cr0: PLL CR0 register address + * @cr1: PLL CR1 register address + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + * @dcr: PLL DCR register address + * @cr0_val: PLL CR0 register value + * @cr1_val: PLL CR1 register value + * @dcr_val: PLL DCR register value + */ +static void clk_control_set_pll_freq(const u32 cr0, const u32 cr1, const u32 cr2, + const u32 scr, const u32 dcr, const u32 cr0_val, + const u32 cr1_val, const u32 dcr_val) +{ + u32 val; + + clk_control_switch_from_pll_to_iosc(cr2, scr); + + /* Disable PLL trigger and wait until it unlocks */ + clk_control_write_cr(cr2, CLK_CONTROL_PLL_CR2_PLLDISTRG); + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(cr2); + if (!(val & CLK_CONTROL_PLL_CR2_PLLCLKSTAB)) + break; + } + + clk_control_write_cr(cr0, cr0_val); + clk_control_write_cr(cr1, cr1_val); + clk_control_write_cr(dcr, dcr_val); + + /* Enable PLL */ + clk_control_write_cr(cr2, CLK_CONTROL_PLL_CR2_PLLENTRG); +} + +/** + * clk_control_set_pll() - Load configuration into PLLs + */ +static void clk_control_set_pll(void) +{ + /* Switch PLLs to internal oscillator and configure dividers. */ + clk_control_set_pll_freq(CLK_CONTROL_PLL01_0_CR0, CLK_CONTROL_PLL01_0_CR1, + CLK_CONTROL_PLL01_0_CR2, CLK_CONTROL_PLL01_0_SCR, + CLK_CONTROL_PLL01_0_DCR, 0x06500000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL01_1_CR0, CLK_CONTROL_PLL01_1_CR1, + CLK_CONTROL_PLL01_1_CR2, CLK_CONTROL_PLL01_1_SCR, + CLK_CONTROL_PLL01_1_DCR, 0x04c00000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL02_0_CR0, CLK_CONTROL_PLL02_0_CR1, + CLK_CONTROL_PLL02_0_CR2, CLK_CONTROL_PLL02_0_SCR, + CLK_CONTROL_PLL02_0_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_1_CR0, CLK_CONTROL_PLL02_1_CR1, + CLK_CONTROL_PLL02_1_CR2, CLK_CONTROL_PLL02_1_SCR, + CLK_CONTROL_PLL02_1_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_2_CR0, CLK_CONTROL_PLL02_2_CR1, + CLK_CONTROL_PLL02_2_CR2, CLK_CONTROL_PLL02_2_SCR, + CLK_CONTROL_PLL02_2_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_3_CR0, CLK_CONTROL_PLL02_3_CR1, + CLK_CONTROL_PLL02_3_CR2, CLK_CONTROL_PLL02_3_SCR, + CLK_CONTROL_PLL02_3_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_4_CR0, CLK_CONTROL_PLL02_4_CR1, + CLK_CONTROL_PLL02_4_CR2, CLK_CONTROL_PLL02_4_SCR, + CLK_CONTROL_PLL02_4_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_5_CR0, CLK_CONTROL_PLL02_5_CR1, + CLK_CONTROL_PLL02_5_CR2, CLK_CONTROL_PLL02_5_SCR, + CLK_CONTROL_PLL02_5_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_6_CR0, CLK_CONTROL_PLL02_6_CR1, + CLK_CONTROL_PLL02_6_CR2, CLK_CONTROL_PLL02_6_SCR, + CLK_CONTROL_PLL02_6_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_7_CR0, CLK_CONTROL_PLL02_7_CR1, + CLK_CONTROL_PLL02_7_CR2, CLK_CONTROL_PLL02_7_SCR, + CLK_CONTROL_PLL02_7_DCR, 0x08900000, 0x04000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL03_0_CR0, CLK_CONTROL_PLL03_0_CR1, + CLK_CONTROL_PLL03_0_CR2, CLK_CONTROL_PLL03_0_SCR, + CLK_CONTROL_PLL03_0_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_1_CR0, CLK_CONTROL_PLL03_1_CR1, + CLK_CONTROL_PLL03_1_CR2, CLK_CONTROL_PLL03_1_SCR, + CLK_CONTROL_PLL03_1_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_2_CR0, CLK_CONTROL_PLL03_2_CR1, + CLK_CONTROL_PLL03_2_CR2, CLK_CONTROL_PLL03_2_SCR, + CLK_CONTROL_PLL03_2_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_3_CR0, CLK_CONTROL_PLL03_3_CR1, + CLK_CONTROL_PLL03_3_CR2, CLK_CONTROL_PLL03_3_SCR, + CLK_CONTROL_PLL03_3_DCR, 0x05f00000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL06_CR0, CLK_CONTROL_PLL06_CR1, + CLK_CONTROL_PLL06_CR2, CLK_CONTROL_PLL06_SCR, + CLK_CONTROL_PLL06_DCR, 0x0a700000, 0x0c000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL07_CR0, CLK_CONTROL_PLL07_CR1, + CLK_CONTROL_PLL07_CR2, CLK_CONTROL_PLL07_SCR, + CLK_CONTROL_PLL07_DCR, 0x09500000, 0x08000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL12_CR0, CLK_CONTROL_PLL12_CR1, + CLK_CONTROL_PLL12_CR2, CLK_CONTROL_PLL12_SCR, + CLK_CONTROL_PLL12_DCR, 0x0a400000, 0x0c000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL13_CR0, CLK_CONTROL_PLL13_CR1, + CLK_CONTROL_PLL13_CR2, CLK_CONTROL_PLL13_SCR, + CLK_CONTROL_PLL13_DCR, 0x08f00000, 0x08000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL14_CR0, CLK_CONTROL_PLL14_CR1, + CLK_CONTROL_PLL14_CR2, CLK_CONTROL_PLL14_SCR, + CLK_CONTROL_PLL14_DCR, 0x04700000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL15_0_CR0, CLK_CONTROL_PLL15_0_CR1, + CLK_CONTROL_PLL15_0_CR2, CLK_CONTROL_PLL15_0_SCR, + CLK_CONTROL_PLL15_0_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_1_CR0, CLK_CONTROL_PLL15_1_CR1, + CLK_CONTROL_PLL15_1_CR2, CLK_CONTROL_PLL15_1_SCR, + CLK_CONTROL_PLL15_1_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_2_CR0, CLK_CONTROL_PLL15_2_CR1, + CLK_CONTROL_PLL15_2_CR2, CLK_CONTROL_PLL15_2_SCR, + CLK_CONTROL_PLL15_2_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_3_CR0, CLK_CONTROL_PLL15_3_CR1, + CLK_CONTROL_PLL15_3_CR2, CLK_CONTROL_PLL15_3_SCR, + CLK_CONTROL_PLL15_3_DCR, 0x07700000, 0x04000000, 0x18); + + /* Switch PLLs back and wait for them to stabilize. */ + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_0_CR2, CLK_CONTROL_PLL01_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_1_CR2, CLK_CONTROL_PLL01_1_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_0_CR2, CLK_CONTROL_PLL02_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_1_CR2, CLK_CONTROL_PLL02_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_2_CR2, CLK_CONTROL_PLL02_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_3_CR2, CLK_CONTROL_PLL02_3_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_4_CR2, CLK_CONTROL_PLL02_4_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_5_CR2, CLK_CONTROL_PLL02_5_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_6_CR2, CLK_CONTROL_PLL02_6_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_7_CR2, CLK_CONTROL_PLL02_7_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_0_CR2, CLK_CONTROL_PLL03_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_1_CR2, CLK_CONTROL_PLL03_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_2_CR2, CLK_CONTROL_PLL03_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_3_CR2, CLK_CONTROL_PLL03_3_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL06_CR2, CLK_CONTROL_PLL06_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL07_CR2, CLK_CONTROL_PLL07_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL12_CR2, CLK_CONTROL_PLL12_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL13_CR2, CLK_CONTROL_PLL13_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL14_CR2, CLK_CONTROL_PLL14_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_0_CR2, CLK_CONTROL_PLL15_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_1_CR2, CLK_CONTROL_PLL15_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_2_CR2, CLK_CONTROL_PLL15_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_3_CR2, CLK_CONTROL_PLL15_3_SCR); + + /* Write second-stage DCR */ + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_1_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_3_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_4_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_5_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_6_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_7_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_3_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL06_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL07_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL12_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL13_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL14_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_3_DCR, 0x10); + + udelay(25); + + /* Write third-stage DCR */ + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_1_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_3_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_4_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_5_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_6_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_7_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_3_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL06_DCR, 0x10); /* 1/2 */ + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL07_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL12_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL13_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL14_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_3_DCR, 0x00); + + udelay(25); +} + +#define MDLC_PERW_BASE 0xc05d0000 +#define MDLC_PERE_BASE 0xc08f0000 +#define MDLC_HSCN_BASE 0xc9c90000 +/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ +#define MDLC_RT_BASE 0xb9440000 +#define MDLC_SCP_BASE 0xc1330000 + +#define MDLC_SCP_MSRES02 (MDLC_SCP_BASE + 0x908) +#define MDLC_SCP_MSRESS02 (MDLC_SCP_BASE + 0x968) +#define MDLC_SCP_MSRES02_SCP_MASK GENMASK(1, 0) +#define MDLC_SCP_PKCPROT1 (MDLC_SCP_BASE + 0xcf4) + +#define MDLC_PERW_MSRES05 (MDLC_PERW_BASE + 0x914) +#define MDLC_PERW_MSRESS05 (MDLC_PERW_BASE + 0x974) +#define MDLC_PERW_MSRES05_HSCIF0_MASK GENMASK(9, 8) +#define MDLC_PERW_MSRES05_HSCIF1_MASK GENMASK(11, 10) +#define MDLC_MSRESS_STANDBY 0 +#define MDLC_MSRESS_RESET 1 +#define MDLC_MSRESS_STOP 2 +#define MDLC_MSRESS_RUN 3 +#define MDLC_PERW_PKCPROT1 (MDLC_PERW_BASE + 0xcf4) + +#define MDLC_MPG_GATING 0 +#define MDLC_MPG_RESET 1 +#define MDLC_MPG_RUN 3 + +#define MDLC_PERE_MPIER (MDLC_PERE_BASE + 0x110) +#define MDLC_PERE_MPIMR (MDLC_PERE_BASE + 0x120) +#define MDLC_PERE_MPDG00 (MDLC_PERE_BASE + 0x200) +#define MDLC_PERE_MPDG01 (MDLC_PERE_BASE + 0x204) +#define MDLC_PERE_MPDGS00 (MDLC_PERE_BASE + 0x300) +#define MDLC_PERE_MPDGS01 (MDLC_PERE_BASE + 0x304) +#define MDLC_PERE_MSRES06 (MDLC_PERE_BASE + 0x918) +#define MDLC_PERE_MSRESS06 (MDLC_PERE_BASE + 0x978) +#define MDLC_PERE_PKCPROT0 (MDLC_PERE_BASE + 0xcf0) +#define MDLC_PERE_PKCPROT1 (MDLC_PERE_BASE + 0xcf4) +#define MDLC_PERE_MSRES06_UFS0_MASK GENMASK(1, 0) +#define MDLC_PERE_MSRES06_UFS1_MASK GENMASK(3, 2) + +#define MDLC_HSCN_MPIER (MDLC_HSCN_BASE + 0x110) +#define MDLC_HSCN_MPIMR (MDLC_HSCN_BASE + 0x120) +#define MDLC_HSCN_MPDG00 (MDLC_HSCN_BASE + 0x200) +#define MDLC_HSCN_MPDG01 (MDLC_HSCN_BASE + 0x204) +#define MDLC_HSCN_MPDG02 (MDLC_HSCN_BASE + 0x208) +#define MDLC_HSCN_MPDG03 (MDLC_HSCN_BASE + 0x20c) +#define MDLC_HSCN_MPDG04 (MDLC_HSCN_BASE + 0x210) +#define MDLC_HSCN_MPDG05 (MDLC_HSCN_BASE + 0x214) +#define MDLC_HSCN_MPDG06 (MDLC_HSCN_BASE + 0x218) +#define MDLC_HSCN_MPDGS00 (MDLC_HSCN_BASE + 0x300) +#define MDLC_HSCN_MPDGS01 (MDLC_HSCN_BASE + 0x304) +#define MDLC_HSCN_MPDGS02 (MDLC_HSCN_BASE + 0x308) +#define MDLC_HSCN_MPDGS03 (MDLC_HSCN_BASE + 0x30c) +#define MDLC_HSCN_MPDGS04 (MDLC_HSCN_BASE + 0x310) +#define MDLC_HSCN_MPDGS05 (MDLC_HSCN_BASE + 0x314) +#define MDLC_HSCN_MPDGS06 (MDLC_HSCN_BASE + 0x318) +#define MDLC_HSCN_PKCPROT0 (MDLC_HSCN_BASE + 0xcf0) + +#define MDLC_RT_MPIER (MDLC_RT_BASE + 0x110) +#define MDLC_RT_MPIMR (MDLC_RT_BASE + 0x120) +#define MDLC_RT_MPDG00 (MDLC_RT_BASE + 0x200) +#define MDLC_RT_MPDG01 (MDLC_RT_BASE + 0x204) +#define MDLC_RT_MPDG02 (MDLC_RT_BASE + 0x208) +#define MDLC_RT_MPDG03 (MDLC_RT_BASE + 0x20c) +#define MDLC_RT_MPDG04 (MDLC_RT_BASE + 0x210) +#define MDLC_RT_MPDG05 (MDLC_RT_BASE + 0x214) +#define MDLC_RT_MPDG06 (MDLC_RT_BASE + 0x218) +#define MDLC_RT_MPDG07 (MDLC_RT_BASE + 0x21c) +#define MDLC_RT_MPDG08 (MDLC_RT_BASE + 0x220) +#define MDLC_RT_MPDG09 (MDLC_RT_BASE + 0x224) +#define MDLC_RT_MPDG10 (MDLC_RT_BASE + 0x228) +#define MDLC_RT_MPDG11 (MDLC_RT_BASE + 0x22c) +#define MDLC_RT_MPDGS00 (MDLC_RT_BASE + 0x300) +#define MDLC_RT_MPDGS01 (MDLC_RT_BASE + 0x304) +#define MDLC_RT_MPDGS02 (MDLC_RT_BASE + 0x308) +#define MDLC_RT_MPDGS03 (MDLC_RT_BASE + 0x30c) +#define MDLC_RT_MPDGS04 (MDLC_RT_BASE + 0x310) +#define MDLC_RT_MPDGS05 (MDLC_RT_BASE + 0x314) +#define MDLC_RT_MPDGS06 (MDLC_RT_BASE + 0x318) +#define MDLC_RT_MPDGS07 (MDLC_RT_BASE + 0x31c) +#define MDLC_RT_MPDGS08 (MDLC_RT_BASE + 0x320) +#define MDLC_RT_MPDGS09 (MDLC_RT_BASE + 0x324) +#define MDLC_RT_MPDGS10 (MDLC_RT_BASE + 0x328) +#define MDLC_RT_MPDGS11 (MDLC_RT_BASE + 0x32c) +#define MDLC_RT_MSRES02 (MDLC_RT_BASE + 0x908) +#define MDLC_RT_MSRESS02 (MDLC_RT_BASE + 0x968) +#define MDLC_RT_MSRES03 (MDLC_RT_BASE + 0x90c) +#define MDLC_RT_MSRESS03 (MDLC_RT_BASE + 0x96c) +#define MDLC_RT_MSRES15 (MDLC_RT_BASE + 0x93c) +#define MDLC_RT_MSRESS15 (MDLC_RT_BASE + 0x99c) +#define MDLC_RT_MSRES15_INTAP0_MASK GENMASK(9, 8) +#define MDLC_RT_MSRES15_INTTP_MASK GENMASK(11, 10) +#define MDLC_RT_MSRES15_INTAP1_MASK GENMASK(13, 12) +#define MDLC_RT_PKCPROT0 (MDLC_RT_BASE + 0xcf0) +#define MDLC_RT_PKCPROT1 (MDLC_RT_BASE + 0xcf4) + +/* + * mdlc_wait_for_reset() - Wait for MDLC reset register and reset status register to align + * @res: Reset register + * @stat: Reset status register + */ +static void mdlc_wait_for_reset(const u32 res, const u32 stat) +{ + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (; readl(res) != readl(stat);) + ; +} + +/** + * mdlc_write_msres() - Write MSRES register to release IP from reset + * @prot: Protect register + * @res: Reset register + * @val: Value to set in the masked out bits + */ +static void mdlc_write_msres(const u32 prot, const u32 res, const int val) +{ + writel(PKC_PROT_UNLOCK, prot); + writel(val, res); + writel(PKC_PROT_LOCK, prot); +} + +/** + * mdlc_rmw_msres() - Read-modify-write MSRES register to release IP from reset + * @prot: Protect register + * @res: Reset register + * @mask: Mask in the register to clear + * @val: Value to set in the masked out bits + */ +static void mdlc_rmw_msres(const u32 prot, const u32 res, const u32 mask, const int val) +{ + u32 reg; + + reg = readl(res); + reg &= ~mask; + reg |= field_prep(mask, val); + + mdlc_write_msres(prot, res, reg); +} + +/** + * mdlc_set_reset() - Set IP into reset + * @prot: Protect register + * @res: Reset register + * @stat: Reset register + * @mask: Mask in the register to clear + */ +static void mdlc_set_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) +{ + u32 status; + + mdlc_wait_for_reset(res, stat); + + status = field_get(mask, readl(stat)); + if (status == MDLC_MSRESS_STOP) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_STANDBY); + mdlc_wait_for_reset(res, stat); + status = field_get(mask, readl(stat)); + } + + if (status == MDLC_MSRESS_STANDBY || status == MDLC_MSRESS_RUN) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); + mdlc_wait_for_reset(res, stat); + } +} + +/** + * mdlc_release_reset() - Release IP from reset + * @prot: Protect register + * @res: Reset register + * @stat: Reset register + * @mask: Mask in the register to clear + */ +static void mdlc_release_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) +{ + u32 status; + + mdlc_wait_for_reset(res, stat); + + status = field_get(mask, readl(stat)); + if (status == MDLC_MSRESS_STANDBY) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); + mdlc_wait_for_reset(res, stat); + status = field_get(mask, readl(stat)); + } + + if (status == MDLC_MSRESS_RESET || status == MDLC_MSRESS_STOP) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RUN); + mdlc_wait_for_reset(res, stat); + } +} + +/** + * mldc_mpg_module_run() - Release MPG module from gating + * @prot: Protect register + * @res: Reset register + * @stat: Reset status register + * @ier: Interrupt enable register + * @imr: Interrupt mask register + */ +static void mldc_mpg_module_run(const u32 prot, const u32 res, const u32 stat, + const u32 ier, const u32 imr) +{ + u32 val; + + mdlc_wait_for_reset(res, stat); + + val = readl(stat); + if (val == MDLC_MPG_GATING) { + writel(0, ier); + writel(0, imr); + mdlc_write_msres(prot, res, MDLC_MPG_RESET); + mdlc_wait_for_reset(res, stat); + val = readl(stat); + } + + if (val == MDLC_MPG_RESET || val == MDLC_MPG_RUN) { + writel(0, ier); + writel(0, imr); + mdlc_write_msres(prot, res, MDLC_MPG_RUN); + mdlc_wait_for_reset(res, stat); + val = readl(stat); + } +} + +/** + * mdlc_mpg_start() - Configure MPG module state + */ +static void mdlc_mpg_start(void) +{ + mldc_mpg_module_run(MDLC_PERE_PKCPROT0, MDLC_PERE_MPDG01, MDLC_PERE_MPDGS01, + MDLC_PERE_MPIER, MDLC_PERE_MPIMR); + mldc_mpg_module_run(MDLC_PERE_PKCPROT0, MDLC_PERE_MPDG00, MDLC_PERE_MPDGS00, + MDLC_PERE_MPIER, MDLC_PERE_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG11, MDLC_RT_MPDGS11, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG10, MDLC_RT_MPDGS10, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG09, MDLC_RT_MPDGS09, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG08, MDLC_RT_MPDGS08, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG07, MDLC_RT_MPDGS07, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG06, MDLC_RT_MPDGS06, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG05, MDLC_RT_MPDGS05, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG04, MDLC_RT_MPDGS04, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG03, MDLC_RT_MPDGS03, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG02, MDLC_RT_MPDGS02, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG01, MDLC_RT_MPDGS01, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG00, MDLC_RT_MPDGS00, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + /* Power on RSwitch */ + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG06, MDLC_HSCN_MPDGS06, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG05, MDLC_HSCN_MPDGS05, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG04, MDLC_HSCN_MPDGS04, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG03, MDLC_HSCN_MPDGS03, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG02, MDLC_HSCN_MPDGS02, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG01, MDLC_HSCN_MPDGS01, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG00, MDLC_HSCN_MPDGS00, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); +} + +#define PFC_GP2_BASE 0xc1081000 +#define PFC_GP2_GPSR (PFC_GP2_BASE + 0x40) +#define PFC_GP2_IOINTSEL (PFC_GP2_BASE + 0x110) +#define PFC_GP2_INOUTSEL (PFC_GP2_BASE + 0x114) +#define PFC_GP2_OUTDT (PFC_GP2_BASE + 0x118) +#define PFC_GP2_POSNEG (PFC_GP2_BASE + 0x1a0) +#define PFC_GP2_PIN_AVS0 BIT(21) +#define PFC_GP2_PIN_AVS1 BIT(22) +#define PFC_GP2_PIN_AVS \ + (PFC_GP2_PIN_AVS0 | PFC_GP2_PIN_AVS1) + +#define PFC_GP3_BASE 0xc0800000 +#define PFC_GP3_PULLEN (PFC_GP3_BASE + 0xc0) +#define PFC_GP3_PUDSEL (PFC_GP3_BASE + 0xc4) + +#define PFC_GP5_BASE 0xc0400000 +#define PFC_GROUP_ADDR_MASK GENMASK(31, 11) +#define PFC_GP5_GPSR (PFC_GP5_BASE + 0x40) +#define PFC_GP5_ALTSEL0 (PFC_GP5_BASE + 0x60) +#define PFC_GP5_ALTSEL1 (PFC_GP5_BASE + 0x64) +#define PFC_GP5_ALTSEL2 (PFC_GP5_BASE + 0x68) +#define PFC_GP5_ALTSEL3 (PFC_GP5_BASE + 0x6c) +#define PFC_GP5_PIN_HTX0 BIT(0) +#define PFC_GP5_PIN_HRX0 BIT(1) +#define PFC_GP5_PIN_SCIF_CLK BIT(5) +#define PFC_GP5_PIN_HTX1 BIT(6) +#define PFC_GP5_PIN_HRX1 BIT(7) +#define PFC_GP5_PIN_HSCIF0_HSCIF1 \ + (PFC_GP5_PIN_HTX0 | PFC_GP5_PIN_HRX0 | \ + PFC_GP5_PIN_HTX1 | PFC_GP5_PIN_HRX1) +#define PFC_GP5_ALTSEL_HSCIF0_HSCIF1 \ + (PFC_GP5_PIN_HSCIF0_HSCIF1 | PFC_GP5_PIN_SCIF_CLK) + +/** + * pfc_rmw_reg() - Read-modify-write PFC register + * @reg: Register to write + * @mask: Mask in the register to clear + * @val: Value to set in the masked out bits + */ +static void pfc_rmw_reg(const u32 reg, const u32 mask, const u32 val) +{ + u32 pmmr = reg & PFC_GROUP_ADDR_MASK; + u32 tmp; + + tmp = readl(reg); + tmp &= ~mask; + tmp |= val; + + writel(~tmp, pmmr); + writel(tmp, reg); +} + +/** + * pfc_set_hscif0_hscif1_pinmux() - Set HSCIF0 and HSCIF1 pinmux + * @bd3250k: Set to TRUE if HSCIF configured for 3.25 MBdps + * + * This function configures both HSCIF0 and HSCIF1 pin multiplexing, + * HSCIF0 is used for follow up stages, HSCIF1 is used for IPL console. + */ +static void pfc_set_hscif0_hscif1_pinmux(bool bd3250k) +{ + u32 gpsr_mask = PFC_GP5_PIN_HSCIF0_HSCIF1; + + if (bd3250k) + gpsr_mask |= PFC_GP5_PIN_SCIF_CLK; + + pfc_rmw_reg(PFC_GP5_ALTSEL0, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL1, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL2, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL3, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_GPSR, gpsr_mask, gpsr_mask); +} + +/** + * pfc_set_avs_pinmux() - Set AVS pinmux + */ +static void pfc_set_avs_pinmux(void) +{ + clrbits_le32(PFC_GP2_POSNEG, PFC_GP2_PIN_AVS); + clrbits_le32(PFC_GP2_IOINTSEL, PFC_GP2_PIN_AVS); + setbits_le32(PFC_GP2_OUTDT, PFC_GP2_PIN_AVS); + setbits_le32(PFC_GP2_INOUTSEL, PFC_GP2_PIN_AVS); + pfc_rmw_reg(PFC_GP2_GPSR, PFC_GP2_PIN_AVS, 0); +} + +/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ +#define MFIS_BASE 0xb89e0000 +#define MFIS_WPCNTR (MFIS_BASE + 0x900) +#define MFIS_CODEVALUE 0xacce0000 + +/** + * mfis_unprotect() - Remove MFIS register write protection + */ +static void mfis_unprotect(void) +{ + writel(MFIS_CODEVALUE, MFIS_WPCNTR); +} + +/** + * rsip_irq_setup() - Configure RSIP interrupts + */ +static void rsip_irq_setup(void) +{ + asm volatile("cpsid i"); + + setbits_le32(RSIP_SHCSR, RSIP_SHCSR_USGFAULTENA | RSIP_SHCSR_BUSFAULTENA | + RSIP_SHCSR_MEMFAULTENA); + + writel(0xffffffff, RSIP_NVIC_ICER_00); + writel(0xffffffff, RSIP_NVIC_ICER_01); + writel(0xffffffff, RSIP_NVIC_ICER_02); + writel(0xffffffff, RSIP_NVIC_ICER_03); + writel(0xffffffff, RSIP_NVIC_ICER_04); + writel(0xffffffff, RSIP_NVIC_ICER_05); + writel(0xffffffff, RSIP_NVIC_ICER_06); + writel(0xffffffff, RSIP_NVIC_ICER_07); + writel(0xffffffff, RSIP_NVIC_ICER_08); + writel(0xffffffff, RSIP_NVIC_ICER_09); + writel(0xffffffff, RSIP_NVIC_ICER_10); + writel(0xffffffff, RSIP_NVIC_ICER_11); + writel(0xffffffff, RSIP_NVIC_ICER_12); + writel(0xffffffff, RSIP_NVIC_ICER_13); + writel(0xffffffff, RSIP_NVIC_ICER_14); + writel(0xffffffff, RSIP_NVIC_ICER_15); + + /* WDT IRQ */ + writel(RSIP_NVIC_ISER_00_SETENA_INTIWDTA0, RSIP_NVIC_ISER_00); + + asm volatile("cpsid i"); +} + +#define RPC_BASE 0xc08c0000 +#define RPC_CMNSR (RPC_BASE + 0x48) +#define RPC_PHYCNT (RPC_BASE + 0x7c) +#define RPC_CMNCR (RPC_BASE + 0x00) +#define RPC_SSLDR (RPC_BASE + 0x04) +#define RPC_DRCR (RPC_BASE + 0x0c) +#define RPC_DRCMR (RPC_BASE + 0x10) +#define RPC_DREAR (RPC_BASE + 0x14) +#define RPC_DROPR (RPC_BASE + 0x18) +#define RPC_DRENR (RPC_BASE + 0x1c) +#define RPC_SMCR (RPC_BASE + 0x20) +#define RPC_SMCMR (RPC_BASE + 0x24) +#define RPC_SMADR (RPC_BASE + 0x28) +#define RPC_SMENR (RPC_BASE + 0x30) +#define RPC_SMWDR0 (RPC_BASE + 0x40) +#define RPC_DRDMCR (RPC_BASE + 0x58) +#define RPC_DRDRENR (RPC_BASE + 0x5c) +#define RPC_PHYOFFSET1 (RPC_BASE + 0x80) +#define RPC_PHYINT (RPC_BASE + 0x88) +#define RPC_SEC_CONF (RPC_BASE + 0xb8) + +#define RPC_CMNSR_TEND BIT(0) + +#define RPC_CMNCR_MD BIT(31) +#define RPC_CMNCR_MOIIO3(n) FIELD_PREP(GENMASK(23, 22), (n)) +#define RPC_CMNCR_MOIIO2(n) FIELD_PREP(GENMASK(21, 20), (n)) +#define RPC_CMNCR_MOIIO1(n) FIELD_PREP(GENMASK(19, 18), (n)) +#define RPC_CMNCR_MOIIO0(n) FIELD_PREP(GENMASK(17, 16), (n)) +#define RPC_CMNCR_IO0FV(n) FIELD_PREP(GENMASK(9, 8), (n)) +#define RPC_CMNCR_BSZ(n) FIELD_PREP(GENMASK(1, 0), (n)) + +#define RPC_SSLDR_SPNDL_MASK GENMASK(18, 16) +#define RPC_SSLDR_SPNDL_SPCLK_2_CYCLES FIELD_PREP(RPC_SSLDR_SPNDL_MASK, 1) +#define RPC_SSLDR_SLNDL_MASK GENMASK(10, 8) +#define RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES FIELD_PREP(RPC_SSLDR_SLNDL_MASK, 4) +#define RPC_SSLDR_SCKDL_MASK GENMASK(2, 0) +#define RPC_SSLDR_SCKDL_SPCLK_2_CYCLES FIELD_PREP(RPC_SSLDR_SCKDL_MASK, 1) + +#define RPC_DRCR_SSLN BIT(24) +#define RPC_DRCR_RBURST_MASK GENMASK(20, 16) +#define RPC_DRCR_RCF_READ_CACHE_CLEARE BIT(9) +#define RPC_DRCR_RBE BIT(8) + +#define RPC_DRCMR_CMD_MASK GENMASK(23, 16) +#define RPC_DRCMR_CMD_HYPERFLASH_READ FIELD_PREP(RPC_DRCMR_CMD_MASK, 0xA0) + +#define RPC_DREAR_EAV_MASK GENMASK(23, 16) +#define RPC_DREAR_EAC_MASK GENMASK(2, 0) + +#define RPC_DRENR_DME BIT(15) +#define RPC_DRENR_CDE BIT(14) +#define RPC_DRENR_OCDE BIT(12) +#define RPC_DRENR_ADE_MASK GENMASK(11, 8) +#define RPC_DRENR_ADE_HYPERFLASH FIELD_PREP(RPC_DRENR_ADE_MASK, 4) +#define RPC_DRENR_OPDE_MASK GENMASK(7, 4) + +#define RPC_DRDMCR_DMCYC_MASK GENMASK(4, 0) +#define RPC_DRDMCR_DMCYC_15_CYCLE FIELD_PREP(RPC_DRDMCR_DMCYC_MASK, 0xe) + +#define RPC_DRDRENR_HYPE_MASK GENMASK(14, 12) +#define RPC_DRDRENR_HYPE_HYPERFLASH FIELD_PREP(RPC_DRDRENR_HYPE_MASK, 5) +#define RPC_DRDRENR_ADDRE BIT(8) +#define RPC_DRDRENR_OPDRE BIT(4) +#define RPC_DRDRENR_DRDRE BIT(0) + +#define RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK 0x08038000 + +#define RPC_PHYCNT_HS BIT(18) +#define RPC_PHYCNT_PHYMEM_MASK GENMASK(1, 0) +#define RPC_PHYCNT_PHYMEM_HYPERFLASH FIELD_PREP(RPC_PHYCNT_PHYMEM_MASK, 3) + +/** + * rpc_safe_setup() - Configure RPC with safe static settings + */ +static void rpc_safe_setup(void) +{ + writel(RPC_CMNCR_MOIIO3(2) | RPC_CMNCR_MOIIO2(2) | RPC_CMNCR_MOIIO1(2) | + RPC_CMNCR_MOIIO0(2) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(1) | + 0x01007000, RPC_CMNCR); + writel(RPC_SSLDR_SPNDL_SPCLK_2_CYCLES | RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES | + RPC_SSLDR_SCKDL_SPCLK_2_CYCLES, RPC_SSLDR); + writel(RPC_DRCR_RBURST_MASK | RPC_DRCR_RBE, RPC_DRCR); + writel(RPC_DRCMR_CMD_HYPERFLASH_READ, RPC_DRCMR); + writel(0, RPC_DREAR); + writel(RPC_DRENR_ADE_HYPERFLASH | 0xa222d000, RPC_DRENR); + writel(0, RPC_SMCR); + writel(0, RPC_SMCMR); + writel(0, RPC_SMADR); + writel(BIT(14), RPC_SMENR); + writel(0, RPC_SMWDR0); + writel(RPC_CMNSR_TEND, RPC_CMNSR); + writel(RPC_DRDMCR_DMCYC_15_CYCLE, RPC_DRDMCR); + writel(RPC_DRDRENR_HYPE_HYPERFLASH | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE, + RPC_DRDRENR); + writel(0x08078263, RPC_PHYCNT); + writel(0x21511144, RPC_PHYOFFSET1); + writel(0x07070002, RPC_PHYINT); + writel(0x00000155, RPC_SEC_CONF); + writel(0x11, CLK_CONTROL_RPCCKCR); + writel(0x10100, PFC_GP3_PULLEN); + writel(0x10100, PFC_GP3_PUDSEL); +} + +/** + * rpc_boot_setup() - Configure RPC after boot from HF + */ +static void rpc_boot_setup(void) +{ + clrsetbits_le32(RPC_PHYCNT, + RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK | RPC_PHYCNT_HS | + RPC_PHYCNT_PHYMEM_MASK, + RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK | + RPC_PHYCNT_HS | RPC_PHYCNT_PHYMEM_HYPERFLASH); + + clrsetbits_le32(RPC_CMNCR, + RPC_CMNCR_MD | + RPC_CMNCR_MOIIO3(3) | RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO1(3) | + RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(3), + RPC_CMNCR_MOIIO3(2) | RPC_CMNCR_MOIIO2(2) | RPC_CMNCR_MOIIO1(2) | + RPC_CMNCR_MOIIO0(2) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(1)); + + clrsetbits_le32(RPC_SSLDR, + RPC_SSLDR_SPNDL_MASK | RPC_SSLDR_SLNDL_MASK | RPC_SSLDR_SCKDL_MASK, + RPC_SSLDR_SPNDL_SPCLK_2_CYCLES | RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES | + RPC_SSLDR_SCKDL_SPCLK_2_CYCLES); + + clrsetbits_le32(RPC_DRCR, + RPC_DRCR_SSLN | RPC_DRCR_RBURST_MASK | RPC_DRCR_RBE, + RPC_DRCR_SSLN | RPC_DRCR_RBURST_MASK | + RPC_DRCR_RCF_READ_CACHE_CLEARE | RPC_DRCR_RBE); + readl(RPC_DRCR); /* Dummy readback */ + + clrsetbits_le32(RPC_DRCMR, RPC_DRCMR_CMD_MASK, RPC_DRCMR_CMD_HYPERFLASH_READ); + + clrbits_le32(RPC_DREAR, RPC_DREAR_EAV_MASK | RPC_DREAR_EAC_MASK); + + writel(0, RPC_DROPR); + + clrsetbits_le32(RPC_DRENR, + RPC_DRENR_DME | RPC_DRENR_CDE | RPC_DRENR_OCDE | + RPC_DRENR_ADE_MASK | RPC_DRENR_OPDE_MASK, + RPC_DRENR_DME | RPC_DRENR_CDE | RPC_DRENR_OCDE | + RPC_DRENR_ADE_HYPERFLASH); + + clrsetbits_le32(RPC_DRDMCR, RPC_DRDMCR_DMCYC_MASK, RPC_DRDMCR_DMCYC_15_CYCLE); + + clrsetbits_le32(RPC_DRDRENR, + RPC_DRDRENR_HYPE_MASK | RPC_DRDRENR_ADDRE | + RPC_DRDRENR_OPDRE | RPC_DRDRENR_DRDRE, + RPC_DRDRENR_HYPE_HYPERFLASH | RPC_DRDRENR_ADDRE | + RPC_DRDRENR_DRDRE); +} + +/** + * rpc_setup() - Configure RPC + */ +static void rpc_setup(void) +{ + const u32 boot = field_get(SYSSS_MODE1_BOOTMODE_MASK, sysss_read_modemr()); + + if (boot != SYSSS_MODE1_BOOTMODE_HF_DMA) { + /* Not booted from HF, this may be SCIF loader, use safe setup. */ + rpc_safe_setup(); + return; + } + + /* Wait for any outstanding transfer to end. */ + /* This can not use readl_poll_timeout(), timer is not available yet. */ + while (!(readl(RPC_CMNSR) & RPC_CMNSR_TEND)) + ; + + /* Tristate IO */ + setbits_le32(RPC_CMNCR, RPC_CMNCR_MOIIO3(3) | RPC_CMNCR_MOIIO2(3) | + RPC_CMNCR_MOIIO1(3) | RPC_CMNCR_MOIIO0(3)); + + /* Set 160 MHz RPC HF clock */ + clrsetbits_le32(CLK_CONTROL_RPCCKCR, + CLK_CONTROL_RPCCKCR_CKSTP1 | CLK_CONTROL_RPCCKCR_RPCFC_MASK, + 0x11); + + rpc_boot_setup(); +} + +#define AXMM10_ADSPLCR0_CTRL 0xe9a07100 +#define AXMM10_ADSPLCR1_CTRL 0xe9a07104 +#define AXMM11_ADSPLCR0_CTRL 0xe9a07150 +#define AXMM11_ADSPLCR1_CTRL 0xe9a07154 + +/** + * axi_qos_init() - Configure AXI bus QoS + */ +static void axi_qos_init(void) +{ + writel(0x00011d0c, AXMM10_ADSPLCR0_CTRL); + writel(0x0000ffff, AXMM10_ADSPLCR1_CTRL); + writel(0x00011d0c, AXMM11_ADSPLCR0_CTRL); + writel(0x0000ffff, AXMM11_ADSPLCR1_CTRL); + dsb(); +} + +/** + * load_perm_table() - Load shared table into SRAM and hardware + * @dstaddr: SRAM destination address + * @dstsize: SRAM destination area size + * @listtable: Table of registers to write at offset 2i + * @listsize: Size of table of registers + * @listval: Value to write at offset 2i+1 + */ +static void load_perm_table(const u32 dstaddr, const u32 dstsize, + const u32 *listtable, const u32 listsize, + const u32 listval) +{ + /* + * The addresses in range 0x08000000..0x1fffffff are + * incremented by 0xa0000000 . + */ + u32 *dmabuf = (u32 *)(dstaddr + 0xa0000000); + u32 reg, rv; + int i; + + /* Place shared bus access permissions configuration table into SRAM */ + for (i = 0; i < dstsize / (2 * sizeof(u32)); i++) { + if (i >= listsize) { + dmabuf[2 * i] = 0; + dmabuf[(2 * i) + 1] = 0; + continue; + } + + dmabuf[2 * i] = listtable[i]; + dmabuf[(2 * i) + 1] = listval; + + /* + * The addresses in range 0x08000000..0x1fffffff are + * incremented by 0xa0000000 . + */ + reg = listtable[i]; + if (reg > 0x08000000 && reg < 0x20000000) + reg += 0xa0000000; + writel(listval, reg); + } + + /* Validate hardware write. */ + for (i = 0; i < listsize; i++) { + reg = listtable[i]; + if (reg > 0x08000000 && reg < 0x20000000) + reg += 0xa0000000; + rv = readl(reg); + if (rv == listval) + continue; + printf("RG[%d] = 0x%x / expected 0x%x\n", i, rv, listval); + } +} + +/** + * load_perm_tables() - Load shared tables into SRAM and hardware + */ +static void load_perm_tables(void) +{ + load_perm_table(RGIDM_SHARED_ADDR, RGIDM_SHARED_SIZE, + rgidm_register_list, ARRAY_SIZE(rgidm_register_list), 0); + load_perm_table(SEC_MODID_SHARED_ADDR, SEC_MODID_SHARED_SIZE, + sec_modid_register_list, ARRAY_SIZE(sec_modid_register_list), 0xffff); + load_perm_table(RGIDR_SHARED_ADDR, RGIDR_SHARED_SIZE, + rgidr_register_list, ARRAY_SIZE(rgidr_register_list), 1); + load_perm_table(RGIDW_SHARED_ADDR, RGIDW_SHARED_SIZE, + rgidw_register_list, ARRAY_SIZE(rgidw_register_list), 1); + + /* Override Region ID secure group settings */ + writel(0xffffffff, 0xc0983820); + writel(0xffffffff, 0xc0983828); + + writel(0xffffffff, 0xec603828); + writel(0xffffffff, 0xec60382c); + writel(0xffffffff, 0xec603830); + writel(0xffffffff, 0xec603834); + writel(0xffffffff, 0xec603838); + writel(0xffffffff, 0xec60383c); + + writel(0xffffffff, 0xc9d03880); + writel(0xffffffff, 0xc9d03884); + + /* + * The addresses in range 0x08000000..0x1fffffff + * are incremented by 0xa0000000 + */ + writel(0xffffffff, 0xba80383c); + writel(0xffffffff, 0xba803840); + writel(0xffffffff, 0xba803848); + writel(0xffffffff, 0xba80384c); + writel(0xffffffff, 0xba803974); + + writel(0xffffffff, 0xde803804); + writel(0xffffffff, 0xde803808); + writel(0xffffffff, 0xde803810); + writel(0xffffffff, 0xde803814); + writel(0xffffffff, 0xde803838); + writel(0xffffffff, 0xde80383c); + writel(0xffffffff, 0xde803840); + writel(0xffffffff, 0xde803844); + + writel(0xffffffff, 0xc1283808); + + writel(0xffffffff, 0xe9a08000); + writel(0xffffffff, 0xe9a081fc); + writel(0xffffffff, 0xe9a08200); + writel(0xffffffff, 0xe9a081fc); +} + +#define SCP_STCM_BASE 0xc1000000 +#define SCP_BASE 0xc1340000 +#define SCP_CFGVECTABLE (SCP_BASE + 0x0) +#define SCP_CFGNSSTCALIB (SCP_BASE + 0x10) +#define SCP_CPUWAIT (SCP_BASE + 0x30) +#define SCP_CFGNSSTCALIB_13_3MHZ 0x010040f0 +#define SCP_CPUWAIT_WAIT BIT(0) + +/** + * scp_initialize() - Initialize SCP + * + * Put SCP into reset, configure SCP entry point address and systick timer, + * release SCP from reset, and zero out SCP STCM regions. + */ +static void scp_initialize(void) +{ + u32 addr; + + mdlc_set_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, + MDLC_SCP_MSRES02_SCP_MASK); + + writel(SCP_STCM_BASE, SCP_CFGVECTABLE); + writel(SCP_CFGNSSTCALIB_13_3MHZ, SCP_CFGNSSTCALIB); + setbits_le32(SCP_CPUWAIT, SCP_CPUWAIT_WAIT); + + mdlc_release_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, + MDLC_SCP_MSRES02_SCP_MASK); + + /* Fill zero to SCP STCM regions 0 ... 27 */ + for (addr = SCP_STCM_BASE; addr < 0xc1061b00; addr += 8) + writeq(0, addr); + + asm volatile("dsb sy"); +} + +#define GIC720AE_GICR_PWRR(cpu) \ + (GICR_BASE + 0x24 + ((cpu) * 0x40000)) + +#define GIC720AE_GICD_IVIEWR(num) \ + (GICD_BASE + 0xf600 + ((num) * 0x4)) +#define GIC720AE_GICD_IVIEWRE(num) \ + (GICD_BASE + 0xf800 + ((num) * 0x4)) +#define GIC720AE_GICR_TYPER(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x8) +#define GIC720AE_GICR_VIEWR(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x2c) +#define GIC720AE_GICR_MPIDR(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x100) +#define GIC720AE_GICR_TYPER_AFF_MASK GENMASK_ULL(63, 32) + +#define CA_CORE_MAX 32 + +/** + * gic720ae_init() - GIC720AE initialization + */ +static void gic720ae_init(void) +{ + u64 val; + int i; + + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTAP0_MASK); + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTTP_MASK); + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTAP1_MASK); + + for (i = 0; i < CA_CORE_MAX; i++) + writel(BIT(1), GIC720AE_GICR_PWRR(i)); + + for (i = 0; i < CA_CORE_MAX; i++) { + val = readq(GIC720AE_GICR_TYPER(i)) & GIC720AE_GICR_TYPER_AFF_MASK; + writel((u32)(val >> 32U), GIC720AE_GICR_MPIDR(i)); + } + + writel(0x3f, GICD_BASE); /* CTRL register */ + + for (i = 2; i <= 61; i++) /* From IVIEWR min..max */ + writel(0x55555555, GIC720AE_GICD_IVIEWR(i)); + + for (i = 0; i <= 63; i++) /* From IVIEWRE min..max */ + writel(0x55555555, GIC720AE_GICD_IVIEWRE(i)); + + for (i = 0; i < CA_CORE_MAX; i++) + writel(1, GIC720AE_GICR_VIEWR(i)); /* View 1 */ +} + +/** + * mach_cpu_init() - Initialize hardware and start other cores + */ +int mach_cpu_init(void) +{ + mfis_unprotect(); + pfc_set_avs_pinmux(); + mdlc_mpg_start(); + clk_control_set_pll(); + rsip_irq_setup(); + rpc_setup(); + axi_qos_init(); + load_perm_tables(); + gic720ae_init(); + + /* Release SCP from reset */ + scp_initialize(); + + return 0; +} + +/** + * board_debug_uart_init() - Initialize all HSCIF + */ +void board_debug_uart_init(void) +{ + const u32 baud = field_get(SYSSS_MODE1_BAUDRATE_MASK, sysss_read_modemr()); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_0_CR2, + CLK_CONTROL_PLL01_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_1_CR2, + CLK_CONTROL_PLL01_1_SCR); + + mdlc_release_reset(MDLC_PERW_PKCPROT1, MDLC_PERW_MSRES05, MDLC_PERW_MSRESS05, + MDLC_PERW_MSRES05_HSCIF0_MASK); + mdlc_release_reset(MDLC_PERW_PKCPROT1, MDLC_PERW_MSRES05, MDLC_PERW_MSRESS05, + MDLC_PERW_MSRES05_HSCIF1_MASK); + + pfc_set_hscif0_hscif1_pinmux(baud == SYSSS_MODE1_BAUDRATE_3250000); +} + +/** + * board_init() - Board specific initialization + */ +int board_init(void) +{ + /* Allow WDT reset */ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK); + + return 0; +} + +/** + * arm_reserve_mmu() - Reserve space for MMU tables + */ +int arm_reserve_mmu(void) +{ + /* Reserve space for MMU tables just above stack in STCM */ + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = CONFIG_CUSTOM_SYS_INIT_SP_ADDR; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + return 0; +} + +/** + * reset_cpu() - Reset this CPU core + */ +void __weak reset_cpu(void) +{ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + writel(0x1, RST_SWSRES1A); +} diff --git a/board/renesas/common/gen5-cm33.h b/board/renesas/common/gen5-cm33.h new file mode 100644 index 00000000000..2dfb0b06cf7 --- /dev/null +++ b/board/renesas/common/gen5-cm33.h @@ -0,0 +1,2001 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +#ifndef __GEN5_CM33_H__ +#define __GEN5_CM33_H__ + +#define RGIDM_SHARED_ADDR 0x1001c000 +#define RGIDM_SHARED_SIZE 0x1000 +#define SEC_MODID_SHARED_ADDR 0x1001d000 +#define SEC_MODID_SHARED_SIZE 0x3000 +#define RGIDR_SHARED_ADDR 0x10020000 +#define RGIDR_SHARED_SIZE 0x8000 +#define RGIDW_SHARED_ADDR 0x10028000 +#define RGIDW_SHARED_SIZE 0x8000 + +static const u32 rgidm_register_list[] = { + 0xec601000, 0xcbf01000, 0xcbf01004, 0xcbf01008, + 0xcbf0100c, 0xcbf01010, 0xcbf01014, 0xcbf01018, + 0xcbf0101c, 0xcbf01020, 0xcbf01024, 0xcbf01028, + 0xcbf0102c, 0xcbf01030, 0xcbf01034, 0xcbf01038, + 0xcbf0103c, 0xcbf01040, 0xcbf01044, 0xcbf01048, + 0xcbf0104c, 0xcbf01050, 0xcbf01054, 0xcbf01058, + 0xcbf0105c, 0xcbf01060, 0xcbf01064, 0xcbf01068, + 0xcbf0106c, 0xcbf01070, 0xcbf01074, 0xcbf01078, + 0xcbf0107c, 0xcbf01080, 0xc9d01000, 0xc9d01004, + 0xc9d01008, 0xc9d0100c, 0xc9d01010, 0xc9d01014, + 0xc9d01018, 0xc9d0101c, 0xc9d01020, 0xc9d01024, + 0xc9d01028, 0xc9d0102c, 0xc9d01030, 0xc9d01034, + 0xc9d01038, 0xc9d0103c, 0xc9d01040, 0xde801000, + 0xde801004, 0xc1a01000, 0xc1a01004, 0xc1a01008, + 0xc1a0100c, 0xc1a01010, 0xc1a01014, 0xc1a01018, + 0xc1a0101c, 0xc1a01020, 0xc1a01024, 0xc1e01000, + 0xc1e01004, 0xc1e01008, 0xc1e0100c, 0xc1e01010, + 0xc1e01014, 0xc1e01018, 0xc1e0101c, 0xc1e01020, + 0xc1e01024, 0xe9a01000, 0xe9a01004, 0xe9a01008, + 0xe9a0100c, 0xd2f01000, 0xd2f01004, 0xd2f01008, + 0xd2f0100c, 0xd2f01010, 0xd2f01014, 0xd2f01018, + 0xd2f0101c, 0xd2f01020, 0xd2f01024, 0xd2f01028, + 0xd2f0102c, 0xd2f01030, 0xd2f01034, 0xd2f01038, + 0xd6f01000, 0xd6f01004, 0xd6f01008, 0xd6f0100c, + 0xd6f01010, 0xd6f01014, 0xd6f01018, 0xd6f0101c, + 0xd6f01020, 0xd6f01024, 0xd6f01028, 0xd6f0102c, + 0xd6f01030, 0xd6f01034, 0xd6f01038, 0xc0981000, + 0xc0981004, 0xc0981008, 0xc098100c, 0xc0581000, + 0xcb401000, 0xcb401004, 0xcb401008, 0xcb40100c, + 0xcb401010, 0xcb401014, 0x1a801000, 0x1a801004, + 0x1a801008, 0x1a80100c, 0x1a801010, 0x1a801014, + 0x1a801018, 0x1a80101c, 0x1a801020, 0x1a801024, + 0x1a801028, 0x1a80102c, 0x1a801030, 0x1a801034, + 0x1a801038, 0x1a80103c, 0x1a801040, 0x1a801044, + 0x1a801048, 0x1a80104c, 0x1a801050, 0x1a801054, + 0x1a801058, 0x1a80105c, 0x1a801060, 0x1a801064, + 0x1a801068, 0x1a80106c, 0x1a801070, 0x1a801074, + 0x1a801078, 0x1a80107c, 0x1a801080, 0x1a801084, + 0x1a801088, 0x1a80108c, 0x1a801090, 0x1a801094, + 0x18b41000, 0x18b41004, 0x18b41008, 0x18b4100c, + 0xc1281000, 0xc1281004, 0xc1281008, 0xc128100c, + 0xc1281010, 0xc1281014, 0xc5801000, 0xc5801004, + 0xc5801008, 0xc580100c, 0xc5801010, 0xc5801014, + 0xc5801018, 0xc580101c, 0xc5801020, 0xc5801024, + 0xc5801028, 0xc580102c, 0xc5801030, 0xc5801034, + 0xc5801038, 0xc580103c, 0xc5801040, 0xc5801044, + 0xc5801048, 0xc580104c, 0xc5801050, 0xc5801054, + 0xc5801058, 0xc580105c, 0xc5801060, 0xc5801064, + 0xc5801068, 0xc580106c, 0xc5801070, 0xc5801074, + 0xc5801078, 0xc580107c, 0xc5801080, 0xc5801084, + 0xc5801088, 0xc580108c, 0xc5801090, 0xc5801094, + 0xc5801098, 0xc580109c, 0xc58010a0, 0xc58010a4, + 0xc58010a8, 0xc58010ac, 0xc58010b0, 0xc58010b4, + 0xc58010b8, 0xc58010bc, 0xc58010c0, 0xc58010c4, + 0xc58010c8, 0xc58010cc, 0xc58010d0, 0xc58010d4, + 0xc58010d8, 0xc58010dc, 0xc58010e0, 0xc3021000, + 0xc3021004, 0xc3021008, 0xc302100c, 0xc3021010, + 0xc3021014, 0xc3421000, 0xc3421004, 0xc3421008, + 0xc342100c, 0xc3421010, 0xc3421014 +}; + +static const u32 rgidr_register_list[] = { + 0xe8022000, 0xe8022004, 0xe8022008, 0xe802200c, + 0xe8022010, 0xe8022014, 0xe8022018, 0xe802201c, + 0xe8022020, 0xe8022024, 0xe8022028, 0xe802202c, + 0xe8022030, 0xe8022034, 0xe8022038, 0xe802203c, + 0xe8022040, 0xe8022044, 0xe8022048, 0xe802204c, + 0xe80a2000, 0xe80a2004, 0xe80a2008, 0xe80a200c, + 0xe80a2010, 0xe80a2014, 0xe80a2018, 0xe80a201c, + 0xe80a2020, 0xe80a2024, 0xe80a2028, 0xe80a202c, + 0xe80a2030, 0xe80a2034, 0xe80a2038, 0xe80a203c, + 0xe80a2040, 0xe80a2044, 0xe80a2048, 0xe80a204c, + 0xe8122000, 0xe8122004, 0xe8122008, 0xe812200c, + 0xe8122010, 0xe8122014, 0xe8122018, 0xe812201c, + 0xe8122020, 0xe8122024, 0xe8122028, 0xe812202c, + 0xe8122030, 0xe8122034, 0xe8122038, 0xe812203c, + 0xe8122040, 0xe8122044, 0xe8122048, 0xe812204c, + 0xe81a2000, 0xe81a2004, 0xe81a2008, 0xe81a200c, + 0xe81a2010, 0xe81a2014, 0xe81a2018, 0xe81a201c, + 0xe81a2020, 0xe81a2024, 0xe81a2028, 0xe81a202c, + 0xe81a2030, 0xe81a2034, 0xe81a2038, 0xe81a203c, + 0xe81a2040, 0xe81a2044, 0xe81a2048, 0xe81a204c, + 0xe8222000, 0xe8222004, 0xe8222008, 0xe822200c, + 0xe8222010, 0xe8222014, 0xe8222018, 0xe822201c, + 0xe8222020, 0xe8222024, 0xe8222028, 0xe822202c, + 0xe8222030, 0xe8222034, 0xe8222038, 0xe822203c, + 0xe8222040, 0xe8222044, 0xe8222048, 0xe822204c, + 0xe82a2000, 0xe82a2004, 0xe82a2008, 0xe82a200c, + 0xe82a2010, 0xe82a2014, 0xe82a2018, 0xe82a201c, + 0xe82a2020, 0xe82a2024, 0xe82a2028, 0xe82a202c, + 0xe82a2030, 0xe82a2034, 0xe82a2038, 0xe82a203c, + 0xe82a2040, 0xe82a2044, 0xe82a2048, 0xe82a204c, + 0xe8322000, 0xe8322004, 0xe8322008, 0xe832200c, + 0xe8322010, 0xe8322014, 0xe8322018, 0xe832201c, + 0xe8322020, 0xe8322024, 0xe8322028, 0xe832202c, + 0xe8322030, 0xe8322034, 0xe8322038, 0xe832203c, + 0xe8322040, 0xe8322044, 0xe8322048, 0xe832204c, + 0xe83a2000, 0xe83a2004, 0xe83a2008, 0xe83a200c, + 0xe83a2010, 0xe83a2014, 0xe83a2018, 0xe83a201c, + 0xe83a2020, 0xe83a2024, 0xe83a2028, 0xe83a202c, + 0xe83a2030, 0xe83a2034, 0xe83a2038, 0xe83a203c, + 0xe83a2040, 0xe83a2044, 0xe83a2048, 0xe83a204c, + 0xc0622000, 0xc0622004, 0xc0622008, 0xc062200c, + 0xc0622010, 0xc0622014, 0xc0622018, 0xc062201c, + 0xc0622020, 0xc0622024, 0xc0622028, 0xc062202c, + 0xc0622030, 0xc0622034, 0xc0622038, 0xc062203c, + 0xc0622040, 0xc0622044, 0xc0622048, 0xc062204c, + 0xc0622050, 0xc0622054, 0xc0762000, 0xc0762004, + 0xc0762008, 0xc076200c, 0xc0762010, 0xc0762014, + 0xc0762018, 0xc076201c, 0xc0762020, 0xc0762024, + 0xc0762028, 0xc076202c, 0xc0762030, 0xc0762034, + 0xc0762038, 0xc076203c, 0xc0762040, 0xc0762044, + 0xc0762048, 0xc076204c, 0xc0762050, 0xc0762054, + 0xc0762058, 0xc076205c, 0xc0762060, 0xc0762064, + 0xc0762068, 0xc076206c, 0xc0762070, 0xc0762074, + 0xc0762078, 0xc076207c, 0xc0762080, 0xc0762084, + 0xc0762088, 0xc076208c, 0xc0762090, 0xc0762094, + 0xc0762098, 0xc076209c, 0xc07620a0, 0xc07620a4, + 0xc07620a8, 0xc07620ac, 0xc07620b0, 0xc07620b4, + 0xc07620b8, 0xc07620bc, 0xc07620c0, 0xc07620c4, + 0xc07620c8, 0xc07620cc, 0xc07620d0, 0xc07620d4, + 0xc07620d8, 0xc07620dc, 0xc07a2000, 0xc07a2004, + 0xc07a2008, 0xc07a200c, 0xc07a2010, 0xc07a2014, + 0xc07a2018, 0xc07a201c, 0xc07a2020, 0xc07a2024, + 0xc07a2028, 0xc07a202c, 0xc07a2030, 0xc07a2034, + 0xc07a2038, 0xc07a203c, 0xc07a2040, 0xc07a2044, + 0xc07a2048, 0xc07a204c, 0xc07a2050, 0xc07a2054, + 0xc07a2058, 0x1d002000, 0x1d002004, 0x1d002008, + 0x1d00200c, 0x1d002010, 0x1d002014, 0x1d002018, + 0x1d00201c, 0x1d002020, 0x1d002024, 0x1d002028, + 0x1d00202c, 0x1d002030, 0x1d002034, 0x1d002038, + 0x1d00203c, 0x1d002040, 0x1d002044, 0x1d002048, + 0x1d00204c, 0x1d002050, 0x1d002054, 0x1d002058, + 0x1d00205c, 0x1d002060, 0x1d002064, 0x1d002068, + 0x1d00206c, 0x1d002070, 0x1d002074, 0x1d002078, + 0x1d00207c, 0x1d002080, 0x1d002084, 0x1d002088, + 0x1d00208c, 0x1d002090, 0x1d002094, 0x1d002098, + 0x1d00209c, 0x1d0020a0, 0x1d0020a4, 0x1d0020a8, + 0x1d0020ac, 0x1d0020b0, 0x1d0020b4, 0x1d0020b8, + 0xc6702000, 0xc6702004, 0xc6702008, 0xc670200c, + 0xc6702010, 0xc6702014, 0xc6702018, 0xc670201c, + 0xc6702020, 0xc6702024, 0xc6702028, 0xc670202c, + 0xc6702030, 0xc6702034, 0xc6702038, 0xc670203c, + 0xc6702040, 0xc6702044, 0xc6702048, 0xc670204c, + 0xc6702050, 0xc6702054, 0xc6702058, 0xc670205c, + 0xc6702060, 0xc6702064, 0xc6702068, 0xc670206c, + 0xc6702070, 0xc6702074, 0xc6702078, 0xc670207c, + 0xc6702080, 0xc6702084, 0xc6702088, 0xc670208c, + 0xc6702090, 0xc6702094, 0xc6702098, 0xc670209c, + 0xc67020a0, 0xc67020a4, 0xc67020a8, 0xc1742000, + 0xc1742004, 0xc1742008, 0xc174200c, 0xc1742010, + 0xc1742014, 0xc1742018, 0xc174201c, 0xc1742020, + 0xc1742024, 0xc1742028, 0xc174202c, 0xc1742030, + 0xc1742034, 0xc1742038, 0xc174203c, 0xc1742040, + 0xc1742044, 0xc1742048, 0xc174204c, 0xc1742050, + 0xc1742054, 0xec602000, 0xec602004, 0xec602008, + 0xec60200c, 0xec602010, 0xec602014, 0xec602018, + 0xec60201c, 0xec602020, 0xec602024, 0xec602028, + 0xec60202c, 0xec602030, 0xec602034, 0xec602038, + 0xec60203c, 0xec602040, 0xec602044, 0xec602048, + 0xec60204c, 0xec602050, 0xec602054, 0xec602058, + 0xec60205c, 0xec602060, 0xec602064, 0xec602068, + 0xec60206c, 0xec602070, 0xec602074, 0xec602078, + 0xec60207c, 0xec602080, 0xec602084, 0xec602088, + 0xec60208c, 0xec602090, 0xec602094, 0xec602098, + 0xec60209c, 0xec6020a0, 0xec6020a4, 0xec6020a8, + 0xec6020ac, 0xec6020b0, 0xec6020b4, 0xec6020b8, + 0xec6020bc, 0xec6020c0, 0xec6020c4, 0xec6020c8, + 0xec6020cc, 0xec6020d0, 0xec6020d4, 0xec6020d8, + 0xec6020dc, 0xec6020e0, 0xec6020e4, 0xec6020e8, + 0xec6020ec, 0xec6020f0, 0xec6020f4, 0xec6020f8, + 0xec6020fc, 0xec602100, 0xec602104, 0xec602108, + 0xec60210c, 0xec602110, 0xec602114, 0xec602118, + 0xec60211c, 0xec602120, 0xec602124, 0xec602128, + 0xec60212c, 0xec602130, 0xec602134, 0xec602138, + 0xec60213c, 0xec602140, 0xec602144, 0xec602148, + 0xec60214c, 0xec602150, 0xec602154, 0xec602158, + 0xec60215c, 0xec602160, 0xec602164, 0xec602168, + 0xec60216c, 0xec602170, 0xec602174, 0xec602178, + 0xec60217c, 0xec602180, 0xec602184, 0xec602188, + 0xec60218c, 0xec602190, 0xec602194, 0xec602198, + 0xec60219c, 0xec6021a0, 0xec6021a4, 0xec6021a8, + 0xec6021ac, 0xec6021b0, 0xec6021b4, 0xec6021b8, + 0xec6021bc, 0xec6021c0, 0xec6021c4, 0xec6021c8, + 0xec6021cc, 0xec6021d0, 0xec6021d4, 0xec6021d8, + 0xec6021dc, 0xec6021e0, 0xec6021e4, 0xec6021e8, + 0xec6021ec, 0xec6021f0, 0xec6021f4, 0xec6021f8, + 0xec6021fc, 0xec602200, 0xec602204, 0xec602208, + 0xec60220c, 0xec602210, 0xec602214, 0xec602218, + 0xec60221c, 0xec602220, 0xec602224, 0xec602228, + 0xec60222c, 0xec602230, 0xec602234, 0xec602238, + 0xec60223c, 0xec602240, 0xec602244, 0xec602248, + 0xec60224c, 0xec602250, 0xec602254, 0xec602258, + 0xec60225c, 0xec602260, 0xec602264, 0xec602268, + 0xec60226c, 0xec602270, 0xec602274, 0xec602278, + 0xec60227c, 0xec602280, 0xec602284, 0xec602288, + 0xec60228c, 0xec602290, 0xec602294, 0xec602298, + 0xec60229c, 0xec6022a0, 0xec6022a4, 0xec6022a8, + 0xec6022ac, 0xec6022b0, 0xec6022b4, 0xec6022b8, + 0xec6022bc, 0xec6022c0, 0xec6022c4, 0xec6022c8, + 0xec6022cc, 0xec6022d0, 0xec6022d4, 0xec6022d8, + 0xec6022dc, 0xec6022e0, 0xec6022e4, 0xec6022e8, + 0xec6022ec, 0xec6022f0, 0xec6022f4, 0xec6022f8, + 0xec6022fc, 0xec602300, 0xec602304, 0xec602308, + 0xec60230c, 0xec602310, 0xec602314, 0xec602318, + 0xec60231c, 0xec602320, 0xec602324, 0xec602328, + 0xec60232c, 0xec602330, 0xec602334, 0xec602338, + 0xec60233c, 0xec602340, 0xec602344, 0xec602348, + 0xec60234c, 0xec602350, 0xec602354, 0xec602358, + 0xec60235c, 0xec602360, 0xec602364, 0xec602368, + 0xec60236c, 0xec602370, 0xec602374, 0xec602378, + 0xec60237c, 0xec602380, 0xec602384, 0xec602388, + 0xec60238c, 0xec602390, 0xec602394, 0xec602398, + 0xec60239c, 0xec6023a0, 0xec6023a4, 0xec6023a8, + 0xec6023ac, 0xec6023b0, 0xec6023b4, 0xec6023b8, + 0xec6023bc, 0xec6023c0, 0xec6023c4, 0xec6023c8, + 0xec6023cc, 0xec6023d0, 0xec6023d4, 0xec6023d8, + 0xec6023dc, 0xec6023e0, 0xec6023e4, 0xec6023e8, + 0xec6023ec, 0xec6023f0, 0xec6023f4, 0xec6023f8, + 0xec6023fc, 0xec602400, 0xec602404, 0xec602408, + 0xec60240c, 0xec602410, 0xec602414, 0xec602418, + 0xec60241c, 0xec602420, 0xec602424, 0xec602428, + 0xec60242c, 0xec602430, 0xec602434, 0xec602438, + 0xec60243c, 0xec602440, 0xec602444, 0xec602448, + 0xec60244c, 0xec602450, 0xec602454, 0xec602458, + 0xec60245c, 0xec602460, 0xec602464, 0xec602468, + 0xec60246c, 0xec602470, 0xec602474, 0xec602478, + 0xec60247c, 0xec602480, 0xec602484, 0xec602488, + 0xec60248c, 0xec602490, 0xec602494, 0xec602498, + 0xec60249c, 0xec6024a0, 0xec6024a4, 0xec6024a8, + 0xec6024ac, 0xec6024b0, 0xec6024b4, 0xec6024b8, + 0xec6024bc, 0xec6024c0, 0xec6024c4, 0xec6024c8, + 0xec6024cc, 0xec6024d0, 0xec6024d4, 0xec6024d8, + 0xec6024dc, 0xec6024e0, 0xec6024e4, 0xec6024e8, + 0xec6024ec, 0xec6024f0, 0xec6024f4, 0xec6024f8, + 0xec6024fc, 0xec602500, 0xec602504, 0xec602508, + 0xec60250c, 0xec602510, 0xec602514, 0xec602518, + 0xec60251c, 0xec602520, 0xec602524, 0xec602528, + 0xec60252c, 0xec602530, 0xec602534, 0xec602538, + 0xec60253c, 0xec602540, 0xec602544, 0xec602548, + 0xec60254c, 0xec602550, 0xec602554, 0xec602558, + 0xec60255c, 0xec602560, 0xec602564, 0xec602568, + 0xec60256c, 0xec602570, 0xec602574, 0xec602578, + 0xec60257c, 0xec602580, 0xec602584, 0xec602588, + 0xec60258c, 0xec602590, 0xec602594, 0xec602598, + 0xec60259c, 0xec6025a0, 0xec6025a4, 0xec6025a8, + 0xec6025ac, 0xec6025b0, 0xec6025b4, 0xec6025b8, + 0xec6025bc, 0xec6025c0, 0xec6025c4, 0xec6025c8, + 0xec6025cc, 0xec6025d0, 0xec6025d4, 0xec6025d8, + 0xec6025dc, 0xec6025e0, 0xec6025e4, 0xec6025e8, + 0xec6025ec, 0xec6025f0, 0xec6025f4, 0xec6025f8, + 0xec6025fc, 0xec602600, 0xec602604, 0xec602608, + 0xec60260c, 0xec602610, 0xec602614, 0xec602618, + 0xec60261c, 0xec602620, 0xec602624, 0xec602628, + 0xec60262c, 0xec602630, 0xec602634, 0xec602638, + 0xec60263c, 0xec602640, 0xec602644, 0xec602648, + 0xec60264c, 0xec602650, 0xec602654, 0xec602658, + 0xec60265c, 0xec602660, 0xec602664, 0xec602668, + 0xec60266c, 0xec602670, 0xec602674, 0xec602678, + 0xec60267c, 0xec602680, 0xec602684, 0xec602688, + 0xec60268c, 0xec602690, 0xec602694, 0xec602698, + 0xec60269c, 0xec6026a0, 0xec6026a4, 0xec6026a8, + 0xec6026ac, 0xec6026b0, 0xec6026b4, 0xec6026b8, + 0xec6026bc, 0xec6026c0, 0xec6026c4, 0xec6026c8, + 0xec6026cc, 0xec6026d0, 0xec6026d4, 0xec6026d8, + 0xec6026dc, 0xec6026e0, 0xec6026e4, 0xec6026e8, + 0xec6026ec, 0xec6026f0, 0xec6026f4, 0xec6026f8, + 0xec6026fc, 0xec602700, 0xec602704, 0xec602708, + 0xec60270c, 0xec602710, 0xec602714, 0xec602718, + 0xec60271c, 0xec602720, 0xec602724, 0xec602728, + 0xec60272c, 0xec602730, 0xec602734, 0xec602738, + 0xec60273c, 0xec602740, 0xec602744, 0xec602748, + 0xec60274c, 0xec602750, 0xec602754, 0xec602758, + 0xec60275c, 0xec602760, 0xec602764, 0xec602768, + 0xec60276c, 0xec602770, 0xec602774, 0xec602778, + 0xec60277c, 0xec602780, 0xec602784, 0xec602788, + 0xec60278c, 0xec602790, 0xec602794, 0xec602798, + 0xec60279c, 0xec6027a0, 0xec6027a4, 0xec6027a8, + 0xec6027ac, 0xec6027b0, 0xec6027b4, 0xec6027b8, + 0xec6027bc, 0xec6027c0, 0xec6027c4, 0xec6027c8, + 0xec6027cc, 0xec6027d0, 0xec6027d4, 0xec6027d8, + 0xec6027dc, 0xec6027e0, 0xec6027e4, 0xec6027e8, + 0xec6027ec, 0xec6027f0, 0xec6027f4, 0xec6027f8, + 0xec6027fc, 0xec602800, 0xec602804, 0xec602808, + 0xec60280c, 0xec602810, 0xec602814, 0xec602818, + 0xec60281c, 0xec602820, 0xec602824, 0xec602828, + 0xec60282c, 0xec602830, 0xec602834, 0xec602838, + 0xec60283c, 0xec602840, 0xec602844, 0xec602848, + 0xec60284c, 0xec602850, 0xec602854, 0xec602858, + 0xec60285c, 0xec602860, 0xec602864, 0xec602868, + 0xec60286c, 0xec602870, 0xec602874, 0xec602878, + 0xec60287c, 0xec602880, 0xec602884, 0xec602888, + 0xec60288c, 0xec602890, 0xec602894, 0xec602898, + 0xec60289c, 0xec6028a0, 0xec6028a4, 0xec6028a8, + 0xec6028ac, 0xec6028b0, 0xec6028b4, 0xec6028b8, + 0xec6028bc, 0xec6028c0, 0xec6028c4, 0xec6028c8, + 0xec6028cc, 0xec6028d0, 0xec6028d4, 0xec6028d8, + 0xec6028dc, 0xec6028e0, 0xec6028e4, 0xec6028e8, + 0xec6028ec, 0xec6028f0, 0xec6028f4, 0xec6028f8, + 0xec6028fc, 0xec602900, 0xec602904, 0xec602908, + 0xec60290c, 0xec602910, 0xec602914, 0xec602918, + 0xec60291c, 0xec602920, 0xec602924, 0xec602928, + 0xec60292c, 0xec602930, 0xec602934, 0xec602938, + 0xec60293c, 0xec602940, 0xec602944, 0xec602948, + 0xec60294c, 0xec602950, 0xec602954, 0xec602958, + 0xec60295c, 0xec602960, 0xec602964, 0xec602968, + 0xec60296c, 0xec602970, 0xec602974, 0xec602978, + 0xec60297c, 0xec602980, 0xec602984, 0xec602988, + 0xec60298c, 0xec602990, 0xec602994, 0xec602998, + 0xec60299c, 0xec6029a0, 0xec6029a4, 0xec6029a8, + 0xec6029ac, 0xec6029b0, 0xec6029b4, 0xec6029b8, + 0xec6029bc, 0xec6029c0, 0xec6029c4, 0xec6029c8, + 0xec6029cc, 0xec6029d0, 0xec6029d4, 0xec6029d8, + 0xec6029dc, 0xec6029e0, 0xec6029e4, 0xec6029e8, + 0xec6029ec, 0xec6029f0, 0xec6029f4, 0xec6029f8, + 0xec6029fc, 0xec602a00, 0xec602a04, 0xec602a08, + 0xec602a0c, 0xec602a10, 0xec602a14, 0xe9e22000, + 0xe9e22004, 0xe9e22008, 0xe9e2200c, 0xe9e22010, + 0xe9e22014, 0xe9e22018, 0xe9e2201c, 0xe9e22020, + 0xe9e22024, 0xe9e22028, 0xe9e2202c, 0xe9e22030, + 0xe9e22034, 0xe9e22038, 0xe9e2203c, 0x3fe08000, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x3fe08000, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x3fe08000, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0x3fe08000, + 0x3fe08000, 0xca442000, 0xca442004, 0xca442008, + 0xca44200c, 0xca442010, 0xca442014, 0xca442018, + 0xca44201c, 0xca442020, 0xca442024, 0xca442028, + 0xca44202c, 0xca442030, 0xca442034, 0xca442038, + 0xca44203c, 0xca442040, 0xca442044, 0xca442048, + 0xca44204c, 0xca442050, 0xca442054, 0xca442058, + 0xca44205c, 0xca542000, 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0x18b42088, 0x18b4208c, + 0x18b42090, 0x18b42094, 0x18b42098, 0x18b4209c, + 0x18b420a0, 0x18b420a4, 0x18b420a8, 0x18b420ac, + 0x18b420b0, 0x18b420b4, 0x18b420b8, 0x18b420bc, + 0x18b420c0, 0x18b420c4, 0x18b420c8, 0x18b420cc, + 0x18b420d0, 0x18b420d4, 0x18b420d8, 0x18b420dc, + 0x18b420e0, 0x18b420e4, 0x18b420e8, 0x18b420ec, + 0x18b420f0, 0x18b420f4, 0x18b420f8, 0x18b420fc, + 0x18b42100, 0x18b42104, 0x18b42108, 0x18b4210c, + 0x18b42110, 0x18b42114, 0x18b42118, 0x18b4211c, + 0x18b42120, 0x18b42124, 0x18b42128, 0x18b4212c, + 0x18b42130, 0x18b42134, 0x18b42138, 0x18b4213c, + 0x18b42140, 0x18b42144, 0x18b42148, 0x18b4214c, + 0x18b42150, 0x18b42154, 0x18b42158, 0x18b4215c, + 0x18b42160, 0x18b42164, 0x18b42168, 0x18b4216c, + 0x18b42170, 0x18b42174, 0x18b42178, 0x18b4217c, + 0x18b42180, 0x18b42184, 0x18b42188, 0x18b4218c, + 0x18b42190, 0x18b42194, 0x18b42198, 0x18b4219c, + 0x18b421a0, 0x18b421a4, 0x18b421a8, 0x18b421ac, + 0x18b421b0, 0x18b421b4, 0x18b421b8, 0x18b421bc, + 0x18b421c0, 0x18b421c4, 0x18b421c8, 0x18b421cc, + 0x18b421d0, 0x18b421d4, 0x18b421d8, 0x18b421dc, + 0x18b421e0, 0x18b421e4, 0x18b421e8, 0x18b421ec, + 0x18b421f0, 0x18b421f4, 0x18b421f8, 0x18b421fc, + 0x18b42200, 0x18b42204, 0x18b42208, 0x18b4220c, + 0x18b42210, 0x18b42214, 0x18b42218, 0x18b4221c, + 0x18b42220, 0x18b42224, 0x18b42228, 0x18b4222c, + 0x18b42230, 0xc1282000, 0xc1282004, 0xc1282008, + 0xc128200c, 0xc1282010, 0xc1282014, 0xc1282018, + 0xc128201c, 0xc1282020, 0xc1282024, 0xc1282028, + 0xc128202c, 0xc1282030, 0xc1282034, 0xc1282038, + 0xc128203c, 0xc1282040, 0xc1282044, 0xc1282048, + 0xc128204c, 0xc1282050, 0xc1282054, 0xc1282058, + 0xc128205c, 0xc1282060, 0xc1282064, 0xc1282068, + 0xc128206c, 0xc1282070, 0xc1282074, 0xc1282078, + 0xc128207c, 0xc1282080, 0xc1282084, 0xc1282088, + 0xc128208c, 0xc1282090, 0xc1282094, 0xc1282098, + 0xc128209c, 0xc12820a0, 0xc12820a4, 0xc12820a8, + 0xc12820ac, 0xc12820b0, 0xc12820b4, 0xc12820b8, + 0xc12820bc, 0xc12820c0, 0xc12820c4, 0xc12820c8, + 0xc12820cc, 0xc12820d0, 0xc12820d4, 0xc12820d8, + 0xc12820dc, 0xc12820e0, 0xc12820e4, 0xc12820e8, + 0xc12820ec, 0xc12820f0, 0xc12820f4, 0xc12820f8, + 0xc12820fc, 0xc1282100, 0xc1282104, 0xc1282108, + 0xc128210c, 0xc1282110, 0xc1282114, 0xc1282118, + 0xc128211c, 0xc1282120, 0xc1282124, 0xc1282128, + 0xc128212c, 0xc1282130, 0xc1282134, 0xc1282138, + 0xc128213c, 0xc1282140, 0xc1282144, 0xc1282148, + 0xc128214c, 0xc1282150, 0xc1282154, 0xc1282158, + 0xc128215c, 0xc1282160, 0xc1282164, 0xc1282168, + 0xc128216c, 0xc1282170, 0xc1282174, 0xc1282178, + 0xc128217c, 0xc1282180, 0xc1282184, 0xc1282188, + 0xc128218c, 0xc1282190, 0xc1282194, 0xc1282198, + 0xc128219c, 0xc12821a0, 0xc12821a4, 0xc12821a8, + 0xc12821ac, 0xc12821b0, 0xc12821b4, 0xc12821b8, + 0xc12821bc, 0xc12821c0, 0xc12821c4, 0xc12821c8, + 0xc12821cc, 0xc12821d0, 0xc12821d4, 0xc12821d8, + 0xc12821dc, 0xc12821e0, 0xc12821e4, 0xc12821e8, + 0xc12821ec, 0xc12821f0, 0xc12821f4, 0xc12821f8, + 0xc12821fc, 0xc1282200, 0xc1282204, 0xc1282208, + 0xc128220c, 0xc1282210, 0xc1282214, 0xc1282218, + 0xc128221c, 0xc1282220, 0xc1282224, 0xc1282228, + 0xc128222c, 0xc1282230, 0xc1282234, 0xc1282238, + 0xc128223c, 0xc1282240, 0xc1282244, 0xc1282248, + 0xc128224c, 0xc1282250, 0xc1282254, 0xc1282258, + 0xc128225c, 0xc1282260, 0xc1282264, 0xc1282268, + 0xc128226c, 0xc1282270, 0xc1282274, 0xc1282278, + 0xc128227c, 0xc1282280, 0xc1282284, 0xc1282288, + 0xc128228c, 0xc1282290, 0xc1282294, 0xc1282298, + 0xc128229c, 0xc12822a0, 0xc12822a4, 0xc12822a8, + 0xc12822ac, 0xc12822b0, 0xc12822b4, 0xc12822b8, + 0xc6802000, 0xc6802004, 0xc6802008, 0xc680200c, + 0xc6802010, 0xc6802014, 0xc6802018, 0xc680201c, + 0xc6802020, 0xc6802024, 0xc6802028, 0xc680202c, + 0xc6802030, 0xc6802034, 0xc6802038, 0xc680203c, + 0xc6802040, 0xc6802044, 0xc6802048, 0xc680204c, + 0xc6802050, 0xc6802054, 0xc6802058, 0xc680205c, + 0xc6802060, 0xc6802064, 0xc6802068, 0xc680206c, + 0xc6802070, 0xc6802074, 0xc6802078, 0xc680207c, + 0xc6802080, 0xc6802084, 0xc6802088, 0xc680208c, + 0xc6802090, 0xc6802094, 0xc6802098, 0xc680209c, + 0xc68020a0, 0xc68020a4, 0xc68020a8, 0xc68020ac, + 0xc68020b0, 0xc68020b4, 0xc68020b8, 0xc68020bc, + 0xc68020c0, 0xc68020c4, 0xc68020c8, 0xc68020cc, + 0xc5802000, 0xc5802004, 0xc5802008, 0xc580200c, + 0xc5802010, 0xc5802014, 0xc5802018, 0xc580201c, + 0xc5802020, 0xc5802024, 0xc5802028, 0xc580202c, + 0xc5802030, 0xc5802034, 0xc5802038, 0xc580203c, + 0xc5802040, 0xc5802044, 0xc5802048, 0xc580204c, + 0xc5802050, 0xc5802054, 0xc5802058, 0xc580205c, + 0xc5802060, 0xc5802064, 0xc5802068, 0xc580206c, + 0xc5802070, 0xc5802074, 0xc5802078, 0xc580207c, + 0xc5802080, 0xc5802084, 0xc5802088, 0xc580208c, + 0xc5802090, 0xc5802094, 0xc5802098, 0xc580209c, + 0xc58020a0, 0xc58020a4, 0xc58020a8, 0xc58020ac, + 0xc58020b0, 0xc58020b4, 0xc58020b8, 0xc58020bc, + 0xc58020c0, 0xc58020c4, 0xc58020c8, 0xc58020cc, + 0xc58020d0, 0xc58020d4, 0xc58020d8, 0xc58020dc, + 0xc58020e0, 0xc58020e4, 0xc58020e8, 0xc58020ec, + 0xc58020f0, 0xc58020f4, 0xc58020f8, 0xc58020fc, + 0xc5802100, 0xc5802104, 0xc5802108, 0xc580210c, + 0xc5802110, 0xc5802114, 0xc5802118, 0xc580211c, + 0xc5802120, 0xc5802124, 0xc5802128, 0xc580212c, + 0xc5802130, 0xc5802134, 0xc5802138, 0xc580213c, + 0xc5802140, 0xc5802144, 0xc5802148, 0xc580214c, + 0xc5802150, 0xc5802154, 0xc5802158, 0xc580215c, + 0xc5802160, 0xc5802164, 0xc5802168, 0xc580216c, + 0xc5802170, 0xc5802174, 0xc5802178, 0xc580217c, + 0xc5802180, 0xc5802184, 0xc5802188, 0xc580218c, + 0xc5802190, 0xc5802194, 0xc5802198, 0xc580219c, + 0xc58021a0, 0xc58021a4, 0xc58021a8, 0xc58021ac, + 0xc58021b0, 0xc58021b4, 0xc58021b8, 0xc58021bc, + 0xc58021c0, 0xc58021c4, 0xc58021c8, 0xc58021cc, + 0xc58021d0, 0xc58021d4, 0xc58021d8, 0xc58021dc, + 0xc58021e0, 0xc58021e4, 0xc58021e8, 0xc58021ec, + 0xc58021f0, 0xc58021f4, 0xc58021f8, 0xc58021fc, + 0xc5802200, 0xc5802204, 0xc5802208, 0xc580220c, + 0xc5802210, 0xc5802214, 0xc5802218, 0xc580221c, + 0xc5802220, 0xc5802224, 0xc5802228, 0xc580222c, + 0xc5802230, 0xc5802234, 0xc5802238, 0xc580223c, + 0xc5802240, 0xc5802244, 0xc5802248, 0xc580224c, + 0xc5802250, 0xc5802254, 0xc5802258, 0xc580225c, + 0xc5802260, 0xc5802264, 0xc5802268, 0xc580226c, + 0xc5802270, 0xc5802274, 0xc5802278, 0xc580227c, + 0xc5802280, 0xc5802284, 0xc5802288, 0xc580228c, + 0xc5802290, 0xc5802294, 0xc5802298, 0xc580229c, + 0xc58022a0, 0xc58022a4, 0xc58022a8, 0xc58022ac, + 0xc58022b0, 0xc58022b4, 0xc58022b8, 0xc58022bc, + 0xc58022c0, 0xc58022c4, 0xc58022c8, 0xc58022cc, + 0xc58022d0, 0xc58022d4, 0xc58022d8, 0xc58022dc, + 0xc58022e0, 0xc58022e4, 0xc58022e8, 0xc58022ec, + 0xc58022f0, 0xc58022f4, 0xc58022f8, 0xc58022fc, + 0xc5802300, 0xc5802304, 0xc5802308, 0xc580230c, + 0xc3022000, 0xc3022004, 0xc3022008, 0xc302200c, + 0xc3022010, 0xc3022014, 0xc3022018, 0xc302201c, + 0xc3022020, 0xc3022024, 0xc3022028, 0xc302202c, + 0xc3022030, 0xc3022034, 0xc3022038, 0xc302203c, + 0xc3022040, 0xc3022044, 0xc3022048, 0xc302204c, + 0xc3022050, 0xc3022054, 0xc3022058, 0xc302205c, + 0xc3022060, 0xc3022064, 0xc3022068, 0xc302206c, + 0xc3022070, 0xc3022074, 0xc3022078, 0xc302207c, + 0xc3022080, 0xc3022084, 0xc3022088, 0xc302208c, + 0xc3022090, 0xc3022094, 0xc3022098, 0xc302209c, + 0xc30220a0, 0xc30220a4, 0xc30220a8, 0xc30220ac, + 0xc30220b0, 0xc3422000, 0xc3422004, 0xc3422008, + 0xc342200c, 0xc3422010, 0xc3422014, 0xc3422018, + 0xc342201c, 0xc3422020, 0xc3422024, 0xc3422028, + 0xc342202c, 0xc3422030, 0xc3422034, 0xc3422038, + 0xc342203c, 0xc3422040, 0xc3422044, 0xc3422048, + 0xc342204c, 0xc3422050, 0xc3422054, 0xc3422058, + 0xc342205c, 0xc3422060, 0xc3422064, 0xc3422068, + 0xc342206c, 0xc3422070, 0xc3422074, 0xc3422078, + 0xc342207c, 0xc3422080, 0xc3422084, 0xc3422088, + 0xc342208c, 0xc3422090, 0xc3422094, 0xc3422098, + 0xc342209c, 0xc34220a0, 0xc34220a4, 0xc34220a8, + 0xc34220ac, 0xc34220b0 +}; + +static const u32 rgidw_register_list[] = { + 0xe8026000, 0xe8026004, 0xe8026008, 0xe802600c, + 0xe8026010, 0xe8026014, 0xe8026018, 0xe802601c, + 0xe8026020, 0xe8026024, 0xe8026028, 0xe802602c, + 0xe8026030, 0xe8026034, 0xe8026038, 0xe802603c, + 0xe8026040, 0xe8026044, 0xe8026048, 0xe802604c, + 0xe80a6000, 0xe80a6004, 0xe80a6008, 0xe80a600c, + 0xe80a6010, 0xe80a6014, 0xe80a6018, 0xe80a601c, + 0xe80a6020, 0xe80a6024, 0xe80a6028, 0xe80a602c, + 0xe80a6030, 0xe80a6034, 0xe80a6038, 0xe80a603c, + 0xe80a6040, 0xe80a6044, 0xe80a6048, 0xe80a604c, + 0xe8126000, 0xe8126004, 0xe8126008, 0xe812600c, + 0xe8126010, 0xe8126014, 0xe8126018, 0xe812601c, + 0xe8126020, 0xe8126024, 0xe8126028, 0xe812602c, + 0xe8126030, 0xe8126034, 0xe8126038, 0xe812603c, + 0xe8126040, 0xe8126044, 0xe8126048, 0xe812604c, + 0xe81a6000, 0xe81a6004, 0xe81a6008, 0xe81a600c, + 0xe81a6010, 0xe81a6014, 0xe81a6018, 0xe81a601c, + 0xe81a6020, 0xe81a6024, 0xe81a6028, 0xe81a602c, + 0xe81a6030, 0xe81a6034, 0xe81a6038, 0xe81a603c, + 0xe81a6040, 0xe81a6044, 0xe81a6048, 0xe81a604c, + 0xe8226000, 0xe8226004, 0xe8226008, 0xe822600c, + 0xe8226010, 0xe8226014, 0xe8226018, 0xe822601c, + 0xe8226020, 0xe8226024, 0xe8226028, 0xe822602c, + 0xe8226030, 0xe8226034, 0xe8226038, 0xe822603c, + 0xe8226040, 0xe8226044, 0xe8226048, 0xe822604c, + 0xe82a6000, 0xe82a6004, 0xe82a6008, 0xe82a600c, + 0xe82a6010, 0xe82a6014, 0xe82a6018, 0xe82a601c, + 0xe82a6020, 0xe82a6024, 0xe82a6028, 0xe82a602c, + 0xe82a6030, 0xe82a6034, 0xe82a6038, 0xe82a603c, + 0xe82a6040, 0xe82a6044, 0xe82a6048, 0xe82a604c, + 0xe8326000, 0xe8326004, 0xe8326008, 0xe832600c, + 0xe8326010, 0xe8326014, 0xe8326018, 0xe832601c, + 0xe8326020, 0xe8326024, 0xe8326028, 0xe832602c, + 0xe8326030, 0xe8326034, 0xe8326038, 0xe832603c, + 0xe8326040, 0xe8326044, 0xe8326048, 0xe832604c, + 0xe83a6000, 0xe83a6004, 0xe83a6008, 0xe83a600c, + 0xe83a6010, 0xe83a6014, 0xe83a6018, 0xe83a601c, + 0xe83a6020, 0xe83a6024, 0xe83a6028, 0xe83a602c, + 0xe83a6030, 0xe83a6034, 0xe83a6038, 0xe83a603c, + 0xe83a6040, 0xe83a6044, 0xe83a6048, 0xe83a604c, + 0xc0626000, 0xc0626004, 0xc0626008, 0xc062600c, + 0xc0626010, 0xc0626014, 0xc0626018, 0xc062601c, + 0xc0626020, 0xc0626024, 0xc0626028, 0xc062602c, + 0xc0626030, 0xc0626034, 0xc0626038, 0xc062603c, + 0xc0626040, 0xc0626044, 0xc0626048, 0xc062604c, + 0xc0626050, 0xc0626054, 0xc0766000, 0xc0766004, + 0xc0766008, 0xc076600c, 0xc0766010, 0xc0766014, + 0xc0766018, 0xc076601c, 0xc0766020, 0xc0766024, + 0xc0766028, 0xc076602c, 0xc0766030, 0xc0766034, + 0xc0766038, 0xc076603c, 0xc0766040, 0xc0766044, + 0xc0766048, 0xc076604c, 0xc0766050, 0xc0766054, + 0xc0766058, 0xc076605c, 0xc0766060, 0xc0766064, + 0xc0766068, 0xc076606c, 0xc0766070, 0xc0766074, + 0xc0766078, 0xc076607c, 0xc0766080, 0xc0766084, + 0xc0766088, 0xc076608c, 0xc0766090, 0xc0766094, + 0xc0766098, 0xc076609c, 0xc07660a0, 0xc07660a4, + 0xc07660a8, 0xc07660ac, 0xc07660b0, 0xc07660b4, + 0xc07660b8, 0xc07660bc, 0xc07660c0, 0xc07660c4, + 0xc07660c8, 0xc07660cc, 0xc07660d0, 0xc07660d4, + 0xc07660d8, 0xc07660dc, 0xc07a6000, 0xc07a6004, + 0xc07a6008, 0xc07a600c, 0xc07a6010, 0xc07a6014, + 0xc07a6018, 0xc07a601c, 0xc07a6020, 0xc07a6024, + 0xc07a6028, 0xc07a602c, 0xc07a6030, 0xc07a6034, + 0xc07a6038, 0xc07a603c, 0xc07a6040, 0xc07a6044, + 0xc07a6048, 0xc07a604c, 0xc07a6050, 0xc07a6054, + 0xc07a6058, 0x1d006000, 0x1d006004, 0x1d006008, + 0x1d00600c, 0x1d006010, 0x1d006014, 0x1d006018, + 0x1d00601c, 0x1d006020, 0x1d006024, 0x1d006028, + 0x1d00602c, 0x1d006030, 0x1d006034, 0x1d006038, + 0x1d00603c, 0x1d006040, 0x1d006044, 0x1d006048, + 0x1d00604c, 0x1d006050, 0x1d006054, 0x1d006058, + 0x1d00605c, 0x1d006060, 0x1d006064, 0x1d006068, + 0x1d00606c, 0x1d006070, 0x1d006074, 0x1d006078, + 0x1d00607c, 0x1d006080, 0x1d006084, 0x1d006088, + 0x1d00608c, 0x1d006090, 0x1d006094, 0x1d006098, + 0x1d00609c, 0x1d0060a0, 0x1d0060a4, 0x1d0060a8, + 0x1d0060ac, 0x1d0060b0, 0x1d0060b4, 0x1d0060b8, + 0xc6706000, 0xc6706004, 0xc6706008, 0xc670600c, + 0xc6706010, 0xc6706014, 0xc6706018, 0xc670601c, + 0xc6706020, 0xc6706024, 0xc6706028, 0xc670602c, + 0xc6706030, 0xc6706034, 0xc6706038, 0xc670603c, + 0xc6706040, 0xc6706044, 0xc6706048, 0xc670604c, + 0xc6706050, 0xc6706054, 0xc6706058, 0xc670605c, + 0xc6706060, 0xc6706064, 0xc6706068, 0xc670606c, + 0xc6706070, 0xc6706074, 0xc6706078, 0xc670607c, + 0xc6706080, 0xc6706084, 0xc6706088, 0xc670608c, + 0xc6706090, 0xc6706094, 0xc6706098, 0xc670609c, + 0xc67060a0, 0xc67060a4, 0xc67060a8, 0xc1746000, + 0xc1746004, 0xc1746008, 0xc174600c, 0xc1746010, + 0xc1746014, 0xc1746018, 0xc174601c, 0xc1746020, + 0xc1746024, 0xc1746028, 0xc174602c, 0xc1746030, + 0xc1746034, 0xc1746038, 0xc174603c, 0xc1746040, + 0xc1746044, 0xc1746048, 0xc174604c, 0xc1746050, + 0xc1746054, 0xec606000, 0xec606004, 0xec606008, + 0xec60600c, 0xec606010, 0xec606014, 0xec606018, + 0xec60601c, 0xec606020, 0xec606024, 0xec606028, + 0xec60602c, 0xec606030, 0xec606034, 0xec606038, + 0xec60603c, 0xec606040, 0xec606044, 0xec606048, + 0xec60604c, 0xec606050, 0xec606054, 0xec606058, + 0xec60605c, 0xec606060, 0xec606064, 0xec606068, + 0xec60606c, 0xec606070, 0xec606074, 0xec606078, + 0xec60607c, 0xec606080, 0xec606084, 0xec606088, + 0xec60608c, 0xec606090, 0xec606094, 0xec606098, + 0xec60609c, 0xec6060a0, 0xec6060a4, 0xec6060a8, + 0xec6060ac, 0xec6060b0, 0xec6060b4, 0xec6060b8, + 0xec6060bc, 0xec6060c0, 0xec6060c4, 0xec6060c8, + 0xec6060cc, 0xec6060d0, 0xec6060d4, 0xec6060d8, + 0xec6060dc, 0xec6060e0, 0xec6060e4, 0xec6060e8, + 0xec6060ec, 0xec6060f0, 0xec6060f4, 0xec6060f8, + 0xec6060fc, 0xec606100, 0xec606104, 0xec606108, + 0xec60610c, 0xec606110, 0xec606114, 0xec606118, + 0xec60611c, 0xec606120, 0xec606124, 0xec606128, + 0xec60612c, 0xec606130, 0xec606134, 0xec606138, + 0xec60613c, 0xec606140, 0xec606144, 0xec606148, + 0xec60614c, 0xec606150, 0xec606154, 0xec606158, + 0xec60615c, 0xec606160, 0xec606164, 0xec606168, + 0xec60616c, 0xec606170, 0xec606174, 0xec606178, + 0xec60617c, 0xec606180, 0xec606184, 0xec606188, + 0xec60618c, 0xec606190, 0xec606194, 0xec606198, + 0xec60619c, 0xec6061a0, 0xec6061a4, 0xec6061a8, + 0xec6061ac, 0xec6061b0, 0xec6061b4, 0xec6061b8, + 0xec6061bc, 0xec6061c0, 0xec6061c4, 0xec6061c8, + 0xec6061cc, 0xec6061d0, 0xec6061d4, 0xec6061d8, + 0xec6061dc, 0xec6061e0, 0xec6061e4, 0xec6061e8, + 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0xc58060c0, 0xc58060c4, 0xc58060c8, 0xc58060cc, + 0xc58060d0, 0xc58060d4, 0xc58060d8, 0xc58060dc, + 0xc58060e0, 0xc58060e4, 0xc58060e8, 0xc58060ec, + 0xc58060f0, 0xc58060f4, 0xc58060f8, 0xc58060fc, + 0xc5806100, 0xc5806104, 0xc5806108, 0xc580610c, + 0xc5806110, 0xc5806114, 0xc5806118, 0xc580611c, + 0xc5806120, 0xc5806124, 0xc5806128, 0xc580612c, + 0xc5806130, 0xc5806134, 0xc5806138, 0xc580613c, + 0xc5806140, 0xc5806144, 0xc5806148, 0xc580614c, + 0xc5806150, 0xc5806154, 0xc5806158, 0xc580615c, + 0xc5806160, 0xc5806164, 0xc5806168, 0xc580616c, + 0xc5806170, 0xc5806174, 0xc5806178, 0xc580617c, + 0xc5806180, 0xc5806184, 0xc5806188, 0xc580618c, + 0xc5806190, 0xc5806194, 0xc5806198, 0xc580619c, + 0xc58061a0, 0xc58061a4, 0xc58061a8, 0xc58061ac, + 0xc58061b0, 0xc58061b4, 0xc58061b8, 0xc58061bc, + 0xc58061c0, 0xc58061c4, 0xc58061c8, 0xc58061cc, + 0xc58061d0, 0xc58061d4, 0xc58061d8, 0xc58061dc, + 0xc58061e0, 0xc58061e4, 0xc58061e8, 0xc58061ec, + 0xc58061f0, 0xc58061f4, 0xc58061f8, 0xc58061fc, + 0xc5806200, 0xc5806204, 0xc5806208, 0xc580620c, + 0xc5806210, 0xc5806214, 0xc5806218, 0xc580621c, + 0xc5806220, 0xc5806224, 0xc5806228, 0xc580622c, + 0xc5806230, 0xc5806234, 0xc5806238, 0xc580623c, + 0xc5806240, 0xc5806244, 0xc5806248, 0xc580624c, + 0xc5806250, 0xc5806254, 0xc5806258, 0xc580625c, + 0xc5806260, 0xc5806264, 0xc5806268, 0xc580626c, + 0xc5806270, 0xc5806274, 0xc5806278, 0xc580627c, + 0xc5806280, 0xc5806284, 0xc5806288, 0xc580628c, + 0xc5806290, 0xc5806294, 0xc5806298, 0xc580629c, + 0xc58062a0, 0xc58062a4, 0xc58062a8, 0xc58062ac, + 0xc58062b0, 0xc58062b4, 0xc58062b8, 0xc58062bc, + 0xc58062c0, 0xc58062c4, 0xc58062c8, 0xc58062cc, + 0xc58062d0, 0xc58062d4, 0xc58062d8, 0xc58062dc, + 0xc58062e0, 0xc58062e4, 0xc58062e8, 0xc58062ec, + 0xc58062f0, 0xc58062f4, 0xc58062f8, 0xc58062fc, + 0xc5806300, 0xc5806304, 0xc5806308, 0xc580630c, + 0xc3026000, 0xc3026004, 0xc3026008, 0xc302600c, + 0xc3026010, 0xc3026014, 0xc3026018, 0xc302601c, + 0xc3026020, 0xc3026024, 0xc3026028, 0xc302602c, + 0xc3026030, 0xc3026034, 0xc3026038, 0xc302603c, + 0xc3026040, 0xc3026044, 0xc3026048, 0xc302604c, + 0xc3026050, 0xc3026054, 0xc3026058, 0xc302605c, + 0xc3026060, 0xc3026064, 0xc3026068, 0xc302606c, + 0xc3026070, 0xc3026074, 0xc3026078, 0xc302607c, + 0xc3026080, 0xc3026084, 0xc3026088, 0xc302608c, + 0xc3026090, 0xc3026094, 0xc3026098, 0xc302609c, + 0xc30260a0, 0xc30260a4, 0xc30260a8, 0xc30260ac, + 0xc30260b0, 0xc3426000, 0xc3426004, 0xc3426008, + 0xc342600c, 0xc3426010, 0xc3426014, 0xc3426018, + 0xc342601c, 0xc3426020, 0xc3426024, 0xc3426028, + 0xc342602c, 0xc3426030, 0xc3426034, 0xc3426038, + 0xc342603c, 0xc3426040, 0xc3426044, 0xc3426048, + 0xc342604c, 0xc3426050, 0xc3426054, 0xc3426058, + 0xc342605c, 0xc3426060, 0xc3426064, 0xc3426068, + 0xc342606c, 0xc3426070, 0xc3426074, 0xc3426078, + 0xc342607c, 0xc3426080, 0xc3426084, 0xc3426088, + 0xc342608c, 0xc3426090, 0xc3426094, 0xc3426098, + 0xc342609c, 0xc34260a0, 0xc34260a4, 0xc34260a8, + 0xc34260ac, 0xc34260b0 +}; + +static const u32 sec_modid_register_list[] = { + 0xe8023800, 0xe8023804, 0xe8023808, 0xe802380c, + 0xe8023810, 0xe8023814, 0xe80a3800, 0xe80a3804, + 0xe80a3808, 0xe80a380c, 0xe80a3810, 0xe80a3814, + 0xe8123800, 0xe8123804, 0xe8123808, 0xe812380c, + 0xe8123810, 0xe8123814, 0xe81a3800, 0xe81a3804, + 0xe81a3808, 0xe81a380c, 0xe81a3810, 0xe81a3814, + 0xe8223800, 0xe8223804, 0xe8223808, 0xe822380c, + 0xe8223810, 0xe8223814, 0xe82a3800, 0xe82a3804, + 0xe82a3808, 0xe82a380c, 0xe82a3810, 0xe82a3814, + 0xe8323800, 0xe8323804, 0xe8323808, 0xe832380c, + 0xe8323810, 0xe8323814, 0xe83a3800, 0xe83a3804, + 0xe83a3808, 0xe83a380c, 0xe83a3810, 0xe83a3814, + 0xc0623800, 0xc0623804, 0xc0623808, 0xc062380c, + 0xc0623810, 0xc0623814, 0xc0623818, 0xc062381c, + 0xc0623820, 0xc0623824, 0xc0623828, 0xc0763800, + 0xc0763804, 0xc0763808, 0xc076380c, 0xc0763810, + 0xc0763814, 0xc0763818, 0xc076381c, 0xc0763820, + 0xc0763824, 0xc0763828, 0xc076382c, 0xc0763830, + 0xc0763834, 0xc0763838, 0xc076383c, 0xc0763840, + 0xc0763844, 0xc0763848, 0xc076384c, 0xc0763850, + 0xc0763854, 0xc0763858, 0xc076385c, 0xc0763860, + 0xc0763864, 0xc0763868, 0xc076386c, 0xc0763870, + 0xc0763874, 0xc0763878, 0xc076387c, 0xc0763880, + 0xc0763884, 0xc0763888, 0xc076388c, 0xc0763890, + 0xc0763894, 0xc0763898, 0xc076389c, 0xc07638a0, + 0xc07638a4, 0xc07638a8, 0xc07638ac, 0xc07638b0, + 0xc07a3800, 0xc07a3804, 0xc07a3808, 0xc07a380c, + 0xc07a3810, 0xc07a3814, 0xc07a3818, 0xc07a381c, + 0xc07a3820, 0xc07a3824, 0xc07a3828, 0xc07a382c, + 0x1d003800, 0x1d003804, 0x1d003808, 0x1d00380c, + 0x1d003810, 0x1d003814, 0x1d003818, 0x1d00381c, + 0x1d003820, 0x1d003824, 0x1d003828, 0x1d00382c, + 0x1d003830, 0x1d003834, 0x1d003838, 0x1d00383c, + 0x1d003840, 0x1d003844, 0x1d003848, 0x1d00384c, + 0x1d003850, 0x1d003854, 0x1d003858, 0x1d00385c, + 0x1d003860, 0x1d003864, 0x1d003868, 0x1d00386c, + 0x1d003870, 0x1d003874, 0x1d003878, 0x1d00387c, + 0x1d003880, 0x1d003884, 0xc6703800, 0xc6703804, + 0xc6703808, 0xc670380c, 0xc6703810, 0xc6703814, + 0xc6703818, 0xc670381c, 0xc6703820, 0xc6703824, + 0xc6703828, 0xc670382c, 0xc6703830, 0xc6703834, + 0xc6703838, 0xc670383c, 0xc6703840, 0xc6703844, + 0xc6703848, 0xc1743800, 0xc1743804, 0xc1743808, + 0xc174380c, 0xc1743810, 0xc1743814, 0xc1743818, + 0xc174381c, 0xc1743820, 0xc1743824, 0xc1743828, + 0xec603800, 0xec603804, 0xec603808, 0xec60380c, + 0xec603810, 0xec603814, 0xec603818, 0xec60381c, + 0xec603820, 0xec603824, 0xec603828, 0xec60382c, + 0xec603830, 0xec603834, 0xec603838, 0xec60383c, + 0xec603840, 0xec603844, 0xec603848, 0xec60384c, + 0xec603850, 0xec603854, 0xec603858, 0xec60385c, + 0xec603860, 0xec603864, 0xec603868, 0xec60386c, + 0xec603870, 0xec603874, 0xec603878, 0xec60387c, + 0xec603880, 0xec603884, 0xec603888, 0xec60388c, + 0xec603890, 0xec603894, 0xec603898, 0xec60389c, + 0xec6038a0, 0xec6038a4, 0xec6038a8, 0xec6038ac, + 0xec6038b0, 0xe9e23800, 0xe9e23804, 0xe9e23808, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0xca443800, + 0xca443804, 0xca443808, 0xca44380c, 0xca443810, + 0xca443814, 0xca443818, 0xca44381c, 0xca443820, + 0xca443824, 0xca543800, 0xca543804, 0xca543808, + 0xca54380c, 0xca543810, 0xca543814, 0xca543818, + 0xca54381c, 0xca543820, 0xcbf03800, 0xcbf03804, + 0xcbf03808, 0xcbf0380c, 0xcbf03810, 0xcbf03814, + 0xcbf03818, 0xcbf0381c, 0xcbf03820, 0xcbf03824, + 0xcbf03828, 0xcbf0382c, 0xcbf03830, 0xcbf03834, + 0xcbf03838, 0xcbf0383c, 0xcbf03840, 0xcbf03844, + 0xcbf03848, 0xcbf0384c, 0xcbf03850, 0xcbf03854, + 0xcbf03858, 0xcbf0385c, 0xcbf03860, 0xcbf03864, + 0xcbf03868, 0xcbf0386c, 0xcbf03870, 0xcbf03874, + 0xcbf03878, 0xcbf0387c, 0xcbf03880, 0xcbf03884, + 0xcbf03888, 0xcbf0388c, 0xcbf03890, 0xcbf03894, + 0xcbf03898, 0xcbf0389c, 0xcbf038a0, 0xcbf038a4, + 0xcbf038a8, 0xcbf038ac, 0xc9d03800, 0xc9d03804, + 0xc9d03808, 0xc9d0380c, 0xc9d03810, 0xc9d03814, + 0xc9d03818, 0xc9d0381c, 0xc9d03820, 0xc9d03824, + 0xc9d03828, 0xc9d0382c, 0xc9d03830, 0xc9d03834, + 0xc9d03838, 0xc9d0383c, 0xc9d03840, 0xc9d03844, + 0xc9d03848, 0xc9d0384c, 0xc9d03850, 0xc9d03854, + 0xc9d03858, 0xc9d0385c, 0xc9d03860, 0xc9d03864, + 0xc9d03868, 0xc9d0386c, 0xc9d03870, 0xc9d03874, + 0xc9d03878, 0xc9d0387c, 0xc9d03880, 0xc9d03884, + 0xc9d03888, 0xc9d0388c, 0xc9d03890, 0xc9d03894, + 0xc9d03898, 0xc9d0389c, 0xc9d038a0, 0xc9d038a4, + 0xc9d038a8, 0xc9d038ac, 0xc9d038b0, 0xc9d038b4, + 0xc9d038b8, 0xc9d038bc, 0xc9d038c0, 0xc9d038c4, + 0xc9d038c8, 0xc9d038cc, 0xde803800, 0xde803804, + 0xde803808, 0xde80380c, 0xde803810, 0xde803814, + 0xde803818, 0xde80381c, 0xde803820, 0xde803824, + 0xde803828, 0xde80382c, 0xde803830, 0xde803834, + 0xde803838, 0xde80383c, 0xde803840, 0xde803844, + 0xde803848, 0xde80384c, 0xde803850, 0xde803854, + 0xde803858, 0xc1a03800, 0xc1a03804, 0xc1a03808, + 0xc1a0380c, 0xc1a03810, 0xc1a03814, 0xc1a03818, + 0xc1a0381c, 0xc1a03820, 0xc1a03824, 0xc1a03828, + 0xc1a0382c, 0xc1a03830, 0xc1e03800, 0xc1e03804, + 0xc1e03808, 0xc1e0380c, 0xc1e03810, 0xc1e03814, + 0xc1e03818, 0xc1e0381c, 0xc1e03820, 0xc1e03824, + 0xc1e03828, 0xc1e0382c, 0xc1e03830, 0xe9a03800, + 0xe9a03804, 0xe9a03808, 0xe9a0380c, 0xe9a03810, + 0xe9a03814, 0xe9a03818, 0xe9a0381c, 0xe9a03820, + 0xe9a03824, 0xe9a03828, 0xe9a0382c, 0xe9a03830, + 0xe9a03834, 0xe9a03838, 0xe9a0383c, 0xe9a03840, + 0xe9a03844, 0xe9a03848, 0xe9a0384c, 0xe9a03850, + 0xe9a03854, 0xe9a03858, 0xe9a0385c, 0xe9a03860, + 0xe9a03864, 0xe9a03868, 0xe9a0386c, 0xe9a03870, + 0xe9a03874, 0xe9a03878, 0xe9a0387c, 0xe9a03880, + 0xe9a03884, 0xe9a03888, 0xe9a0388c, 0xe9a03890, + 0xe9a03894, 0xe9a03898, 0xe9a0389c, 0xe9a038a0, + 0xe9a038a4, 0xe9a038a8, 0xe9a038ac, 0xe9a038b0, + 0xe9a038b4, 0xe9a038b8, 0xe9a038bc, 0xe9a038c0, + 0xe9a038c4, 0xe9a038c8, 0xe9a038cc, 0xe9a038d0, + 0xe9a038d4, 0xe9a038d8, 0xe9a038dc, 0xe9a038e0, + 0xe9a038e4, 0xe9a038e8, 0xe9a038ec, 0xe9a038f0, + 0xe9a038f4, 0xe9a038f8, 0xe9a038fc, 0xe9a03900, + 0xe9a03904, 0xe9a03908, 0xe9a0390c, 0xe9a03910, + 0xe9a03914, 0xe9a03918, 0xe9a0391c, 0xe9a03920, + 0xe9a03924, 0xe9a03928, 0xe9a0392c, 0xe9a03930, + 0xe9a03934, 0xe9a03938, 0xe9a0393c, 0xe9a03940, + 0xe9a03944, 0xe9a03948, 0xe9a0394c, 0xe9a03950, + 0xe9a03954, 0xe9a03958, 0xd2f03800, 0xd2f03804, + 0xd2f03808, 0xd2f0380c, 0xd2f03810, 0xd2f03814, + 0xd2f03818, 0xd2f0381c, 0xd2f03820, 0xd2f03824, + 0xd2f03828, 0xd2f0382c, 0xd2f03830, 0xd2f03834, + 0xd2f03838, 0xd2f0383c, 0xd2f03840, 0xd2f03844, + 0xd2f03848, 0xd2f0384c, 0xd2f03850, 0xd6f03800, + 0xd6f03804, 0xd6f03808, 0xd6f0380c, 0xd6f03810, + 0xd6f03814, 0xd6f03818, 0xd6f0381c, 0xd6f03820, + 0xd6f03824, 0xd6f03828, 0xd6f0382c, 0xd6f03830, + 0xd6f03834, 0xd6f03838, 0xd6f0383c, 0xd6f03840, + 0xd6f03844, 0xd6f03848, 0xd6f0384c, 0xd6f03850, + 0xc0983800, 0xc0983804, 0xc0983808, 0xc098380c, + 0xc0983810, 0xc0983814, 0xc0983818, 0xc098381c, + 0xc0983820, 0xc0983824, 0xc0983828, 0xc098382c, + 0xc0983830, 0xc0983834, 0xc0983838, 0xc098383c, + 0xc0983840, 0xc0583800, 0xc0583804, 0xc0583808, + 0xc058380c, 0xc0583810, 0xc0583814, 0xc0583818, + 0xc058381c, 0xc0583820, 0xc0583824, 0xc0583828, + 0xc058382c, 0xc0583830, 0xc0583834, 0xc0583838, + 0xc058383c, 0xc0583840, 0xc0583844, 0xc0583848, + 0xc058384c, 0xc0583850, 0xc0583854, 0xc0583858, + 0xc058385c, 0xc0583860, 0xc0583864, 0xc0583868, + 0xc058386c, 0xc0583870, 0xc0583874, 0xc0583878, + 0xc058387c, 0xc0583880, 0xc0583884, 0xc0583888, + 0xc058388c, 0xc0583890, 0xc0583894, 0xc0583898, + 0xc058389c, 0xc05838a0, 0xc05838a4, 0xc05838a8, + 0xc05838ac, 0xc05838b0, 0xc05838b4, 0xc05838b8, + 0xc05838bc, 0xc05838c0, 0xc05838c4, 0xc05838c8, + 0xc05838cc, 0xc05838d0, 0xc05838d4, 0xc05838d8, + 0xc05838dc, 0xc05838e0, 0xc05838e4, 0xc05838e8, + 0xc05838ec, 0xc05838f0, 0xc05838f4, 0xc05838f8, + 0xc05838fc, 0xc0583900, 0xc0583904, 0xc0583908, + 0xc058390c, 0xc0583910, 0xcb403800, 0xcb403804, + 0xcb403808, 0xcb40380c, 0xcb403810, 0xcb403814, + 0xcb403818, 0xcb40381c, 0xcb403820, 0xcb403824, + 0xcb403828, 0x1a803800, 0x1a803804, 0x1a803808, + 0x1a80380c, 0x1a803810, 0x1a803814, 0x1a803818, + 0x1a80381c, 0x1a803820, 0x1a803824, 0x1a803828, + 0x1a80382c, 0x1a803830, 0x1a803834, 0x1a803838, + 0x1a80383c, 0x1a803840, 0x1a803844, 0x1a803848, + 0x1a80384c, 0x1a803850, 0x1a803854, 0x1a803858, + 0x1a80385c, 0x1a803860, 0x1a803864, 0x1a803868, + 0x1a80386c, 0x1a803870, 0x1a803874, 0x1a803878, + 0x1a80387c, 0x1a803880, 0x1a803884, 0x1a803888, + 0x1a80388c, 0x1a803890, 0x1a803894, 0x1a803898, + 0x1a80389c, 0x1a8038a0, 0x1a8038a4, 0x1a8038a8, + 0x1a8038ac, 0x1a8038b0, 0x1a8038b4, 0x1a8038b8, + 0x1a8038bc, 0x1a8038c0, 0x1a8038c4, 0x1a8038c8, + 0x1a8038cc, 0x1a8038d0, 0x1a8038d4, 0x1a8038d8, + 0x1a8038dc, 0x1a8038e0, 0x1a8038e4, 0x1a8038e8, + 0x1a8038ec, 0x1a8038f0, 0x1a8038f4, 0x1a8038f8, + 0x1a8038fc, 0x1a803900, 0x1a803904, 0x1a803908, + 0x1a80390c, 0x1a803910, 0x1a803914, 0x1a803918, + 0x1a80391c, 0x1a803920, 0x1a803924, 0x1a803928, + 0x1a80392c, 0x1a803930, 0x1a803934, 0x1a803938, + 0x1a80393c, 0x1a803940, 0x1a803944, 0x1a803948, + 0x1a80394c, 0x1a803950, 0x1a803954, 0x1a803958, + 0x1a80395c, 0x1a803960, 0x1a803964, 0x1a803968, + 0x1a80396c, 0x1a803970, 0x1a803974, 0x1a803978, + 0x1a80397c, 0x1a803980, 0x1a803984, 0x1a803988, + 0x1a80398c, 0x1a803990, 0x1a803994, 0x18b43800, + 0x18b43804, 0x18b43808, 0x18b4380c, 0x18b43810, + 0x18b43814, 0x18b43818, 0x18b4381c, 0x18b43820, + 0x18b43824, 0x18b43828, 0x18b4382c, 0x18b43830, + 0x18b43834, 0x18b43838, 0x18b4383c, 0x18b43840, + 0x18b43844, 0x18b43848, 0x18b4384c, 0x18b43850, + 0x18b43854, 0x18b43858, 0x18b4385c, 0x18b43860, + 0x18b43864, 0x18b43868, 0x18b4386c, 0x18b43870, + 0x18b43874, 0x18b43878, 0x18b4387c, 0x18b43880, + 0x18b43884, 0x18b43888, 0x18b4388c, 0x18b43890, + 0x18b43894, 0x18b43898, 0x18b4389c, 0x18b438a0, + 0x18b438a4, 0x18b438a8, 0x18b438ac, 0x18b438b0, + 0x18b438b4, 0xc1283800, 0xc1283804, 0xc1283808, + 0xc128380c, 0xc1283810, 0xc1283814, 0xc1283818, + 0xc128381c, 0xc1283820, 0xc1283824, 0xc1283828, + 0xc128382c, 0xc1283830, 0xc1283834, 0xc1283838, + 0xc128383c, 0xc1283840, 0xc1283844, 0xc1283848, + 0xc128384c, 0xc1283850, 0xc1283854, 0xc1283858, + 0xc128385c, 0xc1283860, 0xc1283864, 0xc1283868, + 0xc128386c, 0xc1283870, 0xc1283874, 0xc1283878, + 0xc128387c, 0xc1283880, 0xc1283884, 0xc1283888, + 0xc128388c, 0xc1283890, 0xc1283894, 0xc1283898, + 0xc128389c, 0xc12838a0, 0xc12838a4, 0xc12838a8, + 0xc12838ac, 0xc12838b0, 0xc12838b4, 0xc12838b8, + 0xc12838bc, 0xc12838c0, 0xc12838c4, 0xc12838c8, + 0xc12838cc, 0xc12838d0, 0xc12838d4, 0xc12838d8, + 0xc12838dc, 0xc12838e0, 0xc12838e4, 0xc12838e8, + 0xc12838ec, 0xc12838f0, 0xc12838f4, 0xc12838f8, + 0xc6803800, 0xc6803804, 0xc6803808, 0xc680380c, + 0xc6803810, 0xc6803814, 0xc6803818, 0xc680381c, + 0xc6803820, 0xc6803824, 0xc6803828, 0xc680382c, + 0xc6803830, 0xc5803800, 0xc5803804, 0xc5803808, + 0xc580380c, 0xc5803810, 0xc5803814, 0xc5803818, + 0xc580381c, 0xc5803820, 0xc5803824, 0xc5803828, + 0xc580382c, 0xc5803830, 0xc5803834, 0xc5803838, + 0xc580383c, 0xc5803840, 0xc5803844, 0xc5803848, + 0xc580384c, 0xc5803850, 0xc5803854, 0xc5803858, + 0xc580385c, 0xc5803860, 0xc5803864, 0xc5803868, + 0xc580386c, 0xc5803870, 0xc5803874, 0xc5803878, + 0xc580387c, 0xc5803880, 0xc5803884, 0xc5803888, + 0xc580388c, 0xc5803890, 0xc5803894, 0xc5803898, + 0xc580389c, 0xc58038a0, 0xc58038a4, 0xc58038a8, + 0xc58038ac, 0xc58038b0, 0xc58038b4, 0xc58038b8, + 0xc58038bc, 0xc58038c0, 0xc58038c4, 0xc58038c8, + 0xc58038cc, 0xc58038d0, 0xc58038d4, 0xc58038d8, + 0xc58038dc, 0xc58038e0, 0xc58038e4, 0xc58038e8, + 0xc58038ec, 0xc58038f0, 0xc58038f4, 0xc58038f8, + 0xc58038fc, 0xc5803900, 0xc5803904, 0xc5803908, + 0xc580390c, 0xc5803910, 0xc5803914, 0xc5803918, + 0xc580391c, 0xc5803920, 0xc5803924, 0xc5803928, + 0xc580392c, 0xc5803930, 0xc5803934, 0xc5803938, + 0xc580393c, 0xc5803940, 0xc5803944, 0xc5803948, + 0xc580394c, 0xc5803950, 0xc5803954, 0xc5803958, + 0xc580395c, 0xc5803960, 0xc5803964, 0xc5803968, + 0xc580396c, 0xc5803970, 0xc5803974, 0xc5803978, + 0xc580397c, 0xc5803980, 0xc5803984, 0xc5803988, + 0xc580398c, 0xc5803990, 0xc5803994, 0xc5803998, + 0xc580399c, 0xc58039a0, 0xc58039a4, 0xc58039a8, + 0xc58039ac, 0xc58039b0, 0xc58039b4, 0xc58039b8, + 0xc58039bc, 0xc58039c0, 0xc58039c4, 0xc58039c8, + 0xc58039cc, 0xc58039d0, 0xc58039d4, 0xc58039d8, + 0xc58039dc, 0xc58039e0, 0xc58039e4, 0xc58039e8, + 0xc58039ec, 0xc58039f0, 0xc58039f4, 0xc58039f8, + 0xc58039fc, 0xc5803a00, 0xc5803a04, 0xc5803a08, + 0xc5803a0c, 0xc5803a10, 0xc5803a14, 0xc5803a18, + 0xc5803a1c, 0xc5803a20, 0xc5803a24, 0xc5803a28, + 0xc5803a2c, 0xc5803a30, 0xc5803a34, 0xc5803a38, + 0xc5803a3c, 0xc5803a40, 0xc5803a44, 0xc5803a48, + 0xc5803a4c, 0xc5803a50, 0xc5803a54, 0xc5803a58, + 0xc5803a5c, 0xc5803a60, 0xc5803a64, 0xc5803a68, + 0xc5803a6c, 0xc5803a70, 0xc5803a74, 0xc5803a78, + 0xc5803a7c, 0xc5803a80, 0xc5803a84, 0xc5803a88, + 0xc5803a8c, 0xc5803a90, 0xc5803a94, 0xc5803a98, + 0xc5803a9c, 0xc5803aa0, 0xc5803aa4, 0xc5803aa8, + 0xc5803aac, 0xc5803ab0, 0xc5803ab4, 0xc5803ab8, + 0xc5803abc, 0xc5803ac0, 0xc3023800, 0xc3023804, + 0xc3023808, 0xc302380c, 0xc3023810, 0xc3023814, + 0xc3023818, 0xc302381c, 0xc3023820, 0xc3023824, + 0xc3023828, 0xc302382c, 0xc3023830, 0xc3023834, + 0xc3023838, 0xc302383c, 0xc3023840, 0xc3423800, + 0xc3423804, 0xc3423808, 0xc342380c, 0xc3423810, + 0xc3423814, 0xc3423818, 0xc342381c, 0xc3423820, + 0xc3423824, 0xc3423828, 0xc342382c, 0xc3423830, + 0xc3423834, 0xc3423838, 0xc342383c, 0xc3423840, +}; + +#endif /* __GEN5_CM33_H__ */ diff --git a/board/renesas/geist/Kconfig b/board/renesas/geist/Kconfig new file mode 100644 index 00000000000..da36be0942f --- /dev/null +++ b/board/renesas/geist/Kconfig @@ -0,0 +1,15 @@ +if TARGET_GEIST + +config SYS_SOC + default "renesas" + +config SYS_BOARD + default "geist" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "geist" + +endif diff --git a/board/renesas/geist/Makefile b/board/renesas/geist/Makefile new file mode 100644 index 00000000000..3e33c91e9e7 --- /dev/null +++ b/board/renesas/geist/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2025-2026 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0-only +# + +ifndef CONFIG_XPL_BUILD +obj-y += geist.o +endif diff --git a/board/renesas/geist/geist.c b/board/renesas/geist/geist.c new file mode 100644 index 00000000000..09241aed14c --- /dev/null +++ b/board/renesas/geist/geist.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This file is Geist board support. + * + * Copyright (C) 2025-2026 Renesas Electronics Corporation + */ + +#include <asm/io.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/renesas.h> +#include <init.h> + +#define HSUSB_MSTP704 BIT(4) /* HSUSB */ + +/* HSUSB block registers */ +#define HSUSB_REG_LPSTS 0xE6590102 +#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) +#define HSUSB_REG_UGCTRL2 0xE6590184 +#define HSUSB_REG_UGCTRL2_USB0SEL 0x30 +#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 + +int board_init(void) +{ + /* USB1 pull-up */ + setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); + + /* Configure the HSUSB block */ + mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); + /* Choice USB0SEL */ + clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, + HSUSB_REG_UGCTRL2_USB0SEL_EHCI); + /* low power status */ + setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); + + return 0; +} diff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS index 4de97dbb0a4..7758ee9b930 100644 --- a/board/rockchip/evb_rk3229/MAINTAINERS +++ b/board/rockchip/evb_rk3229/MAINTAINERS @@ -1,7 +1,6 @@ EVB-RK3229 M: Kever Yang <[email protected]> S: Maintained -F: arch/arm/dts/rk3229-evb.dts F: arch/arm/dts/rk3229-evb-u-boot.dtsi F: board/rockchip/evb_rk3229 F: include/configs/evb_rk3229.h diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 8c9b42fe2bb..d8748c1c2a2 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,8 +4,7 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig -F: arch/arm/dts/rk3328-evb.dts -F: arch/arm/dts/rk3328-evb-u-boot.dtsi +F: arch/arm/dts/rk3328-evb* GENERIC-RK3328 M: Jonas Karlman <[email protected]> @@ -17,14 +16,12 @@ NANOPI-R2C-RK3328 M: Tianling Shen <[email protected]> S: Maintained F: configs/nanopi-r2c-rk3328_defconfig -F: arch/arm/dts/rk3328-nanopi-r2c.dts F: arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi NANOPI-R2C-PLUS-RK3328 M: Tianling Shen <[email protected]> S: Maintained F: configs/nanopi-r2c-plus-rk3328_defconfig -F: arch/arm/dts/rk3328-nanopi-r2c-plus.dts F: arch/arm/dts/rk3328-nanopi-r2c-plus-u-boot.dtsi NANOPI-R2S-RK3328 @@ -32,7 +29,6 @@ M: David Bauer <[email protected]> S: Maintained F: configs/nanopi-r2s-rk3328_defconfig F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi -F: arch/arm/dts/rk3328-nanopi-r2s.dts NANOPI-R2S-PLUS-RK3328 M: Jonas Karlman <[email protected]> @@ -44,14 +40,12 @@ ORANGEPI-R1-PLUS-RK3328 M: Tianling Shen <[email protected]> S: Maintained F: configs/orangepi-r1-plus-rk3328_defconfig -F: arch/arm/dts/rk3328-orangepi-r1-plus.dts F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi ORANGEPI-R1-PLUS-LTS-RK3328 M: Tianling Shen <[email protected]> S: Maintained F: configs/orangepi-r1-plus-lts-rk3328_defconfig -F: arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi ROC-RK3328-CC @@ -60,16 +54,14 @@ M: Chen-Yu Tsai <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/roc-cc-rk3328_defconfig -F: arch/arm/dts/rk3328-roc-cc.dts -F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +F: arch/arm/dts/rk3328-roc-cc* ROCK64-RK3328 M: Matwey V. Kornilov <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/rock64-rk3328_defconfig -F: arch/arm/dts/rk3328-rock64.dts -F: arch/arm/dts/rk3328-rock64-u-boot.dtsi +F: arch/arm/dts/rk3328-rock64* ROCKPIE-RK3328 M: Banglang Huang <[email protected]> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 8319db2e976..860dd028759 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -24,9 +24,7 @@ KHADAS-EDGE M: Nick Xie <[email protected]> S: Maintained F: configs/khadas-edge-rk3399_defconfig -F: arch/arm/dts/rk3399-khadas-edge.dts -F: arch/arm/dts/rk3399-khadas-edge.dtsi -F: arch/arm/dts/rk3399-khadas-edge-u-boot.dtsi +F: arch/arm/dts/rk3399-khadas-edge* KHADAS-EDGE-CAPTAIN M: Nick Xie <[email protected]> @@ -56,8 +54,7 @@ NANOPI-M4 M: Jagan Teki <[email protected]> S: Maintained F: configs/nanopi-m4-rk3399_defconfig -F: arch/arm/dts/rk3399-nanopi-m4.dts -F: arch/arm/dts/rk3399-nanopi-m4-u-boot.dtsi +F: arch/arm/dts/rk3399-nanopi-m4* NANOPI-M4-2GB M: Jagan Teki <[email protected]> diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 030cdbe6f3d..7e17a6a987a 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -2,8 +2,7 @@ BANANAPI-BPI-R2-PRO M: Frank Wunderlich <[email protected]> S: Maintained F: configs/bpi-r2-pro-rk3568_defconfig -F: arch/arm/dts/rk3568-bpi-r2-pro.dts -F: arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi +F: arch/arm/dts/rk3568-bpi-r2-pro* EVB-RK3568 M: Joseph Chen <[email protected]> @@ -11,78 +10,67 @@ S: Maintained F: board/rockchip/evb_rk3568 F: include/configs/evb_rk3568.h F: configs/evb-rk3568_defconfig -F: arch/arm/dts/rk3568-evb-u-boot.dtsi -F: arch/arm/dts/rk3568-evb.dts +F: arch/arm/dts/rk3568-evb* FASTRHINO-R66S-RK3568 M: Tianling Shen <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/fastrhino-r66s-rk3568_defconfig -F: arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi +F: arch/arm/dts/rk3568-fastrhino-r66s* GENERIC-RK3568 M: Jonas Karlman <[email protected]> S: Maintained F: configs/generic-rk3568_defconfig -F: arch/arm/dts/rk3568-generic.dts -F: arch/arm/dts/rk3568-generic-u-boot.dtsi +F: arch/arm/dts/rk3568-generic* LUBANCAT-2 M: Andy Yan <[email protected]> S: Maintained F: configs/lubancat-2-rk3568_defconfig -F: arch/arm/dts/rk3568-lubancat-2.dts -F: arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi +F: arch/arm/dts/rk3568-lubancat-2* NANOPI-R3S M: Tianling Shen <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/nanopi-r3s-rk3566_defconfig -F: arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi +F: arch/arm/dts/rk3566-nanopi-r3s* NANOPI-R5C M: Tianling Shen <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/nanopi-r5c-rk3568_defconfig -F: arch/arm/dts/rk3568-nanopi-r5c.dts -F: arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi +F: arch/arm/dts/rk3568-nanopi-r5c* NANOPI-R5S M: Tianling Shen <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/nanopi-r5s-rk3568_defconfig -F: arch/arm/dts/rk3568-nanopi-r5s.dts -F: arch/arm/dts/rk3568-nanopi-r5s.dtsi -F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi +F: arch/arm/dts/rk3568-nanopi-r5s* RADXA-CM3-IO M: Jagan Teki <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/radxa-cm3-io-rk3566_defconfig -F: arch/arm/dts/rk3566-radxa-cm3.dtsi -F: arch/arm/dts/rk3566-radxa-cm3-io.dts -F: arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi +F: arch/arm/dts/rk3566-radxa-cm3-io* RADXA-E25 M: Jonas Karlman <[email protected]> S: Maintained F: configs/radxa-e25-rk3568_defconfig -F: arch/arm/dts/rk3568-radxa-cm3i.dtsi -F: arch/arm/dts/rk3568-radxa-e25.dts -F: arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi +F: arch/arm/dts/rk3568-radxa-e25* ROCK-3A M: Akash Gajjar <[email protected]> R: Jonas Karlman <[email protected]> S: Maintained F: configs/rock-3a-rk3568_defconfig -F: arch/arm/dts/rk3568-rock-3a.dts -F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +F: arch/arm/dts/rk3568-rock-3a* ROCK-3B M: Jonas Karlman <[email protected]> @@ -94,11 +82,11 @@ ROCK-3C M: Jonas Karlman <[email protected]> M: Maxim Moskalets <[email protected]> S: Maintained -F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi +F: arch/arm/dts/rk3566-rock-3c* F: configs/rock-3c-rk3566_defconfig LCKFB-TaishanPi M: Jiehui He <[email protected]> S: Maintained F: configs/lckfb-tspi-rk3566_defconfig -F: arch/arm/dts/rk3566-lckfb-tspi-u-boot.dtsi +F: arch/arm/dts/rk3566-lckfb-tspi* diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 8b11db43f5f..b64dd4947ee 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -2,16 +2,13 @@ COOLPI-4B-RK3588S M: Andy Yan <[email protected]> S: Maintained F: configs/coolpi-4b-rk3588s_defconfig -F: arch/arm/dts/rk3588s-coolpi-4b.dts -F: arch/arm/dts/rk3588s-coolpi-u-boot.dtsi +F: arch/arm/dts/rk3588s-coolpi-4b* COOLPI-CM5-EVB-RK3588 M: Andy Yan <[email protected]> S: Maintained F: configs/coolpi-cm5-evb-rk3588_defconfig -F: arch/arm/dts/rk3588-coolpi-cm5.dtsi -F: arch/arm/dts/rk3588-coolpi-cm5-evb.dts -F: arch/arm/dts/rk3588-coolpi-cm5-evb-u-boot.dtsi +F: arch/arm/dts/rk3588-coolpi-cm5-evb* EVB-RK3588 M: Kever Yang <[email protected]> @@ -19,15 +16,13 @@ S: Maintained F: board/rockchip/evb_rk3588 F: include/configs/evb_rk3588.h F: configs/evb-rk3588_defconfig -F: arch/arm/dts/rk3588-evb1-v10.dts -F: arch/arm/dts/rk3588-evb1-v10-u-boot.dtsi +F: arch/arm/dts/rk3588-evb1-v10* GENERIC-RK3588 M: Jonas Karlman <[email protected]> S: Maintained F: configs/generic-rk3588_defconfig -F: arch/arm/dts/rk3588-generic.dts -F: arch/arm/dts/rk3588-generic-u-boot.dtsi +F: arch/arm/dts/rk3588-generic* MNT-REFORM2-RK3588 M: Peter Robinson <[email protected]> @@ -38,24 +33,22 @@ ORANGEPI-5-RK3588 M: Jonas Karlman <[email protected]> S: Maintained F: configs/orangepi-5-rk3588s_defconfig -F: arch/arm/dts/rk3588s-orangepi-5.dts F: arch/arm/dts/rk3588s-orangepi-5-u-boot.dtsi ORANGEPI-5-MAX-RK3588 M: Ilya Katsnelson <[email protected]> S: Maintained F: configs/orangepi-5-max-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-max-u-boot.dtsi +F: arch/arm/dts/rk3588-orangepi-5-max* ORANGEPI-5-PLUS-RK3588 M: Jonas Karlman <[email protected]> S: Maintained F: configs/orangepi-5-plus-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-plus.dts -F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi +F: arch/arm/dts/rk3588-orangepi-5-plus* ORANGEPI-5-RK3588-ULTRA M: Niu Zhihong <[email protected]> S: Maintained F: configs/orangepi-5-ultra-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi +F: arch/arm/dts/rk3588-orangepi-5-ultra* diff --git a/board/rockchip/toybrick_rk3588/MAINTAINERS b/board/rockchip/toybrick_rk3588/MAINTAINERS index cd4401c24f3..e2c76f80e9b 100644 --- a/board/rockchip/toybrick_rk3588/MAINTAINERS +++ b/board/rockchip/toybrick_rk3588/MAINTAINERS @@ -4,5 +4,4 @@ S: Maintained F: board/rockchip/toybrick_rk3588 F: include/configs/toybrick_rk3588.h F: configs/toybrick-rk3588_defconfig -F: arch/arm/dts/rk3588-toybrick-x0.dts -F: arch/arm/dts/rk3588-toybrick-x0-u-boot.dtsi +F: arch/arm/dts/rk3588-toybrick-x0* diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c index ee0ad20ced4..200562482af 100644 --- a/board/ronetix/imx8mq-cm/spl.c +++ b/board/ronetix/imx8mq-cm/spl.c @@ -18,8 +18,6 @@ #include <linux/delay.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - static void spl_dram_init(void) { /* ddr init */ @@ -135,9 +133,6 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - arch_cpu_init(); init_uart_clk(0); diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index ee578749bce..1f78654b685 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -76,11 +76,6 @@ static void pm9261_nand_hw_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* arch number of PM9261-Board */ diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 8125f064cf1..cc58e0f3a38 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -70,11 +70,6 @@ static void pm9263_nand_hw_init(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* arch number of PM9263 Board */ diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index c75f4a0d084..79cf34b40eb 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -232,7 +232,7 @@ void set_board_info_env(void) env_set("seboot_version", buf); env_set("fw_version", PLAIN_VERSION); - if (IS_ENABLED(CONFIG_NET)) { + if (IS_ENABLED(CONFIG_NET_LEGACY)) { int mac_cnt; mac_cnt = sysinfo_get_item_count(sysinfo, SYSID_BOARD_MAC_ADDR); diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile index d0525eba853..18ada7d72ff 100644 --- a/board/sophgo/milkv_duo/Makefile +++ b/board/sophgo/milkv_duo/Makefile @@ -3,4 +3,4 @@ # Copyright (c) 2024, Kongyang Liu <[email protected]> obj-y += board.o -obj-$(CONFIG_NET) += ethernet.o +obj-$(CONFIG_NET_LEGACY) += ethernet.o diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c index 9adbb08f5ce..f0944859b58 100644 --- a/board/sophgo/milkv_duo/board.c +++ b/board/sophgo/milkv_duo/board.c @@ -12,7 +12,7 @@ int board_init(void) if (IS_ENABLED(CONFIG_SYSRESET_CV1800B)) device_bind_driver(gd->dm_root, "cv1800b_sysreset", "sysreset", NULL); - if (IS_ENABLED(CONFIG_NET)) + if (IS_ENABLED(CONFIG_NET_LEGACY)) cv1800b_ephy_init(); return 0; diff --git a/board/st/common/Makefile b/board/st/common/Makefile index 122b13c3aa8..36dfaddfa0e 100644 --- a/board/st/common/Makefile +++ b/board/st/common/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o ifeq ($(CONFIG_ARCH_STM32MP),y) obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o obj-$(CONFIG_$(PHASE_)DFU_VIRT) += stm32mp_dfu_virt.o +obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += stm32mp_fwu.o endif obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o diff --git a/board/st/common/stm32mp_fwu.c b/board/st/common/stm32mp_fwu.c new file mode 100644 index 00000000000..ac7ca6bdca2 --- /dev/null +++ b/board/st/common/stm32mp_fwu.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <[email protected]> + */ + +#include <fwu.h> +#include <part_efi.h> +#include <asm/io.h> +/** + * fwu_plat_get_bootidx() - Get the value of the boot index + * @boot_idx: Boot index value + * + * Get the value of the bank(partition) from which the platform + * has booted. This value is passed to U-Boot from the earlier + * stage bootloader which loads and boots all the relevant + * firmware images + * + */ +void fwu_plat_get_bootidx(uint *boot_idx) +{ + *boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >> + TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; +} + +int fwu_platform_hook(struct udevice *dev, struct fwu_data *data) +{ + uint boot_idx; + efi_guid_t boot_uuid, root_uuid; + const efi_guid_t boot_type_guid = PARTITION_XBOOTLDR; + const efi_guid_t root_type_guid = + PARTITION_LINUX_FILE_SYSTEM_DATA_GUID; + char uuidbuf[UUID_STR_LEN + 1]; + int retb, retr; + + fwu_plat_get_bootidx(&boot_idx); + + retb = fwu_mdata_get_image_guid(&boot_uuid, &boot_type_guid, boot_idx); + retr = fwu_mdata_get_image_guid(&root_uuid, &root_type_guid, boot_idx); + + if (!retb && !retr) { + uuid_bin_to_str(boot_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID); + env_set("boot_partuuid", uuidbuf); + + uuid_bin_to_str(root_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID); + env_set("root_partuuid", uuidbuf); + } else if (!retb && retr) { + log_warning("%s: found boot GUID but missing root GUID (%d)\n", + __func__, retr); + } else if (!retr && retb) { + log_warning("%s: found root GUID but missing boot GUID (%d)\n", + __func__, retb); + } + + return 0; +} diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 244bb5eefb3..8b1b2333779 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -32,11 +32,6 @@ int dram_init_banksize(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - int board_late_init(void) { return 0; diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 5f7c6822116..9b933a2ba0b 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -326,8 +326,8 @@ static int adc_measurement(ofnode node, int adc_count, int *min_uV, int *max_uV) static int board_check_usb_power(void) { ofnode node; - int max_uV = 0; - int min_uV = USB_START_HIGH_THRESHOLD_UV; + int max_uV; + int min_uV; int adc_count, ret; u32 nb_blink; u8 i; @@ -358,6 +358,9 @@ static int board_check_usb_power(void) /* perform maximum of 2 ADC measurements to detect power supply current */ for (i = 0; i < 2; i++) { + max_uV = 0; + min_uV = USB_START_HIGH_THRESHOLD_UV; + ret = adc_measurement(node, adc_count, &min_uV, &max_uV); if (ret) return ret; @@ -834,24 +837,3 @@ static void board_copro_image_process(ulong fw_image, size_t fw_size) } U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process); - -#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) - -#include <fwu.h> - -/** - * fwu_plat_get_bootidx() - Get the value of the boot index - * @boot_idx: Boot index value - * - * Get the value of the bank(partition) from which the platform - * has booted. This value is passed to U-Boot from the earlier - * stage bootloader which loads and boots all the relevant - * firmware images - * - */ -void fwu_plat_get_bootidx(uint *boot_idx) -{ - *boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >> - TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; -} -#endif /* CONFIG_FWU_MULTI_BANK_UPDATE */ diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c index 43bc583378e..7bc7d2a608f 100644 --- a/board/st/stm32mp2/stm32mp2.c +++ b/board/st/stm32mp2/stm32mp2.c @@ -188,24 +188,3 @@ void board_quiesce_devices(void) { led_boot_off(); } - -#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) - -#include <fwu.h> - -/** - * fwu_plat_get_bootidx() - Get the value of the boot index - * @boot_idx: Boot index value - * - * Get the value of the bank(partition) from which the platform - * has booted. This value is passed to U-Boot from the earlier - * stage bootloader which loads and boots all the relevant - * firmware images - * - */ -void fwu_plat_get_bootidx(uint *boot_idx) -{ - *boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >> - TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; -} -#endif /* CONFIG_FWU_MULTI_BANK_UPDATE */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index d7722d1858a..3d1afec7c66 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -563,8 +563,8 @@ static void sunxi_spl_store_dram_size(phys_addr_t dram_size) static void status_led_init(void) { #if CONFIG_IS_ENABLED(SUNXI_LED_STATUS) - unsigned int state = CONFIG_SPL_SUNXI_LED_STATUS_STATE; - unsigned int gpio = CONFIG_SPL_SUNXI_LED_STATUS_BIT; + unsigned int state = IS_ENABLED(CONFIG_SPL_SUNXI_LED_STATUS_ACTIVE_HIGH); + unsigned int gpio = CONFIG_SPL_SUNXI_LED_STATUS_GPIO; gpio_request(gpio, "gpio_led"); gpio_direction_output(gpio, state); diff --git a/board/technexion/pico-imx8mq/spl.c b/board/technexion/pico-imx8mq/spl.c index c9d68b402ae..eed7f70e833 100644 --- a/board/technexion/pico-imx8mq/spl.c +++ b/board/technexion/pico-imx8mq/spl.c @@ -10,7 +10,6 @@ #include <asm/arch/ddr.h> #include <asm/arch/imx8mq_pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/io.h> #include <asm/mach-imx/gpio.h> #include <asm/mach-imx/iomux-v3.h> @@ -24,8 +23,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - #define DDR_DET_1 IMX_GPIO_NR(3, 11) #define DDR_DET_2 IMX_GPIO_NR(3, 12) #define DDR_DET_3 IMX_GPIO_NR(3, 13) @@ -196,9 +193,6 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - arch_cpu_init(); init_uart_clk(0); diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 2f5ad769b9b..e5c78e9c064 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -20,7 +20,7 @@ #include <asm/arch/soc.h> #include <linux/delay.h> #include <linux/mbus.h> -#ifdef CONFIG_NET +#ifdef CONFIG_NET_LEGACY #include <netdev.h> #endif #include <u-boot/crc.h> @@ -244,7 +244,7 @@ int checkboard(void) return 0; } -#ifdef CONFIG_NET +#ifdef CONFIG_NET_LEGACY int board_eth_init(struct bd_info *bis) { cpu_eth_init(bis); /* Built in controller(s) come first */ diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 90e37a8d913..b5f69a45a7c 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -911,7 +911,7 @@ int board_late_init(void) #endif /* CPSW plat */ -#if (CONFIG_IS_ENABLED(NET) || CONFIG_IS_ENABLED(NET_LWIP)) && \ +#if CONFIG_IS_ENABLED(NET) && \ !CONFIG_IS_ENABLED(OF_CONTROL) struct cpsw_slave_data slave_data[] = { { diff --git a/board/ti/am57xx/am57xx.env b/board/ti/am57xx/am57xx.env index a7cbbced099..4f712c5575a 100644 --- a/board/ti/am57xx/am57xx.env +++ b/board/ti/am57xx/am57xx.env @@ -2,6 +2,7 @@ #include <env/ti/mmc.env> #include <env/ti/dfu.env> +bootm_size=0x10000000 bootpart=0:2 bootdir=/boot get_name_kern= diff --git a/board/ti/common/cape_detect.c b/board/ti/common/cape_detect.c index 88fa6ae81f0..65bd6ef39ec 100644 --- a/board/ti/common/cape_detect.c +++ b/board/ti/common/cape_detect.c @@ -13,6 +13,44 @@ #include "cape_detect.h" +struct name_mapping { + char part_number[17]; + char version[5]; + char overlay[64]; +}; + +static struct name_mapping extension_mapping[] = { + { + "BB-GREEN-HDMI", + "00A0", + "am335x-bone-hdmi-00a0.dtbo", + } +}; + +static void set_cape_overlay(char *overlay, char *part_number, char *version) +{ + struct name_mapping *mapping; + + for (int i = 0; i < ARRAY_SIZE(extension_mapping); i++) { + mapping = &extension_mapping[i]; + + if (strncmp(mapping->part_number, part_number, + sizeof(mapping->part_number))) + continue; + + if (strncmp(mapping->version, version, + sizeof(mapping->version))) + continue; + + strlcpy(overlay, mapping->overlay, sizeof(mapping->overlay)); + return; + } + + /* Use default name extracted from the EEPROM */ + snprintf(overlay, sizeof(extension_mapping[0].overlay), "%s-%s.dtbo", + part_number, version); +} + static void sanitize_field(char *text, size_t size) { char *c = NULL; @@ -82,8 +120,8 @@ static int ti_extension_board_scan(struct udevice *dev, printf("BeagleBone Cape: %s (0x%x)\n", eeprom_header.board_name, addr); - snprintf(cape.overlay, sizeof(cape.overlay), "%s-%s.dtbo", - process_cape_part_number, process_cape_version); + set_cape_overlay(cape.overlay, process_cape_part_number, + process_cape_version); strlcpy(cape.name, eeprom_header.board_name, sizeof(eeprom_header.board_name)); strlcpy(cape.version, process_cape_version, diff --git a/board/toradex/aquila-am69/MAINTAINERS b/board/toradex/aquila-am69/MAINTAINERS index f629ba4a019..014e7e99b0b 100644 --- a/board/toradex/aquila-am69/MAINTAINERS +++ b/board/toradex/aquila-am69/MAINTAINERS @@ -3,9 +3,7 @@ M: Francesco Dolcini <[email protected]> W: https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 S: Maintained F: arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi -F: arch/arm/dts/k3-am69-aquila-dev.dts F: arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi -F: arch/arm/dts/k3-am69-aquila.dtsi F: arch/arm/dts/k3-am69-r5-aquila-dev.dts F: board/toradex/aquila-am69 F: configs/aquila-am69_a72_defconfig diff --git a/board/toradex/aquila-am69/aquila-am69.c b/board/toradex/aquila-am69/aquila-am69.c index 0c7123a059e..45fba1bbfe8 100644 --- a/board/toradex/aquila-am69/aquila-am69.c +++ b/board/toradex/aquila-am69/aquila-am69.c @@ -15,6 +15,7 @@ #include <i2c.h> #include <linux/sizes.h> #include <spl.h> +#include <asm/arch/k3-ddr.h> #include "../common/tdx-common.h" #include "aquila_ddrs.h" @@ -30,46 +31,24 @@ #define HW_CFG_MEM_CFG_MASK 0x03 DECLARE_GLOBAL_DATA_PTR; -static u8 hw_cfg; -static u8 aquila_am69_memory_cfg(void) -{ - return hw_cfg & HW_CFG_MEM_CFG_MASK; -} - -static u64 aquila_am69_memory_size(void) -{ - switch (aquila_am69_memory_cfg()) { - case HW_CFG_MEM_SZ_32GB: - return SZ_32G; - case HW_CFG_MEM_SZ_16GB_RANK_2: - case HW_CFG_MEM_SZ_16GB: - return SZ_16G; - case HW_CFG_MEM_SZ_8GB: - return SZ_8G; - default: - puts("Invalid memory size configuration\n"); - return -EINVAL; - } -} - -static void read_hw_cfg(void) +static u8 get_hw_cfg(void) { struct gpio_desc gpio_hw_cfg; char gpio_name[20]; + u8 hw_cfg = 0; int i; - printf("HW CFG: "); for (i = 0; i < 5; i++) { sprintf(gpio_name, "gpio@42110000_%d", 82 + i); if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) { printf("Lookup named gpio error\n"); - return; + return 0; } if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) { printf("gpio request error\n"); - return; + return 0; } if (dm_gpio_get_value(&gpio_hw_cfg) == 1) @@ -77,15 +56,34 @@ static void read_hw_cfg(void) dm_gpio_free(NULL, &gpio_hw_cfg); } - printf("0x%02x\n", hw_cfg); + return hw_cfg; } -static void update_ddr_timings(void) +static u64 aquila_am69_memory_size(void) +{ + u8 hw_cfg = get_hw_cfg(); + + switch (hw_cfg & HW_CFG_MEM_CFG_MASK) { + case HW_CFG_MEM_SZ_32GB: + return SZ_32G; + case HW_CFG_MEM_SZ_16GB_RANK_2: + case HW_CFG_MEM_SZ_16GB: + return SZ_16G; + case HW_CFG_MEM_SZ_8GB: + return SZ_8G; + default: + puts("Invalid memory size configuration\n"); + return -EINVAL; + } +} + +#if defined(CONFIG_TARGET_AQUILA_AM69_R5) +static void update_ddr_timings(u8 hw_cfg) { int ret = 0; void *fdt = (void *)gd->fdt_blob; - switch (aquila_am69_memory_cfg()) { + switch (hw_cfg & HW_CFG_MEM_CFG_MASK) { case HW_CFG_MEM_SZ_8GB: ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB, MULTI_DDR_CFG_INTRLV_SIZE_8GB); @@ -103,6 +101,7 @@ static void update_ddr_timings(void) if (ret) printf("Applying DDR patch error: %d\n", ret); } +#endif static int aquila_am69_fdt_fixup_memory_size(u64 total_sz) { @@ -121,21 +120,33 @@ static int aquila_am69_fdt_fixup_memory_size(u64 total_sz) return fdt_fixup_memory_banks(blob, s, e, CONFIG_NR_DRAM_BANKS); } +#if defined(CONFIG_TARGET_AQUILA_AM69_R5) void do_board_detect(void) { + u8 hw_cfg; + /* MCU_ADC1 pins used as General Purpose Inputs */ writel(readl(CTRL_MMR_CFG0_MCU_ADC1_CTRL) | BIT(16), CTRL_MMR_CFG0_MCU_ADC1_CTRL); - read_hw_cfg(); + hw_cfg = get_hw_cfg(); + printf("HW CFG: 0x%02x\n", hw_cfg); if (IS_ENABLED(CONFIG_K3_DDRSS)) - update_ddr_timings(); + update_ddr_timings(hw_cfg); } +#endif + +#if defined(CONFIG_XPL_BUILD) +void spl_perform_board_fixups(struct spl_image_info *spl_image) +{ + fixup_memory_node(spl_image); +} +#endif int dram_init(void) { - s32 ret; + int ret; ret = fdtdec_setup_mem_size_base_lowest(); if (ret) @@ -146,11 +157,18 @@ int dram_init(void) int dram_init_banksize(void) { - s32 ret; + int ret; - ret = aquila_am69_fdt_fixup_memory_size(aquila_am69_memory_size()); - if (ret) - printf("Error setting memory size. %d\n", ret); + if (IS_ENABLED(CONFIG_SPL_BUILD) && + IS_ENABLED(CONFIG_TARGET_AQUILA_AM69_A72)) { + u64 mem_sz = aquila_am69_memory_size(); + + ret = aquila_am69_fdt_fixup_memory_size(mem_sz); + if (ret) + printf("Error setting memory size. %d\n", ret); + } else { + fdtdec_setup_mem_size_base(); + } ret = fdtdec_setup_memory_banksize(); if (ret) diff --git a/board/toradex/aquila-am69/aquila-am69.env b/board/toradex/aquila-am69/aquila-am69.env index f8b7363dcf5..5371f7c5410 100644 --- a/board/toradex/aquila-am69/aquila-am69.env +++ b/board/toradex/aquila-am69/aquila-am69.env @@ -1,3 +1,5 @@ +#include <env/ti/k3_rproc.env> + #define CFG_RAMDISK_ADDR_R 0x90300000 #define CFG_SCRIPTADDR 0x90280000 @@ -21,21 +23,40 @@ dfu_alt_info_ram= update_tiboot3= askenv confirm Did you load tiboot3.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; fi update_tispl= askenv confirm Did you load tispl.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt}; fi update_uboot= askenv confirm Did you load u-boot.img (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt}; fi + +rprocsemmcboot= + env set boot mmc; + env set bootpart 0:2; + rproc init; + run boot_rprocs_mmc; + env set bootpart; + +rproc_fw_binaries= \ + 2 /lib/firmware/j784s4-main-r5f0_0-fw \ + 3 /lib/firmware/j784s4-main-r5f0_1-fw \ + 4 /lib/firmware/j784s4-main-r5f1_0-fw \ + 5 /lib/firmware/j784s4-main-r5f1_1-fw \ + 6 /lib/firmware/j784s4-main-r5f2_0-fw \ + 7 /lib/firmware/j784s4-main-r5f2_1-fw \ + 8 /lib/firmware/j784s4-c71_0-fw \ + 9 /lib/firmware/j784s4-c71_1-fw \ + 10 /lib/firmware/j784s4-c71_2-fw \ + 11 /lib/firmware/j784s4-c71_3-fw diff --git a/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c index c24e22b620b..66e800ef7c8 100644 --- a/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c +++ b/board/toradex/aquila-am69/aquila_ddrs_16GB_rank_2.c @@ -14,7 +14,7 @@ #include <linux/kernel.h> #include "ddrs_patch.h" -#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FHS_CNT 5 #define DDRSS_CTL_268_DATA 0x01010000 #define DDRSS_CTL_270_DATA 0x00000FFF diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index c8c10742103..896a0d3bd12 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -187,6 +187,9 @@ const struct toradex_som toradex_modules[] = { { OSM_IMX91S_2GB_IT, "OSM iMX91 Solo 2GB IT", TARGET_IS_ENABLED(TORADEX_OSM_IMX91) }, { VERDIN_AM62D_1G_ET_GPU_NODSI, "Verdin AM62 Dual 1GB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, { AQUILA_TDA4O_16GB_IT, "Aquila TDA4 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { VERDIN_IMX95H_4G_WB_IT, "Verdin iMX95 Hexa 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, + { VERDIN_IMX95H_4G_ET, "Verdin iMX95 Hexa 4GB ET", TARGET_IS_ENABLED(VERDIN_IMX95) }, + { VERDIN_IMX95H_16G_IT, "Verdin iMX95 Hexa 16GB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 3022ef615ad..9a96bddfbe1 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -150,6 +150,9 @@ enum { OSM_IMX91S_2GB_IT, /* 220 */ VERDIN_AM62D_1G_ET_GPU_NODSI, AQUILA_TDA4O_16GB_IT = 223, + VERDIN_IMX95H_4G_WB_IT = 226, + VERDIN_IMX95H_4G_ET, + VERDIN_IMX95H_16G_IT, }; enum { diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.env b/board/toradex/smarc-imx8mp/smarc-imx8mp.env index 58f152e6b51..1480db8e5fc 100644 --- a/board/toradex/smarc-imx8mp/smarc-imx8mp.env +++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.env @@ -13,7 +13,7 @@ scriptaddr=0x50280000 update_uboot= askenv confirm Did you load flash.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; diff --git a/board/toradex/smarc-imx95/smarc-imx95.env b/board/toradex/smarc-imx95/smarc-imx95.env index b94250bbc52..35d26b7cfba 100644 --- a/board/toradex/smarc-imx95/smarc-imx95.env +++ b/board/toradex/smarc-imx95/smarc-imx95.env @@ -13,7 +13,7 @@ scriptaddr=0x9c600000 update_uboot= askenv confirm Did you load flash.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; diff --git a/board/toradex/verdin-am62p/verdin-am62p.env b/board/toradex/verdin-am62p/verdin-am62p.env index f8b7363dcf5..ac2828e0b58 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.env +++ b/board/toradex/verdin-am62p/verdin-am62p.env @@ -21,21 +21,21 @@ dfu_alt_info_ram= update_tiboot3= askenv confirm Did you load tiboot3.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; fi update_tispl= askenv confirm Did you load tispl.bin (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt}; fi update_uboot= askenv confirm Did you load u-boot.img (y/N)?; - if test $confirm = y; then + if test "$confirm" = y; then setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt}; fi diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 59b4607f065..69c3408fbba 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -46,7 +46,7 @@ static void setup_fec(void) setbits_le32(&gpr->gpr[1], BIT(22)); } -#if IS_ENABLED(CONFIG_NET) +#if IS_ENABLED(CONFIG_NET_LEGACY) int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) diff --git a/board/toradex/verdin-imx95/Kconfig b/board/toradex/verdin-imx95/Kconfig new file mode 100644 index 00000000000..ef4206c343c --- /dev/null +++ b/board/toradex/verdin-imx95/Kconfig @@ -0,0 +1,36 @@ +if TARGET_VERDIN_IMX95 + +config SYS_BOARD + default "verdin-imx95" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "verdin-imx95" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/verdin-imx95/MAINTAINERS b/board/toradex/verdin-imx95/MAINTAINERS new file mode 100644 index 00000000000..d19ee3ebfe5 --- /dev/null +++ b/board/toradex/verdin-imx95/MAINTAINERS @@ -0,0 +1,13 @@ +Verdin iMX95 +F: arch/arm/dts/imx95-verdin.dtsi +F: arch/arm/dts/imx95-verdin-dev.dtsi +F: arch/arm/dts/imx95-verdin-wifi.dtsi +F: arch/arm/dts/imx95-verdin-wifi-dev.dts +F: arch/arm/dts/imx95-verdin-wifi-dev-u-boot.dtsi +F: board/toradex/verdin-imx95/ +F: configs/verdin-imx95_defconfig +F: doc/board/toradex/verdin-imx95.rst +F: include/configs/verdin-imx95.h +M: Francesco Dolcini <[email protected]> +S: Maintained +W: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 diff --git a/board/toradex/verdin-imx95/Makefile b/board/toradex/verdin-imx95/Makefile new file mode 100644 index 00000000000..bc1b6811bbe --- /dev/null +++ b/board/toradex/verdin-imx95/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (c) Toradex + +obj-y += verdin-imx95.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/toradex/verdin-imx95/spl.c b/board/toradex/verdin-imx95/spl.c new file mode 100644 index 00000000000..9f501c11c1d --- /dev/null +++ b/board/toradex/verdin-imx95/spl.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/sections.h> +#include <asm/global_data.h> +#include <clk.h> +#include <dm/uclass.h> +#include <hang.h> +#include <i2c.h> +#include <init.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION)) + spl_save_restore_data(); + + timer_init(); + + /* Need dm_init() to run before any SCMI calls */ + spl_early_init(); + + /* Need to enable SCMI drivers and ELE driver before console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* MU not probed, nothing can be outputed, hang */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/board/toradex/verdin-imx95/verdin-imx95.c b/board/toradex/verdin-imx95/verdin-imx95.c new file mode 100644 index 00000000000..7c0804c1d1c --- /dev/null +++ b/board/toradex/verdin-imx95/verdin-imx95.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <env.h> +#include <errno.h> +#include <fdt_support.h> +#include <init.h> +#include <stdio.h> +#include <string.h> + +#include "../common/tdx-cfg-block.h" +#include "../common/tdx-common.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + bool is_wifi = false; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a + * module with Wi-Fi/Bluetooth make sure we use the -wifi + * device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX95H_8G_WIFI_BT_IT) || + (tdx_hw_tag.prodid == VERDIN_IMX95H_4G_WB_IT); + } + + if (is_wifi) + strlcpy(&variant[0], "wifi", sizeof(variant)); + else + strlcpy(&variant[0], "nonwifi", sizeof(variant)); + + if (!env_variant || strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + } +} + +int board_late_init(void) +{ + select_dt_from_module_version(); + + return 0; +} + +static const struct ram_alias_check ram_alias_checks[] = { + { (void *)((uintptr_t)PHYS_SDRAM + SZ_8G), (void *)(PHYS_SDRAM), SZ_16G }, + { (void *)((uintptr_t)PHYS_SDRAM + SZ_4G), (void *)(PHYS_SDRAM), SZ_8G }, + { (void *)((uintptr_t)PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G }, + { (void *)((uintptr_t)PHYS_SDRAM + SZ_1G), (void *)(PHYS_SDRAM), SZ_2G }, + { NULL } +}; + +int board_phys_sdram_size(phys_size_t *size) +{ + phys_size_t sz; + + sz = probe_ram_size_by_alias(ram_alias_checks); + if (!sz) { + puts("## WARNING: Less than 2GB RAM detected\n"); + return -EINVAL; + } + + *size = sz - PHYS_SDRAM_FW_RSVD; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif diff --git a/board/toradex/verdin-imx95/verdin-imx95.env b/board/toradex/verdin-imx95/verdin-imx95.env new file mode 100644 index 00000000000..5ca6cb18aaa --- /dev/null +++ b/board/toradex/verdin-imx95/verdin-imx95.env @@ -0,0 +1,20 @@ +boot_scripts=boot.scr +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyLP2 +fdt_board=dev +fdt_addr=0x9c400000 +fdt_addr_r=0x9c400000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x94400000 +kernel_comp_size=0x8000000 +ramdisk_addr_r=0x9c800000 +scriptaddr=0x9c600000 + +update_uboot= + askenv confirm Did you load flash.bin (y/N)?; + if test "$confirm" = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 + ${blkcnt}; + fi diff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS index e6f3dc4da21..b31c5793432 100644 --- a/board/tq/MAINTAINERS +++ b/board/tq/MAINTAINERS @@ -6,3 +6,12 @@ W: https://www.tq-group.com/en/products/tq-embedded/ F: arch/arm/dts/*mba6*.dts* F: arch/arm/dts/*tqma6*.dts* F: configs/tqma6*config + +TQMA7 +M: Alexander Feilke <[email protected]> +S: Maintained +W: https://www.tq-group.com/en/products/tq-embedded/ +F: arch/arm/dts/*mba7*.dts* +F: arch/arm/dts/*tqma7*.dts* +F: configs/tqma7*config diff --git a/board/tq/common/Kconfig b/board/tq/common/Kconfig index a1896929ea3..2fe2ca30072 100644 --- a/board/tq/common/Kconfig +++ b/board/tq/common/Kconfig @@ -11,3 +11,6 @@ config TQ_COMMON_BB config TQ_COMMON_SDMMC bool + +config TQ_COMMON_SOM + bool diff --git a/board/tq/common/Makefile b/board/tq/common/Makefile index ac564a713fd..4af9207da4a 100644 --- a/board/tq/common/Makefile +++ b/board/tq/common/Makefile @@ -6,4 +6,5 @@ # obj-$(CONFIG_TQ_COMMON_BB) += tq_bb.o +obj-$(CONFIG_TQ_COMMON_SOM) += tq_som.o obj-$(CONFIG_TQ_COMMON_SDMMC) += tq_sdmmc.o diff --git a/board/tq/common/tq_som.c b/board/tq/common/tq_som.c new file mode 100644 index 00000000000..6fb4839109b --- /dev/null +++ b/board/tq/common/tq_som.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke, Max Merchel + */ + +#include <init.h> +#include <asm/io.h> +#include <linux/sizes.h> + +#include "tq_som.h" + +void __weak tq_som_ram_init(void) +{ + ; +} + +/* + * checks if the accessible range equals the requested RAM size. + * returns true if successful, false otherwise + */ +bool tq_som_ram_check_size(long ram_size) +{ + long size; + + size = get_ram_size((void *)PHYS_SDRAM, ram_size); + debug("SPL: requested RAM size %lu MiB. accessible %lu MiB\n", + ram_size / (SZ_1M), size / (SZ_1M)); + + return (size == ram_size); +} diff --git a/board/tq/common/tq_som.h b/board/tq/common/tq_som.h new file mode 100644 index 00000000000..0ab01d51f99 --- /dev/null +++ b/board/tq/common/tq_som.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke, Max Merchel + */ + +#ifndef __TQ_SOM_H +#define __TQ_SOM_H + +#include <init.h> +#include <asm/io.h> +#include <linux/iopoll.h> + +void tq_som_ram_init(void); + +/* used as a wrapper to write to specific register addresses */ +static inline void tq_som_init_write_reg(u32 address, u32 value) +{ + writel_relaxed(value, address); +} + +/* + * checks if the accessible range equals the requested ram size. + * returns true if successful, false otherwise + */ +bool tq_som_ram_check_size(long ram_size); + +static inline void tq_som_check_bits_set(u32 address, u32 mask) +{ + u32 val; + readl_poll_timeout(address, val, (val & mask) == mask, 1000); +} + +#endif /* __TQ_SOM_H */ diff --git a/board/tq/tqma7/Kconfig b/board/tq/tqma7/Kconfig new file mode 100644 index 00000000000..477ce3f3d53 --- /dev/null +++ b/board/tq/tqma7/Kconfig @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. +# Author: Markus Niebel, Steffen Doster +# + +if TARGET_TQMA7 + +config SYS_BOARD + default "tqma7" + +config SYS_VENDOR + default "tq" + +config SYS_CONFIG_NAME + default "tqma7" + +choice + prompt "TQMa7x RAM configuration" + default TQMA7_RAM_MULTI + help + Select RAM configuration. Normally use default here but for + specific setup it is possible to use a single RAM size. + +config TQMA7_RAM_MULTI + bool "TQMa7x with 512/1024/2048 MB RAM - Single image" + select TQMA7_RAM_2G + select TQMA7_RAM_1G + select TQMA7_RAM_512M + help + Build a single U-Boot solely for variants + with 512/1024/2048 MB RAM. + +config TQMA7_RAM_SINGLE_2G + bool "TQMa7x with 2 GB RAM" + select TQMA7_RAM_2G + help + Build U-Boot solely for variants + with 2 GB RAM. + +config TQMA7_RAM_SINGLE_1G + bool "TQMa7x with 1 GB RAM" + select TQMA7_RAM_1G + help + Build U-Boot solely for variants + with 1 GB RAM. + +config TQMA7_RAM_SINGLE_512M + bool "TQMa7x with 512 MB RAM" + select TQMA7_RAM_512M + help + Build U-Boot solely for variants + with 512 MB RAM. + +endchoice + +config TQMA7_RAM_2G + bool + +config TQMA7_RAM_1G + bool + +config TQMA7_RAM_512M + bool + +choice + prompt "TQMa7x base board variant" + default MBA7 + help + Select base board + for TQMa7x + +config MBA7 + bool "TQMa7x on MBa7x Starterkit" + select TQ_COMMON_BB + select TQ_COMMON_SOM + select TQ_COMMON_SYSINFO + select I2C_EEPROM + select MISC + imply USB + imply CMD_USB + imply USB_STORAGE + imply PHYLIB + imply CONFIG_PHY_TI_DP83867 + select MXC_UART + select DM_MMC + select DM_SPI + select DM_I2C + select DM_GPIO + imply DM_ETH + help + Select the MBa7x + starterkit. + +endchoice + +config IMX_CONFIG + default "board/tq/tqma7/tqma7.cfg" + +source "board/tq/common/Kconfig" + +endif diff --git a/board/tq/tqma7/Makefile b/board/tq/tqma7/Makefile new file mode 100644 index 00000000000..b1fb270e861 --- /dev/null +++ b/board/tq/tqma7/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. + + +obj-y += tqma7.o +obj-$(CONFIG_MBA7) += tqma7_mba7.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += spl_tqma7_ram.o +obj-$(CONFIG_MBA7) += spl_mba7.o +endif diff --git a/board/tq/tqma7/spl.c b/board/tq/tqma7/spl.c new file mode 100644 index 00000000000..62db30e81f2 --- /dev/null +++ b/board/tq/tqma7/spl.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + */ + +#include <fsl_esdhc_imx.h> +#include <hang.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch-mx7/mx7d_pins.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> + +#include "../common/tq_bb.h" +#include "../common/tq_som.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CMD_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | \ + PAD_CTL_SRE_SLOW | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_STROBE_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM) + +/* eMMC on USDHCI3 always present */ +static const iomux_v3_cfg_t tqma7_usdhc3_pads[] = { + NEW_PAD_CTRL(MX7D_PAD_SD3_CLK__SD3_CLK, USDHC_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_CMD__SD3_CMD, USDHC_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA0__SD3_DATA0, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA1__SD3_DATA1, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA2__SD3_DATA2, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA3__SD3_DATA3, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA4__SD3_DATA4, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA5__SD3_DATA5, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA6__SD3_DATA6, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_DATA7__SD3_DATA7, USDHC_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD3_STROBE__SD3_STROBE, USDHC_STROBE_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg tqma7_usdhc3_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is always present */ + ret = 1; + else + ret = tq_bb_board_mmc_getcd(mmc); + + return ret; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) + /* eMMC/uSDHC3 is not WP */ + ret = 0; + else + ret = tq_bb_board_mmc_getwp(mmc); + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(tqma7_usdhc3_pads, + ARRAY_SIZE(tqma7_usdhc3_pads)); + + tqma7_usdhc3_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + if (fsl_esdhc_initialize(bis, &tqma7_usdhc3_cfg)) + puts("Warning: failed to initialize eMMC dev\n"); + + tq_bb_board_mmc_init(bis); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return tq_bb_board_init(); +} + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + timer_init(); + + tq_bb_board_early_init_f(); + + preloader_console_init(); + + /* DDR initialization */ + tq_som_ram_init(); +} + diff --git a/board/tq/tqma7/spl_mba7.c b/board/tq/tqma7/spl_mba7.c new file mode 100644 index 00000000000..13438247731 --- /dev/null +++ b/board/tq/tqma7/spl_mba7.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + */ + +#include <fsl_esdhc_imx.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/arch-mx7/mx7d_pins.h> + +#include "../common/tq_bb.h" + +#define UART_RX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_PUE | PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +#define UART_TX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_PUE | PAD_CTL_SRE_SLOW) + +#define USDHC_DATA_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CMD_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define USDHC_STROBE_PAD_CTRL (PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM) + +#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_196OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW) +#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW) + +static const iomux_v3_cfg_t mba7_uart6_pads[] = { + NEW_PAD_CTRL(MX7D_PAD_EPDC_DATA08__UART6_DCE_RX, UART_RX_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_EPDC_DATA09__UART6_DCE_TX, UART_TX_PAD_CTRL), +}; + +static void mba7_setup_iomuxc_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(mba7_uart6_pads, ARRAY_SIZE(mba7_uart6_pads)); +} + +static const iomux_v3_cfg_t mba7_usdhc1_pads[] = { + NEW_PAD_CTRL(MX7D_PAD_SD1_CLK__SD1_CLK, USDHC_CLK_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_CMD__SD1_CMD, USDHC_CMD_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA0__SD1_DATA0, USDHC_DATA_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA1__SD1_DATA1, USDHC_DATA_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA2__SD1_DATA2, USDHC_DATA_PAD_CTRL), + NEW_PAD_CTRL(MX7D_PAD_SD1_DATA3__SD1_DATA3, USDHC_DATA_PAD_CTRL), + /* CD */ + NEW_PAD_CTRL(MX7D_PAD_SD1_CD_B__GPIO5_IO0, GPIO_IN_PAD_CTRL), + /* WP */ + NEW_PAD_CTRL(MX7D_PAD_SD1_WP__GPIO5_IO1, GPIO_IN_PAD_CTRL), +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC1_WP_GPIO IMX_GPIO_NR(5, 1) + +int tq_bb_board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = !gpio_get_value(USDHC1_CD_GPIO); + + return ret; +} + +int tq_bb_board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + if (cfg->esdhc_base == USDHC1_BASE_ADDR) + ret = gpio_get_value(USDHC1_WP_GPIO); + + return ret; +} + +static struct fsl_esdhc_cfg mba7_usdhc_cfg = { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, +}; + +int tq_bb_board_mmc_init(struct bd_info *bis) +{ + imx_iomux_v3_setup_multiple_pads(mba7_usdhc1_pads, + ARRAY_SIZE(mba7_usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1-cd"); + gpio_request(USDHC1_WP_GPIO, "usdhc1-wp"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_direction_input(USDHC1_WP_GPIO); + + mba7_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + if (fsl_esdhc_initialize(bis, &mba7_usdhc_cfg)) + puts("Warning: failed to initialize SD\n"); + + return 0; +} + +int tq_bb_board_early_init_f(void) +{ + /* iomux and setup of uart */ + mba7_setup_iomuxc_uart(); + + return 0; +} + +/* + * This is done per baseboard to allow different implementations + */ +void board_boot_order(u32 *spl_boot_list) +{ + enum boot_device bd; + /* + * try to get sd card slots in order: + * eMMC: on Module + * -> therefore index 0 for bootloader + * index n in kernel (controller instance 3) -> patches needed for + * alias indexing + * SD1: on Mainboard + * index n in kernel (controller instance 1) -> patches needed for + * alias indexing + * we assume to have a kernel patch that will present mmcblk dev + * indexed like controller devs + */ + puts("Boot: "); + + bd = get_boot_device(); + switch (bd) { + case MMC3_BOOT: + puts("USDHC3(eMMC)\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + case SD1_BOOT: + puts("USDHC1(SD)\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC2; + break; + case QSPI_BOOT: + puts("QSPI\n"); + spl_boot_list[0] = BOOT_DEVICE_NOR; + break; + case USB_BOOT: + puts("USB\n"); + spl_boot_list[0] = BOOT_DEVICE_BOARD; + break; + default: + /* Default - BOOT_DEVICE_MMC1 */ + puts("WARN: unknown boot device, fallback to eMMC\n"); + spl_boot_list[0] = BOOT_DEVICE_MMC1; + break; + } +} + +int board_fit_config_name_match(const char *name) +{ + char *config = NULL; + + if (is_cpu_type(MXC_CPU_MX7S)) + config = "imx7s-mba7"; + else if (is_cpu_type(MXC_CPU_MX7D)) + config = "imx7d-mba7"; + + if (strcmp(config, name)) + return -EINVAL; + + printf("Device tree: %s\n", name); + + return 0; +} diff --git a/board/tq/tqma7/spl_tqma7_ram.c b/board/tq/tqma7/spl_tqma7_ram.c new file mode 100644 index 00000000000..903df5d9d0f --- /dev/null +++ b/board/tq/tqma7/spl_tqma7_ram.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + */ + +#include <config.h> +#include <hang.h> +#include <asm/arch/imx-regs.h> +#include <asm/mach-imx/iomux-v3.h> +#include <linux/sizes.h> + +#include "../common/tq_som.h" + +#define DDRC_RFSHTMG_512M 0x0020002B +#define DDRC_RFSHTMG_1G 0x00200045 +#define DDRC_RFSHTMG_2G 0x0020005D + +#define DDRC_ADDRMAP1_512M 0x00161616 +#define DDRC_ADDRMAP1_1G 0x00171717 +#define DDRC_ADDRMAP1_2G 0x00181818 + +#define DDRC_ADDRMAP6_512M 0x0F0F0404 +#define DDRC_ADDRMAP6_1G 0x0F040404 +#define DDRC_ADDRMAP6_2G 0x04040404 + +#define DDR_PHY_OFFSET_RD_CON0_512M 0x0B0B0B0B +#define DDR_PHY_OFFSET_RD_CON0_1G 0x0B0B0B0B +#define DDR_PHY_OFFSET_RD_CON0_2G 0x0A0A0A0A + +#define DDR_PHY_OFFSET_WR_CON0_512M 0x06060606 +#define DDR_PHY_OFFSET_WR_CON0_1G 0x06060606 +#define DDR_PHY_OFFSET_WR_CON0_2G 0x04040404 + +static void tqma7_ddr_exit_retention(void) +{ + /* Clear then set bit30 to ensure exit from DDR retention */ + tq_som_init_write_reg(0x30360388, 0x40000000); + tq_som_init_write_reg(0x30360384, 0x40000000); +} + +static void gpr_init(void) +{ + /* reset default and enable GPR OCRAM EPDC */ + tq_som_init_write_reg(0x30340004, 0x4F400005); +} + +static void tqma7_ccgr_init(void) +{ + tq_som_init_write_reg(0x30384130, 0x00000000); /* CCM_CCGR19 */ + tq_som_init_write_reg(0x30340020, 0x00000178); /* IOMUXC_GPR_GPR8 */ + tq_som_init_write_reg(0x30384130, 0x00000002); /* CCM_CCGR19 */ + tq_som_init_write_reg(0x30790018, 0x0000000f); /* DDR_PHY_LP_CON0 */ + + /* wait for auto-ZQ calibration to complete */ + tq_som_check_bits_set(0x307a0004, 0x1); /* DDRC_STAT */ +} + +static void ddr_init_error(const char *msg) +{ + pr_err("%s", msg); + hang(); +} + +#define TQMA7_SELECT_DDR_VALUE(SIZE, NAME) \ + ((SIZE) == SZ_512M ? NAME ## _512M : \ + ((SIZE) == SZ_1G ? NAME ## _1G : \ + ((SIZE) == SZ_2G ? NAME ## _2G : \ + (ddr_init_error("Invalid DDR RAM size detected"), 0)))) + +static void tqma7_init_ddr_controller(u32 size) +{ + gpr_init(); + + /* TQMa7 DDR config */ + /* TQMa7x DRAM Timing REV0201A */ + /* DCD Code i.MX7D/S 528 MHz 512 MByte Samsung K4B2G1646F */ + tq_som_init_write_reg(0x30360070, 0x0070302C); /*CCM_ANALOG_PLL_DDRx*/ + tq_som_init_write_reg(0x30360090, 0x00000000); /*CCM_ANALOG_PLL_NUM*/ + tq_som_init_write_reg(0x30360070, 0x0060302C); /*CCM_ANALOG_PLL_DDRx*/ + + tq_som_check_bits_set(0x30360070, 0x80000000); + + tq_som_init_write_reg(0x30391000, 0x00000002); /*SRC_DDRC_RCR*/ + tq_som_init_write_reg(0x307a0000, 0x01040001); /*DDRC_MSTR*/ + tq_som_init_write_reg(0x307a01a0, 0x80400003); /*DDRC_DFIUPD0*/ + tq_som_init_write_reg(0x307a01a4, 0x00100020); /*DDRC_DFIUPD1*/ + tq_som_init_write_reg(0x307a01a8, 0x80100004); /*DDRC_DFIUPD2*/ + tq_som_init_write_reg(0x307a0064, TQMA7_SELECT_DDR_VALUE(size, DDRC_RFSHTMG)); + tq_som_init_write_reg(0x307a0490, 0x00000001); /*DDRC_MP_PCTRL_0*/ + tq_som_init_write_reg(0x307a00d0, 0x00020081); /*DDRC_INIT0*/ + tq_som_init_write_reg(0x307a00d4, 0x00680000); /*DDRC_INIT1*/ + tq_som_init_write_reg(0x307a00dc, 0x09300004); /*DDRC_INIT3*/ + tq_som_init_write_reg(0x307a00e0, 0x00480000); /*DDRC_INIT4*/ + tq_som_init_write_reg(0x307a00e4, 0x00100004); /*DDRC_INIT5*/ + tq_som_init_write_reg(0x307a00f4, 0x0000033F); /*DDRC_RANKCTL*/ + tq_som_init_write_reg(0x307a0100, 0x090E0809); /*DDRC_DRAMTMG0*/ + tq_som_init_write_reg(0x307a0104, 0x0007020E); /*DDRC_DRAMTMG1*/ + tq_som_init_write_reg(0x307a0108, 0x03040407); /*DDRC_DRAMTMG2*/ + tq_som_init_write_reg(0x307a010c, 0x00002006); /*DDRC_DRAMTMG3*/ + tq_som_init_write_reg(0x307a0110, 0x04020304); /*DDRC_DRAMTMG4*/ + tq_som_init_write_reg(0x307a0114, 0x03030202); /*DDRC_DRAMTMG5*/ + tq_som_init_write_reg(0x307a0120, 0x00000803); /*DDRC_DRAMTMG8*/ + tq_som_init_write_reg(0x307a0180, 0x00800020); /*DDRC_ZQCTL0*/ + tq_som_init_write_reg(0x307a0190, 0x02098204); /*DDRC_DFITMG0*/ + tq_som_init_write_reg(0x307a0194, 0x00030303); /*DDRC_DFITMG1*/ + tq_som_init_write_reg(0x307a0200, 0x0000001F); /*DDRC_ADDRMAP0*/ + tq_som_init_write_reg(0x307a0204, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP1)); + tq_som_init_write_reg(0x307a020C, 0x00000000); /*DDRC_ADDRMAP3*/ + tq_som_init_write_reg(0x307a0210, 0x00000F0F); /*DDRC_ADDRMAP4*/ + tq_som_init_write_reg(0x307a0214, 0x04040404); /*DDRC_ADDRMAP5*/ + tq_som_init_write_reg(0x307a0218, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP6)); + tq_som_init_write_reg(0x307a0240, 0x06000604); /*DDRC_ODTCFG*/ + tq_som_init_write_reg(0x307a0244, 0x00000001); /*DDRC_ODTMAP*/ + tq_som_init_write_reg(0x30391000, 0x00000000); /*SRC_DDRC_RCR*/ + tq_som_init_write_reg(0x30790000, 0x17420F40); /*DDR_PHY_PHY_CON0*/ + tq_som_init_write_reg(0x30790004, 0x10210100); /*DDR_PHY_PHY_CON1*/ + tq_som_init_write_reg(0x30790010, 0x00060807); /*DDR_PHY_PHY_CON4*/ + tq_som_init_write_reg(0x307900b0, 0x1010007E); /*DDR_PHY_MDLL_CON0*/ + tq_som_init_write_reg(0x3079009c, 0x00000924); /*DDR_PHY_DRVDS_CON0*/ + + tq_som_init_write_reg(0x30790020, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_RD_CON0)); + tq_som_init_write_reg(0x30790030, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_WR_CON0)); + tq_som_init_write_reg(0x30790050, 0x01000010); /*DDR_PHY_CMD_SDLL_CON0*/ + tq_som_init_write_reg(0x30790050, 0x00000010); /*DDR_PHY_CMD_SDLL_CON0*/ + + tq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/ + tq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/ + tq_som_init_write_reg(0x307900c0, 0x0C447306); /*DDR_PHY_ZQ_CON0*/ + + tq_som_check_bits_set(0x307900c4, 0x1); /*ZQ Calibration is finished*/ + + tq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/ + tq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/ + + tqma7_ccgr_init(); +} + +void tq_som_ram_init(void) +{ + /* RAM sizes need to be in descending order */ + static const u32 ram_sizes[] = { +#if IS_ENABLED(CONFIG_TQMA7_RAM_2G) + SZ_2G, +#endif +#if IS_ENABLED(CONFIG_TQMA7_RAM_1G) + SZ_1G, +#endif +#if IS_ENABLED(CONFIG_TQMA7_RAM_512M) + SZ_512M, +#endif + }; + int i; + + debug("SPL: tqma7 iomux ....\n"); + tqma7_ddr_exit_retention(); + + for (i = 0; i < ARRAY_SIZE(ram_sizes); i++) { + tqma7_init_ddr_controller(ram_sizes[i]); + if (tq_som_ram_check_size(ram_sizes[i])) + break; + } + + if (i < ARRAY_SIZE(ram_sizes)) { + debug("SPL: tqma7 ddr init done ...\n"); + } else { + pr_err("Error: Invalid DDR RAM size\n"); + hang(); + } +} diff --git a/board/tq/tqma7/tqma7.c b/board/tq/tqma7/tqma7.c new file mode 100644 index 00000000000..30bd155713d --- /dev/null +++ b/board/tq/tqma7/tqma7.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Steffen Doster + */ + +#include <env.h> +#include <fdt_support.h> +#include <mtd_node.h> +#include <spi_flash.h> +#include <asm/bootm.h> +#include <asm/setup.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#include "../common/tq_bb.h" +#include "../common/tq_som.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +#if (!IS_ENABLED(CONFIG_SPL_BUILD)) + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + if (IS_ENABLED(CONFIG_FSL_QSPI)) + set_clk_qspi(); + + return tq_bb_board_init(); +} + +static const char *tqma7_get_boardname(void) +{ + switch (get_cpu_type()) { + case MXC_CPU_MX7S: + return "TQMa7S"; + case MXC_CPU_MX7D: + return "TQMa7D"; + default: + return "??"; + }; +} + +int board_late_init(void) +{ + const char *bname = tqma7_get_boardname(); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + struct tag_serialnr serialnr; + + get_board_serial(&serialnr); + + printf("UID: %08x%08x\n", serialnr.high, serialnr.low); + } + + env_set_runtime("board_name", bname); + + return tq_bb_board_late_init(); +} + +static u32 tqma7_get_board_rev(void) +{ + /* REV.0100 is unsupported */ + return 200; +} + +int checkboard(void) +{ + printf("Board: %s REV.%04u\n", tq_bb_get_boardname(), tqma7_get_board_rev()); + return 0; +} + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + tq_bb_ft_board_setup(blob, bd); + + return 0; +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + +#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */ diff --git a/board/tq/tqma7/tqma7.cfg b/board/tq/tqma7/tqma7.cfg new file mode 100644 index 00000000000..2e807d62348 --- /dev/null +++ b/board/tq/tqma7/tqma7.cfg @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Steffen Doster + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +#include <config.h> + +/* + * Set to sd even for QSPI boot on i.MX7, as i.MX7 uses offset 0x400 rather + * than 0x1000 for QSPI + */ +BOOT_FROM sd + +#if IS_ENABLED(CONFIG_IMX_HAB) +CSF CONFIG_CSF_SIZE +#endif diff --git a/board/tq/tqma7/tqma7.env b/board/tq/tqma7/tqma7.env new file mode 100644 index 00000000000..857f16d11bb --- /dev/null +++ b/board/tq/tqma7/tqma7.env @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Alexander Feilke + * + * TQMa7x environment + */ + +#include <env/tq/tq-imx-shared.env> + +board=tqma7 +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA7_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA7_FDT_ADDRESS +fdtoverlay_addr_r=FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +netdev=eth0 +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA7_INITRD_ADDRESS +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA7_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA7_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA7_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA7_SPI_UBOOT_START +uboot_spi_size=TQMA7_SPI_UBOOT_SIZE + +#ifdef CONFIG_FASTBOOT_UUU_SUPPORT +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV:0 +fastboot_raw_partition_bootloader=TQMA7_MMC_UBOOT_SECTOR_START TQMA7_MMC_UBOOT_SECTOR_COUNT mmcpart 1 +fastbootcmd=fastboot usb 0 +#endif diff --git a/board/tq/tqma7/tqma7_mba7.c b/board/tq/tqma7/tqma7_mba7.c new file mode 100644 index 00000000000..65c6c08771d --- /dev/null +++ b/board/tq/tqma7/tqma7_mba7.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel, Steffen Doster + */ + +#include <env.h> +#include <errno.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-mx7/imx-regs.h> +#include <asm/mach-imx/boot_mode.h> + +#include "../common/tq_bb.h" + +const char *tq_bb_get_boardname(void) +{ + return "MBa7x"; +} + +#if !IS_ENABLED(CONFIG_SPL_BUILD) + +static int mba7_setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + switch (fec_id) { + case 0: + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 0); + break; + case 1: + /* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK, 0); + break; + default: + printf("FEC%d: unsupported\n", fec_id); + return -EINVAL; + } + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + +int tq_bb_board_init(void) +{ + mba7_setup_fec(0); + + if (!is_cpu_type(MXC_CPU_MX7S)) + mba7_setup_fec(1); + + return 0; +} + +int tq_bb_board_late_init(void) +{ + puts("Boot: "); + + if (is_boot_from_usb()) { + puts("USB\n"); + env_set_runtime("boot_dev", "mmc"); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + } else { + /* + * try to get sd card slots in order: + * eMMC: on Module + * -> therefore index 0 for bootloader + * index n in kernel (controller instance 3) -> patches needed for + * alias indexing + * SD1: on Mainboard + * index n in kernel (controller instance 1) -> patches needed for + * alias indexing + * we assume to have a kernel patch that will present mmcblk dev + * indexed like controller devs + */ + enum boot_device bd = get_boot_device(); + + switch (bd) { + case MMC3_BOOT: + puts("USDHC3(eMMC)\n"); + env_set_runtime("boot_dev", "mmc"); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + break; + case SD1_BOOT: + puts("USDHC1(SD)\n"); + env_set_runtime("boot_dev", "mmc"); + env_set_runtime("mmcdev", "1"); + env_set_runtime("mmcblkdev", "1"); + break; + case QSPI_BOOT: + puts("QSPI\n"); + env_set_runtime("boot_dev", "qspi"); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + break; + default: + printf("unhandled boot device %d\n", (int)bd); + env_set_runtime("mmcdev", "0"); + env_set_runtime("mmcblkdev", "0"); + } + } + + if (!env_get("fdtfile")) { + /* provide default setting for fdtfile if nothing in env is set */ + + switch (get_cpu_type()) { + case MXC_CPU_MX7S: + env_set_runtime("fdtfile", "imx7s-mba7.dtb"); + break; + case MXC_CPU_MX7D: + env_set_runtime("fdtfile", "imx7d-mba7.dtb"); + break; + default: + debug("unknown CPU"); + } + } + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + switch (devno) { + case 2: + /* eMMC */ + return 0; + case 0: + /* SD card */ + return 1; + default: + /* Unknown */ + return 0; + } +} + +#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */ diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index d41bd2e9dee..ac8c9a9a81a 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -186,6 +186,58 @@ void fdt_fixup_board_enet(void *fdt) fdt_status_fail(fdt, offset); } +/* The onboard USB hub driver (microchip,usb5744) + * can cause a disconnect-reconnect loop if the operating system + * attempts to re-initialise the hub after U-Boot has already done it. + * (This process only needs to be done once per system RESET cycle) + * + * To avoid this condition, make the hub topology invisible + * to the operating system. + * It is also required to remove the hub on boards + * without it (RevD). + * + * The USB hub fixup may fail for legitimate reasons: + * 1. FDT has already been fixed. For example, the control + * FDT previously modified by board_fix_fdt is + * re-used for bootflow. + * 2. The FDT blob is based on an older version + * without the hub topology, such as older OpenWrt + * FIT images with their own device tree. + */ +int fdt_fixup_usb_hub(void *fdt) +{ + int usb1_hub2744_offset, usb1_hub5744_offset; + int i2c_usb5744_offset; + int err; + + usb1_hub2744_offset = fdt_path_offset(fdt, "/soc/usb@3110000/hub@1"); + + if (usb1_hub2744_offset < 0) + return usb1_hub2744_offset; + + err = fdt_del_node(fdt, usb1_hub2744_offset); + if (err) + return err; + + usb1_hub5744_offset = fdt_path_offset(fdt, "/soc/usb@3110000/hub@2"); + if (usb1_hub5744_offset < 0) + return usb1_hub5744_offset; + + err = fdt_del_node(fdt, usb1_hub5744_offset); + if (err) + return err; + + i2c_usb5744_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/usb-hub@2d"); + if (i2c_usb5744_offset < 0) + return i2c_usb5744_offset; + + err = fdt_setprop_string(fdt, i2c_usb5744_offset, "status", "disabled"); + if (err) + return err; + + return 0; +} + /* Called after SoC board_late_init in fsl-layerscape/soc.c */ int fsl_board_late_init(void) { @@ -233,7 +285,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) } if (mc_memory_base != 0) { - for (i = 0; i <= total_memory_banks; i++) { + for (i = 0; i < total_memory_banks; i++) { if (base[i] == 0 && size[i] == 0) { base[i] = mc_memory_base; size[i] = mc_memory_size; @@ -251,6 +303,24 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_icid(blob); + /* This fixup may fail for legitimate + * reasons (see comments for fdt_fixup_usb_hub). + * Hence, errors with it are silently ignored. + */ + fdt_fixup_usb_hub(blob); + return 0; +} + +/* board_fix_fdt: fixup function for internal (U-Boot) FDT */ +int board_fix_fdt(void *fdt) +{ + u32 board_rev = ten64_get_board_rev(); + + /* Delete USB Hub references in U-Boot's FDT on + * boards without one. + */ + if (board_rev == TEN64_BOARD_REV_D) + fdt_fixup_usb_hub(fdt); return 0; } diff --git a/board/turing/turing-rk1-rk3588/MAINTAINERS b/board/turing/turing-rk1-rk3588/MAINTAINERS index 4f313732fa1..973ac68836c 100644 --- a/board/turing/turing-rk1-rk3588/MAINTAINERS +++ b/board/turing/turing-rk1-rk3588/MAINTAINERS @@ -4,6 +4,4 @@ S: Maintained F: board/turing/turing-rk1-rk3588 F: include/configs/turing-rk1-rk3588.h F: configs/turing-rk1-rk3588_defconfig -F: arch/arm/dts/rk3588-turing-rk1.dts -F: arch/arm/dts/rk3588-turing-rk1.dtsi -F: arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi +F: arch/arm/dts/rk3588-turing-rk1* diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index d022308f943..89562ef77fc 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -508,8 +508,7 @@ int board_late_init_xilinx(void) ret |= env_set_by_index("uuid", id, uuid); } - if (!(CONFIG_IS_ENABLED(NET) || - CONFIG_IS_ENABLED(NET_LWIP))) + if (!CONFIG_IS_ENABLED(NET)) continue; for (i = 0; i < EEPROM_HDR_NO_OF_MAC_ADDR; i++) { diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 769e52bcfb5..a1d8ae26673 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -183,6 +183,23 @@ int board_init(void) zynqmppl.name = strdup(name); fpga_init(); fpga_add(fpga_xilinx, &zynqmppl); + + /* + * zu63dr_SE and zu67dr_SE share ID 0x046D7093. + * Register zu63dr_SE as alternate device. + */ + if (!strcmp(name, "zu67dr_SE")) { + xilinx_desc *alt; + + alt = calloc(1, sizeof(*alt)); + if (!alt) { + log_err("Failed to allocate alt FPGA descriptor\n"); + } else { + *alt = zynqmppl; + alt->name = "zu63dr_SE"; + fpga_add(fpga_xilinx, alt); + } + } } } #endif diff --git a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS index be9c93f6b9d..79981aa43f1 100644 --- a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS +++ b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS @@ -3,4 +3,4 @@ M: Niu Zhihong <[email protected]> S: Maintained F: board/xunlong/orangepi-5-rk3588-ultra F: configs/orangepi-5-ultra-rk3588_defconfig -F: arch/arm/dts/rk3588-orangepi-5-ultra.dts +F: arch/arm/dts/rk3588-orangepi-5-ultra* |