diff options
Diffstat (limited to 'board')
92 files changed, 4534 insertions, 1236 deletions
diff --git a/board/alliedtelesis/x960/MAINTAINERS b/board/alliedtelesis/x960/MAINTAINERS new file mode 100644 index 00000000000..1717a67b22c --- /dev/null +++ b/board/alliedtelesis/x960/MAINTAINERS @@ -0,0 +1,7 @@ +X960 BOARD +M: Chris Packham <[email protected]> +S: Maintained +F: board/alliedtelesis/x960/ +F: arch/arm/dts/cn9130-atl-x960-28ysq.dts +F: include/configs/x960.h +F: configs/x960_defconfig diff --git a/board/alliedtelesis/x960/Makefile b/board/alliedtelesis/x960/Makefile new file mode 100644 index 00000000000..d5c32c02acc --- /dev/null +++ b/board/alliedtelesis/x960/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2026 Allied Telesis +# + +obj-y += x960.o diff --git a/board/alliedtelesis/x960/x960.c b/board/alliedtelesis/x960/x960.c new file mode 100644 index 00000000000..66c782698ff --- /dev/null +++ b/board/alliedtelesis/x960/x960.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <config.h> +#include <asm/global_data.h> +#include <linux/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define DEVICE_BUS_SYNC_CTRL 0xF27004C8 + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */ + writel(0x00004001, DEVICE_BUS_SYNC_CTRL); + + return 0; +} diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index 2afd283b8dd..15b79bbea69 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -11,7 +11,6 @@ #include <env.h> #include <efi_loader.h> #include <fdtdec.h> -#include <fwu.h> #include <init.h> #include <env_internal.h> #include <log.h> @@ -362,8 +361,6 @@ enum env_location env_get_location(enum env_operation op, int prio) #define DFU_ALT_BUF_LEN SZ_1K -#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && \ - !defined(CONFIG_FWU_MULTI_BANK_UPDATE) static void mtd_found_part(u32 *base, u32 *size) { struct mtd_info *part, *mtd; @@ -440,42 +437,6 @@ void configure_capsule_updates(void) update_info.dfu_string = strdup(buf); debug("Capsule DFU: %s\n", update_info.dfu_string); } -#endif - -#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) - -/* Generate dfu_alt_info from partitions */ -void set_dfu_alt_info(char *interface, char *devstr) -{ - int ret; - struct mtd_info *mtd; - - /* - * It is called multiple times for every image - * per bank that's why enough to set it up once. - */ - if (env_get("dfu_alt_info")) - return; - - ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); - memset(buf, 0, DFU_ALT_BUF_LEN); - - mtd_probe_devices(); - - mtd = get_mtd_device_nm("nor0"); - if (IS_ERR_OR_NULL(mtd)) - return; - - ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); - if (ret < 0) { - log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); - return; - } - log_debug("Make dfu_alt_info: '%s'\n", buf); - - env_set("dfu_alt_info", buf); -} -#endif int spi_get_env_dev(void) { diff --git a/board/anbernic/rg-ds_rk3568/Kconfig b/board/anbernic/rg-ds_rk3568/Kconfig new file mode 100644 index 00000000000..8676940651a --- /dev/null +++ b/board/anbernic/rg-ds_rk3568/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RG_DS_RK3568 + +config SYS_BOARD + default "rg-ds_rk3568" + +config SYS_VENDOR + default "anbernic" + +config SYS_CONFIG_NAME + default "anbernic-rg-ds-rk3568" + +endif diff --git a/board/anbernic/rg-ds_rk3568/MAINTAINERS b/board/anbernic/rg-ds_rk3568/MAINTAINERS new file mode 100644 index 00000000000..7b9b546f7bc --- /dev/null +++ b/board/anbernic/rg-ds_rk3568/MAINTAINERS @@ -0,0 +1,7 @@ +ANBERNIC-RG-DS-RK3568 +M: Chris Morgan <[email protected]> +S: Maintained +F: arch/arm/dts/rk3568-anbernic-rg-ds-u-boot.dtsi +F: board/anbernic/rg-ds_rk3568 +F: configs/anbernic-rg-ds-rk3568_defconfig +F: include/configs/anbernic-rg-ds-rk3568.h diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index c6a5740c7a7..6071fb405a7 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -59,7 +59,7 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) { if (boot_dev_spl == MMC3_BOOT) return BOOT_DEVICE_MMC2; /* eMMC */ - else if (boot_dev_spl == MMC2_BOOT) + else if (boot_dev_spl == MMC2_BOOT || boot_dev_spl == SD2_BOOT) return BOOT_DEVICE_MMC1; /* SD */ else return BOOT_DEVICE_BOARD; diff --git a/board/firefly/roc-pc-rk3588s/Kconfig b/board/firefly/roc-pc-rk3588s/Kconfig new file mode 100644 index 00000000000..bded7a2fcba --- /dev/null +++ b/board/firefly/roc-pc-rk3588s/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ROC_PC_RK3588S + +config SYS_BOARD + default "roc-pc-rk3588s" + +config SYS_VENDOR + default "firefly" + +config SYS_CONFIG_NAME + default "roc-pc-rk3588s" + +endif diff --git a/board/firefly/roc-pc-rk3588s/MAINTAINERS b/board/firefly/roc-pc-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..de631519311 --- /dev/null +++ b/board/firefly/roc-pc-rk3588s/MAINTAINERS @@ -0,0 +1,6 @@ +ROC-RK3588S-PC +M: Fabio Estevam <[email protected]> +S: Maintained +F: board/firefly/roc-pc-rk3588s/ +F: configs/roc-pc-rk3588s_defconfig +F: include/configs/roc-pc-rk3588s.h diff --git a/board/gateworks/fsa.c b/board/gateworks/fsa.c index 1af8021057c..126a897ee28 100644 --- a/board/gateworks/fsa.c +++ b/board/gateworks/fsa.c @@ -140,6 +140,9 @@ static int fsa_config_gpios(int fsa, struct fsa_user_info *info, int gpios, stru int i, ret, flags; char name[32]; + /* clamp EEPROM-supplied descriptor count to the array size */ + if (gpios > ARRAY_SIZE(info->gpios)) + gpios = ARRAY_SIZE(info->gpios); /* configure GPIO's */ for (i = 0; i < gpios; i++) { desc = &info->gpios[i]; @@ -637,6 +640,11 @@ static int do_fsa_gpio(struct cmd_tbl *cmdtp, int flag, int argc, char * const a memset(&desc, 0, sizeof(desc)); i = simple_strtoul(argv[0], NULL, 10); + if (i < 0 || i >= (int)ARRAY_SIZE(user_info.gpios)) { + printf("invalid index %d", i); + return CMD_RET_FAILURE; + } + if (i >= 0 && i < board_info.sockgpios) { desc.offset = i; desc.source = 0xff; diff --git a/board/ge/common/vpd_reader.c b/board/ge/common/vpd_reader.c index 2422db38013..b3f9e96615d 100644 --- a/board/ge/common/vpd_reader.c +++ b/board/ge/common/vpd_reader.c @@ -66,7 +66,7 @@ static int verify_bch(int ecc_bits, unsigned int prim_poly, u8 *data, return -1; } - unsigned int *errloc = (unsigned int *)calloc(data_length, + unsigned int *errloc = (unsigned int *)calloc(ecc_bits, sizeof(unsigned int)); int errors = decode_bch(bch, data, data_length, ecc, NULL, NULL, errloc); diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS index 37ca35b4dd4..d99c6d708b2 100644 --- a/board/mediatek/MAINTAINERS +++ b/board/mediatek/MAINTAINERS @@ -21,6 +21,9 @@ MT8188/MT8370/MT8390 M: Macpaul Lin <[email protected]> M: Julien Stephan <[email protected]> S: Maintained +F: arch/arm/dts/mt8188-u-boot.dtsi +F: arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi +F: arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi F: configs/mt8188.config F: configs/mt8370_genio_510_evk_defconfig F: configs/mt8390_genio_700_evk_defconfig diff --git a/board/nxp/common/vid.c b/board/nxp/common/vid.c index 84cb43fad56..70c3b3ecfd8 100644 --- a/board/nxp/common/vid.c +++ b/board/nxp/common/vid.c @@ -11,6 +11,7 @@ #include <i2c.h> #include <irq_func.h> #include <log.h> +#include <pmbus.h> #include <vsprintf.h> #include <asm/io.h> #ifdef CONFIG_FSL_LSCH2 @@ -260,45 +261,38 @@ static int read_voltage_from_IR(int i2caddress) */ #define VOUT_WARNING "VID: VOUT_MODE exponent has resolution worse than 1 V!\n" -/* Checks the PMBus voltage monitor for the format used for voltage values */ -static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) +/* + * Read VOUT_MODE for downstream LINEAR16 decode/encode through the + * tree level <pmbus.h> helpers (pmbus_reg2data_linear16, + * pmbus_data2reg_linear16). Stores the raw VOUT_MODE byte in *mode + * and returns 0 on success, or the negative bus error (a failed read + * must not be decoded: raw 0 aliases Linear mode with exponent 0). + * Emits VOUT_WARNING on Linear mode chips with a non negative + * exponent (resolution >= 1 V is unusable for sub volt SoC rails) + * and an informational note on the unsupported VID format. + */ +static int vid_read_vout_mode(DEVICE_HANDLE_T dev, u8 *mode) { - u8 mode; - int exponent, multiplier, ret; + int ret; - ret = I2C_READ(dev, PMBUS_CMD_VOUT_MODE, &mode, sizeof(mode)); + ret = pmbus_read_byte(dev, PMBUS_VOUT_MODE, mode); if (ret) { printf("VID: unable to determine voltage multiplier\n"); - return 1; + return ret; } - /* Upper 3 bits is mode, lower 5 bits is exponent */ - exponent = (int)mode & 0x1F; - mode >>= 5; - switch (mode) { - case 0: - /* Linear, 5 bit twos component exponent */ - if (exponent & 0x10) { - multiplier = 1 << (16 - (exponent & 0xF)); - } else { - /* If exponent is >= 0, then resolution is 1 V! */ + switch (*mode & PB_VOUT_MODE_MODE_MASK) { + case PB_VOUT_MODE_LINEAR: + if (!(*mode & 0x10)) printf(VOUT_WARNING); - multiplier = 1; - } break; - case 1: - /* VID code identifier */ + case PB_VOUT_MODE_VID: printf("VID: custom VID codes are not supported\n"); - multiplier = MV_PER_V; break; default: - /* Direct, in mV */ - multiplier = MV_PER_V; break; } - - debug("VID: calculated multiplier is %d\n", multiplier); - return multiplier; + return 0; } #endif @@ -306,8 +300,8 @@ static int get_pmbus_multiplier(DEVICE_HANDLE_T dev) defined(CONFIG_VOL_MONITOR_LTC3882_READ) static int read_voltage_from_pmbus(int i2caddress) { - int ret, multiplier, vout; - u8 channel = PWM_CHANNEL0; + int ret, vout; + u8 channel = PWM_CHANNEL0, vout_mode; u16 vcode; DEVICE_HANDLE_T dev; @@ -317,25 +311,33 @@ static int read_voltage_from_pmbus(int i2caddress) return ret; /* Select the right page */ - ret = I2C_WRITE(dev, PMBUS_CMD_PAGE, &channel, sizeof(channel)); + ret = pmbus_write_byte(dev, PMBUS_PAGE, channel); if (ret) { printf("VID: failed to select VDD page %d\n", channel); return ret; } - /* VOUT is little endian */ - ret = I2C_READ(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, sizeof(vcode)); + ret = pmbus_read_word(dev, PMBUS_READ_VOUT, &vcode); if (ret) { printf("VID: failed to read core voltage\n"); return ret; } - /* Scale down to the real mV */ - multiplier = get_pmbus_multiplier(dev); - vout = (int)vcode; - /* Multiplier 1000 (direct mode) requires no change to convert */ - if (multiplier != MV_PER_V) - vout = DIV_ROUND_UP(vout * MV_PER_V, multiplier); + /* + * Decode LINEAR16 via the tree level helper from <pmbus.h>. For + * non Linear VOUT_MODE settings the helper returns 0; fall back + * to the historic mV pass through so existing LSCH boards keep. + */ + ret = vid_read_vout_mode(dev, &vout_mode); + if (ret) + return ret; + if ((vout_mode & PB_VOUT_MODE_MODE_MASK) == PB_VOUT_MODE_LINEAR) { + s64 uv = pmbus_reg2data_linear16(vcode, vout_mode); + + vout = (int)((uv + 500) / 1000); /* round to mV */ + } else { + vout = (int)vcode; + } return vout - board_vdd_drop_compensation(); } #endif @@ -463,11 +465,13 @@ static int set_voltage_to_IR(int i2caddress, int vdd) static int set_voltage_to_pmbus(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; - int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0, multiplier; + int count = MAX_LOOP_WAIT_NEW_VOL, temp = 0; + u8 vout_mode; + u16 raw; unsigned char value; /* The data to be sent with the PMBus command PAGE_PLUS_WRITE */ - u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, 0, 0 }; + u8 buffer[5] = { 0x04, PWM_CHANNEL0, PMBUS_VOUT_COMMAND, 0, 0 }; DEVICE_HANDLE_T dev; /* Open device handle */ @@ -475,24 +479,32 @@ static int set_voltage_to_pmbus(int i2caddress, int vdd) if (ret) return ret; - /* Scale up to the proper value for the VOUT command, little endian */ - multiplier = get_pmbus_multiplier(dev); + /* + * Encode target mV as LINEAR16 raw via the tree level helper + * from <pmbus.h>. For non Linear VOUT_MODE settings the helper + * returns 0; fall back to the historic mV pass through. A failed + * VOUT_MODE read aborts: never write a voltage code whose + * encoding could not be determined. + */ vdd += board_vdd_drop_compensation(); - if (multiplier != MV_PER_V) - vdd = DIV_ROUND_UP(vdd * multiplier, MV_PER_V); - buffer[3] = vdd & 0xFF; - buffer[4] = (vdd & 0xFF00) >> 8; + ret = vid_read_vout_mode(dev, &vout_mode); + if (ret) + return ret; + if ((vout_mode & PB_VOUT_MODE_MODE_MASK) == PB_VOUT_MODE_LINEAR) + raw = pmbus_data2reg_linear16((s64)vdd * 1000LL, vout_mode); + else + raw = (u16)vdd; + buffer[3] = raw & 0xFF; + buffer[4] = (raw & 0xFF00) >> 8; /* Check write protect state */ - ret = I2C_READ(dev, PMBUS_CMD_WRITE_PROTECT, (void *)&value, - sizeof(value)); + ret = pmbus_read_byte(dev, PMBUS_WRITE_PROTECT, &value); if (ret) goto exit; if (value != EN_WRITE_ALL_CMD) { value = EN_WRITE_ALL_CMD; - ret = I2C_WRITE(dev, PMBUS_CMD_WRITE_PROTECT, - (void *)&value, sizeof(value)); + ret = pmbus_write_byte(dev, PMBUS_WRITE_PROTECT, value); if (ret) goto exit; } diff --git a/board/nxp/common/vid.h b/board/nxp/common/vid.h index b34c080b4ba..72c1c089aa1 100644 --- a/board/nxp/common/vid.h +++ b/board/nxp/common/vid.h @@ -22,8 +22,9 @@ #define IR_VDD_STEP_UP 5 /* LTC3882 */ -#define PMBUS_CMD_WRITE_PROTECT 0x10 /* + * PMBUS_WRITE_PROTECT (10h) provided by <pmbus.h> + * * WRITE_PROTECT command supported values * 0x80: Disable all writes except WRITE_PROTECT, PAGE, * STORE_USER_ALL and MFR_EE_UNLOCK commands. @@ -51,12 +52,14 @@ #define VDD_MV_MAX 925 #endif -/* PM Bus commands code for LTC3882*/ +/* + * PM Bus commands code for LTC3882. PMBUS_PAGE / PMBUS_READ_VOUT / + * PMBUS_VOUT_MODE / PMBUS_VOUT_COMMAND are provided by <pmbus.h>. + * PMBUS_CMD_PAGE_PLUS_WRITE (05h) is the LTC3882 SMBus block write + * transaction not in <pmbus.h>'s standard subset, so keep its + * definition here. + */ #define PWM_CHANNEL0 0x0 -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_VOUT_MODE 0x20 -#define PMBUS_CMD_VOUT_COMMAND 0x21 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ diff --git a/board/nxp/imx94_evk/imx94_evk.c b/board/nxp/imx94_evk/imx94_evk.c index 02149afae87..94fa135c759 100644 --- a/board/nxp/imx94_evk/imx94_evk.c +++ b/board/nxp/imx94_evk/imx94_evk.c @@ -11,6 +11,9 @@ int board_init(void) { + /* Power on mcores when using rpmsg cfg */ + power_on_mcore("mx94evkrpmsg"); + return 0; } diff --git a/board/nxp/imx952_evk/imx952_evk.c b/board/nxp/imx952_evk/imx952_evk.c index b5c2da032a8..171bd029f76 100644 --- a/board/nxp/imx952_evk/imx952_evk.c +++ b/board/nxp/imx952_evk/imx952_evk.c @@ -9,6 +9,9 @@ int board_init(void) { + /* Power on mcores when using rpmsg cfg */ + power_on_mcore("mx952evkrpmsg"); + return 0; } diff --git a/board/nxp/imx95_evk/imx95_evk.c b/board/nxp/imx95_evk/imx95_evk.c index 394d6fd459c..8cc61800edc 100644 --- a/board/nxp/imx95_evk/imx95_evk.c +++ b/board/nxp/imx95_evk/imx95_evk.c @@ -7,6 +7,14 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +int board_init(void) +{ + /* Power on mcores when using rpmsg cfg */ + power_on_mcore("mx95evkrpmsg"); + + return 0; +} + int board_late_init(void) { if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) diff --git a/board/nxp/imx95_frdm/Kconfig b/board/nxp/imx95_frdm/Kconfig new file mode 100644 index 00000000000..0da9a56adad --- /dev/null +++ b/board/nxp/imx95_frdm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX95_15X15_FRDM + +config SYS_BOARD + default "imx95_frdm" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx95_frdm" + +endif diff --git a/board/nxp/imx95_frdm/MAINTAINERS b/board/nxp/imx95_frdm/MAINTAINERS new file mode 100644 index 00000000000..33870f054e7 --- /dev/null +++ b/board/nxp/imx95_frdm/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX95 FRDM BOARD +M: Joseph Guo <[email protected]> +S: Maintained +F: board/nxp/imx95_frdm/ +F: include/configs/imx95_frdm.h +F: configs/imx95_15x15_frdm_defconfig diff --git a/board/nxp/imx95_frdm/Makefile b/board/nxp/imx95_frdm/Makefile new file mode 100644 index 00000000000..6965c61a281 --- /dev/null +++ b/board/nxp/imx95_frdm/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2026 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx95_frdm.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/nxp/imx95_frdm/imx95_frdm.c b/board/nxp/imx95_frdm/imx95_frdm.c new file mode 100644 index 00000000000..394d6fd459c --- /dev/null +++ b/board/nxp/imx95_frdm/imx95_frdm.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) +int board_fix_fdt(void *fdt) +{ + /* Remove nodes based on fuses. */ + return imx9_uboot_fixup_by_fuse(fdt); +} +#endif diff --git a/board/nxp/imx95_frdm/imx95_frdm.env b/board/nxp/imx95_frdm/imx95_frdm.env new file mode 100644 index 00000000000..61fbd395645 --- /dev/null +++ b/board/nxp/imx95_frdm/imx95_frdm.env @@ -0,0 +1,93 @@ +sec_boot=no +initrd_addr=0x93800000 +emmc_dev=0 +sd_dev=1 +scriptaddr=0x93500000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +image=Image +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 +splashimage=0xA0000000 +console=ttyLP0,115200 earlycon +fdt_addr_r=0x93000000 +fdt_addr=0x93000000 +cntr_addr=0xA8000000 +cntr_file=os_cntr_signed.bin +boot_fit=no +fdtfile=DEFAULT_FDT_FILE +bootm_size=0x10000000 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcautodetect=yes +mmcargs=setenv bootargs console=${console} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=auth_cntr ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r}; +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + if run auth_os; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +netargs=setenv bootargs console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + if run auth_os; then + run boot_os; + else + echo ERR: failed to authenticate; + fi; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; diff --git a/board/nxp/imx95_frdm/spl.c b/board/nxp/imx95_frdm/spl.c new file mode 100644 index 00000000000..c8a5b4f9d41 --- /dev/null +++ b/board/nxp/imx95_frdm/spl.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 NXP + */ + +#include <hang.h> +#include <init.h> +#include <spl.h> +#include <asm/global_data.h> +#include <asm/sections.h> +#include <asm/arch/clock.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/mach-imx/qb.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + puts("Normal Boot\n"); + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + if (IS_ENABLED(CONFIG_SPL_IMX_QB)) + spl_imx_qb_save(); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_SPL_RECOVER_DATA_SECTION + if (IS_ENABLED(CONFIG_SPL_BUILD)) + spl_save_restore_data(); +#endif + + timer_init(); + + /* Need dm_init() to run before any SCMI calls can be made. */ + spl_early_init(); + + /* Need enable SCMI drivers and ELE driver before enabling console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* if MU not probed, nothing can output, just hang here */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/board/nxp/ls1088a/ls1088a.c b/board/nxp/ls1088a/ls1088a.c index 1b477e83676..8ea76fe3760 100644 --- a/board/nxp/ls1088a/ls1088a.c +++ b/board/nxp/ls1088a/ls1088a.c @@ -7,6 +7,7 @@ #include <display_options.h> #include <env.h> #include <i2c.h> +#include <pmbus.h> #include <init.h> #include <log.h> #include <malloc.h> @@ -667,13 +668,13 @@ int get_serdes_volt(void) /* Select the PAGE 0 using PMBus commands PAGE for VDD */ #if !CONFIG_IS_ENABLED(DM_I2C) ret = i2c_write(I2C_SVDD_MONITOR_ADDR, - PMBUS_CMD_PAGE, 1, &chan, 1); + PMBUS_PAGE, 1, &chan, 1); #else struct udevice *dev; ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev); if (!ret) - ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, + ret = dm_i2c_write(dev, PMBUS_PAGE, &chan, 1); #endif @@ -685,9 +686,9 @@ int get_serdes_volt(void) /* Read the output voltage using PMBus command READ_VOUT */ #if !CONFIG_IS_ENABLED(DM_I2C) ret = i2c_read(I2C_SVDD_MONITOR_ADDR, - PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); + PMBUS_READ_VOUT, 1, (void *)&vcode, 2); #else - dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2); + dm_i2c_read(dev, PMBUS_READ_VOUT, (void *)&vcode, 2); #endif if (ret) { printf("VID: failed to read the voltage\n"); @@ -700,7 +701,7 @@ int get_serdes_volt(void) int set_serdes_volt(int svdd) { int ret, vdd_last; - u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, + u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_VOUT_COMMAND, svdd & 0xFF, (svdd & 0xFF00) >> 8}; /* Write the desired voltage code to the SVDD regulator */ diff --git a/board/phytec/phycore_am62ax/phycore-am62ax.c b/board/phytec/phycore_am62ax/phycore-am62ax.c index 3e1c4102cc1..b22ffe9072f 100644 --- a/board/phytec/phycore_am62ax/phycore-am62ax.c +++ b/board/phytec/phycore_am62ax/phycore-am62ax.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <spl.h> #include <fdt_support.h> +#include <image.h> #include "../common/am6_som_detection.h" @@ -57,3 +58,8 @@ void spl_board_init(void) dram_init_banksize(); } #endif + +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 6df521d789f..376379767cf 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -9,6 +9,7 @@ #include <spl.h> #include <asm/arch/k3-ddr.h> #include <fdt_support.h> +#include <image.h> #include "phycore-ddr-data.h" #include "../common/k3/k3_ddrss_patch.h" @@ -237,3 +238,8 @@ void spl_board_init(void) MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); } #endif + +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} diff --git a/board/phytec/phycore_am68x/phycore-am68x.c b/board/phytec/phycore_am68x/phycore-am68x.c index 312d7ece23e..9b71a4bdc68 100644 --- a/board/phytec/phycore_am68x/phycore-am68x.c +++ b/board/phytec/phycore_am68x/phycore-am68x.c @@ -21,6 +21,7 @@ #include <dm/uclass-internal.h> #include <dm/root.h> #include <asm/arch/k3-ddr.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; @@ -69,6 +70,46 @@ void spl_perform_board_fixups(struct spl_image_info *spl_image) } #endif +#define TPS6594_I2C_WD_ADDR 0x12 +#define WD_THR_CFG_REG 0x09 +#define WD_EN BIT(6) + +int tps6594_disable_watchdog(void) +{ + struct udevice *i2c_bus, *i2c_dev; + int ret; + u8 val; + + ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@40b00000", &i2c_bus); + if (ret) + return ret; + + ret = dm_i2c_probe(i2c_bus, TPS6594_I2C_WD_ADDR, 0, &i2c_dev); + if (ret) + return ret; + + ret = dm_i2c_reg_read(i2c_dev, WD_THR_CFG_REG); + if (ret < 0) + return ret; + + val = (u8)ret; + val &= ~WD_EN; + ret = dm_i2c_reg_write(i2c_dev, WD_THR_CFG_REG, val); + + return ret; +} + +int board_init(void) +{ + int ret; + + ret = tps6594_disable_watchdog(); + if (ret) + printf("disabling TPS6594 watchdog failed: %d\n", ret); + + return 0; +} + void spl_board_init(void) { struct udevice *dev; diff --git a/board/phytec/phycore_imx8mm/Kconfig b/board/phytec/phycore_imx8mm/Kconfig index 06449128ba8..609c11580ce 100644 --- a/board/phytec/phycore_imx8mm/Kconfig +++ b/board/phytec/phycore_imx8mm/Kconfig @@ -12,5 +12,70 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mm/imximage-8mm-sd.cfg" +config PHYCORE_IMX8MM_RAM_SIZE_FIX + bool "Set phyCORE-i.MX8MM RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. + +choice + prompt "phyCORE-i.MX8MM RAM size" + depends on PHYCORE_IMX8MM_RAM_SIZE_FIX + default PHYCORE_IMX8MM_RAM_SIZE_2GB + help + Select a fixed RAM size instead of EEPROM introspection + data. + +config PHYCORE_IMX8MM_RAM_SIZE_1GB + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-i.MX8MM + instead of runtime detection from EEPROM. + +config PHYCORE_IMX8MM_RAM_SIZE_2GB + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-i.MX8MM + instead of runtime detection from EEPROM. + +config PHYCORE_IMX8MM_RAM_SIZE_4GB + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-i.MX8MM + instead of runtime detection from EEPROM. + +endchoice + +config PHYCORE_IMX8MM_RAM_STATIC_SOM_REV + bool "Set static phyCORE-i.MX8MM SoM revision for RAM timing setup" + default false + help + phyCORE-i.MX8MM SoM revision 7 uses a updated set of optimized + RAM timings compared to revision 6 and older. Set the SoM + revision during compile time instead of being detected. + +choice + prompt "phyCORE-i.MX8MM RAM timing SoM revision static config" + depends on PHYCORE_IMX8MM_RAM_STATIC_SOM_REV + default PHYCORE_IMX8MM_USE_SOM_REV_7 + help + Use a fixed revision setting instead of runtime + auto detection. + +config PHYCORE_IMX8MM_USE_SOM_REV_6 + bool "RAM Timings for SoM Revisions 6 and older" + help + Use optimized RAM Timings for phyCORE-i.MX8MM SoM Revisions 6 + and older instead of autodetecting. + +config PHYCORE_IMX8MM_USE_SOM_REV_7 + bool "RAM Timings for SoM Revision 7" + help + Use optimized RAM Timings for phyCORE-i.MX8MM SoM Revision 7 + instead of autodetecting. +endchoice + source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.c b/board/phytec/phycore_imx8mm/lpddr4_timing.c index f5a2f3268b3..162b0209d92 100644 --- a/board/phytec/phycore_imx8mm/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mm/lpddr4_timing.c @@ -1,16 +1,17 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2019 NXP - * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Copyright 2025 NXP + * Copyright 2025 PHYTEC Messtechnik GmbH * - * Generated code from MX8M_DDR_tool + * Code partially generated with DDR Tool v3.6.0_22-aa018543. + * DDR PHY FW2017.09 */ #include <linux/kernel.h> #include <asm/arch/ddr.h> +/* Initialize DDRC registers */ static struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ {0x3d400304, 0x1}, {0x3d400030, 0x1}, {0x3d400000, 0xa1080020}, @@ -20,9 +21,9 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d4000d0, 0xc00305ba}, {0x3d4000d4, 0x940000}, {0x3d4000dc, 0xd4002d}, - {0x3d4000e0, 0x310000}, - {0x3d4000e8, 0x66004d}, - {0x3d4000ec, 0x16004d}, + {0x3d4000e0, 0xe10000}, + {0x3d4000e8, 0x54004d}, + {0x3d4000ec, 0x15004d}, {0x3d400100, 0x191e0c20}, {0x3d400104, 0x60630}, {0x3d40010c, 0xb0b000}, @@ -37,17 +38,17 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400180, 0x2ee0017}, {0x3d400184, 0x2605b8e}, {0x3d400188, 0x0}, - {0x3d400190, 0x497820a}, + {0x3d400190, 0x49b820a}, {0x3d400194, 0x80303}, - {0x3d4001b4, 0x170a}, + {0x3d4001b4, 0x1b0a}, {0x3d4001a0, 0xe0400018}, {0x3d4001a4, 0xdf00e4}, {0x3d4001a8, 0x80000000}, {0x3d4001b0, 0x11}, - {0x3d4001c0, 0x1}, + {0x3d4001c0, 0x7}, {0x3d4001c4, 0x1}, {0x3d4000f4, 0x699}, - {0x3d400108, 0x70e1617}, + {0x3d400108, 0x7101817}, {0x3d400200, 0x1f}, {0x3d40020c, 0x0}, {0x3d400210, 0x1f1f}, @@ -66,56 +67,6 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400498, 0x620096}, {0x3d40049c, 0x1100e07}, {0x3d4004a0, 0xc8012c}, - {0x3d402020, 0x20}, - {0x3d402024, 0x7d00}, - {0x3d402050, 0x20d040}, - {0x3d402064, 0x6001c}, - {0x3d4020dc, 0x840000}, - {0x3d4020e0, 0x310000}, - {0x3d4020e8, 0x66004d}, - {0x3d4020ec, 0x16004d}, - {0x3d402100, 0xa040105}, - {0x3d402104, 0x30407}, - {0x3d402108, 0x203060b}, - {0x3d40210c, 0x505000}, - {0x3d402110, 0x2040202}, - {0x3d402114, 0x2030202}, - {0x3d402118, 0x1010004}, - {0x3d40211c, 0x302}, - {0x3d402130, 0x20300}, - {0x3d402134, 0xa100002}, - {0x3d402138, 0x1d}, - {0x3d402144, 0x14000a}, - {0x3d402180, 0x640004}, - {0x3d402190, 0x3818200}, - {0x3d402194, 0x80303}, - {0x3d4021b4, 0x100}, - {0x3d4020f4, 0x599}, - {0x3d403020, 0x20}, - {0x3d403024, 0x1f40}, - {0x3d403050, 0x20d040}, - {0x3d403064, 0x30007}, - {0x3d4030dc, 0x840000}, - {0x3d4030e0, 0x310000}, - {0x3d4030e8, 0x66004d}, - {0x3d4030ec, 0x16004d}, - {0x3d403100, 0xa010102}, - {0x3d403104, 0x30404}, - {0x3d403108, 0x203060b}, - {0x3d40310c, 0x505000}, - {0x3d403110, 0x2040202}, - {0x3d403114, 0x2030202}, - {0x3d403118, 0x1010004}, - {0x3d40311c, 0x302}, - {0x3d403130, 0x20300}, - {0x3d403134, 0xa100002}, - {0x3d403138, 0x8}, - {0x3d403144, 0x50003}, - {0x3d403180, 0x190004}, - {0x3d403190, 0x3818200}, - {0x3d403194, 0x80303}, - {0x3d4031b4, 0x100}, - {0x3d4030f4, 0x599}, {0x3d400028, 0x0}, }; @@ -161,22 +112,6 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x1215f, 0x1ff}, {0x1305f, 0x1ff}, {0x1315f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x11205f, 0x1ff}, - {0x11215f, 0x1ff}, - {0x11305f, 0x1ff}, - {0x11315f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x21205f, 0x1ff}, - {0x21215f, 0x1ff}, - {0x21305f, 0x1ff}, - {0x21315f, 0x1ff}, {0x55, 0x1ff}, {0x1055, 0x1ff}, {0x2055, 0x1ff}, @@ -188,87 +123,41 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x8055, 0x1ff}, {0x9055, 0x1ff}, {0x200c5, 0x19}, - {0x1200c5, 0x7}, - {0x2200c5, 0x7}, {0x2002e, 0x2}, - {0x12002e, 0x2}, - {0x22002e, 0x2}, {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, {0x20024, 0x1ab}, {0x2003a, 0x0}, - {0x120024, 0x1ab}, - {0x2003a, 0x0}, - {0x220024, 0x1ab}, - {0x2003a, 0x0}, {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0xe00}, - {0x1014d, 0xe00}, - {0x1104d, 0xe00}, - {0x1114d, 0xe00}, - {0x1204d, 0xe00}, - {0x1214d, 0xe00}, - {0x1304d, 0xe00}, - {0x1314d, 0xe00}, - {0x11004d, 0xe00}, - {0x11014d, 0xe00}, - {0x11104d, 0xe00}, - {0x11114d, 0xe00}, - {0x11204d, 0xe00}, - {0x11214d, 0xe00}, - {0x11304d, 0xe00}, - {0x11314d, 0xe00}, - {0x21004d, 0xe00}, - {0x21014d, 0xe00}, - {0x21104d, 0xe00}, - {0x21114d, 0xe00}, - {0x21204d, 0xe00}, - {0x21214d, 0xe00}, - {0x21304d, 0xe00}, - {0x21314d, 0xe00}, - {0x10049, 0xeba}, - {0x10149, 0xeba}, - {0x11049, 0xeba}, - {0x11149, 0xeba}, - {0x12049, 0xeba}, - {0x12149, 0xeba}, - {0x13049, 0xeba}, - {0x13149, 0xeba}, - {0x110049, 0xeba}, - {0x110149, 0xeba}, - {0x111049, 0xeba}, - {0x111149, 0xeba}, - {0x112049, 0xeba}, - {0x112149, 0xeba}, - {0x113049, 0xeba}, - {0x113149, 0xeba}, - {0x210049, 0xeba}, - {0x210149, 0xeba}, - {0x211049, 0xeba}, - {0x211149, 0xeba}, - {0x212049, 0xeba}, - {0x212149, 0xeba}, - {0x213049, 0xeba}, - {0x213149, 0xeba}, - {0x43, 0x63}, - {0x1043, 0x63}, - {0x2043, 0x63}, - {0x3043, 0x63}, - {0x4043, 0x63}, - {0x5043, 0x63}, - {0x6043, 0x63}, - {0x7043, 0x63}, - {0x8043, 0x63}, - {0x9043, 0x63}, + {0x1004d, 0x680}, + {0x1014d, 0x680}, + {0x1104d, 0x680}, + {0x1114d, 0x680}, + {0x1204d, 0x680}, + {0x1214d, 0x680}, + {0x1304d, 0x680}, + {0x1314d, 0x680}, + {0x10049, 0x28a}, + {0x10149, 0x28a}, + {0x11049, 0x28a}, + {0x11149, 0x28a}, + {0x12049, 0x28a}, + {0x12149, 0x28a}, + {0x13049, 0x28a}, + {0x13149, 0x28a}, + {0x43, 0x21}, + {0x1043, 0x21}, + {0x2043, 0x21}, + {0x3043, 0x21}, + {0x4043, 0x21}, + {0x5043, 0x21}, + {0x6043, 0x21}, + {0x7043, 0x21}, + {0x8043, 0x21}, + {0x9043, 0x21}, {0x20018, 0x3}, {0x20075, 0x4}, {0x20050, 0x0}, {0x20008, 0x2ee}, - {0x120008, 0x64}, - {0x220008, 0x19}, {0x20088, 0x9}, {0x200b2, 0xdc}, {0x10043, 0x5a1}, @@ -279,618 +168,864 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x12143, 0x5a1}, {0x13043, 0x5a1}, {0x13143, 0x5a1}, - {0x1200b2, 0xdc}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x112043, 0x5a1}, - {0x112143, 0x5a1}, - {0x113043, 0x5a1}, - {0x113143, 0x5a1}, - {0x2200b2, 0xdc}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x212043, 0x5a1}, - {0x212143, 0x5a1}, - {0x213043, 0x5a1}, - {0x213143, 0x5a1}, {0x200fa, 0x1}, - {0x1200fa, 0x1}, - {0x2200fa, 0x1}, {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x660}, + {0x200f0, 0x0}, {0x200f1, 0x0}, {0x200f2, 0x4444}, {0x200f3, 0x8888}, - {0x200f4, 0x5665}, + {0x200f4, 0x5555}, {0x200f5, 0x0}, {0x200f6, 0x0}, {0x200f7, 0xf000}, {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x21}, - {0x2200c7, 0x21}, + {0x2002d, 0x1}, {0x200ca, 0x24}, {0x1200ca, 0x24}, {0x2200ca, 0x24}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x2200c7, 0x21}, }; -/* ddr phy trained csr */ +/* PHY trained csr */ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x1205f, 0x0}, + {0x1215f, 0x0}, + {0x1305f, 0x0}, + {0x1315f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x3055, 0x0}, + {0x4055, 0x0}, + {0x5055, 0x0}, + {0x6055, 0x0}, + {0x7055, 0x0}, + {0x8055, 0x0}, + {0x9055, 0x0}, + {0x200c5, 0x0}, + {0x2002e, 0x0}, + {0x90204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x20056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x1204d, 0x0}, + {0x1214d, 0x0}, + {0x1304d, 0x0}, + {0x1314d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x12049, 0x0}, + {0x12149, 0x0}, + {0x13049, 0x0}, + {0x13149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x3043, 0x0}, + {0x4043, 0x0}, + {0x5043, 0x0}, + {0x6043, 0x0}, + {0x7043, 0x0}, + {0x8043, 0x0}, + {0x9043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x20008, 0x0}, + {0x20088, 0x0}, {0x200b2, 0x0}, - {0x1200b2, 0x0}, - {0x2200b2, 0x0}, - {0x200cb, 0x0}, {0x10043, 0x0}, - {0x110043, 0x0}, - {0x210043, 0x0}, {0x10143, 0x0}, - {0x110143, 0x0}, - {0x210143, 0x0}, {0x11043, 0x0}, - {0x111043, 0x0}, - {0x211043, 0x0}, {0x11143, 0x0}, - {0x111143, 0x0}, - {0x211143, 0x0}, {0x12043, 0x0}, - {0x112043, 0x0}, - {0x212043, 0x0}, {0x12143, 0x0}, - {0x112143, 0x0}, - {0x212143, 0x0}, {0x13043, 0x0}, - {0x113043, 0x0}, - {0x213043, 0x0}, {0x13143, 0x0}, - {0x113143, 0x0}, - {0x213143, 0x0}, + {0x200fa, 0x0}, + {0x20019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90185, 0x0}, + {0x90186, 0x0}, + {0x90187, 0x0}, + {0x90188, 0x0}, + {0x90189, 0x0}, + {0x9018a, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x400fd, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x12011, 0x0}, + {0x12012, 0x0}, + {0x12013, 0x0}, + {0x12018, 0x0}, + {0x12002, 0x0}, + {0x120b2, 0x0}, + {0x121b4, 0x0}, + {0x122b4, 0x0}, + {0x123b4, 0x0}, + {0x124b4, 0x0}, + {0x125b4, 0x0}, + {0x126b4, 0x0}, + {0x127b4, 0x0}, + {0x128b4, 0x0}, + {0x13011, 0x0}, + {0x13012, 0x0}, + {0x13013, 0x0}, + {0x13018, 0x0}, + {0x13002, 0x0}, + {0x130b2, 0x0}, + {0x131b4, 0x0}, + {0x132b4, 0x0}, + {0x133b4, 0x0}, + {0x134b4, 0x0}, + {0x135b4, 0x0}, + {0x136b4, 0x0}, + {0x137b4, 0x0}, + {0x138b4, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x12068, 0x0}, + {0x12069, 0x0}, + {0x12168, 0x0}, + {0x12169, 0x0}, + {0x120aa, 0x0}, + {0x12062, 0x0}, + {0x12001, 0x0}, + {0x13068, 0x0}, + {0x13069, 0x0}, + {0x13168, 0x0}, + {0x13169, 0x0}, + {0x130aa, 0x0}, + {0x13062, 0x0}, + {0x13001, 0x0}, {0x80, 0x0}, - {0x100080, 0x0}, - {0x200080, 0x0}, {0x1080, 0x0}, - {0x101080, 0x0}, - {0x201080, 0x0}, {0x2080, 0x0}, - {0x102080, 0x0}, - {0x202080, 0x0}, {0x3080, 0x0}, - {0x103080, 0x0}, - {0x203080, 0x0}, {0x4080, 0x0}, - {0x104080, 0x0}, - {0x204080, 0x0}, {0x5080, 0x0}, - {0x105080, 0x0}, - {0x205080, 0x0}, {0x6080, 0x0}, - {0x106080, 0x0}, - {0x206080, 0x0}, {0x7080, 0x0}, - {0x107080, 0x0}, - {0x207080, 0x0}, {0x8080, 0x0}, - {0x108080, 0x0}, - {0x208080, 0x0}, {0x9080, 0x0}, - {0x109080, 0x0}, - {0x209080, 0x0}, + {0x10020, 0x0}, {0x10080, 0x0}, - {0x110080, 0x0}, - {0x210080, 0x0}, - {0x10180, 0x0}, - {0x110180, 0x0}, - {0x210180, 0x0}, - {0x11080, 0x0}, - {0x111080, 0x0}, - {0x211080, 0x0}, - {0x11180, 0x0}, - {0x111180, 0x0}, - {0x211180, 0x0}, - {0x12080, 0x0}, - {0x112080, 0x0}, - {0x212080, 0x0}, - {0x12180, 0x0}, - {0x112180, 0x0}, - {0x212180, 0x0}, - {0x13080, 0x0}, - {0x113080, 0x0}, - {0x213080, 0x0}, - {0x13180, 0x0}, - {0x113180, 0x0}, - {0x213180, 0x0}, {0x10081, 0x0}, - {0x110081, 0x0}, - {0x210081, 0x0}, - {0x10181, 0x0}, - {0x110181, 0x0}, - {0x210181, 0x0}, - {0x11081, 0x0}, - {0x111081, 0x0}, - {0x211081, 0x0}, - {0x11181, 0x0}, - {0x111181, 0x0}, - {0x211181, 0x0}, - {0x12081, 0x0}, - {0x112081, 0x0}, - {0x212081, 0x0}, - {0x12181, 0x0}, - {0x112181, 0x0}, - {0x212181, 0x0}, - {0x13081, 0x0}, - {0x113081, 0x0}, - {0x213081, 0x0}, - {0x13181, 0x0}, - {0x113181, 0x0}, - {0x213181, 0x0}, {0x100d0, 0x0}, - {0x1100d0, 0x0}, - {0x2100d0, 0x0}, - {0x101d0, 0x0}, - {0x1101d0, 0x0}, - {0x2101d0, 0x0}, - {0x110d0, 0x0}, - {0x1110d0, 0x0}, - {0x2110d0, 0x0}, - {0x111d0, 0x0}, - {0x1111d0, 0x0}, - {0x2111d0, 0x0}, - {0x120d0, 0x0}, - {0x1120d0, 0x0}, - {0x2120d0, 0x0}, - {0x121d0, 0x0}, - {0x1121d0, 0x0}, - {0x2121d0, 0x0}, - {0x130d0, 0x0}, - {0x1130d0, 0x0}, - {0x2130d0, 0x0}, - {0x131d0, 0x0}, - {0x1131d0, 0x0}, - {0x2131d0, 0x0}, {0x100d1, 0x0}, - {0x1100d1, 0x0}, - {0x2100d1, 0x0}, - {0x101d1, 0x0}, - {0x1101d1, 0x0}, - {0x2101d1, 0x0}, - {0x110d1, 0x0}, - {0x1110d1, 0x0}, - {0x2110d1, 0x0}, - {0x111d1, 0x0}, - {0x1111d1, 0x0}, - {0x2111d1, 0x0}, - {0x120d1, 0x0}, - {0x1120d1, 0x0}, - {0x2120d1, 0x0}, - {0x121d1, 0x0}, - {0x1121d1, 0x0}, - {0x2121d1, 0x0}, - {0x130d1, 0x0}, - {0x1130d1, 0x0}, - {0x2130d1, 0x0}, - {0x131d1, 0x0}, - {0x1131d1, 0x0}, - {0x2131d1, 0x0}, - {0x10068, 0x0}, - {0x10168, 0x0}, - {0x10268, 0x0}, - {0x10368, 0x0}, - {0x10468, 0x0}, - {0x10568, 0x0}, - {0x10668, 0x0}, - {0x10768, 0x0}, - {0x10868, 0x0}, - {0x11068, 0x0}, - {0x11168, 0x0}, - {0x11268, 0x0}, - {0x11368, 0x0}, - {0x11468, 0x0}, - {0x11568, 0x0}, - {0x11668, 0x0}, - {0x11768, 0x0}, - {0x11868, 0x0}, - {0x12068, 0x0}, - {0x12168, 0x0}, - {0x12268, 0x0}, - {0x12368, 0x0}, - {0x12468, 0x0}, - {0x12568, 0x0}, - {0x12668, 0x0}, - {0x12768, 0x0}, - {0x12868, 0x0}, - {0x13068, 0x0}, - {0x13168, 0x0}, - {0x13268, 0x0}, - {0x13368, 0x0}, - {0x13468, 0x0}, - {0x13568, 0x0}, - {0x13668, 0x0}, - {0x13768, 0x0}, - {0x13868, 0x0}, - {0x10069, 0x0}, - {0x10169, 0x0}, - {0x10269, 0x0}, - {0x10369, 0x0}, - {0x10469, 0x0}, - {0x10569, 0x0}, - {0x10669, 0x0}, - {0x10769, 0x0}, - {0x10869, 0x0}, - {0x11069, 0x0}, - {0x11169, 0x0}, - {0x11269, 0x0}, - {0x11369, 0x0}, - {0x11469, 0x0}, - {0x11569, 0x0}, - {0x11669, 0x0}, - {0x11769, 0x0}, - {0x11869, 0x0}, - {0x12069, 0x0}, - {0x12169, 0x0}, - {0x12269, 0x0}, - {0x12369, 0x0}, - {0x12469, 0x0}, - {0x12569, 0x0}, - {0x12669, 0x0}, - {0x12769, 0x0}, - {0x12869, 0x0}, - {0x13069, 0x0}, - {0x13169, 0x0}, - {0x13269, 0x0}, - {0x13369, 0x0}, - {0x13469, 0x0}, - {0x13569, 0x0}, - {0x13669, 0x0}, - {0x13769, 0x0}, - {0x13869, 0x0}, {0x1008c, 0x0}, - {0x11008c, 0x0}, - {0x21008c, 0x0}, - {0x1018c, 0x0}, - {0x11018c, 0x0}, - {0x21018c, 0x0}, - {0x1108c, 0x0}, - {0x11108c, 0x0}, - {0x21108c, 0x0}, - {0x1118c, 0x0}, - {0x11118c, 0x0}, - {0x21118c, 0x0}, - {0x1208c, 0x0}, - {0x11208c, 0x0}, - {0x21208c, 0x0}, - {0x1218c, 0x0}, - {0x11218c, 0x0}, - {0x21218c, 0x0}, - {0x1308c, 0x0}, - {0x11308c, 0x0}, - {0x21308c, 0x0}, - {0x1318c, 0x0}, - {0x11318c, 0x0}, - {0x21318c, 0x0}, {0x1008d, 0x0}, - {0x11008d, 0x0}, - {0x21008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, {0x1018d, 0x0}, - {0x11018d, 0x0}, - {0x21018d, 0x0}, - {0x1108d, 0x0}, - {0x11108d, 0x0}, - {0x21108d, 0x0}, - {0x1118d, 0x0}, - {0x11118d, 0x0}, - {0x21118d, 0x0}, - {0x1208d, 0x0}, - {0x11208d, 0x0}, - {0x21208d, 0x0}, - {0x1218d, 0x0}, - {0x11218d, 0x0}, - {0x21218d, 0x0}, - {0x1308d, 0x0}, - {0x11308d, 0x0}, - {0x21308d, 0x0}, - {0x1318d, 0x0}, - {0x11318d, 0x0}, - {0x21318d, 0x0}, {0x100c0, 0x0}, - {0x1100c0, 0x0}, - {0x2100c0, 0x0}, - {0x101c0, 0x0}, - {0x1101c0, 0x0}, - {0x2101c0, 0x0}, - {0x102c0, 0x0}, - {0x1102c0, 0x0}, - {0x2102c0, 0x0}, - {0x103c0, 0x0}, - {0x1103c0, 0x0}, - {0x2103c0, 0x0}, - {0x104c0, 0x0}, - {0x1104c0, 0x0}, - {0x2104c0, 0x0}, - {0x105c0, 0x0}, - {0x1105c0, 0x0}, - {0x2105c0, 0x0}, - {0x106c0, 0x0}, - {0x1106c0, 0x0}, - {0x2106c0, 0x0}, - {0x107c0, 0x0}, - {0x1107c0, 0x0}, - {0x2107c0, 0x0}, - {0x108c0, 0x0}, - {0x1108c0, 0x0}, - {0x2108c0, 0x0}, - {0x110c0, 0x0}, - {0x1110c0, 0x0}, - {0x2110c0, 0x0}, - {0x111c0, 0x0}, - {0x1111c0, 0x0}, - {0x2111c0, 0x0}, - {0x112c0, 0x0}, - {0x1112c0, 0x0}, - {0x2112c0, 0x0}, - {0x113c0, 0x0}, - {0x1113c0, 0x0}, - {0x2113c0, 0x0}, - {0x114c0, 0x0}, - {0x1114c0, 0x0}, - {0x2114c0, 0x0}, - {0x115c0, 0x0}, - {0x1115c0, 0x0}, - {0x2115c0, 0x0}, - {0x116c0, 0x0}, - {0x1116c0, 0x0}, - {0x2116c0, 0x0}, - {0x117c0, 0x0}, - {0x1117c0, 0x0}, - {0x2117c0, 0x0}, - {0x118c0, 0x0}, - {0x1118c0, 0x0}, - {0x2118c0, 0x0}, - {0x120c0, 0x0}, - {0x1120c0, 0x0}, - {0x2120c0, 0x0}, - {0x121c0, 0x0}, - {0x1121c0, 0x0}, - {0x2121c0, 0x0}, - {0x122c0, 0x0}, - {0x1122c0, 0x0}, - {0x2122c0, 0x0}, - {0x123c0, 0x0}, - {0x1123c0, 0x0}, - {0x2123c0, 0x0}, - {0x124c0, 0x0}, - {0x1124c0, 0x0}, - {0x2124c0, 0x0}, - {0x125c0, 0x0}, - {0x1125c0, 0x0}, - {0x2125c0, 0x0}, - {0x126c0, 0x0}, - {0x1126c0, 0x0}, - {0x2126c0, 0x0}, - {0x127c0, 0x0}, - {0x1127c0, 0x0}, - {0x2127c0, 0x0}, - {0x128c0, 0x0}, - {0x1128c0, 0x0}, - {0x2128c0, 0x0}, - {0x130c0, 0x0}, - {0x1130c0, 0x0}, - {0x2130c0, 0x0}, - {0x131c0, 0x0}, - {0x1131c0, 0x0}, - {0x2131c0, 0x0}, - {0x132c0, 0x0}, - {0x1132c0, 0x0}, - {0x2132c0, 0x0}, - {0x133c0, 0x0}, - {0x1133c0, 0x0}, - {0x2133c0, 0x0}, - {0x134c0, 0x0}, - {0x1134c0, 0x0}, - {0x2134c0, 0x0}, - {0x135c0, 0x0}, - {0x1135c0, 0x0}, - {0x2135c0, 0x0}, - {0x136c0, 0x0}, - {0x1136c0, 0x0}, - {0x2136c0, 0x0}, - {0x137c0, 0x0}, - {0x1137c0, 0x0}, - {0x2137c0, 0x0}, - {0x138c0, 0x0}, - {0x1138c0, 0x0}, - {0x2138c0, 0x0}, {0x100c1, 0x0}, - {0x1100c1, 0x0}, - {0x2100c1, 0x0}, + {0x101c0, 0x0}, {0x101c1, 0x0}, - {0x1101c1, 0x0}, - {0x2101c1, 0x0}, + {0x102c0, 0x0}, {0x102c1, 0x0}, - {0x1102c1, 0x0}, - {0x2102c1, 0x0}, + {0x103c0, 0x0}, {0x103c1, 0x0}, - {0x1103c1, 0x0}, - {0x2103c1, 0x0}, + {0x104c0, 0x0}, {0x104c1, 0x0}, - {0x1104c1, 0x0}, - {0x2104c1, 0x0}, + {0x105c0, 0x0}, {0x105c1, 0x0}, - {0x1105c1, 0x0}, - {0x2105c1, 0x0}, + {0x106c0, 0x0}, {0x106c1, 0x0}, - {0x1106c1, 0x0}, - {0x2106c1, 0x0}, + {0x107c0, 0x0}, {0x107c1, 0x0}, - {0x1107c1, 0x0}, - {0x2107c1, 0x0}, + {0x108c0, 0x0}, {0x108c1, 0x0}, - {0x1108c1, 0x0}, - {0x2108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, {0x110c1, 0x0}, - {0x1110c1, 0x0}, - {0x2110c1, 0x0}, + {0x111c0, 0x0}, {0x111c1, 0x0}, - {0x1111c1, 0x0}, - {0x2111c1, 0x0}, + {0x112c0, 0x0}, {0x112c1, 0x0}, - {0x1112c1, 0x0}, - {0x2112c1, 0x0}, + {0x113c0, 0x0}, {0x113c1, 0x0}, - {0x1113c1, 0x0}, - {0x2113c1, 0x0}, + {0x114c0, 0x0}, {0x114c1, 0x0}, - {0x1114c1, 0x0}, - {0x2114c1, 0x0}, + {0x115c0, 0x0}, {0x115c1, 0x0}, - {0x1115c1, 0x0}, - {0x2115c1, 0x0}, + {0x116c0, 0x0}, {0x116c1, 0x0}, - {0x1116c1, 0x0}, - {0x2116c1, 0x0}, + {0x117c0, 0x0}, {0x117c1, 0x0}, - {0x1117c1, 0x0}, - {0x2117c1, 0x0}, + {0x118c0, 0x0}, {0x118c1, 0x0}, - {0x1118c1, 0x0}, - {0x2118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x12020, 0x0}, + {0x12080, 0x0}, + {0x12081, 0x0}, + {0x120d0, 0x0}, + {0x120d1, 0x0}, + {0x1208c, 0x0}, + {0x1208d, 0x0}, + {0x12180, 0x0}, + {0x12181, 0x0}, + {0x121d0, 0x0}, + {0x121d1, 0x0}, + {0x1218c, 0x0}, + {0x1218d, 0x0}, + {0x120c0, 0x0}, {0x120c1, 0x0}, - {0x1120c1, 0x0}, - {0x2120c1, 0x0}, + {0x121c0, 0x0}, {0x121c1, 0x0}, - {0x1121c1, 0x0}, - {0x2121c1, 0x0}, + {0x122c0, 0x0}, {0x122c1, 0x0}, - {0x1122c1, 0x0}, - {0x2122c1, 0x0}, + {0x123c0, 0x0}, {0x123c1, 0x0}, - {0x1123c1, 0x0}, - {0x2123c1, 0x0}, + {0x124c0, 0x0}, {0x124c1, 0x0}, - {0x1124c1, 0x0}, - {0x2124c1, 0x0}, + {0x125c0, 0x0}, {0x125c1, 0x0}, - {0x1125c1, 0x0}, - {0x2125c1, 0x0}, + {0x126c0, 0x0}, {0x126c1, 0x0}, - {0x1126c1, 0x0}, - {0x2126c1, 0x0}, + {0x127c0, 0x0}, {0x127c1, 0x0}, - {0x1127c1, 0x0}, - {0x2127c1, 0x0}, + {0x128c0, 0x0}, {0x128c1, 0x0}, - {0x1128c1, 0x0}, - {0x2128c1, 0x0}, + {0x120ae, 0x0}, + {0x120af, 0x0}, + {0x120a0, 0x0}, + {0x120a1, 0x0}, + {0x120a2, 0x0}, + {0x120a3, 0x0}, + {0x120a4, 0x0}, + {0x120a5, 0x0}, + {0x120a6, 0x0}, + {0x120a7, 0x0}, + {0x13020, 0x0}, + {0x13080, 0x0}, + {0x13081, 0x0}, + {0x130d0, 0x0}, + {0x130d1, 0x0}, + {0x1308c, 0x0}, + {0x1308d, 0x0}, + {0x13180, 0x0}, + {0x13181, 0x0}, + {0x131d0, 0x0}, + {0x131d1, 0x0}, + {0x1318c, 0x0}, + {0x1318d, 0x0}, + {0x130c0, 0x0}, {0x130c1, 0x0}, - {0x1130c1, 0x0}, - {0x2130c1, 0x0}, + {0x131c0, 0x0}, {0x131c1, 0x0}, - {0x1131c1, 0x0}, - {0x2131c1, 0x0}, + {0x132c0, 0x0}, {0x132c1, 0x0}, - {0x1132c1, 0x0}, - {0x2132c1, 0x0}, + {0x133c0, 0x0}, {0x133c1, 0x0}, - {0x1133c1, 0x0}, - {0x2133c1, 0x0}, + {0x134c0, 0x0}, {0x134c1, 0x0}, - {0x1134c1, 0x0}, - {0x2134c1, 0x0}, + {0x135c0, 0x0}, {0x135c1, 0x0}, - {0x1135c1, 0x0}, - {0x2135c1, 0x0}, + {0x136c0, 0x0}, {0x136c1, 0x0}, - {0x1136c1, 0x0}, - {0x2136c1, 0x0}, + {0x137c0, 0x0}, {0x137c1, 0x0}, - {0x1137c1, 0x0}, - {0x2137c1, 0x0}, + {0x138c0, 0x0}, {0x138c1, 0x0}, - {0x1138c1, 0x0}, - {0x2138c1, 0x0}, - {0x10020, 0x0}, - {0x110020, 0x0}, - {0x210020, 0x0}, - {0x11020, 0x0}, - {0x111020, 0x0}, - {0x211020, 0x0}, - {0x12020, 0x0}, - {0x112020, 0x0}, - {0x212020, 0x0}, - {0x13020, 0x0}, - {0x113020, 0x0}, - {0x213020, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x20074, 0x0}, - {0x100aa, 0x0}, - {0x110aa, 0x0}, - {0x120aa, 0x0}, - {0x130aa, 0x0}, - {0x20010, 0x0}, - {0x120010, 0x0}, - {0x220010, 0x0}, - {0x20011, 0x0}, - {0x120011, 0x0}, - {0x220011, 0x0}, - {0x100ae, 0x0}, - {0x1100ae, 0x0}, - {0x2100ae, 0x0}, - {0x100af, 0x0}, - {0x1100af, 0x0}, - {0x2100af, 0x0}, - {0x110ae, 0x0}, - {0x1110ae, 0x0}, - {0x2110ae, 0x0}, - {0x110af, 0x0}, - {0x1110af, 0x0}, - {0x2110af, 0x0}, - {0x120ae, 0x0}, - {0x1120ae, 0x0}, - {0x2120ae, 0x0}, - {0x120af, 0x0}, - {0x1120af, 0x0}, - {0x2120af, 0x0}, {0x130ae, 0x0}, - {0x1130ae, 0x0}, - {0x2130ae, 0x0}, {0x130af, 0x0}, - {0x1130af, 0x0}, - {0x2130af, 0x0}, - {0x20020, 0x0}, - {0x120020, 0x0}, - {0x220020, 0x0}, - {0x100a0, 0x0}, - {0x100a1, 0x0}, - {0x100a2, 0x0}, - {0x100a3, 0x0}, - {0x100a4, 0x0}, - {0x100a5, 0x0}, - {0x100a6, 0x0}, - {0x100a7, 0x0}, - {0x110a0, 0x0}, - {0x110a1, 0x0}, - {0x110a2, 0x0}, - {0x110a3, 0x0}, - {0x110a4, 0x0}, - {0x110a5, 0x0}, - {0x110a6, 0x0}, - {0x110a7, 0x0}, - {0x120a0, 0x0}, - {0x120a1, 0x0}, - {0x120a2, 0x0}, - {0x120a3, 0x0}, - {0x120a4, 0x0}, - {0x120a5, 0x0}, - {0x120a6, 0x0}, - {0x120a7, 0x0}, {0x130a0, 0x0}, {0x130a1, 0x0}, {0x130a2, 0x0}, @@ -899,306 +1034,108 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { {0x130a5, 0x0}, {0x130a6, 0x0}, {0x130a7, 0x0}, - {0x2007c, 0x0}, - {0x12007c, 0x0}, - {0x22007c, 0x0}, - {0x2007d, 0x0}, - {0x12007d, 0x0}, - {0x22007d, 0x0}, - {0x400fd, 0x0}, - {0x400c0, 0x0}, {0x90201, 0x0}, - {0x190201, 0x0}, - {0x290201, 0x0}, {0x90202, 0x0}, - {0x190202, 0x0}, - {0x290202, 0x0}, {0x90203, 0x0}, - {0x190203, 0x0}, - {0x290203, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, {0x90205, 0x0}, - {0x190205, 0x0}, - {0x290205, 0x0}, {0x90206, 0x0}, - {0x190206, 0x0}, - {0x290206, 0x0}, {0x90207, 0x0}, - {0x190207, 0x0}, - {0x290207, 0x0}, {0x90208, 0x0}, - {0x190208, 0x0}, - {0x290208, 0x0}, - {0x10062, 0x0}, - {0x10162, 0x0}, - {0x10262, 0x0}, - {0x10362, 0x0}, - {0x10462, 0x0}, - {0x10562, 0x0}, - {0x10662, 0x0}, - {0x10762, 0x0}, - {0x10862, 0x0}, - {0x11062, 0x0}, - {0x11162, 0x0}, - {0x11262, 0x0}, - {0x11362, 0x0}, - {0x11462, 0x0}, - {0x11562, 0x0}, - {0x11662, 0x0}, - {0x11762, 0x0}, - {0x11862, 0x0}, - {0x12062, 0x0}, - {0x12162, 0x0}, - {0x12262, 0x0}, - {0x12362, 0x0}, - {0x12462, 0x0}, - {0x12562, 0x0}, - {0x12662, 0x0}, - {0x12762, 0x0}, - {0x12862, 0x0}, - {0x13062, 0x0}, - {0x13162, 0x0}, - {0x13262, 0x0}, - {0x13362, 0x0}, - {0x13462, 0x0}, - {0x13562, 0x0}, - {0x13662, 0x0}, - {0x13762, 0x0}, - {0x13862, 0x0}, + {0x2007c, 0x0}, + {0x2007d, 0x0}, + {0x20020, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, {0x20077, 0x0}, - {0x10001, 0x0}, - {0x11001, 0x0}, - {0x12001, 0x0}, - {0x13001, 0x0}, + {0x400c0, 0x0}, {0x10040, 0x0}, {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x10030, 0x0}, - {0x10130, 0x0}, - {0x10230, 0x0}, - {0x10330, 0x0}, - {0x10430, 0x0}, - {0x10530, 0x0}, - {0x10630, 0x0}, - {0x10730, 0x0}, - {0x10830, 0x0}, {0x11040, 0x0}, {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, - {0x11030, 0x0}, - {0x11130, 0x0}, - {0x11230, 0x0}, - {0x11330, 0x0}, - {0x11430, 0x0}, - {0x11530, 0x0}, - {0x11630, 0x0}, - {0x11730, 0x0}, - {0x11830, 0x0}, {0x12040, 0x0}, {0x12140, 0x0}, - {0x12240, 0x0}, - {0x12340, 0x0}, - {0x12440, 0x0}, - {0x12540, 0x0}, - {0x12640, 0x0}, - {0x12740, 0x0}, - {0x12840, 0x0}, - {0x12030, 0x0}, - {0x12130, 0x0}, - {0x12230, 0x0}, - {0x12330, 0x0}, - {0x12430, 0x0}, - {0x12530, 0x0}, - {0x12630, 0x0}, - {0x12730, 0x0}, - {0x12830, 0x0}, {0x13040, 0x0}, {0x13140, 0x0}, - {0x13240, 0x0}, - {0x13340, 0x0}, - {0x13440, 0x0}, - {0x13540, 0x0}, - {0x13640, 0x0}, - {0x13740, 0x0}, - {0x13840, 0x0}, - {0x13030, 0x0}, - {0x13130, 0x0}, - {0x13230, 0x0}, - {0x13330, 0x0}, - {0x13430, 0x0}, - {0x13530, 0x0}, - {0x13630, 0x0}, - {0x13730, 0x0}, - {0x13830, 0x0}, }; -/* P0 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp0_cfg[] = { + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { {0xd0000, 0x0}, {0x54003, 0xbb8}, {0x54004, 0x2}, - {0x54005, 0x2228}, + {0x54005, 0x5030}, {0x54006, 0x11}, {0x54008, 0x131f}, {0x54009, 0xc8}, {0x5400b, 0x2}, {0x54012, 0x110}, {0x54019, 0x2dd4}, - {0x5401a, 0x31}, - {0x5401b, 0x4d66}, + {0x5401a, 0xe1}, + {0x5401b, 0x4d54}, {0x5401c, 0x4d00}, - {0x5401e, 0x16}, + {0x5401e, 0x15}, {0x5401f, 0x2dd4}, - {0x54020, 0x31}, - {0x54021, 0x4d66}, + {0x54020, 0xe1}, + {0x54021, 0x4d54}, {0x54022, 0x4d00}, - {0x54024, 0x16}, + {0x54024, 0x15}, {0x5402b, 0x1000}, {0x5402c, 0x1}, {0x54032, 0xd400}, - {0x54033, 0x312d}, - {0x54034, 0x6600}, + {0x54033, 0xe12d}, + {0x54034, 0x5400}, {0x54035, 0x4d}, {0x54036, 0x4d}, - {0x54037, 0x1600}, + {0x54037, 0x1500}, {0x54038, 0xd400}, - {0x54039, 0x312d}, - {0x5403a, 0x6600}, - {0x5403b, 0x4d}, - {0x5403c, 0x4d}, - {0x5403d, 0x1600}, - {0xd0000, 0x1}, -}; - -/* P1 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x101}, - {0x54003, 0x190}, - {0x54004, 0x2}, - {0x54005, 0x2228}, - {0x54006, 0x11}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x2}, - {0x54012, 0x110}, - {0x54019, 0x84}, - {0x5401a, 0x31}, - {0x5401b, 0x4d66}, - {0x5401c, 0x4d00}, - {0x5401e, 0x16}, - {0x5401f, 0x84}, - {0x54020, 0x31}, - {0x54021, 0x4d66}, - {0x54022, 0x4d00}, - {0x54024, 0x16}, - {0x5402b, 0x1000}, - {0x5402c, 0x1}, - {0x54032, 0x8400}, - {0x54033, 0x3100}, - {0x54034, 0x6600}, - {0x54035, 0x4d}, - {0x54036, 0x4d}, - {0x54037, 0x1600}, - {0x54038, 0x8400}, - {0x54039, 0x3100}, - {0x5403a, 0x6600}, + {0x54039, 0xe12d}, + {0x5403a, 0x5400}, {0x5403b, 0x4d}, {0x5403c, 0x4d}, - {0x5403d, 0x1600}, - {0xd0000, 0x1}, + {0x5403d, 0x1500}, + {0xd0000, 0x1} }; -/* P2 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x64}, - {0x54004, 0x2}, - {0x54005, 0x2228}, - {0x54006, 0x11}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x2}, - {0x54012, 0x110}, - {0x54019, 0x84}, - {0x5401a, 0x31}, - {0x5401b, 0x4d66}, - {0x5401c, 0x4d00}, - {0x5401e, 0x16}, - {0x5401f, 0x84}, - {0x54020, 0x31}, - {0x54021, 0x4d66}, - {0x54022, 0x4d00}, - {0x54024, 0x16}, - {0x5402b, 0x1000}, - {0x5402c, 0x1}, - {0x54032, 0x8400}, - {0x54033, 0x3100}, - {0x54034, 0x6600}, - {0x54035, 0x4d}, - {0x54036, 0x4d}, - {0x54037, 0x1600}, - {0x54038, 0x8400}, - {0x54039, 0x3100}, - {0x5403a, 0x6600}, - {0x5403b, 0x4d}, - {0x5403c, 0x4d}, - {0x5403d, 0x1600}, - {0xd0000, 0x1}, -}; -/* P0 2D message block paremeter for training firmware */ +/* P0 2D message block parameter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { {0xd0000, 0x0}, {0x54003, 0xbb8}, {0x54004, 0x2}, - {0x54005, 0x2228}, + {0x54005, 0x5030}, {0x54006, 0x11}, {0x54008, 0x61}, {0x54009, 0xc8}, {0x5400b, 0x2}, + {0x5400d, 0x100}, {0x5400f, 0x100}, {0x54010, 0x1f7f}, {0x54012, 0x110}, {0x54019, 0x2dd4}, - {0x5401a, 0x31}, - {0x5401b, 0x4d66}, + {0x5401a, 0xe1}, + {0x5401b, 0x4d54}, {0x5401c, 0x4d00}, - {0x5401e, 0x16}, + {0x5401e, 0x15}, {0x5401f, 0x2dd4}, - {0x54020, 0x31}, - {0x54021, 0x4d66}, + {0x54020, 0xe1}, + {0x54021, 0x4d54}, {0x54022, 0x4d00}, - {0x54024, 0x16}, + {0x54024, 0x15}, {0x5402b, 0x1000}, {0x5402c, 0x1}, {0x54032, 0xd400}, - {0x54033, 0x312d}, - {0x54034, 0x6600}, + {0x54033, 0xe12d}, + {0x54034, 0x5400}, {0x54035, 0x4d}, {0x54036, 0x4d}, - {0x54037, 0x1600}, + {0x54037, 0x1500}, {0x54038, 0xd400}, - {0x54039, 0x312d}, - {0x5403a, 0x6600}, + {0x54039, 0xe12d}, + {0x5403a, 0x5400}, {0x5403b, 0x4d}, {0x5403c, 0x4d}, - {0x5403d, 0x1600}, - {0xd0000, 0x1}, + {0x5403d, 0x1500}, + {0xd0000, 0x1} }; /* DRAM PHY init engine image */ @@ -1691,18 +1628,10 @@ static struct dram_cfg_param ddr_phy_pie[] = { {0x400d6, 0x20a}, {0x400d7, 0x20b}, {0x2003a, 0x2}, - {0x2000b, 0x34b}, + {0x2000b, 0x5d}, {0x2000c, 0xbb}, {0x2000d, 0x753}, {0x2000e, 0x2c}, - {0x12000b, 0x70}, - {0x12000c, 0x19}, - {0x12000d, 0xfa}, - {0x12000e, 0x10}, - {0x22000b, 0x1c}, - {0x22000c, 0x6}, - {0x22000d, 0x3e}, - {0x22000e, 0x10}, {0x9000c, 0x0}, {0x9000d, 0x173}, {0x9000e, 0x60}, @@ -1713,28 +1642,12 @@ static struct dram_cfg_param ddr_phy_pie[] = { {0x90013, 0x6152}, {0x20010, 0x5a}, {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x220010, 0x5a}, - {0x220011, 0x3}, {0x40080, 0xe0}, {0x40081, 0x12}, {0x40082, 0xe0}, {0x40083, 0x12}, {0x40084, 0xe0}, {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, {0x400fd, 0xf}, {0x10011, 0x1}, {0x10012, 0x1}, @@ -1794,7 +1707,7 @@ static struct dram_cfg_param ddr_phy_pie[] = { {0x138b4, 0x1}, {0x2003a, 0x2}, {0xc0080, 0x2}, - {0xd0000, 0x1} + {0xd0000, 0x1}, }; static struct dram_fsp_msg ddr_dram_fsp_msg[] = { @@ -1806,20 +1719,6 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), }, { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { /* P0 3000mts 2D */ .drate = 3000, .fw_type = FW_2D_IMAGE, @@ -1840,5 +1739,55 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100,}, + .fsp_table = { 3000, }, }; + +void set_dram_timings_1gb(void) +{ + dram_timing.ddrc_cfg[5].val = 0x2d0087; + dram_timing.ddrc_cfg[21].val = 0x8d; + dram_timing.ddrc_cfg[42].val = 0xf070707; +} + +void set_dram_timings_4gb(void) +{ + dram_timing.ddrc_cfg[2].val = 0xa3080020; + dram_timing.ddrc_cfg[37].val = 0x17; + dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x310; + dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x3; + dram_timing.fsp_msg[1].fsp_cfg[11].val = 0x310; + dram_timing.fsp_msg[1].fsp_cfg[23].val = 0x3; +} + +void set_dram_timings_rev7(void) +{ + dram_timing.ddrc_cfg[10].val = 0x55004d; + dram_timing.ddrphy_cfg[64].val = 0x618; + dram_timing.ddrphy_cfg[65].val = 0x618; + dram_timing.ddrphy_cfg[66].val = 0x618; + dram_timing.ddrphy_cfg[67].val = 0x618; + dram_timing.ddrphy_cfg[68].val = 0x618; + dram_timing.ddrphy_cfg[69].val = 0x618; + dram_timing.ddrphy_cfg[70].val = 0x618; + dram_timing.ddrphy_cfg[71].val = 0x618; + dram_timing.ddrphy_cfg[72].val = 0x63; + dram_timing.ddrphy_cfg[73].val = 0x63; + dram_timing.ddrphy_cfg[74].val = 0x63; + dram_timing.ddrphy_cfg[75].val = 0x63; + dram_timing.ddrphy_cfg[76].val = 0x63; + dram_timing.ddrphy_cfg[77].val = 0x63; + dram_timing.ddrphy_cfg[78].val = 0x63; + dram_timing.ddrphy_cfg[79].val = 0x63; + dram_timing.ddrphy_cfg[80].val = 0x63; + dram_timing.ddrphy_cfg[81].val = 0x63; + dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x3c30; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0x4d55; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0x4d55; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x5500; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x5500; + dram_timing.fsp_msg[1].fsp_cfg[3].val = 0x3c30; + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x4d55; + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x4d55; + dram_timing.fsp_msg[1].fsp_cfg[26].val = 0x5500; + dram_timing.fsp_msg[1].fsp_cfg[32].val = 0x5500; +} diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.h b/board/phytec/phycore_imx8mm/lpddr4_timing.h new file mode 100644 index 00000000000..340fefe01c3 --- /dev/null +++ b/board/phytec/phycore_imx8mm/lpddr4_timing.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +void set_dram_timings_1gb(void); +void set_dram_timings_4gb(void); +void set_dram_timings_rev7(void); + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c index 9f6a4ec704d..25e51dce739 100644 --- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c +++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c @@ -9,6 +9,7 @@ #include <asm/mach-imx/boot_mode.h> #include <env.h> #include <miiphy.h> +#include <init.h> static int setup_fec(void) { @@ -50,3 +51,20 @@ int board_late_init(void) return 0; } + +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + /* + * check various RAM sizes (1, 2 and 4 GB) otherwise + * return the default of 2GB + */ + *size = get_ram_size((void *)PHYS_SDRAM, + (long)PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + if (*size == 0) + *size = SZ_2G; + + return 0; +} diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index e688793bc74..a3879881eb7 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -16,11 +16,19 @@ #include <log.h> #include <spl.h> +#include "lpddr4_timing.h" #include "../common/imx8m_som_detection.h" #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 +enum phytec_imx8mm_ddr_eeprom_code { + INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX8MM_DDR_1GB = 1, + PHYTEC_IMX8MM_DDR_2GB = 3, + PHYTEC_IMX8MM_DDR_4GB = 5, +}; + int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -42,17 +50,63 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) static void spl_dram_init(void) { int ret; + enum phytec_imx8mm_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL; + u8 rev = PHYTEC_EEPROM_INVAL; ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, EEPROM_ADDR_FALLBACK); - if (ret) + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_FIX)) goto out; ret = phytec_imx8m_detect(NULL); if (!ret) phytec_print_som_info(NULL); + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_1GB)) + size = PHYTEC_IMX8MM_DDR_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_2GB)) + size = PHYTEC_IMX8MM_DDR_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_SIZE_4GB)) + size = PHYTEC_IMX8MM_DDR_4GB; + } else { + size = phytec_get_imx8m_ddr_size(NULL); + } + + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_RAM_STATIC_SOM_REV)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_USE_SOM_REV_6)) + rev = 6; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MM_USE_SOM_REV_7)) + rev = 7; + } else { + rev = phytec_get_rev(NULL); + } + + if (rev >= 7 || rev == PHYTEC_EEPROM_INVAL) { + debug("%s: Using rev7 RAM timings.\n", __func__); + set_dram_timings_rev7(); + } else { + debug("%s: Using rev6 RAM timings.\n", __func__); + } + + switch (size) { + case PHYTEC_IMX8MM_DDR_1GB: + set_dram_timings_1gb(); + break; + case PHYTEC_IMX8MM_DDR_2GB: + break; + case PHYTEC_IMX8MM_DDR_4GB: + set_dram_timings_4gb(); + break; + default: + goto out; + } + ddr_init(&dram_timing); + + return; out: + puts("Could not detect correct RAM size. Fall back to default.\n"); + set_dram_timings_rev7(); ddr_init(&dram_timing); } diff --git a/board/purism/librem5-devkit/Kconfig b/board/purism/librem5-devkit/Kconfig new file mode 100644 index 00000000000..3e069690142 --- /dev/null +++ b/board/purism/librem5-devkit/Kconfig @@ -0,0 +1,18 @@ +if TARGET_LIBREM5_DEVKIT + +config SYS_BOARD + default "librem5-devkit" + +config SYS_VENDOR + default "purism" + +config SYS_CONFIG_NAME + default "librem5-devkit" + +config ENV_SOURCE_FILE + default "librem5-devkit" + +config IMX_CONFIG + default "board/purism/librem5-devkit/imximage-8mq-lpddr4.cfg" + +endif diff --git a/board/purism/librem5-devkit/MAINTAINERS b/board/purism/librem5-devkit/MAINTAINERS new file mode 100644 index 00000000000..95bdc17cc8f --- /dev/null +++ b/board/purism/librem5-devkit/MAINTAINERS @@ -0,0 +1,8 @@ +PURISM LIBREM5 DEVKIT +M: Guido Günther +S: Supported +F: arch/arm/dts/imx8mq-librem5-devkit-u-boot.dtsi +F: board/purism/librem5-devkit/ +F: configs/librem5-devkit_defconfig +F: include/configs/librem5-devkit.h diff --git a/board/purism/librem5-devkit/Makefile b/board/purism/librem5-devkit/Makefile new file mode 100644 index 00000000000..95044811186 --- /dev/null +++ b/board/purism/librem5-devkit/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2017 NXP +# Copyright 2026 Phosh.mobi e.V. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += librem5-devkit.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o +endif diff --git a/board/purism/librem5-devkit/imximage-8mq-lpddr4.cfg b/board/purism/librem5-devkit/imximage-8mq-lpddr4.cfg new file mode 100644 index 00000000000..d102e70a954 --- /dev/null +++ b/board/purism/librem5-devkit/imximage-8mq-lpddr4.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +FIT +BOOT_FROM sd +SIGNED_HDMI signed_hdmi_imx8m.bin +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/board/purism/librem5-devkit/librem5-devkit.c b/board/purism/librem5-devkit/librem5-devkit.c new file mode 100644 index 00000000000..bbafd392187 --- /dev/null +++ b/board/purism/librem5-devkit/librem5-devkit.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * 2026 Phosh.mobi e.V. + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch-imx8/gpio.h> +#include <linux/delay.h> +#include <efi_loader.h> +#include <env.h> +#include <miiphy.h> +#include <netdev.h> + +int board_early_init_f(void) +{ + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_LOAD_ENV_FROM_MMC_BOOT_PARTITION) +uint board_mmc_get_env_part(struct mmc *mmc) +{ + uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + if (part == EMMC_BOOT_PART_USER) + part = EMMC_HWPART_DEFAULT; + return part; +} +#endif + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + char fdt_str[50]; + + env_set("board_name", "librem5-devkit"); + /* Shipped boards have PCB rev. 0.1.2 */ + env_set("board_rev", "0"); + printf("Board name: %s\n", env_get("board_name")); + printf("Board rev: %s\n", env_get("board_rev")); + + sprintf(fdt_str, "freescale/imx8mq-librem5-devkit.dtb"); + env_set("fdtfile", fdt_str); + } + + if (is_usb_boot()) { + puts("USB Boot\n"); + env_set("bootcmd", "fastboot 0"); + } + + return 0; +} diff --git a/board/purism/librem5-devkit/librem5-devkit.env b/board/purism/librem5-devkit/librem5-devkit.env new file mode 100644 index 00000000000..2acec768c06 --- /dev/null +++ b/board/purism/librem5-devkit/librem5-devkit.env @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 dhcp +bootmeths=efi extlinux script +bootm_size=0x10000000 +console=ttymxc0,115200 +fdt_addr_r=0x43000000 +fdtfile=DEFAULT_FDT_FILE +initrd_addr=0x43800000 +image=Image +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +loadaddr=CONFIG_SYS_LOAD_ADDR +mmcautodetect=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk0p1 +scriptaddr=CONFIG_SYS_LOAD_ADDR +mmcargs=setenv bootargs console=${console} root=${mmcroot} rootwait rw +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} diff --git a/board/purism/librem5-devkit/lpddr4_timing.c b/board/purism/librem5-devkit/lpddr4_timing.c new file mode 100644 index 00000000000..17867319c55 --- /dev/null +++ b/board/purism/librem5-devkit/lpddr4_timing.c @@ -0,0 +1,931 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +#define WR_POST_EXT_3200 /* recommened to define */ + +struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP5(0), 0x07070707 }, + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + + /* Frequency 1: 400mbps */ + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, + { DDRC_FREQ1_INIT3(0), 0x00840000 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + + /* Frequency 2: 100mbps */ + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, + { DDRC_FREQ2_INIT3(0), 0x00840000 }, + { DDRC_FREQ2_INIT4(0), 0x00310008 }, + { DDRC_FREQ2_INIT6(0), 0x0066004a }, + { DDRC_FREQ2_INIT7(0), 0x0006004a }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, + { 0x20111, 0x03 }, + { 0x20112, 0x04 }, + { 0x20113, 0x05 }, + { 0x20114, 0x00 }, + { 0x20115, 0x01 }, + + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + +#ifdef WR_POST_EXT_3200 + { 0x20024, 0xeb }, +#else + { 0x20024, 0xab }, +#endif + { 0x2003a, 0x0 }, + { 0x120024, 0xab }, + { 0x2003a, 0x0 }, + { 0x220024, 0xab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x2200c7, 0x80 }, + { 0x200ca, 0x106 }, + { 0x1200ca, 0x106 }, + { 0x2200ca, 0x106 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */ + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, +/* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d /*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) /*0x084d*/ }, + /* MR16/MR14*/ + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 /*0x4d*/ }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) /*0x500*/ }, + /* MR1 */ + { 0x54038, 0xd400 }, +/* MR3/MR2 */ +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d /*0x312d*/ }, +#endif + /* MR11/MR4 */ + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + /* self:0x284d//MR13/MR12 */ + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) /*0x084d*/ }, + /* MR16/MR14 */ + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 /*0x4d*/ }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) /*0x500*/ }, + /* { 0x5403d, 0x500 } */ + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) /*0x500*/ }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + /* PHY Ron/Rtt */ + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) /*0x2828*/ }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_400 }, + { 0x54009, LPDDR4_HDT_CTL_400_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_400 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + /* MR4/MR3 */ + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) /*0x31*/ }, + /* MR12/MR11 */ + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) /*0x4d46*/ }, + /* self:0x4d28//MR14/MR13 */ + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) /*0x4d08*/ }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 /*0x5*/ }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) /*0x31*/ }, /* MR4/MR3 */ + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) /*0x4d46*/ }, /* MR12/MR11 */ + /* self:0x4d28//MR14/MR13 */ + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) /*0x4d08*/ }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, LPDDR4_TRAIN_SEQ_100 }, + { 0x54009, LPDDR4_HDT_CTL_100_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_100 << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x84 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x84 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x8400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0x8400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, +#ifdef WR_POST_EXT_3200 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, +#else + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, +#endif + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + + { 0x54032, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, +#ifdef WR_POST_EXT_3200 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, +#else + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, +#endif + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, { 0x90000, 0x10 }, { 0x90001, 0x400 }, + { 0x90002, 0x10e }, { 0x90003, 0x0 }, { 0x90004, 0x0 }, + { 0x90005, 0x8 }, { 0x90029, 0xb }, { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, { 0x9002c, 0x8 }, { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, { 0x9002f, 0x8 }, { 0x90030, 0x478 }, + { 0x90031, 0x109 }, { 0x90032, 0x0 }, { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, { 0x90035, 0x2 }, { 0x90036, 0x10 }, + { 0x90037, 0x139 }, { 0x90038, 0xf }, { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, { 0x9003b, 0x44 }, { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, { 0x9003e, 0x14f }, { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, { 0x90041, 0x47 }, { 0x90042, 0x630 }, + { 0x90043, 0x149 }, { 0x90044, 0x4f }, { 0x90045, 0x630 }, + { 0x90046, 0x179 }, { 0x90047, 0x8 }, { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, { 0x9004a, 0x0 }, { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, { 0x9004d, 0x0 }, { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, { 0x90050, 0x0 }, { 0x90051, 0x45a }, + { 0x90052, 0x9 }, { 0x90053, 0x0 }, { 0x90054, 0x448 }, + { 0x90055, 0x109 }, { 0x90056, 0x40 }, { 0x90057, 0x630 }, + { 0x90058, 0x179 }, { 0x90059, 0x1 }, { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, { 0x9005c, 0x40c0 }, { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, { 0x9005f, 0x8 }, { 0x90060, 0x4 }, + { 0x90061, 0x48 }, { 0x90062, 0x4040 }, { 0x90063, 0x630 }, + { 0x90064, 0x149 }, { 0x90065, 0x0 }, { 0x90066, 0x4 }, + { 0x90067, 0x48 }, { 0x90068, 0x40 }, { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, { 0x9006b, 0x10 }, { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, { 0x9006e, 0x0 }, { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, { 0x90071, 0x549 }, { 0x90072, 0x630 }, + { 0x90073, 0x159 }, { 0x90074, 0xd49 }, { 0x90075, 0x630 }, + { 0x90076, 0x159 }, { 0x90077, 0x94a }, { 0x90078, 0x630 }, + { 0x90079, 0x159 }, { 0x9007a, 0x441 }, { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, { 0x9007d, 0x42 }, { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, { 0x90080, 0x1 }, { 0x90081, 0x630 }, + { 0x90082, 0x149 }, { 0x90083, 0x0 }, { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, { 0x90086, 0xa }, { 0x90087, 0x10 }, + { 0x90088, 0x109 }, { 0x90089, 0x9 }, { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, { 0x9008c, 0x9 }, { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, { 0x9008f, 0x18 }, { 0x90090, 0x10 }, + { 0x90091, 0x109 }, { 0x90092, 0x0 }, { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, { 0x90095, 0x18 }, { 0x90096, 0x4 }, + { 0x90097, 0x48 }, { 0x90098, 0x18 }, { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, { 0x9009b, 0xa }, { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, { 0x9009e, 0x2 }, { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, { 0x900a1, 0x5 }, { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, { 0x900a4, 0x10 }, { 0x900a5, 0x10 }, + { 0x900a6, 0x109 }, { 0x40000, 0x811 }, { 0x40020, 0x880 }, + { 0x40040, 0x0 }, { 0x40060, 0x0 }, { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, { 0x40041, 0x4f }, { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, { 0x40022, 0x83 }, { 0x40042, 0x51 }, + { 0x40062, 0x0 }, { 0x40003, 0x811 }, { 0x40023, 0x880 }, + { 0x40043, 0x0 }, { 0x40063, 0x0 }, { 0x40004, 0x720 }, + { 0x40024, 0xf }, { 0x40044, 0x1740 }, { 0x40064, 0x0 }, + { 0x40005, 0x16 }, { 0x40025, 0x83 }, { 0x40045, 0x4b }, + { 0x40065, 0x0 }, { 0x40006, 0x716 }, { 0x40026, 0xf }, + { 0x40046, 0x2001 }, { 0x40066, 0x0 }, { 0x40007, 0x716 }, + { 0x40027, 0xf }, { 0x40047, 0x2800 }, { 0x40067, 0x0 }, + { 0x40008, 0x716 }, { 0x40028, 0xf }, { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, { 0x40009, 0x720 }, { 0x40029, 0xf }, + { 0x40049, 0x1400 }, { 0x40069, 0x0 }, { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, { 0x4004a, 0x0 }, { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, { 0x4002b, 0x15 }, { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, { 0x4000c, 0x4028 }, { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, { 0x4006c, 0x0 }, { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, { 0x4004d, 0x0 }, { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, { 0x4002e, 0x1a }, { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, { 0x4000f, 0x4040 }, { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, { 0x4006f, 0x0 }, { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, { 0x40050, 0x0 }, { 0x40070, 0x0 }, + { 0x40011, 0x708 }, { 0x40031, 0x5 }, { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, { 0x40012, 0x8 }, { 0x40032, 0x80 }, + { 0x40052, 0x0 }, { 0x40072, 0x0 }, { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, { 0x40053, 0x0 }, { 0x40073, 0x0 }, + { 0x40014, 0x708 }, { 0x40034, 0xa }, { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, { 0x40015, 0x4040 }, { 0x40035, 0x80 }, + { 0x40055, 0x0 }, { 0x40075, 0x0 }, { 0x40016, 0x60a }, + { 0x40036, 0x15 }, { 0x40056, 0x1200 }, { 0x40076, 0x0 }, + { 0x40017, 0x61a }, { 0x40037, 0x15 }, { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, { 0x40018, 0x60a }, { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, { 0x40078, 0x0 }, { 0x40019, 0x642 }, + { 0x40039, 0x1a }, { 0x40059, 0x1300 }, { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, { 0x4003a, 0x880 }, { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, { 0x900a7, 0x0 }, { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, { 0x900aa, 0x8 }, { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, { 0x900ad, 0x10 }, { 0x900ae, 0x7b2 }, + { 0x900af, 0x2a }, { 0x900b0, 0x0 }, { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, { 0x900b3, 0x10 }, { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, { 0x900b6, 0x8 }, { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, { 0x900b9, 0xa }, { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, { 0x900bc, 0xc }, { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, { 0x900bf, 0x14 }, { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, { 0x900c2, 0x8 }, { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, { 0x900c5, 0xe }, { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, { 0x900c8, 0x8 }, { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, { 0x900cb, 0x18 }, { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, { 0x900ce, 0x8 }, { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, { 0x900d1, 0x10 }, { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, { 0x900d4, 0x70 }, { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, { 0x900d7, 0x1ff8 }, { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, { 0x900da, 0x50 }, { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, { 0x900dd, 0x60 }, { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, { 0x900e0, 0x8 }, { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, { 0x900e3, 0x8 }, { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, { 0x900e6, 0xa }, { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, { 0x900e9, 0x6e }, { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, { 0x900ec, 0x0 }, { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, { 0x900ef, 0x0 }, { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, { 0x900f2, 0x0 }, { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, { 0x900f5, 0x1ff8 }, { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, { 0x900f8, 0x68 }, { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, { 0x900fb, 0x78 }, { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, { 0x900fe, 0x68 }, { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, { 0x90101, 0x8 }, { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, { 0x90104, 0x8 }, { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, { 0x90107, 0xa }, { 0x90108, 0x408 }, + { 0x90109, 0x169 }, { 0x9010a, 0x58 }, { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, { 0x9010d, 0x0 }, { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, { 0x90110, 0x0 }, { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, { 0x90113, 0x0 }, { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, { 0x90116, 0x0 }, { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, { 0x90119, 0x80 }, { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, { 0x9011c, 0x18 }, { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, { 0x9011f, 0xa }, { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, { 0x90122, 0x8 }, { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, { 0x90125, 0xf }, { 0x90126, 0x408 }, + { 0x90127, 0x169 }, { 0x90128, 0xc }, { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, { 0x9012b, 0x9 }, { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, { 0x9012e, 0x0 }, { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, { 0x90131, 0x0 }, { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, { 0x90134, 0x8 }, { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, { 0x90137, 0x0 }, { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, { 0x9013a, 0xb7 }, { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, { 0x9013d, 0x1f }, { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, { 0x90140, 0x8 }, { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, { 0x90143, 0xf }, { 0x90144, 0x408 }, + { 0x90145, 0x169 }, { 0x90146, 0xc }, { 0x90147, 0x0 }, + { 0x90148, 0x68 }, { 0x90149, 0x0 }, { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, { 0x9014c, 0x0 }, { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, { 0x9014f, 0x8 }, { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, { 0x90152, 0x3 }, { 0x90153, 0x370 }, + { 0x90154, 0x129 }, { 0x90155, 0x20 }, { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, { 0x90158, 0x0 }, { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, { 0x9015b, 0x8 }, { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, { 0x9015e, 0x0 }, { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, { 0x90161, 0x10 }, { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, { 0x90164, 0x8 }, { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, { 0x90167, 0x8 }, { 0x90168, 0x0 }, + { 0x90169, 0x8 }, { 0x9016a, 0x8 }, { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, { 0x9016d, 0xf }, { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, { 0x90170, 0x0 }, { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, { 0x90173, 0x47 }, { 0x90174, 0x630 }, + { 0x90175, 0x109 }, { 0x90176, 0x8 }, { 0x90177, 0x618 }, + { 0x90178, 0x109 }, { 0x90179, 0x8 }, { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, { 0x9017c, 0x0 }, { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, { 0x9017f, 0x8 }, { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, { 0x90182, 0x0 }, { 0x90183, 0x1 }, + { 0x90184, 0x8 }, { 0x90185, 0x8 }, { 0x90186, 0x4 }, + { 0x90187, 0x8 }, { 0x90188, 0x8 }, { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, { 0x90006, 0x0 }, { 0x90007, 0x0 }, + { 0x90008, 0x8 }, { 0x90009, 0x0 }, { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, { 0x90026, 0x6a }, { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, { 0x400d5, 0x202 }, { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, { 0x2000d, 0x7d0 }, { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, { 0x22000b, 0x3 }, { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, { 0x9000e, 0x60 }, { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, { 0x90011, 0xdfbd }, { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, { 0x40084, 0xe0 }, { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, { 0x140081, 0x12 }, { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, { 0x140084, 0xe0 }, { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, { 0x240081, 0x12 }, { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, { 0x240084, 0xe0 }, { 0x240085, 0x12 }, + { 0x400fd, 0xf }, { 0x10011, 0x1 }, { 0x10012, 0x1 }, + { 0x10013, 0x180 }, { 0x10018, 0x1 }, { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, { 0x101b4, 0x1 }, { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, { 0x104b4, 0x1 }, { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, { 0x107b4, 0x1 }, { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, { 0x11012, 0x1 }, { 0x11013, 0x180 }, + { 0x11018, 0x1 }, { 0x11002, 0x6209 }, { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, { 0x112b4, 0x1 }, { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, { 0x115b4, 0x1 }, { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, { 0x118b4, 0x1 }, { 0x12011, 0x1 }, + { 0x12012, 0x1 }, { 0x12013, 0x180 }, { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, { 0x120b2, 0x1 }, { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, { 0x123b4, 0x1 }, { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, { 0x126b4, 0x1 }, { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, { 0x13011, 0x1 }, { 0x13012, 0x1 }, + { 0x13013, 0x180 }, { 0x13018, 0x1 }, { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, { 0x131b4, 0x1 }, { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, { 0x134b4, 0x1 }, { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, { 0x137b4, 0x1 }, { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, { 0xc0080, 0x2 }, { 0xd0000, 0x1 }, +}; + +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P1 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/purism/librem5-devkit/lpddr4_timing_b0.c b/board/purism/librem5-devkit/lpddr4_timing_b0.c new file mode 100644 index 00000000000..89ab6e082e8 --- /dev/null +++ b/board/purism/librem5-devkit/lpddr4_timing_b0.c @@ -0,0 +1,794 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +#define WR_POST_EXT_3200 /* recommened to define */ + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + /* dis_dq=1, indicates no reads or writes are issued to SDRAM */ + { DDRC_DBG1(0), 0x00000001 }, + /* selfref_en=1, SDRAM enter self-refresh state */ + { DDRC_PWRCTL(0), 0x00000001 }, + { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_MSTR2(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x006100E0 }, + { DDRC_INIT0(0), 0xC003061B }, + { DDRC_INIT1(0), 0x009D0000 }, + { DDRC_INIT3(0), 0x00D4002D }, +#ifdef WR_POST_EXT_3200 /* recommened to define */ + { DDRC_INIT4(0), 0x00330008 }, +#else + { DDRC_INIT4(0), 0x00310008 }, +#endif + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0006004a }, + + { DDRC_DRAMTMG0(0), 0x1A201B22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00C0C000 }, + { DDRC_DRAMTMG4(0), 0x0F04080F }, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, + { DDRC_DRAMTMG14(0), 0x000000E6 }, + { DDRC_DRAMTMG17(0), 0x00A00050 }, + + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xE0400018 }, + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, + { DDRC_DFITMG2(0), 0x0000170A }, + + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000001 }, + + /* need be refined by ddrphy trained value */ + { DDRC_RANKCTL(0), 0x00000c99 }, + { DDRC_DRAMTMG2(0), 0x070E171a }, + + /* address mapping */ + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ + { DDRC_ADDRMAP0(0), 0x00000015 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */ + { DDRC_ADDRMAP4(0), 0x00001F1F }, + /* bank interleave */ + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */ + { DDRC_ADDRMAP5(0), 0x07070707 }, + /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */ + { DDRC_ADDRMAP6(0), 0x08080707 }, + + /* 667mts frequency setting */ + { DDRC_FREQ1_DERATEEN(0), 0x0000000 }, + { DDRC_FREQ1_DERATEINT(0), 0x0800000 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 }, + { DDRC_FREQ1_RFSHTMG(0), 0x014001E }, + { DDRC_FREQ1_INIT3(0), 0x0140009 }, + { DDRC_FREQ1_INIT4(0), 0x00310008 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0006004a }, + { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x003040A }, + { DDRC_FREQ1_DRAMTMG2(0), 0x305080C }, + { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 }, + { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 }, + { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 }, + { DDRC_FREQ1_DFITMG0(0), 0x3858202 }, + { DDRC_FREQ1_DFITMG1(0), 0x0000404 }, + { DDRC_FREQ1_DFITMG2(0), 0x0000502 }, + + /* performance setting */ + { DDRC_ODTCFG(0), 0x0b060908 }, + { DDRC_ODTMAP(0), 0x00000000 }, + { DDRC_SCHED(0), 0x29511505 }, + { DDRC_SCHED1(0), 0x0000002c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + /* 150T starve and 0x90 max tran len */ + { DDRC_PERFLPR1(0), 0x90000096 }, + /* 300T starve and 0x10 max tran len */ + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x00000016 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000011 }, + { DDRC_PCCFG(0), 0x00000111 }, + { DDRC_PCFGR_0(0), 0x000010f3 }, + { DDRC_PCFGW_0(0), 0x000072ff }, + { DDRC_PCTRL_0(0), 0x00000001 }, + /* disable Read Qos*/ + { DDRC_PCFGQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + /* disable Write Qos*/ + { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, + { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, + { DDRC_FREQ1_DERATEEN(0), 0x00000202 }, + { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 }, + { DDRC_FREQ1_RFSHTMG(0), 0x00610090 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x20110, 0x02 }, /* MapCAB0toDFI */ + { 0x20111, 0x03 }, /* MapCAB1toDFI */ + { 0x20112, 0x04 }, /* MapCAB2toDFI */ + { 0x20113, 0x05 }, /* MapCAB3toDFI */ + { 0x20114, 0x00 }, /* MapCAB4toDFI */ + { 0x20115, 0x01 }, /* MapCAB5toDFI */ + + /* Initialize PHY Configuration */ + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + + { 0x20024, 0xe3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0xa3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0xa3 }, + { 0x2003a, 0x2 }, + + { 0x20056, 0x3 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + + { 0x10049, 0xfbe }, + { 0x10149, 0xfbe }, + { 0x11049, 0xfbe }, + { 0x11149, 0xfbe }, + { 0x12049, 0xfbe }, + { 0x12149, 0xfbe }, + { 0x13049, 0xfbe }, + { 0x13149, 0xfbe }, + + { 0x110049, 0xfbe }, + { 0x110149, 0xfbe }, + { 0x111049, 0xfbe }, + { 0x111149, 0xfbe }, + { 0x112049, 0xfbe }, + { 0x112149, 0xfbe }, + { 0x113049, 0xfbe }, + { 0x113149, 0xfbe }, + + { 0x210049, 0xfbe }, + { 0x210149, 0xfbe }, + { 0x211049, 0xfbe }, + { 0x211149, 0xfbe }, + { 0x212049, 0xfbe }, + { 0x212149, 0xfbe }, + { 0x213049, 0xfbe }, + { 0x213149, 0xfbe }, + + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0xa7 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x600 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5655 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x29c }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54019, 0x914 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401e, 0x6 }, + { 0x5401f, 0x914 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0x1400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, 0x600 }, + { 0x54038, 0x1400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54007, 0x0 }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_2D }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x2 }, + { 0x5400c, 0x0 }, + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, + { 0x5400e, 0x0 }, + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, + { 0x54010, LPDDR4_2D_WEIGHT }, + { 0x54011, 0x0 }, + { 0x54012, 0x310 }, + { 0x54013, 0x0 }, + { 0x54014, 0x0 }, + { 0x54015, 0x0 }, + { 0x54016, 0x0 }, + { 0x54017, 0x0 }, + { 0x54018, 0x0 }, + { 0x54024, 0x5 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | + LPDDR4_RTT_DQ) }, + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, + { 0x5401d, 0x0 }, + { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | + LPDDR4_RTT_DQ) }, + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, + { 0x54023, 0x0 }, + { 0x54024, LPDDR4_MR22_RANK1 }, + { 0x54025, 0x0 }, + { 0x54026, 0x0 }, + { 0x54027, 0x0 }, + { 0x54028, 0x0 }, + { 0x54029, 0x0 }, + { 0x5402a, 0x0 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x5402d, 0x0 }, + { 0x5402e, 0x0 }, + { 0x5402f, 0x0 }, + { 0x54030, 0x0 }, + { 0x54031, 0x0 }, + { 0x54032, 0xd400 }, + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, + { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54038, 0xd400 }, + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x0 }, + { 0x54040, 0x0 }, + { 0x54041, 0x0 }, + { 0x54042, 0x0 }, + { 0x54043, 0x0 }, + { 0x54044, 0x0 }, + { 0xd0000, 0x1 }, + +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0x0 }, { 0x90000, 0x10 }, { 0x90001, 0x400 }, + { 0x90002, 0x10e }, { 0x90003, 0x0 }, { 0x90004, 0x0 }, + { 0x90005, 0x8 }, { 0x90029, 0xb }, { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, { 0x9002c, 0x8 }, { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, { 0x9002f, 0x8 }, { 0x90030, 0x478 }, + { 0x90031, 0x109 }, { 0x90032, 0x0 }, { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, { 0x90035, 0x2 }, { 0x90036, 0x10 }, + { 0x90037, 0x139 }, { 0x90038, 0xb }, { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, { 0x9003b, 0x44 }, { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, { 0x9003e, 0x14f }, { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, { 0x90041, 0x47 }, { 0x90042, 0x630 }, + { 0x90043, 0x149 }, { 0x90044, 0x4f }, { 0x90045, 0x630 }, + { 0x90046, 0x179 }, { 0x90047, 0x8 }, { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, { 0x9004a, 0x0 }, { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, { 0x9004d, 0x0 }, { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, { 0x90050, 0x0 }, { 0x90051, 0x45a }, + { 0x90052, 0x9 }, { 0x90053, 0x0 }, { 0x90054, 0x448 }, + { 0x90055, 0x109 }, { 0x90056, 0x40 }, { 0x90057, 0x630 }, + { 0x90058, 0x179 }, { 0x90059, 0x1 }, { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, { 0x9005c, 0x40c0 }, { 0x9005d, 0x630 }, + { 0x9005e, 0x149 }, { 0x9005f, 0x8 }, { 0x90060, 0x4 }, + { 0x90061, 0x48 }, { 0x90062, 0x4040 }, { 0x90063, 0x630 }, + { 0x90064, 0x149 }, { 0x90065, 0x0 }, { 0x90066, 0x4 }, + { 0x90067, 0x48 }, { 0x90068, 0x40 }, { 0x90069, 0x630 }, + { 0x9006a, 0x149 }, { 0x9006b, 0x10 }, { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, { 0x9006e, 0x0 }, { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, { 0x90071, 0x549 }, { 0x90072, 0x630 }, + { 0x90073, 0x159 }, { 0x90074, 0xd49 }, { 0x90075, 0x630 }, + { 0x90076, 0x159 }, { 0x90077, 0x94a }, { 0x90078, 0x630 }, + { 0x90079, 0x159 }, { 0x9007a, 0x441 }, { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, { 0x9007d, 0x42 }, { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, { 0x90080, 0x1 }, { 0x90081, 0x630 }, + { 0x90082, 0x149 }, { 0x90083, 0x0 }, { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, { 0x90086, 0xa }, { 0x90087, 0x10 }, + { 0x90088, 0x109 }, { 0x90089, 0x9 }, { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, { 0x9008c, 0x9 }, { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, { 0x9008f, 0x18 }, { 0x90090, 0x10 }, + { 0x90091, 0x109 }, { 0x90092, 0x0 }, { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, { 0x90095, 0x18 }, { 0x90096, 0x4 }, + { 0x90097, 0x48 }, { 0x90098, 0x18 }, { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, { 0x9009b, 0xa }, { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, { 0x9009e, 0x2 }, { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, { 0x900a1, 0x5 }, { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, { 0x900a4, 0xd }, { 0x900a5, 0x7c0 }, + { 0x900a6, 0x109 }, { 0x900a7, 0x4 }, { 0x900a8, 0x7c0 }, + { 0x900a9, 0x109 }, { 0x40000, 0x811 }, { 0x40020, 0x880 }, + { 0x40040, 0x0 }, { 0x40060, 0x0 }, { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, { 0x40041, 0x4f }, { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, { 0x40022, 0x83 }, { 0x40042, 0x51 }, + { 0x40062, 0x0 }, { 0x40003, 0x811 }, { 0x40023, 0x880 }, + { 0x40043, 0x0 }, { 0x40063, 0x0 }, { 0x40004, 0x720 }, + { 0x40024, 0xf }, { 0x40044, 0x1740 }, { 0x40064, 0x0 }, + { 0x40005, 0x16 }, { 0x40025, 0x83 }, { 0x40045, 0x4b }, + { 0x40065, 0x0 }, { 0x40006, 0x716 }, { 0x40026, 0xf }, + { 0x40046, 0x2001 }, { 0x40066, 0x0 }, { 0x40007, 0x716 }, + { 0x40027, 0xf }, { 0x40047, 0x2800 }, { 0x40067, 0x0 }, + { 0x40008, 0x716 }, { 0x40028, 0xf }, { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, { 0x40009, 0x720 }, { 0x40029, 0xf }, + { 0x40049, 0x1400 }, { 0x40069, 0x0 }, { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, { 0x4004a, 0x0 }, { 0x4006a, 0x0 }, + { 0x4000b, 0x623 }, { 0x4002b, 0x15 }, { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, { 0x4000c, 0x4028 }, { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, { 0x4006c, 0x0 }, { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, { 0x4004d, 0x0 }, { 0x4006d, 0x0 }, + { 0x4000e, 0x623 }, { 0x4002e, 0x1a }, { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, { 0x4000f, 0x4040 }, { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, { 0x4006f, 0x0 }, { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, { 0x40050, 0x0 }, { 0x40070, 0x0 }, + { 0x40011, 0x708 }, { 0x40031, 0x5 }, { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, { 0x40012, 0x8 }, { 0x40032, 0x80 }, + { 0x40052, 0x0 }, { 0x40072, 0x0 }, { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, { 0x40053, 0x0 }, { 0x40073, 0x0 }, + { 0x40014, 0x708 }, { 0x40034, 0xa }, { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, { 0x40015, 0x4040 }, { 0x40035, 0x80 }, + { 0x40055, 0x0 }, { 0x40075, 0x0 }, { 0x40016, 0x60a }, + { 0x40036, 0x15 }, { 0x40056, 0x1200 }, { 0x40076, 0x0 }, + { 0x40017, 0x61a }, { 0x40037, 0x15 }, { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, { 0x40018, 0x60a }, { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, { 0x40078, 0x0 }, { 0x40019, 0x642 }, + { 0x40039, 0x1a }, { 0x40059, 0x1300 }, { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, { 0x4003a, 0x880 }, { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, { 0x900aa, 0x0 }, { 0x900ab, 0x790 }, + { 0x900ac, 0x11a }, { 0x900ad, 0x8 }, { 0x900ae, 0x7aa }, + { 0x900af, 0x2a }, { 0x900b0, 0x10 }, { 0x900b1, 0x7b2 }, + { 0x900b2, 0x2a }, { 0x900b3, 0x0 }, { 0x900b4, 0x7c8 }, + { 0x900b5, 0x109 }, { 0x900b6, 0x10 }, { 0x900b7, 0x10 }, + { 0x900b8, 0x109 }, { 0x900b9, 0x10 }, { 0x900ba, 0x2a8 }, + { 0x900bb, 0x129 }, { 0x900bc, 0x8 }, { 0x900bd, 0x370 }, + { 0x900be, 0x129 }, { 0x900bf, 0xa }, { 0x900c0, 0x3c8 }, + { 0x900c1, 0x1a9 }, { 0x900c2, 0xc }, { 0x900c3, 0x408 }, + { 0x900c4, 0x199 }, { 0x900c5, 0x14 }, { 0x900c6, 0x790 }, + { 0x900c7, 0x11a }, { 0x900c8, 0x8 }, { 0x900c9, 0x4 }, + { 0x900ca, 0x18 }, { 0x900cb, 0xe }, { 0x900cc, 0x408 }, + { 0x900cd, 0x199 }, { 0x900ce, 0x8 }, { 0x900cf, 0x8568 }, + { 0x900d0, 0x108 }, { 0x900d1, 0x18 }, { 0x900d2, 0x790 }, + { 0x900d3, 0x16a }, { 0x900d4, 0x8 }, { 0x900d5, 0x1d8 }, + { 0x900d6, 0x169 }, { 0x900d7, 0x10 }, { 0x900d8, 0x8558 }, + { 0x900d9, 0x168 }, { 0x900da, 0x70 }, { 0x900db, 0x788 }, + { 0x900dc, 0x16a }, { 0x900dd, 0x1ff8 }, { 0x900de, 0x85a8 }, + { 0x900df, 0x1e8 }, { 0x900e0, 0x50 }, { 0x900e1, 0x798 }, + { 0x900e2, 0x16a }, { 0x900e3, 0x60 }, { 0x900e4, 0x7a0 }, + { 0x900e5, 0x16a }, { 0x900e6, 0x8 }, { 0x900e7, 0x8310 }, + { 0x900e8, 0x168 }, { 0x900e9, 0x8 }, { 0x900ea, 0xa310 }, + { 0x900eb, 0x168 }, { 0x900ec, 0xa }, { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, { 0x900ef, 0x6e }, { 0x900f0, 0x0 }, + { 0x900f1, 0x68 }, { 0x900f2, 0x0 }, { 0x900f3, 0x408 }, + { 0x900f4, 0x169 }, { 0x900f5, 0x0 }, { 0x900f6, 0x8310 }, + { 0x900f7, 0x168 }, { 0x900f8, 0x0 }, { 0x900f9, 0xa310 }, + { 0x900fa, 0x168 }, { 0x900fb, 0x1ff8 }, { 0x900fc, 0x85a8 }, + { 0x900fd, 0x1e8 }, { 0x900fe, 0x68 }, { 0x900ff, 0x798 }, + { 0x90100, 0x16a }, { 0x90101, 0x78 }, { 0x90102, 0x7a0 }, + { 0x90103, 0x16a }, { 0x90104, 0x68 }, { 0x90105, 0x790 }, + { 0x90106, 0x16a }, { 0x90107, 0x8 }, { 0x90108, 0x8b10 }, + { 0x90109, 0x168 }, { 0x9010a, 0x8 }, { 0x9010b, 0xab10 }, + { 0x9010c, 0x168 }, { 0x9010d, 0xa }, { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, { 0x90110, 0x58 }, { 0x90111, 0x0 }, + { 0x90112, 0x68 }, { 0x90113, 0x0 }, { 0x90114, 0x408 }, + { 0x90115, 0x169 }, { 0x90116, 0x0 }, { 0x90117, 0x8b10 }, + { 0x90118, 0x168 }, { 0x90119, 0x0 }, { 0x9011a, 0xab10 }, + { 0x9011b, 0x168 }, { 0x9011c, 0x0 }, { 0x9011d, 0x1d8 }, + { 0x9011e, 0x169 }, { 0x9011f, 0x80 }, { 0x90120, 0x790 }, + { 0x90121, 0x16a }, { 0x90122, 0x18 }, { 0x90123, 0x7aa }, + { 0x90124, 0x6a }, { 0x90125, 0xa }, { 0x90126, 0x0 }, + { 0x90127, 0x1e9 }, { 0x90128, 0x8 }, { 0x90129, 0x8080 }, + { 0x9012a, 0x108 }, { 0x9012b, 0xf }, { 0x9012c, 0x408 }, + { 0x9012d, 0x169 }, { 0x9012e, 0xc }, { 0x9012f, 0x0 }, + { 0x90130, 0x68 }, { 0x90131, 0x9 }, { 0x90132, 0x0 }, + { 0x90133, 0x1a9 }, { 0x90134, 0x0 }, { 0x90135, 0x408 }, + { 0x90136, 0x169 }, { 0x90137, 0x0 }, { 0x90138, 0x8080 }, + { 0x90139, 0x108 }, { 0x9013a, 0x8 }, { 0x9013b, 0x7aa }, + { 0x9013c, 0x6a }, { 0x9013d, 0x0 }, { 0x9013e, 0x8568 }, + { 0x9013f, 0x108 }, { 0x90140, 0xb7 }, { 0x90141, 0x790 }, + { 0x90142, 0x16a }, { 0x90143, 0x1f }, { 0x90144, 0x0 }, + { 0x90145, 0x68 }, { 0x90146, 0x8 }, { 0x90147, 0x8558 }, + { 0x90148, 0x168 }, { 0x90149, 0xf }, { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, { 0x9014c, 0xc }, { 0x9014d, 0x0 }, + { 0x9014e, 0x68 }, { 0x9014f, 0x0 }, { 0x90150, 0x408 }, + { 0x90151, 0x169 }, { 0x90152, 0x0 }, { 0x90153, 0x8558 }, + { 0x90154, 0x168 }, { 0x90155, 0x8 }, { 0x90156, 0x3c8 }, + { 0x90157, 0x1a9 }, { 0x90158, 0x3 }, { 0x90159, 0x370 }, + { 0x9015a, 0x129 }, { 0x9015b, 0x20 }, { 0x9015c, 0x2aa }, + { 0x9015d, 0x9 }, { 0x9015e, 0x0 }, { 0x9015f, 0x400 }, + { 0x90160, 0x10e }, { 0x90161, 0x8 }, { 0x90162, 0xe8 }, + { 0x90163, 0x109 }, { 0x90164, 0x0 }, { 0x90165, 0x8140 }, + { 0x90166, 0x10c }, { 0x90167, 0x10 }, { 0x90168, 0x8138 }, + { 0x90169, 0x10c }, { 0x9016a, 0x8 }, { 0x9016b, 0x7c8 }, + { 0x9016c, 0x101 }, { 0x9016d, 0x8 }, { 0x9016e, 0x0 }, + { 0x9016f, 0x8 }, { 0x90170, 0x8 }, { 0x90171, 0x448 }, + { 0x90172, 0x109 }, { 0x90173, 0xf }, { 0x90174, 0x7c0 }, + { 0x90175, 0x109 }, { 0x90176, 0x0 }, { 0x90177, 0xe8 }, + { 0x90178, 0x109 }, { 0x90179, 0x47 }, { 0x9017a, 0x630 }, + { 0x9017b, 0x109 }, { 0x9017c, 0x8 }, { 0x9017d, 0x618 }, + { 0x9017e, 0x109 }, { 0x9017f, 0x8 }, { 0x90180, 0xe0 }, + { 0x90181, 0x109 }, { 0x90182, 0x0 }, { 0x90183, 0x7c8 }, + { 0x90184, 0x109 }, { 0x90185, 0x8 }, { 0x90186, 0x8140 }, + { 0x90187, 0x10c }, { 0x90188, 0x0 }, { 0x90189, 0x1 }, + { 0x9018a, 0x8 }, { 0x9018b, 0x8 }, { 0x9018c, 0x4 }, + { 0x9018d, 0x8 }, { 0x9018e, 0x8 }, { 0x9018f, 0x7c8 }, + { 0x90190, 0x101 }, { 0x90006, 0x0 }, { 0x90007, 0x0 }, + { 0x90008, 0x8 }, { 0x90009, 0x0 }, { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, + { 0x9001f, 0x2b }, { 0x90026, 0x6c }, { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, { 0x400d5, 0x202 }, { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, { 0x2000d, 0x7d0 }, { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, { 0x12000c, 0x29 }, { 0x12000d, 0x1a1 }, + { 0x12000e, 0x10 }, { 0x22000b, 0x3 }, { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, { 0x9000e, 0x60 }, { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, { 0x90011, 0xdfbd }, { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, { 0x40084, 0xe0 }, { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, { 0x140081, 0x12 }, { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, { 0x140084, 0xe0 }, { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, { 0x240081, 0x12 }, { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, { 0x240084, 0xe0 }, { 0x240085, 0x12 }, + { 0x400fd, 0xf }, { 0x10011, 0x1 }, { 0x10012, 0x1 }, + { 0x10013, 0x180 }, { 0x10018, 0x1 }, { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, { 0x101b4, 0x1 }, { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, { 0x104b4, 0x1 }, { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, { 0x107b4, 0x1 }, { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, { 0x11012, 0x1 }, { 0x11013, 0x180 }, + { 0x11018, 0x1 }, { 0x11002, 0x6209 }, { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, { 0x112b4, 0x1 }, { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, { 0x115b4, 0x1 }, { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, { 0x118b4, 0x1 }, { 0x12011, 0x1 }, + { 0x12012, 0x1 }, { 0x12013, 0x180 }, { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, { 0x120b2, 0x1 }, { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, { 0x123b4, 0x1 }, { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, { 0x126b4, 0x1 }, { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, { 0x13011, 0x1 }, { 0x13012, 0x1 }, + { 0x13013, 0x180 }, { 0x13018, 0x1 }, { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, { 0x131b4, 0x1 }, { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, { 0x134b4, 0x1 }, { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, { 0x137b4, 0x1 }, { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, { 0x20088, 0x19 }, { 0xc0080, 0x2 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* lpddr4 timing config params on EVK board */ +struct dram_timing_info dram_timing_b0 = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + /* + * this table must be initialized if DDRPHY bypass mode is + * not used: all fsp drate > 666MTS. + */ + .fsp_table = { 3200, 667, }, +}; diff --git a/board/purism/librem5-devkit/spl.c b/board/purism/librem5-devkit/spl.c new file mode 100644 index 00000000000..26e01ed6ba4 --- /dev/null +++ b/board/purism/librem5-devkit/spl.c @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * 2021 Purism + * 2026 Phosh.mobi e.V. + * + * Author: Guido Günther <[email protected]> + */ + +#include <config.h> +#include <asm/io.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <power/pmic.h> +#include <power/bd71837.h> +#include <hang.h> +#include <init.h> +#include <spl.h> +#include <usb.h> +#include <dwc3-uboot.h> +#include <linux/delay.h> +#include <linux/usb/gadget.h> +#include <i2c.h> + +extern struct dram_timing_info dram_timing_b0; + +void spl_dram_init(void) +{ + /* ddr init, the default SOM uses B0 */ + if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) + ddr_init(&dram_timing); + else + ddr_init(&dram_timing_b0); +} + +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = 1; + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL \ + (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_FSEL1) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static const iomux_v3_cfg_t usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static const iomux_v3_cfg_t usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | + MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | + MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | + MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | + MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | + MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | + MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + { USDHC1_BASE_ADDR, 0, 8 }, + { USDHC2_BASE_ADDR, 0, 4 }, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { + log_debug("Initializing FSL USDHC port %d\n", i); + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + log_err("Warning: USDHC controller(%d) not supported\n", + i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#define LDO_VOLT_EN BIT(6) + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define I2C_PMIC 0 +#define POWER_BD71837_I2C_BUS 0 +#define POWER_BD71837_I2C_ADDR 0x4B + +int power_bd71837_init(unsigned char bus) +{ + static const char name[] = BD718XX_REGULATOR_DRIVER; + struct pmic *p = pmic_alloc(); + + if (!p) { + log_err("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = I2C_PMIC; + p->number_of_regs = BD718XX_MAX_REGISTER; + p->hw.i2c.addr = POWER_BD71837_I2C_ADDR; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} + +#define PWR_EN IMX_GPIO_NR(1, 8) +#define HAPTIC_nEN IMX_GPIO_NR(5, 4) +#define IMU_INT IMX_GPIO_NR(3, 19) +#define TS_INT IMX_GPIO_NR(3, 0) +static const iomux_v3_cfg_t pwr_en_pads[] = { + IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | + MUX_PAD_CTRL(PAD_CTL_DSE6 | PAD_CTL_FSEL0), + IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | + MUX_PAD_CTRL(PAD_CTL_DSE6 | PAD_CTL_FSEL1), + IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(PAD_CTL_ODE), + IMX8MQ_PAD_NAND_ALE__GPIO3_IO0 | MUX_PAD_CTRL(PAD_CTL_ODE), +}; + +int power_init_board(void) +{ + struct pmic *p; + int ldo[] = { BD718XX_LDO5_VOLT, BD718XX_LDO6_VOLT, BD71837_LDO7_VOLT }; + u32 val; + int i, rv; + + /* Set the i2c bus */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + /* + * Init PMIC + */ + rv = power_bd71837_init(POWER_BD71837_I2C_BUS); + if (rv) { + log_err("%s: power_bd71837_init(%d) error %d\n", __func__, + POWER_BD71837_I2C_BUS, rv); + goto out; + } + + p = pmic_get(BD718XX_REGULATOR_DRIVER); + if (!p) { + log_err("%s: pmic_get(%s) failed\n", __func__, + BD718XX_REGULATOR_DRIVER); + rv = -ENODEV; + goto out; + } + + rv = pmic_probe(p); + if (rv) { + log_err("%s: pmic_probe() error %d\n", __func__, rv); + goto out; + } + + /* + * Unlock all regs + */ + pmic_reg_write(p, BD718XX_REGLOCK, 0); + + /* find the reset cause */ + pmic_reg_read(p, 0x29, &val); + log_debug("%s: reset cause %d\n", __func__, val); + + /* + * Reconfigure default voltages and disable: + * - BUCK3: VDD_GPU_0V9 (1.00 -> 0.90) + * - BUCK4: VDD_VPU_0V9 (1.00 -> 0.90) + */ + pmic_reg_write(p, BD71837_BUCK3_VOLT_RUN, 0x14); + pmic_reg_write(p, BD71837_BUCK4_VOLT_RUN, 0x14); + + /* + * Enable PHYs voltages: LDO5-7 + */ + for (i = 0; i < ARRAY_SIZE(ldo); i++) { + rv = pmic_reg_read(p, ldo[i], &val); + if (rv) { + log_err("%s: pmic_read(%x) error %d\n", __func__, + ldo[i], rv); + continue; + } + + pmic_reg_write(p, ldo[i], val | LDO_VOLT_EN); + } + + imx_iomux_v3_setup_multiple_pads(pwr_en_pads, ARRAY_SIZE(pwr_en_pads)); + + /* set IMU_INT as input */ + gpio_request(IMU_INT, "imu_int"); + gpio_direction_input(IMU_INT); + + /* set TS_INT as input */ + gpio_request(TS_INT, "ts_int"); + gpio_direction_output(TS_INT, 0); + + /* disable the haptic motor */ + gpio_request(HAPTIC_nEN, "haptic_en"); + gpio_direction_output(HAPTIC_nEN, 1); + + gpio_request(PWR_EN, "pwr_en"); + gpio_direction_output(PWR_EN, 1); + + udelay(500); + + rv = 0; +out: + return 0; +} + +void spl_board_init(void) +{ +} + +/* + * set some safe defaults for the battery charger + */ +int init_charger_bq25896(void) +{ + int ret; + u8 val; + + ret = i2c_set_bus_num(0); + if (ret < 0) + log_err("Failed to set i2c bus 0: %d", ret); + + /* limit the charge current to 1.6A */ + i2c_reg_write(0x6b, 0x12, 0x20); + + /* set the max voltage to 4.192V */ + val = i2c_reg_read(0x6b, 0x6); + val = (val & 0xFC) | 0x16 << 2; + i2c_reg_write(0x6b, 0x6, val); + + return 0; +} + +#define SPEAKER_PAD_MUTE_CTRL PAD_CTL_HYS | PAD_CTL_DSE1 +#define SPEAKER_MUTE_GPIO IMX_GPIO_NR(5, 3) +static const iomux_v3_cfg_t speaker_pad = IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | + MUX_PAD_CTRL(SPEAKER_PAD_MUTE_CTRL); + +static void mute_speaker(void) +{ + imx_iomux_v3_setup_pad(speaker_pad); + gpio_request(SPEAKER_MUTE_GPIO, "speaker_mute"); + gpio_direction_output(SPEAKER_MUTE_GPIO, 0); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + init_uart_clk(0); + + board_early_init_f(); + + timer_init(); + + ret = spl_early_init(); + if (ret) { + log_err("spl_early_init() failed: %d\n", ret); + hang(); + } + preloader_console_init(); + + enable_tzc380(); + + /* PMIC initialization */ + power_init_board(); + init_charger_bq25896(); + + mute_speaker(); + + /* DDR initialization */ + printf("Initializing DRAM\n"); + spl_dram_init(); + + init_clk_usdhc(0); + init_clk_usdhc(1); + + log_debug("Board init\n"); + board_init_r(NULL, 0); +} diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c index b2f6087a943..f532daa16d5 100644 --- a/board/renesas/common/gen5-cm33.c +++ b/board/renesas/common/gen5-cm33.c @@ -535,12 +535,6 @@ static void clk_control_set_pll(void) #define MDLC_HSCN_BASE 0xc9c90000 /* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ #define MDLC_RT_BASE 0xb9440000 -#define MDLC_SCP_BASE 0xc1330000 - -#define MDLC_SCP_MSRES02 (MDLC_SCP_BASE + 0x908) -#define MDLC_SCP_MSRESS02 (MDLC_SCP_BASE + 0x968) -#define MDLC_SCP_MSRES02_SCP_MASK GENMASK(1, 0) -#define MDLC_SCP_PKCPROT1 (MDLC_SCP_BASE + 0xcf4) #define MDLC_PERW_MSRES05 (MDLC_PERW_BASE + 0x914) #define MDLC_PERW_MSRESS05 (MDLC_PERW_BASE + 0x974) @@ -669,32 +663,6 @@ static void mdlc_rmw_msres(const u32 prot, const u32 res, const u32 mask, const } /** - * mdlc_set_reset() - Set IP into reset - * @prot: Protect register - * @res: Reset register - * @stat: Reset register - * @mask: Mask in the register to clear - */ -static void mdlc_set_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) -{ - u32 status; - - mdlc_wait_for_reset(res, stat); - - status = field_get(mask, readl(stat)); - if (status == MDLC_MSRESS_STOP) { - mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_STANDBY); - mdlc_wait_for_reset(res, stat); - status = field_get(mask, readl(stat)); - } - - if (status == MDLC_MSRESS_STANDBY || status == MDLC_MSRESS_RUN) { - mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); - mdlc_wait_for_reset(res, stat); - } -} - -/** * mdlc_release_reset() - Release IP from reset * @prot: Protect register * @res: Reset register @@ -1260,41 +1228,6 @@ static void load_perm_tables(void) writel(0xffffffff, 0xe9a081fc); } -#define SCP_STCM_BASE 0xc1000000 -#define SCP_BASE 0xc1340000 -#define SCP_CFGVECTABLE (SCP_BASE + 0x0) -#define SCP_CFGNSSTCALIB (SCP_BASE + 0x10) -#define SCP_CPUWAIT (SCP_BASE + 0x30) -#define SCP_CFGNSSTCALIB_13_3MHZ 0x010040f0 -#define SCP_CPUWAIT_WAIT BIT(0) - -/** - * scp_initialize() - Initialize SCP - * - * Put SCP into reset, configure SCP entry point address and systick timer, - * release SCP from reset, and zero out SCP STCM regions. - */ -static void scp_initialize(void) -{ - u32 addr; - - mdlc_set_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, - MDLC_SCP_MSRES02_SCP_MASK); - - writel(SCP_STCM_BASE, SCP_CFGVECTABLE); - writel(SCP_CFGNSSTCALIB_13_3MHZ, SCP_CFGNSSTCALIB); - setbits_le32(SCP_CPUWAIT, SCP_CPUWAIT_WAIT); - - mdlc_release_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, - MDLC_SCP_MSRES02_SCP_MASK); - - /* Fill zero to SCP STCM regions 0 ... 27 */ - for (addr = SCP_STCM_BASE; addr < 0xc1061b00; addr += 8) - writeq(0, addr); - - asm volatile("dsb sy"); -} - #define GIC720AE_GICR_PWRR(cpu) \ (GICR_BASE + 0x24 + ((cpu) * 0x40000)) @@ -1362,9 +1295,6 @@ int mach_cpu_init(void) load_perm_tables(); gic720ae_init(); - /* Release SCP from reset */ - scp_initialize(); - return 0; } diff --git a/board/sophgo/milkv_duo/ethernet.c b/board/sophgo/common/ethernet.c index e997ce1037f..e997ce1037f 100644 --- a/board/sophgo/milkv_duo/ethernet.c +++ b/board/sophgo/common/ethernet.c diff --git a/board/sophgo/milkv_duo/ethernet.h b/board/sophgo/common/ethernet.h index 7b21f1b0f66..7b21f1b0f66 100644 --- a/board/sophgo/milkv_duo/ethernet.h +++ b/board/sophgo/common/ethernet.h diff --git a/board/sophgo/milkv_duo/MAINTAINERS b/board/sophgo/milkv_duo/MAINTAINERS index 651a0592f7a..6941dc5b376 100644 --- a/board/sophgo/milkv_duo/MAINTAINERS +++ b/board/sophgo/milkv_duo/MAINTAINERS @@ -2,5 +2,6 @@ Milk-V Duo M: Kongyang Liu <[email protected]> S: Maintained F: board/sophgo/milkv_duo/ +F: board/sophgo/common/ F: configs/milkv_duo_defconfig F: doc/board/sophgo/milkv_duo.rst diff --git a/board/sophgo/milkv_duo/Makefile b/board/sophgo/milkv_duo/Makefile index 18ada7d72ff..aa321d15687 100644 --- a/board/sophgo/milkv_duo/Makefile +++ b/board/sophgo/milkv_duo/Makefile @@ -3,4 +3,4 @@ # Copyright (c) 2024, Kongyang Liu <[email protected]> obj-y += board.o -obj-$(CONFIG_NET_LEGACY) += ethernet.o +obj-$(CONFIG_NET_LEGACY) += ../common/ethernet.o diff --git a/board/sophgo/milkv_duo/board.c b/board/sophgo/milkv_duo/board.c index f0944859b58..34339c42925 100644 --- a/board/sophgo/milkv_duo/board.c +++ b/board/sophgo/milkv_duo/board.c @@ -5,7 +5,7 @@ #include <dm/lists.h> -#include "ethernet.h" +#include "../common/ethernet.h" int board_init(void) { diff --git a/board/sophgo/milkv_duo_256m/Kconfig b/board/sophgo/milkv_duo_256m/Kconfig new file mode 100644 index 00000000000..a443207f65e --- /dev/null +++ b/board/sophgo/milkv_duo_256m/Kconfig @@ -0,0 +1,30 @@ +if TARGET_MILKV_DUO_256M + +config SYS_BOARD + default "milkv_duo_256m" + +config SYS_VENDOR + default "sophgo" + +config SYS_CPU + default "cv1800b" + +config SYS_CONFIG_NAME + default "milkv_duo_256m" + +# The vendor FIP tool prepends a 32-byte loader header to u-boot.bin and loads +# the result at 0x80200000, so the U-Boot code runs 0x20 bytes above that. +config TEXT_BASE + default 0x80200020 + +config ENV_SIZE + default 0x20000 + +config ENV_SECT_SIZE + default 0x40000 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOPHGO_CV1800B + +endif diff --git a/board/sophgo/milkv_duo_256m/MAINTAINERS b/board/sophgo/milkv_duo_256m/MAINTAINERS new file mode 100644 index 00000000000..929960e7251 --- /dev/null +++ b/board/sophgo/milkv_duo_256m/MAINTAINERS @@ -0,0 +1,5 @@ +Milk-V Duo 256M +M: Hiago De Franco <[email protected]> +S: Maintained +F: board/sophgo/milkv_duo_256m/ +F: configs/milkv_duo_256m_defconfig diff --git a/board/sophgo/milkv_duo_256m/Makefile b/board/sophgo/milkv_duo_256m/Makefile new file mode 100644 index 00000000000..c3068e56bf4 --- /dev/null +++ b/board/sophgo/milkv_duo_256m/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2026, Hiago De Franco <[email protected]> + +obj-y += ../milkv_duo/board.o +obj-$(CONFIG_NET_LEGACY) += ../common/ethernet.o diff --git a/board/sophgo/milkv_duo_256m/milkv_duo_256m.env b/board/sophgo/milkv_duo_256m/milkv_duo_256m.env new file mode 100644 index 00000000000..4c1e17b53ca --- /dev/null +++ b/board/sophgo/milkv_duo_256m/milkv_duo_256m.env @@ -0,0 +1,8 @@ +fdt_addr_r=0x84000000 +fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb +kernel_addr_r=0x80200000 +kernel_comp_addr_r=0x88000000 +kernel_comp_size=0x4000000 +pxefile_addr_r=0x84300000 +ramdisk_addr_r=0x84400000 +scriptaddr=0x84200000 diff --git a/board/spacemit/bananapi-f3/MAINTAINERS b/board/spacemit/bananapi-f3/MAINTAINERS deleted file mode 100644 index 131bad03181..00000000000 --- a/board/spacemit/bananapi-f3/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BananaPi F3 -M: Huan Zhou <pericycle.cc@@gmail.com> -S: Maintained -F: board/spacemit/bananapi-f3/ -F: configs/bananapi-f3_defconfig -F: doc/board/spacemit/bananapi-f3.rst diff --git a/board/spacemit/bananapi-f3/Makefile b/board/spacemit/bananapi-f3/Makefile deleted file mode 100644 index 2168698402b..00000000000 --- a/board/spacemit/bananapi-f3/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# -# Copyright (c) 2024, Kongyang Liu <[email protected]> - -obj-y := board.o diff --git a/board/spacemit/bananapi-f3/Kconfig b/board/spacemit/k1/Kconfig index f89fa9af2c7..1c615f89b64 100644 --- a/board/spacemit/bananapi-f3/Kconfig +++ b/board/spacemit/k1/Kconfig @@ -1,7 +1,7 @@ -if TARGET_BANANAPI_F3 +if TARGET_SPACEMIT_K1 config SYS_BOARD - default "bananapi-f3" + default "k1" config SYS_VENDOR default "spacemit" @@ -10,7 +10,7 @@ config SYS_CPU default "k1" config SYS_CONFIG_NAME - default "bananapi-f3" + default "k1" config TEXT_BASE default 0x00200000 diff --git a/board/spacemit/k1/MAINTAINERS b/board/spacemit/k1/MAINTAINERS new file mode 100644 index 00000000000..32d47ecc8f1 --- /dev/null +++ b/board/spacemit/k1/MAINTAINERS @@ -0,0 +1,14 @@ +BananaPi F3 +M: Huan Zhou <[email protected]> +M: Guodong Xu <[email protected]> +S: Maintained +F: arch/riscv/dts/k1-*-u-boot.dtsi +F: board/spacemit/k1/ +F: configs/spacemit_k1_defconfig +F: doc/board/spacemit/bananapi-f3.rst +F: drivers/gpio/spacemit_gpio.c +F: drivers/i2c/k1_i2c.c +F: drivers/pinctrl/spacemit/ +F: drivers/power/pmic/pmic_spacemit_p1.c +F: drivers/power/regulator/spacemit_p1_regulator.c diff --git a/board/spacemit/k1/Makefile b/board/spacemit/k1/Makefile new file mode 100644 index 00000000000..a57af2e1f08 --- /dev/null +++ b/board/spacemit/k1/Makefile @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2024, Kongyang Liu <[email protected]> +# Copyright (c) 2025-2026, RISCstar Ltd. + +obj-y := board.o +obj-$(CONFIG_SPL_BUILD) += spl.o + +DDR_FW_SRC ?= $(DDR_FW_FILE) +FW_TARGET = $(objtree)/ddr_fw.bin + +$(obj)/spl.o: $(FW_TARGET) + +$(FW_TARGET): FORCE + @if [ -n "$(DDR_FW_SRC)" ] && [ -f "$(DDR_FW_SRC)" ]; then \ + if ! cmp -s "$(DDR_FW_SRC)" $@ 2>/dev/null; then \ + echo " Copying DDR firmware from: $(DDR_FW_SRC)"; \ + cp "$(DDR_FW_SRC)" $@; \ + fi; \ + elif [ -s $@ ]; then \ + : ; \ + else \ + echo " Note: No DDR firmware found, creating empty placeholder"; \ + echo " (Set DDR_FW_FILE to specify firmware location)"; \ + touch $@; \ + fi + +clean-files += $(FW_TARGET) diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/k1/board.c index ea416621544..ea416621544 100644 --- a/board/spacemit/bananapi-f3/board.c +++ b/board/spacemit/k1/board.c diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c new file mode 100644 index 00000000000..d749e21a2d5 --- /dev/null +++ b/board/spacemit/k1/spl.c @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025-2026, RISCstar Ltd. + */ + +#include <asm/io.h> +#include <binman.h> +#include <binman_sym.h> +#include <clk.h> +#include <clk-uclass.h> +#include <cpu_func.h> +#include <configs/k1.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <i2c.h> +#include <linux/ctype.h> +#include <linux/delay.h> +#include <log.h> +#include <power/regulator.h> +#include <spi_flash.h> +#include <spl.h> +#include <tlv_eeprom.h> +#include "tlv_codes.h" + +#define MUX_MODE4 4 +#define EDGE_NONE BIT(6) +#define PULL_UP (6 << 13) /* bit[15:13] 110 */ +#define PAD_DS_MEDIUM BIT(12) +#define PAD_1V8_DS2 PAD_DS_MEDIUM +#define I2C_PIN_CONFIG(x) ((x) | EDGE_NONE | PULL_UP | PAD_1V8_DS2) +#define I2C_BUF_SIZE 64 + +#define MFP_GPIO_84 0xd401e154 +#define MFP_GPIO_85 0xd401e158 + +#define DDR_FIRMWARE_BASE 0xc082d000 + +#define DDR_DEFAULT_CS_NUM 2 +#define DDR_DEFAULT_TYPE "LPDDR4X" +#define DDR_DEFAULT_TX_ODT 80 +#define DDR_DEFAULT_DATA_RATE 2400 + +#define MAGIC_NUM 0xaa55aa55 + +typedef void (*puts_func_t)(const char *s); +typedef int (*ddr_init_func_t)(u64 ddr_base, u32 cs_num, u32 data_rate, + puts_func_t puts); + +struct ddr_cfg { + u32 data_rate; + u32 cs_num; + u32 tx_odt; + u8 type[I2C_BUF_SIZE]; +}; + +binman_sym_declare(ulong, ddr_fw, image_pos); +binman_sym_declare(ulong, ddr_fw, size); + +char product_name[I2C_BUF_SIZE] = "k1"; + +static void i2c_early_init(void) +{ + struct udevice *bus; + + // eeprom: I2C2, pin group(GPIO_84, GPIO_85) + writel(I2C_PIN_CONFIG(MUX_MODE4), (void __iomem *)MFP_GPIO_84); + writel(I2C_PIN_CONFIG(MUX_MODE4), (void __iomem *)MFP_GPIO_85); + udelay(100); + uclass_first_device(UCLASS_I2C, &bus); + while (bus) { + uclass_next_device(&bus); + if (!bus) + break; + } +} + +int read_product_name(char *name, int size) +{ + u8 eeprom_data[TLV_TOTAL_LEN_MAX], *p; + struct tlvinfo_header *tlv_hdr; + struct tlvinfo_tlv *tlv_entry; + int ret, i = 0; + u32 entry_size; + + if (!name || size <= 0) + return -EINVAL; + ret = read_tlvinfo_tlv_eeprom(eeprom_data, &tlv_hdr, + &tlv_entry, i); + if (ret) + return ret; + p = (u8 *)tlv_entry; + for (i = 0; i < tlv_hdr->totallen; ) { + if (tlv_entry->type == TLV_CODE_PRODUCT_NAME) { + if (tlv_entry->length < size) + size = tlv_entry->length; + memset(name, 0, size); + memcpy(name, &tlv_entry->value[0], size); + return 0; + } + if (tlv_entry->type == TLV_CODE_CRC_32) + return -ENOENT; + entry_size = tlv_entry->length + sizeof(struct tlvinfo_tlv); + i += entry_size; + p += entry_size; + tlv_entry = (struct tlvinfo_tlv *)p; + } + return -ENOENT; +} + +static void clk_early_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@d4090000", &dev); + if (ret) + panic("Fail to detect clock-controller@d4090000\n"); + ret = uclass_get_device_by_name(UCLASS_CLK, "system-controller@d4050000", &dev); + if (ret) + panic("Fail to detect system-controller@d4050000\n"); + ret = uclass_get_device_by_name(UCLASS_CLK, "system-controller@d4282800", &dev); + if (ret) + panic("Fail to detect system-controller@d4282800\n"); + ret = uclass_get_device_by_name(UCLASS_CLK, "system-controller@d4015000", &dev); + if (ret) + panic("Fail to detect system-controller@d4015000\n"); + + if (device_active(dev)) + log_debug("clk: device is active\n"); + else + log_debug("clk: device not active, probing...\n"); +} + +void serial_early_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_SERIAL, 0, &dev); + if (ret) + panic("Serial uclass init failed: %d\n", ret); +} + +static void set_vdd_core(void) +{ + struct udevice *dev; + int ret; + + ret = regulator_get_by_platname("vdd_core", &dev); + if (ret) + panic("Fail to detect vdd_core (%d)\n", ret); + ret = regulator_set_enable(dev, true); + if (ret) + log_warning("Fail to enable vdd_core (%d)\n", ret); + ret = regulator_get_value(dev); + if (ret < 0) + log_warning("Fail to read vdd_core (%d)\n", ret); + log_info("vdd_core, value:%d\n", ret); +} + +static void set_vdd_1v8(void) +{ + struct udevice *dev; + int ret; + + ret = regulator_get_by_platname("vdd_1v8", &dev); + if (ret) + panic("Fail to detect vdd_1v8 (%d)\n", ret); + ret = regulator_set_value(dev, 1800000); + if (ret) + log_warning("Fail to set vdd_1v8 as 1800000 (%d)\n", ret); + ret = regulator_set_enable(dev, true); + if (ret) + log_warning("Fail to enable vdd_1v8 (%d)\n", ret); + ret = regulator_get_value(dev); + if (ret < 0) + log_warning("Fail to read vdd_1v8 (%d)\n", ret); + log_info("vdd_1v8, value:%d\n", ret); +} + +static void set_vdd_mmc(void) +{ + struct udevice *dev; + int ret; + + ret = regulator_get_by_platname("vdd_1v8_mmc", &dev); + if (ret) + panic("Fail to detect vdd_1v8_mmc (%d)\n", ret); + ret = regulator_set_value(dev, 1800000); + if (ret) + log_warning("Fail to set vdd_1v8_mmc as 1800000 (%d)\n", ret); + ret = regulator_set_enable(dev, true); + if (ret) + log_warning("Fail to enable vdd_1v8_mmc (%d)\n", ret); + ret = regulator_get_value(dev); + if (ret < 0) + log_warning("Fail to read vdd_1v8_mmc (%d)\n", ret); + log_info("vdd_1v8_mmc, value:%d\n", ret); +} + +void pmic_init(void) +{ + struct udevice *pmic_dev; + int ret; + + ret = uclass_get_device(UCLASS_PMIC, 0, &pmic_dev); + if (ret) + panic("Fail to detect PMIC (%d)\n", ret); + set_vdd_core(); + set_vdd_1v8(); + set_vdd_mmc(); +} + +/* Set default value for DDR chips */ +static void ddr_cfg_init(struct ddr_cfg *cfg) +{ + memset(cfg, 0, sizeof(struct ddr_cfg)); + cfg->data_rate = DDR_DEFAULT_DATA_RATE; + cfg->cs_num = DDR_DEFAULT_CS_NUM; + cfg->tx_odt = DDR_DEFAULT_TX_ODT; + strcpy(cfg->type, DDR_DEFAULT_TYPE); +} + +int read_ddr_info(struct ddr_cfg *cfg) +{ + u8 eeprom_data[TLV_TOTAL_LEN_MAX], *p; + struct tlvinfo_header *tlv_hdr; + struct tlvinfo_tlv *tlv_entry; + u32 size, entry_size; + int ret, i; + bool found = false; + + if (!cfg) + return -EINVAL; + ddr_cfg_init(cfg); + ret = read_tlvinfo_tlv_eeprom(eeprom_data, &tlv_hdr, + &tlv_entry, i); + if (ret) + return ret; + p = (u8 *)tlv_entry; + for (i = 0; i < tlv_hdr->totallen; ) { + switch (tlv_entry->type) { + case TLV_CODE_DDR_CSNUM: + memcpy(&cfg->cs_num, &tlv_entry->value[0], 1); + found = true; + break; + case TLV_CODE_DDR_TYPE: + size = min((u32)tlv_entry->length, (u32)I2C_BUF_SIZE); + memcpy(&cfg->type[0], &tlv_entry->value[0], size); + found = true; + break; + case TLV_CODE_DDR_DATARATE: + memcpy(&cfg->data_rate, &tlv_entry->value[0], 2); + found = true; + break; + case TLV_CODE_DDR_TX_ODT: + memcpy(&cfg->tx_odt, &tlv_entry->value[0], 1); + found = true; + break; + case TLV_CODE_CRC_32: + if (!found) + return -ENOENT; + return 0; + } + entry_size = tlv_entry->length + sizeof(struct tlvinfo_tlv); + i += entry_size; + p += entry_size; + tlv_entry = (struct tlvinfo_tlv *)p; + } + if (!found) + return -ENOENT; + return 0; +} + +void ddr_early_init(void) +{ + void __iomem *src, *dst; + ulong pos, size; + struct ddr_cfg cfg; + ddr_init_func_t ddr_init; + + pos = binman_sym(ulong, ddr_fw, image_pos); + size = binman_sym(ulong, ddr_fw, size); + src = (void __iomem *)pos; + dst = (void __iomem *)(DDR_FIRMWARE_BASE); + log_info("DDR firmware: [0x%lx]:0x%x, size:0x%lx\n", pos, readl(src), size); + memcpy((u8 *)dst, (u8 *)src, size); + size = round_up(size, 64); + /* + * Ensure the just-written DDR firmware bytes are observable in the + * instruction stream. RISC-V's fence.i alone is sufficient for the + * single-hart SPL case; skip flush_dcache_range as cbo.flush may + * trap on our current privilege state. + */ + asm volatile ("fence.i" ::: "memory"); + + read_ddr_info(&cfg); + ddr_init = (ddr_init_func_t)DDR_FIRMWARE_BASE; +#ifdef DEBUG + ddr_init(0xc0000000, cfg.cs_num, cfg.data_rate, puts); +#else + ddr_init(0xc0000000, cfg.cs_num, cfg.data_rate, NULL); +#endif + writel(MAGIC_NUM, (void __iomem *)0x00000000); + flush_dcache_range(0, 64); + invalidate_dcache_range(0, 64); + if (readl((void __iomem *)0x00000000) == MAGIC_NUM) + log_info("DDR is ready\n"); + else + log_info("DDR is not ready\n"); +} + +void nor_early_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_SPI, 0, &dev); + if (ret) + panic("Fail to detect spi controller.\n"); + udelay(10); + ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev); + if (ret) + log_info("Fail to detect spi nor flash.\n"); + udelay(10); +} + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed:%d\n", ret); + + riscv_cpu_setup(); + + clk_early_init(); + serial_early_init(); + + preloader_console_init(); + + i2c_early_init(); + ret = read_product_name(product_name, I2C_BUF_SIZE); + if (ret) + log_info("Fail to detect board:%d\n", ret); + else + log_info("Get board name:%s\n", product_name); + pmic_init(); + + ddr_early_init(); + nor_early_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_SPI; +} + +void spl_board_init(void) +{ +} + +int board_fit_config_name_match(const char *name) +{ + char fdt_name[I2C_BUF_SIZE]; + int i; + + memset(fdt_name, 0, I2C_BUF_SIZE); + if (!strncmp(product_name, "k1-x_", 5)) { + snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1", + &product_name[5]); + } + if (fdt_name[0] == '\0') { + /* set default board name */ + sprintf(fdt_name, "k1-musepi-pro"); + } + for (i = 0; i < I2C_BUF_SIZE; i++) { + if (fdt_name[i] == '\0') + break; + fdt_name[i] = tolower(fdt_name[i]); + } + if (!strcmp(name, fdt_name)) + return 0; + return -ENOENT; +} + +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS; +} diff --git a/board/spacemit/k1/tlv_codes.h b/board/spacemit/k1/tlv_codes.h new file mode 100644 index 00000000000..e40fbdcee6d --- /dev/null +++ b/board/spacemit/k1/tlv_codes.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +#ifndef __TLV_CODES_H +#define __TLV_CODES_H + +#define TLV_CODE_SDK_VERSION 0x40 +#define TLV_CODE_DDR_CSNUM 0x41 +#define TLV_CODE_DDR_TYPE 0x42 +#define TLV_CODE_DDR_DATARATE 0x43 +#define TLV_CODE_DDR_TX_ODT 0x44 + +#define TLV_CODE_WIFI_MAC_ADDR 0x60 +#define TLV_CODE_BLUETOOTH_ADDR 0x61 + +#define TLV_CODE_PMIC_TYPE 0x80 +#define TLV_CODE_EEPROM_I2C_INDEX 0x81 +#define TLV_CODE_EEPROM_PIN_GROUP 0x82 + +#endif /* __TLV_CODES_H */ diff --git a/board/st/common/MAINTAINERS b/board/st/common/MAINTAINERS index 0c6db547725..e87284c6a8b 100644 --- a/board/st/common/MAINTAINERS +++ b/board/st/common/MAINTAINERS @@ -1,6 +1,6 @@ ST BOARDS M: Patrick Delaunay <[email protected]> L: [email protected] (moderated for non-subscribers) -T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-stm.git S: Maintained F: board/st/common/ diff --git a/board/st/common/stm32mp_fwu.c b/board/st/common/stm32mp_fwu.c index ac7ca6bdca2..cff020a99bb 100644 --- a/board/st/common/stm32mp_fwu.c +++ b/board/st/common/stm32mp_fwu.c @@ -3,9 +3,11 @@ * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <[email protected]> */ +#include <env.h> #include <fwu.h> #include <part_efi.h> #include <asm/io.h> +#include <asm/arch/stm32.h> /** * fwu_plat_get_bootidx() - Get the value of the boot index * @boot_idx: Boot index value diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index f924e61b3c0..f488361ab47 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -2,7 +2,7 @@ STM32MP1 BOARD M: Patrick Delaunay <[email protected]> M: Patrice Chotard <[email protected]> L: [email protected] (moderated for non-subscribers) -T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-stm.git S: Maintained F: arch/arm/dts/stm32mp13* F: arch/arm/dts/stm32mp15* diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index e231467f2a1..1b4d623d002 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -144,7 +144,12 @@ int board_fit_config_name_match(const char *name) !strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { return 0; } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-lite") && - !strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) { + !strncmp(get_product_id_from_eeprom(), "VF7110SL", 8) && + !get_mmc_size_from_eeprom()) { + return 0; + } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-lite-emmc") && + !strncmp(get_product_id_from_eeprom(), "VF7110SL", 8) && + get_mmc_size_from_eeprom()) { return 0; } diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index 1a76f745ec8..97f40715f8f 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -72,7 +72,11 @@ static void set_fdtfile(void) } else if (!strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "VF7110SL", 8)) { - fdtfile = "starfive/jh7110-starfive-visionfive-2-lite.dtb"; + if (get_mmc_size_from_eeprom()) { + fdtfile = "starfive/jh7110-starfive-visionfive-2-lite-emmc.dtb"; + } else { + fdtfile = "starfive/jh7110-starfive-visionfive-2-lite.dtb"; + } } else { log_err("Unknown product\n"); return; diff --git a/board/sysam/amcore/MAINTAINERS b/board/sysam/amcore/MAINTAINERS index fe5dd9bf39c..01086ef11bb 100644 --- a/board/sysam/amcore/MAINTAINERS +++ b/board/sysam/amcore/MAINTAINERS @@ -1,5 +1,5 @@ AMCORE BOARD -M: Angelo Dureghello <[email protected]> +M: Angelo Dureghello <[email protected]> S: Maintained F: board/sysam/amcore/ F: include/configs/amcore.h diff --git a/board/sysam/amcore/Makefile b/board/sysam/amcore/Makefile index 051186f0d5c..22a71f91170 100644 --- a/board/sysam/amcore/Makefile +++ b/board/sysam/amcore/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2014 Angelo Dureghello <[email protected]> +# (C) Copyright 2014 Angelo Dureghello <[email protected]> # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index d5aa1f0776f..0ab9d97e865 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -2,7 +2,7 @@ /* * Board functions for Sysam AMCORE (MCF5307 based) board * - * (C) Copyright 2016 Angelo Dureghello <[email protected]> + * (C) Copyright 2016 Angelo Dureghello <[email protected]> * * This file copies memory testdram() from sandburst/common/sb_common.c */ diff --git a/board/sysam/stmark2/MAINTAINERS b/board/sysam/stmark2/MAINTAINERS index b87f432bb3f..f7b6e6d216f 100644 --- a/board/sysam/stmark2/MAINTAINERS +++ b/board/sysam/stmark2/MAINTAINERS @@ -1,5 +1,5 @@ STMARK2 BOARD -M: Angelo Dureghello <[email protected]> +M: Angelo Dureghello <[email protected]> S: Maintained F: board/sysam/stmark2/ F: include/configs/stmark2.h diff --git a/board/sysam/stmark2/Makefile b/board/sysam/stmark2/Makefile index 064a57ea05e..3c007567754 100644 --- a/board/sysam/stmark2/Makefile +++ b/board/sysam/stmark2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2014 Angelo Dureghello <[email protected]> +# (C) Copyright 2014 Angelo Dureghello <[email protected]> # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/board/sysam/stmark2/sbf_dram_init.S b/board/sysam/stmark2/sbf_dram_init.S index b6f38731f11..bc1a6cd20d4 100644 --- a/board/sysam/stmark2/sbf_dram_init.S +++ b/board/sysam/stmark2/sbf_dram_init.S @@ -2,7 +2,7 @@ /* * Board-specific early ddr/sdram init. * - * (C) Copyright 2017 Angelo Dureghello <[email protected]> + * (C) Copyright 2017 Angelo Dureghello <[email protected]> */ .equ PPMCR0, 0xfc04002d diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c index 7818f2671d5..f0bf67c4fc4 100644 --- a/board/sysam/stmark2/stmark2.c +++ b/board/sysam/stmark2/stmark2.c @@ -2,7 +2,7 @@ /* * Board-specific init. * - * (C) Copyright 2017 Angelo Dureghello <[email protected]> + * (C) Copyright 2017 Angelo Dureghello <[email protected]> */ #include <config.h> diff --git a/board/ti/am62ax/MAINTAINERS b/board/ti/am62ax/MAINTAINERS index 590f683584e..bb0de6a0496 100644 --- a/board/ti/am62ax/MAINTAINERS +++ b/board/ti/am62ax/MAINTAINERS @@ -7,3 +7,5 @@ F: board/ti/am62ax/ F: include/configs/am62a7_evm.h F: configs/am62ax_evm_r5_defconfig F: configs/am62ax_evm_a53_defconfig +F: configs/am62ax_evm_r5_ethboot_defconfig +F: configs/am62ax_evm_a53_ethboot_defconfig diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index 4916eec3b2b..adb784e69a8 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -6,6 +6,7 @@ * */ +#include <image.h> #include <asm/arch/hardware.h> #include <asm/io.h> #include <dm/uclass.h> @@ -17,6 +18,11 @@ #include "../common/fdt_ops.h" #include "../common/k3_32k_lfosc.h" +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} + #if defined(CONFIG_XPL_BUILD) void spl_perform_board_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 8fde47fb1be..9fa0a1c9f72 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -7,6 +7,7 @@ */ #include <efi_loader.h> +#include <image.h> #include <asm/arch/hardware.h> #include <asm/io.h> #include <cpu_func.h> @@ -43,6 +44,11 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} + #if IS_ENABLED(CONFIG_SPL_BUILD) void spl_board_init(void) { diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 49e58ad6d6c..90beed341b6 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -18,6 +18,7 @@ #include <fdt_support.h> #include <fdt_simplefb.h> #include <asm/io.h> +#include <image.h> #include <asm/arch/hardware.h> #include <dm/uclass.h> #include <asm/arch/k3-ddr.h> @@ -135,6 +136,11 @@ int board_late_init(void) } #endif +int board_fit_config_name_match(const char *name) +{ + return k3_fit_config_match_security_state(name); +} + #if defined(CONFIG_XPL_BUILD) void spl_board_init(void) { diff --git a/board/toradex/aquila-imx95/aquila-imx95.c b/board/toradex/aquila-imx95/aquila-imx95.c index 0c6473e4b3a..a5b26ef3dc3 100644 --- a/board/toradex/aquila-imx95/aquila-imx95.c +++ b/board/toradex/aquila-imx95/aquila-imx95.c @@ -3,14 +3,35 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <errno.h> #include <fdt_support.h> #include <init.h> #include "../common/tdx-cfg-block.h" +/* + * The address wrap-around is not linear: address bits above the module + * capacity alias back to the base with some low address bits XORed, as + * measured on 4GB and 8GB modules (bit 32 -> XOR 0xc000, bit 33 -> XOR + * 0x2000). + */ +static const struct ram_alias_check ram_alias_checks[] = { + { (void *)((uintptr_t)PHYS_SDRAM + SZ_4G), (void *)((uintptr_t)PHYS_SDRAM + 0xc000), SZ_8G }, + { (void *)((uintptr_t)PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G }, + { NULL } +}; + int board_phys_sdram_size(phys_size_t *size) { - *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + phys_size_t sz; + + sz = probe_ram_size_by_alias(ram_alias_checks); + if (!sz) { + puts("## WARNING: Less than 4GB RAM detected\n"); + return -EINVAL; + } + + *size = sz - PHYS_SDRAM_FW_RSVD; return 0; } diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 896a0d3bd12..0b1798dc812 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -190,6 +190,18 @@ const struct toradex_som toradex_modules[] = { { VERDIN_IMX95H_4G_WB_IT, "Verdin iMX95 Hexa 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, { VERDIN_IMX95H_4G_ET, "Verdin iMX95 Hexa 4GB ET", TARGET_IS_ENABLED(VERDIN_IMX95) }, { VERDIN_IMX95H_16G_IT, "Verdin iMX95 Hexa 16GB IT", TARGET_IS_ENABLED(VERDIN_IMX95) }, + { SMARC_IMX95_HEXA_4GB_IT, "SMARC iMX95 Hexa 4GB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX95) }, + { AQUILA_TDA4O_8GB_IT, "Aquila TDA4 Octa 8GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { APALIS_IMX8QM_4GB_WIFI_BT_IT_64G, "Apalis iMX8QM 4GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, + { APALIS_IMX8QM_4GB_IT_64G, "Apalis iMX8QM 4GB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, + { APALIS_IMX8QM_8GB_WIFI_BT_IT_64G, "Apalis iMX8QM 8GB WB IT", TARGET_IS_ENABLED(APALIS_IMX8) }, + { VERDIN_IMX8MPQ_4GB_WIFI_BT_IT_64G, "Verdin iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { VERDIN_IMX8MPQ_4GB_IT_64G, "Verdin iMX8M Plus Quad 4GB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { VERDIN_IMX8MPQ_8GB_WIFI_BT_IT_64G, "Verdin iMX8M Plus Quad 8GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MP) }, + { VERDIN_IMX8MMQ_2G_WIFI_BT_IT_64G, "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, + { SMARC_IMX8MPQ_4GB_WB_IT_64G, "SMARC iMX8M Plus Quad 4GB WB IT", TARGET_IS_ENABLED(TORADEX_SMARC_IMX8MP) }, + { VERDIN_AM62D_1G_WIFI_BT_ET, "Verdin AM62 Dual 1GB WB ET", TARGET_IS_ENABLED(VERDIN_AM62_A53) }, + { AQUILA_IMX95_HEXA_8GB_IT, "Aquila iMX95 Hexa 8GB IT", TARGET_IS_ENABLED(AQUILA_IMX95) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 9a96bddfbe1..32305c61c83 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -153,6 +153,18 @@ enum { VERDIN_IMX95H_4G_WB_IT = 226, VERDIN_IMX95H_4G_ET, VERDIN_IMX95H_16G_IT, + SMARC_IMX95_HEXA_4GB_IT, + AQUILA_TDA4O_8GB_IT, /* 230 */ + APALIS_IMX8QM_4GB_WIFI_BT_IT_64G = 233, + APALIS_IMX8QM_4GB_IT_64G, + APALIS_IMX8QM_8GB_WIFI_BT_IT_64G, /* 235 */ + VERDIN_IMX8MPQ_4GB_WIFI_BT_IT_64G, + VERDIN_IMX8MPQ_4GB_IT_64G, + VERDIN_IMX8MPQ_8GB_WIFI_BT_IT_64G, + VERDIN_IMX8MMQ_2G_WIFI_BT_IT_64G, + SMARC_IMX8MPQ_4GB_WB_IT_64G, /* 240 */ + VERDIN_AM62D_1G_WIFI_BT_ET = 242, + AQUILA_IMX95_HEXA_8GB_IT, }; enum { diff --git a/board/toradex/smarc-imx95/smarc-imx95.c b/board/toradex/smarc-imx95/smarc-imx95.c index 6040c49975a..d09ce8a52ab 100644 --- a/board/toradex/smarc-imx95/smarc-imx95.c +++ b/board/toradex/smarc-imx95/smarc-imx95.c @@ -3,14 +3,35 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#include <errno.h> #include <fdt_support.h> #include <init.h> #include "../common/tdx-cfg-block.h" +/* + * The address wrap-around is not linear: address bits above the module + * capacity alias back to the base with some low address bits XORed, as + * measured on 4GB and 8GB modules (bit 32 -> XOR 0xc000, bit 33 -> XOR + * 0x2000). + */ +static const struct ram_alias_check ram_alias_checks[] = { + { (void *)((uintptr_t)PHYS_SDRAM + SZ_4G), (void *)((uintptr_t)PHYS_SDRAM + 0xc000), SZ_8G }, + { (void *)((uintptr_t)PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G }, + { NULL } +}; + int board_phys_sdram_size(phys_size_t *size) { - *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + phys_size_t sz; + + sz = probe_ram_size_by_alias(ram_alias_checks); + if (!sz) { + puts("## WARNING: Less than 4GB RAM detected\n"); + return -EINVAL; + } + + *size = sz - PHYS_SDRAM_FW_RSVD; return 0; } diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 26af1af2069..6d55638b44b 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -12,6 +12,7 @@ #include <dm/uclass.h> #include <env.h> #include <fdt_support.h> +#include <image.h> #include <init.h> #include <k3-ddrss.h> #include <spl.h> @@ -57,12 +58,10 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return 0x9C000000; } -#if defined(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { - return 0; + return k3_fit_config_match_security_state(name); } -#endif #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) @@ -85,7 +84,8 @@ static void select_dt_from_module_version(void) is_wifi = (tdx_hw_tag.prodid == VERDIN_AM62Q_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_AM62S_512MB_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_AM62D_1G_WIFI_BT_IT) || - (tdx_hw_tag.prodid == VERDIN_AM62Q_2G_WIFI_BT_IT); + (tdx_hw_tag.prodid == VERDIN_AM62Q_2G_WIFI_BT_IT) || + (tdx_hw_tag.prodid == VERDIN_AM62D_1G_WIFI_BT_ET); } if (is_wifi) diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c index ec7775e06a7..1e7fcc9fd9d 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.c +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -14,6 +14,7 @@ #include <dm/uclass.h> #include <env.h> #include <fdt_support.h> +#include <image.h> #include <init.h> #include <k3-ddrss.h> #include <spl.h> @@ -83,12 +84,10 @@ int dram_init_banksize(void) return ret; } -#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { - return 0; + return k3_fit_config_match_security_state(name); } -#endif #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index b56f5bf30a8..4e308084968 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -83,7 +83,8 @@ static void select_dt_from_module_version(void) (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) || (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET) || - (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WB_IT_64G); + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WB_IT_64G) || + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_2G_WIFI_BT_IT_64G); } switch (get_pcb_revision()) { diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 69c3408fbba..1209da593f8 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -79,7 +79,9 @@ static void select_dt_from_module_version(void) is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_2GB_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT) || - (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT_IT); + (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT_IT) || + (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_4GB_WIFI_BT_IT_64G) || + (tdx_hw_tag.prodid == VERDIN_IMX8MPQ_8GB_WIFI_BT_IT_64G); } if (is_wifi) diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c index 005f08c4e5f..f4cd9915185 100644 --- a/board/tq/tqma6/tqma6.c +++ b/board/tq/tqma6/tqma6.c @@ -31,6 +31,18 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * Rev. 0200 and newer optionally implements GIGE errata fix. + * Use a global var to signal presence of the fix. This should be checked + * early. If fix is present, system I2C is I2C1 - otherwise I2C3 + */ +static int has_enet_workaround = -1; + +int tqma6_has_enet_workaround(void) +{ + return has_enet_workaround; +} + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -38,6 +50,36 @@ int dram_init(void) return 0; } +#define GPIO_REVDET_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +static const iomux_v3_cfg_t tqma6_revdet_pads[] = { + MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(GPIO_REVDET_PAD_CTRL), +}; + +void tqma6_detect_enet_workaround(void) +{ + int ret; + struct gpio_desc desc; + + imx_iomux_v3_setup_multiple_pads(tqma6_revdet_pads, + ARRAY_SIZE(tqma6_revdet_pads)); + + ret = dm_gpio_lookup_name("GPIO1_6", &desc); + if (ret) { + pr_err("error: gpio lookup for enet workaround %d\n", ret); + return; + } + + ret = dm_gpio_get_value(&desc); + if (ret == 0) + has_enet_workaround = 1; + else if (ret > 0) + has_enet_workaround = 0; + + dm_gpio_free(NULL, &desc); +} + int board_early_init_f(void) { return tq_bb_board_early_init_f(); @@ -75,6 +117,16 @@ static const char *tqma6_get_boardname(void) }; } +const char *tqma6_get_fdt_configuration(void) +{ + if (is_mx6dq()) + return !tqma6_has_enet_workaround() ? "imx6q-mba6b" : "imx6q-mba6a"; + if (is_mx6sdl()) + return !tqma6_has_enet_workaround() ? "imx6dl-mba6b" : "imx6dl-mba6a"; + + return NULL; +} + #if CONFIG_IS_ENABLED(DM_PMIC) /* setup board specific PMIC */ int power_init_board(void) @@ -95,15 +147,44 @@ int power_init_board(void) } #endif +#define FDTFILE_STRLEN 32u int board_late_init(void) { + char fdtfile[FDTFILE_STRLEN]; + const char *config = tqma6_get_fdt_configuration(); + env_set("board_name", tqma6_get_boardname()); + tqma6_detect_enet_workaround(); + + if (!env_get("fdtfile")) { + if (config) { + snprintf(fdtfile, FDTFILE_STRLEN, "%s.dtb", config); + env_set_runtime("fdtfile", fdtfile); + } else { + pr_err("ENV: Could not set kernel devicetree, ${fdtfile} remains unset\n"); + } + } + tq_bb_board_late_init(); printf("Board: %s on a %s\n", tqma6_get_boardname(), tq_bb_get_boardname()); + puts("Enet workaround: "); + switch (tqma6_has_enet_workaround()) { + case 0: + puts("absent"); + break; + case 1: + puts("implemented"); + break; + default: + puts("Unknown"); + break; + }; + puts("\n"); + return tq_bb_checkboard(); } @@ -111,15 +192,10 @@ int board_late_init(void) * Device Tree Support */ #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -#define MODELSTRLEN 32u int ft_board_setup(void *blob, struct bd_info *bd) { struct mmc *mmc = find_mmc_device(0); - char modelstr[MODELSTRLEN]; - snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(), - tq_bb_get_boardname()); - do_fixup_by_path_string(blob, "/", "model", modelstr); fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size); /* bring in eMMC dsr settings if needed */ diff --git a/board/tq/tqma6/tqma6.h b/board/tq/tqma6/tqma6.h new file mode 100644 index 00000000000..bc09087e3df --- /dev/null +++ b/board/tq/tqma6/tqma6.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Paul Gerber + */ + +#ifndef __TQMA6_H +#define __TQMA6_H + +const char *tqma6_get_fdt_configuration(void); +int tqma6_has_enet_workaround(void); + +#endif /* __TQMA6_H */ diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c index 32aeb1b07c8..8cc5857b06f 100644 --- a/board/tq/tqma6/tqma6_mba6.c +++ b/board/tq/tqma6/tqma6_mba6.c @@ -33,21 +33,11 @@ #include "../common/tq_bb.h" -#if defined(CONFIG_TQMA6Q) - -#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 -#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac - -#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) - -#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 -#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 +#define TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 +#define TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac -#else - -#error "need to select module" - -#endif +#define TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 +#define TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 /* disable on die termination for RGMII */ #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000 @@ -63,10 +53,17 @@ static void mba6_setup_iomuxc_enet(void) /* clear gpr1[ENET_CLK_SEL] for externel clock */ clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); - __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, - (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); - __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, - (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); + if (is_mx6sdl()) { + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, + (void *)TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, + (void *)TQMA6DL_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); + } else if (is_mx6dq()) { + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, + (void *)TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); + __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, + (void *)TQMA6Q_IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); + } } int board_mmc_get_env_dev(int devno) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 52a2e8767d8..f45b879736e 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -14,6 +14,8 @@ #include <init.h> #include <jffs2/load_kernel.h> #include <log.h> +#include <memalign.h> +#include <mtd.h> #include <asm/io.h> #include <asm/global_data.h> #include <asm/sections.h> @@ -22,6 +24,7 @@ #endif #include <dm/uclass.h> #include <i2c.h> +#include <linux/err.h> #include <linux/sizes.h> #include <malloc.h> #include <memtop.h> @@ -65,6 +68,8 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; +#define DFU_ALT_BUF_LEN SZ_1K + #endif /* EFI_HAVE_CAPSULE_SUPPORT */ #define EEPROM_HEADER_MAGIC 0xdaaddeed @@ -846,6 +851,36 @@ int fwu_platform_hook(struct udevice *dev, struct fwu_data *data) /* Copy image type GUID */ memcpy(&fw_images[0].image_type_id, &img_entry->image_type_guid, 16); + /* + * Generate the capsule DFU string from the FWU metadata. This has to + * happen here, and not in configure_capsule_updates() called from + * board_late_init(), because the FWU data is only populated by + * fwu_boottime_checks() at EVT_POST_PREBOOT. + */ + { + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + struct mtd_info *mtd; + int ret; + + memset(buf, 0, DFU_ALT_BUF_LEN); + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor0"); + if (IS_ERR_OR_NULL(mtd)) + return -ENODEV; + + ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); + if (ret < 0) { + log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); + return ret; + } + log_debug("Make dfu_alt_info: '%s'\n", buf); + + update_info.dfu_string = strdup(buf); + debug("Capsule DFU: %s\n", update_info.dfu_string); + } + if (IS_ENABLED(CONFIG_EFI_ESRT)) { efi_status_t ret; diff --git a/board/xilinx/microblaze-generic/MAINTAINERS b/board/xilinx/microblaze-generic/MAINTAINERS index 29ed32f78f9..5220a51a5ea 100644 --- a/board/xilinx/microblaze-generic/MAINTAINERS +++ b/board/xilinx/microblaze-generic/MAINTAINERS @@ -1,7 +1,7 @@ MICROBLAZE-GENERIC BOARD M: Michal Simek <[email protected]> S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git F: board/xilinx/microblaze-generic/ F: include/configs/microblaze-generic.h F: configs/microblaze-generic_defconfig diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS index a13b6566164..07173ee916f 100644 --- a/board/xilinx/versal/MAINTAINERS +++ b/board/xilinx/versal/MAINTAINERS @@ -1,7 +1,7 @@ XILINX_VERSAL BOARDS M: Michal Simek <[email protected]> S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git F: arch/arm/dts/versal* F: board/xilinx/versal/ F: include/configs/xilinx_versal* diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 0537517b1b2..e3e1085fce7 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -10,7 +10,6 @@ #include <env.h> #include <efi_loader.h> #include <fdtdec.h> -#include <fwu.h> #include <init.h> #include <env_internal.h> #include <log.h> @@ -314,8 +313,6 @@ enum env_location env_get_location(enum env_operation op, int prio) #define DFU_ALT_BUF_LEN SZ_1K -#if defined(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) && \ - !defined(CONFIG_FWU_MULTI_BANK_UPDATE) static void mtd_found_part(u32 *base, u32 *size) { struct mtd_info *part, *mtd; @@ -392,39 +389,3 @@ void configure_capsule_updates(void) update_info.dfu_string = strdup(buf); debug("Capsule DFU: %s\n", update_info.dfu_string); } -#endif - -#if defined(CONFIG_FWU_MULTI_BANK_UPDATE) - -/* Generate dfu_alt_info from partitions */ -void set_dfu_alt_info(char *interface, char *devstr) -{ - int ret; - struct mtd_info *mtd; - - /* - * It is called multiple times for every image - * per bank that's why enough to set it up once. - */ - if (env_get("dfu_alt_info")) - return; - - ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); - memset(buf, 0, DFU_ALT_BUF_LEN); - - mtd_probe_devices(); - - mtd = get_mtd_device_nm("nor0"); - if (IS_ERR_OR_NULL(mtd)) - return; - - ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); - if (ret < 0) { - log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); - return; - } - log_debug("Make dfu_alt_info: '%s'\n", buf); - - env_set("dfu_alt_info", buf); -} -#endif diff --git a/board/xilinx/zynq/MAINTAINERS b/board/xilinx/zynq/MAINTAINERS index b5b9e2fe40a..3eb1a451b58 100644 --- a/board/xilinx/zynq/MAINTAINERS +++ b/board/xilinx/zynq/MAINTAINERS @@ -1,7 +1,7 @@ ZYNQ BOARD M: Michal Simek <[email protected]> S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git F: arch/arm/dts/zynq-* F: board/xilinx/zynq/ F: include/configs/zynq*.h diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index a4527f8959a..3db240782f4 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -1,7 +1,7 @@ XILINX_ZYNQMP BOARDS M: Michal Simek <[email protected]> S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git +T: git https://git.u-boot-project.org/u-boot/custodians/u-boot-microblaze.git F: arch/arm/dts/zynqmp-* F: arch/arm/dts/avnet-ultra96* F: board/xilinx/common/ |