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-rw-r--r--board/armltd/vexpress64/Kconfig71
-rw-r--r--board/armltd/vexpress64/MAINTAINERS5
-rw-r--r--board/armltd/vexpress64/vexpress64.c44
-rw-r--r--board/freescale/ls1046ardb/MAINTAINERS1
-rw-r--r--board/freescale/ls1046ardb/README76
-rw-r--r--board/freescale/ls1046ardb/ls1046ardb.c11
6 files changed, 114 insertions, 94 deletions
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 4aab3f092ec..a0314c65379 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO
+if ARCH_VEXPRESS64
config SYS_BOARD
default "vexpress64"
@@ -9,6 +9,43 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "vexpress_aemv8"
+config VEXPRESS64_BASE_MODEL
+ bool
+ select SEMIHOSTING
+ select VIRTIO_BLK if VIRTIO_MMIO
+ select VIRTIO_NET if VIRTIO_MMIO
+ select DM_ETH if VIRTIO_NET
+ select LINUX_KERNEL_IMAGE_HEADER
+ select POSITION_INDEPENDENT
+
+choice
+ prompt "VExpress64 board variant"
+
+config TARGET_VEXPRESS64_BASE_FVP
+ bool "Support Versatile Express ARMv8a FVP BASE model"
+ select VEXPRESS64_BASE_MODEL
+ select OF_BOARD
+
+config TARGET_VEXPRESS64_BASER_FVP
+ bool "Support Versatile Express ARMv8r64 FVP BASE model"
+ select VEXPRESS64_BASE_MODEL
+ imply OF_HAS_PRIOR_STAGE
+
+config TARGET_VEXPRESS64_JUNO
+ bool "Support Versatile Express Juno Development Platform"
+ select PCIE_ECAM_GENERIC if PCI
+ select SATA_SIL
+ select SMC911X if DM_ETH
+ select SMC911X_32_BIT if SMC911X
+ select CMD_USB if USB
+ select USB_EHCI_HCD if USB
+ select USB_EHCI_GENERIC if USB
+ select USB_OHCI_HCD if USB
+ select USB_OHCI_GENERIC if USB
+ imply OF_HAS_PRIOR_STAGE
+
+endchoice
+
config JUNO_DTB_PART
string "NOR flash partition holding DTB"
default "board.dtb"
@@ -16,4 +53,36 @@ config JUNO_DTB_PART
The ARM partition name in the NOR flash memory holding the
device tree blob to configure U-Boot.
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+ default SYS_TEXT_BASE
+
+config SYS_TEXT_BASE
+ default 0x88000000 if TARGET_VEXPRESS64_BASE_FVP
+ default 0xe0000000 if TARGET_VEXPRESS64_JUNO
+ default 0x00001000 if TARGET_VEXPRESS64_BASER_FVP
+
+config SYS_MALLOC_LEN
+ default 0x810000 if TARGET_VEXPRESS64_JUNO
+ default 0x840000 if TARGET_VEXPRESS64_BASE_FVP
+
+config SYS_MALLOC_F_LEN
+ default 0x2000
+
+config SYS_LOAD_ADDR
+ default 0x10000000 if TARGET_VEXPRESS64_BASER_FVP
+ default 0x90000000
+
+config ENV_ADDR
+ default 0x0BFC0000 if TARGET_VEXPRESS64_JUNO
+ default 0x0FFC0000 if TARGET_VEXPRESS64_BASE_FVP
+ default 0x8FFC0000 if TARGET_VEXPRESS64_BASER_FVP
+
+config ENV_SIZE
+ default 0x10000 if TARGET_VEXPRESS64_JUNO
+ default 0x40000
+
+config ENV_SECT_SIZE
+ default 0x10000 if TARGET_VEXPRESS64_JUNO
+ default 0x40000
+
endif
diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS
index 0ba044d7ff8..b3ecc9bba03 100644
--- a/board/armltd/vexpress64/MAINTAINERS
+++ b/board/armltd/vexpress64/MAINTAINERS
@@ -14,3 +14,8 @@ JUNO DEVELOPMENT PLATFORM BOARD
M: Linus Walleij <[email protected]>
S: Maintained
F: configs/vexpress_aemv8a_juno_defconfig
+
+VEXPRESS64 ARMV8R-64
+M: Peter Hoyes <[email protected]>
+S: Maintained
+F: configs/vexpress_aemv8r_defconfig
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 5e22e89824e..709ebf3fb08 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -15,6 +15,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/compiler.h>
+#include <linux/sizes.h>
#include <dm/platform_data/serial_pl01x.h>
#include "pcie.h"
#include <asm/armv8/mmu.h>
@@ -38,16 +39,27 @@ U_BOOT_DRVINFO(vexpress_serials) = {
static struct mm_region vexpress64_mem_map[] = {
{
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
+ .virt = V2M_PA_BASE,
+ .phys = V2M_PA_BASE,
+ .size = SZ_2G,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0xff80000000UL,
+ .virt = V2M_DRAM_BASE,
+ .phys = V2M_DRAM_BASE,
+ .size = SZ_2G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /*
+ * DRAM beyond 2 GiB is located high. Let's map just some
+ * of it, although U-Boot won't realistically use it, and
+ * the actual available amount might be smaller on the model.
+ */
+ .virt = 0x880000000UL, /* 32 + 2 GiB */
+ .phys = 0x880000000UL,
+ .size = 6UL * SZ_1G,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
@@ -76,20 +88,12 @@ int board_init(void)
int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
+ return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-#ifdef PHYS_SDRAM_2
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-#endif
-
- return 0;
+ return fdtdec_setup_memory_banksize();
}
/* Assigned in lowlevel_init.S
@@ -168,11 +172,17 @@ void *board_fdt_blob_setup(int *err)
}
#endif
- if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC) {
+ if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC &&
+ fdt_totalsize(prior_stage_fdt_address) > 0x100) {
*err = 0;
return (void *)prior_stage_fdt_address;
}
+ if (fdt_magic(gd->fdt_blob) == FDT_MAGIC) {
+ *err = 0;
+ return (void *)gd->fdt_blob;
+ }
+
*err = -ENXIO;
return NULL;
}
diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS
index efdea22bdeb..3c8cfe720dc 100644
--- a/board/freescale/ls1046ardb/MAINTAINERS
+++ b/board/freescale/ls1046ardb/MAINTAINERS
@@ -14,3 +14,4 @@ F: configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
F: configs/ls1046ardb_SECURE_BOOT_defconfig
F: configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
F: configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+F: doc/board/nxp/ls1046ardb.rst
diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
deleted file mode 100644
index 90c44f4bce3..00000000000
--- a/board/freescale/ls1046ardb/README
+++ /dev/null
@@ -1,76 +0,0 @@
-Overview
---------
-The LS1046A Reference Design Board (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS1046A
-LayerScape Architecture processor. The LS1046ARDB provides SW development
-platform for the Freescale LS1046A processor series, with a complete
-debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
-
-LS1046A SoC Overview
---------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
-SoC overview.
-
- LS1046ARDB board Overview
- -----------------------
- - SERDES1 Connections, 4 lanes supporting:
- - Lane0: 10GBase-R with x1 RJ45 connector
- - Lane1: 10GBase-R Cage
- - Lane2: SGMII.5
- - Lane3: SGMII.6
- - SERDES2 Connections, 4 lanes supporting:
- - Lane0: PCIe1 with miniPCIe slot
- - Lane1: PCIe2 with PCIe x2 slot
- - Lane2: PCIe3 with PCIe x4 slot
- - Lane3: SATA
- - DDR Controller
- - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
- -IFC/Local Bus
- - One 512 MB NAND flash with ECC support
- - CPLD connection
- - USB 3.0
- - one Type A port, one Micro-AB port
- - SDHC: connects directly to a full SD/MMC slot
- - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
- - 4 I2C controllers
- - UART
- - Two 4-pin serial ports at up to 115.2 Kbit/s
- - Two DB9 D-Type connectors supporting one Serial port each
- - ARM JTAG support
-
-Memory map from core's view
-----------------------------
-Start Address End Address Description Size
-0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
-0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
-0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
-0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
-0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
-0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
-0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
-0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
-0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
-0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
-0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
-0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
-0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
-0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
-
-QSPI flash map:
-Start Address End Address Description Size
-0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB
-0x00_4010_0000 - 0x00_402F_FFFF U-Boot 2MB
-0x00_4030_0000 - 0x00_403F_FFFF U-Boot Env 1MB
-0x00_4040_0000 - 0x00_405F_FFFF PPA 2MB
-0x00_4060_0000 - 0x00_408F_FFFF Secure boot header
- + bootscript 3MB
-0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
-0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
-0x00_4098_0000 - 0x00_40FF_FFFF Reserved 6MB
-0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
-
-Booting Options
----------------
-a) QSPI boot
-b) SD boot
-c) eMMC boot
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index d0abfe8869f..f2949cf8b69 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -7,6 +7,8 @@
#include <i2c.h>
#include <fdt_support.h>
#include <init.h>
+#include <semihosting.h>
+#include <serial.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
@@ -27,6 +29,15 @@
DECLARE_GLOBAL_DATA_PTR;
+struct serial_device *default_serial_console(void)
+{
+#if IS_ENABLED(CONFIG_SEMIHOSTING_SERIAL)
+ if (semihosting_enabled())
+ return &serial_smh_device;
+#endif
+ return &eserial1_device;
+}
+
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
generated by cgit v1.3.1 (git 2.54.0) at 2026-07-08 03:21:03 +0000