diff options
Diffstat (limited to 'doc/board')
42 files changed, 2091 insertions, 301 deletions
diff --git a/doc/board/alliedtelesis/index.rst b/doc/board/alliedtelesis/index.rst new file mode 100644 index 00000000000..a8de2986609 --- /dev/null +++ b/doc/board/alliedtelesis/index.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2026 Allied Telesis Labs + +Allied Telesis +============== + +.. toctree:: + :maxdepth: 2 + + x220 + diff --git a/doc/board/alliedtelesis/x220.rst b/doc/board/alliedtelesis/x220.rst new file mode 100644 index 00000000000..6ca5f61ec4e --- /dev/null +++ b/doc/board/alliedtelesis/x220.rst @@ -0,0 +1,39 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2026 Allied Telesis Labs + +x220 Platforms +============== + +Introduction +------------ + +The x220 has is a range of L2+ switches using the Marvell AlleyCat3 switch with +integrated ARMv7 CPU. It is also sold under some different brands for different +markets. + +- x220-52GP +- x220-52GT +- x220-28GS +- GS980M/52PS +- GS980M/52 +- x230-52 + +DDR Traning (binhdr) +-------------------- + +The AlleyCat3 uses a binary blob for it's DDR training. This is launched by +the built-in bootloader prior to U-Boot starting. + +To generate binary.0 from Marvell's bin_hdr.elf use the following command + +.. prompt:: bash $ + + arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \ + board/alliedtelesis/x220/binary.0 + +Alternatively, it is possible to extract the binary.0 from an existing U-Boot +image + +.. prompt:: bash $ + + ./tools/dumpimage -T kwbimage -p 1 -o board/alliedtelesis/x220/binary.0 u-boot.kwb diff --git a/doc/board/amlogic/beelink-gt1-ultimate.rst b/doc/board/amlogic/beelink-gt1-ultimate.rst index a78a1a2ff25..22afae0ed40 100644 --- a/doc/board/amlogic/beelink-gt1-ultimate.rst +++ b/doc/board/amlogic/beelink-gt1-ultimate.rst @@ -30,19 +30,19 @@ U-Boot Compilation .. code-block:: bash - $ export CROSS_COMPILE=aarch64-none-elf- - $ make beelink-gt1-ultimate_defconfig - $ make + $ export CROSS_COMPILE=aarch64-none-elf- + $ make beelink-gt1-ultimate_defconfig + $ make U-Boot Signing with Pre-Built FIP repo -------------------------------------- .. code-block:: bash - $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 - $ cd amlogic-boot-fip - $ mkdir my-output-dir - $ ./build-fip.sh beelink-gt1 /path/to/u-boot/u-boot.bin my-output-dir + $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 + $ cd amlogic-boot-fip + $ mkdir my-output-dir + $ ./build-fip.sh beelink-gt1 /path/to/u-boot/u-boot.bin my-output-dir U-Boot Manual Signing --------------------- @@ -53,58 +53,58 @@ for signing. However you can download them from the amlogic-fip-repo. .. code-block:: bash - $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 - $ cd amlogic-boot-fip/beelink-gt1 - $ export FIPDIR=$PWD + $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 + $ cd amlogic-boot-fip/beelink-gt1 + $ export FIPDIR=$PWD Go back to the mainline U-Boot source tree then: .. code-block:: bash - $ mkdir fip - $ cp $FIPDIR/bl2.bin fip/ - $ cp $FIPDIR/acs.bin fip/ - $ cp $FIPDIR/bl21.bin fip/ - $ cp $FIPDIR/bl30.bin fip/ - $ cp $FIPDIR/bl301.bin fip/ - $ cp $FIPDIR/bl31.img fip/ - $ cp u-boot.bin fip/bl33.bin + $ mkdir fip + $ cp $FIPDIR/bl2.bin fip/ + $ cp $FIPDIR/acs.bin fip/ + $ cp $FIPDIR/bl21.bin fip/ + $ cp $FIPDIR/bl30.bin fip/ + $ cp $FIPDIR/bl301.bin fip/ + $ cp $FIPDIR/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin - $ $FIPDIR/blx_fix.sh \ - fip/bl30.bin \ - fip/zero_tmp \ - fip/bl30_zero.bin \ - fip/bl301.bin \ - fip/bl301_zero.bin \ - fip/bl30_new.bin \ - bl30 + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 - $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + $ python $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 - $ $FIPDIR/blx_fix.sh \ - fip/bl2_acs.bin \ - fip/zero_tmp \ - fip/bl2_zero.bin \ - fip/bl21.bin \ - fip/bl21_zero.bin \ - fip/bl2_new.bin \ - bl2 + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 - $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin - $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl31.img - $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl33.bin - $ $FIPDIR/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig - $ $FIPDIR/aml_encrypt_gxl --bootmk \ - --output fip/u-boot.bin \ - --bl2 fip/bl2.n.bin.sig \ - --bl30 fip/bl30_new.bin.enc \ - --bl31 fip/bl31.img.enc \ - --bl33 fip/bl33.bin.enc + $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl31.img + $ $FIPDIR/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + $ $FIPDIR/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + $ $FIPDIR/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc Then write U-Boot to SD or eMMC with: .. code-block:: bash - $ DEV=/dev/boot_device - $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 - $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440 + $ DEV=/dev/boot_device + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=440 diff --git a/doc/board/apple/m1.rst b/doc/board/apple/m1.rst index 8fa7637629e..900c5e6d91e 100644 --- a/doc/board/apple/m1.rst +++ b/doc/board/apple/m1.rst @@ -8,21 +8,24 @@ developed by the Asahi Linux project. At this point the machines with the following SoCs work: - Apple M1 SoC (t8103) + - Apple M2 SoC (t8112) - Apple M1 Pro SoC (t6000) - Apple M1 Max SoC (t6001) - Apple M1 Ultra SoC (t6002) + - Apple M2 Pro SoC (t6020) + - Apple M2 Max SoC (t6021) + - Apple M2 Ultra SoC (t6022) On these SoCs the following hardware is supported: - S5L serial port - - SPI keyboard (on laptops) + - SPI keyboard (on M1 laptops) - Framebuffer - NVMe storage - USB 3.1 Type-C ports -Device trees are currently provided for the M1 Mac mini (2020, J274), -M1 MacBook Pro 13" (2020, J293), M1 MacBook Air (2020, J313) and M1 -iMac (2021, J456/J457). +Device trees are provided in dts/upstream/src/arm64/apple/ and available +for all M1 and M2 (t8103, t8112, t600x and t602x) devices. Building U-Boot --------------- @@ -77,7 +80,7 @@ supported SoCs. * - SoC - Base Address - * - M1 (t8103) + * - M1 (t8103) and M2 (t8112) - 0x235200000 - * - M1 Pro/Max/Ultra (t6000/t6001/t6002) + * - M1 Pro/Max/Ultra (t6000/t6001/t6002) and M2 Pro/Max/Ultra (t6020/t6021/t6022) - 0x39b200000 diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst index 1c91c7f3ac6..9e993ca9783 100644 --- a/doc/board/emulation/qemu-arm.rst +++ b/doc/board/emulation/qemu-arm.rst @@ -24,8 +24,78 @@ Additionally, a number of optional peripherals can be added to the PCI bus. See :doc:`../../develop/devicetree/dt_qemu` for information on how to see the devicetree actually generated by QEMU. -Building U-Boot ---------------- +Building (secure) +----------------- + +U-Boot +^^^^^^ + +- For AArch64:: + + make qemu_arm64_defconfig + make + +On successful build 'u-boot.bin' should be created. It's necessary in the following +steps (building TF-A). + +OP-TEE +^^^^^^ + +- For AArch64:: + + git clone https://github.com/OP-TEE/optee_os.git + cd optee_os + git checkout 4.9.0 + export CROSS_COMPILE64=aarch64-none-elf- + export CROSS_COMPILE32=arm-none-eabi- + make PLATFORM=vexpress-qemu_armv8a CFG_TRANSFER_LIST=y CFG_MAP_EXT_DT_SECURE=y + +At least OP-TEE v4.9.0 for AArch64 needs both compiler (64-Bit and 32-Bit edition) for +a successful build. On a successful build following files should be created under the +directory 'out/arm-plat-vexpress/core' from OP-TEE:: + + optee_os/out/arm-plat-vexpress/core/tee-header_v2.bin + optee_os/out/arm-plat-vexpress/core/tee-pageable_v2.bin + optee_os/out/arm-plat-vexpress/core/tee-pager_v2.bin + +TF-A +^^^^ + +- For AArch64:: + + git clone https://github.com/ARM-software/arm-trusted-firmware.git + cd arm-trusted-firmware + git submodule update --init + git checkout v2.14.0 + export CROSS_COMPILE=aarch64-none-elf- + export BL32=path/to/tee-header_v2.bin + export BL32_EXTRA1=path/to/tee-pager_v2.bin + export BL32_EXTRA2=path/to/tee-pageable_v2.bin + export BL33=path/to/u-boot.bin + make PLAT=qemu BL32_RAM_LOCATION=tdram SPD=opteed TRANSFER_LIST=1 all fip + +On successful build the following files should be created under the directory +'build/qemu/release' from TF-A:: + + arm-trusted-firmware/build/qemu/release/bl1.bin + arm-trusted-firmware/build/qemu/release/fip.bin + +The following file is at least created with TF-A v2.14.0 and can be directly passed +with the '-bios' option to QEMU:: + + arm-trusted-firmware/build/qemu/release/qemu_fw.bios + +If the single file ('qemu_fw.bios') doesn't exist, 'bl1.bin' and 'fip.bin' can be +concatenated with the command 'dd' alternatively:: + + dd if=bl1.bin of=qemu_fw.bios bs=4096 conv=notrunc + dd if=fip.bin of=qemu_fw.bios seek=64 bs=4096 conv=notrunc + +Building (non-secure) +--------------------- + +U-Boot +^^^^^^ Set the CROSS_COMPILE environment variable as usual, and run: - For ARM:: @@ -38,8 +108,18 @@ Set the CROSS_COMPILE environment variable as usual, and run: make qemu_arm64_defconfig make -Running U-Boot --------------- +Running U-Boot (secure) +----------------------- + +- For AArch64:: + + qemu-system-aarch64 -machine virt,secure=on,virtualization=on \ + -nographic -cpu cortex-a57 -bios qemu_fw.bios + +For additional QEMU command description see running U-Boot in non-secure state. + +Running U-Boot (non-secure) +--------------------------- The minimal QEMU command line to get U-Boot up and running is: - For ARM:: diff --git a/doc/board/index.rst b/doc/board/index.rst index 7870f1bc246..4103fef8d8f 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -10,6 +10,7 @@ Board-specific doc actions/index advantech/index andestech/index + alliedtelesis/index allwinner/index amlogic/index anbernic/index @@ -71,6 +72,7 @@ Board-specific doc theobroma-systems/index ti/index toradex/index + tq/index variscite/index wexler/index xen/index diff --git a/doc/board/intel/slimbootloader.rst b/doc/board/intel/slimbootloader.rst index 87d71a55bdc..a1d9102859b 100644 --- a/doc/board/intel/slimbootloader.rst +++ b/doc/board/intel/slimbootloader.rst @@ -170,7 +170,7 @@ Build Instruction to use ELF U-Boot $ python BuildLoader.py build <qemu or apl> -p "OsLoader.efi:LLDR:Lz4;u-boot:U-BT:Lzma" -.. _U-Boot: https://source.denx.de/ +.. _U-Boot: https://git.u-boot-project.org/ .. _`Slim Bootloader`: https://github.com/slimbootloader/ .. _`Intel FSP`: https://github.com/IntelFsp/ .. _`Getting Started`: https://slimbootloader.github.io/getting-started/ diff --git a/doc/board/nxp/imx8mq_evk.rst b/doc/board/nxp/imx8mq_evk.rst index 4b0624e7e86..4a9d9e404c5 100644 --- a/doc/board/nxp/imx8mq_evk.rst +++ b/doc/board/nxp/imx8mq_evk.rst @@ -45,11 +45,11 @@ Build U-Boot $ make imx8mq_evk_defconfig $ make -Burn the flash.bin to MicroSD card offset 33KB: +Burn the flash.bin to MicroSD card offset 32KB: .. code-block:: bash - $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=notrunc + $sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc Boot ---- diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 8cd24aecf33..52c8e85fa5b 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -30,3 +30,4 @@ NXP Semiconductors mx6ullevk rproc psb + quickboot diff --git a/doc/board/nxp/quickboot.rst b/doc/board/nxp/quickboot.rst new file mode 100644 index 00000000000..0fd72b4e13b --- /dev/null +++ b/doc/board/nxp/quickboot.rst @@ -0,0 +1,59 @@ +.. SPDX-License-Identifier: GPL-2.0+ + Copyright 2026 NXP + +DDR QuickBoot flow +------------------ + +Some NXP SoCs (which use OEI - iMX943, iMX95, iMX952 etc.) support saving +DDR training data (collected by OEI during Training flow) from volatile +to non-volatile memory, which is then available to OEI at next cold reboot. +OEI uses the saved data to run Quickboot flow and avoid training the DDR again. +This significantly reduces the boot time. + +The location of the quickboot data in NVM is a space left in the bootloader by +mkimage, with the size of 64K. The qb command searches for this space to +save the data. Thus, the NVM should also be a boot device and contain +the bootloader at the time of the saving. + +U-Boot provides no authentication for quickboot data, only its integrity +is verified via the CRC32. The authentication is done in OEI. With +the exception of iMX95 A0/A1, which use CRC32 as well for verifying +the data, the rest of the SoCs use ELE to verify the MAC stored +in the ddrphy_qb_state structure. + +If the quickboot data in memory is not valid (CRC32 check fails), +U-Boot does not save it to NVM. So, if OEI runs Quickboot flow -> no +data is written to volatile memory -> invalid data -> no saving happens +(qb save fails during qb check). + +After successful saving, U-Boot clears the data in volatile memory so +that qb check fails at next reboot and the NVM isn't accessed again. + +There are 2 ways to save this data, both can be enabled: + +1. automatically, in SPL (by enabling CONFIG_SPL_IMX_QB) + +- this will save the data on the current boot device (e.g. SD) +- other configs specific to the boot device need to be enabled (CONFIG_SPL_MMC_WRITE for saving to eMMC/SD) +- use for: automating qb save / saving quickboot data if using Falcon mode (skipping U-Boot proper) + +2. using qb command in U-Boot console (by enabling CONFIG_CMD_IMX_QB) + +- supports saving on the current boot device, or on another, specified device. +- supports specifying the hwpartition for eMMC (for booting from boot0/boot1) +- if flashing via uuu, the command can be added in an uuu script (boot device needs to be specified) +- use 'qb erase' to force DDR re-training +- use for: saving quickboot data during flashing / controlling the NVM to save to / forcing re-training + +:: + + # To save/erase on current boot device + # For eMMC boot1, mmc 0:2 has to be specified explicitly + => qb save/erase + + # To save/erase on other boot device + => qb save/erase mmc 0 # eMMC boot0 + => qb save/erase mmc 0:1 # eMMC boot0 + => qb save/erase mmc 0:2 # eMMC boot1 + => qb save/erase mmc 1 # SD + => qb save/erase spi # NOR SPI diff --git a/doc/board/phytec/k3-common.rst b/doc/board/phytec/k3-common.rst index ffb50b51ad6..3adb176ea8a 100644 --- a/doc/board/phytec/k3-common.rst +++ b/doc/board/phytec/k3-common.rst @@ -1,6 +1,53 @@ .. SPDX-License-Identifier: GPL-2.0+ .. sectionauthor:: Wadim Egorov <[email protected]> +Boot Flow +--------- + +The default `bootcmd` performs three steps: + +.. code-block:: + + run start_watchdog; bootflow scan -lb; run ${boot}boot + +Boot devices are scanned in the order given by `boot_targets`: + +.. code-block:: + + mmc1 mmc0 spi_flash dhcp + +For each device, U-Boot tries the boot methods listed in `bootmeths`: + +.. code-block:: + + [rauc] script efi extlinux pxe + +The `rauc` bootmeth is only present when `CONFIG_BOOTMETH_RAUC=y` is set in +the A53 defconfig. RAUC slot selection is handled entirely by the bootmeth; +no environment-side configuration is required. + +The legacy `${boot}boot` chain (`mmcboot`, `spiboot`, `netboot`) is kept for +backwards compatibility and prints a deprecation warning when run. New +deployments should rely on the standard boot mechanism (`bootflow`) only. + + +Watchdog +-------- + +`bootcmd` runs `start_watchdog` before starting the boot flow. When +`CONFIG_WATCHDOG_TIMEOUT_MSECS` is set to a non-zero value and the +`watchdog` environment variable points to a watchdog device, U-Boot enables +the watchdog with that timeout. + +After this point the OS is responsible for servicing the watchdog. If it +does not feed the watchdog before the timeout expires, the SoC will reset. +Make sure the watchdog driver is enabled and configured in the kernel and +userspace before relying on this. + +To skip the watchdog start, either build with `CONFIG_WATCHDOG_TIMEOUT_MSECS=0` +or set `watchdog_timeout_ms=0` in the environment. + + Environment ----------- diff --git a/doc/board/phytec/phycore-am62ax.rst b/doc/board/phytec/phycore-am62ax.rst index e1f741011e7..aa3518a07ff 100644 --- a/doc/board/phytec/phycore-am62ax.rst +++ b/doc/board/phytec/phycore-am62ax.rst @@ -9,7 +9,7 @@ SoM (System on Module) featuring TI's AM62Ax SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62Ax family. -A development Kit, called `phyBOARD-Lyra <https://www.phytec.com/product/phyboard-am62x>`_ +A development Kit, called `phyBOARD-Lyra <https://www.phytec.com/product/phyboard-am62a>`_ is used as a carrier board reference design around the AM62Ax SoM. Quickstart @@ -57,10 +57,10 @@ Set the variables corresponding to this platform: $ export UBOOT_CFG_CORTEXR=phycore_am62ax_r5_defconfig $ export UBOOT_CFG_CORTEXA=phycore_am62ax_a53_defconfig $ export TFA_BOARD=lite - $ # we dont use any extra TFA parameters + $ # we don't use any extra TFA parameters $ unset TFA_EXTRA_ARGS $ export OPTEE_PLATFORM=k3-am62ax - $ # we dont use any extra OPTEE parameters + $ # we don't use any extra OPTEE parameters $ unset OPTEE_EXTRA_ARGS 1. Trusted Firmware-A: @@ -147,7 +147,7 @@ the main domain serial port: Boot Modes ---------- -The phyCORE-AM62x development kit supports booting from many different +The phyCORE-AM62Ax development kit supports booting from many different interfaces. By default, the development kit is set to boot from the micro-SD card. To change the boot device, DIP switches S5 and S6 can be used. Boot switches should be changed with power off. diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index bd61d0c16cf..5349ba429d4 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -60,7 +60,7 @@ Set the variables corresponding to this platform: $ # we don't use any extra TFA parameters $ unset TFA_EXTRA_ARGS $ export OPTEE_PLATFORM=k3-am62x - $ # we dont use any extra OPTEE parameters + $ # we don't use any extra OPTEE parameters $ unset OPTEE_EXTRA_ARGS .. include:: ../ti/am62x_sk.rst @@ -177,6 +177,25 @@ Boot switches should be changed with power off. - 11001010 - 00100000 +DDR RAM Size +------------ + +By default, the R5 SPL detects the populated DDR size by reading the SoM +EEPROM and configures the DDR controller and the U-Boot device-tree memory +node accordingly. The phyCORE-AM62x is available with 1 GB, 2 GB, or 4 GB of +DDR. If the EEPROM cannot be read or is invalid, the SPL falls back to a +2 GB configuration. + +EEPROM-based detection can be bypassed by enabling +`CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX` in the R5 defconfig and selecting one of: + +* `CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB` +* `CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB` +* `CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB` + +This is mainly useful if no detection is needed or for boards without a +populated SoM EEPROM. + .. include:: k3-common.rst Further Information diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst index 71f1fd7b404..20887d443a9 100644 --- a/doc/board/phytec/phycore-am64x.rst +++ b/doc/board/phytec/phycore-am64x.rst @@ -60,8 +60,8 @@ Set the variables corresponding to this platform: $ # we don't use any extra TFA parameters $ unset TFA_EXTRA_ARGS $ export OPTEE_PLATFORM=k3-am64x - # we don't use any extra OPTEE parameters - unset OPTEE_EXTRA_ARGS + $ # we don't use any extra OPTEE parameters + $ unset OPTEE_EXTRA_ARGS .. include:: ../ti/am62x_sk.rst :start-after: .. am62x_evm_rst_include_start_build_steps @@ -148,7 +148,7 @@ Boot Modes The phyCORE-AM64x development kit supports booting from many different interfaces. By default, the development kit is set to boot from the micro-SD -card. To change the boot device, DIP switches S5 and S6 can be used. +card. To change the boot device, DIP switches SW3 and SW4 can be used. Boot switches should be changed with power off. .. list-table:: Boot Modes @@ -175,6 +175,24 @@ Boot switches should be changed with power off. - 11011100 - 00000000 +DDR RAM Size +------------ + +By default, the R5 SPL detects the populated DDR size by reading the SoM +EEPROM and configures the DDR controller and the U-Boot device-tree memory +node accordingly. The phyCORE-AM64x is available with 1 GB or 2 GB of DDR. +If the EEPROM cannot be read or is invalid, the SPL falls back to a 2 GB +configuration. + +EEPROM-based detection can be bypassed by enabling +`CONFIG_PHYCORE_AM64X_RAM_SIZE_FIX` in the R5 defconfig and selecting one of: + +* `CONFIG_PHYCORE_AM64X_RAM_SIZE_1GB` +* `CONFIG_PHYCORE_AM64X_RAM_SIZE_2GB` + +This is mainly useful if no detection is needed or for boards without a +populated SoM EEPROM. + .. include:: k3-common.rst Further Information diff --git a/doc/board/renesas/build-env-aarch32.rst b/doc/board/renesas/build-env-aarch32.rst new file mode 100644 index 00000000000..5120a042ccb --- /dev/null +++ b/doc/board/renesas/build-env-aarch32.rst @@ -0,0 +1,25 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas 32-bit ARM SoC build environment setup +============================================== + +In order to cross-compile U-Boot for the ARM 32-bit target, it is necessary +to install a suitable toolchain. The toolchain is available in various +distribution repositories as ``arm-linux-gnueabi-*`` or similar package. + +Debian example: + +.. code-block:: console + + $ apt install binutils-arm-linux-gnueabi cpp-arm-linux-gnueabi gcc-arm-linux-gnueabi + +Alternatively, it is possible to download prebuilt toolchain from +kernel.org cross-development toolchains page +https://www.kernel.org/pub/tools/crosstool/ . + +Once the toolchain is installed, add toolchain into ``PATH`` variable: + +.. code-block:: console + + $ export PATH=$PATH:<path/to/arm32/toolchain/bin/> + $ export CROSS_COMPILE=arm-linux-gnueabi- diff --git a/doc/board/renesas/build-env-aarch64.rst b/doc/board/renesas/build-env-aarch64.rst new file mode 100644 index 00000000000..979b599e951 --- /dev/null +++ b/doc/board/renesas/build-env-aarch64.rst @@ -0,0 +1,25 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas 64-bit ARM SoC build environment setup +============================================== + +In order to cross-compile U-Boot for the aarch64 target, it is necessary +to install a suitable toolchain. The toolchain is available in various +distribution repositories as ``aarch64-linux-gnu-*`` or similar package. + +Debian example: + +.. code-block:: console + + $ apt install binutils-aarch64-linux-gnu cpp-aarch64-linux-gnu gcc-aarch64-linux-gnu + +Alternatively, it is possible to download prebuilt toolchain from +kernel.org cross-development toolchains page +https://www.kernel.org/pub/tools/crosstool/ . + +Once the toolchain is installed, add toolchain into ``PATH`` variable: + +.. code-block:: console + + $ export PATH=$PATH:<path/to/arm64/toolchain/bin/> + $ export CROSS_COMPILE=aarch64-linux-gnu- diff --git a/doc/board/renesas/build-env-sh.rst b/doc/board/renesas/build-env-sh.rst new file mode 100644 index 00000000000..52f5cff8198 --- /dev/null +++ b/doc/board/renesas/build-env-sh.rst @@ -0,0 +1,25 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas 32-bit SH4 SoC build environment setup +============================================== + +In order to cross-compile U-Boot for the SH4 32-bit target, it is necessary +to install a suitable toolchain. The toolchain is available in various +distribution repositories as ``sh4-linux-gnu-*`` or similar package. + +Debian example: + +.. code-block:: console + + $ apt install binutils-sh4-linux-gnu cpp-sh4-linux-gnu gcc-sh4-linux-gnu + +Alternatively, it is possible to download prebuilt toolchain from +kernel.org cross-development toolchains page +https://www.kernel.org/pub/tools/crosstool/ . + +Once the toolchain is installed, add toolchain into ``PATH`` variable: + +.. code-block:: console + + $ export PATH=$PATH:<path/to/sh4/toolchain/bin/> + $ export CROSS_COMPILE=sh4-linux-gnu- diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst index fb6558ec11b..be932aa01fb 100644 --- a/doc/board/renesas/index.rst +++ b/doc/board/renesas/index.rst @@ -7,4 +7,17 @@ Renesas :maxdepth: 2 renesas + build-env-sh + build-env-aarch32 + build-env-aarch64 + rcar-gen3-salvator-x + rcar-gen3-ulcb + rcar-gen3-geist + rcar-gen3-ebisu + rcar-gen3-draak + rcar-gen3-install + rcar-gen3-install-hf + rcar-gen3-install-sf + rcar-gen4-sparrow-hawk + rcar-gen5-ironhide rzn1 diff --git a/doc/board/renesas/rcar-gen3-draak.rst b/doc/board/renesas/rcar-gen3-draak.rst new file mode 100644 index 00000000000..7b94eaa4b23 --- /dev/null +++ b/doc/board/renesas/rcar-gen3-draak.rst @@ -0,0 +1,47 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas R-Car Gen3 D3 Draak board +================================= + +- Renesas R-Car D3 Draak board: https://elinux.org/R-Car/Boards/Draak + +Build U-Boot +------------ + +Please follow :doc:`Renesas 64-bit ARM SoC build environment setup <build-env-aarch64>` +to correctly set up the build environment before attempting to build U-Boot. + +Clone up to date U-Boot source code and change directory into the +newly cloned source directory: + +.. code-block:: console + + $ git clone https://source.denx.de/u-boot/u-boot.git/ + $ cd u-boot + +Configure U-Boot: + +.. code-block:: console + + $ make r8a77995_draak_defconfig + +Compile U-Boot: + +.. code-block:: console + + $ make + +To speed up build process, -jN option can be passed to make to start +multiple jobs at the same time, this is beneficial especially on SMP +systems. The following example starts up to number of CPUs in the +system jobs, which is the recommended amount: + +.. code-block:: console + + $ make -j$(nproc) + +Install U-Boot +-------------- + +Please follow :doc:`Renesas R-Car Gen3 U-Boot installation <rcar-gen3-install>` +to install U-Boot into HyperFlash. diff --git a/doc/board/renesas/rcar-gen3-ebisu.rst b/doc/board/renesas/rcar-gen3-ebisu.rst new file mode 100644 index 00000000000..f9632705abc --- /dev/null +++ b/doc/board/renesas/rcar-gen3-ebisu.rst @@ -0,0 +1,47 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas R-Car Gen3 E3 Ebisu board +================================= + +- Renesas R-Car E3 Ebisu board: https://elinux.org/R-Car/Boards/Ebisu + +Build U-Boot +------------ + +Please follow :doc:`Renesas 64-bit ARM SoC build environment setup <build-env-aarch64>` +to correctly set up the build environment before attempting to build U-Boot. + +Clone up to date U-Boot source code and change directory into the +newly cloned source directory: + +.. code-block:: console + + $ git clone https://source.denx.de/u-boot/u-boot.git/ + $ cd u-boot + +Configure U-Boot: + +.. code-block:: console + + $ make r8a77990_ebisu_defconfig + +Compile U-Boot: + +.. code-block:: console + + $ make + +To speed up build process, -jN option can be passed to make to start +multiple jobs at the same time, this is beneficial especially on SMP +systems. The following example starts up to number of CPUs in the +system jobs, which is the recommended amount: + +.. code-block:: console + + $ make -j$(nproc) + +Install U-Boot +-------------- + +Please follow :doc:`Renesas R-Car Gen3 U-Boot installation <rcar-gen3-install>` +to install U-Boot into HyperFlash. diff --git a/doc/board/renesas/rcar-gen3-geist.rst b/doc/board/renesas/rcar-gen3-geist.rst new file mode 100644 index 00000000000..7bedb3a79cb --- /dev/null +++ b/doc/board/renesas/rcar-gen3-geist.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas R-Car Gen3 M3Le Geist board +=================================== + +Build U-Boot +------------ + +Please follow :doc:`Renesas 64-bit ARM SoC build environment setup <build-env-aarch64>` +to correctly set up the build environment before attempting to build U-Boot. + +Clone up to date U-Boot source code and change directory into the +newly cloned source directory: + +.. code-block:: console + + $ git clone https://source.denx.de/u-boot/u-boot.git/ + $ cd u-boot + +Configure U-Boot: + +.. code-block:: console + + $ make r8a779md_geist_defconfig + +Compile U-Boot: + +.. code-block:: console + + $ make + +To speed up build process, -jN option can be passed to make to start +multiple jobs at the same time, this is beneficial especially on SMP +systems. The following example starts up to number of CPUs in the +system jobs, which is the recommended amount: + +.. code-block:: console + + $ make -j$(nproc) + +Install U-Boot +-------------- + +Please follow :doc:`Renesas R-Car Gen3 U-Boot installation <rcar-gen3-install>` +to install U-Boot into SPI NOR. diff --git a/doc/board/renesas/rcar-gen3-install-hf.rst b/doc/board/renesas/rcar-gen3-install-hf.rst new file mode 100644 index 00000000000..d3a753eb2eb --- /dev/null +++ b/doc/board/renesas/rcar-gen3-install-hf.rst @@ -0,0 +1,76 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas R-Car Gen3 U-Boot HyperFlash installation +================================================= + +U-Boot can be installed on R-Car Gen3 systems into HyperFlash from U-Boot. + +.. note:: + + This update mechanism is only available in case the TFA has been built + with `RCAR_RPC_HYPERFLASH_LOCKED=0`. + +Install U-Boot into HyperFlash using NOR write from U-Boot +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In order to install U-Boot using write into HyperFlash, first build U-Boot +for this target and collect ``u-boot.bin`` build artifact. Then start the +target, drop into U-Boot shell, and load the build artifact into DRAM at +well known address: + +.. code-block:: console + + => tftp 0x50000000 u-boot.bin + +Finally, write U-Boot into HyperFlash: + +.. code-block:: console + + => erase 0x8640000 +${filesize} && cp.w 0x50000000 0x8640000 0x80000 + +.. note:: + + The `cp.w` size parameter is in 16-bit short word units, not in Bytes. + The `cp.w` size parameter size in Bytes would be 0x100000 . + +Install U-Boot into HyperFlash using dfu_tftp update from U-Boot +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In order to install U-Boot using dfu_tftp update, first build U-Boot for +this target and collect ``u-boot.bin`` build artifact. Then bundle this +``u-boot.bin`` into an update fitImage using the following fitImage source +file. The update fitImage source file is named ``update.its`` in this example: + +.. code-block:: dts + + // update.its + /dts-v1/; + + / { + description = "Update fitImage for U-Boot"; + + images { + bootparam { + description = "U-Boot"; + data = /incbin/("u-boot.bin"); + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <0x8640000>; + }; + }; + }; + +Generate the update fitImage using the following command: + +.. code-block:: console + + $ mkimage -f update.its update.itb + +Then start the target, drop into U-Boot shell, and load the ``update.itb`` +artifact into DRAM at well known address: + +.. code-block:: console + + => tftp 0x50000000 update.itb && dfu tftp 0x50000000 diff --git a/doc/board/renesas/rcar-gen3-install-sf.rst b/doc/board/renesas/rcar-gen3-install-sf.rst new file mode 100644 index 00000000000..4e8667e1b48 --- /dev/null +++ b/doc/board/renesas/rcar-gen3-install-sf.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas R-Car Gen3 U-Boot SPI NOR installation +============================================== + +U-Boot can be installed on R-Car Gen3 systems into SPI NOR from U-Boot. + +.. note:: + + This update mechanism is only available in case the TFA has been built + with `RCAR_RPC_HYPERFLASH_LOCKED=0 SPD=none`. + +Install U-Boot into SPI NOR using write from U-Boot +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In order to install U-Boot using write into SPI NOR, first build U-Boot +for this target and collect ``u-boot.bin`` build artifact. Then start the +target, drop into U-Boot shell, and load the build artifact into DRAM at +well known address: + +.. code-block:: console + + => tftp 0x50000000 u-boot.bin + +Finally, write U-Boot into SPI NOR: + +.. code-block:: console + + => sf probe && sf update 0x50000000 0x640000 $filesize diff --git a/doc/board/renesas/rcar-gen3-install.rst b/doc/board/renesas/rcar-gen3-install.rst new file mode 100644 index 00000000000..33189d9227b --- /dev/null +++ b/doc/board/renesas/rcar-gen3-install.rst @@ -0,0 +1,34 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas R-Car Gen3 U-Boot installation +====================================== + +U-Boot can be installed on R-Car Gen3 systems in multiple ways. + +The generic installation method, which also requires physical hardware +access, is to install U-Boot using the `flash_writer`_ tool. This +procedure is documented below. + +Installation into the HyperFlash can be performed from U-Boot, please +refer to :doc:`Renesas R-Car Gen3 U-Boot HyperFlash installation <rcar-gen3-install-hf>` +for details. + +Installation into the SPI NOR can be performed from U-Boot, please +refer to :doc:`Renesas R-Car Gen3 U-Boot SPI NOR installation <rcar-gen3-install-sf>` +for details. + +.. note:: + + The maximum u-boot.bin size for this target is 1 MiB or 0x100000 Bytes + +Install U-Boot using flash_writer tool +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In order to install U-Boot using flash_writer tool, first build U-Boot +for this target and collect ``u-boot-elf.srec`` build artifact. Then +follow the `application note`_ shipped together with the flash_writer +tool to install the ``u-boot-elf.srec`` artifact using `XLS2 command`_. + +.. _`flash_writer`: https://github.com/renesas-rcar/flash_writer +.. _`application note`: https://github.com/renesas-rcar/flash_writer/blob/rcar_gen3/docs/application-note.md +.. _`XLS2 command`: https://github.com/renesas-rcar/flash_writer/blob/rcar_gen3/docs/application-note.md#341-write-to-the-s-record-format-images-to-the-serial-flash diff --git a/doc/board/renesas/rcar-gen3-salvator-x.rst b/doc/board/renesas/rcar-gen3-salvator-x.rst new file mode 100644 index 00000000000..37f009452e5 --- /dev/null +++ b/doc/board/renesas/rcar-gen3-salvator-x.rst @@ -0,0 +1,48 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas R-Car Gen3 H3/M3-W/M3-N Salvator-X(S) board +=================================================== + +- Renesas R-Car Gen3 Salvator-X board: https://elinux.org/R-Car/Boards/Salvator-X +- Renesas R-Car Gen3 Salvator-XS board: https://elinux.org/R-Car/Boards/Salvator-XS + +Build U-Boot +------------ + +Please follow :doc:`Renesas 64-bit ARM SoC build environment setup <build-env-aarch64>` +to correctly set up the build environment before attempting to build U-Boot. + +Clone up to date U-Boot source code and change directory into the +newly cloned source directory: + +.. code-block:: console + + $ git clone https://source.denx.de/u-boot/u-boot.git/ + $ cd u-boot + +Configure U-Boot: + +.. code-block:: console + + $ make rcar3_salvator-x_defconfig + +Compile U-Boot: + +.. code-block:: console + + $ make + +To speed up build process, -jN option can be passed to make to start +multiple jobs at the same time, this is beneficial especially on SMP +systems. The following example starts up to number of CPUs in the +system jobs, which is the recommended amount: + +.. code-block:: console + + $ make -j$(nproc) + +Install U-Boot +-------------- + +Please follow :doc:`Renesas R-Car Gen3 U-Boot installation <rcar-gen3-install>` +to install U-Boot into HyperFlash. diff --git a/doc/board/renesas/rcar-gen3-ulcb.rst b/doc/board/renesas/rcar-gen3-ulcb.rst new file mode 100644 index 00000000000..88ec2276a36 --- /dev/null +++ b/doc/board/renesas/rcar-gen3-ulcb.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas R-Car Gen3 H3/M3-W/M3-N ULCB board +========================================== + +- Renesas R-Car H3 ULCB board: https://elinux.org/R-Car/Boards/H3SK +- Renesas R-Car M3-W ULCB board: https://elinux.org/R-Car/Boards/M3SK +- Renesas R-Car M3-N ULCB board: https://elinux.org/R-Car/Boards/M3NSK + +Build U-Boot +------------ + +Please follow :doc:`Renesas 64-bit ARM SoC build environment setup <build-env-aarch64>` +to correctly set up the build environment before attempting to build U-Boot. + +Clone up to date U-Boot source code and change directory into the +newly cloned source directory: + +.. code-block:: console + + $ git clone https://source.denx.de/u-boot/u-boot.git/ + $ cd u-boot + +Configure U-Boot: + +.. code-block:: console + + $ make rcar3_ulcb_defconfig + +Compile U-Boot: + +.. code-block:: console + + $ make + +To speed up build process, -jN option can be passed to make to start +multiple jobs at the same time, this is beneficial especially on SMP +systems. The following example starts up to number of CPUs in the +system jobs, which is the recommended amount: + +.. code-block:: console + + $ make -j$(nproc) + +Install U-Boot +-------------- + +Please follow :doc:`Renesas R-Car Gen3 U-Boot installation <rcar-gen3-install>` +to install U-Boot into HyperFlash. diff --git a/doc/board/renesas/rcar-gen4-sparrow-hawk.rst b/doc/board/renesas/rcar-gen4-sparrow-hawk.rst new file mode 100644 index 00000000000..a1b92ecab57 --- /dev/null +++ b/doc/board/renesas/rcar-gen4-sparrow-hawk.rst @@ -0,0 +1,91 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Retronix R-Car Gen4 V4H Sparrow Hawk board +========================================== + +- Retronix R-Car V4H Sparrow Hawk board: https://www.retronix.com.tw/en/product_sbc.html +- Retronix R-Car V4H Sparrow Hawk documenation: https://rcar-community.github.io/Sparrow-Hawk/index.html + +Build U-Boot +------------ + +Please follow :doc:`Renesas 64-bit ARM SoC build environment setup <build-env-aarch64>` +to correctly set up the build environment before attempting to build U-Boot. + +Clone up to date U-Boot source code and change directory into the +newly cloned source directory: + +.. code-block:: console + + $ git clone https://source.denx.de/u-boot/u-boot.git/ + $ cd u-boot + +Configure U-Boot: + +.. code-block:: console + + $ make r8a779g3_sparrowhawk_defconfig + +Compile U-Boot: + +.. code-block:: console + + $ make + +To speed up build process, -jN option can be passed to make to start +multiple jobs at the same time, this is beneficial especially on SMP +systems. The following example starts up to number of CPUs in the +system jobs, which is the recommended amount: + +.. code-block:: console + + $ make -j$(nproc) + +Install U-Boot +-------------- + +In order to install U-Boot using write into SPI NOR, first build U-Boot +for this target and collect ``flash.bin`` build artifact. Then start the +target, drop into U-Boot shell, and load the build artifact into DRAM at +well known address: + +.. code-block:: console + + => tftp 0x50000000 flash.bin + +Finally, write U-Boot into SPI NOR: + +.. code-block:: console + + => sf probe && sf update 0x50000000 0 ${filesize} + +Bundle TFA BL31 into Linux kernel fitImage +------------------------------------------ + +The Retronix R-Car V4H Sparrow Hawk board starts both TFA BL31 and Linux +kernel from U-Boot. Both TFA BL31, Linux kernel and DT blob have to be +bundled into the fitImage. + +Perform the following steps to build TFA at least v2.14.y: + +.. code-block:: console + + $ git clone https://github.com/ARM-software/arm-trusted-firmware.git + $ cd arm-trusted-firmware + $ make -j$(nproc) bl31 \ + PLAT=rcar_gen4 ARCH=aarch64 LSI=V4H SPD=none \ + CTX_INCLUDE_AARCH32_REGS=0 MBEDTLS_COMMON_MK=1 \ + PTP_NONSECURE_ACCESS=1 LOG_LEVEL=20 DEBUG=0 \ + ENABLE_ASSERTIONS=0 + +The bundling is done using U-Boot ``mkimage`` tool: + +.. code-block:: console + + mkimage \ + -f auto -E -A arm64 -C none -e 0x50200000 -a 0x50200000 \ + -d /path/to/linux/arch/arm64/boot/Image \ + -b /path/to/linux/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dtb \ + -y /path/to/arm-trusted-firmware/build/rcar_gen4/*/bl31.bin \ + -Y 0x46400000 \ + /path/to/output/fitImage diff --git a/doc/board/renesas/rcar-gen5-ironhide.rst b/doc/board/renesas/rcar-gen5-ironhide.rst new file mode 100644 index 00000000000..39fbfdbfe00 --- /dev/null +++ b/doc/board/renesas/rcar-gen5-ironhide.rst @@ -0,0 +1,204 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas R-Car Gen5 X5H Ironhide board +===================================== + +Renesas R-Car Gen5 X5H Ironhide board U-Boot can be built for two separate cores: + +- Cortex-M33 RSIP core, which is the boot core +- Cortex-A720AE core, which is the application core + +Cortex-A720AE target +^^^^^^^^^^^^^^^^^^^^ + +Build U-Boot +------------ + +Please follow :doc:`Renesas 64-bit ARM SoC build environment setup <build-env-aarch64>` +to correctly set up the build environment before attempting to build U-Boot. + +Clone up to date U-Boot source code and change directory into the +newly cloned source directory: + +.. code-block:: console + + $ git clone https://source.denx.de/u-boot/u-boot.git/ + $ cd u-boot + +Configure U-Boot: + +.. code-block:: console + + $ make r8a78000_ironhide_defconfig + +Compile U-Boot: + +.. code-block:: console + + $ make + +To speed up build process, -jN option can be passed to make to start +multiple jobs at the same time, this is beneficial especially on SMP +systems. The following example starts up to number of CPUs in the +system jobs, which is the recommended amount: + +.. code-block:: console + + $ make -j$(nproc) + +Install U-Boot +-------------- + +In order to install U-Boot for Cortex-A720AE into UFS, first build U-Boot +for this target and collect ``u-boot-elf.srec`` build artifact. + +Next, configure the board for SCIF loader boot. Upload IPL flash_writer +mot binary. Use the tool to write ``u-boot-elf.srec`` into HyperFlash +at offset 0x8e300000 . Finally, power off the board and configure the +board back to HyperFlash boot mode. + +Cortex-M33 RSIP target +^^^^^^^^^^^^^^^^^^^^^^ + +Build U-Boot +------------ + +Please follow :doc:`Renesas 32-bit ARM SoC build environment setup <build-env-aarch32>` +to correctly set up the build environment before attempting to build U-Boot. + +Clone up to date U-Boot source code and change directory into the +newly cloned source directory: + +.. code-block:: console + + $ git clone https://source.denx.de/u-boot/u-boot.git/ + $ cd u-boot + +Configure U-Boot: + +.. code-block:: console + + $ make r8a78000_ironhide_cm33_defconfig + +Compile U-Boot: + +.. code-block:: console + + $ make + +To speed up build process, -jN option can be passed to make to start +multiple jobs at the same time, this is beneficial especially on SMP +systems. The following example starts up to number of CPUs in the +system jobs, which is the recommended amount: + +.. code-block:: console + + $ make -j$(nproc) + +Install U-Boot +-------------- + +In order to install U-Boot for RSIP into HyperFlash, first build U-Boot +for this target and collect ``u-boot-elf.shdr`` and ``u-boot-elf.srec`` +build artifacts. + +Next, configure the board for SCIF loader boot. Upload IPL flash_writer +mot binary. Use the tool to write ``u-boot-elf.shdr`` into HyperFlash +at offset 0, and ``u-boot-elf.srec`` into HyperFlash at offset 0x40000 . +Finally, power off the board and configure the board back to HyperFlash +boot mode. + +Power on the board, U-Boot on RSIP will start. Interaction with U-Boot +on RSIP is possible via HSCIF1, which is the second serial console that +is available on the USB-to-Serial adapter port. HSCIF1 is used in order +to avoid interference with software running on the Cortex-A720AE cores, +which uses HSCIF0. + +Ethernet boot of bootloader components +-------------------------------------- + +The U-Boot for RSIP is capable of ethernet access, which allows download +of bootloader components via TFTP. This is useful during development and +can be used for fast iterative testing of either SCP firmware, TFA BL31, +OPTEE-OS, U-Boot or Linux on the SCP core and Cortex-A720AE cores +respectively. + +An example U-Boot environment applicable to ``include/configs/rcar-gen5-common.h`` +or executable manually is listed below. The environment script ``rsip_ipl_boot_ca0`` +implements download of SCP firmware ``scp.bin``, TFA BL31 ``bl31.bin``, +U-Boot ``u-boot.bin`` and Linux ``fitImage`` from TFTP server at address +``192.168.1.1/24`` and starts those components on the SCP and Cortex-A720AE +cores respectively. OPTEE-OS is loaded from UFS to retain at least this +example of UFS loading, however, it perfectly fine to download OPTEE-OS +via TFTP in the same manner as the other components are downloaded: + +.. code-block:: console + + rsip_ipl_params_base=0x8c100000 + rsip_ipl_params_optee=0x8c100088 + rsip_ipl_params_uboot=0x8c100030 + rsip_ipl_scp_ep=0x8c180000 + rsip_ipl_optee_ep=0x8c400000 + rsip_ipl_tfa_ep=0x8c200000 + rsip_ipl_uboot_ep=0x8e300000 + rsip_ipl_linux_ep=0x91000000 + + rsip_ipl_params_write= /* Build handoff structure */ \ + base ${rsip_ipl_params_base} ; \ + mw 0x00 0 0x9e ; /* Clear the area */ \ + mw 0x00 0x00300103 ; /* type, version, size */ \ + mw 0x20 0x${rsip_ipl_params_uboot} ; /* U-Boot descriptor */ \ + \ + base ${rsip_ipl_params_uboot} ; \ + mw 0x00 0x00580101 ; /* type, version, size */ \ + mw 0x04 0x00000001 ; /* attr */ \ + mw 0x08 ${rsip_ipl_uboot_ep} ; /* U-Boot entry point */ \ + mw 0x10 0x000003c5 ; /* SPSR */ \ + \ + base ${rsip_ipl_params_optee} ; \ + mw 0x00 0x00580201 ; /* type, version, size */ \ + mw 0x04 0x00000008 ; /* attr */ \ + mw 0x08 ${rsip_ipl_optee_ep} ; /* OPTEE-OS entry point */ \ + mw 0x10 0x000003c5 ; /* SPSR */ \ + \ + base 0 + + rsip_ipl_boot_ca0= /* Start TFA BL31, OPTEE-OS, U-Boot, Linux on Cortex-A720AE core 0 */ \ + setenv ipaddr 192.168.1.10 && \ + setenv serverip 192.168.1.1 && \ + setenv netmask 255.255.255.0 && \ + \ + tftp ${rsip_ipl_scp_ep} scp.bin && \ + tftp ${rsip_ipl_tfa_ep} bl31.bin && \ + tftp ${rsip_ipl_uboot_ep} u-boot.bin && \ + tftp ${rsip_ipl_linux_ep} fitImage && \ + \ + scsi scan && /* Scan for UFS devices */ \ + rproc init && /* Start remoteproc */ \ + rproc load 0 ${rsip_ipl_scp_ep} 0x60000 && /* Load SCP STCM */ \ + rproc start 0 && /* Start SCP */ \ + scsi read ${rsip_ipl_optee_ep} 0x5200 0x200 && /* Load OPTEE-OS from UFS */ \ + run rsip_ipl_params_write && /* Write entry point descriptors */ \ + \ + rproc load 13 ${rsip_ipl_tfa_ep} 4 && /* Set up Cortex-A720AE Core 0 */ \ + rproc start 13 /* Start Cortex-A720AE Core 0 */ + + +.. note:: + + U-Boot on RSIP environment is not persistent across reboots, + but this will likely change in the upcoming U-Boot release. + +.. note:: + + U-Boot on RSIP can start the SCP core via rproc command, but + it can not stop SCP after it was started. This was intended + as a safety mechanism, since SCP is central component of the + system, however, this will likely change in the upcoming U-Boot + release. + +.. note:: + + U-Boot on RSIP can start non-SCP cores via ``rproc`` command only + after the SCP got started, because those cores are started via + SCMI calls to the SCP. diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst index fedfeed42e3..c0cefc15dd8 100644 --- a/doc/board/renesas/renesas.rst +++ b/doc/board/renesas/renesas.rst @@ -14,237 +14,104 @@ Renesas SoC based boards Renesas is a SoC solutions provider for automotive and industrial applications. -.. list-table:: Supported Renesas SoC based boards - :widths: 10, 25, 15, 10, 25 - :header-rows: 1 +.. table:: Supported Renesas SoC based boards - * - Family - - Board - - SoC - - Arch - - defconfig + +--------+------------------+----------------------------------+--------------------+--------------------+----------------------------------------------+----------------------------------+ + | Family | Generation | Architecture | SoC | Core | Board | defconfig | + +========+==================+==================================+====================+====================+==============================================+==================================+ + | R2D | | :doc:`SH <build-env-sh>` | SH7751 | SH4 | R2D-PLUS | r2dplus_defconfig | + +--------+------------------+----------------------------------+--------------------+--------------------+----------------------------------------------+----------------------------------+ + | R-Car | | | | | Lager | lager_defconfig | + | | | | R8A7790 (H2) | Cortex A7 or A15 +----------------------------------------------+----------------------------------+ + | | | | | | Stout | stout_defconfig | + | | | +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | | | Koelsch | koelsch_defconfig | + | | | | R8A7791 (M2-W) | +----------------------------------------------+----------------------------------+ + | | | | | Cortex A15 | Porter | porter_defconfig | + | | Gen2 | :doc:`arm <build-env-aarch32>` +--------------------+ +----------------------------------------------+----------------------------------+ + | | | | R8A7792 (V2H) | | Blanche | blanche_defconfig | + | | | +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | R8A7793 (M2-N) | Cortex A7 or A15 | Gose | gose_defconfig | + | | | +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | | | Alt | alt_defconfig | + | | | | R8A7794 (E2) | Cortex A7 +----------------------------------------------+----------------------------------+ + | | | | | | Silk | silk_defconfig | + | +------------------+----------------------------------+--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | | | :doc:`Salvator-X(S) <rcar-gen3-salvator-x>` | rcar3_salvator-x_defconfig | + | | | | R8A77951 (H3) | +----------------------------------------------+----------------------------------+ + | | | | | | :doc:`ULCB <rcar-gen3-ulcb>` | rcar3_ulcb_defconfig | + | | | +--------------------+ +----------------------------------------------+----------------------------------+ + | | | | | | :doc:`Salvator-X(S) <rcar-gen3-salvator-x>` | rcar3_salvator-x_defconfig | + | | | | R8A77960 (M3-W) | Cortex A53 or A57 +----------------------------------------------+----------------------------------+ + | | | | | | :doc:`ULCB <rcar-gen3-ulcb>` | rcar3_ulcb_defconfig | + | | | +--------------------+ +----------------------------------------------+----------------------------------+ + | | | | | | :doc:`Salvator-X(S) <rcar-gen3-salvator-x>` | rcar3_salvator-x_defconfig | + | | | | R8A77965 (M3-N) | +----------------------------------------------+----------------------------------+ + | | | | | | :doc:`ULCB <rcar-gen3-ulcb>` | rcar3_ulcb_defconfig | + | | | +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | Gen3 | :doc:`arm64 <build-env-aarch64>` | R8A779MD (M3Le) | Cortex A57 | :doc:`Geist <rcar-gen3-geist>` | r8a779md_geist_defconfig | + | | | +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | | | Eagle | r8a77970_eagle_defconfig | + | | | | R8A77970 (V3M) | +----------------------------------------------+----------------------------------+ + | | | | | | V3MSK | r8a77970_v3msk_defconfig | + | | | +--------------------+ +----------------------------------------------+----------------------------------+ + | | | | | | Condor | r8a77980_condor_defconfig | + | | | | R8A77980 (V3H) | Cortex A53 +----------------------------------------------+----------------------------------+ + | | | | | | V3HSK | r8a77980_v3hsk_defconfig | + | | | +--------------------+ +----------------------------------------------+----------------------------------+ + | | | | R8A77990 (E3) | | :doc:`Ebisu <rcar-gen3-ebisu>` | r8a77990_ebisu_defconfig | + | | | +--------------------+ +----------------------------------------------+----------------------------------+ + | | | | R8A77995 (D3) | | :doc:`Draak <rcar-gen3-draak>` | r8a77995_draak_defconfig | + | +------------------+----------------------------------+--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | R8A779A0 (V3U) | Cortex A76 | Falcon | r8a779a0_falcon_defconfig | + | | | +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | | | Spider | r8a779f0_spider_defconfig | + | | | | R8A779F0 (S4) | Cortex A55 +----------------------------------------------+----------------------------------+ + | | | | | | S4SK | r8a779f4_s4sk_defconfig | + | | Gen4 | :doc:`arm64 <build-env-aarch64>` +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | | | White Hawk | r8a779g0_whitehawk_defconfig | + | | | | R8A779G3 (V4H) | +----------------------------------------------+----------------------------------+ + | | | | | Cortex A76 | :doc:`Sparrow Hawk <rcar-gen4-sparrow-hawk>` | r8a779g3_sparrowhawk_defconfig | + | | | +--------------------+ +----------------------------------------------+----------------------------------+ + | | | | R8A779H0 (V4M) | | Gray Hawk | r8a779h0_grayhawk_defconfig | + | +------------------+----------------------------------+--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | :doc:`arm <build-env-aarch32>` | | Cortex M33 RSIP | | r8a78000_ironhide_cm33_defconfig | + | | Gen5 +----------------------------------+ R8A78000 (X5H) +--------------------+ :doc:`Ironhide <rcar-gen5-ironhide>` +----------------------------------+ + | | | :doc:`arm64 <build-env-aarch64>` | | Cortex A720AE | | r8a78000_ironhide_defconfig | + +--------+------------------+----------------------------------+--------------------+--------------------+----------------------------------------------+----------------------------------+ + | RZ | A1 | :doc:`arm <build-env-aarch32>` | R7S72100 (RZ/A1H) | Cortex A9 | GR-PEACH | grpeach_defconfig | + | +------------------+----------------------------------+--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | | | Beacon EmbeddedWorks RZ/G2M SoM | rzg2_beacon_defconfig | + | | | | R8A774A1 (RZ/G2M) | Cortex A53 or A57 +----------------------------------------------+----------------------------------+ + | | | | | | HopeRun HiHope RZ/G2M | hihope_rzg2_defconfig | + | | | +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | | | Beacon EmbeddedWorks RZ/G2N SoM | rzg2_beacon_defconfig | + | | G2 | :doc:`arm64 <build-env-aarch64>` | R8A774B1 (RZ/G2N) | Cortex A57 +----------------------------------------------+----------------------------------+ + | | | | | | HopeRun HiHope RZ/G2N | hihope_rzg2_defconfig | + | | | +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | R8A774C0 (RZ/G2E) | Cortex A53 | Silicon Linux RZ/G2E evaluation kit (EK874) | silinux_ek874_defconfig | + | | | +--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | | | Beacon EmbeddedWorks RZ/G2H SoM | rzg2_beacon_defconfig | + | | | | R8A774E1 (RZ/G2H) | Cortex A53 or A57 +----------------------------------------------+----------------------------------+ + | | | | | | HopeRun HiHope RZ/G2H | hihope_rzg2_defconfig | + +--------+------------------+----------------------------------+--------------------+--------------------+----------------------------------------------+----------------------------------+ + | | | | R9A06G032 (RZ/N1D) | | Schneider RZ/N1D board | rzn1_snarc_defconfig | + | | :doc:`N1 <rzn1>` | :doc:`arm <build-env-aarch32>` +--------------------+ Cortex A7 +----------------------------------------------+----------------------------------+ + | | | | R9A06G033 (RZ/N1S) | | Schneider RZ/N1S board | rzn1_snarc_defconfig | + +--------+------------------+----------------------------------+--------------------+--------------------+----------------------------------------------+----------------------------------+ - * - R2D - - R2D-PLUS - - SH7751 - - sh - - r2dplus_defconfig +Generic build procedure +----------------------- - * - RZ/A1 - - GR-PEACH - - R7S72100 (RZ/A1H) - - arm - - grpeach_defconfig +This procedure applies only unless the ``Board`` column in +the table above does not contain a link to board specific +details. - * - R-Car Gen2 - - Lager - - R8A7790 (H2) - - arm - - lager_defconfig +Locate the appropriate defconfig in the table above. +Follow toolchain setup procedure in ``Architecture`` column. +Finally, apply standard build procedure: - * - - - Stout - - R8A7790 (H2) - - arm - - stout_defconfig - - * - - - Koelsch - - R8A7791 (M2-W) - - arm - - koelsch_defconfig - - * - - - Porter - - R8A7791 (M2-W) - - arm - - porter_defconfig - - * - - - Blanche - - R8A7792 (V2H) - - arm - - blanche_defconfig - - * - - - Gose - - R8A7793 (M2-N) - - arm - - gose_defconfig - - * - - - Alt - - R8A7794 (E2) - - arm - - alt_defconfig - - * - - - Silk - - R8A7794 (E2) - - arm - - silk_defconfig - - * - R-Car Gen3 - - Salvator-X(S) - - R8A77951 (H3) - - arm64 - - rcar3_salvator-x_defconfig - - * - - - ULCB - - R8A77951 (H3) - - arm64 - - rcar3_ulcb_defconfig - - * - - - Salvator-X(S) - - R8A77960 (M3-W) - - arm64 - - rcar3_salvator-x_defconfig - - * - - - ULCB - - R8A77960 (M3-W) - - arm64 - - rcar3_ulcb_defconfig - - * - - - Salvator-X(S) - - R8A77965 (M3-N) - - arm64 - - rcar3_salvator-x_defconfig - - * - - - ULCB - - R8A77965 (M3-N) - - arm64 - - rcar3_ulcb_defconfig - - * - - - Eagle - - R8A77970 (V3M) - - arm64 - - r8a77970_eagle_defconfig - - * - - - V3MSK - - R8A77970 (V3M) - - arm64 - - r8a77970_v3msk_defconfig - - * - - - Condor - - R8A77980 (V3H) - - arm64 - - r8a77980_condor_defconfig - - * - - - V3HSK - - R8A77980 (V3H) - - arm64 - - r8a77980_v3hsk_defconfig - - * - - - Ebisu - - R8A77990 (E3) - - arm64 - - r8a77990_ebisu_defconfig - - * - - - Draak - - R8A77995 (D3) - - arm64 - - r8a77995_draak_defconfig - - * - R-Car Gen4 - - Falcon - - R8A779A0 (V3U) - - arm64 - - r8a779a0_falcon_defconfig - - * - - - Spider - - R8A779F0 (S4) - - arm64 - - r8a779f0_spider_defconfig - - * - - - S4SK - - R8A779F4 (S4) - - arm64 - - r8a779f4_s4sk_defconfig - - * - - - White Hawk - - R8A779G0 (V4H) - - arm64 - - r8a779g0_whitehawk_defconfig - - * - - - Sparrow Hawk - - R8A779G3 (V4H) - - arm64 - - r8a779g3_sparrowhawk_defconfig - - * - RZ/G2 Family - - Beacon EmbeddedWorks RZ/G2M SoM - - R8A774A1 (RZ/G2M) - - arm64 - - rzg2_beacon_defconfig - - * - - - HopeRun HiHope RZ/G2M - - R8A774A1 (RZ/G2M) - - arm64 - - hihope_rzg2_defconfig - - * - - - Beacon EmbeddedWorks RZ/G2N SoM - - R8A774B1 (RZ/G2N) - - arm64 - - rzg2_beacon_defconfig - - * - - - HopeRun HiHope RZ/G2N - - R8A774B1 (RZ/G2N) - - arm64 - - hihope_rzg2_defconfig - - * - - - Silicon Linux RZ/G2E evaluation kit (EK874) - - R8A774C0 (RZ/G2E) - - arm64 - - silinux_ek874_defconfig - - * - - - Beacon EmbeddedWorks RZ/G2H SoM - - R8A774E1 (RZ/G2H) - - arm64 - - rzg2_beacon_defconfig - - * - - - HopeRun HiHope RZ/G2H - - R8A774E1 (RZ/G2H) - - arm64 - - hihope_rzg2_defconfig - - * - :doc:`RZ/N1 Family <rzn1>` - - Schneider RZ/N1D board - - R9A06G032 (RZ/N1D) - - arm64 - - rzn1_snarc_defconfig - - * - - - Schneider RZ/N1S board - - R9A06G033 (RZ/N1S) - - arm64 - - rzn1_snarc_defconfig - -Build ------ - -Locate the appropriate defconfig in the table above. Then apply standard build -procedure:: +.. code-block:: console make <board_defconfig> make diff --git a/doc/board/renesas/rzn1.rst b/doc/board/renesas/rzn1.rst index e6d636b89e8..24ce7709dd7 100644 --- a/doc/board/renesas/rzn1.rst +++ b/doc/board/renesas/rzn1.rst @@ -10,12 +10,14 @@ This document describes how to build and flash U-Boot for the RZ/N1. U-Boot ^^^^^^ +Please follow :doc:`Renesas 32-bit ARM SoC build environment setup <build-env-aarch32>` +to correctly set up the build environment before attempting to build U-Boot. Clone the U-Boot repository and build it as follows: .. code-block:: bash - git clone --depth 1 https://source.denx.de/u-boot/u-boot.git + git clone --depth 1 https://git.u-boot-project.org/u-boot/u-boot.git cd u-boot make rzn1_snarc_defconfig make CROSS_COMPILE=arm-linux-gnu- diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 141071f528a..9351a5b8eae 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -126,6 +126,7 @@ List of mainline supported Rockchip boards: - Xunlong Orange Pi 3B (orangepi-3b-rk3566) * rk3568 + - 9Tripod X3568 v4 (9tripod-x3568-v4-rk3568) - Rockchip Evb-RK3568 (evb-rk3568) - Banana Pi BPI-R2 Pro (bpi-r2-pro-rk3568) - EmbedFire LubanCat 2 (lubancat-2-rk3568) @@ -133,6 +134,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568) - Generic RK3566/RK3568 (generic-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) + - LinkEase EasePi R1 (easepi-r1-rk3568) - Lunzn FastRhino R66S (fastrhino-r66s-rk3568) - QNAP TS-433 (qnap-ts433-rk3568) - Radxa E25 Carrier Board (radxa-e25-rk3568) @@ -143,6 +145,7 @@ List of mainline supported Rockchip boards: - ArmSoM Sige5 (sige5-rk3576) - Firefly ROC-RK3576-PC (roc-pc-rk3576) - FriendlyElec NanoPi M5 (nanopi-m5-rk3576) + - FriendlyElec NanoPi R76S (nanopi-r76s-rk3576) - Generic RK3576 (generic-rk3576) - Luckfox Omni3576 (omni3576-rk3576) - Radxa ROCK 4D (rock-4d-rk3576) @@ -225,7 +228,7 @@ U-Boot .. code-block:: bash - git clone --depth 1 https://source.denx.de/u-boot/u-boot.git + git clone --depth 1 https://git.u-boot-project.org/u-boot/u-boot.git cd u-boot To build px30 boards: @@ -247,7 +250,7 @@ To build rk3288 boards: .. code-block:: bash - make evb-rk3288-mk808_defconfig + make evb-rk3288-rk808_defconfig make CROSS_COMPILE=arm-linux-gnueabihf- To build rk3308 boards: diff --git a/doc/board/spacemit/bananapi-f3.rst b/doc/board/spacemit/bananapi-f3.rst index f2220950a3a..1ece2ce9d02 100644 --- a/doc/board/spacemit/bananapi-f3.rst +++ b/doc/board/spacemit/bananapi-f3.rst @@ -29,7 +29,7 @@ built for SpacemiT K1 SoC as below: .. code-block:: console cd <U-Boot-dir> - make bananapi-f3_defconfig + make spacemit_k1_defconfig make OPENSBI=<OpenSBI-dir>/build/platform/generic/firmware/fw_dynamic.bin This will generate u-boot.itb diff --git a/doc/board/spacemit/index.rst b/doc/board/spacemit/index.rst index e7d3d94e459..a5e35ee12ab 100644 --- a/doc/board/spacemit/index.rst +++ b/doc/board/spacemit/index.rst @@ -6,4 +6,5 @@ SpacemiT :maxdepth: 1 bananapi-f3 + k1-spl diff --git a/doc/board/spacemit/k1-spl.rst b/doc/board/spacemit/k1-spl.rst new file mode 100644 index 00000000000..187eed56e8e --- /dev/null +++ b/doc/board/spacemit/k1-spl.rst @@ -0,0 +1,243 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +SpacemiT K1 SPL Build and Test Guide +===================================== + +This guide explains how to build and test U-Boot SPL on SpacemiT K1 based +boards. It covers building SPL with DDR initialization, generating the signed +FSBL image, and deploying via USB fastboot. + +Tested boards: Banana Pi BPI-F3, MusePi Pro. + +.. note:: + + The procedure described here loads SPL into SRAM via USB fastboot and + does not modify the on-board flash, so a power cycle restores the + board's normal boot path. + + At this stage of the patchset, SPL initializes DDR and then halts with + "SPL: Unsupported Boot Device!" because SPI NOR storage support is not + yet available in U-Boot proper. This document will be updated when + U-Boot stage support is ready. + +Prerequisites +~~~~~~~~~~~~~ + +- A SpacemiT K1 board with USB Type-C and UART access +- USB-to-UART adapter (3.3V TTL) +- ``minicom`` or equivalent serial terminal, configured at 115200 8N1 +- ``fastboot`` tool on the host + +Hardware Setup +~~~~~~~~~~~~~~ + +**1. UART Connection** + +Remove all other cables first, then attach UART. Connect a 3.3V +USB-to-UART cable to the board's UART header (J25 on the BPI-F3):: + + BPI-F3 top view + +--------------------------------------------------+ + | | + | J15: USB-C [====] [FDL] [PWR] [RST] | + | | + | | + | J25 (UART header) | + | [TXD] [RXD] [GND] | + +--------------------------------------------------+ + +After UART is connected, attach the USB Type-C cable to the OTG port +(J15 on BPI-F3) to power on. + +**2. Serial Console** + +.. code-block:: console + + $ minicom -D /dev/ttyUSB0 + +Default baudrate: 115200. + +Building U-Boot SPL +~~~~~~~~~~~~~~~~~~~~ + +**1. Obtain the DDR training firmware** + +The DDR training firmware is a proprietary binary provided by SpacemiT. It is +not included in U-Boot and must be downloaded separately from: + +https://github.com/spacemit-com/spacemit-firmware/tree/master/k1/v0.2 + +Download ``ddr_fw.bin`` from that directory. + +This binary is integrated into the SPL image at build time via the binman +framework. When the SPL image is loaded to SRAM (e.g., via USB fastboot), +the SPL executes the DDR firmware from SRAM to perform DDR initialization. + +**2. Obtain OpenSBI fw_dynamic.bin** + +Any pre-built ``fw_dynamic.bin`` is sufficient. Upstream OpenSBI +sources are at https://github.com/riscv-software-src/opensbi if you +need to build one. + +At this stage of the patchset, SPL halts before invoking OpenSBI, +but U-Boot's binman still packages ``fw_dynamic.bin`` into +``u-boot.itb`` and the build fails if it is missing. + +**3. Build SPL** + +.. code-block:: console + + $ export CROSS_COMPILE=riscv64-linux-gnu- + $ export ARCH=riscv + $ export DDR_FW_FILE=$(pwd)/ddr_fw.bin + $ export OPENSBI=/path/to/fw_dynamic.bin + $ make spacemit_k1_defconfig + $ make + +Output: ``u-boot-spl-ddr.bin`` in the build directory. This image contains the +SPL code and the DDR firmware blob packaged together via binman. + +.. note:: + + If ``DDR_FW_FILE`` is not set, the build completes with an empty + placeholder. The resulting SPL will boot but cannot initialize DDR. + +**4. Generate signed FSBL image** + +The K1 BootROM requires a signed first-stage bootloader (FSBL). The signing +tool (``tools/build_binary_file.py``) is in SpacemiT's vendor U-Boot repository: + +.. code-block:: console + + $ git clone -b k1-bl-v2.2.y https://gitee.com/spacemit-buildroot/uboot-2022.10 + +The script uses ``fsbl_ddr.json`` which may not exist by default. If +``fsbl_ddr.json`` does not exist in +``uboot-2022.10/board/spacemit/k1-x/configs/``, +create it by copying ``fsbl.json`` and replacing the reference to +``u-boot-spl.bin`` with ``u-boot-spl-ddr.bin``: + +.. code-block:: console + + $ cd uboot-2022.10/board/spacemit/k1-x/configs + $ cp fsbl.json fsbl_ddr.json + $ sed -i 's/u-boot-spl\.bin/u-boot-spl-ddr.bin/g' fsbl_ddr.json + +Create the ``fsbl.sh`` script below in the ``uboot-2022.10`` directory. +Update the path variables to match your local setup: + +.. code-block:: bash + + #!/bin/sh + MAINLINE_UBOOT_IMG_PATH="{your path}/u-boot" + MAINLINE_SPL_IMG_PATH="{your path}/u-boot/spl" + FSBL_PATH="{your path}/uboot-2022.10/spl_bin" + KEY_TOOL_PATH="{your path}/uboot-2022.10/tools" + CONFIG_PATH="{your path}/uboot-2022.10/board/spacemit/k1-x/configs" + + mkdir -p ${FSBL_PATH} + echo "Clean binaries in ${FSBL_PATH}" + rm -f ${FSBL_PATH}/u-boot-spl-ddr.bin + rm -f ${FSBL_PATH}/u-boot-spl.bin + + if [ ! -d ${MAINLINE_SPL_IMG_PATH} ]; then + MAINLINE_UBOOT_IMG_PATH="{your path}/build" + MAINLINE_SPL_IMG_PATH="{your path}/build/spl" + fi + + # The signing tool reads u-boot-spl-ddr.bin from the path declared in + # fsbl_ddr.json's "source" field, which is resolved relative to the + # JSON file's directory -- i.e. one level up from CONFIG_PATH, not + # FSBL_PATH. Stage the unsigned binary there before signing. + cp ${MAINLINE_UBOOT_IMG_PATH}/u-boot-spl-ddr.bin ${CONFIG_PATH}/../ + python3 ${KEY_TOOL_PATH}/build_binary_file.py \ + -c ${CONFIG_PATH}/fsbl_ddr.json \ + -o ${FSBL_PATH}/FSBL.bin + +Then run: + +.. code-block:: console + + $ chmod +x fsbl.sh + $ ./fsbl.sh + +Output: ``FSBL.bin`` in the ``spl_bin`` directory, ready for deployment. + +Deploying via USB Fastboot +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To enter BootROM fastboot mode: + +1. Power off the board by unplugging its power supply. +2. **Press and hold** the FDL button (called "Boot Key" on some boards; + see the board layout above for the BPI-F3). +3. While holding the button, use a USB cable to connect the OTG port to + your host. This cable is also used by fastboot to upload the firmware. +4. Release the button. + +On the host, ``fastboot devices`` should list the board:: + + dfu-device DFU download + +The serial console shows the BootROM's USB download handler trace, +including a line like:: + + usb2d_initialize : enter + +This indicates the board is ready to accept an image via USB. + +.. tip:: + + If you are worried about insufficient USB power, you can first plug + in the power, then release the button, and then plug in the USB + cable. + +On the host: + +.. code-block:: console + + $ sudo fastboot stage FSBL.bin + $ sudo fastboot continue + +Expected Output +~~~~~~~~~~~~~~~~ + +During successful SPL boot with DDR initialization, the serial console +shows output like:: + + <debug_uart> + + U-Boot SPL 2026.04-rc4-00430-g8b84b1ed8ea9 (May 08 2026 - 09:08:27 -0400) + Fail to detect board:-19 + vdd_core, value:900000 + vdd_1v8, value:1800000 + vdd_1v8_mmc, value:1800000 + DDR firmware: [0xc0815840]:0xf0227179, size:0x8d98 + DDR is ready + SPL: Unsupported Boot Device! + SPL: failed to boot from all boot devices + ### ERROR ### Please RESET the board ### + +To walk through the key lines: + +- ``DDR firmware: [...], size:0x8d98`` - DDR firmware loaded successfully +- ``DDR is ready`` - DDR initialization completed +- ``SPL: failed to boot from all boot devices`` - expected at this stage, + confirms that SPL with DDR init is working correctly + +If SPL hangs before printing DDR messages, verify that ``DDR_FW_FILE`` was set +during build and that ``ddr_fw.bin`` is not empty. + +.. tip:: + + To see verbose DDR training output from the DDR firmware (per-phase + training pass/fail logs), add ``#define DEBUG`` at the top of + ``board/spacemit/k1/spl.c`` and rebuild. SPL then passes ``puts`` as + the firmware's log callback; otherwise the callback is ``NULL`` and + the firmware runs silently. + +References +~~~~~~~~~~~ + +- `DDR firmware repository <https://github.com/spacemit-com/spacemit-firmware>`_ +- `SpacemiT vendor U-Boot (signing tool) <https://gitee.com/spacemit-buildroot/uboot-2022.10>`_ diff --git a/doc/board/starfive/jh7110_common.rst b/doc/board/starfive/jh7110_common.rst index e9c0ed5b022..013bab50045 100644 --- a/doc/board/starfive/jh7110_common.rst +++ b/doc/board/starfive/jh7110_common.rst @@ -170,7 +170,7 @@ Build U-Boot .. code-block:: console - git clone https://source.denx.de/u-boot/u-boot.git u-boot.git + git clone https://git.u-boot-project.org/u-boot/u-boot.git u-boot.git make -C u-boot.git O=u-boot starfive_visionfive2_defconfig make -C u-boot.git O=u-boot OPENSBI=opensbi/platform/generic/firmware/fw_dynamic.bin diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 74ece0c9acf..d3ecaf59909 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -170,7 +170,7 @@ online * **Das U-Boot** - | **source:** https://source.denx.de/u-boot/u-boot.git + | **source:** https://git.u-boot-project.org/u-boot/u-boot.git | **branch:** master * **Trusted Firmware-A (TF-A)** @@ -651,6 +651,17 @@ Refer (:ref:`U-boot ARMV8 build <k3_rst_include_start_build_steps_uboot>`) This will need to be explicitly disabled by changing the boot_targets to disallow fallback during testing. +DDR Configuration +----------------- + +The K3 DDRSS driver (drivers/ram/k3-ddrss/k3-ddrss.c) configures the DDR during +the R5 SPL stage. The driver utilizes an auto-generated configuration file +containing necessary settings for the DDR. It configures the frequency, timing +parameters, training algorithms etc. for DDR initialization. The configuration +DTSI can be generated using the `Sysconfig tool <https://dev.ti.com/sysconfig>`_ +and selecting the software product as "DDR Configuration for \*" as well as the +required device. + Saving environment ------------------ @@ -1258,3 +1269,86 @@ Currently, OpenOCD does not support tracing for K3 platforms. Tracing function could be beneficial if the bug in code occurs deep within nested function and can optionally save developers major trouble of stepping through a large quantity of code. + +Firmware TPM (fTPM) Support +--------------------------- + +K3 family of devices with **eMMC** are capable of supporting firmware TPM +(fTPM) functionality through OP-TEE, providing TPM 2.0 capabilities +without requiring discrete TPM hardware. +The fTPM Trusted Application runs in OP-TEE secure world and uses +eMMC Replay Protected Memory Block (RPMB) for secure persistent +storage. + +The fTPM implementation consists of: + +* **fTPM TA**: Microsoft's fTPM Trusted Application (TA) running in OP-TEE +* **RPMB Storage**: eMMC RPMB partition for persistent TPM NV storage +* **U-Boot Support**: TPM commands and RPMB access via OP-TEE + +fTPM can be used to enable security features such as: + +* Measured boot +* Secure key storage +* Platform attestation + +Enabling fTPM in U-Boot +^^^^^^^^^^^^^^^^^^^^^^^ + +The following are the steps to enable fTPM in uboot: + +1. Programming Keys into eMMC RPMB +"""""""""""""""""""""""""""""""""" + +Since fTPM uses RPMB for persistent storage, the eMMC RPMB must be +provisioned with an authentication key on first boot. This requires +building optee_os with the ``CFG_RPMB_WRITE_KEY=y`` flag + +.. prompt:: bash $ + + # inside optee_os source + make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 CFG_ARM64_core=y \ + PLATFORM=$OPTEE_PLATFORM CFG_RPMB_WRITE_KEY=y + +.. warning:: + + Programming the RPMB key is a **one-time, irreversible operation**. + The key is derived from the Hardware Unique Key (HUK) and cannot + be changed once programmed. For further details, refer + `Secure Storage <https://optee.readthedocs.io/en/latest/architecture/secure_storage.html>`_ + +On first boot with this configuration, OP-TEE will automatically program +the RPMB authentication key. Subsequent boots should use OP-TEE built +without this flag. + +2. Generate fTPM TA binary +"""""""""""""""""""""""""" + +To generate fTPM TA binary, follow the +`Building the TA <https://github.com/OP-TEE/optee_ftpm#building-the-ta>`_ +steps mentioned in the OP-TEE fTPM Github repository + +3. Build OP-TEE with TA: +"""""""""""""""""""""""" + +With the TA generated from last step, build optee-os with RPMB and early +TA enabled: + +.. prompt:: bash $ + + # inside optee_os source + make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 CFG_ARM64_core=y \ + PLATFORM=$OPTEE_PLATFORM CFG_RPMB_FS=y CFG_REE_FS=n \ + CFG_EARLY_TA=y CFG_RPMB_ANNOUNCE_PROBE_CAP=n \ + EARLY_TA_PATHS=/path/to/ftpm_ta.stripped.elf + +Expected Outcome +^^^^^^^^^^^^^^^^ + +To verify fTPM support is working, run tpm2 commands in u-boot prompt: + +.. code-block:: console + + => tpm2 info + Microsoft OP-TEE fTPM + => tpm2 init diff --git a/doc/board/toradex/aquila-imx95.rst b/doc/board/toradex/aquila-imx95.rst new file mode 100644 index 00000000000..edd40252657 --- /dev/null +++ b/doc/board/toradex/aquila-imx95.rst @@ -0,0 +1,175 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Toradex Aquila iMX95 Module +=========================== + +- SoM: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 +- Carrier board: https://www.toradex.com/products/carrier-board/aquila-development-board-kit + +Quick Start +----------- + +- Setup environment +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Setup environment +----------------- + +Suggested current toolchains are ARM 14.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads): + +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz + +.. code-block:: console + + $ export TOOLS=<path/to/directory/with/toolchains> + $ export CROSS_COMPILE_32=<path/to/arm/toolchain/bin/>arm-none-linux-gnueabihf- + $ export CROSS_COMPILE_64=<path/to/arm64/toolchain/bin/>aarch64-none-linux-gnu- + +Get ahab-container.img +---------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +--------------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree) + +Get and Build OEI Images +------------------------ + +Note: `$srctree` is the U-Boot source directory +Get OEI from: https://git.toradex.com/cgit/imx-oei-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-oei-toradex.git/ + $ cd imx-oei-toradex + + $ make board=toradex-aquila-imx95 oei=ddr DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/ddr/oei-m33-ddr.bin $(srctree) + + $ make board=toradex-aquila-imx95 oei=tcm DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/tcm/oei-m33-tcm.bin $(srctree) + +The Makefile will set `DDR_CONFIG` automatically based on the selected silicon +revision. + +Get and Build the System Manager Image +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get System Manager from: https://git.toradex.com/cgit/imx-sm-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-sm-toradex.git/ + $ cd imx-sm-toradex + $ make config=aquila-imx95 all + $ cp build/aquila-imx95/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ unset LDFLAGS + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git + $ cd imx-atf + $ make PLAT=imx95 bl31 + $ cp build/imx95/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ make aquila-imx95_defconfig + $ make + +Flash to eMMC +------------- + +.. code-block:: console + + > tftpboot ${loadaddr} flash.bin + > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 + > mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt} + +As a convenience, instead of the last two commands, one may also use the update +U-Boot wrapper: + +.. code-block:: console + + > run update_uboot + +Boot +---- + +Boot sequence is: + +* SPL ---> ATF (TF-A) ---> U-Boot proper + +Output: + +.. code-block:: console + + U-Boot SPL 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + SYS Boot reason: por, origin: -1, errid: -1 + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + Trying to boot from MMC1 + Load image from MMC/SD 0xd2800 + NOTICE: BL31: v2.10.0 (release):lf-6.6.52-2.2.1-dirty + NOTICE: BL31: Built : 06:40:36, Jul 7 2025 + + + U-Boot 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + + CPU: NXP i.MX95 Rev2.0 A55 at 1800 MHz - invalid sensor data + DRAM: 7.8 GiB + Core: 321 devices, 30 uclasses, devicetree: separate + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + MMC: FSL_SDHC: 0, FSL_SDHC: 1 + Loading Environment from MMC... Reading from MMC(0)... OK + In: serial@44380000 + Out: serial@44380000 + Err: serial@44380000 + Model: Toradex 0098 Aquila iMX95 Hexa 8GB WB IT V1.0A + Serial#: 12594391 + + BuildInfo: + - ELE firmware version 2.0.2-c110ba4b + + Net: WARNING: no MAC address assigned for MAC0 + imx_get_mac_from_fuse: fuse read err: 0 + eth0: enetc-0 [PRIME] + Hit any key to stop autoboot: 0 + Aquila iMX95 # diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 27f059542e6..c5955ea1ad8 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -8,6 +8,7 @@ Toradex apalis-imx8 aquila-am69 + aquila-imx95 colibri_imx7 colibri-imx8x smarc-imx8mp @@ -16,3 +17,4 @@ Toradex verdin-am62p verdin-imx8mm verdin-imx8mp + verdin-imx95 diff --git a/doc/board/toradex/verdin-imx95.rst b/doc/board/toradex/verdin-imx95.rst new file mode 100644 index 00000000000..d252277cc20 --- /dev/null +++ b/doc/board/toradex/verdin-imx95.rst @@ -0,0 +1,171 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Verdin iMX95 Module +========================== + +- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 +- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit + +Quick Start +----------- + +- Setup environment +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Setup environment +----------------- + +Suggested current toolchains are ARM 14.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads): + +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz + +.. code-block:: console + + $ export TOOLS=<path/to/directory/with/toolchains> + $ export CROSS_COMPILE_32=<path/to/arm/toolchain/bin/>arm-none-linux-gnueabihf- + $ export CROSS_COMPILE_64=<path/to/arm64/toolchain/bin/>aarch64-none-linux-gnu- + +Get ahab-container.img +---------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +--------------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4x*v202409.bin $(srctree) + +Get and Build OEI Images +------------------------ + +Note: `$srctree` is the U-Boot source directory +Get OEI from: https://git.toradex.com/cgit/imx-oei-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-oei-toradex.git/ + $ cd imx-oei-toradex + + $ make board=toradex-verdin-imx95 oei=ddr DEBUG=1 r=B0 all + $ cp build/toradex-verdin-imx95/ddr/oei-m33-ddr.bin $(srctree) + +The Makefile will set `DDR_CONFIG` automatically based on the selected silicon +revision. + +Get and Build the System Manager Image +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get System Manager from: https://git.toradex.com/cgit/imx-sm-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-sm-toradex.git/ + $ cd imx-sm-toradex + $ make config=verdin-imx95 all + $ cp build/verdin-imx95/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ unset LDFLAGS + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git + $ cd imx-atf + $ make PLAT=imx95 bl31 + $ cp build/imx95/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ make verdin-imx95_defconfig + $ make + +Flash to eMMC +------------- + +.. code-block:: console + + > tftpboot ${loadaddr} flash.bin + > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 + > mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt} + +As a convenience, instead of the last two commands, one may also use the update +U-Boot wrapper: + +.. code-block:: console + + > run update_uboot + +Boot +---- + +Boot sequence is: + +* SPL ---> ATF (TF-A) ---> U-Boot proper + +Output: + +.. code-block:: console + + U-Boot SPL 2026.04-00756-ge7053d7cab88 (Apr 15 2026 - 12:27:34 +0200) + SYS Boot reason: pmic, origin: -1, errid: -1 + SYS shutdown reason: pmic, origin: -1, errid: -1 + Trying to boot from MMC1 + Primary set selected + Load image from MMC/SD 0xca000 + NOTICE: BL31: v2.12.0(release):lf-6.12.20-2.0.0 + NOTICE: BL31: Built : 17:34:12, Oct 21 2025 + + + U-Boot 2026.04-00756-ge7053d7cab88 (Apr 15 2026 - 12:27:34 +0200) + + CPU: NXP i.MX95 Rev2.0 A55 at 1800 MHz - invalid sensor data + DRAM: 7.8 GiB + Core: 323 devices, 28 uclasses, devicetree: separate + MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 + Loading Environment from MMC... Reading from MMC(0)... OK + In: serial@44380000 + Out: serial@44380000 + Err: serial@44380000 + Model: Toradex 0089 Verdin iMX95 Hexa 8GB WB IT V1.0B + Serial#: 12594936 + + BuildInfo: + - ELE firmware version 2.0.2-2a118457 + + Setting variant to wifi + Net: No ethernet found. + Hit any key to stop autoboot: 0 + Verdin iMX95 # diff --git a/doc/board/tq/index.rst b/doc/board/tq/index.rst new file mode 100644 index 00000000000..775957474e7 --- /dev/null +++ b/doc/board/tq/index.rst @@ -0,0 +1,13 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later or CC-BY-4.0 + +.. Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, +.. D-82229 Seefeld, Germany. + +TQ-Systems +========== + +.. toctree:: + :maxdepth: 2 + + tqma6ul + tqma7 diff --git a/doc/board/tq/tqma6ul.rst b/doc/board/tq/tqma6ul.rst new file mode 100644 index 00000000000..2b346715642 --- /dev/null +++ b/doc/board/tq/tqma6ul.rst @@ -0,0 +1,105 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later or CC-BY-4.0 + +.. Copyright (c) 2017-2025 TQ-Systems GmbH <[email protected]>, +.. D-82229 Seefeld, Germany. + +######################################## +U-Boot for the TQ-Systems TQMa6x modules +######################################## + +The following hardware revisions are supported: + +Modules: + ++------------+----------+ +| TQMa6ULx | REV.030x | ++------------+----------+ +| TQMa6ULLx | REV.030x | ++------------+----------+ +| TQMa6ULxL | REV.030x | ++------------+----------+ +| TQMa6ULLxL | REV.030x | ++------------+----------+ + +Mainboards: + ++----------+----------+ +| MBa6ULx | REV.020x | ++----------+----------+ + +Hardware on modules TQMa6ULx, TQMa6ULxL, TQMa6ULLx and TQMa6ULLxL + +- eMMC +- RTC +- PMIC +- SPI-NOR (optional) +- EEPROM +- Temperature sensor +- RAM (256 MiB / 512 MiB) + +Supported hardware on Starterkit MBa6ULx: + +- 2 Ethernet PHY connected to FEC0 / FEC1 (usage depends on CPU) +- SD-card slot +- UART +- USB + +Note: To change the Ethernet port to use for networking functionality, use the +U-Boot generic environment variable ``ethact``. + +.. code-block:: bash + + setenv ethact <FEC> + +*********** +Boot source +*********** + +- SD/eMMC +- USB/SDP (with NXP UUU tool) +- SPI NOR (functional but requires additional prepended NXP header. + Not supported in U-Boot.) + +******** +Building +******** + +To build U-Boot for the TQ-Systems TQMa6L modules: + +.. code-block:: bash + + make <som>_<baseboard>_<boot>_defconfig + make + + +**som** is a placeholder for the module base variant: + ++------------+------------+----------------+ +| tqma6ulx | TQMa6ULx | i.MX6UL | ++------------+------------+----------------+ +| tqma6ullx | TQMa6ULLx | i.MX6ULL | ++------------+------------+----------------+ +| tqma6ulxl | TQMa6ULxL | i.MX6UL (lga) | ++------------+------------+----------------+ +| tqma6ullxl | TQMa6ULLxL | i.MX6ULL (lga) | ++------------+------------+----------------+ + +**baseboard** is a placeholder for the mainboard to compile for: + ++----------+----------+ +| mba6ul | MBa6ULx | ++----------+----------+ + +**boot** is a placeholder for the boot device: + ++------+---------+ +| mmc | SD/eMMC | ++------+---------+ +| spi | SPI-NOR | ++------+---------+ + +************ +Support Wiki +************ + +See `TQ Embedded Wiki for TQMa6ulx <https://support.tq-group.com/en/arm/tqma6ulx>`_. diff --git a/doc/board/tq/tqma7.rst b/doc/board/tq/tqma7.rst new file mode 100644 index 00000000000..60fd883968d --- /dev/null +++ b/doc/board/tq/tqma7.rst @@ -0,0 +1,77 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +.. Copyright (c) 2020-2026 TQ-Systems GmbH <[email protected]>, +.. D-82229 Seefeld, Germany. + +######################################## +U-Boot for the TQ-Systems TQMa7x modules +######################################## + +This file contains information for the port of +U-Boot to the TQ-Systems TQMa7x modules. + +*********** +Boot source +*********** + +The following boot sources are supported: + +- SD/eMMC +- USB (SDP) + +QSPI boot is functional but requires an additional prepended NXP header +image. This currently unsupported in u-boot. + +******** +Building +******** + +To build U-Boot for the TQ-Systems TQMa7x modules: + +.. code-block:: bash + + make tqma7_mba7_<boot>_defconfig + make + +**boot** is a placeholder for the boot device: + ++------+-----------+ +| mmc | SD/eMMC | ++------+-----------+ +| uuu | USB (SDP) | ++------+-----------+ + +The default build artifact is named ``u-boot-with-spl.imx``. + +***************************************** +Serial Download Protocol (SDP) / USB boot +***************************************** + +The complete system image can be programmed with ``uuu`` +(https://github.com/nxp-imx/mfgtools) to eMMC. + +Serial Download Protocol is supported on the Micro-B USB port (X5) of MBa7x. +The command ``fastboot usb 0`` is used to enable the fastboot gadget. + +Build SDP enabled U-Boot image +============================== + +.. code-block:: bash + + make <som>_mba7_uuu_defconfig + make + +Booting +======= + +With UUU + +.. code-block:: bash + + uuu -b spl <UUU U-Boot image> + +************ +Support Wiki +************ + +See `TQ Embedded Wiki for TQMa7x <https://support.tq-group.com/en/arm/tqma7x>`_. |