diff options
Diffstat (limited to 'drivers/crypto')
| -rw-r--r-- | drivers/crypto/aspeed/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/crypto/aspeed/aspeed_acry.c | 4 | ||||
| -rw-r--r-- | drivers/crypto/aspeed/aspeed_hace.c | 2 | ||||
| -rw-r--r-- | drivers/crypto/aspeed/cptra_ecdsa.c | 2 | ||||
| -rw-r--r-- | drivers/crypto/aspeed/cptra_sha.c | 2 | ||||
| -rw-r--r-- | drivers/crypto/fsl/Kconfig | 11 | ||||
| -rw-r--r-- | drivers/crypto/tegra/tegra_aes.c | 2 |
7 files changed, 16 insertions, 15 deletions
diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig index 401225b8528..a4710257f62 100644 --- a/drivers/crypto/aspeed/Kconfig +++ b/drivers/crypto/aspeed/Kconfig @@ -15,11 +15,11 @@ config ASPEED_ACRY bool "ASPEED RSA and ECC Engine" depends on ASPEED_AST2600 help - Select this option to enable a driver for using the RSA/ECC engine in - the ASPEED BMC SoCs. + Select this option to enable a driver for using the RSA/ECC engine in + the ASPEED BMC SoCs. - Enabling this allows the use of RSA/ECC operations in hardware without requiring the - software implementations. It also improves performance and saves code size. + Enabling this allows the use of RSA/ECC operations in hardware without requiring the + software implementations. It also improves performance and saves code size. config ASPEED_CPTRA_SHA bool "Caliptra SHA ACC for Aspeed AST27xx SoCs" diff --git a/drivers/crypto/aspeed/aspeed_acry.c b/drivers/crypto/aspeed/aspeed_acry.c index e3f81ebd5c7..ff01256e150 100644 --- a/drivers/crypto/aspeed/aspeed_acry.c +++ b/drivers/crypto/aspeed/aspeed_acry.c @@ -144,13 +144,13 @@ static int aspeed_acry_probe(struct udevice *dev) return ret; } - acry->base = devfdt_get_addr_index(dev, 0); + acry->base = dev_read_addr_index(dev, 0); if (acry->base == FDT_ADDR_T_NONE) { debug("Failed to get acry base\n"); return acry->base; } - acry->sram_base = devfdt_get_addr_index(dev, 1); + acry->sram_base = dev_read_addr_index(dev, 1); if (acry->sram_base == FDT_ADDR_T_NONE) { debug("Failed to get acry SRAM base\n"); return acry->sram_base; diff --git a/drivers/crypto/aspeed/aspeed_hace.c b/drivers/crypto/aspeed/aspeed_hace.c index 17cc30a7b54..22b5008a296 100644 --- a/drivers/crypto/aspeed/aspeed_hace.c +++ b/drivers/crypto/aspeed/aspeed_hace.c @@ -341,7 +341,7 @@ static int aspeed_hace_probe(struct udevice *dev) return rc; } - hace->base = devfdt_get_addr(dev); + hace->base = dev_read_addr(dev); return rc; } diff --git a/drivers/crypto/aspeed/cptra_ecdsa.c b/drivers/crypto/aspeed/cptra_ecdsa.c index 4b70d89def7..7603ca373ff 100644 --- a/drivers/crypto/aspeed/cptra_ecdsa.c +++ b/drivers/crypto/aspeed/cptra_ecdsa.c @@ -149,7 +149,7 @@ static int cptra_ecdsa_probe(struct udevice *dev) { struct cptra_ecdsa *ce = dev_get_priv(dev); - ce->regs = (void *)devfdt_get_addr(dev); + ce->regs = (void *)dev_read_addr(dev); if (ce->regs == (void *)FDT_ADDR_T_NONE) { debug("cannot map Caliptra mailbox registers\n"); return -EINVAL; diff --git a/drivers/crypto/aspeed/cptra_sha.c b/drivers/crypto/aspeed/cptra_sha.c index 26b97bdd92b..f57778e160d 100644 --- a/drivers/crypto/aspeed/cptra_sha.c +++ b/drivers/crypto/aspeed/cptra_sha.c @@ -219,7 +219,7 @@ static int cptra_sha_probe(struct udevice *dev) { struct cptra_sha *cs = dev_get_priv(dev); - cs->regs = (void *)devfdt_get_addr(dev); + cs->regs = (void *)dev_read_addr(dev); if (cs->regs == (void *)FDT_ADDR_T_NONE) { debug("cannot map Caliptra SHA ACC registers\n"); return -ENODEV; diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index eb01c6cf700..244a9bd905d 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -20,6 +20,7 @@ config SYS_FSL_MAX_NUM_OF_SEC config CAAM_64BIT bool + depends on FSL_CAAM default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 help Select Crypto driver for 64 bits CAAM version @@ -27,27 +28,27 @@ config CAAM_64BIT config SYS_FSL_HAS_SEC bool help - Enable Freescale Secure Boot and Trusted Architecture + Enable Freescale Secure Boot and Trusted Architecture config SYS_FSL_SEC_COMPAT_2 bool help - Secure boot and trust architecture compatible version 2 + Secure boot and trust architecture compatible version 2 config SYS_FSL_SEC_COMPAT_4 bool help - Secure boot and trust architecture compatible version 4 + Secure boot and trust architecture compatible version 4 config SYS_FSL_SEC_COMPAT_5 bool help - Secure boot and trust architecture compatible version 5 + Secure boot and trust architecture compatible version 5 config SYS_FSL_SEC_COMPAT_6 bool help - Secure boot and trust architecture compatible version 6 + Secure boot and trust architecture compatible version 6 config SYS_FSL_SEC_BE bool "Big-endian access to Freescale Secure Boot" diff --git a/drivers/crypto/tegra/tegra_aes.c b/drivers/crypto/tegra/tegra_aes.c index 7b374c757ba..55a4cec525b 100644 --- a/drivers/crypto/tegra/tegra_aes.c +++ b/drivers/crypto/tegra/tegra_aes.c @@ -518,7 +518,7 @@ static int tegra_aes_probe(struct udevice *dev) return -EINVAL; } - priv->iram_addr = devfdt_get_addr_size_name_ptr(dev, "iram-buffer", &iram_size); + priv->iram_addr = dev_read_addr_size_name_ptr(dev, "iram-buffer", &iram_size); if (!priv->iram_addr) { log_debug("%s: Cannot find iram buffer address, binding failed\n", __func__); return -EINVAL; |