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-rw-r--r--drivers/mmc/Kconfig15
-rw-r--r--drivers/mmc/cv1800b_sdhci.c5
-rw-r--r--drivers/mmc/dw_mmc.c6
-rw-r--r--drivers/mmc/fsl_esdhc_imx.c14
-rw-r--r--drivers/mmc/mmc.c7
-rw-r--r--drivers/mmc/mmc_bootdev.c2
-rw-r--r--drivers/mmc/msm_sdhci.c7
-rw-r--r--drivers/mmc/mvebu_mmc.c4
-rw-r--r--drivers/mmc/octeontx_hsmmc.c74
-rw-r--r--drivers/mmc/octeontx_hsmmc.h1
-rw-r--r--drivers/mmc/pci_mmc.c4
-rw-r--r--drivers/mmc/sdhci-cadence.c108
-rw-r--r--drivers/mmc/sdhci-cadence.h5
-rw-r--r--drivers/mmc/sdhci-cadence6.c45
-rw-r--r--drivers/mmc/sdhci.c4
-rw-r--r--drivers/mmc/xenon_sdhci.c5
16 files changed, 70 insertions, 236 deletions
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 24bd16ad5f3..f9f7aa5cf97 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -332,7 +332,7 @@ config MMC_MESON_GX
bool "Meson GX EMMC controller support"
depends on ARCH_MESON
help
- Support for EMMC host controller on Meson GX ARM SoCs platform (S905)
+ Support for EMMC host controller on Meson GX ARM SoCs platform (S905)
config MMC_OWL
bool "Actions OWL Multimedia Card Interface support"
@@ -415,7 +415,7 @@ config MMC_OMAP36XX_PINS
config HSMMC2_8BIT
bool "Enable 8-bit interface for eMMC (interface #2)"
- depends on MMC_OMAP_HS && (OMAP54XX || DRA7XX || AM33XX || \
+ depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \
AM43XX || ARCH_KEYSTONE)
config SH_MMCIF
@@ -576,7 +576,7 @@ config MMC_SDHCI_ATMEL
specification.
config MMC_SDHCI_BCM2835
- tristate "SDHCI support for the BCM2835 SD/MMC Controller"
+ bool "SDHCI support for the BCM2835 SD/MMC Controller"
depends on ARCH_BCM283X
depends on MMC_SDHCI
select MMC_SDHCI_IO_ACCESSORS
@@ -589,7 +589,7 @@ config MMC_SDHCI_BCM2835
If unsure, say N.
config MMC_SDHCI_BCMSTB
- tristate "SDHCI support for the BCMSTB SD/MMC Controller"
+ bool "SDHCI support for the BCMSTB SD/MMC Controller"
depends on MMC_SDHCI && (ARCH_BCMSTB || ARCH_BCM283X)
help
This selects the Broadcom set-top box SD/MMC controller.
@@ -659,8 +659,8 @@ config MMC_SDHCI_MSM
depends on MMC_SDHCI && ARCH_SNAPDRAGON
help
Enables support for SDHCI 2.0 controller present on some Qualcomm
- Snapdragon devices. This device is compatible with eMMC v4.5 and
- SD 3.0 specifications. Both SD and eMMC devices are supported.
+ Snapdragon devices. This device is compatible with eMMC v4.5 and
+ SD 3.0 specifications. Both SD and eMMC devices are supported.
Card-detect gpios are not supported.
config MMC_SDHCI_MV
@@ -852,12 +852,13 @@ config FTSDC010_SDIO
bool "Support ftsdc010 sdio"
depends on FTSDC010
help
- This can enable ftsdc010 sdio function.
+ This can enable ftsdc010 sdio function.
config MMC_MTK
bool "MediaTek SD/MMC Card Interface support"
depends on ARCH_MEDIATEK || ARCH_MTMIPS || ARCH_AIROHA
depends on OF_CONTROL
+ imply LMB_LIMIT_DMA_BELOW_RAM_TOP
help
This selects the MediaTek(R) Secure digital and Multimedia card Interface.
If you have a machine with a integrated SD/MMC card reader, say Y here.
diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c
index 036e798f374..b756649f90f 100644
--- a/drivers/mmc/cv1800b_sdhci.c
+++ b/drivers/mmc/cv1800b_sdhci.c
@@ -85,7 +85,7 @@ static int cv1800b_sdhci_probe(struct udevice *dev)
int ret;
host->name = dev->name;
- host->ioaddr = devfdt_get_addr_ptr(dev);
+ host->ioaddr = dev_read_addr_ptr(dev);
upriv->mmc = &plat->mmc;
host->mmc = &plat->mmc;
@@ -94,6 +94,9 @@ static int cv1800b_sdhci_probe(struct udevice *dev)
host->ops = &cv1800b_sdhci_sd_ops;
host->max_clk = MMC_MAX_CLOCK;
+ if (dev_read_bool(dev, "no-1-8-v"))
+ host->quirks |= SDHCI_QUIRK_NO_1_8_V;
+
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index d9c05b223d5..c2424d7875c 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -645,9 +645,11 @@ static int dwmci_set_ios(struct mmc *mmc)
int ret;
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
- ret = regulator_set_value(mmc->vqmmc_supply, 1800000);
+ ret = regulator_set_value_clamp(mmc->vqmmc_supply,
+ 1700000, 1800000, 1950000);
else
- ret = regulator_set_value(mmc->vqmmc_supply, 3300000);
+ ret = regulator_set_value_clamp(mmc->vqmmc_supply,
+ 2700000, 3300000, 3600000);
if (ret && ret != -ENOSYS)
return ret;
}
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 87125493c0d..e718a17f94c 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -36,7 +36,6 @@
#include <dm/pinctrl.h>
#include <dt-structs.h>
#include <mapmem.h>
-#include <dm/ofnode.h>
#include <linux/iopoll.h>
#include <linux/dma-mapping.h>
@@ -1393,7 +1392,6 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev)
struct udevice *vqmmc_dev;
int ret;
- ofnode node = dev_ofnode(dev);
fdt_addr_t addr;
unsigned int val;
@@ -1407,15 +1405,15 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev)
priv->dev = dev;
priv->mode = -1;
- val = ofnode_read_u32_default(node, "fsl,tuning-step", 1);
+ val = dev_read_u32_default(dev, "fsl,tuning-step", 1);
priv->tuning_step = val;
- val = ofnode_read_u32_default(node, "fsl,tuning-start-tap",
- ESDHC_TUNING_START_TAP_DEFAULT);
+ val = dev_read_u32_default(dev, "fsl,tuning-start-tap",
+ ESDHC_TUNING_START_TAP_DEFAULT);
priv->tuning_start_tap = val;
- val = ofnode_read_u32_default(node, "fsl,strobe-dll-delay-target",
- ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
+ val = dev_read_u32_default(dev, "fsl,strobe-dll-delay-target",
+ ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
priv->strobe_dll_delay_target = val;
- val = ofnode_read_u32_default(node, "fsl,signal-voltage-switch-extra-delay-ms", 0);
+ val = dev_read_u32_default(dev, "fsl,signal-voltage-switch-extra-delay-ms", 0);
priv->signal_voltage_switch_extra_delay_ms = val;
if (dev_read_bool(dev, "broken-cd"))
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f0e38efb262..2e565560656 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2721,10 +2721,11 @@ static int mmc_startup(struct mmc *mmc)
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
/*
- * If the card has already switched to 1.8V signaling, then
- * set the signal voltage to 1.8V.
+ * If voltage switch was skipped during ACMD41 but the card is
+ * already at 1.8V (retained from a previous session, e.g. warm
+ * reboot), re-configure the host to match.
*/
- if (mmc_sd_card_using_v18(mmc)) {
+ if (!(mmc->ocr & OCR_S18R) && mmc_sd_card_using_v18(mmc)) {
/*
* During a signal voltage level switch, the clock must be gated
* for 5 ms according to the SD spec.
diff --git a/drivers/mmc/mmc_bootdev.c b/drivers/mmc/mmc_bootdev.c
index 5a1688b75d0..b382521fdeb 100644
--- a/drivers/mmc/mmc_bootdev.c
+++ b/drivers/mmc/mmc_bootdev.c
@@ -19,7 +19,7 @@ static int mmc_bootdev_bind(struct udevice *dev)
return 0;
}
-struct bootdev_ops mmc_bootdev_ops = {
+static const struct bootdev_ops mmc_bootdev_ops = {
};
static const struct udevice_id mmc_bootdev_ids[] = {
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index aaa87923604..7bdb02142a2 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -64,14 +64,13 @@ static int msm_sdc_clk_init(struct udevice *dev)
{
struct msm_sdhc *prv = dev_get_priv(dev);
const struct msm_sdhc_variant_info *var_info;
- ofnode node = dev_ofnode(dev);
ulong clk_rate;
int ret, i = 0, n_clks;
const char *clk_name;
var_info = (void *)dev_get_driver_data(dev);
- if (ofnode_read_u32(node, "max-frequency", (uint *)(&clk_rate)))
+ if (dev_read_u32(dev, "max-frequency", (uint *)(&clk_rate)))
clk_rate = 201500000;
ret = clk_get_bulk(dev, &prv->clks);
@@ -87,7 +86,7 @@ static int msm_sdc_clk_init(struct udevice *dev)
}
/* If clock-names is unspecified, then the first clock is the core clock */
- if (!ofnode_get_property(node, "clock-names", &n_clks)) {
+ if (!dev_read_prop(dev, "clock-names", &n_clks)) {
if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
log_warning("Couldn't set core clock rate: %d\n", ret);
return -EINVAL;
@@ -96,7 +95,7 @@ static int msm_sdc_clk_init(struct udevice *dev)
/* Find the index of the "core" clock */
while (i < n_clks) {
- ofnode_read_string_index(node, "clock-names", i, &clk_name);
+ dev_read_string_index(dev, "clock-names", i, &clk_name);
if (!strcmp(clk_name, "core"))
break;
i++;
diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c
index 5af1953cd14..89d511c1a6f 100644
--- a/drivers/mmc/mvebu_mmc.c
+++ b/drivers/mmc/mvebu_mmc.c
@@ -375,8 +375,8 @@ static void mvebu_window_setup(const struct mmc *mmc)
break;
}
- size = gd->bd->bi_dram[i].size;
- base = gd->bd->bi_dram[i].start;
+ size = gd->dram[i].size;
+ base = gd->dram[i].start;
if (size && attrib) {
mvebu_mmc_write(mmc, WINDOW_CTRL(i),
MVCPU_WIN_CTRL_DATA(size,
diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c
index bb4fb29424b..b4942f99a52 100644
--- a/drivers/mmc/octeontx_hsmmc.c
+++ b/drivers/mmc/octeontx_hsmmc.c
@@ -3514,7 +3514,7 @@ static u32 xlate_voltage(u32 voltage)
*/
static bool octeontx_mmc_get_valid(struct udevice *dev)
{
- const char *stat = ofnode_read_string(dev_ofnode(dev), "status");
+ const char *stat = dev_read_string(dev, "status");
if (!stat || !strncmp(stat, "ok", 2))
return true;
@@ -3536,16 +3536,13 @@ static int octeontx_mmc_get_config(struct udevice *dev)
uint low, high;
char env_name[32];
int err;
- ofnode node = dev_ofnode(dev);
int bus_width = 1;
ulong new_max_freq;
debug("%s(%s)", __func__, dev->name);
slot->cfg.name = dev->name;
- slot->cfg.f_max = ofnode_read_s32_default(dev_ofnode(dev),
- "max-frequency",
- 26000000);
+ slot->cfg.f_max = dev_read_s32_default(dev, "max-frequency", 26000000);
snprintf(env_name, sizeof(env_name), "mmc_max_frequency%d",
slot->bus_id);
@@ -3562,26 +3559,21 @@ static int octeontx_mmc_get_config(struct udevice *dev)
if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
slot->hs400_tuning_block =
- ofnode_read_s32_default(dev_ofnode(dev),
- "marvell,hs400-tuning-block",
- -1);
+ dev_read_s32_default(dev, "marvell,hs400-tuning-block", -1);
debug("%s(%s): mmc HS400 tuning block: %d\n", __func__,
dev->name, slot->hs400_tuning_block);
slot->hs200_tap_adj =
- ofnode_read_s32_default(dev_ofnode(dev),
- "marvell,hs200-tap-adjust", 0);
+ dev_read_s32_default(dev, "marvell,hs200-tap-adjust", 0);
debug("%s(%s): hs200-tap-adjust: %d\n", __func__, dev->name,
slot->hs200_tap_adj);
slot->hs400_tap_adj =
- ofnode_read_s32_default(dev_ofnode(dev),
- "marvell,hs400-tap-adjust", 0);
+ dev_read_s32_default(dev, "marvell,hs400-tap-adjust", 0);
debug("%s(%s): hs400-tap-adjust: %d\n", __func__, dev->name,
slot->hs400_tap_adj);
}
- err = ofnode_read_u32_array(dev_ofnode(dev), "voltage-ranges",
- voltages, 2);
+ err = dev_read_u32_array(dev, "voltage-ranges", voltages, 2);
if (err) {
slot->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
} else {
@@ -3601,12 +3593,12 @@ static int octeontx_mmc_get_config(struct udevice *dev)
} while (low <= high);
}
debug("%s: config voltages: 0x%x\n", __func__, slot->cfg.voltages);
- slot->slew = ofnode_read_s32_default(node, "cavium,clk-slew", -1);
- slot->drive = ofnode_read_s32_default(node, "cavium,drv-strength", -1);
+ slot->slew = dev_read_s32_default(dev, "cavium,clk-slew", -1);
+ slot->drive = dev_read_s32_default(dev, "cavium,drv-strength", -1);
gpio_request_by_name(dev, "cd-gpios", 0, &slot->cd_gpio, GPIOD_IS_IN);
- slot->cd_inverted = ofnode_read_bool(node, "cd-inverted");
+ slot->cd_inverted = dev_read_bool(dev, "cd-inverted");
gpio_request_by_name(dev, "wp-gpios", 0, &slot->wp_gpio, GPIOD_IS_IN);
- slot->wp_inverted = ofnode_read_bool(node, "wp-inverted");
+ slot->wp_inverted = dev_read_bool(dev, "wp-inverted");
if (slot->cfg.voltages & MMC_VDD_165_195) {
slot->is_1_8v = true;
slot->is_3_3v = false;
@@ -3617,7 +3609,7 @@ static int octeontx_mmc_get_config(struct udevice *dev)
slot->is_3_3v = true;
}
- bus_width = ofnode_read_u32_default(node, "bus-width", 1);
+ bus_width = dev_read_u32_default(dev, "bus-width", 1);
/* Note fall-through */
switch (bus_width) {
case 8:
@@ -3628,63 +3620,63 @@ static int octeontx_mmc_get_config(struct udevice *dev)
slot->cfg.host_caps |= MMC_MODE_1BIT;
break;
}
- if (ofnode_read_bool(node, "no-1-8-v")) {
+ if (dev_read_bool(dev, "no-1-8-v")) {
slot->is_3_3v = true;
slot->is_1_8v = false;
if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34)))
pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n",
__func__, dev->name);
}
- if (ofnode_read_bool(node, "mmc-ddr-3-3v")) {
+ if (dev_read_bool(dev, "mmc-ddr-3-3v")) {
slot->is_3_3v = true;
slot->is_1_8v = false;
if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34)))
pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n",
__func__, dev->name);
}
- if (ofnode_read_bool(node, "cap-sd-highspeed") ||
- ofnode_read_bool(node, "cap-mmc-highspeed") ||
- ofnode_read_bool(node, "sd-uhs-sdr25"))
+ if (dev_read_bool(dev, "cap-sd-highspeed") ||
+ dev_read_bool(dev, "cap-mmc-highspeed") ||
+ dev_read_bool(dev, "sd-uhs-sdr25"))
slot->cfg.host_caps |= MMC_MODE_HS;
if (slot->cfg.f_max >= 50000000 &&
slot->cfg.host_caps & MMC_MODE_HS)
slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
- if (ofnode_read_bool(node, "sd-uhs-sdr50"))
+ if (dev_read_bool(dev, "sd-uhs-sdr50"))
slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
- if (ofnode_read_bool(node, "sd-uhs-ddr50"))
+ if (dev_read_bool(dev, "sd-uhs-ddr50"))
slot->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz |
MMC_MODE_DDR_52MHz;
if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
if (!slot->is_asim && !slot->is_emul) {
- if (ofnode_read_bool(node, "mmc-hs200-1_8v"))
+ if (dev_read_bool(dev, "mmc-hs200-1_8v"))
slot->cfg.host_caps |= MMC_MODE_HS200 |
MMC_MODE_HS_52MHz;
- if (ofnode_read_bool(node, "mmc-hs400-1_8v"))
+ if (dev_read_bool(dev, "mmc-hs400-1_8v"))
slot->cfg.host_caps |= MMC_MODE_HS400 |
MMC_MODE_HS_52MHz |
MMC_MODE_HS200 |
MMC_MODE_DDR_52MHz;
slot->cmd_out_hs200_delay =
- ofnode_read_u32_default(node,
+ dev_read_u32_default(dev,
"marvell,cmd-out-hs200-dly",
MMC_DEFAULT_HS200_CMD_OUT_DLY);
debug("%s(%s): HS200 cmd out delay: %d\n",
__func__, dev->name, slot->cmd_out_hs200_delay);
slot->data_out_hs200_delay =
- ofnode_read_u32_default(node,
+ dev_read_u32_default(dev,
"marvell,data-out-hs200-dly",
MMC_DEFAULT_HS200_DATA_OUT_DLY);
debug("%s(%s): HS200 data out delay: %d\n",
__func__, dev->name, slot->data_out_hs200_delay);
slot->cmd_out_hs400_delay =
- ofnode_read_u32_default(node,
+ dev_read_u32_default(dev,
"marvell,cmd-out-hs400-dly",
MMC_DEFAULT_HS400_CMD_OUT_DLY);
debug("%s(%s): HS400 cmd out delay: %d\n",
__func__, dev->name, slot->cmd_out_hs400_delay);
slot->data_out_hs400_delay =
- ofnode_read_u32_default(node,
+ dev_read_u32_default(dev,
"marvell,data-out-hs400-dly",
MMC_DEFAULT_HS400_DATA_OUT_DLY);
debug("%s(%s): HS400 data out delay: %d\n",
@@ -3692,12 +3684,10 @@ static int octeontx_mmc_get_config(struct udevice *dev)
}
}
- slot->disable_ddr = ofnode_read_bool(node, "marvell,disable-ddr");
- slot->non_removable = ofnode_read_bool(node, "non-removable");
- slot->cmd_clk_skew = ofnode_read_u32_default(node,
- "cavium,cmd-clk-skew", 0);
- slot->dat_clk_skew = ofnode_read_u32_default(node,
- "cavium,dat-clk-skew", 0);
+ slot->disable_ddr = dev_read_bool(dev, "marvell,disable-ddr");
+ slot->non_removable = dev_read_bool(dev, "non-removable");
+ slot->cmd_clk_skew = dev_read_u32_default(dev, "cavium,cmd-clk-skew", 0);
+ slot->dat_clk_skew = dev_read_u32_default(dev, "cavium,dat-clk-skew", 0);
debug("%s(%s): host caps: 0x%x\n", __func__,
dev->name, slot->cfg.host_caps);
return 0;
@@ -3843,7 +3833,6 @@ static int octeontx_mmc_host_probe(struct udevice *dev)
pr_err("%s: No device tree information found\n", __func__);
return -1;
}
- host->node = dev_ofnode(dev);
host->last_slotid = -1;
#if !defined(CONFIG_ARCH_OCTEON)
if (otx_is_platform(PLATFORM_ASIM))
@@ -3851,9 +3840,7 @@ static int octeontx_mmc_host_probe(struct udevice *dev)
if (otx_is_platform(PLATFORM_EMULATOR))
host->is_emul = true;
#endif
- host->dma_wait_delay =
- ofnode_read_u32_default(dev_ofnode(dev),
- "marvell,dma-wait-delay", 1);
+ host->dma_wait_delay = dev_read_u32_default(dev, "marvell,dma-wait-delay", 1);
/* Force reset of eMMC */
writeq(0, host->base_addr + MIO_EMM_CFG());
debug("%s: Clearing MIO_EMM_CFG\n", __func__);
@@ -3922,13 +3909,12 @@ static int octeontx_mmc_host_child_pre_probe(struct udevice *dev)
struct octeontx_mmc_host *host = dev_get_priv(dev_get_parent(dev));
struct octeontx_mmc_slot *slot;
struct mmc_uclass_priv *upriv;
- ofnode node = dev_ofnode(dev);
u32 bus_id;
char name[16];
int err;
debug("%s(%s) Pre-Probe\n", __func__, dev->name);
- if (ofnode_read_u32(node, "reg", &bus_id)) {
+ if (dev_read_u32(dev, "reg", &bus_id)) {
pr_err("%s(%s): Error: \"reg\" not found in device tree\n",
__func__, dev->name);
return -1;
diff --git a/drivers/mmc/octeontx_hsmmc.h b/drivers/mmc/octeontx_hsmmc.h
index 9849121f174..c374ce18838 100644
--- a/drivers/mmc/octeontx_hsmmc.h
+++ b/drivers/mmc/octeontx_hsmmc.h
@@ -123,7 +123,6 @@ struct octeontx_mmc_host {
union mio_emm_cfg emm_cfg;
u64 timing_taps;
struct mmc *last_mmc; /** Last mmc used */
- ofnode node;
int cur_slotid;
int last_slotid;
int max_width;
diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c
index d446c55f72b..82e393fd9d6 100644
--- a/drivers/mmc/pci_mmc.c
+++ b/drivers/mmc/pci_mmc.c
@@ -137,11 +137,11 @@ static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev,
return 0;
}
-struct acpi_ops pci_mmc_acpi_ops = {
#ifdef CONFIG_ACPIGEN
+static const struct acpi_ops pci_mmc_acpi_ops = {
.fill_ssdt = pci_mmc_acpi_fill_ssdt,
-#endif
};
+#endif
static const struct udevice_id pci_mmc_match[] = {
{ .compatible = "intel,apl-sd", .data = TYPE_SD },
diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
index a76f9e8d6bd..5bbc18dfa51 100644
--- a/drivers/mmc/sdhci-cadence.c
+++ b/drivers/mmc/sdhci-cadence.c
@@ -39,9 +39,6 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
};
-static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
- unsigned int opcode);
-
static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
u8 addr, u8 data)
{
@@ -158,93 +155,8 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
sdhci_cdns6_phy_adj(mmc->dev, plat, mmc->selected_mode);
}
-static __maybe_unused bool sdhci_cdns_sd_needs_tuning(struct mmc *mmc)
-{
- struct sdhci_cdns_plat *plat = dev_get_plat(mmc->dev);
-
- if (!IS_SD(mmc))
- return false;
-
- if (!dev_read_bool(mmc->dev, "cdns,sd-hs-tuning"))
- return false;
-
- /* Already tuned for this mode */
- if (plat->tuned_mode == mmc->selected_mode)
- return false;
-
- switch (mmc->selected_mode) {
- case SD_HS:
- return mmc->bus_width == 4;
- /* Add future modes here, e.g.:
- * case UHS_SDR50:
- * return true;
- */
- default:
- return false;
- }
-}
-
-static int sdhci_cdns_set_ios_post(struct sdhci_host *host)
-{
- struct mmc *mmc = host->mmc;
- struct sdhci_cdns_plat *plat = dev_get_plat(mmc->dev);
- int ret __maybe_unused;
- /*
- * The SD6HC soft PHY requires runtime DLL delay calibration
- * for SD High Speed mode. The default PHY_DLL_SLAVE_CTRL_REG
- * values (READ_DQS_CMD_DELAY and READ_DQS_DELAY = 0) do not
- * provide sufficient timing margin due to PVT and board trace
- * variations.
- *
- * Tuning is performed once per entry into SD_HS mode
- * (tracked by plat->tuned_mode state). The calibrated PHY delay
- * values remain valid while the card stays in SD_HS mode, and
- * leaving that tuned mode clears the state so re-entering SD_HS
- * triggers tuning again.
- *
- * This must be done in set_ios_post (not set_control_reg)
- * because the SDHCI controller must already be operating at
- * the target bus width, clock, and speed mode before CMD19
- * tuning commands can succeed.
- */
-
- if (IS_ENABLED(CONFIG_MMC_SUPPORTS_TUNING)) {
- if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_420 &&
- sdhci_cdns_sd_needs_tuning(mmc)) {
- ret = sdhci_cdns_execute_tuning(mmc->dev,
- MMC_CMD_SEND_TUNING_BLOCK);
- if (ret) {
- dev_err(mmc->dev,
- "SD_HS tuning failed (ret=%d), using default PHY\n",
- ret);
- /* Restore default PHY settings and avoid retrying in this mode */
- sdhci_cdns6_phy_adj(mmc->dev, plat,
- mmc->selected_mode);
- plat->tuned_mode = mmc->selected_mode;
- plat->tuned_dll_slave_ctrl = sdhci_cdns6_phy_get_dll_slave(plat);
- return 0;
- }
- /*
- * Tuning succeeded. The tuned_mode is already set by
- * execute_tuning(), so the tuned value will be preserved
- * across subsequent PHY reconfigurations.
- */
- dev_dbg(mmc->dev, "SD_HS tuning successful\n");
- }
-
- /* Reset when mode changes away from a tuned mode */
- if (mmc->selected_mode != plat->tuned_mode) {
- plat->tuned_mode = MMC_MODES_END;
- plat->tuned_dll_slave_ctrl = 0;
- }
- }
-
- return 0;
-}
-
static const struct sdhci_ops sdhci_cdns_ops = {
.set_control_reg = sdhci_cdns_set_control_reg,
- .set_ios_post = sdhci_cdns_set_ios_post,
};
static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
@@ -292,7 +204,6 @@ static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
int cur_streak = 0;
int max_streak = 0;
int end_of_streak = 0;
- int ret;
int i;
/*
@@ -318,24 +229,7 @@ static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
return -EIO;
}
- ret = sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
- if (ret)
- return ret;
-
- /*
- * Mark this mode as tuned. This is critical for both driver tuning
- * (SD_HS via set_ios_post) and framework tuning (UHS_SDR104, MMC_HS_200,
- * MMC_HS_400) so that subsequent PHY reconfigurations restore the
- * calibrated DLL value instead of overwriting with DT defaults.
- *
- * For HS400, tuning is performed while the controller is in HS200 mode
- * (mmc->selected_mode == MMC_HS_200 and mmc->hs400_tuning == true).
- * Record the tuned mode as MMC_HS_400 so the calibrated DLL value is
- * preserved across the HS200→HS400 transition.
- */
- plat->tuned_mode = mmc->hs400_tuning ? MMC_HS_400 : mmc->selected_mode;
-
- return 0;
+ return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
}
static struct dm_mmc_ops sdhci_cdns_mmc_ops;
diff --git a/drivers/mmc/sdhci-cadence.h b/drivers/mmc/sdhci-cadence.h
index ea517491860..7101f00b75b 100644
--- a/drivers/mmc/sdhci-cadence.h
+++ b/drivers/mmc/sdhci-cadence.h
@@ -7,8 +7,6 @@
#ifndef SDHCI_CADENCE_H_
#define SDHCI_CADENCE_H_
-#include <mmc.h>
-
/* HRS - Host Register Set (specific to Cadence) */
/* PHY access port */
#define SDHCI_CDNS_HRS04 0x10
@@ -62,13 +60,10 @@ struct sdhci_cdns_plat {
struct mmc_config cfg;
struct mmc mmc;
void __iomem *hrs_addr;
- enum bus_mode tuned_mode;
- u32 tuned_dll_slave_ctrl;
};
int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode);
int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat);
int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val);
-u32 sdhci_cdns6_phy_get_dll_slave(struct sdhci_cdns_plat *plat);
#endif
diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c
index c8b42532e17..ca1086e2359 100644
--- a/drivers/mmc/sdhci-cadence6.c
+++ b/drivers/mmc/sdhci-cadence6.c
@@ -173,30 +173,6 @@ static void sdhci_cdns6_write_phy_reg(struct sdhci_cdns_plat *plat, u32 addr, u3
writel(val, plat->hrs_addr + SDHCI_CDNS_HRS05);
}
-static bool sdhci_cdns6_mode_is_tuned(struct sdhci_cdns_plat *plat, u32 mode)
-{
- /*
- * Check if the given mode has a valid tuned DLL value.
- * Only modes that support tuning (driver or framework) can have
- * valid tuned values. This prevents the initial state (tuned_mode=0)
- * from falsely matching MMC_LEGACY.
- */
- if (plat->tuned_mode != mode)
- return false;
-
- switch (mode) {
- case SD_HS: /* Driver tuning via set_ios_post */
- case UHS_SDR50: /* Future driver tuning support */
- case UHS_SDR104: /* Framework tuning */
- case MMC_HS_200: /* Framework tuning */
- case MMC_HS_400: /* Framework tuning */
- case MMC_HS_400_ES: /* Framework tuning */
- return true;
- default:
- return false;
- }
-}
-
static int sdhci_cdns6_reset_phy_dll(struct sdhci_cdns_plat *plat, bool reset)
{
void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS09;
@@ -283,18 +259,7 @@ int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 m
sdhci_cdns6_write_phy_reg(plat, PHY_DQS_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[0].val);
sdhci_cdns6_write_phy_reg(plat, PHY_GATE_LPBK_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[1].val);
sdhci_cdns6_write_phy_reg(plat, PHY_DLL_MASTER_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[4].val);
- if (sdhci_cdns6_mode_is_tuned(plat, mode)) {
- /*
- * Use previously saved tuned DLL slave control value.
- * Note: 0 is a valid tuned value (e.g., optimal tap at position 0),
- * so we check both mode match AND that it's a tunable mode.
- */
- sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR,
- plat->tuned_dll_slave_ctrl);
- } else {
- sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR,
- sdhci_cdns6_phy_cfgs[2].val);
- }
+ sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[2].val);
/* Switch Off the DLL Reset */
ret = sdhci_cdns6_reset_phy_dll(plat, false);
@@ -353,9 +318,6 @@ int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val)
sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, tmp);
- /* Store tuned DLL slave control value which will be reapplied via set_ios(). */
- plat->tuned_dll_slave_ctrl = tmp;
-
/* Switch Off the DLL Reset */
ret = sdhci_cdns6_reset_phy_dll(plat, false);
if (ret) {
@@ -365,8 +327,3 @@ int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val)
return 0;
}
-
-u32 sdhci_cdns6_phy_get_dll_slave(struct sdhci_cdns_plat *plat)
-{
- return sdhci_cdns6_read_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR);
-}
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 648dfa4b5ef..71a6d8ea2f5 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -215,7 +215,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
u32 mask, flags, mode = 0;
unsigned int time = 0;
int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
- ulong start = get_timer(0);
+ ulong start;
host->start_addr = 0;
/* Timeout unit - ms */
@@ -551,7 +551,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
void sdhci_set_voltage(struct sdhci_host *host)
{
- if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
+ if (CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)) {
struct mmc *mmc = (struct mmc *)host->mmc;
u32 ctrl;
diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c
index 0e4902fab77..6aa73792f96 100644
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -537,10 +537,9 @@ static int xenon_sdhci_of_to_plat(struct udevice *dev)
host->ioaddr = dev_read_addr_ptr(dev);
if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
- priv->pad_ctrl_reg = devfdt_get_addr_index_ptr(dev, 1);
+ priv->pad_ctrl_reg = dev_read_addr_index_ptr(dev, 1);
- name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
- NULL);
+ name = ofnode_get_property(dev_ofnode(dev), "marvell,pad-type", NULL);
if (name) {
if (0 == strncmp(name, "sd", 2)) {
priv->pad_type = SOC_PAD_SD;
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-13 07:32:26 +0000