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-rw-r--r--drivers/ram/aspeed/Kconfig16
-rw-r--r--drivers/ram/aspeed/Makefile1
-rw-r--r--drivers/ram/aspeed/sdram_ast2600.c15
-rw-r--r--drivers/ram/aspeed/sdram_ast2700.c19
-rw-r--r--drivers/ram/octeon/Kconfig6
-rw-r--r--drivers/ram/stm32mp1/Kconfig36
6 files changed, 49 insertions, 44 deletions
diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig
index e4918460de6..fa5c890bb7a 100644
--- a/drivers/ram/aspeed/Kconfig
+++ b/drivers/ram/aspeed/Kconfig
@@ -4,19 +4,19 @@ menuconfig ASPEED_RAM
depends on ARCH_ASPEED || TARGET_ASPEED_AST2700_IBEX
default ARCH_ASPEED
help
- Configuration options for DDR SDRAM on ASPEED systems.
+ Configuration options for DDR SDRAM on ASPEED systems.
- RAM initialisation is always built in for the platform. This menu
- allows customisation of the configuration used.
+ RAM initialisation is always built in for the platform. This menu
+ allows customisation of the configuration used.
config ASPEED_DDR4_DUALX8
bool "Enable Dual X8 DDR4 die"
depends on ASPEED_RAM
help
- Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM
- SRAM controller needs to know if the memory chip mounted on the
- board is dual x8 die or not, otherwise it may get the wrong
- size of the memory space.
+ Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM
+ SRAM controller needs to know if the memory chip mounted on the
+ board is dual x8 die or not, otherwise it may get the wrong
+ size of the memory space.
config ASPEED_BYPASS_SELFTEST
depends on ASPEED_RAM
@@ -77,7 +77,7 @@ choice
prompt "AST2700 DDR target date rate"
default ASPEED_DDR_3200
depends on ASPEED_RAM
- depends on TARGET_ASPEED_AST2700_IBEX
+ depends on ASPEED_AST2700 || TARGET_ASPEED_AST2700_IBEX
config ASPEED_DDR_1600
bool "1600 Mbps"
diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile
index 1f0b22c8e9f..d29e2154ce9 100644
--- a/drivers/ram/aspeed/Makefile
+++ b/drivers/ram/aspeed/Makefile
@@ -2,4 +2,5 @@
#
obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o
obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o
+obj-$(CONFIG_ASPEED_AST2700) += sdram_ast2700.o
obj-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += sdram_ast2700.o
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index 55e80fba3dc..2cf9296468d 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -1076,10 +1076,10 @@ static int ast2600_sdrammc_probe(struct udevice *dev)
return ret;
}
- priv->scu = devfdt_get_addr_ptr(clk_dev);
- if (IS_ERR(priv->scu)) {
+ priv->scu = dev_read_addr_ptr(clk_dev);
+ if (!priv->scu) {
debug("%s(): can't get SCU\n", __func__);
- return PTR_ERR(priv->scu);
+ return -ENODEV;
}
if (readl(&priv->scu->dram_hdshk) & SCU_DRAM_HDSHK_RDY) {
@@ -1136,12 +1136,11 @@ static int ast2600_sdrammc_of_to_plat(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
- priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
- priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
- priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2);
+ priv->regs = (void *)(uintptr_t)dev_read_addr_index(dev, 0);
+ priv->phy_setting = (void *)(uintptr_t)dev_read_addr_index(dev, 1);
+ priv->phy_status = (void *)(uintptr_t)dev_read_addr_index(dev, 2);
- priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
- "clock-frequency", 0);
+ priv->clock_rate = ofnode_read_s32_default(dev_ofnode(dev), "clock-frequency", 0);
if (!priv->clock_rate) {
debug("DDR Clock Rate not defined\n");
return -EINVAL;
diff --git a/drivers/ram/aspeed/sdram_ast2700.c b/drivers/ram/aspeed/sdram_ast2700.c
index 4a019c4edb1..8605a92abb2 100644
--- a/drivers/ram/aspeed/sdram_ast2700.c
+++ b/drivers/ram/aspeed/sdram_ast2700.c
@@ -14,6 +14,11 @@
#include <linux/sizes.h>
#include <ram.h>
+__weak int fmc_hdr_get_prebuilt(u32 type, u32 *ofst, u32 *size)
+{
+ return -ENOSYS;
+}
+
enum ddr_type {
DDR4_1600 = 0x0,
DDR4_2400,
@@ -128,13 +133,13 @@ static size_t ast2700_sdrammc_get_vga_mem_size(struct sdrammc *sdrammc)
reg = readl(scu0 + SCU0_PCI_MISC70);
if (reg & SCU0_PCI_MISC70_EN_PCIEVGA0) {
- debug("VGA0:%dMB\n", vga_memsz[sel] / SZ_1M);
+ debug("VGA0:%zuMB\n", vga_memsz[sel] / SZ_1M);
dual++;
}
reg = readl(scu0 + SCU0_PCI_MISC80);
if (reg & SCU0_PCI_MISC80_EN_PCIEVGA1) {
- debug("VGA1:%dMB\n", vga_memsz[sel] / SZ_1M);
+ debug("VGA1:%zuMB\n", vga_memsz[sel] / SZ_1M);
dual++;
}
@@ -560,7 +565,7 @@ void dwc_get_mailbox(struct sdrammc *sdrammc, const int mode, u32 *mbox)
dwc_ddrphy_apb_wr(0xd0031, 1);
}
-uint32_t dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half)
+u32 dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half)
{
u32 data_word;
@@ -727,7 +732,7 @@ int dwc_ddrphy_phyinit_userCustom_D_loadIMEM(struct sdrammc *sdrammc, const int
fmc_hdr_get_prebuilt(pb_type, &imem_ofst, &imem_size);
memcpy(sdrammc->phy + (DWC_PHY_IMEM_OFST << 1),
- (void *)(0x20000000 + imem_ofst), imem_size);
+ (void *)(uintptr_t)(0x20000000 + imem_ofst), imem_size);
return 0;
}
@@ -746,7 +751,7 @@ int dwc_ddrphy_phyinit_userCustom_F_loadDMEM(struct sdrammc *sdrammc,
fmc_hdr_get_prebuilt(pb_type, &dmem_ofst, &dmem_size);
memcpy(sdrammc->phy + (DWC_PHY_DMEM_OFST << 1),
- (void *)(0x20000000 + dmem_ofst), dmem_size);
+ (void *)(uintptr_t)(0x20000000 + dmem_ofst), dmem_size);
return 0;
}
@@ -956,13 +961,13 @@ static int ast2700_sdrammc_of_to_plat(struct udevice *dev)
ofnode node;
int rc;
- sdrammc->regs = (struct sdrammc_regs *)devfdt_get_addr_index(dev, 0);
+ sdrammc->regs = (struct sdrammc_regs *)dev_read_addr_index(dev, 0);
if (sdrammc->regs == (void *)FDT_ADDR_T_NONE) {
debug("cannot map DRAM register\n");
return -ENODEV;
}
- sdrammc->phy = (void *)devfdt_get_addr_index(dev, 1);
+ sdrammc->phy = (void *)dev_read_addr_index(dev, 1);
if (sdrammc->phy == (void *)FDT_ADDR_T_NONE) {
debug("cannot map PHY memory\n");
return -ENODEV;
diff --git a/drivers/ram/octeon/Kconfig b/drivers/ram/octeon/Kconfig
index f19957293f9..37bf4851400 100644
--- a/drivers/ram/octeon/Kconfig
+++ b/drivers/ram/octeon/Kconfig
@@ -2,14 +2,14 @@ config RAM_OCTEON
bool "Ram drivers for Octeon SoCs"
depends on RAM && ARCH_OCTEON
help
- This enables support for RAM drivers for Octeon SoCs.
+ This enables support for RAM drivers for Octeon SoCs.
if RAM_OCTEON
config RAM_OCTEON_DDR4
bool "Octeon III DDR4 RAM support"
help
- This enables support for DDR4 RAM suppoort for Octeon III. This does
- not include support for Octeon CN70XX.
+ This enables support for DDR4 RAM suppoort for Octeon III. This does
+ not include support for Octeon CN70XX.
endif # RAM_OCTEON
diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig
index 1aaf064c30c..76bd17a8874 100644
--- a/drivers/ram/stm32mp1/Kconfig
+++ b/drivers/ram/stm32mp1/Kconfig
@@ -6,43 +6,43 @@ config STM32MP1_DDR
select SPL_RAM if SPL
default y
help
- activate STM32MP1 DDR controller driver for STM32MP1 soc
- family: support for LPDDR2, LPDDR3 and DDR3
- the SDRAM parameters for controleur and phy need to be provided
- in device tree (computed by DDR tuning tools)
+ activate STM32MP1 DDR controller driver for STM32MP1 soc
+ family: support for LPDDR2, LPDDR3 and DDR3
+ the SDRAM parameters for controleur and phy need to be provided
+ in device tree (computed by DDR tuning tools)
config STM32MP1_DDR_INTERACTIVE
bool "STM32MP1 DDR driver : interactive support"
depends on STM32MP1_DDR
help
- activate interactive support in STM32MP1 DDR controller driver
- used for DDR tuning tools
- to enter in intercative mode type 'd' during SPL DDR driver
- initialisation
+ activate interactive support in STM32MP1 DDR controller driver
+ used for DDR tuning tools
+ to enter in intercative mode type 'd' during SPL DDR driver
+ initialisation
config STM32MP1_DDR_INTERACTIVE_FORCE
bool "STM32MP1 DDR driver : force interactive mode"
depends on STM32MP1_DDR_INTERACTIVE
help
- force interactive mode in STM32MP1 DDR controller driver
- skip the polling of character 'd' in console
- useful when SPL is loaded in sysram
- directly by programmer
+ force interactive mode in STM32MP1 DDR controller driver
+ skip the polling of character 'd' in console
+ useful when SPL is loaded in sysram
+ directly by programmer
config STM32MP1_DDR_TESTS
bool "STM32MP1 DDR driver : tests support"
depends on STM32MP1_DDR_INTERACTIVE
default y
help
- activate test support for interactive support in
- STM32MP1 DDR controller driver: command test
+ activate test support for interactive support in
+ STM32MP1 DDR controller driver: command test
config STM32MP1_DDR_TUNING
bool "STM32MP1 DDR driver : support of tuning"
depends on STM32MP1_DDR_INTERACTIVE
default y
help
- activate tuning command in STM32MP1 DDR interactive mode
- used for DDR tuning tools
- - DQ Deskew algorithm
- - DQS Trimming
+ activate tuning command in STM32MP1 DDR interactive mode
+ used for DDR tuning tools
+ - DQ Deskew algorithm
+ - DQS Trimming
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-13 04:03:36 +0000