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-rw-r--r--drivers/serial/Kconfig18
-rw-r--r--drivers/serial/serial_cortina.c8
-rw-r--r--drivers/serial/serial_goldfish.c6
-rw-r--r--drivers/serial/serial_lpuart.c25
-rw-r--r--drivers/serial/serial_msm_geni.c4
-rw-r--r--drivers/serial/serial_sh.c2
6 files changed, 35 insertions, 28 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 5f8b98f0704..e221800d5d0 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -759,11 +759,11 @@ config MVEBU_A3700_UART
config MCFUART
bool "Freescale ColdFire UART support"
depends on M68K
- help
- Choose this option to add support for UART driver on the ColdFire
- SoC's family. The serial communication channel provides a full-duplex
- asynchronous/synchronous receiver and transmitter deriving an
- operating frequency from the internal bus clock or an external clock.
+ help
+ Choose this option to add support for UART driver on the ColdFire
+ SoC's family. The serial communication channel provides a full-duplex
+ asynchronous/synchronous receiver and transmitter deriving an
+ operating frequency from the internal bus clock or an external clock.
config MXC_UART
bool "IMX serial port support"
@@ -1024,12 +1024,12 @@ config OCTEON_SERIAL_BOOTCMD
bool "MIPS Octeon PCI remote bootcmd input"
depends on ARCH_OCTEON
depends on DM_SERIAL
- select SYS_IS_IN_ENV
+ select SYS_CONSOLE_IS_IN_ENV
select CONSOLE_MUX
help
- This driver supports remote input over the PCIe bus from a host
- to U-Boot for entering commands. It is utilized by the host
- commands 'oct-remote-load' and 'oct-remote-bootcmd'.
+ This driver supports remote input over the PCIe bus from a host
+ to U-Boot for entering commands. It is utilized by the host
+ commands 'oct-remote-load' and 'oct-remote-bootcmd'.
config OCTEON_SERIAL_PCIE_CONSOLE
bool "MIPS Octeon PCIe remote console"
diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c
index 3ae8fb46584..de8af5b0574 100644
--- a/drivers/serial/serial_cortina.c
+++ b/drivers/serial/serial_cortina.c
@@ -83,11 +83,13 @@ int ca_serial_setbrg(struct udevice *dev, int baudrate)
static int ca_serial_getc(struct udevice *dev)
{
struct ca_uart_priv *priv = dev_get_priv(dev);
- int ch;
+ unsigned int status;
- ch = readl(priv->base + URX_DATA) & 0xFF;
+ status = readl(priv->base + UINFO);
+ if (status & UINFO_RX_FIFO_EMPTY)
+ return -EAGAIN;
- return (int)ch;
+ return readl(priv->base + URX_DATA) & 0xFF;
}
static int ca_serial_putc(struct udevice *dev, const char ch)
diff --git a/drivers/serial/serial_goldfish.c b/drivers/serial/serial_goldfish.c
index 91dc040fcf2..732f167caae 100644
--- a/drivers/serial/serial_goldfish.c
+++ b/drivers/serial/serial_goldfish.c
@@ -74,8 +74,10 @@ static int goldfish_serial_of_to_plat(struct udevice *dev)
fdt_addr_t addr;
addr = dev_read_addr(dev);
- if (addr != FDT_ADDR_T_NONE)
- plat->reg = addr;
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ plat->reg = addr;
return 0;
}
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 9fdb6503085..917445e1ee2 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -53,11 +53,7 @@
#define FIFO_RXSIZE_MASK 0x7
#define FIFO_RXSIZE_OFF 0
#define FIFO_TXFE 0x80
-#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
#define FIFO_RXFE 0x08
-#else
-#define FIFO_RXFE 0x40
-#endif
#define WATER_TXWATER_OFF 0
#define WATER_RXWATER_OFF 16
@@ -366,10 +362,14 @@ static int _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
static int _lpuart32_serial_tstc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl_reg32 *base = plat->reg;
- u32 water;
+ u32 stat, water;
lpuart_read32(plat->flags, &base->water, &water);
+ lpuart_read32(plat->flags, &base->stat, &stat);
+ if (stat & STAT_OR)
+ lpuart_write32(plat->flags, &base->stat, STAT_OR);
+
if ((water >> 24) == 0)
return 0;
@@ -523,8 +523,7 @@ static int lpuart_serial_probe(struct udevice *dev)
static int lpuart_serial_of_to_plat(struct udevice *dev)
{
struct lpuart_serial_plat *plat = dev_get_plat(dev);
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
+ ofnode node = dev_ofnode(dev);
fdt_addr_t addr;
addr = dev_read_addr(dev);
@@ -534,18 +533,18 @@ static int lpuart_serial_of_to_plat(struct udevice *dev)
plat->reg = (void *)addr;
plat->flags = dev_get_driver_data(dev);
- if (fdtdec_get_bool(blob, node, "little-endian"))
+ if (ofnode_read_bool(node, "little-endian"))
plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
- if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
+ if (ofnode_device_is_compatible(node, "fsl,ls1021a-lpuart"))
plat->devtype = DEV_LS1021A;
- else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
+ else if (ofnode_device_is_compatible(node, "fsl,imx7ulp-lpuart"))
plat->devtype = DEV_MX7ULP;
- else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
+ else if (ofnode_device_is_compatible(node, "fsl,vf610-lpuart"))
plat->devtype = DEV_VF610;
- else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
+ else if (ofnode_device_is_compatible(node, "fsl,imx8qm-lpuart"))
plat->devtype = DEV_IMX8;
- else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
+ else if (ofnode_device_is_compatible(node, "fsl,imxrt-lpuart"))
plat->devtype = DEV_IMXRT;
return 0;
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 3dca581f68f..ae4015e0fdc 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -55,6 +55,7 @@
#define SE_UART_RX_PARITY_CFG 0x2a8
#define DEF_TX_WM 2
+#define DEF_RX_WM 2
/* GENI_FORCE_DEFAULT_REG fields */
#define UART_START_READ 0x1
@@ -345,6 +346,7 @@ static void qcom_geni_serial_start_rx(struct udevice *dev)
geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
+ writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG);
setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
}
@@ -373,6 +375,7 @@ static void msm_geni_serial_setup_rx(struct udevice *dev)
geni_se_setup_s_cmd(priv->base, UART_START_READ, 0);
+ writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG);
setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
}
@@ -616,6 +619,7 @@ static inline void _debug_uart_init(void)
phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE);
geni_serial_init(&init_dev);
+ writel(DEF_RX_WM, base + SE_GENI_RX_WATERMARK_REG);
geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE);
qcom_geni_serial_start_tx(base);
}
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index bc205234e24..7debff6cb3a 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -257,7 +257,7 @@ static int sh_serial_of_to_plat(struct udevice *dev)
int ret;
addr = dev_read_addr(dev);
- if (!addr)
+ if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = addr;
generated by cgit v1.3.1 (git 2.54.0) at 2026-08-10 22:33:57 +0000