diff options
Diffstat (limited to 'drivers/timer')
| -rw-r--r-- | drivers/timer/Kconfig | 19 | ||||
| -rw-r--r-- | drivers/timer/Makefile | 8 | ||||
| -rw-r--r-- | drivers/timer/altera_timer.c | 104 | ||||
| -rw-r--r-- | drivers/timer/timer-uclass.c | 42 |
4 files changed, 173 insertions, 0 deletions
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig new file mode 100644 index 00000000000..97c41280052 --- /dev/null +++ b/drivers/timer/Kconfig @@ -0,0 +1,19 @@ +menu "Timer Support" + +config TIMER + bool "Enable Driver Model for Timer drivers" + depends on DM + help + Enable driver model for Timer access. It uses the same API as + lib/time.c. But now implemented by the uclass. The first timer + will be used. The timer is usually a 32 bits free-running up + counter. There may be no real tick, and no timer interrupt. + +config ALTERA_TIMER + bool "Altera Timer support" + depends on TIMER + help + Select this to enable an timer for Altera devices. Please find + details on the "Embedded Peripherals IP User Guide" of Altera. + +endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile new file mode 100644 index 00000000000..ae66c07d0e4 --- /dev/null +++ b/drivers/timer/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015 Thomas Chou <[email protected]> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_TIMER) += timer-uclass.o +obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o diff --git a/drivers/timer/altera_timer.c b/drivers/timer/altera_timer.c new file mode 100644 index 00000000000..2ef9ad6934e --- /dev/null +++ b/drivers/timer/altera_timer.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, [email protected]. + * + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct altera_timer_regs { + u32 status; /* Timer status reg */ + u32 control; /* Timer control reg */ + u32 periodl; /* Timeout period low */ + u32 periodh; /* Timeout period high */ + u32 snapl; /* Snapshot low */ + u32 snaph; /* Snapshot high */ +}; + +struct altera_timer_platdata { + struct altera_timer_regs *regs; + unsigned long clock_rate; +}; + +/* control register */ +#define ALTERA_TIMER_CONT (1 << 1) /* Continuous mode */ +#define ALTERA_TIMER_START (1 << 2) /* Start timer */ +#define ALTERA_TIMER_STOP (1 << 3) /* Stop timer */ + +static int altera_timer_get_count(struct udevice *dev, unsigned long *count) +{ + struct altera_timer_platdata *plat = dev->platdata; + struct altera_timer_regs *const regs = plat->regs; + u32 val; + + /* Trigger update */ + writel(0x0, ®s->snapl); + + /* Read timer value */ + val = readl(®s->snapl) & 0xffff; + val |= (readl(®s->snaph) & 0xffff) << 16; + *count = ~val; + + return 0; +} + +static int altera_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct altera_timer_platdata *plat = dev->platdata; + struct altera_timer_regs *const regs = plat->regs; + + uc_priv->clock_rate = plat->clock_rate; + + writel(0, ®s->status); + writel(0, ®s->control); + writel(ALTERA_TIMER_STOP, ®s->control); + + writel(0xffff, ®s->periodl); + writel(0xffff, ®s->periodh); + writel(ALTERA_TIMER_CONT | ALTERA_TIMER_START, ®s->control); + + return 0; +} + +static int altera_timer_ofdata_to_platdata(struct udevice *dev) +{ + struct altera_timer_platdata *plat = dev_get_platdata(dev); + + plat->regs = ioremap(dev_get_addr(dev), + sizeof(struct altera_timer_regs)); + plat->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 0); + + return 0; +} + +static const struct timer_ops altera_timer_ops = { + .get_count = altera_timer_get_count, +}; + +static const struct udevice_id altera_timer_ids[] = { + { .compatible = "altr,timer-1.0", }, + { } +}; + +U_BOOT_DRIVER(altera_timer) = { + .name = "altera_timer", + .id = UCLASS_TIMER, + .of_match = altera_timer_ids, + .ofdata_to_platdata = altera_timer_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_timer_platdata), + .probe = altera_timer_probe, + .ops = &altera_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c new file mode 100644 index 00000000000..12aee5ba4e8 --- /dev/null +++ b/drivers/timer/timer-uclass.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2015 Thomas Chou <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> + +/* + * Implement a Timer uclass to work with lib/time.c. The timer is usually + * a 32 bits free-running up counter. The get_rate() method is used to get + * the input clock frequency of the timer. The get_count() method is used + * get the current 32 bits count value. If the hardware is counting down, + * the value should be inversed inside the method. There may be no real + * tick, and no timer interrupt. + */ + +int timer_get_count(struct udevice *dev, unsigned long *count) +{ + const struct timer_ops *ops = device_get_ops(dev); + + if (!ops->get_count) + return -ENOSYS; + + return ops->get_count(dev, count); +} + +unsigned long timer_get_rate(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + return uc_priv->clock_rate; +} + +UCLASS_DRIVER(timer) = { + .id = UCLASS_TIMER, + .name = "timer", + .per_device_auto_alloc_size = sizeof(struct timer_dev_priv), +}; |