diff options
Diffstat (limited to 'drivers/video')
29 files changed, 560 insertions, 168 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 08c9b020788..15000e21840 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -29,6 +29,13 @@ config VIDEO_FONT_4X6 Provides character bitmap data in header file. When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. +config VIDEO_FONT_6X8 + bool "6 x 8 font size" + help + Font for video console driver, 6 x 8 pixels. + Provides character bitmap data in header file. + When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. + config VIDEO_FONT_8X16 bool "8 x 16 font size" default y @@ -247,10 +254,10 @@ config SYS_WHITE_ON_BLACK bool "Display console as white on a black background" default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || ARCH_TEGRA || X86 || ARCH_SUNXI help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background. This can be - better in low-light situations or to reduce eye strain in some - cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background. This can be + better in low-light situations or to reduce eye strain in some + cases. config NO_FB_CLEAR bool "Skip framebuffer clear" @@ -508,10 +515,10 @@ config FRAMEBUFFER_VESA_MODE config VIDEO_LCD_ANX9804 bool "ANX9804 bridge chip" - ---help--- - Support for the ANX9804 bridge chip, which can take pixel data coming - from a parallel LCD interface and translate it on the fy into a DP - interface for driving eDP TFT displays. It uses I2C for configuration. + help + Support for the ANX9804 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fy into a DP + interface for driving eDP TFT displays. It uses I2C for configuration. config ATMEL_LCD bool "Atmel LCD panel support" @@ -534,7 +541,7 @@ config VIDEO_BCM2835 that U-Boot can access it with full colour depth. config VIDEO_LCD_ENDEAVORU - tristate "Endeavoru 720x1280 DSI video mode panel" + bool "Endeavoru 720x1280 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -549,11 +556,19 @@ config VIDEO_LCD_HIMAX_HX8394 depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Himax HX8394 - dsi 4dl panel. + Say Y here if you want to enable support for Himax HX8394 + dsi 4dl panel. + +config VIDEO_LCD_ILITEK_ILI9806E + bool "Ilitek ILI9806E-based panels" + depends on PANEL && BACKLIGHT + help + Say Y here if you want to enable support for panels base on + the Ilitek ILI9806E controller. Currently only the DBI panel + is implemented. config VIDEO_LCD_MOT - tristate "Atrix 4G and Droid X2 540x960 DSI video mode panel" + bool "Atrix 4G and Droid X2 540x960 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -566,15 +581,15 @@ config VIDEO_LCD_NOVATEK_NT35510 bool "Novatek NT35510 DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Novatek nt35510 - dsi panel. + Say Y here if you want to enable support for Novatek nt35510 + dsi panel. config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Orise Technology - otm8009a 480x800 dsi 2dl panel. + Say Y here if you want to enable support for Orise Technology + otm8009a 480x800 dsi 2dl panel. config VIDEO_LCD_LG_LD070WX3 bool "LD070WX3 DSI LCD panel support" @@ -594,13 +609,14 @@ config VIDEO_LCD_LG_LH400WV3 config VIDEO_LCD_RAYDIUM_RM68200 bool "RM68200 DSI LCD panel support" + depends on BACKLIGHT select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Raydium RM68200 - 720x1280 DSI video mode panel. + Say Y here if you want to enable support for Raydium RM68200 + 720x1280 DSI video mode panel. config VIDEO_LCD_RENESAS_R61307 - tristate "Renesas R61307 DSI video mode panel" + bool "Renesas R61307 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -609,7 +625,7 @@ config VIDEO_LCD_RENESAS_R61307 resolution and uses 24 bit RGB per pixel. config VIDEO_LCD_RENESAS_R69328 - tristate "Renesas R69328 720x1280 DSI video mode panel" + bool "Renesas R69328 720x1280 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -618,7 +634,7 @@ config VIDEO_LCD_RENESAS_R69328 resolution and uses 24 bit RGB per pixel. config VIDEO_LCD_SAMSUNG_LTL106HL02 - tristate "Samsung LTL106HL02 1920x1080 DSI video mode panel" + bool "Samsung LTL106HL02 1920x1080 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -627,7 +643,7 @@ config VIDEO_LCD_SAMSUNG_LTL106HL02 resolution (1920x1080). config VIDEO_LCD_SHARP_LQ079L1SX01 - tristate "Sharp LQ079L1SX01 1536x2048 DSI video mode panel" + bool "Sharp LQ079L1SX01 1536x2048 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -636,7 +652,7 @@ config VIDEO_LCD_SHARP_LQ079L1SX01 resolution (1536x2048). config VIDEO_LCD_SHARP_LQ101R1SX01 - tristate "Sharp LQ101R1SX01 2560x1600 DSI video mode panel" + bool "Sharp LQ101R1SX01 2560x1600 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -646,41 +662,41 @@ config VIDEO_LCD_SHARP_LQ101R1SX01 config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" - ---help--- - Support for the SSD2828 bridge chip, which can take pixel data coming - from a parallel LCD interface and translate it on the fly into MIPI DSI - interface for driving a MIPI compatible LCD panel. It uses SPI for - configuration. + help + Support for the SSD2828 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fly into MIPI DSI + interface for driving a MIPI compatible LCD panel. It uses SPI for + configuration. config VIDEO_LCD_SSD2828_TX_CLK int "SSD2828 TX_CLK frequency (in MHz)" depends on VIDEO_LCD_SSD2828 default 0 - ---help--- - The frequency of the crystal, which is clocking SSD2828. It may be - anything in the 8MHz-30MHz range and the exact value should be - retrieved from the board schematics. Or in the case of Allwinner - hardware, it can be usually found as 'lcd_xtal_freq' variable in - FEX files. It can be also set to 0 for selecting PCLK from the - parallel LCD interface instead of TX_CLK as the PLL clock source. + help + The frequency of the crystal, which is clocking SSD2828. It may be + anything in the 8MHz-30MHz range and the exact value should be + retrieved from the board schematics. Or in the case of Allwinner + hardware, it can be usually found as 'lcd_xtal_freq' variable in + FEX files. It can be also set to 0 for selecting PCLK from the + parallel LCD interface instead of TX_CLK as the PLL clock source. config VIDEO_LCD_SSD2828_RESET string "RESET pin of SSD2828" depends on VIDEO_LCD_SSD2828 default "" - ---help--- - The reset pin of SSD2828 chip. This takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + The reset pin of SSD2828 chip. This takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_TDO_TL070WSH30 bool "TDO TL070WSH30 DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for TDO TL070WSH30 - 1024x600 DSI video mode panel. + Say Y here if you want to enable support for TDO TL070WSH30 + 1024x600 DSI video mode panel. config VIDEO_LCD_HITACHI_TX10D07VM0BAA - tristate "Hitachi TX10D07VM0BAA 480x800 MIPI DSI video mode panel" + bool "Hitachi TX10D07VM0BAA 480x800 MIPI DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -689,13 +705,13 @@ config VIDEO_LCD_HITACHI_TX10D07VM0BAA config VIDEO_LCD_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LVDS LCD panel support" - ---help--- - Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a - lcd controller which needs to be initialized over SPI, once that is - done they work like a regular LVDS panel. + help + Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a + lcd controller which needs to be initialized over SPI, once that is + done they work like a regular LVDS panel. config VIDEO_LCD_SONY_L4F00430T01 - tristate "Sony L4F00430T01 480x800 LCD panel support" + bool "Sony L4F00430T01 480x800 LCD panel support" depends on PANEL help Say Y here if you want to enable support for Sony L4F00430T01 @@ -704,7 +720,7 @@ config VIDEO_LCD_SONY_L4F00430T01 data comes from RGB. config VIDEO_LCD_SAMSUNG_S6E63M0 - tristate "Samsung S6E63M0 controller based panel support" + bool "Samsung S6E63M0 controller based panel support" depends on PANEL && BACKLIGHT help Say Y here if you want to enable support for Samsung S6E63M0 @@ -715,44 +731,44 @@ config VIDEO_LCD_SPI_CS string "SPI CS pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_SCLK string "SPI SCLK pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MOSI string "SPI MOSI pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MISO string "SPI MISO pin for LCD related config job (optional)" depends on VIDEO_LCD_SSD2828 default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. If wired up, this pin may provide additional - useful functionality. Such as bi-directional communication with the - hardware and LCD panel id retrieval (if the panel can report it). The - option takes a string in the format understood by 'sunxi_name_to_gpio' - function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. If wired up, this pin may provide additional + useful functionality. Such as bi-directional communication with the + hardware and LCD panel id retrieval (if the panel can report it). The + option takes a string in the format understood by 'sunxi_name_to_gpio' + function, e.g. PH1 for pin 1 of port H. source "drivers/video/meson/Kconfig" @@ -760,9 +776,9 @@ config VIDEO_MVEBU bool "Armada XP LCD controller" depends on ARCH_MVEBU imply VIDEO_DAMAGE - ---help--- - Support for the LCD controller integrated in the Marvell - Armada XP SoC. + help + Support for the LCD controller integrated in the Marvell + Armada XP SoC. config VIDEO_OMAP3 bool "Enable OMAP3+ DSS Support" @@ -773,23 +789,23 @@ config VIDEO_OMAP3 config I2C_EDID bool "Enable EDID library" help - This enables library for accessing EDID data from an LCD panel. + This enables library for accessing EDID data from an LCD panel. config I2C_EDID_STANDARD bool "Enable standard timings EDID library expansion" depends on I2C_EDID help - This enables standard timings expansion for EDID data from an LCD panel. + This enables standard timings expansion for EDID data from an LCD panel. config DISPLAY bool "Enable Display support" depends on DM select I2C_EDID help - This supports drivers that provide a display, such as eDP (Embedded - DisplayPort) and HDMI (High Definition Multimedia Interface). - The devices provide a simple interface to start up the display, - read display information and enable it. + This supports drivers that provide a display, such as eDP (Embedded + DisplayPort) and HDMI (High Definition Multimedia Interface). + The devices provide a simple interface to start up the display, + read display information and enable it. config NXP_TDA19988 bool "Enable NXP TDA19988 support" @@ -803,7 +819,7 @@ config ATMEL_HLCD depends on ARCH_AT91 imply VIDEO_DAMAGE help - HLCDC supports video output to an attached LCD panel. + HLCDC supports video output to an attached LCD panel. config BACKLIGHT_AAT2870 bool "Backlight Driver for AAT2870" @@ -857,7 +873,7 @@ source "drivers/video/exynos/Kconfig" config LOGICORE_DP_TX bool "Enable Logicore DP TX driver" - depends on DISPLAY + depends on DISPLAY && AXI help Enable the driver for the transmitter part of the Xilinx LogiCORE DisplayPort, a IP core for Xilinx FPGAs that implements a DisplayPort @@ -922,9 +938,9 @@ config VIDEO_NX bool "Enable video support on Nexell SoC" depends on ARCH_S5P6818 || ARCH_S5P4418 help - Nexell SoC supports many video output options including eDP and - HDMI. This option enables this support which can be used on devices - which have an eDP display connected. + Nexell SoC supports many video output options including eDP and + HDMI. This option enables this support which can be used on devices + which have an eDP display connected. config VIDEO_SEPS525 bool "Enable video support for Seps525" @@ -1010,9 +1026,9 @@ config OSD bool "Enable OSD support" depends on DM help - This supports drivers that provide a OSD (on-screen display), which - is a (usually text-oriented) graphics buffer to show information on - a display. + This supports drivers that provide a OSD (on-screen display), which + is a (usually text-oriented) graphics buffer to show information on + a display. config SANDBOX_OSD bool "Enable sandbox OSD" @@ -1205,10 +1221,10 @@ config SPL_SPLASH_SCREEN config SPL_SYS_WHITE_ON_BLACK bool "Display console as white on a black background at SPL" help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background at spl stage. - This can be better in low-light situations or to reduce eye strain in - some cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. config SPL_VIDEO_PCI_DEFAULT_FB_SIZE hex "Default framebuffer size to use if no drivers request it at SPL" @@ -1271,10 +1287,10 @@ config SPL_SIMPLE_PANEL config SPL_SYS_WHITE_ON_BLACK bool "Display console as white on a black background at SPL" help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background at spl stage. - This can be better in low-light situations or to reduce eye strain in - some cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. config SPL_VIDEO_REMOVE bool "Remove video driver after SPL stage" @@ -1400,13 +1416,13 @@ config SPL_VIDEO_BPP32 will be empty. config SPL_HIDE_LOGO_VERSION - bool "Hide the version information on the splash screen at SPL" - help - Normally the U-Boot version string is shown on the display when the - splash screen is enabled. This information is not otherwise visible - since video starts up after U-Boot has displayed the initial banner. + bool "Hide the version information on the splash screen at SPL" + help + Normally the U-Boot version string is shown on the display when the + splash screen is enabled. This information is not otherwise visible + since video starts up after U-Boot has displayed the initial banner. - Enable this option to hide this information. + Enable this option to hide this information. endif endmenu diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 984768ea156..082b8967982 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_$(PHASE_)PANEL) += panel-uclass.o obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o obj-$(CONFIG_$(PHASE_)SIMPLE_PANEL) += simple_panel.o -obj-$(CONFIG_VIDEO_LOGO) += u_boot_logo.o +obj-$(CONFIG_VIDEO_LOGO) += u_boot_logo.bmp.o obj-$(CONFIG_$(PHASE_)BMP) += bmp.o endif @@ -61,6 +61,7 @@ obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX10D07VM0BAA) += hitachi-tx10d07vm0baa.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o +obj-$(CONFIG_VIDEO_LCD_ILITEK_ILI9806E) += ilitek-ili9806e.o obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o obj-$(CONFIG_VIDEO_LCD_LG_LH400WV3) += lg-lh400wv3-sd04.o obj-$(CONFIG_VIDEO_LCD_MOT) += mot-panel.o diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 0c81e606622..0e0cc1979eb 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -66,6 +66,7 @@ static int bcm2835_video_probe(struct udevice *dev) static const struct udevice_id bcm2835_video_ids[] = { { .compatible = "brcm,bcm2835-hdmi" }, { .compatible = "brcm,bcm2711-hdmi0" }, + { .compatible = "brcm,bcm2712-hdmi0" }, { .compatible = "brcm,bcm2708-fb" }, #if !IS_ENABLED(CONFIG_VIDEO_DT_SIMPLEFB) { .compatible = "simple-framebuffer" }, diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig index 5322a002928..81261c61005 100644 --- a/drivers/video/bridge/Kconfig +++ b/drivers/video/bridge/Kconfig @@ -41,8 +41,8 @@ config VIDEO_BRIDGE_ANALOGIX_ANX6345 depends on VIDEO_BRIDGE select DM_I2C help - The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD - panel to be connected to an parallel LCD interface. + The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD + panel to be connected to an parallel LCD interface. config VIDEO_BRIDGE_SOLOMON_SSD2825 bool "Solomon SSD2825 bridge driver" diff --git a/drivers/video/bridge/anx6345.c b/drivers/video/bridge/anx6345.c index 8cee4c958bd..a5d2781aa48 100644 --- a/drivers/video/bridge/anx6345.c +++ b/drivers/video/bridge/anx6345.c @@ -403,7 +403,7 @@ static int anx6345_probe(struct udevice *dev) return anx6345_enable(dev); } -struct video_bridge_ops anx6345_ops = { +static const struct video_bridge_ops anx6345_ops = { .attach = anx6345_attach, .set_backlight = anx6345_set_backlight, .read_edid = anx6345_read_edid, diff --git a/drivers/video/bridge/ps862x.c b/drivers/video/bridge/ps862x.c index efd03752281..a08227f8355 100644 --- a/drivers/video/bridge/ps862x.c +++ b/drivers/video/bridge/ps862x.c @@ -116,7 +116,7 @@ static int ps8622_probe(struct udevice *dev) return 0; } -struct video_bridge_ops ps8622_ops = { +static const struct video_bridge_ops ps8622_ops = { .attach = ps8622_attach, .set_backlight = ps8622_set_backlight, }; diff --git a/drivers/video/bridge/ptn3460.c b/drivers/video/bridge/ptn3460.c index 5851e1ef15e..ce576c0b282 100644 --- a/drivers/video/bridge/ptn3460.c +++ b/drivers/video/bridge/ptn3460.c @@ -15,7 +15,7 @@ static int ptn3460_attach(struct udevice *dev) return video_bridge_set_active(dev, true); } -struct video_bridge_ops ptn3460_ops = { +static const struct video_bridge_ops ptn3460_ops = { .attach = ptn3460_attach, }; diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 07db613ac53..6dc0a6eaf9d 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -133,7 +133,7 @@ static int console_set_cursor_visible(struct udevice *dev, bool visible, return 0; } -struct vidconsole_ops console_ops = { +static const struct vidconsole_ops console_ops = { .putc_xy = console_putc_xy, .move_rows = console_move_rows, .set_row = console_set_row, diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index 886b25dcfaf..e478e0ef3bc 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -284,7 +284,7 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, int cp) return VID_TO_POS(fontdata->width); } -struct vidconsole_ops console_ops_1 = { +static const struct vidconsole_ops console_ops_1 = { .putc_xy = console_putc_xy_1, .move_rows = console_move_rows_1, .set_row = console_set_row_1, @@ -293,7 +293,7 @@ struct vidconsole_ops console_ops_1 = { .select_font = console_simple_select_font, }; -struct vidconsole_ops console_ops_2 = { +static const struct vidconsole_ops console_ops_2 = { .putc_xy = console_putc_xy_2, .move_rows = console_move_rows_2, .set_row = console_set_row_2, @@ -302,7 +302,7 @@ struct vidconsole_ops console_ops_2 = { .select_font = console_simple_select_font, }; -struct vidconsole_ops console_ops_3 = { +static const struct vidconsole_ops console_ops_3 = { .putc_xy = console_putc_xy_3, .move_rows = console_move_rows_3, .set_row = console_set_row_3, diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index eaf169e8386..b9b6f394fbc 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -1069,7 +1069,7 @@ static int console_truetype_probe(struct udevice *dev) return 0; } -struct vidconsole_ops console_truetype_ops = { +static const struct vidconsole_ops console_truetype_ops = { .putc_xy = console_truetype_putc_xy, .move_rows = console_truetype_move_rows, .set_row = console_truetype_set_row, diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c index c74fe678d12..ec5d4c81812 100644 --- a/drivers/video/dw_mipi_dsi.c +++ b/drivers/video/dw_mipi_dsi.c @@ -837,7 +837,7 @@ static int dw_mipi_dsi_enable(struct udevice *dev) return 0; } -struct dsi_host_ops dw_mipi_dsi_ops = { +static const struct dsi_host_ops dw_mipi_dsi_ops = { .init = dw_mipi_dsi_init, .enable = dw_mipi_dsi_enable, }; diff --git a/drivers/video/fonts/Makefile b/drivers/video/fonts/Makefile index 1111f92a2c6..4d32fa43994 100644 --- a/drivers/video/fonts/Makefile +++ b/drivers/video/fonts/Makefile @@ -3,8 +3,8 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, [email protected]. -obj-$(CONFIG_CONSOLE_TRUETYPE_NIMBUS) += nimbus_sans_l_regular.o -obj-$(CONFIG_CONSOLE_TRUETYPE_ANKACODER) += ankacoder_c75_r.o -obj-$(CONFIG_CONSOLE_TRUETYPE_RUFSCRIPT) += rufscript010.o -obj-$(CONFIG_CONSOLE_TRUETYPE_CANTORAONE) += cantoraone_regular.o -obj-$(CONFIG_CONSOLE_TRUETYPE_DEJAVU) += dejavu_mono.o +obj-$(CONFIG_CONSOLE_TRUETYPE_NIMBUS) += nimbus_sans_l_regular.ttf.o +obj-$(CONFIG_CONSOLE_TRUETYPE_ANKACODER) += ankacoder_c75_r.ttf.o +obj-$(CONFIG_CONSOLE_TRUETYPE_RUFSCRIPT) += rufscript010.ttf.o +obj-$(CONFIG_CONSOLE_TRUETYPE_CANTORAONE) += cantoraone_regular.ttf.o +obj-$(CONFIG_CONSOLE_TRUETYPE_DEJAVU) += dejavu_mono.ttf.o diff --git a/drivers/video/ilitek-ili9806e.c b/drivers/video/ilitek-ili9806e.c new file mode 100644 index 00000000000..9ba580639c9 --- /dev/null +++ b/drivers/video/ilitek-ili9806e.c @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <[email protected]> + */ + +#include <backlight.h> +#include <dm.h> +#include <mipi_display.h> +#include <panel.h> +#include <spi.h> +#include <asm/gpio.h> +#include <dm/device_compat.h> +#include <linux/delay.h> +#include <power/regulator.h> + +struct ilitek_ili9806e_priv { + struct udevice *vdd; + struct udevice *backlight; + struct gpio_desc reset_gpio; + const struct ilitek_ili9806e_desc *desc; +}; + +struct ilitek_ili9806e_desc { + const struct display_timing timing; + void (*init_sequence)(struct udevice *dev); +}; + +static int ilitek_ili9806e_dcs_write(struct udevice *dev, u8 cmd, const u8 *seq, int len) +{ + u16 data[16]; + int i, ret; + + if ((len + 1) > ARRAY_SIZE(data)) { + dev_err(dev, "Command length (%d) exceeds buffer size (%lu)\n", + len + 1, ARRAY_SIZE(data)); + return -EMSGSIZE; + } + + data[0] = cmd; + if (len) { + for (i = 0; i < len; i++) + data[i + 1] = seq[i] | 0x0100; + } + + ret = dm_spi_xfer(dev, (len + 1) * 8 * sizeof(u16), data, NULL, + SPI_XFER_ONCE); + return 0; +} + +#define ilitek_ili9806e_dcs_write_seq(dev, cmd, seq...) \ +({ \ + static const u8 b[] = { seq }; \ + ilitek_ili9806e_dcs_write(dev, cmd, b, ARRAY_SIZE(b)); \ +}) + +static int ilitek_ili9806e_enable_backlight(struct udevice *dev) +{ + struct ilitek_ili9806e_priv *priv = dev_get_priv(dev); + const struct ilitek_ili9806e_desc *desc = priv->desc; + + desc->init_sequence(dev); + + return panel_set_backlight(dev, BACKLIGHT_DEFAULT); +} + +static int ilitek_ili9806e_set_backlight(struct udevice *dev, int percent) +{ + struct ilitek_ili9806e_priv *priv = dev_get_priv(dev); + int ret; + + ret = backlight_enable(priv->backlight); + if (ret) { + dev_err(dev, "Cannot enable backlight\n"); + return ret; + } + + ret = backlight_set_brightness(priv->backlight, percent); + if (ret) + dev_err(dev, "Cannot set backlight brightness\n"); + + return ret; +} + +static int ilitek_ili9806e_get_display_timing(struct udevice *dev, + struct display_timing *timing) +{ + struct ilitek_ili9806e_priv *priv = dev_get_priv(dev); + + memcpy(timing, &priv->desc->timing, sizeof(*timing)); + + return 0; +} + +static int ilitek_ili9806e_of_to_plat(struct udevice *dev) +{ + struct ilitek_ili9806e_priv *priv = dev_get_priv(dev); + int ret; + + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + ret = device_get_supply_regulator(dev, "vdd-supply", &priv->vdd); + if (ret) { + dev_err(dev, "Cannot get vdd supply\n"); + return ret; + } + } + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + dev_err(dev, "Cannot get backlight\n"); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + dev_err(dev, "Cannot get reset GPIO\n"); + return ret; + } + + return 0; +} + +static int ilitek_ili9806e_hw_init(struct udevice *dev) +{ + struct ilitek_ili9806e_priv *priv = dev_get_priv(dev); + int ret; + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + dev_err(dev, "Cannot enter reset\n"); + return ret; + } + + ret = regulator_set_enable_if_allowed(priv->vdd, 1); + if (ret) { + dev_err(dev, "Cannot enable vdd-supply\n"); + return ret; + } + + mdelay(20); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + dev_err(dev, "Cannot exit reset\n"); + return ret; + } + + mdelay(20); + + return 0; +} + +static int ilitek_ili9806e_probe(struct udevice *dev) +{ + struct ilitek_ili9806e_priv *priv = dev_get_priv(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); + int ret; + + ret = spi_set_wordlen(slave, 9); + if (ret) { + dev_err(dev, "Cannot set SPI.bits_per_word\n"); + return ret; + } + + ret = spi_claim_bus(slave); + if (ret) { + dev_err(dev, "Cannot get SPI bus\n"); + return ret; + } + + priv->desc = (struct ilitek_ili9806e_desc *)dev_get_driver_data(dev); + + return ilitek_ili9806e_hw_init(dev); +} + +static const struct panel_ops ilitek_ili9806e_ops = { + .enable_backlight = ilitek_ili9806e_enable_backlight, + .set_backlight = ilitek_ili9806e_set_backlight, + .get_display_timing = ilitek_ili9806e_get_display_timing, +}; + +static void rk050hr345_ct106a_init(struct udevice *dev) +{ + /* Switch to page 1 */ + ilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01); + /* Interface Settings */ + ilitek_ili9806e_dcs_write_seq(dev, 0x08, 0x10); + ilitek_ili9806e_dcs_write_seq(dev, 0x21, 0x01); + /* Panel Settings */ + ilitek_ili9806e_dcs_write_seq(dev, 0x30, 0x01); + ilitek_ili9806e_dcs_write_seq(dev, 0x31, 0x00); + /* Power Control */ + ilitek_ili9806e_dcs_write_seq(dev, 0x40, 0x15); + ilitek_ili9806e_dcs_write_seq(dev, 0x41, 0x44); + ilitek_ili9806e_dcs_write_seq(dev, 0x42, 0x03); + ilitek_ili9806e_dcs_write_seq(dev, 0x43, 0x09); + ilitek_ili9806e_dcs_write_seq(dev, 0x44, 0x09); + ilitek_ili9806e_dcs_write_seq(dev, 0x50, 0x78); + ilitek_ili9806e_dcs_write_seq(dev, 0x51, 0x78); + ilitek_ili9806e_dcs_write_seq(dev, 0x52, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x53, 0x3a); + ilitek_ili9806e_dcs_write_seq(dev, 0x57, 0x50); + /* Timing Control */ + ilitek_ili9806e_dcs_write_seq(dev, 0x60, 0x07); + ilitek_ili9806e_dcs_write_seq(dev, 0x61, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x62, 0x08); + ilitek_ili9806e_dcs_write_seq(dev, 0x63, 0x00); + /* Gamma Settings */ + ilitek_ili9806e_dcs_write_seq(dev, 0xa0, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0xa1, 0x03); + ilitek_ili9806e_dcs_write_seq(dev, 0xa2, 0x0b); + ilitek_ili9806e_dcs_write_seq(dev, 0xa3, 0x0f); + ilitek_ili9806e_dcs_write_seq(dev, 0xa4, 0x0b); + ilitek_ili9806e_dcs_write_seq(dev, 0xa5, 0x1b); + ilitek_ili9806e_dcs_write_seq(dev, 0xa6, 0x0a); + ilitek_ili9806e_dcs_write_seq(dev, 0xa7, 0x0a); + ilitek_ili9806e_dcs_write_seq(dev, 0xa8, 0x02); + ilitek_ili9806e_dcs_write_seq(dev, 0xa9, 0x07); + ilitek_ili9806e_dcs_write_seq(dev, 0xaa, 0x05); + ilitek_ili9806e_dcs_write_seq(dev, 0xab, 0x03); + ilitek_ili9806e_dcs_write_seq(dev, 0xac, 0x0e); + ilitek_ili9806e_dcs_write_seq(dev, 0xad, 0x32); + ilitek_ili9806e_dcs_write_seq(dev, 0xae, 0x2d); + ilitek_ili9806e_dcs_write_seq(dev, 0xaf, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0xc0, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0xc1, 0x03); + ilitek_ili9806e_dcs_write_seq(dev, 0xc2, 0x0e); + ilitek_ili9806e_dcs_write_seq(dev, 0xc3, 0x10); + ilitek_ili9806e_dcs_write_seq(dev, 0xc4, 0x09); + ilitek_ili9806e_dcs_write_seq(dev, 0xc5, 0x17); + ilitek_ili9806e_dcs_write_seq(dev, 0xc6, 0x09); + ilitek_ili9806e_dcs_write_seq(dev, 0xc7, 0x07); + ilitek_ili9806e_dcs_write_seq(dev, 0xc8, 0x04); + ilitek_ili9806e_dcs_write_seq(dev, 0xc9, 0x09); + ilitek_ili9806e_dcs_write_seq(dev, 0xca, 0x06); + ilitek_ili9806e_dcs_write_seq(dev, 0xcb, 0x06); + ilitek_ili9806e_dcs_write_seq(dev, 0xcc, 0x0c); + ilitek_ili9806e_dcs_write_seq(dev, 0xcd, 0x25); + ilitek_ili9806e_dcs_write_seq(dev, 0xce, 0x20); + ilitek_ili9806e_dcs_write_seq(dev, 0xcf, 0x00); + + /* Switch to page 6 */ + ilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06); + /* GIP settings */ + ilitek_ili9806e_dcs_write_seq(dev, 0x00, 0x21); + ilitek_ili9806e_dcs_write_seq(dev, 0x01, 0x09); + ilitek_ili9806e_dcs_write_seq(dev, 0x02, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x03, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x04, 0x01); + ilitek_ili9806e_dcs_write_seq(dev, 0x05, 0x01); + ilitek_ili9806e_dcs_write_seq(dev, 0x06, 0x80); + ilitek_ili9806e_dcs_write_seq(dev, 0x07, 0x05); + ilitek_ili9806e_dcs_write_seq(dev, 0x08, 0x02); + ilitek_ili9806e_dcs_write_seq(dev, 0x09, 0x80); + ilitek_ili9806e_dcs_write_seq(dev, 0x0a, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x0b, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x0c, 0x0a); + ilitek_ili9806e_dcs_write_seq(dev, 0x0d, 0x0a); + ilitek_ili9806e_dcs_write_seq(dev, 0x0e, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x0f, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x10, 0xe0); + ilitek_ili9806e_dcs_write_seq(dev, 0x11, 0xe4); + ilitek_ili9806e_dcs_write_seq(dev, 0x12, 0x04); + ilitek_ili9806e_dcs_write_seq(dev, 0x13, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x14, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x15, 0xc0); + ilitek_ili9806e_dcs_write_seq(dev, 0x16, 0x08); + ilitek_ili9806e_dcs_write_seq(dev, 0x17, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x18, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x19, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x1a, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x1b, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x1c, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x1d, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x20, 0x01); + ilitek_ili9806e_dcs_write_seq(dev, 0x21, 0x23); + ilitek_ili9806e_dcs_write_seq(dev, 0x22, 0x45); + ilitek_ili9806e_dcs_write_seq(dev, 0x23, 0x67); + ilitek_ili9806e_dcs_write_seq(dev, 0x24, 0x01); + ilitek_ili9806e_dcs_write_seq(dev, 0x25, 0x23); + ilitek_ili9806e_dcs_write_seq(dev, 0x26, 0x45); + ilitek_ili9806e_dcs_write_seq(dev, 0x27, 0x67); + ilitek_ili9806e_dcs_write_seq(dev, 0x30, 0x01); + ilitek_ili9806e_dcs_write_seq(dev, 0x31, 0x11); + ilitek_ili9806e_dcs_write_seq(dev, 0x32, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, 0x33, 0xee); + ilitek_ili9806e_dcs_write_seq(dev, 0x34, 0xff); + ilitek_ili9806e_dcs_write_seq(dev, 0x35, 0xbb); + ilitek_ili9806e_dcs_write_seq(dev, 0x36, 0xca); + ilitek_ili9806e_dcs_write_seq(dev, 0x37, 0xdd); + ilitek_ili9806e_dcs_write_seq(dev, 0x38, 0xac); + ilitek_ili9806e_dcs_write_seq(dev, 0x39, 0x76); + ilitek_ili9806e_dcs_write_seq(dev, 0x3a, 0x67); + ilitek_ili9806e_dcs_write_seq(dev, 0x3b, 0x22); + ilitek_ili9806e_dcs_write_seq(dev, 0x3c, 0x22); + ilitek_ili9806e_dcs_write_seq(dev, 0x3d, 0x22); + ilitek_ili9806e_dcs_write_seq(dev, 0x3e, 0x22); + ilitek_ili9806e_dcs_write_seq(dev, 0x3f, 0x22); + ilitek_ili9806e_dcs_write_seq(dev, 0x40, 0x22); + ilitek_ili9806e_dcs_write_seq(dev, 0x52, 0x10); + ilitek_ili9806e_dcs_write_seq(dev, 0x53, 0x10); + + /* Switch to page 7 */ + ilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07); + ilitek_ili9806e_dcs_write_seq(dev, 0x17, 0x22); + ilitek_ili9806e_dcs_write_seq(dev, 0x02, 0x77); + ilitek_ili9806e_dcs_write_seq(dev, 0xe1, 0x79); + ilitek_ili9806e_dcs_write_seq(dev, 0xb3, 0x10); + + /* Switch to page 0 */ + ilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00); + ilitek_ili9806e_dcs_write_seq(dev, MIPI_DCS_EXIT_SLEEP_MODE); + + mdelay(120); + + ilitek_ili9806e_dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_ON); + + mdelay(120); +} + +static const struct ilitek_ili9806e_desc rk050hr345_ct106a_desc = { + .timing = { + .pixelclock.typ = 27000000, + .hactive.typ = 480, + .hfront_porch.typ = 10, + .hback_porch.typ = 10, + .hsync_len.typ = 10, + .vactive.typ = 854, + .vfront_porch.typ = 10, + .vback_porch.typ = 10, + .vsync_len.typ = 10, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, + }, + .init_sequence = rk050hr345_ct106a_init, +}; + +static const struct udevice_id ilitek_ili9806e_ids[] = { + { + .compatible = "rocktech,rk050hr345-ct106a", + .data = (ulong)&rk050hr345_ct106a_desc, + }, + { } +}; + +U_BOOT_DRIVER(ilitek_ili9806e) = { + .name = "ilitek_ili9806e", + .id = UCLASS_PANEL, + .of_match = ilitek_ili9806e_ids, + .ops = &ilitek_ili9806e_ops, + .of_to_plat = ilitek_ili9806e_of_to_plat, + .probe = ilitek_ili9806e_probe, + .priv_auto = sizeof(struct ilitek_ili9806e_priv), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig index c25f209629e..0c386595559 100644 --- a/drivers/video/imx/Kconfig +++ b/drivers/video/imx/Kconfig @@ -20,7 +20,7 @@ config IPU_CLK_LEGACY depends on VIDEO_IPUV3 && !CLK default y help - Use legacy clock management instead of Common Clock Framework. + Use legacy clock management instead of Common Clock Framework. config IMX_LDB bool "Freescale i.MX8MP LDB bridge" diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h index ae40e20bc28..aecb6adffce 100644 --- a/drivers/video/imx/ipu.h +++ b/drivers/video/imx/ipu.h @@ -136,7 +136,6 @@ struct ipu_ctx { struct clk *ipu_clk; struct clk *ldb_clk; - unsigned char ipu_clk_enabled; struct clk *di_clk[2]; struct clk *pixel_clk[2]; diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index 8630374a055..d3b52605731 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -299,9 +299,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk); clk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk); +#endif clk_enable(ctx->ipu_clk); -#endif for (int i = 0; i <= 1; i++) { ret = ipu_di_clk_init(ctx, i); @@ -384,10 +384,8 @@ int32_t ipu_init_channel(struct ipu_ctx *ctx, ipu_channel_t channel, debug("init channel = %d\n", IPU_CHAN_ID(channel)); - if (ctx->ipu_clk_enabled == 0) { - ctx->ipu_clk_enabled = 1; + if (!ipu_clk_enabled(ctx)) clk_enable(ipu_clk); - } if (*channel_init_mask & (1L << IPU_CHAN_ID(channel))) { printf("Warning: channel already initialized %d\n", @@ -543,7 +541,6 @@ void ipu_uninit_channel(struct ipu_ctx *ctx, ipu_channel_t channel) if (ipu_conf == 0) { clk_disable(ctx->ipu_clk); - ctx->ipu_clk_enabled = 0; } } @@ -1045,5 +1042,9 @@ ipu_color_space_t format_to_colorspace(u32 fmt) bool ipu_clk_enabled(struct ipu_ctx *ctx) { - return ctx->ipu_clk_enabled; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return clk_get_usecount(ctx->ipu_clk); +#else + return ctx->ipu_clk->enable_count; +#endif } diff --git a/drivers/video/imx/ldb.c b/drivers/video/imx/ldb.c index e918341c0a3..32a327647f8 100644 --- a/drivers/video/imx/ldb.c +++ b/drivers/video/imx/ldb.c @@ -230,7 +230,7 @@ dis_clk: return ret; } -struct video_bridge_ops imx_ldb_ops = { +static const struct video_bridge_ops imx_ldb_ops = { .attach = imx_ldb_attach, .set_backlight = imx_ldb_set_backlight, }; diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c index ca627728743..a686faf9f58 100644 --- a/drivers/video/meson/meson_vpu.c +++ b/drivers/video/meson/meson_vpu.c @@ -81,8 +81,8 @@ cvbs: meson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize * ((1 << VPU_MAX_LOG2_BPP) / 8) + MESON_VPU_OVERSCAN, EFI_PAGE_SIZE); - meson_fb.base = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - meson_fb.fb_size; + meson_fb.base = gd->dram[0].start + + gd->dram[0].size - meson_fb.fb_size; /* Override the framebuffer address */ uc_plat->base = meson_fb.base; @@ -175,8 +175,8 @@ static void meson_vpu_setup_simplefb(void *fdt) * at the end of the RAM and we strip this portion from the kernel * allowed region */ - mem_start = gd->bd->bi_dram[0].start; - mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size; + mem_start = gd->dram[0].start; + mem_size = gd->dram[0].size - meson_fb.fb_size; ret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1); if (ret) { eprintf("Cannot setup simplefb: Error reserving memory\n"); diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 96af6d28ef0..41d249cb90c 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -21,7 +21,7 @@ menuconfig VIDEO_ROCKCHIP Rockchip RK3288 and RK3399. config VIDEO_ROCKCHIP_MAX_XRES - int "Maximum horizontal resolution (for memory allocation purposes)" + int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP default 3840 if DISPLAY_ROCKCHIP_HDMI default 1920 @@ -31,7 +31,7 @@ config VIDEO_ROCKCHIP_MAX_XRES framebuffer during device-model binding/probing. config VIDEO_ROCKCHIP_MAX_YRES - int "Maximum vertical resolution (for memory allocation purposes)" + int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP default 2160 if DISPLAY_ROCKCHIP_HDMI default 1080 diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 8d0772d4e51..631ae00b1e1 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -9,6 +9,8 @@ #include <log.h> #include <video.h> #include <asm/global_data.h> +#include <asm/system.h> +#include <linux/sizes.h> static int simple_video_probe(struct udevice *dev) { @@ -20,8 +22,14 @@ static int simple_video_probe(struct udevice *dev) fdt_addr_t base; fdt_size_t size; u32 width, height, stride, rot; + struct ofnode_phandle_args args; + + ret = dev_read_phandle_with_args(dev, "memory-region", NULL, 0, 0, &args); + if (ret) + base = dev_read_addr_size(dev, &size); + else + base = ofnode_get_addr_size(args.node, "reg", &size); - base = dev_read_addr_size(dev, &size); if (base == FDT_ADDR_T_NONE) { debug("%s: Failed to decode memory region\n", __func__); return -EINVAL; @@ -37,6 +45,13 @@ static int simple_video_probe(struct udevice *dev) plat->base = base; plat->size = size; +#ifdef CONFIG_ARM64 + /* The framebuffer buffer might not be mapped on some devices */ + if (plat->base % SZ_4K) + log_warning("Framebuffer base %lx is not 4k aligned!\n", plat->base); + mmu_map_region((phys_addr_t)plat->base, (phys_addr_t)ALIGN(plat->size, SZ_4K), false); +#endif + video_set_flush_dcache(dev, true); debug("%s: Query resolution...\n", __func__); diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c index 65a91f5cff7..29c57a4ff89 100644 --- a/drivers/video/stm32/stm32_dsi.c +++ b/drivers/video/stm32/stm32_dsi.c @@ -493,8 +493,11 @@ static int stm32_dsi_probe(struct udevice *dev) priv->hw_version != HWVER_131) { dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version); dev_dbg(dev, "remove and unbind all DSI child\n"); - device_chld_remove(dev, NULL, DM_REMOVE_NORMAL); - device_chld_unbind(dev, NULL); + ret = device_chld_remove(dev, NULL, DM_REMOVE_NORMAL); + if (!ret) + ret = device_chld_unbind(dev, NULL); + if (ret) + dev_err(dev, "Unbinding from %s failed %d\n", dev->name, ret); ret = -ENODEV; goto err_clk; } @@ -508,7 +511,7 @@ err_reg: return ret; } -struct video_bridge_ops stm32_dsi_ops = { +static const struct video_bridge_ops stm32_dsi_ops = { .attach = stm32_dsi_attach, .set_backlight = stm32_dsi_set_backlight, }; diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 154641b9a69..ab36ee1595b 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -368,7 +368,7 @@ int sunxi_simplefb_setup(void *blob) return 0; /* Keep older kernels working */ } - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = de2_plat->base - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 4a6a89ef9d2..fa492c661db 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -1336,7 +1336,7 @@ int sunxi_simplefb_setup(void *blob) * and e.g. Linux refuses to iomap RAM on ARM, see: * linux/arch/arm/mm/ioremap.c around line 301. */ - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = sunxi_display->fb_addr - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/drivers/video/tda19988.c b/drivers/video/tda19988.c index ebc8521c6ed..a4cc3a49232 100644 --- a/drivers/video/tda19988.c +++ b/drivers/video/tda19988.c @@ -522,7 +522,7 @@ static int tda19988_enable(struct udevice *dev, int panel_bpp, return 0; } -struct dm_display_ops tda19988_ops = { +static const struct dm_display_ops tda19988_ops = { .read_edid = tda19988_read_edid, .enable = tda19988_enable, }; diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig index 8bc29f2838b..125504024fc 100644 --- a/drivers/video/tegra/Kconfig +++ b/drivers/video/tegra/Kconfig @@ -9,13 +9,13 @@ config VIDEO_TEGRA depends on OF_CONTROL && ARCH_TEGRA select HOST1X_TEGRA help - Enable support for Display Controller found in Tegra SoC. The - Display Controller Complex integrates two independent display - controllers. Each display controller is capable of interfacing - to an external display device, which can be a parallel interface - or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD. - Direct interface is supported directly to most LCD displays with - TFT or TFT-like interface. + Enable support for Display Controller found in Tegra SoC. The + Display Controller Complex integrates two independent display + controllers. Each display controller is capable of interfacing + to an external display device, which can be a parallel interface + or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD. + Direct interface is supported directly to most LCD displays with + TFT or TFT-like interface. config VIDEO_DSI_TEGRA bool "Enable DSI controller support on Tegra devices" @@ -23,9 +23,9 @@ config VIDEO_DSI_TEGRA select VIDEO_TEGRA select VIDEO_MIPI_DSI help - Enable support for the Display Serial Interface (DSI) found in - Tegra SoC. It is a MIPI standard serial bitstream, intended to - provide a low pin count interface to a display panel. + Enable support for the Display Serial Interface (DSI) found in + Tegra SoC. It is a MIPI standard serial bitstream, intended to + provide a low pin count interface to a display panel. config VIDEO_HDMI_TEGRA bool "Enable HDMI support on Tegra devices" @@ -33,31 +33,31 @@ config VIDEO_HDMI_TEGRA select I2C_EDID select VIDEO_TEGRA help - Enable support for the High-Definition Multimedia Interface (HDMI) - found in Tegra SoC. + Enable support for the High-Definition Multimedia Interface (HDMI) + found in Tegra SoC. config TEGRA_BACKLIGHT_PWM bool "Enable Tegra DC PWM backlight support" depends on BACKLIGHT && VIDEO_TEGRA help - Enable support for the Display Controller dependent PWM backlight - found in the Tegra SoC and usually used with DSI panels. + Enable support for the Display Controller dependent PWM backlight + found in the Tegra SoC and usually used with DSI panels. config TEGRA_8BIT_CPU_BRIDGE bool "Enable 8 bit panel communication protocol for Tegra 20/30" depends on VIDEO_BRIDGE && DM_GPIO && VIDEO_TEGRA select VIDEO_MIPI_DSI help - Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control - protocol. This option allows use it as a MIPI DSI bridge to - set up and control compatible panel. + Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control + protocol. This option allows use it as a MIPI DSI bridge to + set up and control compatible panel. config VIDEO_TEGRA124 bool "Enable video support on Tegra124" depends on ARCH_TEGRA imply VIDEO_DAMAGE help - Tegra124 supports many video output options including eDP and - HDMI. At present only eDP is supported by U-Boot. This option - enables this support which can be used on devices which - have an eDP display connected. + Tegra124 supports many video output options including eDP and + HDMI. At present only eDP is supported by U-Boot. This option + enables this support which can be used on devices which + have an eDP display connected. diff --git a/drivers/video/tegra/dsi.c b/drivers/video/tegra/dsi.c index bc308869f4e..f53fabf6fd6 100644 --- a/drivers/video/tegra/dsi.c +++ b/drivers/video/tegra/dsi.c @@ -337,7 +337,7 @@ static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, return count; } -struct mipi_dsi_host_ops tegra_dsi_bridge_host_ops = { +static const struct mipi_dsi_host_ops tegra_dsi_bridge_host_ops = { .transfer = tegra_dsi_host_transfer, }; diff --git a/drivers/video/ti/Kconfig b/drivers/video/ti/Kconfig index 0483f760ea1..a3cbefef0de 100644 --- a/drivers/video/ti/Kconfig +++ b/drivers/video/ti/Kconfig @@ -6,4 +6,4 @@ config AM335X_LCD bool "Enable AM335x video support" depends on ARCH_OMAP2PLUS help - Supports video output to an attached LCD panel. + Supports video output to an attached LCD panel. diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig index 3291b3ceb8d..c9849110059 100644 --- a/drivers/video/tidss/Kconfig +++ b/drivers/video/tidss/Kconfig @@ -10,7 +10,7 @@ menuconfig VIDEO_TIDSS bool "Enable TIDSS video support" - depends on VIDEO + depends on VIDEO && PANEL imply VIDEO_DAMAGE help TIDSS supports video output options LVDS and @@ -19,7 +19,7 @@ menuconfig VIDEO_TIDSS config SPL_VIDEO_TIDSS bool "Enable TIDSS video support in SPL Stage" - depends on SPL_VIDEO + depends on SPL_VIDEO && SPL_PANEL help This options enables tidss driver in SPL stage. If you need to use tidss at SPL stage use this config. diff --git a/drivers/video/zynqmp/Kconfig b/drivers/video/zynqmp/Kconfig index b35cd1fb342..2c737710639 100644 --- a/drivers/video/zynqmp/Kconfig +++ b/drivers/video/zynqmp/Kconfig @@ -3,6 +3,6 @@ config VIDEO_ZYNQMP_DPSUB bool "Enable video support for ZynqMP Display Port" depends on ZYNQMP_POWER_DOMAIN help - Enable support for Xilinx ZynqMP Display Port. Currently this file - is used as placeholder for driver. The main reason is to record - compatible string and calling power domain driver. + Enable support for Xilinx ZynqMP Display Port. Currently this file + is used as placeholder for driver. The main reason is to record + compatible string and calling power domain driver. |