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-rw-r--r--drivers/clk/rockchip/clk_rk3528.c2
-rw-r--r--drivers/clk/rockchip/clk_rk3576.c54
-rw-r--r--drivers/gpio/qcom_pmic_gpio.c1
-rw-r--r--drivers/gpio/qcom_spmi_gpio.c1
-rw-r--r--drivers/power/regulator/qcom-rpmh-regulator.c106
-rw-r--r--drivers/reset/Kconfig9
-rw-r--r--drivers/reset/Makefile2
7 files changed, 123 insertions, 52 deletions
diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
index bcdc0f930d2..cf8c3a62349 100644
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -1335,6 +1335,7 @@ static ulong rk3528_clk_get_rate(struct clk *clk)
DPLL);
break;
+ case CLK_REF_USB3OTG:
case TCLK_EMMC:
case TCLK_WDT_NS:
rate = OSC_HZ;
@@ -1455,6 +1456,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
priv->cru, PPLL);
break;
+ case CLK_REF_USB3OTG:
case TCLK_EMMC:
case TCLK_WDT_NS:
return (rate == OSC_HZ) ? 0 : -EINVAL;
diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
index 1026af27ca1..db8ce25852f 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -1549,6 +1549,24 @@ static ulong rk3576_gmac_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
con = readl(&cru->clksel_con[31]);
div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT;
return DIV_TO_RATE(priv->cpll_hz, div);
+ case REFCLKO25M_GMAC0_OUT:
+ con = readl(&cru->clksel_con[36]);
+ div = (con & CLK_REFCLKO25M_GMAC0_DIV_MASK) >> CLK_REFCLKO25M_GMAC0_DIV_SHIFT;
+ src = (con & CLK_REFCLKO25M_GMAC0_SEL_MASK) >> CLK_REFCLKO25M_GMAC0_SEL_SHIFT;
+ if (src == CLK_REFCLKO25M_GMAC0_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else
+ p_rate = priv->gpll_hz;
+ return DIV_TO_RATE(p_rate, div);
+ case REFCLKO25M_GMAC1_OUT:
+ con = readl(&cru->clksel_con[36]);
+ div = (con & CLK_REFCLKO25M_GMAC1_DIV_MASK) >> CLK_REFCLKO25M_GMAC1_DIV_SHIFT;
+ src = (con & CLK_REFCLKO25M_GMAC1_SEL_MASK) >> CLK_REFCLKO25M_GMAC1_SEL_SHIFT;
+ if (src == CLK_REFCLKO25M_GMAC1_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else
+ p_rate = priv->gpll_hz;
+ return DIV_TO_RATE(p_rate, div);
default:
return -ENOENT;
}
@@ -1608,6 +1626,34 @@ static ulong rk3576_gmac_set_clk(struct rk3576_clk_priv *priv,
CLK_GMAC1_125M_DIV_MASK,
(div - 1) << CLK_GMAC1_125M_DIV_SHIFT);
break;
+ case REFCLKO25M_GMAC0_OUT:
+ if (!(priv->gpll_hz % rate)) {
+ src = CLK_REFCLKO25M_GMAC0_SEL_GPLL;
+ div = priv->gpll_hz / rate;
+ } else {
+ src = CLK_REFCLKO25M_GMAC0_SEL_CPLL;
+ div = priv->cpll_hz / rate;
+ }
+ rk_clrsetreg(&cru->clksel_con[36],
+ CLK_REFCLKO25M_GMAC0_SEL_MASK |
+ CLK_REFCLKO25M_GMAC0_DIV_MASK,
+ src << CLK_REFCLKO25M_GMAC0_SEL_SHIFT |
+ (div - 1) << CLK_REFCLKO25M_GMAC0_DIV_SHIFT);
+ break;
+ case REFCLKO25M_GMAC1_OUT:
+ if (!(priv->gpll_hz % rate)) {
+ src = CLK_REFCLKO25M_GMAC1_SEL_GPLL;
+ div = priv->gpll_hz / rate;
+ } else {
+ src = CLK_REFCLKO25M_GMAC1_SEL_CPLL;
+ div = priv->cpll_hz / rate;
+ }
+ rk_clrsetreg(&cru->clksel_con[36],
+ CLK_REFCLKO25M_GMAC1_SEL_MASK |
+ CLK_REFCLKO25M_GMAC1_DIV_MASK,
+ src << CLK_REFCLKO25M_GMAC1_SEL_SHIFT |
+ (div - 1) << CLK_REFCLKO25M_GMAC1_DIV_SHIFT);
+ break;
default:
return -ENOENT;
}
@@ -1987,6 +2033,8 @@ static ulong rk3576_clk_get_rate(struct clk *clk)
case HCLK_SDIO:
rate = rk3576_mmc_get_clk(priv, clk->id);
break;
+ case CLK_REF_USB3OTG0:
+ case CLK_REF_USB3OTG1:
case TCLK_EMMC:
case TCLK_WDT0:
rate = OSC_HZ;
@@ -2014,6 +2062,8 @@ static ulong rk3576_clk_get_rate(struct clk *clk)
case CLK_GMAC1_PTP_REF:
case CLK_GMAC0_125M_SRC:
case CLK_GMAC1_125M_SRC:
+ case REFCLKO25M_GMAC0_OUT:
+ case REFCLKO25M_GMAC1_OUT:
rate = rk3576_gmac_get_clk(priv, clk->id);
break;
case CLK_UART_FRAC_0:
@@ -2151,6 +2201,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
case HCLK_SDIO:
ret = rk3576_mmc_set_clk(priv, clk->id, rate);
break;
+ case CLK_REF_USB3OTG0:
+ case CLK_REF_USB3OTG1:
case TCLK_EMMC:
case TCLK_WDT0:
ret = OSC_HZ;
@@ -2193,6 +2245,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
case CLK_GMAC1_PTP_REF:
case CLK_GMAC0_125M_SRC:
case CLK_GMAC1_125M_SRC:
+ case REFCLKO25M_GMAC0_OUT:
+ case REFCLKO25M_GMAC1_OUT:
ret = rk3576_gmac_set_clk(priv, clk->id, rate);
break;
case CLK_UART_FRAC_0:
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 4458c55cd3d..6215f794e09 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -344,7 +344,6 @@ static int qcom_gpio_probe(struct udevice *dev)
static const struct udevice_id qcom_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
- { .compatible = "qcom,pm8998-gpio" },
{ .compatible = "qcom,pms405-gpio" },
{ .compatible = "qcom,pm6125-gpio" },
{ .compatible = "qcom,pm8150-gpio" },
diff --git a/drivers/gpio/qcom_spmi_gpio.c b/drivers/gpio/qcom_spmi_gpio.c
index 77a69140213..fc1aac8b534 100644
--- a/drivers/gpio/qcom_spmi_gpio.c
+++ b/drivers/gpio/qcom_spmi_gpio.c
@@ -752,6 +752,7 @@ static const struct udevice_id qcom_spmi_pmic_gpio_ids[] = {
{ .compatible = "qcom,pm8550b-gpio" },
{ .compatible = "qcom,pm8550ve-gpio" },
{ .compatible = "qcom,pm8550vs-gpio" },
+ { .compatible = "qcom,pm8998-gpio" },
{ .compatible = "qcom,pmk8550-gpio" },
{ .compatible = "qcom,pmr735d-gpio" },
{ }
diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c
index 4d65aae1690..f789b5b6f86 100644
--- a/drivers/power/regulator/qcom-rpmh-regulator.c
+++ b/drivers/power/regulator/qcom-rpmh-regulator.c
@@ -295,6 +295,56 @@ static int rpmh_regulator_vrm_get_value(struct udevice *rdev)
return vreg->uv;
}
+static int rpmh_regulator_vrm_set_mode_bypass(struct rpmh_vreg *vreg,
+ unsigned int mode, bool bypassed)
+{
+ struct tcs_cmd cmd = {
+ .addr = vreg->addr + RPMH_REGULATOR_REG_VRM_MODE,
+ };
+ struct dm_regulator_mode *pmic_mode;
+ int i;
+
+ if (mode > REGULATOR_MODE_HPM)
+ return -EINVAL;
+
+ for (i = 0; i < vreg->hw_data->n_modes; i++) {
+ pmic_mode = &vreg->hw_data->pmic_mode_map[i];
+ if (pmic_mode->id == mode)
+ break;
+ }
+ if (pmic_mode->id != mode) {
+ printf("Invalid mode %d\n", mode);
+ return -EINVAL;
+ }
+
+ if (bypassed)
+ // XXX: should have a version check for PMIC4 but we don't have any yet
+ // and we don't use bypass mode
+ cmd.data = PMIC5_BOB_MODE_PASS;
+ else
+ cmd.data = pmic_mode->register_value;
+
+ return rpmh_regulator_send_request(vreg, &cmd, true);
+}
+
+static int rpmh_regulator_vrm_set_mode(struct udevice *rdev,
+ int mode)
+{
+ struct rpmh_vreg *vreg = dev_get_priv(rdev);
+ int ret;
+
+ debug("%s: set_mode %d (current %d)\n", rdev->name, mode, vreg->mode);
+
+ if (mode == vreg->mode)
+ return 0;
+
+ ret = rpmh_regulator_vrm_set_mode_bypass(vreg, mode, vreg->bypassed);
+ if (!ret)
+ vreg->mode = mode;
+
+ return ret;
+}
+
static int rpmh_regulator_is_enabled(struct udevice *rdev)
{
struct rpmh_vreg *vreg = dev_get_priv(rdev);
@@ -331,6 +381,12 @@ static int rpmh_regulator_set_enable_state(struct udevice *rdev,
debug("%s: set_enable %d (current %d)\n", rdev->name, enable,
vreg->enabled);
+ if (vreg->mode != -EINVAL) {
+ ret = rpmh_regulator_vrm_set_mode_bypass(vreg, vreg->mode, vreg->bypassed);
+ if (ret < 0)
+ return ret;
+ }
+
if (vreg->enabled == -EINVAL &&
vreg->uv != -ENOTRECOVERABLE) {
ret = _rpmh_regulator_vrm_set_value(rdev,
@@ -346,56 +402,6 @@ static int rpmh_regulator_set_enable_state(struct udevice *rdev,
return ret;
}
-static int rpmh_regulator_vrm_set_mode_bypass(struct rpmh_vreg *vreg,
- unsigned int mode, bool bypassed)
-{
- struct tcs_cmd cmd = {
- .addr = vreg->addr + RPMH_REGULATOR_REG_VRM_MODE,
- };
- struct dm_regulator_mode *pmic_mode;
- int i;
-
- if (mode > REGULATOR_MODE_HPM)
- return -EINVAL;
-
- for (i = 0; i < vreg->hw_data->n_modes; i++) {
- pmic_mode = &vreg->hw_data->pmic_mode_map[i];
- if (pmic_mode->id == mode)
- break;
- }
- if (pmic_mode->id != mode) {
- printf("Invalid mode %d\n", mode);
- return -EINVAL;
- }
-
- if (bypassed)
- // XXX: should have a version check for PMIC4 but we don't have any yet
- // and we don't use bypass mode
- cmd.data = PMIC5_BOB_MODE_PASS;
- else
- cmd.data = pmic_mode->register_value;
-
- return rpmh_regulator_send_request(vreg, &cmd, true);
-}
-
-static int rpmh_regulator_vrm_set_mode(struct udevice *rdev,
- int mode)
-{
- struct rpmh_vreg *vreg = dev_get_priv(rdev);
- int ret;
-
- debug("%s: set_mode %d (current %d)\n", rdev->name, mode, vreg->mode);
-
- if (mode == vreg->mode)
- return 0;
-
- ret = rpmh_regulator_vrm_set_mode_bypass(vreg, mode, vreg->bypassed);
- if (!ret)
- vreg->mode = mode;
-
- return ret;
-}
-
static int rpmh_regulator_vrm_get_pmic_mode(struct rpmh_vreg *vreg, int *pmic_mode)
{
struct tcs_cmd cmd = {
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 485f907b041..e7c0870c918 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -116,6 +116,15 @@ config RESET_ROCKCHIP
though is that some reset signals, like I2C or MISC reset multiple
devices.
+config SPL_RESET_ROCKCHIP
+ bool "SPL reset controller driver for Rockchip SoCs"
+ depends on SPL_DM_RESET && ARCH_ROCKCHIP && SPL_CLK
+ default y
+ help
+ Support for the reset controller on Rockchip SoCs in SPL. Select this
+ if you observe any reset-related warnings or errors when booting SPL,
+ such as when using UFS storage
+
config RESET_HSDK
bool "Synopsys HSDK Reset Driver"
depends on DM_RESET && TARGET_HSDK
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index c369bdb3d6c..2c83f858895 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -18,7 +18,7 @@ obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
-obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
+obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
generated by cgit v1.3.1 (git 2.54.0) at 2026-06-14 21:21:32 +0000