diff options
Diffstat (limited to 'drivers')
102 files changed, 3491 insertions, 621 deletions
diff --git a/drivers/block/efi_blk.c b/drivers/block/efi_blk.c index f3ae70290e7..a1714c41d00 100644 --- a/drivers/block/efi_blk.c +++ b/drivers/block/efi_blk.c @@ -79,7 +79,7 @@ static const struct blk_ops efi_blk_ops = { .write = efi_bl_write, }; -U_BOOT_DRIVER(efi_block) = { +U_BOOT_DRIVER(efi_media_block) = { .name = "efi_block", .id = UCLASS_BLK, .ops = &efi_blk_ops, diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index 1d738f160b6..2449ac9fae6 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -136,7 +136,7 @@ static const struct udevice_id at91_sckc_match[] = { {} }; -U_BOOT_DRIVER(at91_sckc) = { +U_BOOT_DRIVER(at91sam9x5_sckc) = { .name = "at91-sckc", .id = UCLASS_SIMPLE_BUS, .of_match = at91_sckc_match, @@ -368,7 +368,7 @@ static const struct udevice_id at91_system_clk_match[] = { {} }; -U_BOOT_DRIVER(at91_system_clk) = { +U_BOOT_DRIVER(at91rm9200_system_clk) = { .name = "at91-system-clk", .id = UCLASS_MISC, .of_match = at91_system_clk_match, diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 3fde8ea7138..dcaffd360fd 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -162,7 +162,7 @@ static const struct udevice_id sam9x60_sckc_ids[] = { { /* Sentinel. */ }, }; -U_BOOT_DRIVER(at91_sckc) = { +U_BOOT_DRIVER(sam9x60_sckc) = { .name = UBOOT_DM_CLK_AT91_SCKC, .id = UCLASS_CLK, .of_match = sam9x60_sckc_ids, diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index ee237ed6337..12c7b1e8254 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -341,6 +341,12 @@ static int scmi_clk_probe(struct udevice *dev) if (ret) return ret; + ret = scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_CLOCK, &priv->version); + if (ret) { + dev_dbg(dev, "%s: get SCMI clock management protocol version failed\n", __func__); + return ret; + } + if (!CONFIG_IS_ENABLED(CLK_CCF)) return 0; @@ -352,12 +358,6 @@ static int scmi_clk_probe(struct udevice *dev) if (ret) return ret; - ret = scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_CLOCK, &priv->version); - if (ret) { - dev_dbg(dev, "%s: get SCMI clock management protocol version failed\n", __func__); - return ret; - } - clk_scmi_bulk = kzalloc(num_clocks * sizeof(*clk_scmi), GFP_KERNEL); if (!clk_scmi_bulk) return -ENOMEM; diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 78a2410ca21..2e0c382ef30 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -326,6 +326,7 @@ static int __versal_clock_get_parents(struct clock_parent *parents, u32 *data, parent = &parents[i]; parent->id = data[i] & CLK_PARENTS_ID_MASK; if (data[i] == DUMMY_PARENT) { + parent->id = 0; strcpy(parent->name, "dummy_name"); parent->flag = 0; } else { diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 5c38df70474..79315912fd4 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -828,8 +828,8 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = { .id = UCLASS_CLK, .of_match = mt7622_infracfg_compat, .probe = mt7622_infracfg_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_infrasys_ops, .flags = DM_FLAG_PRE_RELOC, }; @@ -838,8 +838,8 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = { .id = UCLASS_CLK, .of_match = mt7622_pericfg_compat, .probe = mt7622_pericfg_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_infrasys_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index fec908728c0..d11947ee461 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -287,12 +287,16 @@ enum { CLK_PAD_CLK32K, CLK_PAD_CLK26M, CLK_PAD_ULPOSC, + CLK_PAD_CLK13M, + CLK_PAD_AUD_ADC_EXT, }; static ulong ext_clock_rates[] = { [CLK_PAD_CLK32K] = 32000, [CLK_PAD_CLK26M] = 26 * MHZ, [CLK_PAD_ULPOSC] = 260 * MHZ, + [CLK_PAD_CLK13M] = 13 * MHZ, + [CLK_PAD_AUD_ADC_EXT] = 260 * MHZ, }; #define MT8189_PLL_FMAX (3800UL * MHZ) @@ -1637,6 +1641,298 @@ static const struct mtk_gate mminfra_config_clks[] = { GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, CLK_TOP_MMINFRA_SEL, 17), }; +static const struct mtk_gate_regs ufscfg_ao_reg_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0xc, + .sta_ofs = 0x4, +}; + +#define GATE_UFSCFG_AO_REG_EXT(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &ufscfg_ao_reg_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_EXT) + +#define GATE_UFSCFG_AO_REG_TOP(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &ufscfg_ao_reg_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate ufs_config_ao_clks[] = { + GATE_UFSCFG_AO_REG_EXT(CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM, CLK_PAD_CLK26M, 1), + GATE_UFSCFG_AO_REG_EXT(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0, CLK_PAD_CLK26M, 2), + GATE_UFSCFG_AO_REG_EXT(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1, CLK_PAD_CLK26M, 3), + GATE_UFSCFG_AO_REG_TOP(CLK_UFSCFG_AO_REG_UNIPRO_SYS, CLK_TOP_U_SEL, 4), + GATE_UFSCFG_AO_REG_EXT(CLK_UFSCFG_AO_REG_U_SAP_CFG, CLK_PAD_CLK26M, 5), + GATE_UFSCFG_AO_REG_TOP(CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS, CLK_TOP_AXI_U_SEL, 6), +}; + +static const struct mtk_gate_regs ufscfg_pdn_reg_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0xc, + .sta_ofs = 0x4, +}; + +#define GATE_UFSCFG_PDN_REG(_id, _parent, _shift) \ + GATE_FLAGS(_id, _parent, &ufscfg_pdn_reg_cg_regs, _shift, \ + CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate ufs_config_pdn_clks[] = { + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_UFS, CLK_TOP_U_SEL, 0), + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_AES, CLK_TOP_AES_UFSFDE_SEL, 1), + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AHB, CLK_TOP_AXI_U_SEL, 3), + GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AXI, CLK_TOP_MEM_SUB_U_SEL, 5), +}; + +static const struct mtk_parent vlp_26m_oscd10_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_vadsp_vowpll_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VOWPLL), +}; + +static const struct mtk_parent vlp_sspm_ulposc_parents[] = { + EXT_PARENT(CLK_PAD_ULPOSC), + TOP_PARENT(CLK_TOP_UNIVPLL_D5_D2), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_aud_adc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_VOWPLL), + EXT_PARENT(CLK_PAD_AUD_ADC_EXT), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_scp_iic_spi_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_vadsp_uarthub_b_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D2), +}; + +static const struct mtk_parent vlp_axi_kp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_OSC_D2), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D2), +}; + +static const struct mtk_parent vlp_sspm_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D2), + EXT_PARENT(CLK_PAD_ULPOSC), + TOP_PARENT(CLK_TOP_MAINPLL_D6), +}; + +static const struct mtk_parent vlp_pwm_vlp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D4), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D8), +}; + +static const struct mtk_parent vlp_pwrap_ulposc_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_OSC_D7), + TOP_PARENT(CLK_TOP_OSC_D8), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), +}; + +static const struct mtk_parent vlp_vadsp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_OSC_D20), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_OSC_D2), + EXT_PARENT(CLK_PAD_ULPOSC), + TOP_PARENT(CLK_TOP_MAINPLL_D4_D2), +}; + +static const struct mtk_parent vlp_scp_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_D4), + TOP_PARENT(CLK_TOP_UNIVPLL_D3), + TOP_PARENT(CLK_TOP_MAINPLL_D3), + TOP_PARENT(CLK_TOP_UNIVPLL_D6), + APMIXED_PARENT(CLK_APMIXED_APLL1), + TOP_PARENT(CLK_TOP_MAINPLL_D4), + TOP_PARENT(CLK_TOP_MAINPLL_D6), + TOP_PARENT(CLK_TOP_MAINPLL_D7), + TOP_PARENT(CLK_TOP_OSC_D10), +}; + +static const struct mtk_parent vlp_spmi_p_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_OSC_D8), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_OSC_D7), + EXT_PARENT(CLK_PAD_CLK32K), + TOP_PARENT(CLK_TOP_MAINPLL_D7_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D6_D8), + TOP_PARENT(CLK_TOP_MAINPLL_D5_D8), +}; + +static const struct mtk_parent vlp_camtg_parents[] = { + EXT_PARENT(CLK_PAD_CLK26M), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D8), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D4), + TOP_PARENT(CLK_TOP_OSC_D16), + TOP_PARENT(CLK_TOP_OSC_D20), + TOP_PARENT(CLK_TOP_OSC_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_D6_D16), + TOP_PARENT(CLK_TOP_TVDPLL1_D16), + TOP_PARENT(CLK_TOP_F26M_CK_D2), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D10), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D16), + TOP_PARENT(CLK_TOP_UNIVPLL_192M_D32), +}; + +static const struct mtk_composite vlp_ck_muxes[] = { + /* VLP_CLK_CFG_0 */ + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_SCP_SEL, vlp_scp_parents, + 0x008, 0x00c, 0x010, 0, 4, 7, 0x04, 0), + MUX_CLR_SET_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, vlp_pwrap_ulposc_parents, + 0x008, 0x00c, 0x010, 8, 3, 0x04, 1), + MUX_CLR_SET_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, vlp_spmi_p_parents, + 0x008, 0x00c, 0x010, 16, 4, 0x04, 2), + MUX_CLR_SET_UPD(CLK_VLP_CK_DVFSRC_SEL, vlp_26m_oscd10_parents, + 0x008, 0x00c, 0x010, 24, 1, 0x04, 3), + /* VLP_CLK_CFG_1 */ + MUX_CLR_SET_UPD(CLK_VLP_CK_PWM_VLP_SEL, vlp_pwm_vlp_parents, + 0x014, 0x018, 0x01c, 0, 3, 0x04, 4), + MUX_CLR_SET_UPD(CLK_VLP_CK_AXI_VLP_SEL, vlp_axi_kp_parents, + 0x014, 0x018, 0x01c, 8, 3, 0x04, 5), + MUX_CLR_SET_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, vlp_26m_oscd10_parents, + 0x014, 0x018, 0x01c, 16, 1, 0x04, 6), + MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_SEL, vlp_sspm_parents, + 0x014, 0x018, 0x01c, 24, 3, 0x04, 7), + /* VLP_CLK_CFG_2 */ + MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_F26M_SEL, vlp_26m_oscd10_parents, + 0x020, 0x024, 0x028, 0, 1, 0x04, 8), + MUX_CLR_SET_UPD(CLK_VLP_CK_SRCK_SEL, vlp_26m_oscd10_parents, + 0x020, 0x024, 0x028, 8, 1, 0x04, 9), + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_SEL, vlp_scp_iic_spi_parents, + 0x020, 0x024, 0x028, 16, 2, 0x04, 10), + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_SEL, vlp_scp_iic_spi_parents, + 0x020, 0x024, 0x028, 24, 2, 0x04, 11), + /* VLP_CLK_CFG_3 */ + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL, + vlp_scp_iic_spi_parents, + 0x02c, 0x030, 0x034, 0, 2, 0x04, 12), + MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL, + vlp_scp_iic_spi_parents, + 0x02c, 0x030, 0x034, 8, 2, 0x04, 13), + MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, vlp_sspm_ulposc_parents, + 0x02c, 0x030, 0x034, 16, 2, 0x04, 14), + MUX_CLR_SET_UPD(CLK_VLP_CK_APXGPT_26M_SEL, vlp_26m_oscd10_parents, + 0x02c, 0x030, 0x034, 24, 1, 0x04, 15), + /* VLP_CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_SEL, vlp_vadsp_parents, + 0x038, 0x03c, 0x040, 0, 3, 7, 0x04, 16), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_VOWPLL_SEL, + vlp_vadsp_vowpll_parents, + 0x038, 0x03c, 0x040, 8, 1, 15, 0x04, 17), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL, + vlp_vadsp_uarthub_b_parents, + 0x038, 0x03c, 0x040, 16, 2, 23, 0x04, 18), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG0_SEL, vlp_camtg_parents, + 0x038, 0x03c, 0x040, 24, 4, 31, 0x04, 19), + /* VLP_CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG1_SEL, vlp_camtg_parents, + 0x044, 0x048, 0x04c, 0, 4, 7, 0x04, 20), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG2_SEL, vlp_camtg_parents, + 0x044, 0x048, 0x04c, 8, 4, 15, 0x04, 21), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_AUD_ADC_SEL, vlp_aud_adc_parents, + 0x044, 0x048, 0x04c, 16, 2, 23, 0x04, 22), + MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, vlp_axi_kp_parents, + 0x044, 0x048, 0x04c, 24, 3, 31, 0x04, 23), +}; + +static const struct mtk_gate_regs vlp_ck_gate_regs = { + .set_ofs = 0x1f4, + .clr_ofs = 0x1f8, + .sta_ofs = 0x1f0, +}; + +#define GATE_VLP_CK(id, parent, shift, flags) \ + GATE_FLAGS(id, parent, &vlp_ck_gate_regs, shift, flags | CLK_GATE_NO_SETCLR_INV) + +#define GATE_VLP_CK_EXT(id, parent, shift) \ + GATE_VLP_CK(id, parent, shift, CLK_PARENT_EXT) + +#define GATE_VLP_CK_TOP(id, parent, shift) \ + GATE_VLP_CK(id, parent, shift, CLK_PARENT_TOPCKGEN) + +static const struct mtk_gate vlp_ck_gates[] = { + GATE_VLP_CK_EXT(CLK_VLP_CK_VADSYS_VLP_26M_EN, CLK_PAD_CLK26M, 1), + GATE_VLP_CK_EXT(CLK_VLP_CK_SEJ_13M_EN, CLK_PAD_CLK13M, 4), + GATE_VLP_CK_EXT(CLK_VLP_CK_SEJ_26M_EN, CLK_PAD_CLK26M, 5), + GATE_VLP_CK_TOP(CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN, CLK_TOP_OSC_D10, 11), +}; + +static const struct mtk_gate_regs vlpcfg_ao_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x4, + .sta_ofs = 0x4, +}; + +/* + * REVISIT: this is currently the only clock tree using the infrasys ops so we + * are using it instead of introducing a new parent in the core code. Instead, + * we should eventually rework the core code to do a better job of supporting + * arbitrary parent trees. + */ +#define CLK_PARENT_VLP_CK CLK_PARENT_INFRASYS + +#define GATE_VLPCFG_AO(id, parent, shift, flags) \ + GATE_FLAGS(id, parent, &vlpcfg_ao_regs, shift, flags | CLK_GATE_NO_SETCLR_INV) + +#define GATE_VLPCFG_AO_EXT(id, parent, shift) \ + GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_EXT) + +#define GATE_VLPCFG_AO_TOP(id, parent, shift) \ + GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_TOPCKGEN) + +#define GATE_VLPCFG_AO_VLP(id, parent, shift) \ + GATE_VLPCFG_AO(id, parent, shift, CLK_PARENT_VLP_CK) + +static const struct mtk_gate vlpcfg_ao_clks[] = { + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SCP, CLK_VLP_CK_SCP_SEL, 28), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_RG_R_APXGPT_26M, CLK_PAD_CLK26M, 24), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_DPMSRCK_TEST, CLK_PAD_CLK26M, 23), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, CLK_PAD_CLK32K, 22), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DPMSRULP_TEST, CLK_TOP_OSC_D10, 21), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SPMI_P_MST, CLK_VLP_CK_SPMI_P_MST_SEL, 20), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SPMI_P_MST_32K, CLK_PAD_CLK32K, 18), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 13), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_TMR, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 12), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_M_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 11), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_M_TMR, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 10), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DVFSRC, CLK_VLP_CK_DVFSRC_SEL, 9), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PWM_VLP, CLK_VLP_CK_PWM_VLP_SEL, 8), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SRCK, CLK_VLP_CK_SRCK_SEL, 7), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SSPM_F26M, CLK_VLP_CK_SSPM_F26M_SEL, 4), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SSPM_F32K, CLK_PAD_CLK32K, 3), + GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SSPM_ULPOSC, CLK_VLP_CK_SSPM_ULPOSC_SEL, 2), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_VLP_32K_COM, CLK_PAD_CLK32K, 1), + GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_VLP_26M_COM, CLK_PAD_CLK26M, 0), +}; + static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = { .pll_parent = EXT_PARENT(CLK_PAD_CLK26M), .ext_clk_rates = ext_clock_rates, @@ -1659,6 +1955,17 @@ static const struct mtk_clk_tree mt8189_topckgen_clk_tree = { .num_gates = ARRAY_SIZE(top_gates), }; +static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), + .muxes_offs = CLK_VLP_CK_SCP_SEL, + .gates_offs = CLK_VLP_CK_VADSYS_VLP_26M_EN, + .muxes = vlp_ck_muxes, + .gates = vlp_ck_gates, + .num_muxes = ARRAY_SIZE(vlp_ck_muxes), + .num_gates = ARRAY_SIZE(vlp_ck_gates), +}; + static const struct udevice_id mt8189_apmixed[] = { { .compatible = "mediatek,mt8189-apmixedsys", }, { } @@ -1669,6 +1976,11 @@ static const struct udevice_id mt8189_topckgen_compat[] = { { } }; +static const struct udevice_id mt8189_vlpckgen[] = { + { .compatible = "mediatek,mt8189-vlpckgen", }, + { } +}; + struct mt8189_gate_clk_data { const struct mtk_gate *gates; int num_gates; @@ -1683,12 +1995,18 @@ GATE_CLK_DATA(perao_clks); GATE_CLK_DATA(imp_clks); GATE_CLK_DATA(mm_clks); GATE_CLK_DATA(mminfra_config_clks); +GATE_CLK_DATA(ufs_config_ao_clks); +GATE_CLK_DATA(ufs_config_pdn_clks); +GATE_CLK_DATA(vlpcfg_ao_clks); static const struct udevice_id of_match_mt8189_clk_gate[] = { { .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_data }, { .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_data }, { .compatible = "mediatek,mt8189-dispsys", .data = (ulong)&mm_clks_data }, { .compatible = "mediatek,mt8189-mm-infra", .data = (ulong)&mminfra_config_clks_data }, + { .compatible = "mediatek,mt8189-ufscfg-ao", .data = (ulong)&ufs_config_ao_clks_data }, + { .compatible = "mediatek,mt8189-ufscfg-pdn", .data = (ulong)&ufs_config_pdn_clks_data }, + { .compatible = "mediatek,mt8189-vlpcfg-ao", .data = (ulong)&vlpcfg_ao_clks_data }, { } }; @@ -1702,6 +2020,11 @@ static int mt8189_topckgen_probe(struct udevice *dev) return mtk_common_clk_init(dev, &mt8189_topckgen_clk_tree); } +static int mt8189_infrasys_probe(struct udevice *dev) +{ + return mtk_common_clk_infrasys_init(dev, &mt8189_vlpckgen_clk_tree); +} + static int mt8189_clk_gate_probe(struct udevice *dev) { struct mt8189_gate_clk_data *data; @@ -1733,6 +2056,16 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .flags = DM_FLAG_PRE_RELOC, }; +U_BOOT_DRIVER(mtk_clk_vlpckgen) = { + .name = "mt8189-vlpckgen", + .id = UCLASS_CLK, + .of_match = mt8189_vlpckgen, + .probe = mt8189_infrasys_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_infrasys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + U_BOOT_DRIVER(mtk_clk_gate) = { .name = "mt8189-gate-clk", .id = UCLASS_CLK, diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 3557aeac3d5..9d0a6cd79cf 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -204,10 +204,6 @@ static ulong mtk_clk_find_parent_rate(struct clk *clk, int id, return clk_get_rate(&parent); } -const struct clk_ops mtk_clk_apmixedsys_ops; -const struct clk_ops mtk_clk_topckgen_ops; -const struct clk_ops mtk_clk_infrasys_ops; - static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, const int parent, u16 flags) { @@ -216,15 +212,21 @@ static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk, switch (flags & CLK_PARENT_MASK) { case CLK_PARENT_APMIXED: /* APMIXEDSYS can be parent or grandparent. */ - if (dev_get_driver_ops(clk->dev) == &mtk_clk_apmixedsys_ops) + if (dev_get_driver_ops(clk->dev) == &mtk_clk_apmixedsys_ops || + dev_get_driver_ops(clk->dev) == &mtk_clk_fixed_pll_ops) { parent_dev = clk->dev; - else if (dev_get_driver_ops(priv->parent) == &mtk_clk_apmixedsys_ops) + } else if (dev_get_driver_ops(priv->parent) == &mtk_clk_apmixedsys_ops || + dev_get_driver_ops(priv->parent) == &mtk_clk_fixed_pll_ops) { parent_dev = priv->parent; - else if (dev_get_driver_ops(dev_get_parent(priv->parent)) == &mtk_clk_apmixedsys_ops) - parent_dev = dev_get_parent(priv->parent); - else - return -EINVAL; - + } else { + struct udevice *grandparent_dev = dev_get_parent(priv->parent); + + if (dev_get_driver_ops(grandparent_dev) == &mtk_clk_apmixedsys_ops || + dev_get_driver_ops(grandparent_dev) == &mtk_clk_fixed_pll_ops) + parent_dev = grandparent_dev; + else + return -EINVAL; + } break; case CLK_PARENT_TOPCKGEN: if (dev_get_driver_ops(clk->dev) == &mtk_clk_topckgen_ops) diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c index a1b8d791491..669247a9a09 100644 --- a/drivers/clk/meson/a1.c +++ b/drivers/clk/meson/a1.c @@ -712,7 +712,7 @@ static struct clk_ops meson_clk_ops = { #endif }; -U_BOOT_DRIVER(meson_clk) = { +U_BOOT_DRIVER(meson_clk_a1) = { .name = "meson-clk-a1", .id = UCLASS_CLK, .of_match = meson_clk_ids, diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 51f124869c9..218be45c2cb 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -962,7 +962,7 @@ static const struct udevice_id meson_clk_ids[] = { { } }; -U_BOOT_DRIVER(meson_clk) = { +U_BOOT_DRIVER(meson_clk_gxbb) = { .name = "meson_clk", .id = UCLASS_CLK, .of_match = meson_clk_ids, diff --git a/drivers/clk/nuvoton/clk_npcm7xx.c b/drivers/clk/nuvoton/clk_npcm7xx.c index b23dd37af6c..4c787823d05 100644 --- a/drivers/clk/nuvoton/clk_npcm7xx.c +++ b/drivers/clk/nuvoton/clk_npcm7xx.c @@ -84,7 +84,7 @@ static const struct udevice_id npcm7xx_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_npcm) = { +U_BOOT_DRIVER(clk_npcm750) = { .name = "clk_npcm", .id = UCLASS_CLK, .of_match = npcm7xx_clk_ids, diff --git a/drivers/clk/nuvoton/clk_npcm8xx.c b/drivers/clk/nuvoton/clk_npcm8xx.c index d1b32e32371..c7a510f5c25 100644 --- a/drivers/clk/nuvoton/clk_npcm8xx.c +++ b/drivers/clk/nuvoton/clk_npcm8xx.c @@ -87,7 +87,7 @@ static const struct udevice_id npcm8xx_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_npcm) = { +U_BOOT_DRIVER(clk_npcm845) = { .name = "clk_npcm", .id = UCLASS_CLK, .of_match = npcm8xx_clk_ids, diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c index 4700baba8c9..2087fc38f63 100644 --- a/drivers/clk/qcom/clock-qcs615.c +++ b/drivers/clk/qcom/clock-qcs615.c @@ -66,6 +66,8 @@ static const struct gate_clk qcs615_clks[] = { GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)), + GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT), diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 39ec06a9556..5e88cf63e20 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -2193,7 +2193,7 @@ static int stm32mp1_clk_probe(struct udevice *dev) return 0; } -U_BOOT_DRIVER(stm32mp1_clock) = { +U_BOOT_DRIVER(stm32mp13_clock) = { .name = "stm32mp13_clk", .id = UCLASS_CLK, .ops = &stm32_clk_ops, diff --git a/drivers/core/device.c b/drivers/core/device.c index 779f371b9d5..d365204ba11 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -473,7 +473,11 @@ static int device_get_dma_constraints(struct udevice *dev) return ret; } - dev_set_dma_offset(dev, cpu - bus); +#if CONFIG_IS_ENABLED(DM_DMA) + dev->dma_cpu = cpu; + dev->dma_bus = bus; + dev->dma_size = size; +#endif return 0; } diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index b11e36202c1..969492aae37 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -598,6 +598,25 @@ int of_read_u64(const struct device_node *np, const char *propname, u64 *outp) return of_read_u64_index(np, propname, 0, outp); } +int of_read_u64_array(const struct device_node *np, const char *propname, + u64 *out_values, size_t sz) +{ + const __be64 *val; + + log_debug("%s: %s: ", __func__, propname); + val = of_find_property_value_of_size(np, propname, + sz * sizeof(*out_values)); + + if (IS_ERR(val)) + return PTR_ERR(val); + + log_debug("size %zd\n", sz); + while (sz--) + *out_values++ = be64_to_cpup(val++); + + return 0; +} + int of_property_match_string(const struct device_node *np, const char *propname, const char *string) { @@ -845,6 +864,39 @@ int of_count_phandle_with_args(const struct device_node *np, cell_count); } +/** + * of_property_count_elems_of_size - Count the number of elements in a property + * + * @np: device node from which the property value is to be read. + * @propname: name of the property to be searched. + * @elem_size: size of the individual element + * + * Search for a property in a device node and count the number of elements of + * size elem_size in it. + * + * Return: The number of elements on sucess, -EINVAL if the property does not + * exist or its length does not match a multiple of elem_size and -ENODATA if + * the property does not have a value. + */ +int of_property_count_elems_of_size(const struct device_node *np, + const char *propname, int elem_size) +{ + const struct property *prop = of_find_property(np, propname, NULL); + + if (!prop) + return -EINVAL; + if (!prop->value) + return -ENODATA; + + if (prop->length % elem_size != 0) { + pr_err("size of %s in node %pOF is not a multiple of %d\n", + propname, np, elem_size); + return -EINVAL; + } + + return prop->length / elem_size; +} + static void of_alias_add(struct alias_prop *ap, struct device_node *np, int id, const char *stem, int stem_len) { diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 3a36b6fdd03..d605c0f7b7c 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -664,6 +664,54 @@ int ofnode_read_u32_array(ofnode node, const char *propname, } } +int ofnode_read_u64_array(ofnode node, const char *propname, + u64 *out_values, size_t sz) +{ + assert(ofnode_valid(node)); + log_debug("%s: %s: ", __func__, propname); + + if (ofnode_is_np(node)) { + return of_read_u64_array(ofnode_to_np(node), propname, + out_values, sz); + } else { + int ret; + + ret = fdtdec_get_long_array(ofnode_to_fdt(node), + ofnode_to_offset(node), propname, + out_values, sz); + + /* get the error right, but space is more important in SPL */ + if (!IS_ENABLED(CONFIG_XPL_BUILD)) { + if (ret == -FDT_ERR_NOTFOUND) + return -EINVAL; + else if (ret == -FDT_ERR_BADLAYOUT) + return -EOVERFLOW; + } + return ret; + } +} + +int ofnode_count_elems_of_size(ofnode node, const char *propname, int elem_size) +{ + const char *prop; + int len; + assert(ofnode_valid(node)); + + if (ofnode_is_np(node)) { + return of_property_count_elems_of_size(node.np, propname, elem_size); + } else { + prop = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node), propname, &len); + if (!prop) + return -ENOENT; + if (len % elem_size != 0) { + log_debug("size of %s in node %pOF is not a multiple of %d\n", + propname, &node, elem_size); + return -EINVAL; + } + return len / elem_size; + } +} + #if !CONFIG_IS_ENABLED(DM_INLINE_OFNODE) bool ofnode_is_enabled(ofnode node) { diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index 0a45340ffb6..b953bca4f06 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -24,9 +24,9 @@ config IMX9_DRAM_INLINE_ECC config SAVED_DRAM_TIMING_BASE hex "Define the base address for saved dram timing" + default 0x2051C000 help after DRAM is trained, need to save the dram related timming info into memory for low power use. - default 0x2051C000 endmenu diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c index b0dfc3a0b4f..147ec9ab061 100644 --- a/drivers/ddr/imx/phy/helper.c +++ b/drivers/ddr/imx/phy/helper.c @@ -38,6 +38,8 @@ binman_sym_declare(ulong, ddr_2d_dmem_fw, image_pos); binman_sym_declare(ulong, ddr_2d_dmem_fw, size); #endif +binman_sym_declare(ulong, u_boot_spl, image_pos); + /* We need PHY iMEM PHY is 32KB padded */ void ddr_load_train_firmware(enum fw_type type) { @@ -49,6 +51,7 @@ void ddr_load_train_firmware(enum fw_type type) unsigned long dmem_start; unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN; static enum fw_type last_type = -1; + unsigned long spl_start = 0; /* If FW doesn't change, we can save the loading. */ if (last_type == type) @@ -67,6 +70,9 @@ void ddr_load_train_firmware(enum fw_type type) dmem_start = imem_start + imem_len; if (BINMAN_SYMS_OK) { + if (IS_ENABLED(CONFIG_IMX8MQ)) + spl_start = binman_sym(ulong, u_boot_spl, image_pos); + switch (type) { case FW_1D_IMAGE: imem_start = binman_sym(ulong, ddr_1d_imem_fw, image_pos); @@ -83,6 +89,13 @@ void ddr_load_train_firmware(enum fw_type type) #endif break; } + + if (IS_ENABLED(CONFIG_IMX8MQ)) { + imem_start -= spl_start; + imem_start += CONFIG_SPL_TEXT_BASE; + dmem_start -= spl_start; + dmem_start += CONFIG_SPL_TEXT_BASE; + } } pr_from32 = imem_start; diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 01824310995..5b440bb38b8 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2866,7 +2866,7 @@ static const struct udevice_id udma_ids[] = { { /* Sentinel */ }, }; -U_BOOT_DRIVER(ti_edma3) = { +U_BOOT_DRIVER(ti_udma) = { .name = "ti-udma", .id = UCLASS_DMA, .of_match = udma_ids, diff --git a/drivers/firmware/scmi/pinctrl.c b/drivers/firmware/scmi/pinctrl.c index 47f7a8ad9b8..e670538c87f 100644 --- a/drivers/firmware/scmi/pinctrl.c +++ b/drivers/firmware/scmi/pinctrl.c @@ -259,6 +259,8 @@ static int scmi_pinctrl_settings_configure_helper(struct udevice *dev, in->attr = 0; in->attr |= FIELD_PREP(GENMASK(9, 2), num_configs); in->attr |= FIELD_PREP(GENMASK(1, 0), select_type); + if (function_id != SCMI_PINCTRL_FUNCTION_NONE) + in->attr |= BIT(10); memcpy(in->configs, configs, num_configs * sizeof(u32) * 2); ret = devm_scmi_process_msg(dev, &msg); diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 25b348648ef..44d7ad6bd54 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -11,6 +11,7 @@ * Xilinx FPGA support */ +#include <env.h> #include <fpga.h> #include <log.h> #include <virtex2.h> @@ -92,7 +93,11 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, __func__); printf("%s: Bitstream ID %s, current device ID %d/%s\n", __func__, dataptr, devnum, xdesc->name); - return FPGA_FAIL; + if (!CONFIG_IS_ENABLED(ENV_SUPPORT) || + env_get_yesno("fpga_skip_idcheck") != 1) + return FPGA_FAIL; + + printf("%s: Skipping ID check\n", __func__); } } else { printf("%s: Please fill correct device ID to xilinx_desc\n", diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1484dd3504c..0b5466b39b8 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -732,6 +732,12 @@ config SLG7XL45106_I2C_GPO 8-bit gpo expander, all gpo lines are controlled by writing value into data register. +config GPIO_SCMI + bool "SCMI GPIO pinctrl driver" + depends on DM_GPIO && PINCTRL_SCMI + help + Support pinctrl GPIO over the SCMI interface. + config ADP5585_GPIO bool "ADP5585 GPIO driver" depends on DM_GPIO && DM_I2C diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fec258f59f5..863557e45ce 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ADP5588_GPIO) += adp5588_gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o +obj-$(CONFIG_GPIO_SCMI) += gpio_scmi.o obj-$(CONFIG_$(PHASE_)ADP5585_GPIO) += adp5585_gpio.o obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o obj-$(CONFIG_MPFS_GPIO) += mpfs_gpio.o diff --git a/drivers/gpio/gpio_scmi.c b/drivers/gpio/gpio_scmi.c new file mode 100644 index 00000000000..d25e3b6a4aa --- /dev/null +++ b/drivers/gpio/gpio_scmi.c @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Linaro Ltd. + */ + +#include <asm/gpio.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <linux/list.h> +#include <scmi_protocols.h> + +struct scmi_gpio_range { + u32 base; + u32 offset; + u32 npins; + struct list_head list; +}; + +static int bank_cnt; + +struct scmi_gpio_priv { + struct udevice *pin_dev; + struct list_head gpio_ranges; + char *bank_name; + u32 num_pins; + u16 *pins; +}; + +static int scmi_gpio_request(struct udevice *dev, unsigned int offset, const char *label) +{ + struct scmi_gpio_priv *priv = dev_get_priv(dev); + int pin; + int ret; + + if (offset >= priv->num_pins) + return -EINVAL; + pin = priv->pins[offset]; + + ret = scmi_pinctrl_request(priv->pin_dev, SCMI_PIN, pin); + if (ret == -EOPNOTSUPP) + ret = 0; + if (ret) + dev_err(dev, "%s(): request failed: %d\n", __func__, ret); + return ret; +} + +static int scmi_gpio_rfree(struct udevice *dev, unsigned int offset) +{ + struct scmi_gpio_priv *priv = dev_get_priv(dev); + int pin; + int ret; + + if (offset >= priv->num_pins) + return -EINVAL; + pin = priv->pins[offset]; + + ret = scmi_pinctrl_release(priv->pin_dev, SCMI_PIN, pin); + if (ret == -EOPNOTSUPP) + ret = 0; + if (ret) + dev_err(dev, "%s(): release failed: %d\n", __func__, ret); + return ret; +} + +static int scmi_gpio_set_flags(struct udevice *dev, unsigned int offset, ulong flags) +{ + struct scmi_gpio_priv *priv = dev_get_priv(dev); + const int MAX_FLAGS = 10; + u32 configs[MAX_FLAGS * 2]; + int cnt = 0; + u32 pin; + + if (offset >= priv->num_pins) + return -EINVAL; + pin = priv->pins[offset]; + + if (flags & GPIOD_IS_OUT) { + configs[cnt++] = SCMI_PIN_OUTPUT_MODE; + configs[cnt++] = 1; + configs[cnt++] = SCMI_PIN_OUTPUT_VALUE; + if (flags & GPIOD_IS_OUT_ACTIVE) + configs[cnt++] = 1; + else + configs[cnt++] = 0; + } + if (flags & GPIOD_IS_IN) { + configs[cnt++] = SCMI_PIN_INPUT_MODE; + configs[cnt++] = 1; + } + if (flags & GPIOD_OPEN_DRAIN) { + configs[cnt++] = SCMI_PIN_DRIVE_OPEN_DRAIN; + configs[cnt++] = 1; + } + if (flags & GPIOD_OPEN_SOURCE) { + configs[cnt++] = SCMI_PIN_DRIVE_OPEN_SOURCE; + configs[cnt++] = 1; + } + if (flags & GPIOD_PULL_UP) { + configs[cnt++] = SCMI_PIN_BIAS_PULL_UP; + configs[cnt++] = 1; + } + if (flags & GPIOD_PULL_DOWN) { + configs[cnt++] = SCMI_PIN_BIAS_PULL_DOWN; + configs[cnt++] = 1; + } + /* TODO: handle GPIOD_ACTIVE_LOW and GPIOD_IS_AF flags */ + + return scmi_pinctrl_settings_configure(priv->pin_dev, SCMI_PIN, pin, + cnt / 2, &configs[0]); +} + +static int scmi_gpio_get_value(struct udevice *dev, unsigned int offset) +{ + struct scmi_gpio_priv *priv = dev_get_priv(dev); + u32 value; + int pin; + int ret; + + if (offset >= priv->num_pins) + return -EINVAL; + pin = priv->pins[offset]; + + ret = scmi_pinctrl_settings_get_one(priv->pin_dev, SCMI_PIN, pin, + SCMI_PIN_INPUT_VALUE, &value); + if (ret) { + dev_err(dev, "settings_get_one() failed: %d\n", ret); + return ret; + } + + return value; +} + +static int scmi_gpio_get_function(struct udevice *dev, unsigned int offset) +{ + struct scmi_gpio_priv *priv = dev_get_priv(dev); + u32 value; + int pin; + int ret; + + if (offset >= priv->num_pins) + return -EINVAL; + pin = priv->pins[offset]; + + ret = scmi_pinctrl_settings_get_one(priv->pin_dev, SCMI_PIN, pin, + SCMI_PIN_INPUT_MODE, + &value); + if (ret) { + dev_err(dev, "settings_get() failed %d\n", ret); + return ret; + } + + if (value) + return GPIOF_INPUT; + return GPIOF_OUTPUT; +} + +static const struct dm_gpio_ops scmi_gpio_ops = { + .request = scmi_gpio_request, + .rfree = scmi_gpio_rfree, + .set_flags = scmi_gpio_set_flags, + .get_value = scmi_gpio_get_value, + .get_function = scmi_gpio_get_function, +}; + +static int scmi_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct scmi_gpio_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + struct scmi_gpio_range *range; + int index = 0; + int ret, i; + + INIT_LIST_HEAD(&priv->gpio_ranges); + + for (;; index++) { + ret = dev_read_phandle_with_args(dev, "gpio-ranges", + NULL, 3, index, &args); + if (ret) + break; + + if (index == 0) { + ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL, + args.node, + &priv->pin_dev); + if (ret) { + dev_err(dev, "failed to find pinctrl device: %d\n", ret); + return ret; + } + } + + range = devm_kmalloc(dev, sizeof(*range), GFP_KERNEL); + if (!range) + return -ENOMEM; + + range->base = args.args[0]; + if (range->base != priv->num_pins) { + dev_err(dev, "no gaps allowed in between pins %d vs %d\n", + priv->num_pins, range->base); + return -EINVAL; + } + range->offset = args.args[1]; + range->npins = args.args[2]; + priv->num_pins += args.args[2]; + list_add_tail(&range->list, &priv->gpio_ranges); + } + + if (priv->num_pins == 0) { + dev_err(dev, "failed to registier pin-groups\n"); + return -EINVAL; + } + + priv->pins = devm_kzalloc(dev, priv->num_pins * sizeof(u16), GFP_KERNEL); + if (!priv->pins) + return -ENOMEM; + + list_for_each_entry(range, &priv->gpio_ranges, list) { + for (i = 0; i < range->npins; i++) + priv->pins[range->base + i] = range->offset + i; + } + + ret = snprintf(NULL, 0, "gpio_scmi%d_", bank_cnt); + uc_priv->bank_name = devm_kzalloc(dev, ret + 1, GFP_KERNEL); + if (!uc_priv->bank_name) + return -ENOMEM; + snprintf((char *)uc_priv->bank_name, ret + 1, "gpio_scmi%d_", bank_cnt); + bank_cnt++; + + uc_priv->gpio_count = priv->num_pins; + + return 0; +} + +static const struct udevice_id scmi_gpio_match[] = { + { .compatible = "scmi-pinctrl-gpio" }, + { } +}; + +U_BOOT_DRIVER(scmi_pinctrl_gpio) = { + .name = "scmi_pinctrl_gpio", + .id = UCLASS_GPIO, + .of_match = scmi_gpio_match, + .probe = scmi_gpio_probe, + .priv_auto = sizeof(struct scmi_gpio_priv), + .ops = &scmi_gpio_ops, +}; + diff --git a/drivers/i2c/tegra186_bpmp_i2c.c b/drivers/i2c/tegra186_bpmp_i2c.c index d30eb523122..b76ef016cda 100644 --- a/drivers/i2c/tegra186_bpmp_i2c.c +++ b/drivers/i2c/tegra186_bpmp_i2c.c @@ -117,7 +117,7 @@ static const struct udevice_id tegra186_bpmp_i2c_ids[] = { { } }; -U_BOOT_DRIVER(i2c_gpio) = { +U_BOOT_DRIVER(tegra186_bpmp_i2c) = { .name = "tegra186_bpmp_i2c", .id = UCLASS_I2C, .of_match = tegra186_bpmp_i2c_ids, diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 5bf122c5505..df8fbf1551d 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -64,7 +64,7 @@ config CPCAP_POWER_BUTTON config CROS_EC_KEYB bool "Enable Chrome OS EC keyboard support" - depends on INPUT + depends on INPUT && CROS_EC help Most ARM Chromebooks use an EC to provide access to the keyboard. Messages are used to request key scans from the EC and these are @@ -72,7 +72,7 @@ config CROS_EC_KEYB config SPL_CROS_EC_KEYB bool "Enable Chrome OS EC keyboard support in SPL" - depends on SPL_INPUT + depends on SPL_INPUT && SPL_CROS_EC help Most ARM Chromebooks use an EC to provide access to the keyboard. Messages are used to request key scans from the EC and these are @@ -80,7 +80,7 @@ config SPL_CROS_EC_KEYB config TPL_CROS_EC_KEYB bool "Enable Chrome OS EC keyboard support in TPL" - depends on TPL_INPUT + depends on TPL_INPUT && TPL_CROS_EC help Most ARM Chromebooks use an EC to provide access to the keyboard. Messages are used to request key scans from the EC and these are diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c index 598a51d914a..655d9902dfa 100644 --- a/drivers/mmc/bcm2835_sdhci.c +++ b/drivers/mmc/bcm2835_sdhci.c @@ -243,7 +243,7 @@ static const struct udevice_id bcm2835_sdhci_match[] = { { /* sentinel */ } }; -U_BOOT_DRIVER(sdhci_cdns) = { +U_BOOT_DRIVER(sdhci_bcm2835) = { .name = "sdhci-bcm2835", .id = UCLASS_MMC, .of_match = bcm2835_sdhci_match, diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 335b44a8a1a..87125493c0d 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1686,7 +1686,7 @@ static int fsl_esdhc_bind(struct udevice *dev) return mmc_bind(dev, &plat->mmc, &plat->cfg); } -U_BOOT_DRIVER(fsl_esdhc) = { +U_BOOT_DRIVER(fsl_esdhc_imx) = { .name = "fsl_esdhc", .id = UCLASS_MMC, .of_match = fsl_esdhc_ids, diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 8116e464278..b685da8643c 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -745,7 +745,7 @@ static const struct udevice_id sdhci_ids[] = { { } }; -U_BOOT_DRIVER(arasan_sdhci_drv) = { +U_BOOT_DRIVER(rockchip_sdhci_5_1_drv) = { .name = "rockchip_sdhci_5_1", .id = UCLASS_MMC, .of_match = sdhci_ids, diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 56f6fb70acd..de78a6cb707 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -157,6 +157,11 @@ config SPI_FLASH_ATMEL help Add support for various Atmel SPI flash chips (AT45xxx and AT25xxx) +config SPI_FLASH_DOSILICON + bool "Dosilicon SPI flash support" + help + Add support for various Dosilicon SPI flash chips (DS25xxx) + config SPI_FLASH_EON bool "EON SPI flash support" help @@ -215,6 +220,7 @@ config SPI_FLASH_MT35XU config SPI_FLASH_SST bool "SST SPI flash support" + depends on SPI_FLASH_LOCK help Add support for various SST SPI flash chips (SST25xxx) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index e7fea375706..c0fa98424aa 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -77,6 +77,17 @@ const struct flash_info spi_nor_ids[] = { { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, #endif +#ifdef CONFIG_SPI_FLASH_DOSILICON + /* Dosilicon Co., Ltd */ + { INFO("ds25m4cb", 0xe5401a, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("ds25m4dn", 0xe5401b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("ds25q4cb", 0xe5301a, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("ds25q4dn", 0xe5301b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, +#endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ /* EON -- en25xxx */ { INFO("en25q80b", 0x1c3014, 0, 64 * 1024, 16, SECT_4K) }, @@ -202,6 +213,8 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + {INFO("gd25lx128j", 0xc86818, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_OCTAL_READ)}, { INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) @@ -233,6 +246,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp512mj", 0x9d6020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, @@ -248,16 +263,44 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_4B_OPCODES) }, { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp512mj", 0x9d7020, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp01gg", 0x9d7021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wx128", 0x9d5b18, 0, 64 * 1024, 256, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ) }, { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + { INFO("is25lx128", 0x9d5a18, 0, 64 * 1024, 256, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ) }, { INFO("is25lx512", 0x9d5a1a, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) }, { INFO("is25lp01gg", 0x9d6021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, + { INFO("is25lp010e", 0x9d4011, 0, 64 * 1024, 2, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp020e", 0x9d4012, 0, 64 * 1024, 4, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp040e", 0x9d4013, 0, 64 * 1024, 8, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp01gj", 0x9d6021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, + { INFO("is25lp02gg", 0x9d6022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, + { INFO("is25lp02gj", 0x9d6022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, + { INFO("is25wp01gg", 0x9d7021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, + { INFO("is25wp01gj", 0x9d7021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, + { INFO("is25wj128f", 0x9d7118, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, { INFO("is25wp02gg", 0x9d7022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, + { INFO("is25wp02gj", 0x9d7022, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -272,7 +315,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) }, - { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) }, + { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, @@ -338,6 +382,18 @@ const struct flash_info spi_nor_ids[] = { { INFO ("p25q128h", 0x856018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO + ("py25f512hb", 0x85231a, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO + ("py25f01ghb", 0x85231b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO + ("py25f512lc", 0x85631a, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO + ("py25f01glc", 0x85631b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SILICONKAISER @@ -618,6 +674,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("XM25QH512C", 0x204020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("XM25QU512C", 0x204120, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("XM25QH01D", 0x204021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_XTX /* XTX Technology Limited */ diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index ebb399457fb..92990fa6d47 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -597,7 +597,7 @@ static const struct udevice_id xgmac_eth_ids[] = { { } }; -U_BOOT_DRIVER(eth_xgmac) = { +U_BOOT_DRIVER(calxeda_hb_xgmac) = { .name = "eth_xgmac", .id = UCLASS_ETH, .of_match = xgmac_eth_ids, diff --git a/drivers/net/dwc_eth_qos_adi.c b/drivers/net/dwc_eth_qos_adi.c index b578225eaad..37db8525b48 100644 --- a/drivers/net/dwc_eth_qos_adi.c +++ b/drivers/net/dwc_eth_qos_adi.c @@ -15,7 +15,7 @@ #include <reset.h> #include <linux/io.h> -#include <asm/arch-adi/sc5xx/sc5xx.h> +#include <asm/arch/sc5xx.h> #include "dwc_eth_qos.h" diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c index 2ab5ec5f0d9..311b57011c3 100644 --- a/drivers/net/dwc_eth_xgmac.c +++ b/drivers/net/dwc_eth_xgmac.c @@ -1206,7 +1206,7 @@ static const struct udevice_id xgmac_ids[] = { { } }; -U_BOOT_DRIVER(eth_xgmac) = { +U_BOOT_DRIVER(dwc_eth_xgmac) = { .name = "eth_xgmac", .id = UCLASS_ETH, .of_match = of_match_ptr(xgmac_ids), diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index c8ed702f50a..e28f8d96ed7 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2017-2018, 2020-2021 NXP + * Copyright 2017-2018, 2020-2021, 2025 NXP */ #include <config.h> #include <command.h> @@ -72,6 +72,7 @@ static u64 mc_lazy_dpl_addr; static u32 dpsparser_obj_id; static u16 dpsparser_handle; static char *mc_err_msg_apply_spb[] = MC_ERROR_MSG_APPLY_SPB; +static bool wait_for_dpl; #ifdef DEBUG void dump_ram_words(const char *title, void *addr) @@ -653,7 +654,7 @@ static int load_mc_aiop_img(u64 aiop_fw_addr) } #endif -static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr) +static int wait_for_mc(u32 *final_reg_gsr) { u32 reg_gsr; u32 mc_fw_boot_status; @@ -792,7 +793,7 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) * Deassert reset and release MC core 0 to run */ out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST); - error = wait_for_mc(true, ®_gsr); + error = wait_for_mc(®_gsr); if (error != 0) goto out; @@ -855,13 +856,20 @@ int mc_apply_dpl(u64 mc_dpl_addr) * Tell the MC to deploy the DPL: */ out_le32(&mc_ccsr_regs->reg_gsr, 0x0); - printf("fsl-mc: Deploying data path layout ... "); - error = wait_for_mc(false, ®_gsr); - if (!error) - mc_dpl_applied = 0; + /* Wait for the MC firmware to finish processing the DPL */ + if (wait_for_dpl) { + printf("fsl-mc: Deploying data path layout ... "); + error = wait_for_mc(®_gsr); + if (error) + return error; + } else { + printf("fsl-mc: Started the DPL deploy process\n"); + } - return error; + mc_dpl_applied = 0; + + return 0; } int get_mc_boot_status(void) @@ -1995,6 +2003,11 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, * later from announce_and_cleanup(). */ mc_lazy_dpl_addr = mc_dpl_addr; + + wait_for_dpl = true; + if (argc >= 5 && strcmp(argv[4], "nowait") == 0) + wait_for_dpl = false; + break; } @@ -2023,6 +2036,10 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, mc_apply_addr = simple_strtoull(argv[3], NULL, 16); + wait_for_dpl = true; + if (argc >= 5 && strcmp(argv[4], "nowait") == 0) + wait_for_dpl = false; + /* The user wants DPL applied now */ if (!fsl_mc_ldpaa_exit(NULL)) err = mc_apply_dpl(mc_apply_addr); @@ -2070,12 +2087,12 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD( fsl_mc, CONFIG_SYS_MAXARGS, 1, do_fsl_mc, "DPAA2 command to manage Management Complex (MC)", - "start mc [FW_addr] [DPC_addr] - Start Management Complex\n" - "fsl_mc apply DPL [DPL_addr] - Apply DPL file\n" - "fsl_mc lazyapply DPL [DPL_addr] - Apply DPL file on exit\n" - "fsl_mc apply spb [spb_addr] - Apply SPB Soft Parser Blob\n" - "fsl_mc start aiop [FW_addr] - Start AIOP\n" - "fsl_mc dump_log - Dump MC Log\n" + "fsl_mc start mc <fw_addr> <DPC_addr> - Start the Management Complex firmware\n" + "fsl_mc apply dpl <dpl_addr> [nowait] - Apply the DPL (Data Path Layout) file\n" + "fsl_mc lazyapply dpl <DPL_addr> [nowait] - Apply the DPL (Data Path Layout) file on exit\n" + "fsl_mc apply spb <spb_addr> - Apply the SPB Soft Parser Blob\n" + "fsl_mc start aiop <fw_addr> - Start AIOP\n" + "fsl_mc dump_log - Dump the MC Log\n" ); void mc_env_boot(void) diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index a4ba27904bc..206f1a381bb 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -8,6 +8,7 @@ #include <clk.h> #include <cpu_func.h> #include <dm.h> +#include <dm/device_compat.h> #include <errno.h> #include <fdt_support.h> #include <malloc.h> @@ -20,14 +21,21 @@ #include <linux/bug.h> #include <linux/delay.h> #include <linux/build_bug.h> +#include <linux/bitfield.h> +#include <power/regulator.h> +#include "fsl_enetc.h" #ifdef CONFIG_ARCH_IMX9 #include <asm/mach-imx/sys_proto.h> #include <cpu_func.h> +#include "fsl_enetc_xpcs_phy.c" +#else +static inline int xpcs_phy_usxgmii_pma_config(struct udevice *dev) +{ + return 0; +} #endif -#include "fsl_enetc.h" - #define ENETC_DRIVER_NAME "enetc_eth" /* @@ -454,19 +462,23 @@ static void enetc_setup_mac_iface(struct udevice *dev, /* set up serdes for SXGMII */ static int enetc_init_sxgmii(struct udevice *dev) { - struct enetc_priv *priv = dev_get_priv(dev); - if (!enetc_has_imdio(dev)) return 0; - /* Dev ability - SXGMII */ - enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL, - ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII); + if (enetc_is_imx95(dev)) { + xpcs_phy_usxgmii_pma_config(dev); + } else { + struct enetc_priv *priv = dev_get_priv(dev); + + /* Dev ability - SXGMII */ + enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL, + ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII); - /* Restart PCS AN */ - enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL, - ENETC_PCS_CR, - ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN); + /* Restart PCS AN */ + enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL, + ENETC_PCS_CR, + ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN); + } return 0; } @@ -523,6 +535,10 @@ static int enetc_config_phy(struct udevice *dev) return -ENODEV; supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full; + + if (enetc_is_imx95(dev)) + supported |= PHY_10G_FEATURES; + priv->phy->supported &= supported; priv->phy->advertising &= supported; @@ -537,12 +553,31 @@ static int enetc_probe(struct udevice *dev) { struct enetc_priv *priv = dev_get_priv(dev); int res; + struct udevice *supply = NULL; if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_enabled(dev_ofnode(dev))) { enetc_dbg(dev, "interface disabled\n"); return -ENODEV; } + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + res = device_get_supply_regulator(dev, "serdes-supply", + &supply); + if (res && res != -ENOENT) { + printf("%s: device_get_supply_regulator failed: %d\n", + __func__, res); + return res; + } + + if (supply) { + res = regulator_set_enable_if_allowed(supply, true); + if (res) { + printf("%s: Error enabling phy supply\n", dev->name); + return res; + } + } + } + priv->enetc_txbd = memalign(ENETC_BD_ALIGN, sizeof(struct enetc_tx_bd) * ENETC_BD_CNT); priv->enetc_rxbd = memalign(ENETC_BD_ALIGN, diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h index 804df853bf5..6d868e82f8c 100644 --- a/drivers/net/fsl_enetc.h +++ b/drivers/net/fsl_enetc.h @@ -205,6 +205,7 @@ struct enetc_data { /* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */ #define ENETC_PCS_PHY_ADDR 0 +#define ENETC_NON_PCS_PHY_ADDR 16 /* PCS registers */ #define ENETC_PCS_CR 0x00 diff --git a/drivers/net/fsl_enetc_xpcs_phy.c b/drivers/net/fsl_enetc_xpcs_phy.c new file mode 100644 index 00000000000..4039690223d --- /dev/null +++ b/drivers/net/fsl_enetc_xpcs_phy.c @@ -0,0 +1,970 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2024 NXP + */ + +#define XPCS_PHY_GLOBAL 0x0 +#define XPCS_PHY_MPLLA 0x1 +#define XPCS_PHY_MPLLB 0x2 +#define XPCS_PHY_LANE 0x3 +#define XPCS_PHY_MAC_ADAPTER 0x1f + +#define XPCS_PHY_REG(x) (((x) & 0x1fffe) >> 1) + +/* MAC ADAPTER */ +#define MAC_ADAPTER_LOCK_PHY 0x200 +#define MAC_ADAPTER_LOCK_MPLLA 0x204 +#define MAC_ADAPTER_LOCK_MPLLB 0x208 +#define MAC_ADAPTER_LOCK_ROM 0x20c +#define MAC_ADAPTER_LOCK_RAM 0x210 +#define MAC_ADAPTER_LOCK_EVENT 0x214 + +#define MAC_ADAPTER_LOCK_LOCK BIT(7) + +/* PMA */ +#define PMA_RX_LSTS 0x10040 +#define PMA_RX_LSTS_RX_VALID_0 BIT(12) +#define PMA_MP_12G_16G_25G_TX_GENCTRL0 0x10060 +#define PMA_TX_GENCTRL0_TX_RST_0 BIT(8) +#define PMA_TX_GENCTRL0_TX_DT_EN_0 BIT(12) +#define PMA_MP_12G_16G_25G_TX_GENCTRL1 0x10062 +#define PMA_TX_GENCTRL1_VBOOST_EN_0 BIT(4) +#define PMA_TX_GENCTRL1_VBOOST_LVL_MASK GENMASK(10, 8) +#define PMA_TX_GENCTRL1_VBOOST_LVL(x) (((x) << 8) & GENMASK(10, 8)) +#define PMA_TX_GENCTRL1_TX_CLK_RDY_0 BIT(12) +#define PMA_MP_12G_16G_TX_GENCTRL2 0x10064 +#define PMA_TX_GENCTRL2_TX_REQ_0 BIT(0) +#define PMA_TX_GENCTRL2_TX0_WIDTH_MASK GENMASK(9, 8) +#define PMA_TX_GENCTRL2_TX0_WIDTH(x) (((x) << 8) & GENMASK(9, 8)) +#define PMA_MP_12G_16G_25G_TX_BOOST_CTRL 0x10066 +#define PMA_TX_BOOST_CTRL_TX0_IBOOST_MASK GENMASK(3, 0) +#define PMA_TX_BOOST_CTRL_TX0_IBOOST(x) ((x) & GENMASK(3, 0)) +#define PMA_MP_12G_16G_25G_TX_RATE_CTRL 0x10068 +#define PMA_TX_RATE_CTRL_TX0_RATE_MASK GENMASK(2, 0) +#define PMA_TX_RATE_CTRL_TX0_RATE(x) ((x) & GENMASK(2, 0)) +#define PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL 0x1006A +#define PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK GENMASK(1, 0) +#define PMA_POWER_STATE_CTRL_TX0_PSTATE(x) ((x) & GENMASK(1, 0)) +#define PMA_POWER_STATE_CTRL_TX_DISABLE_0 BIT(8) +#define PMA_MP_12G_16G_25G_TX_EQ_CTRL0 0x1006C +#define PMA_TX_EQ_CTRL0_TX_EQ_PRE_MASK GENMASK(5, 0) +#define PMA_TX_EQ_CTRL0_TX_EQ_PRE(x) ((x) & GENMASK(5, 0)) +#define PMA_TX_EQ_CTRL0_TX_EQ_MAIN_MASK GENMASK(13, 8) +#define PMA_TX_EQ_CTRL0_TX_EQ_MAIN(x) (((x) << 8) & GENMASK(13, 8)) +#define PMA_MP_12G_16G_25G_TX_EQ_CTRL1 0x1006E +#define PMA_TX_EQ_CTRL1_TX_EQ_POST_MASK GENMASK(5, 0) +#define PMA_TX_EQ_CTRL1_TX_EQ_POST(x) ((x) & GENMASK(5, 0)) +#define PMA_MP_16G_25G_TX_MISC_CTRL0 0x1007C +#define PMA_TX_MISC_CTRL0_TX0_MISC_MASK GENMASK(7, 0) +#define PMA_TX_MISC_CTRL0_TX0_MISC(x) ((x) & GENMASK(7, 0)) +#define PMA_MP_12G_16G_25G_RX_GENCTRL0 0x100A0 +#define PMA_RX_GENCTRL0_RX_DT_EN_0 BIT(8) +#define PMA_MP_12G_16G_25G_RX_GENCTRL1 0x100A2 +#define PMA_RX_GENCTRL1_RX_RST_0 BIT(4) +#define PMA_RX_GENCTRL1_RX_TERM_ACDC_0 BIT(8) +#define PMA_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0 BIT(12) +#define PMA_MP_12G_16G_RX_GENCTRL2 0x100A4 +#define PMA_RX_GENCTRL2_RX_REQ_0 BIT(0) +#define PMA_RX_GENCTRL2_RX0_WIDTH_MASK GENMASK(9, 8) +#define PMA_RX_GENCTRL2_RX0_WIDTH(x) (((x) << 8) & GENMASK(9, 8)) +#define PMA_MP_12G_16G_RX_GENCTRL3 0x100A6 +#define PMA_RX_GENCTRL3_LOS_TRSHLD_0_MASK GENMASK(2, 0) +#define PMA_RX_GENCTRL3_LOS_TRSHLD_0(x) ((x) & GENMASK(2, 0)) +#define PMA_RX_GENCTRL3_LOS_LFPS_EN_0 BIT(12) +#define PMA_MP_12G_16G_25G_RX_RATE_CTRL 0x100A8 +#define PMA_RX_RATE_CTRL_RX0_RATE_MASK GENMASK(1, 0) +#define PMA_RX_RATE_CTRL_RX0_RATE(x) ((x) & GENMASK(1, 0)) +#define PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL 0x100AA +#define PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK GENMASK(1, 0) +#define PMA_RX_POWER_STATE_CTRL_RX0_PSTATE(x) ((x) & GENMASK(1, 0)) +#define PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0 BIT(8) +#define PMA_MP_12G_16G_25G_RX_CDR_CTRL 0x100AC +#define PMA_RX_CDR_CTRL_CDR_SSC_EN_0 BIT(4) +#define PMA_MP_12G_16G_25G_RX_ATTN_CTRL 0x100AE +#define PMA_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_MASK GENMASK(2, 0) +#define PMA_RX_ATTN_CTRL_RX0_EQ_ATT_LVL(x) ((x) & GENMASK(2, 0)) +#define PMA_MP_16G_25G_RX_EQ_CTRL0 0x100B0 +#define PMA_RX_EQ_CTRL0_CTLE_BOOST_0_MASK GENMASK(4, 0) +#define PMA_RX_EQ_CTRL0_CTLE_BOOST_0(x) ((x) & GENMASK(4, 0)) +#define PMA_RX_EQ_CTRL0_CTLE_POLE_0_MASK GENMASK(6, 5) +#define PMA_RX_EQ_CTRL0_CTLE_POLE_0(x) (((x) << 5) & GENMASK(6, 5)) +#define PMA_RX_EQ_CTRL0_VGA2_GAIN_0_MASK GENMASK(10, 8) +#define PMA_RX_EQ_CTRL0_VGA2_GAIN_0(x) (((x) << 8) & GENMASK(10, 8)) +#define PMA_RX_EQ_CTRL0_VGA1_GAIN_0_MASK GENMASK(14, 12) +#define PMA_RX_EQ_CTRL0_VGA1_GAIN_0(x) (((x) << 12) & GENMASK(14, 12)) +#define PMA_MP_12G_16G_25G_RX_EQ_CTRL4 0x100B8 +#define PMA_RX_EQ_CTRL4_CONT_ADAPT_0 BIT(0) +#define PMA_RX_EQ_CTRL4_RX_AD_REQ BIT(12) +#define PMA_MP_16G_25G_RX_EQ_CTRL5 0x100BA +#define PMA_RX_EQ_CTRL5_RX_ADPT_SEL_0 BIT(0) +#define PMA_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK GENMASK(5, 4) +#define PMA_RX_EQ_CTRL5_RX0_ADPT_MODE(x) (((x) << 4) & GENMASK(5, 4)) +#define PMA_MP_12G_16G_25G_DFE_TAP_CTRL0 0x100BC +#define PMA_DFE_TAP_CTRL0_DFE_TAP1_0_MASK GENMASK(7, 0) +#define PMA_DFE_TAP_CTRL0_DFE_TAP1_0(x) ((x) & GENMASK(7, 0)) +#define PMA_MP_16G_RX_CDR_CTRL1 0x100C8 +#define PMA_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0 BIT(0) +#define PMA_RX_CDR_CTRL1_VCO_STEP_CTRL_0 BIT(4) +#define PMA_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK GENMASK(9, 8) +#define PMA_RX_CDR_CTRL1_VCO_FRQBAND_0(x) (((x) << 8) & GENMASK(9, 8)) +#define PMA_MP_16G_25G_RX_PPM_CTRL0 0x100CA +#define PMA_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_MASK GENMASK(4, 0) +#define PMA_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(x) ((x) & GENMASK(4, 0)) +#define PMA_MP_16G_25G_RX_GENCTRL4 0x100D0 +#define PMA_RX_GENCTRL4_RX_DFE_BYP_0 BIT(8) +#define PMA_MP_16G_25G_RX_MISC_CTRL0 0x100D2 +#define PMA_RX_MISC_CTRL0_RX0_MISC_MASK GENMASK(7, 0) +#define PMA_RX_MISC_CTRL0_RX0_MISC(x) ((x) & GENMASK(7, 0)) +#define PMA_MP_16G_25G_RX_IQ_CTRL0 0x100D6 +#define PMA_RX_IQ_CTRL0_RX0_MARGIN_IQ_MASK GENMASK(6, 0) +#define PMA_RX_IQ_CTRL0_RX0_MARGIN_IQ(x) ((x) & GENMASK(6, 0)) +#define PMA_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK GENMASK(11, 8) +#define PMA_RX_IQ_CTRL0_RX0_DELTA_IQ(x) (((x) << 8) & GENMASK(11, 8)) +#define PMA_MP_12G_16G_25G_MPLL_CMN_CTRL 0x100E0 +#define PMA_MPLL_CMN_CTRL_MPLL_EN_0 BIT(0) +#define PMA_MPLL_CMN_CTRL_MPLLB_SEL_0 BIT(4) +#define PMA_MP_12G_16G_MPLLA_CTRL0 0x100E2 +#define PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK GENMASK(7, 0) +#define PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER(x) ((x) & GENMASK(7, 0)) +#define PMA_MP_16G_MPLLA_CTRL1 0x100E4 +#define PMA_MPLLA_CTRL1_MPLLA_SSC_EN BIT(0) +#define PMA_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL BIT(4) +#define PMA_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK GENMASK(15, 5) +#define PMA_MPLLA_CTRL1_MPLLA_FRACN_CTRL(x) (((x) << 5) & GENMASK(15, 5)) +#define PMA_MP_12G_16G_MPLLA_CTRL2 0x100E6 +#define PMA_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK GENMASK(6, 0) +#define PMA_MPLLA_CTRL2_MPLLA_DIV_MULT(x) ((x) & GENMASK(6, 0)) +#define PMA_MPLLA_CTRL2_MPLLA_DIV_CLK_EN BIT(7) +#define PMA_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN BIT(8) +#define PMA_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN BIT(9) +#define PMA_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN BIT(10) +#define PMA_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK GENMASK(12, 11) +#define PMA_MPLLA_CTRL2_MPLLA_TX_CLK_DIV(x) (((x) << 11) & GENMASK(12, 11)) +#define PMA_MP_16G_MPLLA_CTRL3 0x100EE +#define PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK GENMASK(15, 0) +#define PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH(x) ((x) & GENMASK(15, 0)) +#define PMA_MP_16G_MPLLA_CTRL4 0x100F2 +#define PMA_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_MASK GENMASK(11, 0) +#define PMA_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT(x) ((x) & GENMASK(11, 0)) +#define PMA_MP_16G_MPLLA_CTRL5 0x100F4 +#define PMA_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK GENMASK(7, 0) +#define PMA_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK(x) ((x) & GENMASK(7, 0)) +#define PMA_MPLLA_CTRL5_MPLLA_SSC_SPD_EN BIT(8) +#define PMA_MP_12G_16G_25G_MISC_CTRL0 0x10120 +#define PMA_MISC_CTRL0_RX_VREF_CTRL_MASK GENMASK(12, 8) +#define PMA_MISC_CTRL0_RX_VREF_CTRL(x) (((x) << 8) & GENMASK(12, 8)) +#define PMA_MP_12G_16G_25G_REF_CLK_CTRL 0x10122 +#define PMA_REF_CLK_CTRL_REF_CLK_DIV2 BIT(2) +#define PMA_REF_CLK_CTRL_REF_RANGE_MASK GENMASK(5, 3) +#define PMA_REF_CLK_CTRL_REF_RANGE(x) (((x) << 3) & GENMASK(5, 3)) +#define PMA_REF_CLK_CTRL_REF_MPLLA_DIV2 BIT(6) +#define PMA_MP_12G_16G_25G_VCO_CAL_LD0 0x10124 +#define PMA_VCO_CAL_LD0_VCO_LD_VAL_0_MASK GENMASK(12, 0) +#define PMA_VCO_CAL_LD0_VCO_LD_VAL_0(x) ((x) & GENMASK(12, 0)) +#define PMA_MP_16G_25G_VCO_CAL_REF0 0x1012C +#define PMA_VCO_CAL_REF0_VCO_REF_LD_0_MASK GENMASK(6, 0) +#define PMA_VCO_CAL_REF0_VCO_REF_LD_0(x) ((x) & GENMASK(6, 0)) +#define PMA_MP_12G_16G_25G_MISC_STS 0x10130 +#define PMA_MISC_STS_RX_ADPT_ACK BIT(12) +#define PMA_MP_12G_16G_25G_SRAM 0x10136 +#define PMA_SRAM_INIT_DN BIT(0) +#define PMA_SRAM_EXT_LD_DN BIT(1) +#define PMA_MP_16G_25G_MISC_CTRL2 0x10138 +#define PMA_MISC_CTRL2_SUP_MISC_MASK GENMASK(7, 0) +#define PMA_MISC_CTRL2_SUP_MISC(x) ((x) & GENMASK(7, 0)) + +/* PCS */ +#define PCS_CTRL1 0x0 +#define PCS_CTRL1_RESET BIT(15) +#define PCS_CTRL2 0xE +#define PCS_CTRL2_PCS_TYPE_SEL_MASK GENMASK(3, 0) +#define PCS_CTRL2_PCS_TYPE_SEL(x) ((x) & GENMASK(3, 0)) +#define PCS_DIG_CTRL1 0x10000 +#define PCS_DIG_CTRL1_USXG_EN BIT(9) +#define PCS_DIG_CTRL1_USRA_RST BIT(10) +#define PCS_DIG_CTRL1_VR_RST BIT(15) +#define PCS_DEBUG_CTRL 0x1000A +#define PCS_DEBUG_CTRL_SUPRESS_LOS_DET BIT(4) +#define PCS_DEBUG_CTRL_RX_DT_EN_CTL BIT(6) +#define PCS_DEBUG_CTRL_TX_PMBL_CTL BIT(8) +#define PCS_KR_CTRL1 0x1000E +#define PCS_KR_CTRL1_USXG_MODE_MASK GENMASK(12, 10) +#define PCS_KR_CTRL1_USXG_MODE(x) (((x) << 10) & GENMASK(12, 10)) + +/* VS MII MMD */ +#define MII_CTRL 0x0 +#define MII_CTRL_SS5 BIT(5) +#define MII_CTRL_SS6 BIT(6) +#define MII_CTRL_AN_ENABLE BIT(12) +#define MII_CTRL_SS13 BIT(13) +#define MII_DIG_CTRL1 0x10000 +#define MII_DIG_CTRL1_CL37_TMR_OVR_RIDE BIT(3) +#define MII_AN_CTRL 0x10002 +#define MII_AN_CTRL_MII_AN_INTR_EN BIT(0) +#define MII_AN_CTRL_TX_CONFIG BIT(3) +#define MII_AN_INTR_STS 0x10004 +#define MII_AN_INTR_STS_CL37_ANCMPLT_INTR BIT(0) +#define MII_LINK_TIMER_CTRL 0x10014 +#define MII_LINK_TIMER_CTRL_CL37_LINK_TIME_MASK GENMASK(15, 0) +#define MII_LINK_TIMER_CTRL_CL37_LINK_TIME(x) ((x) & GENMASK(15, 0)) + +/* E16 MEM MAP */ +#define IDCODE_LO 0x0 +#define IDCODE_HI 0x4 +#define GLOBAL_CTRL_EX_0 0x114 +#define GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS BIT(0) +#define L0_RX_VCO_OVRD_OUT_0 0x20c +#define L0_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE_MASK GENMASK(12, 3) +#define L0_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE(x) (((x) << 3) & GENMASK(12, 3)) +#define L0_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN BIT(15) +#define L0_RX_VCO_OVRD_OUT_2 0x214 +#define L0_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK BIT(0) + +static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg); +static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val); + +int xpcs_read(struct udevice *dev, int devaddr, u32 reg) +{ + struct enetc_priv *priv = dev_get_priv(dev); + + return enetc_mdio_read(&priv->imdio, ENETC_PCS_PHY_ADDR, devaddr, reg); +} + +int xpcs_write(struct udevice *dev, int devaddr, u32 reg, u16 val) +{ + struct enetc_priv *priv = dev_get_priv(dev); + + return enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, devaddr, reg, val); +} + +int xpcs_phy_read(struct udevice *dev, int devaddr, u32 reg) +{ + struct enetc_priv *priv = dev_get_priv(dev); + + return enetc_mdio_read(&priv->imdio, ENETC_NON_PCS_PHY_ADDR, devaddr, reg); +} + +int xpcs_phy_write(struct udevice *dev, int devaddr, u32 reg, u16 val) +{ + struct enetc_priv *priv = dev_get_priv(dev); + + return enetc_mdio_write(&priv->imdio, ENETC_NON_PCS_PHY_ADDR, devaddr, reg, val); +} + +int xpcs_phy_read_pma(struct udevice *dev, u32 reg) +{ + return xpcs_read(dev, MDIO_MMD_PMAPMD, XPCS_PHY_REG(reg)); +} + +int xpcs_phy_write_pma(struct udevice *dev, int reg, u16 val) +{ + return xpcs_write(dev, MDIO_MMD_PMAPMD, XPCS_PHY_REG(reg), val); +} + +int xpcs_phy_usxgmii_init_seq_2(struct udevice *dev) +{ + ulong begin; + u16 val; + + /* Seq 2.1 Keep preamble data */ + val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL)); + val |= PCS_DEBUG_CTRL_TX_PMBL_CTL; + xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL), val); + + /* Seq 2.2 Power up MPLLA to P1 state */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL); + val = u16_replace_bits(val, 2, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL); + val |= PMA_MPLL_CMN_CTRL_MPLL_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val); + + /* Seq 2.3 Assert request of transmitand receive */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2); + val |= PMA_TX_GENCTRL2_TX_REQ_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + val |= PMA_RX_GENCTRL2_RX_REQ_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val); + + /* Seq 2.4 Poll for acknowledge */ + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (val & PMA_TX_GENCTRL2_TX_REQ_0); + + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (val & PMA_RX_GENCTRL2_RX_REQ_0); + + /* Seq 2.5 Turn transmit to P0 state */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL); + val = u16_replace_bits(val, 0, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0); + val &= ~PMA_TX_GENCTRL0_TX_RST_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL); + val &= ~PMA_POWER_STATE_CTRL_TX_DISABLE_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL); + val |= PMA_MPLL_CMN_CTRL_MPLL_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val); + + /* Seq 2.6 Turn receive to P0 state */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1); + val &= ~PMA_RX_GENCTRL1_RX_RST_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL); + val &= ~PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK; + val &= ~PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL); + val &= ~PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK; + val &= ~PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val); + + /* Seq 2.7 Enable transmitter output driver in the PHY */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0); + val |= PMA_TX_GENCTRL0_TX_DT_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val); + + /* Seq 2.8 Enable receiver data output from PHY */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0); + val |= PMA_RX_GENCTRL0_RX_DT_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val); + + /* Seq 2.9 Assert request of transmit and receive */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2); + val |= PMA_TX_GENCTRL2_TX_REQ_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + val |= PMA_RX_GENCTRL2_RX_REQ_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val); + + /* Seq 2.10 Poll for acknowledge */ + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + schedule(); + } while (val & PMA_TX_GENCTRL2_TX_REQ_0); + + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + schedule(); + } while (val & PMA_RX_GENCTRL2_RX_REQ_0); + + return 0; + +timeout: + return -ETIMEDOUT; +} + +void xpcs_phy_reg_lock(struct udevice *dev) +{ + u16 val; + ulong begin; + + if (xpcs_phy_read(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_PHY)) & MAC_ADAPTER_LOCK_LOCK) + return; + + xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_PHY), MAC_ADAPTER_LOCK_LOCK); + xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_MPLLA), MAC_ADAPTER_LOCK_LOCK); + xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_MPLLB), MAC_ADAPTER_LOCK_LOCK); + xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_ROM), MAC_ADAPTER_LOCK_LOCK); + xpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_RAM), MAC_ADAPTER_LOCK_LOCK); + + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_SRAM); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (!(val & PMA_SRAM_INIT_DN)); + + /* Work around */ + // xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_SRAM, PMA_SRAM_EXT_LD_DN); + xpcs_phy_write(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(GLOBAL_CTRL_EX_0), GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS); + + begin = get_timer(0); + do { + val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_CTRL1)); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (val & PCS_CTRL1_RESET); + + mdelay(1); + +timeout: + return; +} + +int xpcs_phy_usxgmii_pma_config(struct udevice *dev) +{ + ulong begin; + u16 val; + + xpcs_phy_reg_lock(dev); + + /* 1.6 Turn off C37 auto-negotiation */ + val = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL)); + val &= ~MII_CTRL_AN_ENABLE; + xpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL), val); + + /* 1.7 Assert tx_reset and rx_reset*/ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0); + val |= PMA_TX_GENCTRL0_TX_RST_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1); + val |= PMA_RX_GENCTRL1_RX_RST_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val); + + /* 1.8 Wait for more than 1us */ + udelay(5); + + /* 1.9 Deassert tx_reset and rx_reset*/ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0); + val &= ~PMA_TX_GENCTRL0_TX_RST_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1); + val &= ~PMA_RX_GENCTRL1_RX_RST_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val); + + /* 1.10 Power down MPLLA */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL); + val = u16_replace_bits(val, 3, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL); + val &= ~PMA_MPLL_CMN_CTRL_MPLL_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0); + val &= ~PMA_TX_GENCTRL0_TX_DT_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val); + + /* 1.11 Change RX0 power state to P2 */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0); + val &= ~PMA_RX_GENCTRL0_RX_DT_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val); + + /* TODO: check if it is needed */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL); + val = u16_replace_bits(val, 1, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL); + val = u16_replace_bits(val, 3, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val); + + /* 1.12 Assert request of transmit and receive */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2); + val |= PMA_TX_GENCTRL2_TX_REQ_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + val |= PMA_RX_GENCTRL2_RX_REQ_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val); + + /* 1.13 Poll for acknlowledge */ + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (val & PMA_TX_GENCTRL2_TX_REQ_0); + + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (val & PMA_RX_GENCTRL2_RX_REQ_0); + + /* 2 Config MPLL for 10G XGMII */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL); + val = u16_replace_bits(val, 6, PMA_REF_CLK_CTRL_REF_RANGE_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL); + val &= ~PMA_REF_CLK_CTRL_REF_CLK_DIV2; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL); + val |= PMA_REF_CLK_CTRL_REF_MPLLA_DIV2; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2); + val &= ~PMA_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2); + val |= PMA_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2); + val |= PMA_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2); + val &= ~PMA_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2); + val |= PMA_MPLLA_CTRL2_MPLLA_DIV_CLK_EN; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2); + val = u16_replace_bits(val, 5, PMA_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL1); + val &= ~PMA_MPLLA_CTRL1_MPLLA_SSC_EN; + xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL1); + val &= ~PMA_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL; + xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL5); + val &= ~PMA_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK; + xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL5, val); + + xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL4, 0); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL5); + val &= ~PMA_MPLLA_CTRL5_MPLLA_SSC_SPD_EN; + xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL5, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL1); + val &= ~PMA_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK; + xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0); + val = u16_replace_bits(val, 33, PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1); + val = u16_replace_bits(val, 5, PMA_TX_GENCTRL1_VBOOST_LVL_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val); + + val = PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016); + xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL3, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MISC_CTRL0); + val = u16_replace_bits(val, 0x11, PMA_MISC_CTRL0_RX_VREF_CTRL_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MISC_CTRL0, val); + + val = PMA_MISC_CTRL2_SUP_MISC(1); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_MISC_CTRL2, val); + + val = PMA_VCO_CAL_REF0_VCO_REF_LD_0(0x29); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_VCO_CAL_REF0, val); + + val = PMA_VCO_CAL_LD0_VCO_LD_VAL_0(0x549); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_VCO_CAL_LD0, val); + + val = PMA_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(0x12); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_PPM_CTRL0, val); + + /* 3 Configure LANE0 for 10G XGMII */ + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_TX_MISC_CTRL0, 0x0); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_RATE_CTRL, 0x0); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL); + val &= ~PMA_MPLL_CMN_CTRL_MPLLB_SEL_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2); + val = u16_replace_bits(val, 3, PMA_TX_GENCTRL2_TX0_WIDTH_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1); + val |= PMA_TX_GENCTRL1_VBOOST_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val); + + val = PMA_TX_BOOST_CTRL_TX0_IBOOST(0xf); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_BOOST_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0); + val = u16_replace_bits(val, 0, PMA_TX_EQ_CTRL0_TX_EQ_PRE_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0, val); + + val = PMA_TX_EQ_CTRL1_TX_EQ_POST(0x20); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0); + val = u16_replace_bits(val, 0x20, PMA_TX_EQ_CTRL0_TX_EQ_MAIN_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0, val); + + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_RATE_CTRL, 0x0); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0); + val = u16_replace_bits(val, 0x2, PMA_RX_EQ_CTRL0_CTLE_POLE_0_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0); + val = u16_replace_bits(val, 0x10, PMA_RX_EQ_CTRL0_CTLE_BOOST_0_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3); + val = u16_replace_bits(val, 0x7, PMA_RX_GENCTRL3_LOS_TRSHLD_0_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1); + val |= PMA_RX_CDR_CTRL1_VCO_STEP_CTRL_0; + xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1); + val |= PMA_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val); + + val = PMA_RX_MISC_CTRL0_RX0_MISC(0x12); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_MISC_CTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + val = u16_replace_bits(val, 0x3, PMA_RX_GENCTRL2_RX0_WIDTH_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1); + val |= PMA_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val); + + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_CDR_CTRL, 0x0); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3); + val &= ~PMA_RX_GENCTRL3_LOS_LFPS_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4); + val &= ~PMA_RX_GENCTRL4_RX_DFE_BYP_0; + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4, val); + + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_ATTN_CTRL, 0x0); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0); + val = u16_replace_bits(val, 0x5, PMA_RX_EQ_CTRL0_VGA1_GAIN_0_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0); + val = u16_replace_bits(val, 0x5, PMA_RX_EQ_CTRL0_VGA2_GAIN_0_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val); + + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_DFE_TAP_CTRL0, 0x0); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1); + val = u16_replace_bits(val, 0x1, PMA_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1); + val |= PMA_RX_GENCTRL1_RX_TERM_ACDC_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0); + val = u16_replace_bits(val, 0x0, PMA_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5); + val &= ~PMA_RX_EQ_CTRL5_RX_ADPT_SEL_0; + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5); + val = u16_replace_bits(val, 0x3, PMA_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5, val); + + /* 4 Configure XPCS for 10G XGMII */ + xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_CTRL2), 0x0); + + val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1)); + val |= PCS_DIG_CTRL1_USXG_EN; + xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1), val); + + val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_KR_CTRL1)); + val = u16_replace_bits(val, 0x0, PCS_KR_CTRL1_USXG_MODE_MASK); + xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_KR_CTRL1), val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0); + val = u16_replace_bits(val, 0x21, PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0, val); + + val = PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016); + xpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL3, val); + + val = PMA_VCO_CAL_LD0_VCO_LD_VAL_0(0x549); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_VCO_CAL_LD0, val); + + val = PMA_VCO_CAL_REF0_VCO_REF_LD_0(0x29); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_VCO_CAL_REF0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4); + val |= PMA_RX_EQ_CTRL4_CONT_ADAPT_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4, val); + + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_RATE_CTRL, 0x0); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_RATE_CTRL, 0x0); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2); + val = u16_replace_bits(val, 0x3, PMA_TX_GENCTRL2_TX0_WIDTH_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + val = u16_replace_bits(val, 0x3, PMA_RX_GENCTRL2_RX0_WIDTH_MASK); + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2); + val |= PMA_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2); + val |= PMA_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2); + val &= ~PMA_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1); + val |= PMA_TX_GENCTRL1_VBOOST_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0); + val = u16_replace_bits(val, 0x10, PMA_RX_EQ_CTRL0_CTLE_BOOST_0_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1); + val |= PMA_RX_CDR_CTRL1_VCO_STEP_CTRL_0; + xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1); + val |= PMA_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val); + + val = PMA_RX_MISC_CTRL0_RX0_MISC(0x12); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_MISC_CTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4); + val &= ~PMA_RX_GENCTRL4_RX_DFE_BYP_0; + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1); + val = u16_replace_bits(val, 0x1, PMA_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0); + val = u16_replace_bits(val, 0x0, PMA_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5); + val = u16_replace_bits(val, 0x3, PMA_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK); + xpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1); + val &= ~PMA_TX_GENCTRL1_TX_CLK_RDY_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val); + + /* 5 Assert soft reset */ + val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1)); + val |= PCS_DIG_CTRL1_VR_RST; + xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1), val); + + /* 6 Poll for SRAM initialization done */ + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_SRAM); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (!(val & PMA_SRAM_INIT_DN)); + + /* 7 Assert SRAM external loading done */ + /* Workaround */ + // xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_SRAM, PMA_SRAM_EXT_LD_DN); + xpcs_phy_write(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(GLOBAL_CTRL_EX_0), GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS); + + /* 8 Poll for vendor-specific soft reset */ + begin = get_timer(0); + do { + val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1)); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (val & PCS_DIG_CTRL1_VR_RST); + + /* 9 Turn receive to P0 state */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1); + val &= ~PMA_RX_GENCTRL1_RX_RST_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL); + val &= ~PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val); + + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL); + val &= ~PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val); + + /* 10 Enable receiver data output from PHY */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0); + val |= PMA_RX_GENCTRL0_RX_DT_EN_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val); + + /* 11 Assert request of receive */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + val |= PMA_RX_GENCTRL2_RX_REQ_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val); + + /* 11.1 Poll for acknowledge */ + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (val & PMA_RX_GENCTRL2_RX_REQ_0); + + /* 12 Assert TX0 clock is active and stable */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1); + val |= PMA_TX_GENCTRL1_TX_CLK_RDY_0; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val); + + /* + * 13.1 Configure XPCS to consider Loss-of-Signal indicated by the + * PHY while evaluating the receive link status + */ + val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL)); + val |= PCS_DEBUG_CTRL_SUPRESS_LOS_DET; + xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL), val); + /* + * 13.2 Configure XPCS to deassert "receiver data enable" on + * detecting of Loss-of-Signal + */ + val = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL)); + val |= PCS_DEBUG_CTRL_RX_DT_EN_CTL; + xpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL), val); + + /* 14 Poll for DPLL lock status for Lane 0 */ + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_RX_LSTS); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (!(val & PMA_RX_LSTS_RX_VALID_0)); + + /* 15 Assert request of receive adaptation */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4); + val |= PMA_RX_EQ_CTRL4_RX_AD_REQ; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4, val); + + /* 16 Poll for acknowledge */ + begin = get_timer(0); + do { + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MISC_STS); + if (get_timer(begin) > 500) { + dev_err(dev, "Polling timeout, line: %d\n", __LINE__); + goto timeout; + } + mdelay(10); + } while (!(val & PMA_MISC_STS_RX_ADPT_ACK)); + + /* 17 Deassert request of receive adaptation */ + val = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4); + val &= ~PMA_RX_EQ_CTRL4_RX_AD_REQ; + xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4, val); + + /* 18 Set the value of Config_Reg to 0 for Clause 37 autonegotiation. */ + val = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_AN_CTRL)); + val &= ~MII_AN_CTRL_TX_CONFIG; + xpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_AN_CTRL), val); + + /* 19 Select XGMII speed */ + val = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL)); + val &= ~MII_CTRL_SS5; + val |= MII_CTRL_SS6 | MII_CTRL_SS13; + xpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL), val); + + val = xpcs_phy_usxgmii_init_seq_2(dev); + if (val) + return val; + + return 0; + +timeout: + return -ETIMEDOUT; +} + +u32 xpcs_phy_get_id(struct udevice *dev) +{ + int ret; + u32 id; + + /* First, search C73 PCS using PCS MMD */ + ret = xpcs_phy_read(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(IDCODE_HI)); + if (ret < 0) + return 0xffffffff; + + id = ret << 16; + + ret = xpcs_phy_read(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(IDCODE_LO)); + if (ret < 0) + return 0xffffffff; + + /* If Device IDs are not all zeros or all ones, + * we found C73 AN-type device + */ + if ((id | ret) && (id | ret) != 0xffffffff) + return id | ret; + + return 0xffffffff; +} diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 10b87dfb8ab..83da3e1cc77 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -400,7 +400,7 @@ int aquantia_config(struct phy_device *phydev) int interface = phydev->interface; u32 val, id, rstatus, fault; u32 reg_val1 = 0; - int num_retries = 5; + int num_retries = 200; int usx_an = 0; /* diff --git a/drivers/net/qe/dm_qe_uec_phy.c b/drivers/net/qe/dm_qe_uec_phy.c index 8c0168be859..107c7686b3b 100644 --- a/drivers/net/qe/dm_qe_uec_phy.c +++ b/drivers/net/qe/dm_qe_uec_phy.c @@ -152,7 +152,7 @@ static const struct udevice_id qe_uec_mdio_ids[] = { { } }; -U_BOOT_DRIVER(mvmdio) = { +U_BOOT_DRIVER(qe_uec_mdio) = { .name = "qe_uec_mdio", .id = UCLASS_MDIO, .of_match = qe_uec_mdio_ids, diff --git a/drivers/net/sni_netsec.c b/drivers/net/sni_netsec.c index 71afe78fd28..b74a5c27cae 100644 --- a/drivers/net/sni_netsec.c +++ b/drivers/net/sni_netsec.c @@ -1138,7 +1138,7 @@ static const struct udevice_id netsec_ids[] = { {} }; -U_BOOT_DRIVER(ave) = { +U_BOOT_DRIVER(synquacer_netsec) = { .name = "synquacer_netsec", .id = UCLASS_ETH, .of_match = netsec_ids, diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index e9cc5db52d2..1ea81fe1830 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -28,6 +28,10 @@ #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */ #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */ +/* Reset and Address Filter (RAF) Register bit definitions */ +#define XAE_RAF_MCSTREJ_MASK 0x00000002 /* Reject rx multicast dst addr */ +#define XAE_RAF_BCSTREJ_MASK 0x00000004 /* Reject rx broadcast dst addr */ + /* Interrupt Status/Enable/Mask Registers bit definitions */ #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */ #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */ @@ -153,7 +157,8 @@ static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN))); static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN))); struct axi_regs { - u32 reserved[3]; + u32 raf; /* 0x0: Reset and Address Filter */ + u32 reserved[2]; u32 is; /* 0xC: Interrupt status */ u32 reserved2; u32 ie; /* 0x14: Interrupt enable */ @@ -528,6 +533,19 @@ static int axi_ethernet_init(struct axidma_priv *priv) /* Set default MDIO divisor */ writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc); + /* + * Reject broadcast and multicast frames at MAC level to reduce + * unnecessary traffic processing. Multicast rejection is only + * enabled when IPv6 is not configured because IPv6 Neighbor + * Discovery and DHCPv6 rely on multicast. + */ + if (!IS_ENABLED(CONFIG_IPV6)) + writel(readl(®s->raf) | XAE_RAF_MCSTREJ_MASK | + XAE_RAF_BCSTREJ_MASK, ®s->raf); + else + writel(readl(®s->raf) | XAE_RAF_BCSTREJ_MASK, + ®s->raf); + debug("axiemac: InitHw done\n"); return 0; } diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index a50d5aee03f..f570ae9ee73 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -69,10 +69,13 @@ #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ +#define ZYNQ_GEM_DBUS_WIDTH_MASK (3 << 21) /* bits 22:21 */ #ifdef CONFIG_ARM64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ +# define ZYNQ_GEM_DBUS_WIDTH_128 (2 << 21) /* 128 bit bus */ #else # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ +# define ZYNQ_GEM_DBUS_WIDTH_128 (0 << 21) /* 32 bit bus */ #endif #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ @@ -134,6 +137,7 @@ #define ZYNQ_GEM_FREQUENCY_10 2500000UL #define ZYNQ_GEM_FREQUENCY_100 25000000UL #define ZYNQ_GEM_FREQUENCY_1000 125000000UL +#define ZYNQ_GEM_FREQUENCY_10000 150000000UL #define RXCLK_EN BIT(0) @@ -470,28 +474,6 @@ static int zynq_gem_init(struct udevice *dev) for (i = 0; i < STAT_SIZE; i++) readl(®s->stat[i]); - /* Setup RxBD space */ - memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); - - for (i = 0; i < RX_BUF; i++) { - priv->rx_bd[i].status = 0xF0000000; - priv->rx_bd[i].addr = - (lower_32_bits((ulong)(priv->rxbuffers) - + (i * PKTSIZE_ALIGN))); -#if defined(CONFIG_PHYS_64BIT) - priv->rx_bd[i].addr_hi = - (upper_32_bits((ulong)(priv->rxbuffers) - + (i * PKTSIZE_ALIGN))); -#endif - } - /* WRAP bit to last BD */ - priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; - /* Write RxBDs to IP */ - writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase); -#if defined(CONFIG_PHYS_64BIT) - writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase); -#endif - /* Setup for DMA Configuration register */ writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); @@ -520,6 +502,35 @@ static int zynq_gem_init(struct udevice *dev) priv->init++; } + /* + * Reinitialize RX BDs on every init. The 10GBE USX block asserts + * RX_SYNC_RESET during setup which resets the GEM RX DMA pointer + * back to rxqbase, so BDs and rxqbase must be refreshed each time + * to keep the hardware and driver ring indices in sync. + */ + priv->rxbd_current = 0; + priv->rx_first_buf = 0; + memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); + for (i = 0; i < RX_BUF; i++) { + priv->rx_bd[i].status = 0xF0000000; + priv->rx_bd[i].addr = + (lower_32_bits((ulong)(priv->rxbuffers) + + (i * PKTSIZE_ALIGN))); +#if defined(CONFIG_PHYS_64BIT) + priv->rx_bd[i].addr_hi = + (upper_32_bits((ulong)(priv->rxbuffers) + + (i * PKTSIZE_ALIGN))); +#endif + } + /* WRAP bit to last BD */ + priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; + + /* Write RxBDs to IP */ + writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase); +#if defined(CONFIG_PHYS_64BIT) + writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase); +#endif + ret = phy_startup(priv->phydev); if (ret) return ret; @@ -532,6 +543,8 @@ static int zynq_gem_init(struct udevice *dev) nwconfig = ZYNQ_GEM_NWCFG_INIT; if (device_is_compatible(dev, "amd,versal2-10gbe")) { + nwconfig &= ~ZYNQ_GEM_DBUS_WIDTH_MASK; + nwconfig |= ZYNQ_GEM_DBUS_WIDTH_128; if (priv->interface == PHY_INTERFACE_MODE_10GBASER) { ctrl = readl(®s->nwcfg); ctrl |= PCSSEL; @@ -602,6 +615,9 @@ static int zynq_gem_init(struct udevice *dev) } switch (priv->phydev->speed) { + case SPEED_10000: + clk_rate = ZYNQ_GEM_FREQUENCY_10000; + break; case SPEED_1000: nwconfig |= ZYNQ_GEM_NWCFG_SPEED1000; clk_rate = ZYNQ_GEM_FREQUENCY_1000; @@ -615,6 +631,7 @@ static int zynq_gem_init(struct udevice *dev) break; } nwcfg = readl(®s->nwcfg); + nwcfg &= ~(ZYNQ_GEM_NWCFG_SPEED100 | ZYNQ_GEM_NWCFG_SPEED1000); nwcfg |= nwconfig; if (nwcfg) writel(nwcfg, ®s->nwcfg); diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 8fc57895a78..39df0e776df 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -456,6 +456,17 @@ config PCIE_STARFIVE_JH7110 Say Y here if you want to enable PLDA XpressRich PCIe controller support on StarFive JH7110 SoC. +config PCIE_DW_AMD + bool "AMD Versal2 DW PCIe host controller" + depends on ARCH_VERSAL2 + depends on DM_GPIO + select PCIE_DW_COMMON + select SYS_PCI_64BIT + help + Say Y here to enable support for the AMD Versal Gen 2 PCIe + host controller. This is a DesignWare-based PCIe controller + used in AMD Versal Gen 2 SoCs. + config PCIE_DW_IMX bool "i.MX DW PCIe controller support" depends on ARCH_IMX8M || ARCH_IMX9 diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 98f3c226f63..e6d71fd172b 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -56,4 +56,5 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o +obj-$(CONFIG_PCIE_DW_AMD) += pcie_dw_amd.o obj-$(CONFIG_PCIE_DW_IMX) += pcie_dw_imx.o diff --git a/drivers/pci/pcie_dw_amd.c b/drivers/pci/pcie_dw_amd.c new file mode 100644 index 00000000000..81c6d8f2817 --- /dev/null +++ b/drivers/pci/pcie_dw_amd.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AMD Versal2 DesignWare PCIe host controller driver + * + * Copyright (C) 2025 - 2026, Advanced Micro Devices, Inc. + * Author: Pranav Sanwal <[email protected]> + */ + +#include <dm.h> +#include <log.h> +#include <pci.h> +#include <wait_bit.h> + +#include <asm/gpio.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/ofnode.h> +#include <linux/delay.h> + +#include "pcie_dw_common.h" + +/* + * SLCR (System Level Control Register) Interrupt Register Offsets + * These are relative to the SLCR base address from device tree + */ +#define AMD_DW_TLP_IR_STATUS_MISC 0x4c0 +#define AMD_DW_TLP_IR_DISABLE_MISC 0x4cc + +/* Interrupt bit definitions */ +#define AMD_DW_PCIE_INTR_CMPL_TIMEOUT 15 +#define AMD_DW_PCIE_INTR_PM_PME_RCVD 24 +#define AMD_DW_PCIE_INTR_PME_TO_ACK_RCVD 25 +#define AMD_DW_PCIE_INTR_MISC_CORRECTABLE 26 +#define AMD_DW_PCIE_INTR_NONFATAL 27 +#define AMD_DW_PCIE_INTR_FATAL 28 + +#define AMD_DW_PCIE_INTR_INTX_MASK GENMASK(23, 16) + +#define AMD_DW_PCIE_IMR_ALL_MASK \ + (BIT(AMD_DW_PCIE_INTR_CMPL_TIMEOUT) | \ + BIT(AMD_DW_PCIE_INTR_PM_PME_RCVD) | \ + BIT(AMD_DW_PCIE_INTR_PME_TO_ACK_RCVD) | \ + BIT(AMD_DW_PCIE_INTR_MISC_CORRECTABLE) | \ + BIT(AMD_DW_PCIE_INTR_NONFATAL) | \ + BIT(AMD_DW_PCIE_INTR_FATAL) | \ + AMD_DW_PCIE_INTR_INTX_MASK) + +/* DW PCIe Debug Registers (in DBI space) */ +#define AMD_DW_PCIE_PORT_DEBUG1 0x72c +#define AMD_DW_PCIE_PORT_DEBUG1_LINK_UP BIT(4) +#define AMD_DW_PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29) +#define AMD_DW_PCIE_DBI_64BIT_MEM_DECODE BIT(0) + +/* Link training timeout */ +#define LINK_WAIT_MSLEEP_MAX 1000 + +/* PCIe spec timing requirements */ +#define PCIE_RESET_CONFIG_WAIT_MS 100 +#define PCIE_T_PERST_WAIT_MS 1 + +/** + * struct amd_dw_pcie - AMD DesignWare PCIe controller private data + * @dw: DesignWare PCIe common structure + * @slcr_base: System Level Control Register base (for interrupts) + */ +struct amd_dw_pcie { + struct pcie_dw dw; + void __iomem *slcr_base; +}; + +static void amd_dw_pcie_init_port(struct amd_dw_pcie *pcie) +{ + u32 val; + + if (!pcie->slcr_base) + return; + + /* Disable all TLP interrupts */ + writel(AMD_DW_PCIE_IMR_ALL_MASK, + pcie->slcr_base + AMD_DW_TLP_IR_DISABLE_MISC); + + /* Clear any pending TLP interrupts */ + val = readl(pcie->slcr_base + AMD_DW_TLP_IR_STATUS_MISC); + val &= AMD_DW_PCIE_IMR_ALL_MASK; + writel(val, pcie->slcr_base + AMD_DW_TLP_IR_STATUS_MISC); +} + +static void amd_dw_pcie_start_link(struct amd_dw_pcie *pcie) +{ + void __iomem *reg = pcie->dw.dbi_base + AMD_DW_PCIE_PORT_DEBUG1; + struct udevice *dev = pcie->dw.dev; + struct pcie_dw *pci = &pcie->dw; + int ret; + + ret = wait_for_bit_le32(reg, AMD_DW_PCIE_PORT_DEBUG1_LINK_UP, + true, LINK_WAIT_MSLEEP_MAX, + false); + if (!ret) + ret = wait_for_bit_le32(reg, + AMD_DW_PCIE_PORT_DEBUG1_LINK_IN_TRAINING, + false, LINK_WAIT_MSLEEP_MAX, false); + if (ret) + dev_warn(dev, "PCIE-%d: Link down\n", dev_seq(dev)); + else + dev_dbg(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", + dev_seq(dev), pcie_dw_get_link_speed(pci), + pcie_dw_get_link_width(pci), pci->first_busno); +} + +static void amd_dw_pcie_host_init(struct amd_dw_pcie *pcie) +{ + struct pcie_dw *pci = &pcie->dw; + + /* + * Set 64-bit prefetchable memory decode capability. U-Boot's pci_auto.c + * reads this bit before assigning prefetchable BARs. If cleared, it skips + * PCI_PREF_BASE_UPPER32 programming, causing 64-bit BAR assignment to fail. + */ + dw_pcie_dbi_write_enable(pci, true); + setbits_le32(pci->dbi_base + PCI_PREF_MEMORY_BASE, + AMD_DW_PCIE_DBI_64BIT_MEM_DECODE); + dw_pcie_dbi_write_enable(pci, false); + + amd_dw_pcie_init_port(pcie); + pcie_dw_setup_host(pci); +} + +static void amd_dw_pcie_request_gpio(struct udevice *dev) +{ + struct gpio_desc perst_gpio; + ofnode child_node; + int ret; + + /* + * PERST# reset GPIO is optional. Child PCI endpoint nodes may carry a + * 'reset-gpios' property to toggle the endpoint reset signal during + * initialization. If absent, the endpoint is assumed to be already + * released from reset. + */ + ofnode_for_each_subnode(child_node, dev_ofnode(dev)) { + ret = gpio_request_by_name_nodev(child_node, "reset-gpios", 0, + &perst_gpio, GPIOD_IS_OUT); + if (!ret) { + dev_dbg(dev, "Found reset-gpios in child node %s\n", + ofnode_get_name(child_node)); + dm_gpio_set_value(&perst_gpio, 1); + mdelay(PCIE_T_PERST_WAIT_MS); + dm_gpio_set_value(&perst_gpio, 0); + mdelay(PCIE_RESET_CONFIG_WAIT_MS); + dm_gpio_free(dev, &perst_gpio); + } + } +} + +static int amd_dw_pcie_of_to_plat(struct udevice *dev) +{ + struct pci_region *io_region, *mem_region, *pref_region; + struct amd_dw_pcie *pcie = dev_get_priv(dev); + struct pcie_dw *pci = &pcie->dw; + int ret; + + pci->dev = dev; + + pci->dbi_base = dev_read_addr_name_ptr(dev, "dbi"); + if (!pci->dbi_base) { + dev_err(dev, "Missing 'dbi' register region\n"); + return -EINVAL; + } + + pci->cfg_base = dev_read_addr_size_name_ptr(dev, "config", &pci->cfg_size); + if (!pci->cfg_base) { + dev_err(dev, "Missing 'config' register region\n"); + return -EINVAL; + } + + pci->atu_base = dev_read_addr_name_ptr(dev, "atu"); + if (!pci->atu_base) { + dev_dbg(dev, "No 'atu' region, using default offset from DBI\n"); + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } + + pcie->slcr_base = dev_read_addr_name_ptr(dev, "slcr"); + if (!pcie->slcr_base) + dev_dbg(dev, "No 'slcr' region, interrupt features disabled\n"); + + ret = pci_get_regions(dev, &io_region, &mem_region, &pref_region); + if (ret < 0) { + dev_err(dev, "Failed to get PCI regions: %d\n", ret); + return ret; + } + + if (mem_region) + pci->mem = *mem_region; + + return 0; +} + +static int amd_dw_pcie_probe(struct udevice *dev) +{ + struct amd_dw_pcie *pcie = dev_get_priv(dev); + struct pcie_dw *pci = &pcie->dw; + + /* Set first bus number */ + pci->first_busno = dev_seq(dev); + + amd_dw_pcie_request_gpio(dev); + amd_dw_pcie_host_init(pcie); + amd_dw_pcie_start_link(pcie); + + if (pci->mem.size) { + dev_dbg(dev, "Programming ATU region 0 for MEM: phys=0x%llx bus=0x%llx size=0x%llx\n", + (unsigned long long)pci->mem.phys_start, + (unsigned long long)pci->mem.bus_start, + (unsigned long long)pci->mem.size); + pcie_dw_prog_outbound_atu_unroll(pci, + PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, + pci->mem.phys_start, + pci->mem.bus_start, + pci->mem.size); + } else { + dev_warn(dev, "No MEM region configured!\n"); + } + + dev_dbg(dev, "dbi: 0x%lx | config: 0x%lx | atu: 0x%lx | slcr: 0x%lx\n", + (long)pci->dbi_base, (long)pci->cfg_base, + (long)pci->atu_base, (long)pcie->slcr_base); + + return 0; +} + +static const struct dm_pci_ops amd_dw_pcie_ops = { + .read_config = pcie_dw_read_config, + .write_config = pcie_dw_write_config, +}; + +static const struct udevice_id amd_dw_pcie_ids[] = { + { .compatible = "amd,versal2-mdb-host" }, + { } +}; + +U_BOOT_DRIVER(pcie_dw_amd) = { + .name = "pcie_dw_amd", + .id = UCLASS_PCI, + .of_match = amd_dw_pcie_ids, + .ops = &amd_dw_pcie_ops, + .of_to_plat = amd_dw_pcie_of_to_plat, + .probe = amd_dw_pcie_probe, + .priv_auto = sizeof(struct amd_dw_pcie), +}; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 09810b62b51..fc4daa00661 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -292,6 +292,17 @@ config PHY_MTK_UFS initialization, power on and power off flow of specified M-PHYs. +config PHY_MTK_XSPHY + bool "MediaTek XS-PHY Driver" + depends on PHY + depends on ARCH_MEDIATEK + select REGMAP + select SYSCON + help + Enable this to support the SuperSpeedPlus XS-PHY transceiver for + USB3.1 GEN2 controllers on MediaTek chips. The driver supports + multiple USB2.0, USB3.1 GEN2 ports. + config PHY_NPCM_USB bool "Nuvoton NPCM USB PHY support" depends on PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 83102349669..684e9a99af8 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_EXYNOS_USBDRD) += phy-exynos-usbdrd.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o +obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o obj-$(CONFIG_$(PHASE_)PHY_IMX8MQ_USB) += phy-imx8mq-usb.o obj-$(CONFIG_PHY_IMX8M_PCIE) += phy-imx8m-pcie.o diff --git a/drivers/phy/phy-mtk-ufs.c b/drivers/phy/phy-mtk-ufs.c index 1eda3df858d..c4c214dcde0 100644 --- a/drivers/phy/phy-mtk-ufs.c +++ b/drivers/phy/phy-mtk-ufs.c @@ -6,52 +6,41 @@ * Copyright (c) 2025, Igor Belwon <[email protected]> */ -#include "dm/ofnode.h" -#include "dm/read.h" -#include <clk.h> -#include <dm.h> -#include <generic-phy.h> -#include <malloc.h> -#include <mapmem.h> -#include <regmap.h> -#include <syscon.h> #include <asm/io.h> +#include <clk.h> +#include <dm/device.h> #include <dm/device_compat.h> -#include <dm/devres.h> -#include <linux/bitfield.h> +#include <dm/read.h> +#include <generic-phy.h> #include <linux/bitops.h> #include <linux/delay.h> - -#include <dt-bindings/phy/phy.h> +#include <mapmem.h> /* mphy register and offsets */ -#define MP_GLB_DIG_8C 0x008C -#define FRC_PLL_ISO_EN BIT(8) -#define PLL_ISO_EN BIT(9) -#define FRC_FRC_PWR_ON BIT(10) -#define PLL_PWR_ON BIT(11) - -#define MP_LN_DIG_RX_9C 0xA09C -#define FSM_DIFZ_FRC BIT(18) +#define MP_GLB_DIG_8C 0x008C +#define FRC_PLL_ISO_EN BIT(8) +#define PLL_ISO_EN BIT(9) +#define FRC_FRC_PWR_ON BIT(10) +#define PLL_PWR_ON BIT(11) -#define MP_LN_DIG_RX_AC 0xA0AC -#define FRC_RX_SQ_EN BIT(0) -#define RX_SQ_EN BIT(1) +#define MP_LN_DIG_RX_9C 0xA09C +#define FSM_DIFZ_FRC BIT(18) -#define MP_LN_RX_44 0xB044 -#define FRC_CDR_PWR_ON BIT(17) -#define CDR_PWR_ON BIT(18) -#define FRC_CDR_ISO_EN BIT(19) -#define CDR_ISO_EN BIT(20) +#define MP_LN_DIG_RX_AC 0xA0AC +#define FRC_RX_SQ_EN BIT(0) +#define RX_SQ_EN BIT(1) -#define UFSPHY_CLKS_CNT 2 +#define MP_LN_RX_44 0xB044 +#define FRC_CDR_PWR_ON BIT(17) +#define CDR_PWR_ON BIT(18) +#define FRC_CDR_ISO_EN BIT(19) +#define CDR_ISO_EN BIT(20) struct mtk_ufs_phy { struct udevice *dev; void __iomem *mmio; - struct clk *unipro_clk; - struct clk *mp_clk; + struct clk_bulk clk_bulk; }; static void ufs_mtk_phy_set_active(struct mtk_ufs_phy *phy) @@ -88,16 +77,9 @@ static int mtk_phy_power_on(struct phy *phy) struct mtk_ufs_phy *ufs_phy = dev_get_priv(phy->dev); int ret; - ret = clk_enable(ufs_phy->mp_clk); - if (ret < 0) { - dev_err(phy->dev, "failed to enable mp_clk\n"); - return ret; - } - - ret = clk_enable(ufs_phy->unipro_clk); - if (ret < 0) { - dev_err(phy->dev, "failed to enable unipro_clk %d\n", ret); - clk_disable(ufs_phy->unipro_clk); + ret = clk_enable_bulk(&ufs_phy->clk_bulk); + if (ret) { + dev_err(phy->dev, "failed to enable clocks (ret=%d)\n", ret); return ret; } @@ -106,34 +88,44 @@ static int mtk_phy_power_on(struct phy *phy) return 0; } -static int mtk_phy_power_off(struct phy *phy) +static void ufs_mtk_phy_set_inactive(struct mtk_ufs_phy *phy) { - struct mtk_ufs_phy *ufs_phy = dev_get_priv(phy->dev); - /* Set PHY to Deep Hibernate mode */ - setbits_le32(ufs_phy->mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); + setbits_le32(phy->mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC); /* force DA_MP_RX0_SQ_EN */ - setbits_le32(ufs_phy->mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); - clrbits_le32(ufs_phy->mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); + setbits_le32(phy->mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN); + clrbits_le32(phy->mmio + MP_LN_DIG_RX_AC, RX_SQ_EN); /* force DA_MP_CDR_ISO_EN */ - setbits_le32(ufs_phy->mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); - setbits_le32(ufs_phy->mmio + MP_LN_RX_44, CDR_ISO_EN); + setbits_le32(phy->mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); + setbits_le32(phy->mmio + MP_LN_RX_44, CDR_ISO_EN); /* force DA_MP_CDR_PWR_ON */ - setbits_le32(ufs_phy->mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); - clrbits_le32(ufs_phy->mmio + MP_LN_RX_44, CDR_PWR_ON); + setbits_le32(phy->mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); + clrbits_le32(phy->mmio + MP_LN_RX_44, CDR_PWR_ON); /* force DA_MP_PLL_ISO_EN */ - setbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); - setbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, PLL_ISO_EN); + setbits_le32(phy->mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); + setbits_le32(phy->mmio + MP_GLB_DIG_8C, PLL_ISO_EN); /* force DA_MP_PLL_PWR_ON */ - setbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); - clrbits_le32(ufs_phy->mmio + MP_GLB_DIG_8C, PLL_PWR_ON); + setbits_le32(phy->mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); + clrbits_le32(phy->mmio + MP_GLB_DIG_8C, PLL_PWR_ON); +} - return 0; +static int mtk_phy_power_off(struct phy *phy) +{ + struct mtk_ufs_phy *ufs_phy = dev_get_priv(phy->dev); + int ret; + + ufs_mtk_phy_set_inactive(ufs_phy); + + ret = clk_disable_bulk(&ufs_phy->clk_bulk); + if (ret) + dev_err(phy->dev, "failed to disable clocks (ret=%d)\n", ret); + + return ret; } static const struct phy_ops mtk_ufs_phy_ops = { @@ -147,10 +139,6 @@ static int mtk_ufs_phy_probe(struct udevice *dev) fdt_addr_t addr; int ret; - phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -ENOMEM; @@ -158,21 +146,11 @@ static int mtk_ufs_phy_probe(struct udevice *dev) phy->dev = dev; phy->mmio = map_sysmem(addr, 0); - phy->mp_clk = devm_clk_get(dev, "mp"); - if (IS_ERR(phy->mp_clk)) { - ret = PTR_ERR(phy->mp_clk); - dev_err(dev, "Failed to get mp clock (ret=%d)\n", ret); - return ret; - } + ret = clk_get_bulk(dev, &phy->clk_bulk); + if (ret) + dev_err(dev, "Failed to get clocks (ret=%d)\n", ret); - phy->unipro_clk = devm_clk_get(dev, "unipro"); - if (IS_ERR(phy->unipro_clk)) { - ret = PTR_ERR(phy->unipro_clk); - dev_err(dev, "Failed to get unipro clock (ret=%d)\n", ret); - return ret; - } - - return 0; + return ret; } static const struct udevice_id mtk_ufs_phy_id_table[] = { diff --git a/drivers/phy/phy-mtk-xsphy.c b/drivers/phy/phy-mtk-xsphy.c new file mode 100644 index 00000000000..d3418ffb101 --- /dev/null +++ b/drivers/phy/phy-mtk-xsphy.c @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MediaTek USB3.1 gen2 xsphy Driver + * + * Copyright (c) 2026 MediaTek Inc. + * Copyright (c) 2026 BayLibre, SAS + * + * Based on Linux mtk-xsphy driver: + * Copyright (c) 2018 MediaTek Inc. + * Author: Chunfeng Yun <[email protected]> + * + * And U-Boot mtk-tphy driver: + * Copyright (c) 2015 - 2019 MediaTek Inc. + * Author: Chunfeng Yun <[email protected]> + * Ryder Lee <[email protected]> + */ + +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <malloc.h> +#include <mapmem.h> +#include <regmap.h> +#include <syscon.h> + +#include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/iopoll.h> + +#include <dt-bindings/phy/phy.h> + +/* u2 phy banks */ +#define SSUSB_SIFSLV_MISC 0x000 +#define SSUSB_SIFSLV_U2FREQ 0x100 +#define SSUSB_SIFSLV_U2PHY_COM 0x300 + +/* u3 phy shared banks */ +#define SSPXTP_SIFSLV_DIG_GLB 0x000 +#define SSPXTP_SIFSLV_PHYA_GLB 0x100 + +/* u3 phy banks */ +#define SSPXTP_SIFSLV_DIG_LN_TOP 0x000 +#define SSPXTP_SIFSLV_DIG_LN_TX0 0x100 +#define SSPXTP_SIFSLV_DIG_LN_RX0 0x200 +#define SSPXTP_SIFSLV_DIG_LN_DAIF 0x300 +#define SSPXTP_SIFSLV_PHYA_LN 0x400 + +#define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00) +#define P2F_RG_FREQDET_EN BIT(24) +#define P2F_RG_CYCLECNT GENMASK(23, 0) + +#define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c) + +#define XSP_U2FREQ_FMMONR1 ((SSUSB_SIFSLV_U2FREQ) + 0x10) +#define P2F_RG_FRCK_EN BIT(8) +#define P2F_USB_FM_VALID BIT(0) + +#define XSP_USBPHYACR0 ((SSUSB_SIFSLV_U2PHY_COM) + 0x00) +#define P2A0_RG_INTR_EN BIT(5) + +#define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04) +#define P2A1_RG_INTR_CAL GENMASK(23, 19) +#define P2A1_RG_VRT_SEL GENMASK(14, 12) +#define P2A1_RG_TERM_SEL GENMASK(10, 8) + +#define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014) +#define P2A5_RG_HSTX_SRCAL_EN BIT(15) +#define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12) + +#define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018) +#define P2A6_RG_BC11_SW_EN BIT(23) +#define P2A6_RG_OTG_VBUSCMP_EN BIT(20) + +#define XSP_U2PHYDTM1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C) +#define P2D_FORCE_IDDIG BIT(9) +#define P2D_RG_VBUSVALID BIT(5) +#define P2D_RG_SESSEND BIT(4) +#define P2D_RG_AVALID BIT(2) +#define P2D_RG_IDDIG BIT(1) + +#define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00) +#define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16) + +#define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04) +#define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0) + +#define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014) +#define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0) + +#define XSP_REF_CLK_MHZ 26 +#define XSP_SLEW_RATE_COEF 17 +#define XSP_SR_COEF_DIVISOR 1000 +#define XSP_FM_DET_CYCLE_CNT 1024 + +/* PHY switch between pcie/usb3/sgmii */ +#define USB_PHY_SWITCH_CTRL 0x0 +#define RG_PHY_SW_TYPE GENMASK(3, 0) +#define RG_PHY_SW_PCIE 0x0 +#define RG_PHY_SW_USB3 0x1 +#define RG_PHY_SW_SGMII 0x2 + +struct mtk_xsphy_instance { + void __iomem *port_base; + struct device_node *np; + struct clk ref_clk; /* reference clock of analog phy */ + u32 index; + u32 type; + struct regmap *type_sw; + u32 type_sw_reg; + u32 type_sw_index; + /* only for HQA test */ + u32 efuse_intr; + u32 efuse_tx_imp; + u32 efuse_rx_imp; + /* u2 eye diagram */ + u32 eye_src; + u32 eye_vrt; + u32 eye_term; +}; + +struct mtk_xsphy { + struct udevice *dev; + void __iomem *sif_base; + struct mtk_xsphy_instance **phys; + u32 nphys; + u32 src_ref_clk_mhz; /* reference clock for slew rate calibrate */ + u32 src_coef; /* coefficient for slew rate calibrate */ +}; + +static void mtk_xsphy_u2_slew_rate_calibrate(struct mtk_xsphy *xsphy, + struct mtk_xsphy_instance *instance) +{ + void __iomem *pbase = instance->port_base; + u32 calib_val; + u32 fm_out; + u32 tmp; + + /* use force value */ + if (instance->eye_src) + return; + + /* enable USB ring oscillator */ + setbits_le32(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); + /* wait for clock to become stable */ + udelay(1); + + /* enable free run clock */ + setbits_le32(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); + + /* set cycle count as 1024 */ + clrsetbits_le32(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT, + FIELD_PREP(P2F_RG_CYCLECNT, XSP_FM_DET_CYCLE_CNT)); + + /* enable frequency meter */ + setbits_le32(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); + + /* ignore return value */ + readl_poll_sleep_timeout(pbase + XSP_U2FREQ_FMMONR1, tmp, + (tmp & P2F_USB_FM_VALID), 10, 200); + + fm_out = readl(pbase + XSP_U2FREQ_MMONR0); + + /* disable frequency meter */ + clrbits_le32(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); + + /* disable free run clock */ + clrbits_le32(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); + + if (fm_out) { + /* (1024 / FM_OUT) x reference clock frequency x coefficient */ + tmp = xsphy->src_ref_clk_mhz * xsphy->src_coef; + tmp = (tmp * XSP_FM_DET_CYCLE_CNT) / fm_out; + calib_val = DIV_ROUND_CLOSEST(tmp, XSP_SR_COEF_DIVISOR); + } else { + /* if FM detection fail, set default value */ + calib_val = 3; + } + dev_dbg(xsphy->dev, "phy.%u, fm_out:%u, calib:%u (clk:%u, coef:%u)\n", + instance->index, fm_out, calib_val, xsphy->src_ref_clk_mhz, + xsphy->src_coef); + + /* set HS slew rate */ + clrsetbits_le32(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, + FIELD_PREP(P2A5_RG_HSTX_SRCTRL, calib_val)); + + /* disable USB ring oscillator */ + clrbits_le32(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN); +} + +static void mtk_xsphy_u2_instance_init(struct mtk_xsphy *xsphy, + struct mtk_xsphy_instance *instance) +{ + void __iomem *pbase = instance->port_base; + + /* DP/DM BC1.1 path Disable */ + clrbits_le32(pbase + XSP_USBPHYACR6, P2A6_RG_BC11_SW_EN); + + setbits_le32(pbase + XSP_USBPHYACR0, P2A0_RG_INTR_EN); +} + +static void mtk_xsphy_u2_instance_power_on(struct mtk_xsphy *xsphy, + struct mtk_xsphy_instance *instance) +{ + void __iomem *pbase = instance->port_base; + + setbits_le32(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN); + + clrsetbits_le32(pbase + XSP_U2PHYDTM1, + P2D_RG_VBUSVALID | P2D_RG_AVALID | P2D_RG_SESSEND, + P2D_RG_VBUSVALID | P2D_RG_AVALID); + + dev_dbg(xsphy->dev, "%s(%u)\n", __func__, instance->index); +} + +static void mtk_xsphy_u2_instance_power_off(struct mtk_xsphy *xsphy, + struct mtk_xsphy_instance *instance) +{ + void __iomem *pbase = instance->port_base; + + clrbits_le32(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN); + + clrsetbits_le32(pbase + XSP_U2PHYDTM1, + P2D_RG_VBUSVALID | P2D_RG_AVALID | P2D_RG_SESSEND, + P2D_RG_SESSEND); + + dev_dbg(xsphy->dev, "%s(%u)\n", __func__, instance->index); +} + +static void mtk_xsphy_u2_instance_set_mode(struct mtk_xsphy *xsphy, + struct mtk_xsphy_instance *instance, + enum phy_mode mode) +{ + u32 tmp; + + tmp = readl(instance->port_base + XSP_U2PHYDTM1); + + switch (mode) { + case PHY_MODE_USB_DEVICE: + tmp |= P2D_FORCE_IDDIG | P2D_RG_IDDIG; + break; + case PHY_MODE_USB_HOST: + tmp |= P2D_FORCE_IDDIG; + tmp &= ~P2D_RG_IDDIG; + break; + case PHY_MODE_USB_OTG: + tmp &= ~(P2D_FORCE_IDDIG | P2D_RG_IDDIG); + break; + default: + return; + } + + writel(tmp, instance->port_base + XSP_U2PHYDTM1); +} + +static void mtk_xsphy_parse_property(struct mtk_xsphy *xsphy, + struct mtk_xsphy_instance *instance) +{ + ofnode node = np_to_ofnode(instance->np); + + switch (instance->type) { + case PHY_TYPE_USB2: + ofnode_read_u32(node, "mediatek,efuse-intr", &instance->efuse_intr); + ofnode_read_u32(node, "mediatek,eye-src", &instance->eye_src); + ofnode_read_u32(node, "mediatek,eye-vrt", &instance->eye_vrt); + ofnode_read_u32(node, "mediatek,eye-term", &instance->eye_term); + + dev_dbg(xsphy->dev, "intr:%u, src:%u, vrt:%u, term:%u\n", + instance->efuse_intr, instance->eye_src, + instance->eye_vrt, instance->eye_term); + return; + case PHY_TYPE_USB3: + ofnode_read_u32(node, "mediatek,efuse-intr", &instance->efuse_intr); + ofnode_read_u32(node, "mediatek,efuse-tx-imp", &instance->efuse_tx_imp); + ofnode_read_u32(node, "mediatek,efuse-rx-imp", &instance->efuse_rx_imp); + + dev_dbg(xsphy->dev, "intr:%u, tx-imp:%u, rx-imp:%u\n", + instance->efuse_intr, instance->efuse_tx_imp, + instance->efuse_rx_imp); + return; + case PHY_TYPE_PCIE: + case PHY_TYPE_SGMII: + /* nothing to do */ + return; + default: + dev_err(xsphy->dev, "incompatible PHY type\n"); + return; + } +} + +static void mtk_xsphy_u2_props_set(struct mtk_xsphy *xsphy, + struct mtk_xsphy_instance *instance) +{ + void __iomem *pbase = instance->port_base; + + if (instance->efuse_intr) + clrsetbits_le32(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL, + FIELD_PREP(P2A1_RG_INTR_CAL, instance->efuse_intr)); + + if (instance->eye_src) + clrsetbits_le32(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, + FIELD_PREP(P2A5_RG_HSTX_SRCTRL, instance->eye_src)); + + if (instance->eye_vrt) + clrsetbits_le32(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL, + FIELD_PREP(P2A1_RG_VRT_SEL, instance->eye_vrt)); + + if (instance->eye_term) + clrsetbits_le32(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL, + FIELD_PREP(P2A1_RG_TERM_SEL, instance->eye_term)); +} + +static void mtk_xsphy_u3_props_set(struct mtk_xsphy *xsphy, + struct mtk_xsphy_instance *instance) +{ + void __iomem *pbase = instance->port_base; + + if (instance->efuse_intr) + clrsetbits_le32(xsphy->sif_base + SSPXTP_PHYA_GLB_00, + RG_XTP_GLB_BIAS_INTR_CTRL, + FIELD_PREP(RG_XTP_GLB_BIAS_INTR_CTRL, instance->efuse_intr)); + + if (instance->efuse_tx_imp) + clrsetbits_le32(pbase + SSPXTP_PHYA_LN_04, RG_XTP_LN0_TX_IMPSEL, + FIELD_PREP(RG_XTP_LN0_TX_IMPSEL, instance->efuse_tx_imp)); + + if (instance->efuse_rx_imp) + clrsetbits_le32(pbase + SSPXTP_PHYA_LN_14, RG_XTP_LN0_RX_IMPSEL, + FIELD_PREP(RG_XTP_LN0_RX_IMPSEL, instance->efuse_rx_imp)); +} + +/* type switch for usb3/pcie/sgmii */ +static int mtk_xsphy_type_syscon_get(struct udevice *dev, + struct mtk_xsphy_instance *instance, + ofnode dn) +{ + struct ofnode_phandle_args args; + int ret; + + if (!ofnode_read_bool(dn, "mediatek,syscon-type")) + return 0; + + ret = ofnode_parse_phandle_with_args(dn, "mediatek,syscon-type", + NULL, 2, 0, &args); + if (ret) + return ret; + + instance->type_sw_reg = args.args[0]; + instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ + instance->type_sw = syscon_node_to_regmap(args.node); + if (IS_ERR(instance->type_sw)) + return PTR_ERR(instance->type_sw); + + dev_dbg(dev, "phy-%s.%d: type_sw - reg %#x, index %d\n", + dev->name, instance->index, instance->type_sw_reg, + instance->type_sw_index); + + return 0; +} + +static int mtk_xsphy_type_set(struct mtk_xsphy_instance *instance) +{ + int type; + u32 offset; + + if (!instance->type_sw) + return 0; + + switch (instance->type) { + case PHY_TYPE_USB3: + type = RG_PHY_SW_USB3; + break; + case PHY_TYPE_PCIE: + type = RG_PHY_SW_PCIE; + break; + case PHY_TYPE_SGMII: + type = RG_PHY_SW_SGMII; + break; + case PHY_TYPE_USB2: + default: + return 0; + } + + offset = instance->type_sw_index * BITS_PER_BYTE; + regmap_update_bits(instance->type_sw, instance->type_sw_reg, + RG_PHY_SW_TYPE << offset, type << offset); + + return 0; +} + +static int mtk_xsphy_init(struct phy *phy) +{ + struct mtk_xsphy *xsphy = dev_get_priv(phy->dev); + struct mtk_xsphy_instance *instance = xsphy->phys[phy->id]; + int ret; + + ret = clk_enable(&instance->ref_clk); + if (ret) { + dev_err(xsphy->dev, "failed to enable ref_clk\n"); + return ret; + } + + switch (instance->type) { + case PHY_TYPE_USB2: + mtk_xsphy_u2_instance_init(xsphy, instance); + mtk_xsphy_u2_props_set(xsphy, instance); + break; + case PHY_TYPE_USB3: + mtk_xsphy_u3_props_set(xsphy, instance); + break; + case PHY_TYPE_PCIE: + case PHY_TYPE_SGMII: + /* nothing to do, only used to set type */ + break; + default: + dev_err(xsphy->dev, "incompatible PHY type\n"); + clk_disable(&instance->ref_clk); + return -EINVAL; + } + + return 0; +} + +static int mtk_xsphy_power_on(struct phy *phy) +{ + struct mtk_xsphy *xsphy = dev_get_priv(phy->dev); + struct mtk_xsphy_instance *instance = xsphy->phys[phy->id]; + + if (instance->type == PHY_TYPE_USB2) { + mtk_xsphy_u2_instance_power_on(xsphy, instance); + mtk_xsphy_u2_slew_rate_calibrate(xsphy, instance); + } + + return 0; +} + +static int mtk_xsphy_power_off(struct phy *phy) +{ + struct mtk_xsphy *xsphy = dev_get_priv(phy->dev); + struct mtk_xsphy_instance *instance = xsphy->phys[phy->id]; + + if (instance->type == PHY_TYPE_USB2) + mtk_xsphy_u2_instance_power_off(xsphy, instance); + + return 0; +} + +static int mtk_xsphy_exit(struct phy *phy) +{ + struct mtk_xsphy *xsphy = dev_get_priv(phy->dev); + struct mtk_xsphy_instance *instance = xsphy->phys[phy->id]; + + clk_disable(&instance->ref_clk); + + return 0; +} + +static int mtk_xsphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct mtk_xsphy *xsphy = dev_get_priv(phy->dev); + struct mtk_xsphy_instance *instance = xsphy->phys[phy->id]; + + if (instance->type == PHY_TYPE_USB2) + mtk_xsphy_u2_instance_set_mode(xsphy, instance, mode); + + return 0; +} + +static int mtk_xsphy_xlate(struct phy *phy, struct ofnode_phandle_args *args) +{ + struct mtk_xsphy *xsphy = dev_get_priv(phy->dev); + struct mtk_xsphy_instance *instance = NULL; + const struct device_node *phy_np = ofnode_to_np(args->node); + u32 index; + + if (!phy_np) { + dev_err(phy->dev, "null pointer phy node\n"); + return -EINVAL; + } + + if (args->args_count != 2) { + dev_err(phy->dev, "invalid number of cells in 'phy' property\n"); + return -EINVAL; + } + + for (index = 0; index < xsphy->nphys; index++) + if (phy_np == xsphy->phys[index]->np) { + instance = xsphy->phys[index]; + break; + } + + if (!instance) { + dev_err(phy->dev, "failed to find appropriate phy\n"); + return -EINVAL; + } + + phy->id = index; + instance->type = args->args[1]; + if (!(instance->type == PHY_TYPE_USB2 || + instance->type == PHY_TYPE_USB3 || + instance->type == PHY_TYPE_PCIE || + instance->type == PHY_TYPE_SGMII)) { + dev_err(phy->dev, "unsupported PHY type\n"); + return -EINVAL; + } + + mtk_xsphy_parse_property(xsphy, instance); + mtk_xsphy_type_set(instance); + + return 0; +} + +static const struct phy_ops mtk_xsphy_ops = { + .init = mtk_xsphy_init, + .exit = mtk_xsphy_exit, + .power_on = mtk_xsphy_power_on, + .power_off = mtk_xsphy_power_off, + .set_mode = mtk_xsphy_set_mode, + .of_xlate = mtk_xsphy_xlate, +}; + +static int mtk_xsphy_probe(struct udevice *dev) +{ + struct mtk_xsphy *xsphy = dev_get_priv(dev); + fdt_addr_t sif_addr; + ofnode subnode; + int index = 0; + + xsphy->nphys = dev_get_child_count(dev); + + xsphy->phys = devm_kcalloc(dev, xsphy->nphys, sizeof(*xsphy->phys), + GFP_KERNEL); + if (!xsphy->phys) + return -ENOMEM; + + xsphy->dev = dev; + + sif_addr = ofnode_get_addr(dev_ofnode(dev)); + /* optional, may not exist if no u3 phys */ + if (sif_addr != FDT_ADDR_T_NONE) + xsphy->sif_base = map_sysmem(sif_addr, 0); + + xsphy->src_ref_clk_mhz = XSP_REF_CLK_MHZ; + xsphy->src_coef = XSP_SLEW_RATE_COEF; + /* update parameters of slew rate calibrate if exist */ + ofnode_read_u32(dev_ofnode(dev), "mediatek,src-ref-clk-mhz", + &xsphy->src_ref_clk_mhz); + ofnode_read_u32(dev_ofnode(dev), "mediatek,src-coef", &xsphy->src_coef); + + dev_for_each_subnode(subnode, dev) { + struct mtk_xsphy_instance *inst; + fdt_addr_t addr; + int ret; + + inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + + xsphy->phys[index] = inst; + + addr = ofnode_get_addr(subnode); + if (addr == FDT_ADDR_T_NONE) + return -EADDRNOTAVAIL; + + inst->port_base = map_sysmem(addr, 0); + inst->index = index; + inst->np = ofnode_to_np(subnode); + + ret = clk_get_by_name_nodev(subnode, "ref", &inst->ref_clk); + if (ret) { + dev_err(dev, "failed to get ref_clk(id-%d)\n", index); + return ret; + } + + ret = mtk_xsphy_type_syscon_get(dev, inst, subnode); + if (ret) + return ret; + + index++; + } + + return 0; +} + +static const struct udevice_id mtk_xsphy_id_table[] = { + { .compatible = "mediatek,xsphy" }, + { } +}; + +U_BOOT_DRIVER(mtk_xsphy) = { + .name = "mtk-xsphy", + .id = UCLASS_PHY, + .of_match = mtk_xsphy_id_table, + .ops = &mtk_xsphy_ops, + .probe = mtk_xsphy_probe, + .priv_auto = sizeof(struct mtk_xsphy), +}; diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c index 9e821365c15..6278171b100 100644 --- a/drivers/phy/qcom/phy-qcom-qusb2.c +++ b/drivers/phy/qcom/phy-qcom-qusb2.c @@ -176,6 +176,19 @@ static const unsigned int sm6115_regs_layout[] = { [QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc, }; +static const unsigned int ipq6018_regs_layout[] = { + [QUSB2PHY_PLL_STATUS] = 0x38, + [QUSB2PHY_PORT_TUNE1] = 0x80, + [QUSB2PHY_PORT_TUNE2] = 0x84, + [QUSB2PHY_PORT_TUNE3] = 0x88, + [QUSB2PHY_PORT_TUNE4] = 0x8C, + [QUSB2PHY_PORT_TUNE5] = 0x90, + [QUSB2PHY_PORT_TEST1] = 0x98, + [QUSB2PHY_PORT_TEST2] = 0x9C, + [QUSB2PHY_PORT_POWERDOWN] = 0xB4, + [QUSB2PHY_INTR_CTRL] = 0xBC, +}; + static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), @@ -189,6 +202,19 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), }; +static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = { + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), + QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), +}; + static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), @@ -260,6 +286,16 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = { .autoresume_en = BIT(3), }; +static const struct qusb2_phy_cfg qcs615_phy_cfg = { + .tbl = qcs615_init_tbl, + .tbl_num = ARRAY_SIZE(qcs615_init_tbl), + .regs = ipq6018_regs_layout, + + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), + .mask_core_ready = PLL_LOCKED, + .autoresume_en = BIT(0), +}; + static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { .tbl = qusb2_v2_init_tbl, .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), @@ -467,6 +503,8 @@ static const struct udevice_id qusb2phy_ids[] = { { .compatible = "qcom,qusb2-phy" }, { .compatible = "qcom,qcm2290-qusb2-phy", .data = (ulong)&sm6115_phy_cfg }, + { .compatible = "qcom,qcs615-qusb2-phy", + .data = (ulong)&qcs615_phy_cfg }, { .compatible = "qcom,sdm660-qusb2-phy", .data = (ulong)&sdm660_phy_cfg }, { .compatible = "qcom,sm6115-qusb2-phy", diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c index 4ecc8bac645..90eee88eb13 100644 --- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c @@ -30,6 +30,11 @@ struct bcm283x_pinctrl_priv { #define MAX_PINS_PER_BANK 16 +/* pull states for BCM2711 */ +#define BCM2711_PULL_NONE 0 +#define BCM2711_PULL_UP 1 +#define BCM2711_PULL_DOWN 2 + static void bcm2835_gpio_set_func_id(struct udevice *dev, unsigned int gpio, int func) { @@ -93,6 +98,17 @@ static void bcm2711_gpio_set_pull(struct udevice *dev, unsigned int gpio, int pu u32 bit_shift; u32 pull_bits; + if (!device_is_compatible(dev, "brcm,bcm2711-gpio")) + return; + + /* BCM2711's pull values differ from BCM2835 */ + if (pull == BCM2835_PUD_UP) + pull = BCM2711_PULL_UP; + else if (pull == BCM2835_PUD_DOWN) + pull = BCM2711_PULL_DOWN; + else + pull = BCM2711_PULL_NONE; + /* Findout which GPIO_PUP_PDN_CNTRL register to use */ reg_offset = BCM2711_GPPUD_CNTRL_REG0 + BCM2711_PUD_REG_OFFSET(gpio); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 8875c276f36..5219b147797 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -106,7 +106,7 @@ static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), - PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(11, 11, 5, 0x20, 0x10, 10, 1), PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), @@ -215,7 +215,7 @@ static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 7, 0x70, 0x10, 8, 1), PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), @@ -279,8 +279,8 @@ static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), - PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), + PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 3), PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), @@ -288,9 +288,9 @@ static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(11, 11, 5, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(13, 13, 5, 0x10, 0x10, 3, 3), PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), @@ -302,7 +302,7 @@ static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(23, 23, 2, 0x10, 0x10, 0, 3), PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), @@ -368,7 +368,7 @@ static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(20, 20, 2, 0x30, 0x10, 3, 1), PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c index a64440d8bb3..b01533ed80b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8189.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c @@ -1015,6 +1015,29 @@ static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = { PIN_FIELD_BASE(182, IO_BASE_RT, 0x0000, 9, 3), }; +static const struct mtk_pin_field_calc mt8189_pin_rsel_range[] = { + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x00B0, 0, 3), /* SCP_SCL0 */ + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x00B0, 6, 3), /* SCP_SDA0 */ + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x00B0, 3, 3), /* SCP_SCL1 */ + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x00B0, 9, 3), /* SCP_SDA1 */ + PIN_FIELD_BASE(55, IO_BASE_LM, 0x00B0, 0, 3), /* SCL2 */ + PIN_FIELD_BASE(56, IO_BASE_LM, 0x00B0, 3, 3), /* SDA2 */ + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00B0, 0, 3), /* SCL3 */ + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00B0, 12, 3), /* SDA3 */ + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00B0, 3, 3), /* SCL4 */ + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00B0, 15, 3), /* SDA4 */ + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00B0, 6, 3), /* SCL5 */ + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00B0, 18, 3), /* SDA5 */ + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00B0, 9, 3), /* SCL6 */ + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00B0, 21, 3), /* SDA6 */ + PIN_FIELD_BASE(65, IO_BASE_RT, 0x00E0, 0, 3), /* SCL7 */ + PIN_FIELD_BASE(66, IO_BASE_RT, 0x00E0, 6, 3), /* SDA7 */ + PIN_FIELD_BASE(67, IO_BASE_RT, 0x00E0, 3, 3), /* SCL8 */ + PIN_FIELD_BASE(68, IO_BASE_RT, 0x00E0, 9, 3), /* SDA8 */ + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0110, 0, 3), /* SPMI_P_SCL */ + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0110, 3, 3), /* SPMI_P_SDA */ +}; + static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range), [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range), @@ -1028,6 +1051,7 @@ static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = { [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range), [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range), [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8189_pin_rsel_range), }; static const char * const mt8189_pinctrl_register_base_names[] = { @@ -1048,198 +1072,222 @@ static const char * const mt8189_pinctrl_register_base_names[] = { [IO_BASE_EINT4] = "eint4", }; +#define MT8189_TYPE0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT8189_TYPE1_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +#define MT8189_TYPE2_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP2) + static const struct mtk_pin_desc mt8189_pins[] = { - MTK_TYPED_PIN(0, "GPIO00", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(1, "GPIO01", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(2, "GPIO02", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(3, "GPIO03", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(4, "GPIO04", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(5, "GPIO05", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(6, "GPIO06", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(7, "GPIO07", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(8, "GPIO08", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(9, "GPIO09", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(10, "GPIO10", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(11, "GPIO11", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(12, "GPIO12", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(13, "GPIO13", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(14, "GPIO14", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(15, "GPIO15", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(16, "GPIO16", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(17, "GPIO17", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(18, "GPIO18", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(19, "GPIO19", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(20, "GPIO20", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(21, "GPIO21", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(22, "GPIO22", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(23, "GPIO23", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(24, "GPIO24", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(25, "GPIO25", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(26, "GPIO26", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(27, "GPIO27", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(28, "GPIO28", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(29, "GPIO29", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(30, "GPIO30", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(31, "GPIO31", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(32, "GPIO32", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(33, "GPIO33", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(34, "GPIO34", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(35, "GPIO35", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(36, "GPIO36", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(37, "GPIO37", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(38, "GPIO38", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(39, "GPIO39", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(40, "GPIO40", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(41, "GPIO41", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(42, "GPIO42", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(43, "GPIO43", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(44, "GPIO44", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(45, "GPIO45", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(46, "GPIO46", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(47, "GPIO47", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(48, "GPIO48", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(49, "GPIO49", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(50, "GPIO50", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(51, "GPIO51", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(52, "GPIO52", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(53, "GPIO53", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(54, "GPIO54", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(55, "GPIO55", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(56, "GPIO56", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(57, "GPIO57", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(58, "GPIO58", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(59, "GPIO59", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(60, "GPIO60", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(61, "GPIO61", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(62, "GPIO62", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(63, "GPIO63", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(64, "GPIO64", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(65, "GPIO65", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(66, "GPIO66", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(67, "GPIO67", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(68, "GPIO68", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(69, "GPIO69", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(70, "GPIO70", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(71, "GPIO71", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(72, "GPIO72", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(73, "GPIO73", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(74, "GPIO74", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(75, "GPIO75", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(76, "GPIO76", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(77, "GPIO77", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(78, "GPIO78", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(79, "GPIO79", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(80, "GPIO80", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(81, "GPIO81", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(82, "GPIO82", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(83, "GPIO83", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(84, "GPIO84", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(85, "GPIO85", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(86, "GPIO86", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(87, "GPIO87", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(88, "GPIO88", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(89, "GPIO89", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(90, "GPIO90", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(91, "GPIO91", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(92, "GPIO92", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(93, "GPIO93", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(94, "GPIO94", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(95, "GPIO95", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(96, "GPIO96", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(97, "GPIO97", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(98, "GPIO98", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(99, "GPIO99", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(100, "GPIO100", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(101, "GPIO101", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(102, "GPIO102", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(103, "GPIO103", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(104, "GPIO104", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(105, "GPIO105", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(106, "GPIO106", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(107, "GPIO107", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(108, "GPIO108", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(109, "GPIO109", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(110, "GPIO110", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(111, "GPIO111", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(112, "GPIO112", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(113, "GPIO113", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(114, "GPIO114", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(115, "GPIO115", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(116, "GPIO116", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(117, "GPIO117", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(118, "GPIO118", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(119, "GPIO119", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(120, "GPIO120", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(121, "GPIO121", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(122, "GPIO122", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(123, "GPIO123", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(124, "GPIO124", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(125, "GPIO125", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(126, "GPIO126", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(127, "GPIO127", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(128, "GPIO128", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(129, "GPIO129", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(130, "GPIO130", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(131, "GPIO131", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(132, "GPIO132", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(133, "GPIO133", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(134, "GPIO134", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(135, "GPIO135", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(136, "GPIO136", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(137, "GPIO137", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(138, "GPIO138", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(139, "GPIO139", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(140, "GPIO140", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(141, "GPIO141", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(142, "GPIO142", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(143, "GPIO143", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(144, "GPIO144", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(145, "GPIO145", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(146, "GPIO146", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(147, "GPIO147", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(148, "GPIO148", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(149, "GPIO149", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(150, "GPIO150", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(151, "GPIO151", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(152, "GPIO152", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(153, "GPIO153", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(154, "GPIO154", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(155, "GPIO155", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(156, "GPIO156", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(157, "GPIO157", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(158, "GPIO158", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(159, "GPIO159", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(160, "GPIO160", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(161, "GPIO161", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(162, "GPIO162", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(163, "GPIO163", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(164, "GPIO164", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(165, "GPIO165", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(166, "GPIO166", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(167, "GPIO167", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(168, "GPIO168", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(169, "GPIO169", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(170, "GPIO170", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(171, "GPIO171", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(172, "GPIO172", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(173, "GPIO173", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(174, "GPIO174", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(175, "GPIO175", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(176, "GPIO176", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(177, "GPIO177", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(178, "GPIO178", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(179, "GPIO179", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(180, "GPIO180", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(181, "GPIO181", DRV_GRP4, DRV_GRP0), - MTK_TYPED_PIN(182, "GPIO182", DRV_GRP4, DRV_GRP0), + MT8189_TYPE0_PIN(0, "GPIO00"), + MT8189_TYPE0_PIN(1, "GPIO01"), + MT8189_TYPE0_PIN(2, "GPIO02"), + MT8189_TYPE0_PIN(3, "GPIO03"), + MT8189_TYPE0_PIN(4, "GPIO04"), + MT8189_TYPE0_PIN(5, "GPIO05"), + MT8189_TYPE0_PIN(6, "GPIO06"), + MT8189_TYPE0_PIN(7, "GPIO07"), + MT8189_TYPE0_PIN(8, "GPIO08"), + MT8189_TYPE0_PIN(9, "GPIO09"), + MT8189_TYPE0_PIN(10, "GPIO10"), + MT8189_TYPE0_PIN(11, "GPIO11"), + MT8189_TYPE0_PIN(12, "GPIO12"), + MT8189_TYPE0_PIN(13, "GPIO13"), + MT8189_TYPE0_PIN(14, "GPIO14"), + MT8189_TYPE0_PIN(15, "GPIO15"), + MT8189_TYPE0_PIN(16, "GPIO16"), + MT8189_TYPE0_PIN(17, "GPIO17"), + MT8189_TYPE0_PIN(18, "GPIO18"), + MT8189_TYPE0_PIN(19, "GPIO19"), + MT8189_TYPE0_PIN(20, "GPIO20"), + MT8189_TYPE0_PIN(21, "GPIO21"), + MT8189_TYPE0_PIN(22, "GPIO22"), + MT8189_TYPE0_PIN(23, "GPIO23"), + MT8189_TYPE0_PIN(24, "GPIO24"), + MT8189_TYPE0_PIN(25, "GPIO25"), + MT8189_TYPE0_PIN(26, "GPIO26"), + MT8189_TYPE0_PIN(27, "GPIO27"), + MT8189_TYPE0_PIN(28, "GPIO28"), + MT8189_TYPE0_PIN(29, "GPIO29"), + MT8189_TYPE0_PIN(30, "GPIO30"), + MT8189_TYPE0_PIN(31, "GPIO31"), + MT8189_TYPE0_PIN(32, "GPIO32"), + MT8189_TYPE0_PIN(33, "GPIO33"), + MT8189_TYPE0_PIN(34, "GPIO34"), + MT8189_TYPE0_PIN(35, "GPIO35"), + MT8189_TYPE0_PIN(36, "GPIO36"), + MT8189_TYPE0_PIN(37, "GPIO37"), + MT8189_TYPE0_PIN(38, "GPIO38"), + MT8189_TYPE0_PIN(39, "GPIO39"), + MT8189_TYPE0_PIN(40, "GPIO40"), + MT8189_TYPE0_PIN(41, "GPIO41"), + MT8189_TYPE0_PIN(42, "GPIO42"), + MT8189_TYPE0_PIN(43, "GPIO43"), + MT8189_TYPE1_PIN(44, "GPIO44"), + MT8189_TYPE1_PIN(45, "GPIO45"), + MT8189_TYPE1_PIN(46, "GPIO46"), + MT8189_TYPE1_PIN(47, "GPIO47"), + MT8189_TYPE0_PIN(48, "GPIO48"), + MT8189_TYPE0_PIN(49, "GPIO49"), + MT8189_TYPE0_PIN(50, "GPIO50"), + MT8189_TYPE2_PIN(51, "GPIO51"), + MT8189_TYPE2_PIN(52, "GPIO52"), + MT8189_TYPE2_PIN(53, "GPIO53"), + MT8189_TYPE2_PIN(54, "GPIO54"), + MT8189_TYPE2_PIN(55, "GPIO55"), + MT8189_TYPE2_PIN(56, "GPIO56"), + MT8189_TYPE2_PIN(57, "GPIO57"), + MT8189_TYPE2_PIN(58, "GPIO58"), + MT8189_TYPE2_PIN(59, "GPIO59"), + MT8189_TYPE2_PIN(60, "GPIO60"), + MT8189_TYPE2_PIN(61, "GPIO61"), + MT8189_TYPE2_PIN(62, "GPIO62"), + MT8189_TYPE2_PIN(63, "GPIO63"), + MT8189_TYPE2_PIN(64, "GPIO64"), + MT8189_TYPE2_PIN(65, "GPIO65"), + MT8189_TYPE2_PIN(66, "GPIO66"), + MT8189_TYPE2_PIN(67, "GPIO67"), + MT8189_TYPE2_PIN(68, "GPIO68"), + MT8189_TYPE0_PIN(69, "GPIO69"), + MT8189_TYPE0_PIN(70, "GPIO70"), + MT8189_TYPE0_PIN(71, "GPIO71"), + MT8189_TYPE0_PIN(72, "GPIO72"), + MT8189_TYPE0_PIN(73, "GPIO73"), + MT8189_TYPE0_PIN(74, "GPIO74"), + MT8189_TYPE0_PIN(75, "GPIO75"), + MT8189_TYPE0_PIN(76, "GPIO76"), + MT8189_TYPE0_PIN(77, "GPIO77"), + MT8189_TYPE0_PIN(78, "GPIO78"), + MT8189_TYPE0_PIN(79, "GPIO79"), + MT8189_TYPE0_PIN(80, "GPIO80"), + MT8189_TYPE0_PIN(81, "GPIO81"), + MT8189_TYPE0_PIN(82, "GPIO82"), + MT8189_TYPE0_PIN(83, "GPIO83"), + MT8189_TYPE0_PIN(84, "GPIO84"), + MT8189_TYPE0_PIN(85, "GPIO85"), + MT8189_TYPE0_PIN(86, "GPIO86"), + MT8189_TYPE0_PIN(87, "GPIO87"), + MT8189_TYPE0_PIN(88, "GPIO88"), + MT8189_TYPE0_PIN(89, "GPIO89"), + MT8189_TYPE0_PIN(90, "GPIO90"), + MT8189_TYPE0_PIN(91, "GPIO91"), + MT8189_TYPE0_PIN(92, "GPIO92"), + MT8189_TYPE0_PIN(93, "GPIO93"), + MT8189_TYPE0_PIN(94, "GPIO94"), + MT8189_TYPE0_PIN(95, "GPIO95"), + MT8189_TYPE0_PIN(96, "GPIO96"), + MT8189_TYPE0_PIN(97, "GPIO97"), + MT8189_TYPE0_PIN(98, "GPIO98"), + MT8189_TYPE0_PIN(99, "GPIO99"), + MT8189_TYPE0_PIN(100, "GPIO100"), + MT8189_TYPE0_PIN(101, "GPIO101"), + MT8189_TYPE0_PIN(102, "GPIO102"), + MT8189_TYPE0_PIN(103, "GPIO103"), + MT8189_TYPE0_PIN(104, "GPIO104"), + MT8189_TYPE0_PIN(105, "GPIO105"), + MT8189_TYPE0_PIN(106, "GPIO106"), + MT8189_TYPE0_PIN(107, "GPIO107"), + MT8189_TYPE0_PIN(108, "GPIO108"), + MT8189_TYPE0_PIN(109, "GPIO109"), + MT8189_TYPE0_PIN(110, "GPIO110"), + MT8189_TYPE0_PIN(111, "GPIO111"), + MT8189_TYPE0_PIN(112, "GPIO112"), + MT8189_TYPE0_PIN(113, "GPIO113"), + MT8189_TYPE0_PIN(114, "GPIO114"), + MT8189_TYPE0_PIN(115, "GPIO115"), + MT8189_TYPE0_PIN(116, "GPIO116"), + MT8189_TYPE0_PIN(117, "GPIO117"), + MT8189_TYPE0_PIN(118, "GPIO118"), + MT8189_TYPE0_PIN(119, "GPIO119"), + MT8189_TYPE0_PIN(120, "GPIO120"), + MT8189_TYPE0_PIN(121, "GPIO121"), + MT8189_TYPE0_PIN(122, "GPIO122"), + MT8189_TYPE0_PIN(123, "GPIO123"), + MT8189_TYPE0_PIN(124, "GPIO124"), + MT8189_TYPE0_PIN(125, "GPIO125"), + MT8189_TYPE0_PIN(126, "GPIO126"), + MT8189_TYPE0_PIN(127, "GPIO127"), + MT8189_TYPE0_PIN(128, "GPIO128"), + MT8189_TYPE0_PIN(129, "GPIO129"), + MT8189_TYPE0_PIN(130, "GPIO130"), + MT8189_TYPE0_PIN(131, "GPIO131"), + MT8189_TYPE0_PIN(132, "GPIO132"), + MT8189_TYPE0_PIN(133, "GPIO133"), + MT8189_TYPE0_PIN(134, "GPIO134"), + MT8189_TYPE0_PIN(135, "GPIO135"), + MT8189_TYPE0_PIN(136, "GPIO136"), + MT8189_TYPE0_PIN(137, "GPIO137"), + MT8189_TYPE0_PIN(138, "GPIO138"), + MT8189_TYPE0_PIN(139, "GPIO139"), + MT8189_TYPE0_PIN(140, "GPIO140"), + MT8189_TYPE0_PIN(141, "GPIO141"), + MT8189_TYPE0_PIN(142, "GPIO142"), + MT8189_TYPE0_PIN(143, "GPIO143"), + MT8189_TYPE0_PIN(144, "GPIO144"), + MT8189_TYPE0_PIN(145, "GPIO145"), + MT8189_TYPE0_PIN(146, "GPIO146"), + MT8189_TYPE0_PIN(147, "GPIO147"), + MT8189_TYPE0_PIN(148, "GPIO148"), + MT8189_TYPE0_PIN(149, "GPIO149"), + MT8189_TYPE0_PIN(150, "GPIO150"), + MT8189_TYPE0_PIN(151, "GPIO151"), + MT8189_TYPE0_PIN(152, "GPIO152"), + MT8189_TYPE0_PIN(153, "GPIO153"), + MT8189_TYPE0_PIN(154, "GPIO154"), + MT8189_TYPE0_PIN(155, "GPIO155"), + MT8189_TYPE1_PIN(156, "GPIO156"), + MT8189_TYPE1_PIN(157, "GPIO157"), + MT8189_TYPE1_PIN(158, "GPIO158"), + MT8189_TYPE1_PIN(159, "GPIO159"), + MT8189_TYPE1_PIN(160, "GPIO160"), + MT8189_TYPE1_PIN(161, "GPIO161"), + MT8189_TYPE1_PIN(162, "GPIO162"), + MT8189_TYPE1_PIN(163, "GPIO163"), + MT8189_TYPE1_PIN(164, "GPIO164"), + MT8189_TYPE1_PIN(165, "GPIO165"), + MT8189_TYPE1_PIN(166, "GPIO166"), + MT8189_TYPE1_PIN(167, "GPIO167"), + MT8189_TYPE1_PIN(168, "GPIO168"), + MT8189_TYPE1_PIN(169, "GPIO169"), + MT8189_TYPE1_PIN(170, "GPIO170"), + MT8189_TYPE1_PIN(171, "GPIO171"), + MT8189_TYPE1_PIN(172, "GPIO172"), + MT8189_TYPE1_PIN(173, "GPIO173"), + MT8189_TYPE1_PIN(174, "GPIO174"), + MT8189_TYPE1_PIN(175, "GPIO175"), + MT8189_TYPE1_PIN(176, "GPIO176"), + MT8189_TYPE1_PIN(177, "GPIO177"), + MT8189_TYPE1_PIN(178, "GPIO178"), + MT8189_TYPE1_PIN(179, "GPIO179"), + MT8189_TYPE2_PIN(180, "GPIO180"), + MT8189_TYPE2_PIN(181, "GPIO181"), + MT8189_TYPE0_PIN(182, "GPIO182"), }; static const struct mtk_io_type_desc mt8189_io_type_desc[] = { [IO_TYPE_GRP0] = { .name = "mt8189", - .bias_set = mtk_pinconf_bias_set_v1, + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + .get_pinconf = mtk_pinconf_get_pu_pd, + }, + [IO_TYPE_GRP1] = { + .name = "MSDC", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + .get_pinconf = mtk_pinconf_get_pupd_r1_r0, + }, + [IO_TYPE_GRP2] = { + .name = "I2C", + .bias_set = mtk_pinconf_bias_set_pu_pd_rsel, .drive_set = mtk_pinconf_drive_set_v1, .input_enable = mtk_pinconf_input_enable_v1, + .get_pinconf = mtk_pinconf_get_pu_pd_rsel, }, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index d152e216634..cfffbaeef84 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -237,9 +237,39 @@ static int mtk_get_pin_io_type(struct udevice *dev, int pin, io_type->bias_set = priv->soc->io_type[io_n].bias_set; io_type->drive_set = priv->soc->io_type[io_n].drive_set; io_type->input_enable = priv->soc->io_type[io_n].input_enable; + io_type->get_pinconf = priv->soc->io_type[io_n].get_pinconf; return 0; } + +static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + struct mtk_io_type_desc io_type; + int err, pos; + + /* If we fail to get the type, then we just don't add any more info. */ + if (mtk_get_pin_io_type(dev, pin, &io_type)) + return 0; + + pos = snprintf(buf, size, " (%s)", io_type.name); + if (pos >= size) + return pos; + + if (io_type.get_pinconf) { + err = io_type.get_pinconf(dev, pin, buf + pos, size - pos); + if (err < 0) + return err; + + pos += err; + } + + return pos; +} +#else +static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + return 0; +} #endif static int mtk_get_groups_count(struct udevice *dev) @@ -270,12 +300,20 @@ static int mtk_get_pins_count(struct udevice *dev) static int mtk_get_pin_muxing(struct udevice *dev, unsigned int selector, char *buf, int size) { - int val, err; + int val, err, pos; + err = mtk_hw_get_value(dev, selector, PINCTRL_PIN_REG_MODE, &val); if (err) return err; - snprintf(buf, size, "Aux Func.%d", val); + pos = snprintf(buf, size, "Aux Func.%d", val); + if (pos >= size) + return 0; + + err = mtk_pinconf_get(dev, selector, buf + pos, size - pos); + if (err < 0) + return err; + return 0; } @@ -450,6 +488,20 @@ int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable, return 0; } +int mtk_pinconf_bias_set_pu_pd_rsel(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val) +{ + int err; + + /* val is expected to be one of MTK_PULL_SET_RSEL_XXX */ + + err = mtk_pinconf_bias_set_pu_pd(dev, pin, disable, pullup, val); + if (err) + return err; + + return mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_RSEL, val & 0x7); +} + int mtk_pinconf_bias_set(struct udevice *dev, u32 pin, u32 arg, u32 val) { int err; @@ -656,6 +708,55 @@ static int mtk_pinconf_group_set(struct udevice *dev, return 0; } + +int mtk_pinconf_get_pu_pd(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + int err, pu, pd; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_PU, &pu); + if (err) + return err; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_PD, &pd); + if (err) + return err; + + return snprintf(buf, size, " PU:%d PD:%d", pu, pd); +} + +int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + int err, r0, r1, pupd; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_PUPD, &pupd); + if (err) + return err; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_R1, &r1); + if (err) + return err; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_R0, &r0); + if (err) + return err; + + return snprintf(buf, size, " PUPD:%d R1:%d R0:%d", pupd, r1, r0); +} + +int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t size) +{ + int pos, err, rsel; + + pos = mtk_pinconf_get_pu_pd(dev, pin, buf, size); + if (pos < 0 || pos >= size) + return pos; + + err = mtk_hw_get_value(dev, pin, PINCTRL_PIN_REG_RSEL, &rsel); + if (err) + return err; + + return pos + snprintf(buf + pos, size - pos, " RSEL:%d", rsel); +} #endif static int mtk_pinctrl_pinmux_property_set(struct udevice *dev, u32 pinmux_group) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 58f13613633..bd17964090a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -67,6 +67,7 @@ enum { PINCTRL_PIN_REG_PUPD, PINCTRL_PIN_REG_R0, PINCTRL_PIN_REG_R1, + PINCTRL_PIN_REG_RSEL, PINCTRL_PIN_REG_MAX, }; @@ -203,6 +204,7 @@ struct mtk_io_type_desc { bool pullup, u32 val); int (*drive_set)(struct udevice *dev, u32 pin, u32 arg); int (*input_enable)(struct udevice *dev, u32 pin, u32 arg); + int (*get_pinconf)(struct udevice *dev, u32 pin, char *buf, size_t size); #endif }; @@ -253,6 +255,8 @@ int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin, bool disable, bool pullup, u32 val); int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable, bool pullup, u32 val); +int mtk_pinconf_bias_set_pu_pd_rsel(struct udevice *dev, u32 pin, bool disable, + bool pullup, u32 val); int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable, bool pullup, u32 val); int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable, @@ -260,6 +264,9 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable, int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg); int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg); int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg); +int mtk_pinconf_get_pu_pd(struct udevice *dev, u32 pin, char *buf, size_t size); +int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t size); +int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t size); #endif diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index 67114df6824..29cfdcaa7f8 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -1283,7 +1283,7 @@ static const struct udevice_id meson_g12a_pinctrl_match[] = { { }, }; -U_BOOT_DRIVER(meson_axg_pinctrl) = { +U_BOOT_DRIVER(meson_g12a_pinctrl) = { .name = "meson-g12a-pinctrl", .id = UCLASS_PINCTRL, .of_match = of_match_ptr(meson_g12a_pinctrl_match), diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c index 63d4f8ffeb5..fa31b573f31 100644 --- a/drivers/pinctrl/pinctrl-scmi.c +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -33,20 +33,6 @@ static const struct pinconf_param pinctrl_scmi_conf_params[] = { /* The SCMI spec also include "default", "pull-mode" and "input-value */ }; -static bool valid_selector(struct udevice *dev, enum select_type select_type, u32 selector) -{ - struct pinctrl_scmi_priv *priv = dev_get_priv(dev); - - if (select_type == SCMI_PIN) - return selector < priv->num_pins; - if (select_type == SCMI_GROUP) - return selector < priv->num_groups; - if (select_type == SCMI_FUNCTION) - return selector < priv->num_functions; - - return false; -} - static int pinctrl_scmi_get_pins_count(struct udevice *dev) { struct pinctrl_scmi_priv *priv = dev_get_priv(dev); @@ -98,6 +84,38 @@ static const char *pinctrl_scmi_get_function_name(struct udevice *dev, unsigned return (const char *)priv->function_info[selector].name; } +static int pinctrl_scmi_get_function_id(struct udevice *dev, const char *function) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + int i; + + if (!function) + return -EINVAL; + + for (i = 0; i < priv->num_functions; i++) { + if (strcmp(priv->function_info[i].name, function) == 0) + return i; + } + + return -EINVAL; +} + +static int pinctrl_scmi_get_group_id(struct udevice *dev, const char *group) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + int i; + + if (!group) + return -EINVAL; + + for (i = 0; i < priv->num_groups; i++) { + if (strcmp(priv->group_info[i].name, group) == 0) + return i; + } + + return -EINVAL; +} + static int pinctrl_scmi_pinmux_set(struct udevice *dev, u32 pin, u32 function) { struct pinctrl_scmi_priv *priv = dev_get_priv(dev); @@ -120,96 +138,35 @@ static int pinctrl_scmi_pinmux_group_set(struct udevice *dev, u32 group, u32 fun static int pinctrl_scmi_set_state(struct udevice *dev, struct udevice *config) { - struct pinctrl_scmi_priv *priv = dev_get_priv(dev); - /* batch the setup into 20 lines at a go (there are 5 u32s in a config) */ - const int batch_count = 20 * 5; - u32 prev_type = -1u; - u32 prev_selector; - u32 *configs; - const u32 *prop; - int offset, cnt, len; - int ret = 0; - - prop = dev_read_prop(config, "pinmux", &len); - if (!prop) - return 0; - - if (len % sizeof(u32) * 5) { - dev_err(dev, "invalid pin configuration: len=%d\n", len); - return -FDT_ERR_BADSTRUCTURE; - } - - configs = kcalloc(batch_count, sizeof(u32), GFP_KERNEL); - if (!configs) - return -ENOMEM; - - offset = 0; - cnt = 0; - while (offset + 4 < len / sizeof(u32)) { - u32 select_type = fdt32_to_cpu(prop[offset]); - u32 selector = fdt32_to_cpu(prop[offset + 1]); - u32 function = fdt32_to_cpu(prop[offset + 2]); - u32 config_type = fdt32_to_cpu(prop[offset + 3]); - u32 config_value = fdt32_to_cpu(prop[offset + 4]); - - if (select_type > SCMI_GROUP || - !valid_selector(dev, select_type, selector) || - (function != SCMI_PINCTRL_FUNCTION_NONE && - function > priv->num_functions)) { - dev_err(dev, "invalid pinctrl data (%u %u %u %u %u)\n", - select_type, selector, function, config_type, - config_value); - ret = -EINVAL; - goto free; - } + int function_id, group_id; + const char *function; + const char **groups; + int group_count; + int ret; + int i; - if (function != SCMI_PINCTRL_FUNCTION_NONE) { - if (cnt) { - ret = scmi_pinctrl_settings_configure(dev, - prev_type, - prev_selector, - cnt / 2, configs); - if (ret) - goto free; - prev_type = -1u; - cnt = 0; - } - scmi_pinctrl_set_function(dev, select_type, selector, function); - offset += 5; - continue; - } + ret = dev_read_string_index(config, "function", 0, &function); + if (ret) + return ret; - if (cnt == batch_count) - goto set; + function_id = pinctrl_scmi_get_function_id(dev, function); + if (function_id < 0) + return function_id; - if (prev_type == -1u) - goto store; + group_count = dev_read_string_list(config, "groups", &groups); + if (group_count < 0) + return group_count; - if (select_type == prev_type && selector == prev_selector) - goto store; -set: - ret = scmi_pinctrl_settings_configure(dev, prev_type, prev_selector, - cnt / 2, configs); + for (i = 0; i < group_count; i++) { + group_id = pinctrl_scmi_get_group_id(dev, groups[i]); + if (group_id < 0) + return group_id; + ret = pinctrl_scmi_pinmux_group_set(dev, group_id, function_id); if (ret) - goto free; - cnt = 0; -store: - prev_type = select_type; - prev_selector = selector; - configs[cnt++] = config_type; - configs[cnt++] = config_value; - offset += 5; + return ret; } - if (cnt) - ret = scmi_pinctrl_settings_configure(dev, prev_type, prev_selector, - cnt / 2, configs); -free: - kfree(configs); - if (ret) - dev_err(dev, "set_state() failed: %d\n", ret); - - return ret; + return 0; } static int get_pin_muxing(struct udevice *dev, unsigned int selector, diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index c32d590a7e0..b3727b917dc 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -182,8 +182,8 @@ static const struct udevice_id tegra_pinctrl_ids[] = { { }, }; -U_BOOT_DRIVER(tegra_pinctrl) = { - .name = "tegra_pinctrl", +U_BOOT_DRIVER(tegra20_pinctrl) = { + .name = "tegra20_pinctrl", .id = UCLASS_PINCTRL, .of_match = tegra_pinctrl_ids, .bind = tegra_pinctrl_bind, diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 4f39e46cebd..a4ee5f1335a 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -244,7 +244,7 @@ config DM_REGULATOR_QCOM_RPMH config DM_REGULATOR_QCOM_USB_VBUS bool "Enable driver model for Qualcomm USB vbus regulator" - depends on DM_REGULATOR + depends on DM_REGULATOR && DM_PMIC ---help--- Enable support for the Qualcomm USB Vbus regulator. The driver implements get/set api for the regulator to be used by u-boot. diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 8056f210abc..f07ae903a28 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -45,7 +45,7 @@ config REMOTEPROC_RENESAS_APMU select REMOTEPROC depends on ARCH_RENESAS && RCAR_GEN4 && DM && OF_CONTROL help - Say 'y' here to add support for Renesas R-Car Gen4 Cortex-A52 + Say 'y' here to add support for Renesas R-Car Gen4 Cortex-R52 processor via the remoteproc framework. config REMOTEPROC_SANDBOX diff --git a/drivers/reset/stm32/stm32-reset-mp1.c b/drivers/reset/stm32/stm32-reset-mp1.c index ce4532561e5..e7ac2c6f066 100644 --- a/drivers/reset/stm32/stm32-reset-mp1.c +++ b/drivers/reset/stm32/stm32-reset-mp1.c @@ -46,7 +46,7 @@ static int stm32_reset_probe(struct udevice *dev) return stm32_reset_core_probe(dev, &stm32mp1_reset_data); } -U_BOOT_DRIVER(stm32mp25_rcc_reset) = { +U_BOOT_DRIVER(stm32mp1_rcc_reset) = { .name = "stm32mp1_reset", .id = UCLASS_RESET, .probe = stm32_reset_probe, diff --git a/drivers/rtc/rv3028.c b/drivers/rtc/rv3028.c index b14d2a246ff..4e05ef8de2a 100644 --- a/drivers/rtc/rv3028.c +++ b/drivers/rtc/rv3028.c @@ -130,7 +130,6 @@ static int rv3028_rtc_get(struct udevice *dev, struct rtc_time *tm) static int rv3028_rtc_set(struct udevice *dev, const struct rtc_time *tm) { u8 regs[RTC_RV3028_LEN]; - u8 status; int ret; debug("%s: %4d-%02d-%02d (wday=%d( %2d:%02d:%02d\n", @@ -157,13 +156,7 @@ static int rv3028_rtc_set(struct udevice *dev, const struct rtc_time *tm) return ret; } - ret = dm_i2c_read(dev, RV3028_STATUS, &status, 1); - if (ret < 0) { - printf("%s: error reading RTC status: %x\n", __func__, ret); - return -EIO; - } - status |= RV3028_STATUS_PORF; - return dm_i2c_write(dev, RV3028_STATUS, &status, 1); + return dm_i2c_reg_clrset(dev, RV3028_STATUS, RV3028_STATUS_PORF, 0); } static int rv3028_rtc_reset(struct udevice *dev) diff --git a/drivers/scsi/scsi-uclass.c b/drivers/scsi/scsi-uclass.c index 3eb6069649f..39b4c7476d4 100644 --- a/drivers/scsi/scsi-uclass.c +++ b/drivers/scsi/scsi-uclass.c @@ -29,15 +29,9 @@ int scsi_get_blk_by_uuid(const char *uuid, struct blk_desc **blk_desc_ptr, struct disk_partition *part_info_ptr) { - static int is_scsi_scanned; struct blk_desc *blk; int i, ret; - if (!is_scsi_scanned) { - scsi_scan(false /* no verbose */); - is_scsi_scanned = 1; - } - for (i = 0; i < blk_find_max_devnum(UCLASS_SCSI) + 1; i++) { ret = blk_get_desc(UCLASS_SCSI, i, &blk); if (ret) @@ -50,7 +44,7 @@ int scsi_get_blk_by_uuid(const char *uuid, } } - return -1; + return -ENODEV; } int scsi_bus_reset(struct udevice *dev) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c86c883e0cb..5f8b98f0704 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -510,6 +510,14 @@ config DEBUG_UART_XTENSA_SEMIHOSTING start up driver model. The driver will be available until the real driver model serial is running. +config DEBUG_UART_GOLDFISH + bool "Goldfish TTY" + help + Select this to enable the debug UART using the Goldfish TTY driver. + This provides basic serial output from the console without needing to + start up driver model. The driver will be available until the real + driver model serial is running. + endchoice config DEBUG_UART_BASE diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 2f24f47badf..10271f46aa6 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -586,6 +586,7 @@ const struct dm_serial_ops ns16550_serial_ops = { .getinfo = ns16550_serial_getinfo, }; +#if CONFIG_IS_ENABLED(SERIAL_PRESENT) #if CONFIG_IS_ENABLED(OF_REAL) /* * Please consider existing compatible strings before adding a new @@ -603,8 +604,6 @@ static const struct udevice_id ns16550_serial_ids[] = { }; #endif /* OF_REAL */ -#if CONFIG_IS_ENABLED(SERIAL_PRESENT) - /* TODO([email protected]): Integrate this into a macro like CONFIG_IS_ENABLED */ #if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL) U_BOOT_DRIVER(ns16550_serial) = { diff --git a/drivers/serial/serial_goldfish.c b/drivers/serial/serial_goldfish.c index 4ac2cfb6231..91dc040fcf2 100644 --- a/drivers/serial/serial_goldfish.c +++ b/drivers/serial/serial_goldfish.c @@ -115,3 +115,21 @@ U_BOOT_DRIVER(serial_goldfish) = { .priv_auto = sizeof(struct goldfish_tty_priv), .flags = DM_FLAG_PRE_RELOC, }; + +#ifdef CONFIG_DEBUG_UART_GOLDFISH + +#include <debug_uart.h> + +static inline void _debug_uart_init(void) +{ +} + +static inline void _debug_uart_putc(int ch) +{ + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + __raw_writel(ch, base + GOLDFISH_TTY_PUT_CHAR); +} + +DEBUG_UART_FUNCS +#endif diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index bb5a2cb4d2c..3dca581f68f 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -212,7 +212,7 @@ static int msm_serial_setbrg(struct udevice *dev, int baud) ret = clk_set_rate(priv->se, clk_rate); if (ret < 0) { pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret); - return ret; + return 0; } geni_serial_baud(priv->base, clk_div, baud); @@ -517,13 +517,14 @@ static int msm_serial_probe(struct udevice *dev) u32 proto; struct clk *clk; - clk = devm_clk_get(dev, NULL); + clk = devm_clk_get_optional(dev, NULL); if (IS_ERR(clk)) - return PTR_ERR(clk); - priv->se = clk; + dev_dbg(dev, "Couldn't find UART clock: %ld", PTR_ERR(clk)); + else + priv->se = clk; /* Try enable clock */ - ret = clk_enable(clk); + clk_enable(clk); /* Check if firmware loading is needed (BT UART) */ proto = readl(priv->base + GENI_FW_REVISION_RO); @@ -547,10 +548,6 @@ static int msm_serial_probe(struct udevice *dev) if (ofnode_device_is_compatible(dev_ofnode(dev), "qcom,geni-uart")) return -ENOENT; - /* Now handle clock enable return value */ - if (ret) - return ret; - ret = geni_set_oversampling(dev); if (ret < 0) return ret; diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index 224d9cbf29d..8289336e08d 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -104,7 +104,7 @@ DEBUG_UART_FUNCS #if CONFIG_IS_ENABLED(DM_SERIAL) -#if CONFIG_IS_ENABLED(OF_REAL) +#if CONFIG_IS_ENABLED(OF_REAL) && CONFIG_IS_ENABLED(SERIAL_PRESENT) static int omap_serial_of_to_plat(struct udevice *dev) { struct ns16550_plat *plat = dev_get_plat(dev); diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 7ab62e0e90b..bc205234e24 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -59,7 +59,7 @@ static void sh_serial_init_generic(struct uart_port *port) sci_out(port, SCSPTR, 0x0003); #endif -#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_GEN3) || IS_ENABLED(CONFIG_RCAR_GEN4) +#if IS_ENABLED(CONFIG_RCAR_GEN2) || IS_ENABLED(CONFIG_RCAR_GEN3) || IS_ENABLED(CONFIG_RCAR_GEN4) || IS_ENABLED(CONFIG_RCAR_GEN5) if (port->type == PORT_HSCIF) sci_out(port, HSSRR, HSSRR_SRE | HSSRR_SRCYC8); #endif diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index dce61f26229..0b821cc6f9d 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -261,8 +261,8 @@ static struct tcs_group *get_tcs_for_msg(struct rsc_drv *drv, * just always used the first active TCS. */ if (msg->state != RPMH_ACTIVE_ONLY_STATE) { - log_err("WARN: only ACTIVE_ONLY state supported\n"); - return ERR_PTR(-EINVAL); + log_debug("WARN: only ACTIVE_ONLY state supported\n"); + return NULL; } return &drv->tcs[ACTIVE_TCS]; @@ -390,8 +390,8 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg) u32 val; tcs = get_tcs_for_msg(drv, msg); - if (IS_ERR(tcs)) - return PTR_ERR(tcs); + if (IS_ERR_OR_NULL(tcs)) + return 0; /* U-Boot is single-threaded, always use the first TCS as we'll never conflict */ tcs_id = tcs->offset; diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c index 8c222324c66..b55e23c4417 100644 --- a/drivers/soc/qcom/rpmh.c +++ b/drivers/soc/qcom/rpmh.c @@ -60,8 +60,8 @@ static int __rpmh_write(const struct udevice *dev, enum rpmh_state state, struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr(dev); if (state != RPMH_ACTIVE_ONLY_STATE) { - log_err("only ACTIVE_ONLY state supported\n"); - return -EINVAL; + log_debug("WARN: Only ACTIVE_ONLY state supported\n"); + return 0; } return rpmh_rsc_send_data(ctrlr_to_drv(ctrlr), &rpm_msg->msg); diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index b97cd443c60..4abc73013eb 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -71,6 +71,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_EG_LR, }, { + .id = 0x0468A093, + .device = 1, + .variants = ZYNQMP_VARIANT_EG_LR, + }, + { .id = 0x04711093, .device = 2, .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, @@ -209,6 +214,16 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_DR, }, { + .id = 0x047F9093, + .device = 58, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x047FC093, + .device = 59, + .variants = ZYNQMP_VARIANT_DR, + }, + { .id = 0x046d0093, .device = 67, .variants = ZYNQMP_VARIANT_DR, @@ -219,6 +234,36 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_DR_SE, }, { + .id = 0x046D1093, + .device = 65, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x046D2093, + .device = 55, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x046D3093, + .device = 57, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x046D4093, + .device = 42, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x046D5093, + .device = 63, + .variants = ZYNQMP_VARIANT_DR, + }, + { + .id = 0x046D6093, + .device = 64, + .variants = ZYNQMP_VARIANT_DR, + }, + { .id = 0x04712093, .device = 24, .variants = 0, diff --git a/drivers/spi/cadence_xspi.c b/drivers/spi/cadence_xspi.c index 717f226b709..8a894025d02 100644 --- a/drivers/spi/cadence_xspi.c +++ b/drivers/spi/cadence_xspi.c @@ -441,6 +441,7 @@ static const struct udevice_id cdns_xspi_of_match[] = { U_BOOT_DRIVER(cadence_xspi) = { .name = CDNS_XSPI_NAME, .id = UCLASS_SPI, + .plat_auto = sizeof(struct cdns_xspi_plat), .of_match = cdns_xspi_of_match, .ops = &cdns_xspi_ops, .probe = cdns_xspi_probe, diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 095cbea0fca..bb5ab26685c 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -347,8 +347,8 @@ static const struct udevice_id mvebu_spi_ids[] = { { } }; -U_BOOT_DRIVER(mvebu_spi) = { - .name = "mvebu_spi", +U_BOOT_DRIVER(kirkwood_spi) = { + .name = "kirkwood_spi", .id = UCLASS_SPI, .of_match = mvebu_spi_ids, .ops = &mvebu_spi_ops, diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index 79836d7e271..370a52a90b3 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -307,8 +307,8 @@ static const struct udevice_id mvebu_spi_ids[] = { { } }; -U_BOOT_DRIVER(mvebu_spi) = { - .name = "mvebu_spi", +U_BOOT_DRIVER(mvebu_a3700_spi) = { + .name = "mvebu_a3700_spi", .id = UCLASS_SPI, .of_match = mvebu_spi_ids, .ops = &mvebu_spi_ops, diff --git a/drivers/sysreset/sysreset_socfpga_soc64.c b/drivers/sysreset/sysreset_socfpga_soc64.c index 6ce30d9eaf0..e1267ac118a 100644 --- a/drivers/sysreset/sysreset_socfpga_soc64.c +++ b/drivers/sysreset/sysreset_socfpga_soc64.c @@ -80,7 +80,7 @@ static struct sysreset_ops socfpga_sysreset = { .request = socfpga_sysreset_request, }; -U_BOOT_DRIVER(sysreset_socfpga) = { +U_BOOT_DRIVER(sysreset_socfpga_soc64) = { .id = UCLASS_SYSRESET, .name = "socfpga_sysreset", .ops = &socfpga_sysreset, diff --git a/drivers/ufs/ufs-mediatek.c b/drivers/ufs/ufs-mediatek.c index e860d765eea..268627d5863 100644 --- a/drivers/ufs/ufs-mediatek.c +++ b/drivers/ufs/ufs-mediatek.c @@ -182,19 +182,15 @@ static int ufs_mtk_bind_mphy(struct ufs_hba *hba) struct ufs_mtk_host *host = dev_get_priv(hba->dev); int err = 0; - err = generic_phy_get_by_index(hba->dev, 0, host->mphy); + err = generic_phy_get_by_index(hba->dev, 0, &host->mphy); - if (IS_ERR(host->mphy)) { - err = PTR_ERR(host->mphy); - if (err != -ENODEV) { - dev_info(hba->dev, "%s: Could NOT get a valid PHY %d\n", __func__, - err); - } + if (err) { + if (err == -ENOENT) + return 0; /* no PHY, nothing to do */ + dev_err(hba->dev, "Failed to get PHY: %d.\n", err); + return err; } - if (err) - host->mphy = NULL; - return err; } @@ -321,19 +317,35 @@ static int ufs_mtk_init(struct ufs_hba *hba) ufs_mtk_init_reset(hba); - // TODO: Clocking + err = clk_get_bulk(hba->dev, &priv->clks); + if (err) { + dev_err(hba->dev, "failed to initialize clocks, err:%d\n", err); + return err; + } + + err = clk_enable_bulk(&priv->clks); + if (err) { + dev_err(hba->dev, "failed to enable clocks, err:%d\n", err); + goto err_clk_enable; + } - err = generic_phy_power_on(priv->mphy); + err = generic_phy_power_on(&priv->mphy); if (err) { dev_err(hba->dev, "%s: phy init failed, err = %d\n", __func__, err); - return err; + goto err_phy_power_on; } ufs_mtk_setup_ref_clk(hba, true); ufs_mtk_get_hw_ip_version(hba); return 0; + +err_phy_power_on: + clk_disable_bulk(&priv->clks); +err_clk_enable: + clk_release_bulk(&priv->clks); + return err; } static int ufs_mtk_device_reset(struct ufs_hba *hba) @@ -383,7 +395,9 @@ static int ufs_mtk_probe(struct udevice *dev) static const struct udevice_id ufs_mtk_ids[] = { { .compatible = "mediatek,mt6878-ufshci" }, - {}, + { .compatible = "mediatek,mt8183-ufshci" }, + { .compatible = "mediatek,mt8195-ufshci" }, + { } }; U_BOOT_DRIVER(mediatek_ufshci) = { diff --git a/drivers/ufs/ufs-mediatek.h b/drivers/ufs/ufs-mediatek.h index 11a83d34c5b..0ffd0483eff 100644 --- a/drivers/ufs/ufs-mediatek.h +++ b/drivers/ufs/ufs-mediatek.h @@ -154,7 +154,7 @@ struct ufs_mtk_mcq_intr_info { }; struct ufs_mtk_host { - struct phy *mphy; + struct phy mphy; struct reset_ctl *unipro_reset; struct reset_ctl *crypto_reset; struct reset_ctl *hci_reset; diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c index bb997aace8f..81fd431f951 100644 --- a/drivers/ufs/ufs-uclass.c +++ b/drivers/ufs/ufs-uclass.c @@ -19,6 +19,7 @@ #include <dm/device-internal.h> #include <malloc.h> #include <hexdump.h> +#include <phys2bus.h> #include <scsi.h> #include <ufs.h> #include <asm/io.h> @@ -466,13 +467,13 @@ static int ufshcd_make_hba_operational(struct ufs_hba *hba) ufshcd_disable_intr_aggr(hba); /* Configure UTRL and UTMRL base address registers */ - ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl), + ufshcd_writel(hba, lower_32_bits(dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->utrdl))), REG_UTP_TRANSFER_REQ_LIST_BASE_L); - ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl), + ufshcd_writel(hba, upper_32_bits(dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->utrdl))), REG_UTP_TRANSFER_REQ_LIST_BASE_H); - ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl), + ufshcd_writel(hba, lower_32_bits(dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->utmrdl))), REG_UTP_TASK_REQ_LIST_BASE_L); - ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl), + ufshcd_writel(hba, upper_32_bits(dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->utmrdl))), REG_UTP_TASK_REQ_LIST_BASE_H); /* @@ -660,7 +661,7 @@ static void ufshcd_host_memory_configure(struct ufs_hba *hba) u16 prdt_offset; utrdlp = hba->utrdl; - cmd_desc_dma_addr = (dma_addr_t)hba->ucdl; + cmd_desc_dma_addr = dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)(hba->ucdl)); utrdlp->command_desc_base_addr_lo = cpu_to_le32(lower_32_bits(cmd_desc_dma_addr)); @@ -1612,12 +1613,15 @@ void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba, ufshcd_cache_flush(hba->ucd_rsp_ptr, sizeof(*hba->ucd_rsp_ptr)); } -static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry, +static inline void prepare_prdt_desc(struct ufs_hba *hba, + struct ufshcd_sg_entry *entry, unsigned char *buf, ulong len) { + dma_addr_t da = dev_phys_to_bus(hba->dev, (phys_addr_t)(uintptr_t)buf); + entry->size = cpu_to_le32(len) | GENMASK(1, 0); - entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf)); - entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf)); + entry->base_addr = cpu_to_le32(lower_32_bits(da)); + entry->upper_addr = cpu_to_le32(upper_32_bits(da)); } static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) @@ -1639,13 +1643,13 @@ static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb) buf = pccb->pdata; i = table_length; while (--i) { - prepare_prdt_desc(&prd_table[table_length - i - 1], buf, + prepare_prdt_desc(hba, &prd_table[table_length - i - 1], buf, MAX_PRDT_ENTRY - 1); buf += MAX_PRDT_ENTRY; datalen -= MAX_PRDT_ENTRY; } - prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1); + prepare_prdt_desc(hba, &prd_table[table_length - i - 1], buf, datalen - 1); req_desc->prd_table_length = table_length; ufshcd_cache_flush(prd_table, sizeof(*prd_table) * table_length); diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index 10bc4cabed4..4434dc15bec 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -392,52 +392,6 @@ static const struct udevice_id cdns3_ids[] = { { }, }; -/* - * The VBUS Valid Bit in the OTG Status register can be used to determine - * the role. When VBUS Valid is set, it indicates that a USB Host is supplying - * power, so the Controller should assume the PERIPHERAL role. If it isn't set, - * it indicates the absence of a USB Host, so the Controller should assume the - * HOST role. If the OTG Status register is inaccessible, return an error. - */ -static int cdns3_get_otg_mode(struct udevice *parent, enum usb_dr_mode *mode) -{ - /* Create a temporary child device for using devfdt_remap_addr_name() */ - struct udevice child = { - .parent = parent, - }; - struct cdns3 cdns, *cdnsp; - void __iomem *otg_regs; - - dev_set_ofnode(&child, ofnode_first_subnode(dev_ofnode(parent))); - otg_regs = devfdt_remap_addr_name(&child, "otg"); - if (!otg_regs) { - dev_err(parent, "failed to get otg registers for child node\n"); - return -ENXIO; - } - - /* - * As mentioned in drivers/usb/cdns3/drd.c, there are two versions - * of the Controller. The following logic detects the version of the - * Controller and interprets the register layout accordingly. - */ - cdnsp = &cdns; - cdnsp->otg_v0_regs = otg_regs; - if (!readl(&cdnsp->otg_v0_regs->cmd)) { - cdnsp->otg_regs = otg_regs; - } else { - cdnsp->otg_v1_regs = otg_regs; - cdnsp->otg_regs = (void *)&cdnsp->otg_v1_regs->cmd; - } - - /* Use VBUS Valid to determine role */ - if (readl(&cdnsp->otg_regs->sts) & OTGSTS_VBUS_VALID) - *mode = USB_DR_MODE_PERIPHERAL; - else - *mode = USB_DR_MODE_HOST; - - return 0; -} - int cdns3_bind(struct udevice *parent) { enum usb_dr_mode dr_mode; @@ -459,13 +413,6 @@ int cdns3_bind(struct udevice *parent) if (dr_mode == USB_DR_MODE_UNKNOWN) dr_mode = usb_get_dr_mode(dev_ofnode(parent)); - /* Use VBUS Valid to determine role */ - if (dr_mode == USB_DR_MODE_OTG) { - ret = cdns3_get_otg_mode(parent, &dr_mode); - if (ret < 0) - return ret; - } - switch (dr_mode) { #if defined(CONFIG_SPL_USB_HOST) || \ (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST)) diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c index 0ca40a5cc8d..cbb13342343 100644 --- a/drivers/usb/cdns3/drd.c +++ b/drivers/usb/cdns3/drd.c @@ -301,17 +301,6 @@ int cdns3_drd_init(struct cdns3 *cdns) cdns->dr_mode = USB_DR_MODE_PERIPHERAL; } - /* - * In the absence of STRAP configuration, use VBUS Valid to - * determine the appropriate role to be assigned to dr_mode. - */ - if (cdns->dr_mode == USB_DR_MODE_OTG) { - if (cdns3_get_vbus(cdns)) - cdns->dr_mode = USB_DR_MODE_PERIPHERAL; - else - cdns->dr_mode = USB_DR_MODE_HOST; - } - state = readl(&cdns->otg_regs->sts); if (OTGSTS_OTG_NRDY(state) != 0) { dev_err(cdns->dev, "Cadence USB3 OTG device not ready\n"); diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 6f22b9232ba..65c4d1a4e6f 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -206,6 +206,7 @@ static void dwc3_free_one_event_buffer(struct dwc3 *dwc, struct dwc3_event_buffer *evt) { dma_free_coherent(evt->buf); + free(evt); } /** @@ -252,6 +253,8 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc) if (evt) dwc3_free_one_event_buffer(dwc, evt); } + + free(dwc->ev_buffs); } /** diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 41d15996e5b..49e9c3fa0e9 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -533,7 +533,7 @@ static const struct udevice_id dwc3_meson_g12a_ids[] = { { } }; -U_BOOT_DRIVER(dwc3_generic_wrapper) = { +U_BOOT_DRIVER(dwc3_meson_g12a) = { .name = "dwc3-meson-g12a", .id = UCLASS_SIMPLE_BUS, .of_match = dwc3_meson_g12a_ids, diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index 5fb9b477ada..0edf41a4720 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -430,7 +430,7 @@ static const struct udevice_id dwc3_meson_gxl_ids[] = { { } }; -U_BOOT_DRIVER(dwc3_generic_wrapper) = { +U_BOOT_DRIVER(dwc3_meson_gxl) = { .name = "dwc3-meson-gxl", .id = UCLASS_SIMPLE_BUS, .of_match = dwc3_meson_gxl_ids, diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index e1fc04efd2e..ec21b7c6246 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -249,7 +249,7 @@ static const struct udevice_id ehci_usb_ids[] = { { } }; -U_BOOT_DRIVER(usb_ehci) = { +U_BOOT_DRIVER(ehci_exynos) = { .name = "ehci_exynos", .id = UCLASS_USB, .of_match = ehci_usb_ids, diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index 8aeb6a91556..a58eff7cb9c 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -117,7 +117,7 @@ void ci_init_after_reset(struct ehci_ctrl *ctrl) } #endif -U_BOOT_DRIVER(usb_ehci) = { +U_BOOT_DRIVER(ehci_msm) = { .name = "ehci_msm", .id = UCLASS_USB, .of_to_plat = ehci_usb_of_to_plat, diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 89b87886da1..c1f76752cb1 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -969,7 +969,7 @@ static const struct udevice_id ehci_usb_ids[] = { { } }; -U_BOOT_DRIVER(usb_ehci) = { +U_BOOT_DRIVER(ehci_tegra) = { .name = "ehci_tegra", .id = UCLASS_USB, .of_match = ehci_usb_ids, diff --git a/drivers/usb/host/ehci-vf.c b/drivers/usb/host/ehci-vf.c index 5afe28ea303..96d1363a76e 100644 --- a/drivers/usb/host/ehci-vf.c +++ b/drivers/usb/host/ehci-vf.c @@ -344,7 +344,7 @@ static const struct udevice_id vf_usb_ids[] = { { } }; -U_BOOT_DRIVER(usb_ehci) = { +U_BOOT_DRIVER(ehci_vf) = { .name = "ehci_vf", .id = UCLASS_USB, .of_match = vf_usb_ids, diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c index d321d147c2f..a36950082af 100644 --- a/drivers/usb/host/ohci-da8xx.c +++ b/drivers/usb/host/ohci-da8xx.c @@ -165,7 +165,7 @@ static const struct udevice_id da8xx_ohci_ids[] = { { } }; -U_BOOT_DRIVER(ohci_generic) = { +U_BOOT_DRIVER(ohci_da8xx) = { .name = "ohci-da8xx", .id = UCLASS_USB, .of_match = da8xx_ohci_ids, diff --git a/drivers/usb/musb-new/pic32.c b/drivers/usb/musb-new/pic32.c index 0b25e5893b3..b878e979d93 100644 --- a/drivers/usb/musb-new/pic32.c +++ b/drivers/usb/musb-new/pic32.c @@ -279,7 +279,7 @@ static const struct udevice_id pic32_musb_ids[] = { { } }; -U_BOOT_DRIVER(usb_musb) = { +U_BOOT_DRIVER(musb_pic32) = { .name = "pic32-musb", .id = UCLASS_USB, .of_match = pic32_musb_ids, diff --git a/drivers/usb/musb-new/sc5xx.c b/drivers/usb/musb-new/sc5xx.c index 991846818a2..b1765abe827 100644 --- a/drivers/usb/musb-new/sc5xx.c +++ b/drivers/usb/musb-new/sc5xx.c @@ -188,7 +188,7 @@ static const struct udevice_id sc5xx_musb_ids[] = { { } }; -U_BOOT_DRIVER(usb_musb) = { +U_BOOT_DRIVER(musb_sc5xx) = { .name = "sc5xx-musb", .id = UCLASS_USB, .of_match = sc5xx_musb_ids, diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index b577ba41878..0747f025f2a 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -545,7 +545,7 @@ static const struct udevice_id sunxi_musb_ids[] = { { } }; -U_BOOT_DRIVER(usb_musb) = { +U_BOOT_DRIVER(musb_sunxi) = { .name = "sunxi-musb", #ifdef CONFIG_USB_MUSB_HOST .id = UCLASS_USB, diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 984768ea156..dbc3018d716 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -24,7 +24,7 @@ obj-$(CONFIG_$(PHASE_)PANEL) += panel-uclass.o obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o obj-$(CONFIG_$(PHASE_)SIMPLE_PANEL) += simple_panel.o -obj-$(CONFIG_VIDEO_LOGO) += u_boot_logo.o +obj-$(CONFIG_VIDEO_LOGO) += u_boot_logo.bmp.o obj-$(CONFIG_$(PHASE_)BMP) += bmp.o endif diff --git a/drivers/video/fonts/Makefile b/drivers/video/fonts/Makefile index 1111f92a2c6..4d32fa43994 100644 --- a/drivers/video/fonts/Makefile +++ b/drivers/video/fonts/Makefile @@ -3,8 +3,8 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, [email protected]. -obj-$(CONFIG_CONSOLE_TRUETYPE_NIMBUS) += nimbus_sans_l_regular.o -obj-$(CONFIG_CONSOLE_TRUETYPE_ANKACODER) += ankacoder_c75_r.o -obj-$(CONFIG_CONSOLE_TRUETYPE_RUFSCRIPT) += rufscript010.o -obj-$(CONFIG_CONSOLE_TRUETYPE_CANTORAONE) += cantoraone_regular.o -obj-$(CONFIG_CONSOLE_TRUETYPE_DEJAVU) += dejavu_mono.o +obj-$(CONFIG_CONSOLE_TRUETYPE_NIMBUS) += nimbus_sans_l_regular.ttf.o +obj-$(CONFIG_CONSOLE_TRUETYPE_ANKACODER) += ankacoder_c75_r.ttf.o +obj-$(CONFIG_CONSOLE_TRUETYPE_RUFSCRIPT) += rufscript010.ttf.o +obj-$(CONFIG_CONSOLE_TRUETYPE_CANTORAONE) += cantoraone_regular.ttf.o +obj-$(CONFIG_CONSOLE_TRUETYPE_DEJAVU) += dejavu_mono.ttf.o diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index 850fe310754..574ba8c6957 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -177,8 +177,8 @@ static const struct udevice_id rk_mipi_dsi_ids[] = { { } }; -U_BOOT_DRIVER(rk_mipi_dsi) = { - .name = "rk_mipi_dsi", +U_BOOT_DRIVER(rk3288_mipi_dsi) = { + .name = "rk3288_mipi_dsi", .id = UCLASS_DISPLAY, .of_match = rk_mipi_dsi_ids, .of_to_plat = rk_mipi_of_to_plat, diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index 57e36eed6a9..68316df871c 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -168,8 +168,8 @@ static const struct udevice_id rk_mipi_dsi_ids[] = { { } }; -U_BOOT_DRIVER(rk_mipi_dsi) = { - .name = "rk_mipi_dsi", +U_BOOT_DRIVER(rk3399_mipi_dsi) = { + .name = "rk3399_mipi_dsi", .id = UCLASS_DISPLAY, .of_match = rk_mipi_dsi_ids, .of_to_plat = rk_mipi_of_to_plat, diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 1cd737aca24..62afe609ec0 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -354,7 +354,7 @@ static int virtio_mmio_probe(struct udevice *udev) magic = readl(priv->base + VIRTIO_MMIO_MAGIC_VALUE); if (magic != ('v' | 'i' << 8 | 'r' << 16 | 't' << 24)) { debug("(%s): wrong magic value 0x%08x!\n", udev->name, magic); - return 0; + return -ENODEV; } /* Check device version */ @@ -362,7 +362,7 @@ static int virtio_mmio_probe(struct udevice *udev) if (priv->version < 1 || priv->version > 2) { debug("(%s): version %d not supported!\n", udev->name, priv->version); - return 0; + return -ENXIO; } /* Check device ID */ @@ -372,7 +372,7 @@ static int virtio_mmio_probe(struct udevice *udev) * virtio-mmio device with an ID 0 is a (dummy) placeholder * with no function. End probing now with no error reported. */ - return 0; + return -ENODEV; } uc_priv->vendor = readl(priv->base + VIRTIO_MMIO_VENDOR_ID); diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 35ae7d106b1..416d29d256a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -16,6 +16,7 @@ config WATCHDOG_AUTOSTART depends on WDT default n if ARCH_SUNXI default n if ARCH_STM32MP + default n if ARCH_SNAPDRAGON default y help Automatically start watchdog timer and start servicing it during diff --git a/drivers/watchdog/arm_smc_wdt.c b/drivers/watchdog/arm_smc_wdt.c index f6854aa9ac9..151dc42d116 100644 --- a/drivers/watchdog/arm_smc_wdt.c +++ b/drivers/watchdog/arm_smc_wdt.c @@ -130,7 +130,7 @@ static const struct udevice_id smcwd_dt_ids[] = { {} }; -U_BOOT_DRIVER(wdt_sandbox) = { +U_BOOT_DRIVER(arm_smc_wdt) = { .name = "smcwd", .id = UCLASS_WDT, .of_match = smcwd_dt_ids, diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c index e4ebb1f31d4..a8d7e7a7950 100644 --- a/drivers/watchdog/qcom-wdt.c +++ b/drivers/watchdog/qcom-wdt.c @@ -129,7 +129,7 @@ static int qcom_wdt_probe(struct udevice *dev) wdt->clk_rate = (ulong)rate; - return 0; + return qcom_wdt_stop(dev); } static const struct wdt_ops qcom_wdt_ops = { |