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-rw-r--r--drivers/mtd/nand/raw/am335x_spl_bch.c12
-rw-r--r--drivers/mtd/nand/raw/atmel_nand.c40
-rw-r--r--drivers/mtd/nand/raw/davinci_nand.c14
-rw-r--r--drivers/mtd/nand/raw/denali_spl.c4
-rw-r--r--drivers/mtd/nand/raw/fsl_elbc_nand.c6
-rw-r--r--drivers/mtd/nand/raw/fsl_elbc_spl.c12
-rw-r--r--drivers/mtd/nand/raw/fsl_ifc_nand.c6
-rw-r--r--drivers/mtd/nand/raw/fsl_ifc_spl.c20
-rw-r--r--drivers/mtd/nand/raw/fsmc_nand.c2
-rw-r--r--drivers/mtd/nand/raw/kmeter1_nand.c4
-rw-r--r--drivers/mtd/nand/raw/lpc32xx_nand_slc.c22
-rw-r--r--drivers/mtd/nand/raw/mxc_nand.c6
-rw-r--r--drivers/mtd/nand/raw/mxc_nand_spl.c8
-rw-r--r--drivers/mtd/nand/raw/nand.c6
-rw-r--r--drivers/mtd/nand/raw/nand_spl_load.c6
-rw-r--r--drivers/mtd/nand/raw/nand_spl_simple.c16
-rw-r--r--drivers/mtd/nand/raw/omap_gpmc.c2
-rw-r--r--drivers/mtd/nand/raw/vf610_nfc.c2
18 files changed, 94 insertions, 94 deletions
diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c
index 83590a63cca..6ab3f1f42c5 100644
--- a/drivers/mtd/nand/raw/am335x_spl_bch.c
+++ b/drivers/mtd/nand/raw/am335x_spl_bch.c
@@ -16,13 +16,13 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+ CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
/*
@@ -155,8 +155,8 @@ static int nand_read_page(int block, int page, void *dst)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
uint32_t data_pos = 0;
@@ -207,7 +207,7 @@ void nand_init(void)
*/
mtd = nand_to_mtd(&nand_chip);
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
- (void __iomem *)CONFIG_SYS_NAND_BASE;
+ (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)
diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c
index a541af6db4a..9fbb0b57cf1 100644
--- a/drivers/mtd/nand/raw/atmel_nand.c
+++ b/drivers/mtd/nand/raw/atmel_nand.c
@@ -1227,16 +1227,16 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
- | CONFIG_SYS_NAND_MASK_CLE);
+ IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE
+ | CFG_SYS_NAND_MASK_CLE);
if (ctrl & NAND_CLE)
- IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
+ IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE;
if (ctrl & NAND_ALE)
- IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
+ IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE;
-#ifdef CONFIG_SYS_NAND_ENABLE_PIN
- at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
+#ifdef CFG_SYS_NAND_ENABLE_PIN
+ at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN,
!(ctrl & NAND_NCE));
#endif
this->IO_ADDR_W = (void *) IO_ADDR_W;
@@ -1246,10 +1246,10 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
writeb(cmd, this->IO_ADDR_W);
}
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
static int at91_nand_ready(struct mtd_info *mtd)
{
- return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
+ return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN);
}
#endif
@@ -1314,10 +1314,10 @@ static int nand_is_bad_block(int block)
}
#ifdef CONFIG_SPL_NAND_ECC
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+ CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
static int nand_read_page(int block, int page, void *dst)
{
@@ -1325,8 +1325,8 @@ static int nand_read_page(int block, int page, void *dst)
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
int i;
uint8_t *p = dst;
@@ -1415,7 +1415,7 @@ int board_nand_init(struct nand_chip *nand)
nand->read_buf = nand_read_buf;
#endif
nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#else
nand->dev_ready = at91_nand_wait_ready;
@@ -1439,8 +1439,8 @@ void nand_init(void)
mtd = nand_to_mtd(&nand_chip);
mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
- nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
- nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+ nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#ifdef CONFIG_SPL_NAND_ECC
@@ -1464,11 +1464,11 @@ void nand_deselect(void)
#else
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
int atmel_nand_chip_init(int devnum, ulong base_addr)
{
@@ -1487,7 +1487,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
nand->options = NAND_BUSWIDTH_16;
#endif
nand->cmd_ctrl = at91_nand_hwcontrol;
-#ifdef CONFIG_SYS_NAND_READY_PIN
+#ifdef CFG_SYS_NAND_READY_PIN
nand->dev_ready = at91_nand_ready;
#endif
nand->chip_delay = 75;
diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
index 54aed136388..e4e144bd7c8 100644
--- a/drivers/mtd/nand/raw/davinci_nand.c
+++ b/drivers/mtd/nand/raw/davinci_nand.c
@@ -170,7 +170,7 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
u_int32_t ecc = 0;
ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
- CONFIG_SYS_NAND_CS - 2]));
+ CFG_SYS_NAND_CS - 2]));
return ecc;
}
@@ -183,8 +183,8 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
nand_davinci_readecc(mtd);
val = __raw_readl(&davinci_emif_regs->nandfcr);
- val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
- val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS);
__raw_writel(val, &davinci_emif_regs->nandfcr);
}
@@ -486,8 +486,8 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
*/
val = __raw_readl(&davinci_emif_regs->nandfcr);
val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
- val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
- val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS);
+ val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS);
val |= DAVINCI_NANDFCR_4BIT_ECC_START;
__raw_writel(val, &davinci_emif_regs->nandfcr);
break;
@@ -794,8 +794,8 @@ static int davinci_nand_probe(struct udevice *dev)
struct mtd_info *mtd = nand_to_mtd(nand);
int ret;
- nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
- nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE;
+ nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE;
davinci_nand_init(nand);
diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c
index f72142817e7..690279c9976 100644
--- a/drivers/mtd/nand/raw/denali_spl.c
+++ b/drivers/mtd/nand/raw/denali_spl.c
@@ -25,9 +25,9 @@
#define BANK(x) ((x) << 24)
static void __iomem *denali_flash_mem =
- (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+ (void __iomem *)CFG_SYS_NAND_DATA_BASE;
static void __iomem *denali_flash_reg =
- (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+ (void __iomem *)CFG_SYS_NAND_REGS_BASE;
static const int flash_bank;
static int page_size, oob_size, pages_per_block;
diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
index 4f0acd7c89b..7853c3f74e2 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
@@ -819,12 +819,12 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev)
#ifndef CONFIG_NAND_FSL_ELBC_DT
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
- CONFIG_SYS_NAND_BASE_LIST;
+ CFG_SYS_NAND_BASE_LIST;
void board_nand_init(void)
{
diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c
index e55b40f8f13..26aaab08e89 100644
--- a/drivers/mtd/nand/raw/fsl_elbc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c
@@ -46,8 +46,8 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
#endif
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
- uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
- const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
+ uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
+ const int large = CFG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
const int block_shift = large ? 17 : 14;
const int block_size = 1 << block_shift;
const int page_size = large ? 2048 : 512;
@@ -143,8 +143,8 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -161,13 +161,13 @@ void nand_boot(void)
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
- flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+ flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
#endif
puts("transfering control\n");
/*
* Jump to U-Boot image
*/
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
(*uboot)();
}
diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index e5ff937872e..59de3256405 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -1053,12 +1053,12 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
return 0;
}
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
- CONFIG_SYS_NAND_BASE_LIST;
+ CFG_SYS_NAND_BASE_LIST;
void board_nand_init(void)
{
diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index 4d11922a650..7d4b77dd11d 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c
@@ -110,7 +110,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
{
struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
struct fsl_ifc_runtime *ifc = NULL;
- uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
+ uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
int page_size;
int port_size;
int pages_per_blk;
@@ -129,8 +129,8 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
ifc = runtime_regs_address();
/* Get NAND Flash configuration */
- csor = CONFIG_SYS_NAND_CSOR;
- cspr = CONFIG_SYS_NAND_CSPR;
+ csor = CFG_SYS_NAND_CSOR;
+ cspr = CFG_SYS_NAND_CSPR;
port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
@@ -250,8 +250,8 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -270,7 +270,7 @@ void nand_boot(void)
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
- flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+ flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE);
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
@@ -279,11 +279,11 @@ void nand_boot(void)
* calculate U-boot header address using U-boot header size.
*/
#define CONFIG_U_BOOT_HDR_ADDR \
- ((CONFIG_SYS_NAND_U_BOOT_START + \
- CONFIG_SYS_NAND_U_BOOT_SIZE) - \
+ ((CFG_SYS_NAND_U_BOOT_START + \
+ CFG_SYS_NAND_U_BOOT_SIZE) - \
CONFIG_U_BOOT_HDR_SIZE)
spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
- CONFIG_SYS_NAND_U_BOOT_START);
+ CFG_SYS_NAND_U_BOOT_START);
/*
* In case of failure in validation, spl_validate_uboot would
* not return back in case of Production environment with ITS=1.
@@ -293,7 +293,7 @@ void nand_boot(void)
*/
#endif
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
uboot();
}
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index a92c6252a5d..d795864949c 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -427,7 +427,7 @@ int fsmc_nand_init(struct nand_chip *nand)
nand->ecc.hwctl = fsmc_enable_hwecc;
nand->cmd_ctrl = fsmc_nand_hwcontrol;
nand->IO_ADDR_R = nand->IO_ADDR_W =
- (void __iomem *)CONFIG_SYS_NAND_BASE;
+ (void __iomem *)CFG_SYS_NAND_BASE;
nand->badblockbits = 7;
mtd = nand_to_mtd(nand);
diff --git a/drivers/mtd/nand/raw/kmeter1_nand.c b/drivers/mtd/nand/raw/kmeter1_nand.c
index b838164bf2e..84564b2f70a 100644
--- a/drivers/mtd/nand/raw/kmeter1_nand.c
+++ b/drivers/mtd/nand/raw/kmeter1_nand.c
@@ -10,8 +10,8 @@
#include <linux/delay.h>
#include <linux/mtd/rawnand.h>
-#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000)
-#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000)
+#define CONFIG_NAND_MODE_REG (void *)(CFG_SYS_NAND_BASE + 0x20000)
+#define CONFIG_NAND_DATA_REG (void *)(CFG_SYS_NAND_BASE + 0x30000)
#define read_mode() in_8(CONFIG_NAND_MODE_REG)
#define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val)
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
index 3d6cb1dc635..f4f1b22f5e2 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c
@@ -84,7 +84,7 @@ static struct nand_ecclayout lpc32xx_nand_oob_16 = {
};
#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
-#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE)
/*
* DMA Descriptors
@@ -187,7 +187,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
DMAC_CHAN_DEST_AHB1;
/* CTRL descriptor entry for reading/writing Data */
- ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
+ ctrl = (CFG_SYS_NAND_ECCSIZE / 4) |
DMAC_CHAN_SRC_BURST_4 |
DMAC_CHAN_DEST_BURST_4 |
DMAC_CHAN_SRC_WIDTH_32 |
@@ -241,7 +241,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
*/
- for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
+ for (i = 0; i < size/CFG_SYS_NAND_ECCSIZE; i++) {
dmalist_cur = &dmalist[i * 2];
dmalist_cur_ecc = &dmalist[(i * 2) + 1];
@@ -337,9 +337,9 @@ static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
{
int i;
- for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
- i += CONFIG_SYS_NAND_ECCBYTES) {
- u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
+ for (i = 0; i < (count * CFG_SYS_NAND_ECCBYTES);
+ i += CFG_SYS_NAND_ECCBYTES) {
+ u32 ce = ecc[i / CFG_SYS_NAND_ECCBYTES];
ce = ~(ce << 2) & 0xFFFFFF;
spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
@@ -386,9 +386,9 @@ int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat,
u16 data_offset = 0;
for (i = 0 ; i < ECCSTEPS ; i++) {
- r += CONFIG_SYS_NAND_ECCBYTES;
- c += CONFIG_SYS_NAND_ECCBYTES;
- data_offset += CONFIG_SYS_NAND_ECCSIZE;
+ r += CFG_SYS_NAND_ECCBYTES;
+ c += CFG_SYS_NAND_ECCBYTES;
+ data_offset += CFG_SYS_NAND_ECCSIZE;
ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
if (ret1 < 0)
@@ -568,8 +568,8 @@ int board_nand_init(struct nand_chip *lpc32xx_chip)
* These values are predefined
* for both small and large page NAND flash devices.
*/
- lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
+ lpc32xx_chip->ecc.size = CFG_SYS_NAND_ECCSIZE;
+ lpc32xx_chip->ecc.bytes = CFG_SYS_NAND_ECCBYTES;
lpc32xx_chip->ecc.strength = 1;
if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
index 2b8a132a5fc..fa903e324c5 100644
--- a/drivers/mtd/nand/raw/mxc_nand.c
+++ b/drivers/mtd/nand/raw/mxc_nand.c
@@ -50,7 +50,7 @@ static struct mxc_nand_host *host = &mxc_host;
/* OOB placement block for use with hardware ecc generation */
#if defined(MXC_NFC_V1)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 5,
.eccpos = {6, 7, 8, 9, 10},
@@ -69,7 +69,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = {
};
#endif
#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
-#ifndef CONFIG_SYS_NAND_LARGEPAGE
+#ifndef CFG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
@@ -1219,7 +1219,7 @@ int board_nand_init(struct nand_chip *this)
if (is_16bit_nand())
this->options |= NAND_BUSWIDTH_16;
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
+#ifdef CFG_SYS_NAND_LARGEPAGE
host->pagesize_2k = 1;
this->ecc.layout = &nand_hw_eccoob2k;
#else
diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c
index 0fea307ea46..309e75d01e5 100644
--- a/drivers/mtd/nand/raw/mxc_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxc_nand_spl.c
@@ -332,14 +332,14 @@ __used void nand_boot(void)
__attribute__((noreturn)) void (*uboot)(void);
/*
- * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
+ * CONFIG_SYS_NAND_U_BOOT_OFFS and CFG_SYS_NAND_U_BOOT_SIZE must
* be aligned to full pages
*/
if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (uchar *)CFG_SYS_NAND_U_BOOT_DST)) {
/* Copy from NAND successful, start U-Boot */
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
uboot();
} else {
/* Unrecoverable error when copying from NAND */
diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c
index 14bca12024b..eacd99c4e27 100644
--- a/drivers/mtd/nand/raw/nand.c
+++ b/drivers/mtd/nand/raw/nand.c
@@ -11,8 +11,8 @@
#include <linux/mtd/concat.h>
#include <linux/mtd/rawnand.h>
-#ifndef CONFIG_SYS_NAND_BASE_LIST
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#ifndef CFG_SYS_NAND_BASE_LIST
+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#endif
int nand_curr_device = -1;
@@ -21,7 +21,7 @@ static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
-static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
+static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
#endif
static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
diff --git a/drivers/mtd/nand/raw/nand_spl_load.c b/drivers/mtd/nand/raw/nand_spl_load.c
index ecd373e054b..7ac9bf4d120 100644
--- a/drivers/mtd/nand/raw/nand_spl_load.c
+++ b/drivers/mtd/nand/raw/nand_spl_load.c
@@ -20,8 +20,8 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ CFG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CFG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
@@ -36,6 +36,6 @@ void nand_boot(void)
/*
* Jump to U-Boot image
*/
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ uboot = (void *)CFG_SYS_NAND_U_BOOT_START;
(*uboot)();
}
diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c
index 727861c8f7e..2f3af9edd4c 100644
--- a/drivers/mtd/nand/raw/nand_spl_simple.c
+++ b/drivers/mtd/nand/raw/nand_spl_simple.c
@@ -10,13 +10,13 @@
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
+static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS;
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
+ CFG_SYS_NAND_ECCSIZE)
+#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES)
#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
@@ -139,8 +139,8 @@ static int nand_read_page(int block, int page, uchar *dst)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
@@ -170,8 +170,8 @@ static int nand_read_page(int block, int page, void *dst)
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
+ int eccsize = CFG_SYS_NAND_ECCSIZE;
+ int eccbytes = CFG_SYS_NAND_ECCBYTES;
int eccsteps = ECCSTEPS;
uint8_t *p = dst;
@@ -212,7 +212,7 @@ void nand_init(void)
*/
mtd = nand_to_mtd(&nand_chip);
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
- (void __iomem *)CONFIG_SYS_NAND_BASE;
+ (void __iomem *)CFG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
#ifdef CONFIG_SPL_NAND_SOFTECC
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 8b9ff4de189..b7d261d8ce1 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -407,7 +407,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
for (i = 0; i < cnt / 4; i++) {
- *buf++ = readl(CONFIG_SYS_NAND_BASE);
+ *buf++ = readl(CFG_SYS_NAND_BASE);
len -= 4;
}
} while (len);
diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c
index 13fd631cb40..d4b40e810f0 100644
--- a/drivers/mtd/nand/raw/vf610_nfc.c
+++ b/drivers/mtd/nand/raw/vf610_nfc.c
@@ -812,7 +812,7 @@ void board_nand_init(void)
return;
}
- nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE;
+ nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE;
err = vf610_nfc_nand_init(nfc, 0);
if (err)
printf("VF610 NAND init failed (err %d)\n", err);
generated by cgit v1.3.1 (git 2.54.0) at 2026-07-19 08:20:25 +0000