diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/raw/sunxi_nand.c | 11 | ||||
| -rw-r--r-- | drivers/mtd/nand/raw/sunxi_nand_spl.c | 13 |
2 files changed, 12 insertions, 12 deletions
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index c6b9b2a4eba..ba2740ed187 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -289,8 +289,7 @@ static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl) static void sunxi_nfc_set_clk_rate(unsigned long hz) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void * const ccm = (void *)SUNXI_CCM_BASE; int div_m, div_n; div_m = (clock_get_pll6() + hz - 1) / hz; @@ -305,14 +304,14 @@ static void sunxi_nfc_set_clk_rate(unsigned long hz) /* config mod clock */ writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 | CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m), - &ccm->nand0_clk_cfg); + ccm + CCU_NAND0_CLK_CFG); /* gate on nand clock */ - setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0)); + setbits_le32(ccm + CCU_AHB_GATE0, (1 << AHB_GATE_OFFSET_NAND0)); #ifdef CONFIG_MACH_SUN9I - setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); + setbits_le32(ccm + CCU_AHB_GATE1, (1 << AHB_GATE_OFFSET_DMA)); #else - setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); + setbits_le32(ccm + CCU_AHB_GATE0, (1 << AHB_GATE_OFFSET_DMA)); #endif } diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c index bd6fcd07be5..ab569d8086a 100644 --- a/drivers/mtd/nand/raw/sunxi_nand_spl.c +++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c @@ -531,14 +531,15 @@ unsigned int nand_page_size(void) void nand_deselect(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void * const ccm = (void *)SUNXI_CCM_BASE; - clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); + clrbits_le32(ccm + CCU_AHB_GATE0, + (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); #ifdef CONFIG_MACH_SUN9I - clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); + clrbits_le32(ccm + CCU_AHB_GATE1, (1 << AHB_GATE_OFFSET_DMA)); #else - clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); + clrbits_le32(ccm + CCU_AHB_GATE0, (1 << AHB_GATE_OFFSET_DMA)); #endif - clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); + clrbits_le32(ccm + CCU_NAND0_CLK_CFG, CCM_NAND_CTRL_ENABLE | + CCM_NAND_CTRL_N(0) | CCM_NAND_CTRL_M(1)); } |