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-rw-r--r--drivers/clk/mediatek/clk-mtk.h3
-rw-r--r--drivers/i2c/rk_i2c.c27
-rw-r--r--drivers/mmc/sdhci-cadence.c1
-rw-r--r--drivers/spi/Kconfig8
-rw-r--r--drivers/spi/Makefile2
5 files changed, 29 insertions, 12 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 4ef1341aea6..89479001ba8 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -133,8 +133,7 @@ struct mtk_parent {
* struct mtk_composite - aggregate clock of mux, divider and gate clocks
*
* @id: index of clocks
- * @parent: index of parnet clocks
- * @parent: index of parnet clocks
+ * @parent: index of parent clocks
* @parent_flags: table of parent clocks with flags
* @mux_reg: hardware-specific mux register
* @gate_reg: hardware-specific gate register
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index fa167268ae7..def07018148 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -137,7 +137,7 @@ static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
writel(I2C_CON_EN | I2C_CON_STOP, &regs->con);
- writel(I2C_CON_STOP, &regs->ien);
+ writel(I2C_STOPIEN, &regs->ien);
start = get_timer(0);
while (1) {
@@ -195,13 +195,14 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
while (bytes_remain_len) {
if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
- con = I2C_CON_EN;
- bytes_xferred = 32;
- } else {
/*
* The hw can read up to 32 bytes at a time. If we need
- * more than one chunk, send an ACK after the last byte.
+ * more than one chunk, send an ACK after the last byte
+ * of the current chunk.
*/
+ con = I2C_CON_EN;
+ bytes_xferred = 32;
+ } else {
con = I2C_CON_EN | I2C_CON_LASTACK;
bytes_xferred = bytes_remain_len;
}
@@ -254,8 +255,6 @@ static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
}
i2c_exit:
- rk_i2c_disable(i2c);
-
return err;
}
@@ -332,8 +331,6 @@ static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
}
i2c_exit:
- rk_i2c_disable(i2c);
-
return err;
}
@@ -358,6 +355,18 @@ static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
ret = -EREMOTEIO;
break;
}
+
+ /*
+ * The HW is actually not capable of REPEATED START. But we can
+ * get the intended effect by resetting its internal state
+ * and issuing an ordinary START.
+ *
+ * Do NOT disable the controller after the last message (before
+ * sending the STOP condition) as this triggers an illegal
+ * START condition followed by a STOP condition.
+ */
+ if (nmsgs > 1)
+ rk_i2c_disable(i2c);
}
rk_i2c_send_stop_bit(i2c);
diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c
index c7f88977ef9..5bbc18dfa51 100644
--- a/drivers/mmc/sdhci-cadence.c
+++ b/drivers/mmc/sdhci-cadence.c
@@ -298,6 +298,7 @@ static int sdhci_cdns_probe(struct udevice *dev)
static const struct udevice_id sdhci_cdns_match[] = {
{ .compatible = "socionext,uniphier-sd4hc" },
{ .compatible = "cdns,sd4hc" },
+ { .compatible = "altr,agilex5-sd6hc" },
{ .compatible = "cdns,sd6hc" },
{ /* sentinel */ }
};
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2afb15fff1e..e31db9d4e31 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -677,6 +677,14 @@ config SH_QSPI
Enable the Renesas Quad SPI controller driver. This driver can be
used on Renesas SoCs.
+config SPL_DESIGNWARE_SPI
+ bool "Designware SPI driver in SPL"
+ depends on SPL_DM_SPI
+ default y if DESIGNWARE_SPI
+ help
+ Enable the Designware SPI driver during SPL.
+ See the help of DESIGNWARE_SPI for details.
+
config MXC_SPI
bool "MXC SPI Driver"
depends on MACH_IMX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d5d1e543588..0dc2d23e172 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -35,7 +35,7 @@ obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o
obj-$(CONFIG_CV1800B_SPIF) += cv1800b_spif.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
-obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
+obj-$(CONFIG_$(PHASE_)DESIGNWARE_SPI) += designware_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o