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-rw-r--r--drivers/clk/altera/clk-agilex.c130
-rw-r--r--drivers/clk/altera/clk-agilex.h20
-rw-r--r--drivers/ddr/altera/iossm_mailbox.c24
-rw-r--r--drivers/ddr/altera/sdram_soc64.c6
-rw-r--r--drivers/ddr/altera/sdram_soc64.h2
-rw-r--r--drivers/i2c/designware_i2c.c2
-rw-r--r--drivers/mmc/socfpga_dw_mmc.c33
-rw-r--r--drivers/mtd/nand/raw/am335x_spl_bch.c2
-rw-r--r--drivers/pci/pci-rcar-gen4.c7
9 files changed, 198 insertions, 28 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index 242740a4b00..fdbf834bb2f 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -14,6 +14,7 @@
#include <dm/lists.h>
#include <dm/util.h>
#include <dt-bindings/clock/agilex-clock.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <asm/arch/clock_manager.h>
@@ -22,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR;
struct socfpga_clk_plat {
void __iomem *regs;
+ int pllgrp;
+ int bitmask;
};
/*
@@ -544,14 +547,11 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
/* Get EMAC clock source */
ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
if (emac_id == AGILEX_EMAC0_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
+ ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK, ctl);
else if (emac_id == AGILEX_EMAC1_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
+ ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK, ctl);
else if (emac_id == AGILEX_EMAC2_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
+ ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK, ctl);
else
return 0;
@@ -643,8 +643,125 @@ static ulong socfpga_clk_get_rate(struct clk *clk)
}
}
+static int bitmask_from_clk_id(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+
+ switch (clk->id) {
+ case AGILEX_MPU_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK;
+ break;
+ case AGILEX_L4_MAIN_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;
+ break;
+ case AGILEX_L4_MP_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;
+ break;
+ case AGILEX_L4_SP_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK;
+ break;
+ case AGILEX_CS_AT_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case AGILEX_CS_TRACE_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case AGILEX_CS_PDBG_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case AGILEX_CS_TIMER_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK;
+ break;
+ case AGILEX_S2F_USER0_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK;
+ break;
+ case AGILEX_EMAC0_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK;
+ break;
+ case AGILEX_EMAC1_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK;
+ break;
+ case AGILEX_EMAC2_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK;
+ break;
+ case AGILEX_EMAC_PTP_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK;
+ break;
+ case AGILEX_GPIO_DB_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK;
+ break;
+ case AGILEX_SDMMC_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK;
+ break;
+ case AGILEX_S2F_USER1_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK;
+ break;
+ case AGILEX_PSI_REF_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK;
+ break;
+ case AGILEX_USB_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK;
+ break;
+ case AGILEX_SPI_M_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK;
+ break;
+ case AGILEX_NAND_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
+ break;
+ default:
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
static int socfpga_clk_enable(struct clk *clk)
{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+ int ret;
+
+ ret = bitmask_from_clk_id(clk);
+ if (ret)
+ return ret;
+
+ setbits_le32(base_addr + plat->pllgrp, plat->bitmask);
+
+ return 0;
+}
+
+static int socfpga_clk_disable(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+ int ret;
+
+ ret = bitmask_from_clk_id(clk);
+ if (ret)
+ return ret;
+
+ clrbits_le32(base_addr + plat->pllgrp, plat->bitmask);
+
return 0;
}
@@ -672,6 +789,7 @@ static int socfpga_clk_of_to_plat(struct udevice *dev)
static struct clk_ops socfpga_clk_ops = {
.enable = socfpga_clk_enable,
+ .disable = socfpga_clk_disable,
.get_rate = socfpga_clk_get_rate,
};
diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h
index b3e8841a512..be639957940 100644
--- a/drivers/clk/altera/clk-agilex.h
+++ b/drivers/clk/altera/clk-agilex.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#ifndef _CLK_AGILEX_
@@ -210,7 +211,26 @@ struct cm_config {
#define CLKMGR_LOSTLOCK_SET_MASK BIT(0)
+#define CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK BIT(0)
+#define CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK BIT(1)
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2)
+#define CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK BIT(3)
+#define CLKMGR_MAINPLLGRP_EN_CSCLK_MASK BIT(4)
+#define CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK BIT(5)
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(6)
+
+#define CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK BIT(0)
+#define CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK BIT(1)
+#define CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK BIT(2)
+#define CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK BIT(3)
+#define CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK BIT(4)
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
+#define CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK BIT(6)
+#define CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK BIT(7)
+#define CLKMGR_PERPLLGRP_EN_USBCLK_MASK BIT(8)
+#define CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK BIT(9)
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK BIT(10)
+
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26)
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27
diff --git a/drivers/ddr/altera/iossm_mailbox.c b/drivers/ddr/altera/iossm_mailbox.c
index 21f94959a04..2a2f86a650e 100644
--- a/drivers/ddr/altera/iossm_mailbox.c
+++ b/drivers/ddr/altera/iossm_mailbox.c
@@ -38,6 +38,8 @@
#define IOSSM_STATUS_CMD_RESPONSE_ERROR(n) FIELD_GET(IOSSM_STATUS_CMD_RESPONSE_ERROR_MASK, n)
#define IOSSM_STATUS_GENERAL_ERROR_MASK GENMASK(4, 1)
#define IOSSM_STATUS_GENERAL_ERROR(n) FIELD_GET(IOSSM_STATUS_GENERAL_ERROR_MASK, n)
+#define IOSSM_MAILBOX_SPEC_VERSION_MASK GENMASK(2, 0)
+#define IOSSM_MAILBOX_SPEC_VERSION(n) FIELD_GET(IOSSM_MAILBOX_SPEC_VERSION_MASK, n)
/* Offset of Mailbox Read-only Registers */
#define IOSSM_MAILBOX_HEADER_OFFSET 0x0
@@ -383,6 +385,23 @@ err:
return ret;
}
+static bool is_mailbox_spec_compatible(struct io96b_info *io96b_ctrl)
+{
+ u32 mailbox_header;
+ u8 mailbox_spec_ver;
+
+ mailbox_header = readl(io96b_ctrl->io96b[0].io96b_csr_addr +
+ IOSSM_MAILBOX_HEADER_OFFSET);
+ mailbox_spec_ver = IOSSM_MAILBOX_SPEC_VERSION(mailbox_header);
+ printf("%s: IOSSM mailbox version: %d\n", __func__, mailbox_spec_ver);
+
+ /* for now there are two mailbox spec versions, 0 and 1; only version 1 is compatible */
+ if (!mailbox_spec_ver)
+ return false;
+
+ return true;
+}
+
/*
* Initial function to be called to set memory interface IP type and instance ID
* IP type and instance ID need to be determined before sending mailbox command
@@ -392,6 +411,11 @@ void io96b_mb_init(struct io96b_info *io96b_ctrl)
int i, j;
u32 mem_intf_info_0, mem_intf_info_1;
+ if (!is_mailbox_spec_compatible(io96b_ctrl)) {
+ printf("DDR: Failed to get compatible mailbox version\n");
+ hang();
+ }
+
debug("%s: num_instance %d\n", __func__, io96b_ctrl->num_instance);
for (i = 0; i < io96b_ctrl->num_instance; i++) {
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index f8fc92060db..2d0093c591c 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -85,11 +85,11 @@ int emif_reset(struct altera_sdram_plat *plat)
debug("DDR: Triggerring emif reset\n");
hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
- /* if seq2core[3] = 0, we are good */
+ /* if seq2core[2:0] = 0b0000_0111, we are good */
ret = wait_for_bit_le32((const void *)(plat->hmc +
RSTHANDSHAKESTAT),
- DDR_HMC_SEQ2CORE_INT_RESP_MASK,
- false, 1000, false);
+ DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK,
+ true, 1000, false);
if (ret) {
printf("DDR: failed to get ack from EMIF\n");
return ret;
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 6031cef560e..6fe0653922c 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -77,7 +77,7 @@ struct altera_sdram_plat {
#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
#define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f
#define DDR_HMC_CORE2SEQ_INT_REQ 0x0000000f
-#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
+#define DDR_HMC_SEQ2CORE_INT_REQ_ACK_MASK GENMASK(2, 0)
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
#define DDR_HMC_ERRINTEN_INTMASK \
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index a54976e7889..8ad716f410e 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -764,7 +764,7 @@ int designware_i2c_of_to_plat(struct udevice *bus)
ret = reset_get_bulk(bus, &priv->resets);
if (ret) {
- if (ret != -ENOTSUPP)
+ if (ret != -ENOTSUPP && ret != -ENOENT)
dev_warn(bus, "Can't get reset: %d\n", ret);
} else {
reset_deassert_bulk(&priv->resets);
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 3b86bc9b18c..db4e0129c2e 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -29,7 +29,9 @@ struct socfpga_dwmci_plat {
/* socfpga implmentation specific driver private data */
struct dwmci_socfpga_priv_data {
+ struct udevice *dev;
struct dwmci_host host;
+ struct clk mmc_clk_ciu;
unsigned int drvsel;
unsigned int smplsel;
};
@@ -51,28 +53,23 @@ static void socfpga_dwmci_reset(struct udevice *dev)
static int socfpga_dwmci_clksel(struct dwmci_host *host)
{
struct dwmci_socfpga_priv_data *priv = host->priv;
+ int ret;
+
u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
- /* Get clock manager base address */
- struct udevice *clkmgr_dev;
- int ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@ffd10000", &clkmgr_dev);
-
+ ret = clk_get_by_name(priv->dev, "ciu", &priv->mmc_clk_ciu);
if (ret) {
- printf("Failed to get clkmgr device: %d\n", ret);
+ debug("%s: Failed to get SDMMC clock from dts\n", __func__);
return ret;
}
- fdt_addr_t clkmgr_base = dev_read_addr(clkmgr_dev);
-
- if (clkmgr_base == FDT_ADDR_T_NONE) {
- printf("Failed to read base address from clkmgr DT node\n");
- return -EINVAL;
- }
-
/* Disable SDMMC clock. */
- clrbits_le32(clkmgr_base + CLKMGR_PERPLL_EN,
- CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+ ret = clk_disable(&priv->mmc_clk_ciu);
+ if (ret) {
+ printf("%s: Failed to disable SDMMC clock\n", __func__);
+ return ret;
+ }
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
@@ -92,8 +89,11 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host)
#endif
/* Enable SDMMC clock */
- setbits_le32(clkmgr_base + CLKMGR_PERPLL_EN,
- CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+ ret = clk_enable(&priv->mmc_clk_ciu);
+ if (ret) {
+ printf("%s: Failed to enable SDMMC clock\n", __func__);
+ return ret;
+ }
return 0;
}
@@ -169,6 +169,7 @@ static int socfpga_dwmmc_probe(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
+ priv->dev = dev;
int ret;
ret = socfpga_dwmmc_get_clk_rate(dev);
diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c
index 4b50f351d35..a77206d3815 100644
--- a/drivers/mtd/nand/raw/am335x_spl_bch.c
+++ b/drivers/mtd/nand/raw/am335x_spl_bch.c
@@ -212,6 +212,8 @@ void nand_init(void)
if (nand_chip.select_chip)
nand_chip.select_chip(mtd, 0);
+ mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+
/* NAND chip may require reset after power-on */
nand_command(0, 0, 0, NAND_CMD_RESET);
}
diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c
index 41f0d958447..1f41ce28b0b 100644
--- a/drivers/pci/pci-rcar-gen4.c
+++ b/drivers/pci/pci-rcar-gen4.c
@@ -243,7 +243,7 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable
clrbits_le32(rcar->app_base + PCIERSTCTRL1, APP_HOLD_PHY_RST);
- ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, !(val & BIT(18)), 10000);
+ ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, val & BIT(18), 10000);
if (ret < 0)
return ret;
@@ -306,6 +306,8 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
if (ret)
goto err_unprepare;
+ mdelay(1);
+
setbits_le32(rcar->app_base + PCIEMSR0,
DEVICE_TYPE_RC |
((rcar->num_lanes < 4) ? BIFUR_MOD_SET_ON : 0));
@@ -314,6 +316,9 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
if (ret)
goto err_unprepare;
+ reset_status(&rcar->pwr_rst);
+ mdelay(1);
+
rcar_gen4_pcie_additional_common_init(rcar);
return 0;
generated by cgit v1.3.1 (git 2.54.0) at 2026-05-31 08:54:27 +0000