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-rw-r--r--drivers/ddr/imx/imx9/Kconfig7
-rw-r--r--drivers/i2c/imx_lpi2c.c4
-rw-r--r--drivers/net/Kconfig4
-rw-r--r--drivers/net/fsl_enetc.c46
-rw-r--r--drivers/net/fsl_enetc_netc_blk_ctrl.c72
-rw-r--r--drivers/net/phy/nxp-c45-tja11xx.c2
-rw-r--r--drivers/power/regulator/pfuze100.c2
7 files changed, 123 insertions, 14 deletions
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
index b953bca4f06..7b3dbf53dff 100644
--- a/drivers/ddr/imx/imx9/Kconfig
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -29,4 +29,11 @@ config SAVED_DRAM_TIMING_BASE
after DRAM is trained, need to save the dram related timming
info into memory for low power use.
+config QB_SAVED_STATE_BASE
+ hex "Define the base address for saved QuickBoot state"
+ default 0x8fe00000
+ help
+ Once DRAM is trained, the resulted training info is
+ saved into memory in order to be reachable from U-Boot.
+
endmenu
diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
index a309fd6f07c..e2b4fd334ec 100644
--- a/drivers/i2c/imx_lpi2c.c
+++ b/drivers/i2c/imx_lpi2c.c
@@ -239,7 +239,6 @@ static int bus_i2c_stop(struct udevice *bus)
start_time = get_timer(0);
while (1) {
status = readl(&regs->msr);
- result = imx_lpci2c_check_clear_error(regs);
/* stop detect flag */
if (status & LPI2C_MSR_SDF_MASK) {
/* clear stop flag */
@@ -250,10 +249,13 @@ static int bus_i2c_stop(struct udevice *bus)
if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
debug("stop timeout\n");
+ result = imx_lpci2c_check_clear_error(regs);
return -ETIMEDOUT;
}
}
+ result = imx_lpci2c_check_clear_error(regs);
+
return result;
}
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 666618681df..f2e838b84de 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1018,8 +1018,8 @@ config FSL_ENETC
config FSL_ENETC_NETC_BLK_CTRL
bool "NXP ENETC NETC blocks control driver"
depends on FSL_ENETC
- depends on IMX95 || IMX94
- default y if IMX95 || IMX94
+ depends on IMX95 || IMX94 || IMX952
+ default y if IMX95 || IMX94 || IMX952
help
This driver configures Integrated Endpoint Register Block (IERB) and
Privileged Register Block (PRB) of NETC. For i.MX platforms, it also
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index 206f1a381bb..f393af40e27 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -18,6 +18,7 @@
#include <asm/io.h>
#include <pci.h>
#include <miiphy.h>
+#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/build_bug.h>
@@ -74,10 +75,36 @@ static int enetc_is_ls1028a(struct udevice *dev)
pplat->vendor == PCI_VENDOR_ID_FREESCALE;
}
+static int enetc_dev_id_imx(struct udevice *dev)
+{
+ if (IS_ENABLED(CONFIG_IMX952)) {
+ int bus_devfn;
+ u32 reg[5];
+ int error;
+
+ error = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg));
+ if (error)
+ return error;
+
+ bus_devfn = (reg[0] >> 8) & 0xffff;
+
+ switch (bus_devfn) {
+ case 0:
+ return 0;
+ case 0x100:
+ return 1;
+ default:
+ return -EINVAL;
+ }
+ }
+
+ return PCI_DEV(pci_get_devfn(dev)) >> 3;
+}
+
static int enetc_dev_id(struct udevice *dev)
{
if (enetc_is_imx95(dev))
- return PCI_DEV(pci_get_devfn(dev)) >> 3;
+ return enetc_dev_id_imx(dev);
if (enetc_is_ls1028a(dev))
return PCI_FUNC(pci_get_devfn(dev));
@@ -396,7 +423,7 @@ static int enetc_init_sgmii(struct udevice *dev)
/* set up MAC for RGMII */
static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
{
- u32 old_val, val, dpx = 0;
+ u32 old_val, val = 0;
old_val = val = enetc_read_mac_port(dev, ENETC_PM_IF_MODE);
@@ -416,15 +443,14 @@ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
val |= ENETC_PM_IFM_SSP_10;
}
- if (enetc_is_imx95(dev))
- dpx = ENETC_PM_IFM_FULL_DPX_IMX;
+ if (enetc_is_imx95(dev))
+ val = u32_replace_bits(val,
+ phydev->duplex == DUPLEX_FULL ? 0 : 1,
+ ENETC_PM_IFM_FULL_DPX_IMX);
else if (enetc_is_ls1028a(dev))
- dpx = ENETC_PM_IFM_FULL_DPX_LS;
-
- if (phydev->duplex == DUPLEX_FULL)
- val |= dpx;
- else
- val &= ~dpx;
+ val = u32_replace_bits(val,
+ phydev->duplex == DUPLEX_FULL ? 1 : 0,
+ ENETC_PM_IFM_FULL_DPX_LS);
if (val == old_val)
return;
diff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c
index 8577bb75632..0c87d80ea5c 100644
--- a/drivers/net/fsl_enetc_netc_blk_ctrl.c
+++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c
@@ -35,6 +35,7 @@
#define MII_PROT_RGMII 0x2
#define MII_PROT_SERIAL 0x3
#define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2))
+#define MII_PROT_GET(reg, port) (((reg) >> ((port) << 2)) & 0xf)
#define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4)
#define PCS_PROT_1G_SGMII BIT(0)
@@ -97,6 +98,9 @@
#define IMX94_TIMER1_ID 1
#define IMX94_TIMER2_ID 2
+#define IMX952_ENETC0_BUS_DEVFN 0x0
+#define IMX952_ENETC1_BUS_DEVFN 0x100
+
/* Flags for different platforms */
#define NETC_HAS_NETCMIX BIT(0)
@@ -567,6 +571,69 @@ static int netc_prb_check_error(struct netc_blk_ctrl *priv)
return 0;
}
+static int imx952_netcmix_init(struct udevice *dev)
+{
+ struct netc_blk_ctrl *priv = dev_get_priv(dev);
+ ofnode child, gchild;
+ phy_interface_t interface;
+ int bus_devfn, mii_proto;
+ u32 val;
+
+ /* Default setting */
+ val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII);
+
+ /* Update the link MII protocol through parsing phy-mode */
+ dev_for_each_subnode(child, dev) {
+ if (!ofnode_is_enabled(child))
+ continue;
+
+ ofnode_for_each_subnode(gchild, child) {
+ if (!ofnode_is_enabled(gchild))
+ continue;
+
+ if (!ofnode_device_is_compatible(gchild, "pci1131,e101"))
+ continue;
+
+ bus_devfn = netc_of_pci_get_bus_devfn(gchild);
+ if (bus_devfn < 0)
+ return -EINVAL;
+
+ interface = ofnode_read_phy_mode(gchild);
+ if (interface == -1)
+ continue;
+
+ mii_proto = netc_get_link_mii_protocol(interface);
+ if (mii_proto < 0)
+ return -EINVAL;
+
+ switch (bus_devfn) {
+ case IMX952_ENETC0_BUS_DEVFN:
+ val &= ~CFG_LINK_MII_PORT_0;
+ val |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto);
+ break;
+ case IMX952_ENETC1_BUS_DEVFN:
+ val &= ~CFG_LINK_MII_PORT_1;
+ val |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto);
+ break;
+ default:
+ return -EINVAL;
+ }
+ }
+ }
+
+ if (MII_PROT_GET(val, 1) == MII_PROT_SERIAL) {
+ /* Configure Link I/O variant */
+ netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR,
+ IO_VAR(1, IO_VAR_16FF_16G_SERDES));
+ /* Configure Link 2 PCS protocol */
+ netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(1),
+ PCS_PROT_2500M_SGMII);
+ }
+ netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val);
+
+ return 0;
+}
+
static const struct netc_devinfo imx95_devinfo = {
.netcmix_init = imx95_netcmix_init,
.ierb_init = imx95_ierb_init,
@@ -578,9 +645,14 @@ static const struct netc_devinfo imx94_devinfo = {
.xpcs_port_init = imx94_netc_xpcs_port_init,
};
+static const struct netc_devinfo imx952_devinfo = {
+ .netcmix_init = imx952_netcmix_init,
+};
+
static const struct udevice_id netc_blk_ctrl_match[] = {
{ .compatible = "nxp,imx95-netc-blk-ctrl", .data = (ulong)&imx95_devinfo },
{ .compatible = "nxp,imx94-netc-blk-ctrl", .data = (ulong)&imx94_devinfo },
+ { .compatible = "nxp,imx952-netc-blk-ctrl", .data = (ulong)&imx952_devinfo },
{},
};
diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
index a1e4c3d053b..9814ac498ed 100644
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -343,7 +343,7 @@ static int nxp_c45_probe(struct phy_device *phydev)
{
struct nxp_c45_phy *priv;
- priv = devm_kzalloc(phydev->priv, sizeof(*priv), GFP_KERNEL);
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c
index 77c82a00b65..57af16cfbb9 100644
--- a/drivers/power/regulator/pfuze100.c
+++ b/drivers/power/regulator/pfuze100.c
@@ -550,6 +550,8 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)
return -EINVAL;
}
val = pmic_reg_read(dev->parent, desc->vsel_reg);
+ if (val < 0)
+ return val;
if (desc->high_volt_mask && (val & desc->high_volt_mask)) {
min_uV = desc->high_volt_desc->min_uV;
uV_step = desc->high_volt_desc->uV_step;
generated by cgit v1.3.1 (git 2.54.0) at 2026-07-11 22:40:27 +0000