diff options
Diffstat (limited to 'drivers')
336 files changed, 6600 insertions, 2263 deletions
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index 2b45f9e5eba..d5ef0795401 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -5,7 +5,7 @@ config ADC This enables ADC API for drivers, which allows driving ADC features by single and multi-channel methods for: - start/stop/get data for conversion of a single-channel selected by - a number or multi-channels selected by a bitmask + a number or multi-channels selected by a bitmask - get data mask (ADC resolution) ADC reference Voltage supply options: - methods for get Vdd/Vss reference Voltage values with polarity diff --git a/drivers/ata/dwc_ahci.c b/drivers/ata/dwc_ahci.c index b480cde4465..0431d370716 100644 --- a/drivers/ata/dwc_ahci.c +++ b/drivers/ata/dwc_ahci.c @@ -39,7 +39,7 @@ static int dwc_ahci_of_to_plat(struct udevice *dev) priv->base = map_physmem(dev_read_addr(dev), sizeof(void *), MAP_NOCACHE); - addr = devfdt_get_addr_index(dev, 1); + addr = dev_read_addr_index(dev, 1); if (addr != FDT_ADDR_T_NONE) { priv->wrapper_base = map_physmem(addr, sizeof(void *), MAP_NOCACHE); diff --git a/drivers/ata/fsl_sata.c b/drivers/ata/fsl_sata.c index 4990148388b..a29735f7609 100644 --- a/drivers/ata/fsl_sata.c +++ b/drivers/ata/fsl_sata.c @@ -960,7 +960,7 @@ static int sata_fsl_scan(struct udevice *dev) return 0; } -struct ahci_ops sata_fsl_ahci_ops = { +static const struct ahci_ops sata_fsl_ahci_ops = { .scan = sata_fsl_scan, }; diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c index 53aabee0a5e..1d4245ee635 100644 --- a/drivers/ata/mtk_ahci.c +++ b/drivers/ata/mtk_ahci.c @@ -45,7 +45,9 @@ static int mtk_ahci_of_to_plat(struct udevice *dev) { struct mtk_ahci_priv *priv = dev_get_priv(dev); - priv->base = devfdt_remap_addr_index(dev, 0); + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) + return -EINVAL; return 0; } @@ -54,11 +56,9 @@ static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv, struct udevice *dev) { struct mtk_ahci_priv *plat = dev_get_priv(dev); - const void *fdt = gd->fdt_blob; /* enable SATA function if needed */ - if (fdt_get_property(fdt, dev_of_offset(dev), - "mediatek,phy-mode", NULL)) { + if (dev_read_prop(dev, "mediatek,phy-mode", NULL)) { plat->mode = syscon_regmap_lookup_by_phandle(dev, "mediatek,phy-mode"); if (IS_ERR(plat->mode)) { @@ -69,8 +69,8 @@ static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv, SYS_CFG_SATA_MSK, SYS_CFG_SATA_EN); } - ofnode_read_u32(dev_ofnode(dev), "ports-implemented", - &hpriv->port_map); + dev_read_u32(dev, "ports-implemented", &hpriv->port_map); + return 0; } diff --git a/drivers/ata/sata_bootdev.c b/drivers/ata/sata_bootdev.c index a5ca6f6fd5b..7d5ef3c94bf 100644 --- a/drivers/ata/sata_bootdev.c +++ b/drivers/ata/sata_bootdev.c @@ -37,9 +37,6 @@ static int sata_bootdev_hunt(struct bootdev_hunter *info, bool show) return 0; } -struct bootdev_ops sata_bootdev_ops = { -}; - static const struct udevice_id sata_bootdev_ids[] = { { .compatible = "u-boot,bootdev-sata" }, { } @@ -48,7 +45,6 @@ static const struct udevice_id sata_bootdev_ids[] = { U_BOOT_DRIVER(sata_bootdev) = { .name = "sata_bootdev", .id = UCLASS_BOOTDEV, - .ops = &sata_bootdev_ops, .bind = sata_bootdev_bind, .of_match = sata_bootdev_ids, }; diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index b8c73b4a9dd..3fb1a245698 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -1122,7 +1122,7 @@ static const struct udevice_id sata_mv_ids[] = { { } }; -struct ahci_ops sata_mv_ahci_ops = { +static const struct ahci_ops sata_mv_ahci_ops = { .scan = sata_mv_scan, }; diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index adf338ab00c..d44cf4bcb6b 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -68,10 +68,10 @@ config BLKMAP bool "Composable virtual block devices (blkmap)" depends on BLK help - Create virtual block devices that are backed by various sources, - e.g. RAM, or parts of an existing block device. Though much more - rudimentary, it borrows a lot of ideas from Linux's device mapper - subsystem. + Create virtual block devices that are backed by various sources, + e.g. RAM, or parts of an existing block device. Though much more + rudimentary, it borrows a lot of ideas from Linux's device mapper + subsystem. Example use-cases: - Treat a region of RAM as a block device, i.e. a RAM disk. This let's diff --git a/drivers/block/Makefile b/drivers/block/Makefile index f5a9d8637a3..c827fa81a2d 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -13,7 +13,7 @@ ifndef CONFIG_XPL_BUILD obj-$(CONFIG_IDE) += ide.o obj-$(CONFIG_RKMTD) += rkmtd.o endif -obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o +obj-$(CONFIG_SANDBOX) += sandbox.o sandbox-bootdev.o host-uclass.o host_dev.o obj-$(CONFIG_$(PHASE_)BLOCK_CACHE) += blkcache.o obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap.o obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap_helper.o diff --git a/drivers/block/host-uclass.c b/drivers/block/host-uclass.c index cf42bd1e07a..95b0b0b2ffe 100644 --- a/drivers/block/host-uclass.c +++ b/drivers/block/host-uclass.c @@ -150,6 +150,21 @@ struct udevice *host_find_by_label(const char *label) return NULL; } +int host_set_flags_by_label(const char *label, unsigned int flags) +{ + struct udevice *dev; + struct host_sb_plat *plat; + + dev = host_find_by_label(label); + if (!dev) + return -ENODEV; + + plat = dev_get_plat(dev); + plat->flags = flags; + + return 0; +} + struct udevice *host_get_cur_dev(void) { struct uclass *uc = uclass_find(UCLASS_HOST); diff --git a/drivers/block/ide.c b/drivers/block/ide.c index cab5e1bc92b..c1a46dd2a94 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -969,9 +969,6 @@ static int ide_bootdev_hunt(struct bootdev_hunter *info, bool show) return 0; } -struct bootdev_ops ide_bootdev_ops = { -}; - static const struct udevice_id ide_bootdev_ids[] = { { .compatible = "u-boot,bootdev-ide" }, { } @@ -980,7 +977,6 @@ static const struct udevice_id ide_bootdev_ids[] = { U_BOOT_DRIVER(ide_bootdev) = { .name = "ide_bootdev", .id = UCLASS_BOOTDEV, - .ops = &ide_bootdev_ops, .bind = ide_bootdev_bind, .of_match = ide_bootdev_ids, }; diff --git a/drivers/block/rkmtd.c b/drivers/block/rkmtd.c index f84cacd7ead..9334ab24a61 100644 --- a/drivers/block/rkmtd.c +++ b/drivers/block/rkmtd.c @@ -935,7 +935,7 @@ int rkmtd_detach_mtd(struct udevice *dev) return 0; } -struct rkmtd_ops rkmtd_ops = { +static const struct rkmtd_ops rkmtd_ops = { .attach_mtd = rkmtd_attach_mtd, .detach_mtd = rkmtd_detach_mtd, }; diff --git a/drivers/block/sandbox-bootdev.c b/drivers/block/sandbox-bootdev.c new file mode 100644 index 00000000000..15af0c17d1f --- /dev/null +++ b/drivers/block/sandbox-bootdev.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#define LOG_CATEGORY UCLASS_HOST + +#include <bootdev.h> +#include <dm.h> +#include <log.h> +#include <sandbox_host.h> + +static int sandbox_bootdev_bind(struct udevice *dev) +{ + struct bootdev_uc_plat *ucp = dev_get_uclass_plat(dev); + + ucp->prio = BOOTDEVP_4_SCAN_FAST; + + return 0; +} + +/** + * sandbox_bootdev_hunt() - Hunt host bootdev. + * + * Note, this hunter exists for bootdev testing to simulate a failure + * mode. Do not use as an example of a real hunter. + * + * @info: Hunter details. + * @show: Enable extra printouts. + * + * Returns: 0 if OK, -ve on error (expected by the test) + */ +static int sandbox_bootdev_hunt(struct bootdev_hunter *info, bool show) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + uclass_id_foreach_dev(UCLASS_HOST, dev, uc) { + struct host_sb_plat *plat = dev_get_plat(dev); + + log_debug("hunting %s\n", plat->label); + + if (plat->flags & HOST_FLAG_BROKEN) { + ret = -ETIME; + log_debug("cannot hunt sandbox device '%s': %d\n", + plat->label, ret); + return ret; + } + } + + return 0; +} + +static const struct bootdev_ops sandbox_bootdev_ops = { +}; + +static const struct udevice_id sandbox_bootdev_ids[] = { + { .compatible = "u-boot,bootdev-sandbox" }, + { } +}; + +U_BOOT_DRIVER(sandbox_bootdev) = { + .name = "sandbox_bootdev", + .id = UCLASS_BOOTDEV, + .ops = &sandbox_bootdev_ops, + .bind = sandbox_bootdev_bind, + .of_match = sandbox_bootdev_ids, +}; + +BOOTDEV_HUNTER(sandbox_bootdev_hunter) = { + .prio = BOOTDEVP_4_SCAN_FAST, + .uclass = UCLASS_HOST, + .hunt = sandbox_bootdev_hunt, + .drv = DM_DRIVER_REF(sandbox_bootdev), +}; diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 4c0c8d89bb4..af6bd2f1a7d 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -68,7 +68,7 @@ config BOOTCOUNT_ENV saveenv on all reboots, the environment variable "upgrade_available" is used. If "upgrade_available" is 0, "bootcount" is always 0. If "upgrade_available" is 1, - "bootcount" is incremented in the environment. + "bootcount" is incremented in the environment. So the Userspace Application must set the "upgrade_available" and "bootcount" variables to 0, if the system booted successfully. @@ -83,7 +83,7 @@ config BOOTCOUNT_AT91 depends on AT91SAM9XE config DM_BOOTCOUNT - bool "Boot counter in a device-model device" + bool "Boot counter in a device-model device" help Enables reading/writing the bootcount in a device-model based backing store. If an entry in /chosen/u-boot,bootcount-device diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c index 33e157b865a..f726d9ab016 100644 --- a/drivers/bootcount/bootcount_ram.c +++ b/drivers/bootcount/bootcount_ram.c @@ -27,7 +27,7 @@ void bootcount_store(ulong a) int i; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); writel(a, save_addr); writel(CONFIG_SYS_BOOTCOUNT_MAGIC, &save_addr[1]); @@ -50,7 +50,7 @@ ulong bootcount_load(void) int i, tmp; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - size += gd->bd->bi_dram[i].size; + size += gd->dram[i].size; save_addr = (ulong *)(size - BOOTCOUNT_ADDR); counter = readl(&save_addr[0]); diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c2da7b3938b..addcece4da3 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -134,8 +134,8 @@ config CLK_CDCE9XX bool "Enable CDCD9XX clock driver" depends on CLK && ARCH_OMAP2PLUS help - Enable the clock synthesizer driver for CDCE913/925/937/949 - series of chips. + Enable the clock synthesizer driver for CDCE913/925/937/949 + series of chips. config CLK_ICS8N3QV01 bool "Enable ICS8N3QV01 VCXO driver" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 5f0c0d8a5c2..c37ef75d420 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_$(PHASE_)CLK_STUB) += clk-stub.o obj-y += adi/ obj-y += airoha/ obj-y += analogbits/ -obj-y += imx/ +obj-$(CONFIG_MACH_IMX) += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c index ac59571a853..149e3016dd3 100644 --- a/drivers/clk/altera/clk-mem-n5x.c +++ b/drivers/clk/altera/clk-mem-n5x.c @@ -103,12 +103,13 @@ static int socfpga_mem_clk_enable(struct clk *clk) static int socfpga_mem_clk_of_to_plat(struct udevice *dev) { struct socfpga_mem_clk_plat *plat = dev_get_plat(dev); - fdt_addr_t addr; + void __iomem *addr; - addr = devfdt_get_addr(dev); - if (addr == FDT_ADDR_T_NONE) + addr = dev_read_addr_ptr(dev); + if (!addr) return -EINVAL; - plat->regs = (void __iomem *)addr; + + plat->regs = addr; return 0; } diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 185c9028a78..0a3bae38589 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -454,12 +454,12 @@ static int socfpga_clk_probe(struct udevice *dev) static int socfpga_clk_of_to_plat(struct udevice *dev) { struct socfpga_clk_plat *plat = dev_get_plat(dev); - fdt_addr_t addr; + void __iomem *addr; - addr = devfdt_get_addr(dev); - if (addr == FDT_ADDR_T_NONE) + addr = dev_read_addr_ptr(dev); + if (!addr) return -EINVAL; - plat->regs = (void __iomem *)addr; + plat->regs = addr; return 0; } diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile index 84776e5265e..285180b67cf 100644 --- a/drivers/clk/aspeed/Makefile +++ b/drivers/clk/aspeed/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o obj-$(CONFIG_ASPEED_AST2600) += clk_ast2600.o +obj-$(CONFIG_ASPEED_AST2700) += clk_ast2700.o diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index a330dcda4dc..94c7f662319 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -534,7 +534,7 @@ static int ast2500_clk_enable(struct clk *clk) return 0; } -struct clk_ops ast2500_clk_ops = { +static const struct clk_ops ast2500_clk_ops = { .get_rate = ast2500_clk_get_rate, .set_rate = ast2500_clk_set_rate, .enable = ast2500_clk_enable, @@ -544,9 +544,9 @@ static int ast2500_clk_of_to_plat(struct udevice *dev) { struct ast2500_clk_priv *priv = dev_get_priv(dev); - priv->scu = devfdt_get_addr_ptr(dev); - if (IS_ERR(priv->scu)) - return PTR_ERR(priv->scu); + priv->scu = dev_read_addr_ptr(dev); + if (!priv->scu) + return -EINVAL; return 0; } diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 535010b7941..74209e947ed 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -1161,7 +1161,7 @@ static void ast2600_clk_dump(struct udevice *dev) } #endif -struct clk_ops ast2600_clk_ops = { +static const struct clk_ops ast2600_clk_ops = { .get_rate = ast2600_clk_get_rate, .set_rate = ast2600_clk_set_rate, .enable = ast2600_clk_enable, @@ -1174,9 +1174,9 @@ static int ast2600_clk_probe(struct udevice *dev) { struct ast2600_clk_priv *priv = dev_get_priv(dev); - priv->scu = devfdt_get_addr_ptr(dev); - if (IS_ERR(priv->scu)) - return PTR_ERR(priv->scu); + priv->scu = dev_read_addr_ptr(dev); + if (!priv->scu) + return -EINVAL; ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); diff --git a/drivers/clk/aspeed/clk_ast2700.c b/drivers/clk/aspeed/clk_ast2700.c new file mode 100644 index 00000000000..ca76abef48f --- /dev/null +++ b/drivers/clk/aspeed/clk_ast2700.c @@ -0,0 +1,952 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <asm/io.h> +#include <asm/arch/scu_ast2700.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <syscon.h> +#include <linux/bitfield.h> + +#include <dt-bindings/clock/aspeed,ast2700-scu.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * RGMII clock source tree + * HPLL -->|\ + * | |---->| divider |---->RGMII 125M for MAC#0 & MAC#1 + * APLL -->|/ + */ +#define RGMII_DEFAULT_CLK_SRC SCU1_CLK_HPLL + +struct mac_delay_config { + u32 tx_delay_1000; + u32 rx_delay_1000; + u32 tx_delay_100; + u32 rx_delay_100; + u32 tx_delay_10; + u32 rx_delay_10; +}; + +typedef int (*ast2700_clk_init_fn)(struct udevice *dev); + +struct ast2700_clk_priv { + void __iomem *reg; + ast2700_clk_init_fn init; +}; + +static u32 ast2700_soc1_get_pll_rate(struct ast2700_scu1 *scu, int pll_idx) +{ + union ast2700_pll_reg pll_reg; + u32 mul = 1, div = 1; + + switch (pll_idx) { + case SCU1_CLK_HPLL: + pll_reg.w = readl(&scu->hpll); + break; + case SCU1_CLK_APLL: + pll_reg.w = readl(&scu->apll); + break; + case SCU1_CLK_DPLL: + pll_reg.w = readl(&scu->dpll); + break; + } + + if (!pll_reg.b.bypass) { + mul = (pll_reg.b.m + 1) / (pll_reg.b.n + 1); + div = (pll_reg.b.p + 1); + } + + return ((CLKIN_25M * mul) / div); +} + +#define SCU_CLKSEL2_HCLK_DIV_MASK GENMASK(22, 20) +#define SCU_CLKSEL2_HCLK_DIV_SHIFT 20 + +static u32 ast2700_soc1_get_hclk_rate(struct ast2700_scu1 *scu) +{ + u32 rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 clk_sel2 = readl(&scu->clk_sel2); + u32 hclk_div = (clk_sel2 & SCU_CLKSEL2_HCLK_DIV_MASK) >> + SCU_CLKSEL2_HCLK_DIV_SHIFT; + + if (!hclk_div) + hclk_div = 2; + else + hclk_div++; + + return (rate / hclk_div); +} + +#define SCU1_CLKSEL1_PCLK_DIV_MASK GENMASK(20, 18) +#define SCU1_CLKSEL1_PCLK_DIV_SHIFT 18 + +static u32 ast2700_soc1_get_pclk_rate(struct ast2700_scu1 *scu) +{ + u32 rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + + u32 clk_sel1 = readl(&scu->clk_sel1); + u32 pclk_div = (clk_sel1 & SCU1_CLKSEL1_PCLK_DIV_MASK) >> + SCU1_CLKSEL1_PCLK_DIV_SHIFT; + + return (rate / ((pclk_div + 1) * 2)); +} + +#define SCU_UART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_UART_CLKGEN_N_SHIFT 8 +#define SCU_UART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_UART_CLKGEN_R_SHIFT 0 + +static u32 ast2700_soc1_get_uart_uxclk_rate(struct ast2700_scu1 *scu) +{ + u32 uxclk_sel = readl(&scu->clk_sel2) & GENMASK(1, 0); + u32 uxclk_ctrl = readl(&scu->uxclk_ctrl); + u32 rate; + + switch (uxclk_sel) { + case 0: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 4; + break; + case 1: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 2; + break; + case 2: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL); + break; + case 3: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + break; + } + + u32 n = (uxclk_ctrl & SCU_UART_CLKGEN_N_MASK) >> + SCU_UART_CLKGEN_N_SHIFT; + u32 r = (uxclk_ctrl & SCU_UART_CLKGEN_R_MASK) >> + SCU_UART_CLKGEN_R_SHIFT; + + return ((rate * r) / (n * 2)); +} + +#define SCU_HUART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_HUART_CLKGEN_N_SHIFT 8 +#define SCU_HUART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_HUART_CLKGEN_R_SHIFT 0 + +static u32 ast2700_soc1_get_uart_huxclk_rate(struct ast2700_scu1 *scu) +{ + u32 huxclk_sel = (readl(&scu->clk_sel2) & GENMASK(4, 3)) >> 3; + u32 huxclk_ctrl = readl(&scu->huxclk_ctrl); + u32 n = (huxclk_ctrl & SCU_HUART_CLKGEN_N_MASK) >> + SCU_HUART_CLKGEN_N_SHIFT; + u32 r = (huxclk_ctrl & SCU_HUART_CLKGEN_R_MASK) >> + SCU_HUART_CLKGEN_R_SHIFT; + u32 rate; + + switch (huxclk_sel) { + case 0: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 4; + break; + case 1: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 2; + break; + case 2: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL); + break; + case 3: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + break; + } + + return ((rate * r) / (n * 2)); +} + +#define SCU_CLKSRC1_SDIO_DIV_MASK GENMASK(16, 14) +#define SCU_CLKSRC1_SDIO_DIV_SHIFT 14 +#define SCU_CLKSRC1_SDIO_SEL BIT(13) +const int ast2700_sd_div_tbl[] = { + 2, 2, 3, 4, 5, 6, 7, 8 +}; + +static u32 ast2700_soc1_get_sdio_clk_rate(struct ast2700_scu1 *scu) +{ + u32 rate = 0; + u32 clk_sel1 = readl(&scu->clk_sel1); + u32 div = (clk_sel1 & SCU_CLKSRC1_SDIO_DIV_MASK) >> + SCU_CLKSRC1_SDIO_DIV_SHIFT; + + if (clk_sel1 & SCU_CLKSRC1_SDIO_SEL) + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL); + else + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + + if (!div) + div = 1; + + div++; + + return (rate / div); +} + +static void ast2700_init_sdclk(struct ast2700_scu1 *scu) +{ + u32 src_clk = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 reg_280; + int i; + + for (i = 0; i < 8; i++) { + if (src_clk / ast2700_sd_div_tbl[i] <= 125000000) + break; + } + + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~(SCU_CLKSRC1_SDIO_DIV_MASK | SCU_CLKSRC1_SDIO_SEL); + reg_280 |= i << SCU_CLKSRC1_SDIO_DIV_SHIFT; + writel(reg_280, &scu->clk_sel1); +} + +static u32 +ast2700_soc1_get_uart_clk_rate(struct ast2700_scu1 *scu, int uart_idx) +{ + u32 rate = 0; + + if (readl(&scu->clk_sel1) & BIT(uart_idx)) + rate = ast2700_soc1_get_uart_huxclk_rate(scu); + else + rate = ast2700_soc1_get_uart_uxclk_rate(scu); + + return rate; +} + +static ulong ast2700_soc1_clk_get_rate(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + struct ast2700_scu1 *scu = (struct ast2700_scu1 *)priv->reg; + ulong rate = 0; + + switch (clk->id) { + case SCU1_CLK_HPLL: + case SCU1_CLK_APLL: + case SCU1_CLK_DPLL: + rate = ast2700_soc1_get_pll_rate(scu, clk->id); + break; + case SCU1_CLK_AHB: + rate = ast2700_soc1_get_hclk_rate(scu); + break; + case SCU1_CLK_APB: + rate = ast2700_soc1_get_pclk_rate(scu); + break; + case SCU1_CLK_GATE_UART0CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 0); + break; + case SCU1_CLK_GATE_UART1CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 1); + break; + case SCU1_CLK_GATE_UART2CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 2); + break; + case SCU1_CLK_GATE_UART3CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 3); + break; + case SCU1_CLK_GATE_UART5CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 5); + break; + case SCU1_CLK_GATE_UART6CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 6); + break; + case SCU1_CLK_GATE_UART7CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 7); + break; + case SCU1_CLK_GATE_UART8CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 8); + break; + case SCU1_CLK_GATE_UART9CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 9); + break; + case SCU1_CLK_GATE_UART10CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 10); + break; + case SCU1_CLK_GATE_UART11CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 11); + break; + case SCU1_CLK_GATE_UART12CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 12); + break; + case SCU1_CLK_GATE_SDCLK: + rate = ast2700_soc1_get_sdio_clk_rate(scu); + break; + case SCU1_CLK_UXCLK: + rate = ast2700_soc1_get_uart_uxclk_rate(scu); + break; + case SCU1_CLK_HUXCLK: + rate = ast2700_soc1_get_uart_huxclk_rate(scu); + break; + default: + debug("%s: unknown clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +} + +static int ast2700_soc1_clk_enable(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + struct ast2700_scu1 *scu = (struct ast2700_scu1 *)priv->reg; + u32 clkgate_bit; + + if (clk->id >= 32) + clkgate_bit = BIT(clk->id - 32); + else + clkgate_bit = BIT(clk->id); + + writel(clkgate_bit, &scu->clkgate_clr1); + + return 0; +} + +static const struct clk_ops ast2700_soc1_clk_ops = { + .get_rate = ast2700_soc1_clk_get_rate, + .enable = ast2700_soc1_clk_enable, +}; + +#define SCU_HW_REVISION_ID GENMASK(23, 16) +#define SCU_CPUCLK_MASK GENMASK(4, 2) +#define SCU_CPUCLK_SHIFT 2 +static u32 ast2700_soc0_get_hpll_rate(struct ast2700_scu0 *scu) +{ + u32 chip_id1 = readl(&scu->chip_id1); + u32 hwstrap1 = readl(&scu->hwstrap1); + union ast2700_pll_reg pll_reg; + u32 mul = 1, div = 1; + u32 rate; + + pll_reg.w = readl(&scu->hpll); + + if ((chip_id1 & SCU_HW_REVISION_ID) && (hwstrap1 & BIT(3))) { + switch ((hwstrap1 & GENMASK(4, 2)) >> 2) { + case 2: + rate = 1800000000; + break; + case 3: + rate = 1700000000; + break; + case 6: + rate = 1200000000; + break; + case 7: + rate = 800000000; + break; + default: + rate = 1600000000; + } + } else if (hwstrap1 & GENMASK(3, 2)) { + switch ((hwstrap1 & GENMASK(3, 2)) >> 2) { + case 1U: + rate = 1900000000; + break; + case 2U: + rate = 1800000000; + break; + case 3U: + rate = 1700000000; + break; + default: + rate = 1600000000; + break; + } + } else { + if (pll_reg.b.bypass == 0U) { + /* F = 25Mhz * [(M + 2) / 2 * (n + 1)] / (p + 1) */ + mul = (pll_reg.b.m + 1) / ((pll_reg.b.n + 1) * 2); + div = (pll_reg.b.p + 1); + } + rate = ((CLKIN_25M * mul) / div); + } + + return rate; +} + +static u32 ast2700_soc0_get_pll_rate(struct ast2700_scu0 *scu, int pll_idx) +{ + union ast2700_pll_reg pll_reg; + u32 mul = 1, div = 1; + u32 rate; + + switch (pll_idx) { + case SCU0_CLK_DPLL: + pll_reg.w = readl(&scu->dpll); + break; + case SCU0_CLK_MPLL: + pll_reg.w = readl(&scu->mpll); + break; + default: + pr_err("%s: invalid PSP clock source (%d)\n", __func__, pll_idx); + return 0; + } + + if (pll_reg.b.bypass == 0U) { + if (pll_idx == SCU0_CLK_MPLL) { + /* F = 25Mhz * [M / (n + 1)] / (p + 1) */ + mul = (pll_reg.b.m) / ((pll_reg.b.n + 1)); + div = (pll_reg.b.p + 1); + } else { + /* F = 25Mhz * [(M + 2) / 2 * (n + 1)] / (p + 1) */ + mul = (pll_reg.b.m + 1) / ((pll_reg.b.n + 1) * 2); + div = (pll_reg.b.p + 1); + } + } + + rate = ((CLKIN_25M * mul) / div); + + return rate; +} + +/* + * AST2700A1 + * SCU010[4:2]: + * 000: CPUCLK=MPLL=1.6GHz (MPLL default setting with SCU310, SCU314) + * 001: CPUCLK=HPLL=2.0GHz (HPLL default setting with SCU300, SCU304) + * 010: CPUCLK=HPLL=1.8GHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + * 011: CPUCLK=HPLL=1.7GHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + * 100: CPUCLK=MPLL/2=800MHz (MPLL default setting with SCU310, SCU314) + * 101: CPUCLK=HPLL/2=1.0GHz (HPLL default setting with SCU300, SCU304) + * 110: CPUCLK=HPLL=1.2GHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + * 111: CPUCLK=HPLL=800MHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + */ + +static u32 ast2700_soc0_get_pspclk_rate(struct ast2700_scu0 *scu) +{ + u32 chip_id1 = readl(&scu->chip_id1); + u32 hwstrap1 = readl(&scu->hwstrap1); + u32 rate; + int cpuclk_set; + + if (chip_id1 & SCU_HW_REVISION_ID) { + cpuclk_set = (hwstrap1 & SCU_CPUCLK_MASK) >> SCU_CPUCLK_SHIFT; + switch (cpuclk_set) { + case 0: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + break; + case 1: + case 2: + case 3: + case 6: + case 7: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + case 4: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 2; + break; + case 5: + rate = ast2700_soc0_get_hpll_rate(scu) / 2; + break; + default: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + } + } else { + if (hwstrap1 & BIT(4)) + rate = ast2700_soc0_get_hpll_rate(scu); + else + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + } + return rate; +} + +static u32 ast2700_soc0_get_axi0clk_rate(struct ast2700_scu0 *scu) +{ + return ast2700_soc0_get_pspclk_rate(scu) / 2; +} + +#define SCU_AHB_DIV_MASK GENMASK(6, 5) +#define SCU_AHB_DIV_SHIFT 5 +static u32 hclk_ast2700a1_div_table[] = { + 6, 5, 4, 7, +}; + +static u32 ast2700_soc0_get_hclk_rate(struct ast2700_scu0 *scu) +{ + u32 hwstrap1 = readl(&scu->hwstrap1); + u32 chip_id1 = readl(&scu->chip_id1); + u32 src_clk; + int div; + + if (chip_id1 & SCU_HW_REVISION_ID) { + if (hwstrap1 & BIT(7)) + src_clk = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + else + src_clk = ast2700_soc0_get_hpll_rate(scu); + + div = (hwstrap1 & SCU_AHB_DIV_MASK) >> SCU_AHB_DIV_SHIFT; + div = hclk_ast2700a1_div_table[div]; + } else { + if (hwstrap1 & BIT(7)) + src_clk = ast2700_soc0_get_hpll_rate(scu); + else + src_clk = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + + div = (hwstrap1 & SCU_AHB_DIV_MASK) >> SCU_AHB_DIV_SHIFT; + + if (!div) + div = 4; + else + div = (div + 1) * 2; + } + return (src_clk / div); +} + +static u32 ast2700_soc0_get_axi1clk_rate(struct ast2700_scu0 *scu) +{ + if (readl(&scu->chip_id1) & SCU_HW_REVISION_ID) + return ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 4; + else + return ast2700_soc0_get_hclk_rate(scu); +} + +#define SCU0_CLKSEL1_PCLK_DIV_MASK GENMASK(25, 23) +#define SCU0_CLKSEL1_PCLK_DIV_SHIFT 23 + +static u32 ast2700_soc0_get_pclk_rate(struct ast2700_scu0 *scu) +{ + u32 rate = ast2700_soc0_get_axi0clk_rate(scu); + u32 clksel1 = readl(&scu->clk_sel1); + int div; + + div = (clksel1 & SCU0_CLKSEL1_PCLK_DIV_MASK) >> + SCU0_CLKSEL1_PCLK_DIV_SHIFT; + + return (rate / ((div + 1) * 2)); +} + +#define SCU_CLKSEL1_MPHYCLK_SEL_MASK GENMASK(19, 18) +#define SCU_CLKSEL1_MPHYCLK_SEL_SHIFT 18 +#define SCU_CLKSEL1_MPHYCLK_DIV_MASK GENMASK(7, 0) +static u32 ast2700_soc0_get_mphyclk_rate(struct ast2700_scu0 *scu) +{ + int div = readl(&scu->mphyclk_para) & SCU_CLKSEL1_MPHYCLK_DIV_MASK; + u32 chip_id1 = readl(&scu->chip_id1); + u32 clk_sel2; + int clk_sel; + u32 rate = 0; + + if (chip_id1 & SCU_HW_REVISION_ID) { + clk_sel2 = readl(&scu->clk_sel2); + clk_sel = (clk_sel2 & SCU_CLKSEL1_MPHYCLK_SEL_MASK) + >> SCU_CLKSEL1_MPHYCLK_SEL_SHIFT; + switch (clk_sel) { + case 0: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + break; + case 1: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + case 2: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_DPLL); + break; + case 3: + rate = 26000000; + break; + } + } else { + rate = ast2700_soc0_get_hpll_rate(scu); + } + + return (rate / (div + 1)); +} + +static void ast2700_mphy_clk_init(struct ast2700_scu0 *scu) +{ + u32 clksrc1, rate = 0; + int i; + + /* set mphy clk */ + if (readl(&scu->chip_id1) & SCU_HW_REVISION_ID) { + clksrc1 = (readl(&scu->clk_sel2) & SCU_CLKSEL1_MPHYCLK_SEL_MASK) + >> SCU_CLKSEL1_MPHYCLK_SEL_SHIFT; + switch (clksrc1) { + case 0: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + break; + case 1: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + case 2: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_DPLL); + break; + case 3: + rate = 26000000; + break; + } + } else { + rate = ast2700_soc0_get_hpll_rate(scu); + } + + for (i = 1; i < 256; i++) { + if ((rate / i) <= 26000000) + break; + } + + /* register defined the value plus 1 is divider*/ + i--; + writel(i, &scu->mphyclk_para); +} + +#define SCU_CLKSRC1_EMMC_DIV_MASK GENMASK(14, 12) +#define SCU_CLKSRC1_EMMC_DIV_SHIFT 12 +#define SCU_CLKSRC1_EMMC_SEL BIT(11) +static u32 ast2700_soc0_get_emmcclk_rate(struct ast2700_scu0 *scu) +{ + u32 clksel1 = readl(&scu->clk_sel1); + u32 rate; + int div; + + div = (clksel1 & SCU_CLKSRC1_EMMC_DIV_MASK) >> SCU_CLKSRC1_EMMC_DIV_SHIFT; + + if (clksel1 & SCU_CLKSRC1_EMMC_SEL) + rate = ast2700_soc0_get_hpll_rate(scu) / 4; + else + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 4; + + return (rate / ((div + 1) * 2)); +} + +static void ast2700_emmc_init(struct ast2700_scu0 *scu) +{ + u32 clksrc1, rate, div; + int i; + + /* set clk/cmd driving */ + writel(2, &scu->gpio18d0_ioctrl); /* clk driving */ + writel(1, &scu->gpio18d1_ioctrl); /* cmd driving */ + writel(1, &scu->gpio18d2_ioctrl); /* data0 driving */ + writel(1, &scu->gpio18d3_ioctrl); /* data1 driving */ + writel(1, &scu->gpio18d4_ioctrl); /* data2 driving */ + writel(1, &scu->gpio18d5_ioctrl); /* data2 driving */ + + /* emmc clk: set clk src mpll/4:400Mhz */ + clksrc1 = readl(&scu->clk_sel1); + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 4; + for (i = 0; i < 8; i++) { + div = (i + 1) * 2; + if ((rate / div) <= 200000000) + break; + } + + clksrc1 &= ~(SCU_CLKSRC1_EMMC_DIV_MASK | SCU_CLKSRC1_EMMC_SEL); + clksrc1 |= (i << SCU_CLKSRC1_EMMC_DIV_SHIFT); + writel(clksrc1, &scu->clk_sel1); +} + +static void ast2700_vga_clk_init(struct ast2700_scu0 *scu) +{ + if ((readl(&scu->chip_id1) & SCU_HW_REVISION_ID) == 0) + return; + + // Use d0clk/d1clk which generated from hpll for vga0/1 after A0 + // Use CRT1clk as soc display source + setbits_le32(&scu->clk_sel3, BIT(14) | BIT(13) | BIT(12)); +} + +static u32 ast2700_soc0_get_uartclk_rate(struct ast2700_scu0 *scu) +{ + u32 clksel2 = readl(&scu->clk_sel2); + u32 div = 1; + u32 rate; + + if (clksel2 & BIT(15)) + rate = 192000000; + else + rate = 24000000; + + if (clksel2 & BIT(30)) + div = 13; + return (rate / div); +} + +static ulong ast2700_soc0_clk_get_rate(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + switch (clk->id) { + case SCU0_CLK_PSP: + rate = ast2700_soc0_get_pspclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_HPLL: + rate = ast2700_soc0_get_hpll_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_DPLL: + case SCU0_CLK_MPLL: + rate = ast2700_soc0_get_pll_rate((struct ast2700_scu0 *)priv->reg, clk->id); + break; + case SCU0_CLK_AXI0: + rate = ast2700_soc0_get_axi0clk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_AXI1: + rate = ast2700_soc0_get_axi1clk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_AHB: + rate = ast2700_soc0_get_hclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_APB: + rate = ast2700_soc0_get_pclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_GATE_EMMCCLK: + rate = ast2700_soc0_get_emmcclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_GATE_UART4CLK: + rate = ast2700_soc0_get_uartclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_MPHY: + rate = ast2700_soc0_get_mphyclk_rate((struct ast2700_scu0 *)priv->reg); + break; + default: + debug("%s: unknown clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +} + +static int ast2700_soc0_clk_enable(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + struct ast2700_scu0 *scu = (struct ast2700_scu0 *)priv->reg; + u32 clkgate_bit = BIT(clk->id); + + writel(clkgate_bit, &scu->clkgate_clr); + + return 0; +} + +static const struct clk_ops ast2700_soc0_clk_ops = { + .get_rate = ast2700_soc0_clk_get_rate, + .enable = ast2700_soc0_clk_enable, +}; + +static void ast2700_init_mac_clk(struct ast2700_scu1 *scu) +{ + u32 src_clk = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 reg_280; + u8 div_idx; + + /* The MAC source clock selects HPLL only, and the default clock + * setting is 200 Mhz. + * Calculate the corresponding divider: + * 1: div 2 + * 2: div 3 + * ... + * 7: div 8 + */ + for (div_idx = 1; div_idx <= 7; div_idx++) + if (DIV_ROUND_UP(src_clk, div_idx + 1) == 200000000) + break; + + if (div_idx == 8) { + pr_err("MAC clock cannot divide to 200 MHz\n"); + return; + } + + /* set HPLL clock divider */ + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~GENMASK(31, 29); + reg_280 |= div_idx << 29; + writel(reg_280, &scu->clk_sel1); +} + +static void ast2700_init_rgmii_clk(struct ast2700_scu1 *scu) +{ + u32 reg_284 = readl(&scu->clk_sel2); + u32 src_clk = ast2700_soc1_get_pll_rate(scu, RGMII_DEFAULT_CLK_SRC); + + if (RGMII_DEFAULT_CLK_SRC == SCU1_CLK_HPLL) { + u32 reg_280; + u8 div_idx; + + /* Calculate the corresponding divider: + * 1: div 4 + * 2: div 6 + * ... + * 7: div 16 + */ + for (div_idx = 1; div_idx <= 7; div_idx++) { + u8 div = 4 + 2 * (div_idx - 1); + + if (DIV_ROUND_UP(src_clk, div) == 125000000) + break; + } + if (div_idx == 8) { + pr_err("RGMII using HPLL cannot divide to 125 MHz\n"); + return; + } + + /* set HPLL clock divider */ + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~GENMASK(27, 25); + reg_280 |= div_idx << 25; + writel(reg_280, &scu->clk_sel1); + + /* select HPLL clock source */ + reg_284 &= ~BIT(18); + } else { + /* APLL clock divider is fixed to 8 */ + if (DIV_ROUND_UP(src_clk, 8) != 125000000) { + pr_err("RGMII using APLL cannot divide to 125 MHz\n"); + return; + } + + /* select APLL clock source */ + reg_284 |= BIT(18); + } + + writel(reg_284, &scu->clk_sel2); +} + +static void ast2700_init_rmii_clk(struct ast2700_scu1 *scu) +{ + u32 src_clk = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 reg_280; + u8 div_idx; + + /* The RMII source clock selects HPLL only. + * Calculate the corresponding divider: + * 1: div 8 + * 2: div 12 + * ... + * 7: div 32 + */ + for (div_idx = 1; div_idx <= 7; div_idx++) { + u8 div = 8 + 4 * (div_idx - 1); + + if (DIV_ROUND_UP(src_clk, div) == 50000000) + break; + } + if (div_idx == 8) { + pr_err("RMII using HPLL cannot divide to 50 MHz\n"); + return; + } + + /* set RMII clock divider */ + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~GENMASK(23, 21); + reg_280 |= div_idx << 21; + writel(reg_280, &scu->clk_sel1); +} + +static void ast2700_init_spi(struct ast2700_scu1 *scu) +{ + writel(readl(&scu->io_driving8) | 0x0000aaaa, &scu->io_driving8); /* fwspi driving */ + writel(readl(&scu->io_driving3) | 0x00000aaa, &scu->io_driving3); /* spi0 driving */ + writel(readl(&scu->io_driving3) | 0x0aaa0000, &scu->io_driving3); /* spi1 driving */ + writel(readl(&scu->io_driving4) | 0x00002aaa, &scu->io_driving4); /* spi2 driving */ +} + +#define SCU1_CLK_I3C_DIV_MASK GENMASK(25, 23) +#define SCU1_CLK_I3C_DIV(n) ((n) - 1) +static void ast2700_init_i3c_clk(struct ast2700_scu1 *scu) +{ + u32 reg_284; + + /* I3C 250MHz = HPLL/4 */ + reg_284 = readl(&scu->clk_sel2); + reg_284 &= ~SCU1_CLK_I3C_DIV_MASK; + reg_284 |= FIELD_PREP(SCU1_CLK_I3C_DIV_MASK, SCU1_CLK_I3C_DIV(4)); + writel(reg_284, &scu->clk_sel2); +} + +static int ast2700_clk1_init(struct udevice *dev) +{ + struct ast2700_clk_priv *priv = dev_get_priv(dev); + struct ast2700_scu1 *scu = (struct ast2700_scu1 *)priv->reg; + + ast2700_init_spi(scu); + ast2700_init_mac_clk(scu); + ast2700_init_rgmii_clk(scu); + ast2700_init_rmii_clk(scu); + ast2700_init_sdclk(scu); + ast2700_init_i3c_clk(scu); + + return 0; +} + +static int ast2700_clk0_init(struct udevice *dev) +{ + struct ast2700_clk_priv *priv = dev_get_priv(dev); + struct ast2700_scu0 *scu = (struct ast2700_scu0 *)priv->reg; + + ast2700_emmc_init(scu); + ast2700_mphy_clk_init(scu); + ast2700_vga_clk_init(scu); + + return 0; +} + +static int ast2700_clk_probe(struct udevice *dev) +{ + struct ast2700_clk_priv *priv = dev_get_priv(dev); + + priv->init = (ast2700_clk_init_fn)dev_get_driver_data(dev); + priv->reg = (void __iomem *)dev_read_addr_ptr(dev); + + if (priv->init) + return priv->init(dev); + + return 0; +} + +static int ast2700_clk_bind(struct udevice *dev) +{ + struct udevice *sysreset_dev, *rst_dev; + int ret; + + /* The system reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &sysreset_dev); + if (ret) + debug("Warning: No sysreset driver: ret = %d\n", ret); + + /* Bind the per-SCU reset controller to the same ofnode so that + * <&syscon0/1 RESET_X> phandle references resolve to a UCLASS_RESET + * device. This pairs with the airoha-style binding pattern. + */ + if (CONFIG_IS_ENABLED(RESET_AST2700)) { + ret = device_bind_driver_to_node(dev, "ast2700_reset", "reset", + dev_ofnode(dev), &rst_dev); + if (ret) + debug("Warning: failed to bind reset controller: ret = %d\n", ret); + } + + return 0; +} + +static const struct udevice_id ast2700_soc1_clk_ids[] = { + { .compatible = "aspeed,ast2700-scu1", .data = (ulong)&ast2700_clk1_init }, + { }, +}; + +U_BOOT_DRIVER(aspeed_ast2700_soc1_clk) = { + .name = "aspeed_ast2700_scu1", + .id = UCLASS_CLK, + .of_match = ast2700_soc1_clk_ids, + .priv_auto = sizeof(struct ast2700_clk_priv), + .ops = &ast2700_soc1_clk_ops, + .probe = ast2700_clk_probe, + .bind = ast2700_clk_bind, +}; + +static const struct udevice_id ast2700_soc0_clk_ids[] = { + { .compatible = "aspeed,ast2700-scu0", .data = (ulong)&ast2700_clk0_init }, + { }, +}; + +U_BOOT_DRIVER(aspeed_ast2700_soc0_clk) = { + .name = "aspeed_ast2700_scu0", + .id = UCLASS_CLK, + .of_match = ast2700_soc0_clk_ids, + .priv_auto = sizeof(struct ast2700_clk_priv), + .ops = &ast2700_soc0_clk_ops, + .probe = ast2700_clk_probe, + .bind = ast2700_clk_bind, +}; diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 2251e2846fa..0d0e39db57e 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -426,7 +426,7 @@ static const struct pmc_clk_setup sam9x60_clk_setup[] = { static int sam9x60_clk_probe(struct udevice *dev) { - void __iomem *base = (void *)devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); unsigned int *clkmuxallocs[64], *muxallocs[64]; const char *p[10]; unsigned int cm[10], m[10], *tmpclkmux, *tmpmux; diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index 9ea253e6ff8..93f899b6617 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -817,7 +817,7 @@ static const struct { static int sam9x7_clk_probe(struct udevice *dev) { - void __iomem *base = (void *)devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); unsigned int *clkmuxallocs[64], *muxallocs[64]; const char *p[10]; unsigned int cm[10], m[10], *tmpclkmux, *tmpmux; diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 9f0b394543b..0c17a8cf67b 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1176,7 +1176,7 @@ static const struct pmc_clk_setup sama7d65_clk_setup[] = { static int sama7d65_clk_probe(struct udevice *dev) { - void __iomem *base = (void *)devfdt_get_addr(dev); + void __iomem *base = dev_read_addr_ptr(dev); unsigned int *clkmuxallocs[SAMA7D65_MAX_MUX_ALLOCS]; unsigned int *muxallocs[SAMA7D65_MAX_MUX_ALLOCS]; const char *p[12]; @@ -1185,8 +1185,8 @@ static int sama7d65_clk_probe(struct udevice *dev) bool main_osc_bypass; int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j; - if (IS_ERR(base)) - return PTR_ERR(base); + if (!base) + return -EINVAL; memset(muxallocs, 0, ARRAY_SIZE(muxallocs)); memset(clkmuxallocs, 0, ARRAY_SIZE(clkmuxallocs)); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index f24d251857f..c436038aed2 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -1109,7 +1109,7 @@ static const struct pmc_clk_setup sama7g5_clk_setup[] = { static int sama7g5_clk_probe(struct udevice *dev) { - void __iomem *base = devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); unsigned int *clkmuxallocs[SAMA7G5_MAX_MUX_ALLOCS]; unsigned int *muxallocs[SAMA7G5_MAX_MUX_ALLOCS]; const char *p[10]; @@ -1118,8 +1118,8 @@ static int sama7g5_clk_probe(struct udevice *dev) bool main_osc_bypass; int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j; - if (IS_ERR(base)) - return PTR_ERR(base); + if (!base) + return -EINVAL; memset(muxallocs, 0, sizeof(muxallocs)); memset(clkmuxallocs, 0, sizeof(clkmuxallocs)); diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index dcaffd360fd..410bc088248 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -124,12 +124,15 @@ U_BOOT_DRIVER(at91_sam9x60_td_slck) = { static int at91_sam9x60_sckc_probe(struct udevice *dev) { struct sam9x60_sckc *sckc = dev_get_priv(dev); - void __iomem *base = devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); const char *slow_rc_osc, *slow_osc; const char *parents[2]; struct clk *clk, c; int ret; + if (!base) + return -EINVAL; + ret = clk_get_by_index(dev, 0, &c); if (ret) return ret; diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index e692b9c2167..d30786a9e6c 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -228,20 +228,30 @@ static struct clk *_register_divider(struct udevice *dev, const char *name, return clk; } -struct clk *clk_register_divider(struct udevice *dev, const char *name, +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags) + u8 clk_divider_flags, const struct clk_div_table *table) { struct clk *clk; clk = _register_divider(dev, name, parent_name, flags, reg, shift, - width, clk_divider_flags, NULL); + width, clk_divider_flags, table); if (IS_ERR(clk)) return ERR_CAST(clk); return clk; } +struct clk *clk_register_divider(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags) +{ + return clk_register_divider_table(dev, name, parent_name, flags, reg, + shift, width, clk_divider_flags, + NULL); +} + U_BOOT_DRIVER(ccf_clk_divider) = { .name = UBOOT_DM_CLK_CCF_DIVIDER, .id = UCLASS_CLK, diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index 53655059279..dbc926a4391 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -753,11 +753,11 @@ static int hsdk_cgu_clk_probe(struct udevice *dev) else hsdk_clk->map = hsdk_4xd_clk_map; - hsdk_clk->cgu_regs = devfdt_get_addr_index_ptr(dev, 0); + hsdk_clk->cgu_regs = dev_read_addr_index_ptr(dev, 0); if (!hsdk_clk->cgu_regs) return -EINVAL; - hsdk_clk->creg_regs = devfdt_get_addr_index_ptr(dev, 1); + hsdk_clk->creg_regs = dev_read_addr_index_ptr(dev, 1); if (!hsdk_clk->creg_regs) return -EINVAL; diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c index 117266ac778..4a6c71016da 100644 --- a/drivers/clk/clk-stub.c +++ b/drivers/clk/clk-stub.c @@ -49,11 +49,13 @@ static struct clk_ops stub_clk_ops = { }; static const struct udevice_id stub_clk_ids[] = { + { .compatible = "qcom,qcs615-rpmh-clk" }, { .compatible = "qcom,rpmcc" }, - { .compatible = "qcom,sdm670-rpmh-clk" }, - { .compatible = "qcom,sdm845-rpmh-clk" }, + { .compatible = "qcom,sa8775p-rpmh-clk" }, { .compatible = "qcom,sc7180-rpmh-clk" }, { .compatible = "qcom,sc7280-rpmh-clk" }, + { .compatible = "qcom,sdm670-rpmh-clk" }, + { .compatible = "qcom,sdm845-rpmh-clk" }, { .compatible = "qcom,sm6350-rpmh-clk" }, { .compatible = "qcom,sm8150-rpmh-clk" }, { .compatible = "qcom,sm8250-rpmh-clk" }, diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index f57ac79f8ca..846b8011f5c 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -9,6 +9,7 @@ #include <log.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <dm/of_access.h> #include <dt-bindings/clock/imx6qdl-clock.h> #include "clk.h" @@ -46,6 +47,33 @@ static struct clk_ops imx6q_clk_ops = { .disable = ccf_clk_disable, }; +static const char *const pll_bypass_src_sels[] = { + "osc", + "lvds1_in", + "lvds2_in", + "dummy", +}; + +static const char *const pll2_bypass_sels[] = { + "pll2", + "pll2_bypass_src", +}; + +static const char *const pll3_bypass_sels[] = { + "pll3", + "pll3_bypass_src", +}; + +static const char *const pll5_bypass_sels[] = { + "pll5", + "pll5_bypass_src", +}; + +static const char *const pll6_bypass_sels[] = { + "pll6", + "pll6_bypass_src", +}; + static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", @@ -72,6 +100,23 @@ static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; + +static const struct clk_div_table post_div_table[] = { + { .val = 2, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 0, .div = 4, }, + { /* sentinel */ } +}; + +static const struct clk_div_table video_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 1, }, + { .val = 3, .div = 4, }, + { /* sentinel */ } +}; + +#if CONFIG_IS_ENABLED(VIDEO) static const char *const ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", @@ -113,6 +158,122 @@ static const char *ipu2_di1_sels_2[] = { static unsigned int share_count_mipi_core_cfg; +static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel, + int *ldb_di1_sel) +{ + struct ofnode_phandle_args clk_args, parent_args; + ofnode node = dev_ofnode(dev); + int count, err; + + count = dev_count_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0); + if (count <= 0) { + if (count == 0) + debug("%s: no assigned_clocks found\n", dev->name); + else + pr_err("%s: failed to get phandle count (%d)\n", + dev->name, count); + return; + } + + for (int i = 0; i < count; i++) { + err = dev_read_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0, i, + &clk_args); + if (err == -ENOENT) + /* Skip empty handles */ + continue; + else if (err < 0) + return; + + if (!ofnode_equal(clk_args.node, node) || + clk_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: clock %d not in ccm\n", dev->name, i); + return; + } + + err = dev_read_phandle_with_args(dev, "assigned-clock-parents", + "#clock-cells", 0, i, + &parent_args); + if (err < 0) + return; + + if (!ofnode_equal(parent_args.node, node) || + parent_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: parent clock %d not in ccm\n", dev->name, + i); + return; + } + + if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI0_SEL) + *ldb_di0_sel = parent_args.args[0]; + else if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI1_SEL) + *ldb_di1_sel = parent_args.args[0]; + } +} + +static void imx6q_init_ldb_clks(struct udevice *dev) +{ + int ldb_di_sel[] = { IMX6QDL_CLK_END, IMX6QDL_CLK_END }; + enum ldb_di_clock ldb_di_clk[] = { MXC_MMDC_CH1_CLK, MXC_MMDC_CH1_CLK }; + + of_assigned_ldb_sels(dev, &ldb_di_sel[0], &ldb_di_sel[1]); + for (int i = 0; i < 2; i++) { + switch (ldb_di_sel[i]) { + case IMX6QDL_CLK_PLL5_VIDEO_DIV: + ldb_di_clk[i] = MXC_PLL5_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD0_352M: + ldb_di_clk[i] = MXC_PLL2_PFD0_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD2_396M: { + struct clk *clk, *parent; + + int err = clk_get_by_id(IMX6QDL_CLK_PERIPH_PRE, &clk); + + if (err) { + pr_err("%s: failed to get periph_pre clock " + "(%d)\n", + dev->name, err); + return; + } + + err = clk_get_by_id(IMX6QDL_CLK_PLL2_PFD2_396M, + &parent); + if (err) { + pr_err("%s: failed to get pll2_pfd2_396m clock" + " (%d)\n", + dev->name, err); + return; + } + + if (parent == clk) { + pr_err("%s: ldb_di%d_sel: couldn't disable " + "pll2_pfd2_396m clock\n", + dev->name, i); + return; + } + + ldb_di_clk[i] = MXC_PLL2_PFD2_CLK; + break; + } + case IMX6QDL_CLK_MMDC_CH1_AXI: + case IMX6QDL_CLK_END: + /* use the default clock */ + break; + case IMX6QDL_CLK_PLL3_USB_OTG: + ldb_di_clk[i] = MXC_PLL3_SW_CLK; + break; + default: + pr_err("%s: invalid LDB clock parent\n", dev->name); + return; + } + } + + select_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]); +} +#endif /* CONFIG_IS_ENABLED(VIDEO) */ + static int imx6q_clk_probe(struct udevice *dev) { void *base; @@ -120,26 +281,70 @@ static int imx6q_clk_probe(struct udevice *dev) /* Anatop clocks */ base = (void *)ANATOP_BASE_ADDR; - clk_dm(IMX6QDL_CLK_PLL2, - imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc", - base + 0x30, 0x1)); + clk_dm(IMX6QDL_PLL2_BYPASS_SRC, + imx_clk_mux(dev, "pll2_bypass_src", base + 0x30, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL3_BYPASS_SRC, + imx_clk_mux(dev, "pll3_bypass_src", base + 0x10, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL5_BYPASS_SRC, + imx_clk_mux(dev, "pll5_bypass_src", base + 0xa0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL6_BYPASS_SRC, + imx_clk_mux(dev, "pll6_bypass_src", base + 0xe0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + + clk_dm(IMX6QDL_CLK_PLL2, imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2", + "osc", base + 0x30, 0x1)); + clk_dm(IMX6QDL_CLK_PLL3, imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3", + "osc", base + 0x10, 0x3)); + clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", + base + 0xa0, 0x7f)); + clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", + "osc", base + 0xe0, 0x3)); + + clk_dm(IMX6QDL_PLL2_BYPASS, + imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, + pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL3_BYPASS, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, + pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL5_BYPASS, + imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1, + pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL6_BYPASS, + imx_clk_mux_flags(dev, "pll6_bypass", base + 0xe0, 16, 1, + pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), + CLK_SET_RATE_PARENT)); + + SET_CLK_PARENT(IMX6QDL_PLL2_BYPASS, IMX6QDL_CLK_PLL2); + SET_CLK_PARENT(IMX6QDL_PLL3_BYPASS, IMX6QDL_CLK_PLL3); + SET_CLK_PARENT(IMX6QDL_PLL5_BYPASS, IMX6QDL_CLK_PLL5); + SET_CLK_PARENT(IMX6QDL_PLL6_BYPASS, IMX6QDL_CLK_PLL6); + + clk_dm(IMX6QDL_CLK_PLL2_BUS, + imx_clk_gate(dev, "pll2_bus", "pll2_bypass", base + 0x30, 13)); clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, - imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", - base + 0x10, 0x3)); + imx_clk_gate(dev, "pll3_usb_otg", "pll3_bypass", base + 0x10, + 13)); + clk_dm(IMX6QDL_CLK_PLL5_VIDEO, + imx_clk_gate(dev, "pll5_video", "pll5_bypass", base + 0xa0, 13)); + clk_dm(IMX6QDL_CLK_PLL6_ENET, + imx_clk_gate(dev, "pll6_enet", "pll6_bypass", base + 0xe0, 13)); + clk_dm(IMX6QDL_CLK_PLL3_60M, imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL3_80M, imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMX6QDL_CLK_PLL3_120M, imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4)); - clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", - base + 0xa0, 0x7f)); - clk_dm(IMX6QDL_CLK_PLL5_VIDEO, - imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13)); - clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", - "osc", base + 0xe0, 0x3)); - clk_dm(IMX6QDL_CLK_PLL6_ENET, - imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); @@ -151,10 +356,14 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PLL2_198M, imx_clk_fixed_factor(dev, "pll2_198m", "pll2_pfd2_396m", 1, 2)); clk_dm(IMX6QDL_CLK_PLL5_POST_DIV, - imx_clk_fixed_factor(dev, "pll5_post_div", "pll5_video", 1, 1)); + clk_register_divider_table(dev, "pll5_post_div", "pll5_video", + CLK_SET_RATE_PARENT, base + 0xa0, 19, + 2, 0, post_div_table)); clk_dm(IMX6QDL_CLK_PLL5_VIDEO_DIV, - imx_clk_fixed_factor(dev, "pll5_video_div", "pll5_post_div", 1, - 1)); + clk_register_divider_table(dev, "pll5_video_div", + "pll5_post_div", CLK_SET_RATE_PARENT, + base + 0x170, 30, 2, 0, + video_div_table)); clk_dm(IMX6QDL_CLK_VIDEO_27M, imx_clk_fixed_factor(dev, "video_27m", "pll3_pfd1_540m", 1, 20)); @@ -263,6 +472,7 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22)); +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_IPU1_SEL, imx_clk_mux(dev, "ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels))); @@ -279,9 +489,12 @@ static int imx6q_clk_probe(struct udevice *dev) ldb_di_sels, ARRAY_SIZE(ldb_di_sels))); } else { /* - * Need to set these as read-only due to a hardware bug. - * Keeping default mux values. Fixed on the i.MX6 QuadPlus - */ + * Need to set these as read-only due to a hardware bug. + * Keeping default mux values. Fixed on the i.MX6 QuadPlus + * Need to set the clocks now and make them read-only due to a + * hardware bug. Fixed on the i.MX6 QuadPlus + */ + imx6q_init_ldb_clks(dev); clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), @@ -413,6 +626,7 @@ static int imx6q_clk_probe(struct udevice *dev) ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT)); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ clk_dm(IMX6QDL_CLK_ECSPI1, imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0)); @@ -453,6 +667,8 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); + +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_MIPI_CORE_CFG, imx_clk_gate2_shared(dev, "mipi_core_cfg", "video_27m", base + 0x74, 16, @@ -480,6 +696,7 @@ static int imx6q_clk_probe(struct udevice *dev) SET_CLK_PARENT(IMX6QDL_CLK_IPU1_SEL, IMX6QDL_CLK_PLL3_PFD1_540M); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ return 0; } diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig index c6afef90034..5f3b8fe8ab4 100644 --- a/drivers/clk/owl/Kconfig +++ b/drivers/clk/owl/Kconfig @@ -1,8 +1,8 @@ config CLK_OWL - bool "Actions Semi OWL clock drivers" - depends on CLK && ARCH_OWL - help - Enable support for clock managemet unit present in Actions Semi + bool "Actions Semi OWL clock drivers" + depends on CLK && ARCH_OWL + help + Enable support for clock managemet unit present in Actions Semi Owl series S900/S700 SoCs. diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0a2ce55aaa2..9ad233c83ac 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -111,6 +111,14 @@ config CLK_QCOM_SM6115 on the Snapdragon SM6115 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_SM6125 + bool "Qualcomm SM6125 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SM6125 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_SM6350 bool "Qualcomm SM6350 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b96d61b603e..c0d95a6300e 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o +obj-$(CONFIG_CLK_QCOM_SM6125) += clock-sm6125.o obj-$(CONFIG_CLK_QCOM_SM6350) += clock-sm6350.o obj-$(CONFIG_CLK_QCOM_SM7150) += clock-sm7150.o obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c index 5a599085b50..c38ff1a1e4a 100644 --- a/drivers/clk/qcom/clock-qcm2290.c +++ b/drivers/clk/qcom/clock-qcm2290.c @@ -73,7 +73,7 @@ static const struct pll_vote_clk gpll6_clk = { .status = 0x6000, .status_bit = BIT(31), .ena_vote = 0x79000, - .vote_bit = BIT(7), + .vote_bit = BIT(6), }; static const struct gate_clk qcm2290_clks[] = { diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c index 2087fc38f63..7b3fe49de9c 100644 --- a/drivers/clk/qcom/clock-qcs615.c +++ b/drivers/clk/qcom/clock-qcs615.c @@ -19,6 +19,11 @@ #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c #define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf060 +#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77020 +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x77048 +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77060 +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x7707c + #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12) @@ -33,9 +38,37 @@ #define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26) #define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27) +/* UFS PHY AXI clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), + { } +}; + +/* UFS PHY ICE CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + +/* UFS PHY UNIPRO CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0, 8, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + { } +}; + static ulong qcs615_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; if (clk->id < priv->data->num_clks) debug("%s: %s, requested rate=%ld\n", __func__, @@ -52,6 +85,24 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate) 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); return rate; + case GCC_UFS_PHY_AXI_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_UNIPRO_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_ICE_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_PHY_AUX_CLK: + clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return 19200000; default: return 0; } @@ -81,7 +132,17 @@ static const struct gate_clk qcs615_clks[] = { GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT), GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)), - GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)) + GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)), + /* UFS clocks */ + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0)), + GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)), }; static int qcs615_enable(struct clk *clk) diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c index 4957abf6f58..7eec4aeae48 100644 --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -19,6 +19,11 @@ #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028 #define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c +#define UFS_PHY_AXI_CLK_CMD_RCGR 0x8302c +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x83074 +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x830a8 +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x8308c + #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12) @@ -44,9 +49,35 @@ #define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25) +/* UFS AXI clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + +/* UFS ICE CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + +/* UFS UNIPRO CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + static ulong sa8775p_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; if (clk->id < priv->data->num_clks) debug("%s: %s, requested rate=%ld\n", __func__, @@ -63,6 +94,24 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate) 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); return rate; + case GCC_UFS_PHY_AXI_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_UNIPRO_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_ICE_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_PHY_AUX_CLK: + clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return 19200000; default: return 0; } @@ -106,6 +155,20 @@ static const struct gate_clk sa8775p_clks[] = { /* QUP Wrapper 3 clocks */ GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT), + + /* UFS PHY clocks */ + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, 1), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, 1), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, 1), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, 1), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, 1), + + /* EDP reference clock (used by UFS PHY) */ + GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, 1), }; static int sa8775p_enable(struct clk *clk) diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 01c8587ac39..91e3fcc27cb 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -23,6 +23,10 @@ #define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058 #define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c #define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054 +#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77024 +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x7706c +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x770a0 +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77084 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), @@ -54,6 +58,33 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0), + { } +}; + static ulong sc7280_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -103,6 +134,26 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate) case GCC_PCIE1_PHY_RCHNG_CLK: clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN); return 100000000; + case GCC_UFS_PHY_AXI_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_ICE_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_PHY_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_phy_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_UNIPRO_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; default: return rate; } @@ -148,6 +199,7 @@ static const struct gate_clk sc7280_clks[] = { GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)), GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)), GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)), GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)), GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)), diff --git a/drivers/clk/qcom/clock-sm6125.c b/drivers/clk/qcom/clock-sm6125.c new file mode 100644 index 00000000000..1fd72d55e88 --- /dev/null +++ b/drivers/clk/qcom/clock-sm6125.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm sm6125 + * + * (C) Copyright 2026 Biswapriyo Nath <[email protected]> + * + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/bug.h> +#include <dt-bindings/clock/qcom,gcc-sm6125.h> + +#include "clock-qcom.h" + +#define GCC_BASE 0x01400000 + +#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608 +#define SDCC1_APPS_CLK_CMD_RCGR 0x38028 +#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c + +#define GCC_GPLL0_MODE 0x0 +#define GCC_GPLL3_MODE 0x3000 +#define GCC_GPLL4_MODE 0x4000 +#define GCC_GPLL5_MODE 0x5000 +#define GCC_GPLL6_MODE 0x6000 +#define GCC_GPLL7_MODE 0x7000 +#define GCC_GPLL8_MODE 0x8000 +#define GCC_GPLL9_MODE 0x9000 + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0), + {} +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), + {} +}; + +static const struct pll_vote_clk gpll0_clk = { + .status = 0, + .status_bit = BIT(31), + .ena_vote = 0x79000, + .vote_bit = BIT(0), +}; + +static const struct gate_clk sm6125_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, BIT(0)), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, BIT(9)), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, BIT(8)), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, BIT(10)), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, BIT(11)), + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, BIT(12)), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, BIT(13)), + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, BIT(14)), + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, BIT(15)), + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, BIT(6)), + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, BIT(7)), + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, BIT(0)), + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, BIT(0)), + GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, BIT(0)), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, BIT(0)), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, BIT(0)), + GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, BIT(0)), + GATE_CLK(GCC_SYS_NOC_UFS_PHY_AXI_CLK, 0x45098, BIT(0)), + GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x45014, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x45010, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x45044, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x45078, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x4501c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x45018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x45040, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x80278, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, BIT(0)), + GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, BIT(0)), + GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)), +}; + +static ulong sm6125_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + debug("%s: clk %s rate %lu\n", __func__, sm6125_clks[clk->id].name, + rate); + + switch (clk->id) { + case GCC_QUPV3_WRAP0_S4_CLK: + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 16); + return 0; + case GCC_SDCC2_APPS_CLK: + clk_enable_gpll0(priv->base, &gpll0_clk); + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + WARN(freq->src != CFG_CLK_SRC_GPLL0, + "SDCC2_APPS_CLK_SRC not set to GPLL0, requested rate %lu\n", + rate); + clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 8); + return freq->freq; + case GCC_SDCC1_APPS_CLK: + /* The firmware turns this on for us and always sets it to this rate */ + return 384000000; + default: + return rate; + } +} + +static int sm6125_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %s\n", __func__, sm6125_clks[clk->id].name); + + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK); + break; + } + + return qcom_gate_clk_en(priv, clk->id); +} + +static const struct qcom_reset_map sm6125_gcc_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, + [GCC_UFS_PHY_BCR] = { 0x45000 }, + [GCC_USB30_PRIM_BCR] = { 0x1a000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, + [GCC_CAMSS_MICRO_BCR] = { 0x560ac }, +}; + +static const struct qcom_power_map sm6125_gdscs[] = { + [USB30_PRIM_GDSC] = { 0x1a004 }, + [UFS_PHY_GDSC] = { 0x45004 }, + [CAMSS_VFE0_GDSC] = { 0x54004 }, + [CAMSS_VFE1_GDSC] = { 0x5403c }, + [CAMSS_TOP_GDSC] = { 0x5607c }, + [CAM_CPP_GDSC] = { 0x560bc }, + [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = { 0x7d060 }, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = { 0x80074 }, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = { 0x80084 }, + [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = { 0x80094 }, +}; + +static const phys_addr_t sm6125_gpll_addrs[] = { + GCC_BASE + GCC_GPLL0_MODE, GCC_BASE + GCC_GPLL3_MODE, + GCC_BASE + GCC_GPLL4_MODE, GCC_BASE + GCC_GPLL5_MODE, + GCC_BASE + GCC_GPLL6_MODE, GCC_BASE + GCC_GPLL7_MODE, + GCC_BASE + GCC_GPLL8_MODE, GCC_BASE + GCC_GPLL9_MODE, +}; + +static const phys_addr_t sm6125_rcg_addrs[] = { + 0x0141a01c, // GCC_USB30_PRIM_MASTER_CMD_RCGR + 0x0141a034, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR + 0x0141a060, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR + 0x01438028, // GCC_SDCC1_APPS_CMD_RCGR + 0x0141e00c, // GCC_SDCC2_APPS_CMD_RCGR + 0x0141f148, // GCC_QUPV3_WRAP0_S0_CMD_RCGR + 0x0141f278, // GCC_QUPV3_WRAP0_S1_CMD_RCGR + 0x0141f3a8, // GCC_QUPV3_WRAP0_S2_CMD_RCGR + 0x0141f4d8, // GCC_QUPV3_WRAP0_S3_CMD_RCGR + 0x0141f608, // GCC_QUPV3_WRAP0_S4_CMD_RCGR + 0x0141f738, // GCC_QUPV3_WRAP0_S5_CMD_RCGR + 0x01445020, // GCC_UFS_PHY_AXI_CMD_RCGR + 0x01445048, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR + 0x01445060, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR + 0x0144507c, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR +}; + +static const char *const sm6125_rcg_names[] = { + "GCC_USB30_PRIM_MASTER_CMD_RCGR", + "GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR", + "GCC_USB3_PRIM_PHY_AUX_CMD_RCGR", + "GCC_SDCC1_APPS_CMD_RCGR", + "GCC_SDCC2_APPS_CMD_RCGR", + "GCC_QUPV3_WRAP0_S0_CMD_RCGR", + "GCC_QUPV3_WRAP0_S1_CMD_RCGR", + "GCC_QUPV3_WRAP0_S2_CMD_RCGR", + "GCC_QUPV3_WRAP0_S3_CMD_RCGR", + "GCC_QUPV3_WRAP0_S4_CMD_RCGR", + "GCC_QUPV3_WRAP0_S5_CMD_RCGR", + "GCC_UFS_PHY_AXI_CMD_RCGR", + "GCC_UFS_PHY_ICE_CORE_CMD_RCGR", + "GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR", + "GCC_UFS_PHY_PHY_AUX_CMD_RCGR", +}; + +static struct msm_clk_data sm6125_gcc_data = { + .resets = sm6125_gcc_resets, + .num_resets = ARRAY_SIZE(sm6125_gcc_resets), + .clks = sm6125_clks, + .num_clks = ARRAY_SIZE(sm6125_clks), + .power_domains = sm6125_gdscs, + .num_power_domains = ARRAY_SIZE(sm6125_gdscs), + + .enable = sm6125_enable, + .set_rate = sm6125_set_rate, + + .dbg_pll_addrs = sm6125_gpll_addrs, + .num_plls = ARRAY_SIZE(sm6125_gpll_addrs), + .dbg_rcg_addrs = sm6125_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sm6125_rcg_addrs), + .dbg_rcg_names = sm6125_rcg_names, +}; + +static const struct udevice_id gcc_sm6125_of_match[] = { + { + .compatible = "qcom,gcc-sm6125", + .data = (ulong)&sm6125_gcc_data, + }, + {} +}; + +U_BOOT_DRIVER(gcc_sm6125) = { + .name = "gcc_sm6125", + .id = UCLASS_NOP, + .of_match = gcc_sm6125_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 72f99e9fa1b..1893b6c4181 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -61,11 +61,11 @@ config CLK_RCAR_GEN3 Enable this to support the clocks on Renesas R-Car Gen3 and Gen4 SoCs. config CLK_R8A774A1 - bool "Renesas R8A774A1 clock driver" + bool "Renesas R8A774A1 clock driver" def_bool y if R8A774A1 - depends on CLK_RCAR_GEN3 - help - Enable this to support the clocks on Renesas R8A774A1 SoC. + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A774A1 SoC. config CLK_R8A774B1 bool "Renesas R8A774B1 clock driver" diff --git a/drivers/clk/sophgo/clk-cv1800b.c b/drivers/clk/sophgo/clk-cv1800b.c index d946ea57a46..248a69321fc 100644 --- a/drivers/clk/sophgo/clk-cv1800b.c +++ b/drivers/clk/sophgo/clk-cv1800b.c @@ -500,9 +500,12 @@ static int cv1800b_register_clk(struct udevice *dev) { struct clk osc; ulong osc_rate; - void *base = devfdt_get_addr_ptr(dev); + void __iomem *base = dev_read_addr_ptr(dev); int i, ret; + if (!base) + return -EINVAL; + ret = clk_get_by_index(dev, 0, &osc); if (ret) { pr_err("Failed to get clock\n"); diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 842a0541bd6..046d5d1605a 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -64,7 +64,7 @@ static int sunxi_clk_disable(struct clk *clk) return sunxi_set_gate(clk, false); } -struct clk_ops sunxi_clk_ops = { +static const struct clk_ops sunxi_clk_ops = { .enable = sunxi_clk_enable, .disable = sunxi_clk_disable, }; diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c index c5c97dc35c4..08f7410edce 100644 --- a/drivers/clk/ti/clk-ctrl.c +++ b/drivers/clk/ti/clk-ctrl.c @@ -8,7 +8,11 @@ #include <dm.h> #include <dm/device_compat.h> #include <clk-uclass.h> -#include <asm/arch-am33xx/clock.h> +#include <asm/ti-common/omap_clock.h> +#include <asm/io.h> +#include <linux/iopoll.h> + +#define TRANSITION_TIMEOUT_US 10000 struct clk_ti_ctrl_offs { fdt_addr_t start; @@ -33,10 +37,37 @@ static int clk_ti_ctrl_check_offs(struct clk *clk, fdt_addr_t offs) return -EFAULT; } +#define IDLEST_DISABLED (MODULE_CLKCTRL_IDLEST_DISABLED << MODULE_CLKCTRL_IDLEST_SHIFT) +#define IDLEST_TRANSITION (MODULE_CLKCTRL_IDLEST_TRANSITIONING << MODULE_CLKCTRL_IDLEST_SHIFT) +static int clk_ti_ctrl_disable_clock_module(u32 addr) +{ + int val; + + clrsetbits_le32(addr, MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + + return readl_relaxed_poll_timeout(addr, val, + (val & MODULE_CLKCTRL_IDLEST_MASK) == IDLEST_DISABLED, + TRANSITION_TIMEOUT_US); +} + +static int clk_ti_ctrl_enable_clock_module(u32 addr) +{ + int val; + + clrsetbits_le32(addr, MODULE_CLKCTRL_MODULEMODE_MASK, + MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << + MODULE_CLKCTRL_MODULEMODE_SHIFT); + return readl_relaxed_poll_timeout(addr, val, + ((val & MODULE_CLKCTRL_IDLEST_MASK) != IDLEST_DISABLED) && + ((val & MODULE_CLKCTRL_IDLEST_MASK) != IDLEST_TRANSITION), + TRANSITION_TIMEOUT_US); +} + static int clk_ti_ctrl_disable(struct clk *clk) { struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev); - u32 *clk_modules[2] = { }; fdt_addr_t offs; int err; @@ -47,16 +78,13 @@ static int clk_ti_ctrl_disable(struct clk *clk) return err; } - clk_modules[0] = (u32 *)(offs); - dev_dbg(clk->dev, "disable module @ %p\n", clk_modules[0]); - do_disable_clocks(NULL, clk_modules, 1); - return 0; + dev_dbg(clk->dev, "disable module @ %x\n", offs); + return clk_ti_ctrl_disable_clock_module(offs); } static int clk_ti_ctrl_enable(struct clk *clk) { struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev); - u32 *clk_modules[2] = { }; fdt_addr_t offs; int err; @@ -67,10 +95,8 @@ static int clk_ti_ctrl_enable(struct clk *clk) return err; } - clk_modules[0] = (u32 *)(offs); - dev_dbg(clk->dev, "enable module @ %p\n", clk_modules[0]); - do_enable_clocks(NULL, clk_modules, 1); - return 0; + dev_dbg(clk->dev, "enable module @ %x\n", offs); + return clk_ti_ctrl_enable_clock_module(offs); } static ulong clk_ti_ctrl_get_rate(struct clk *clk) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 5419bf65b5d..ae0c3466772 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -337,11 +337,19 @@ config SIMPLE_BUS_CORRECT_RANGE config SIMPLE_PM_BUS bool "Support simple-pm-bus driver" - depends on DM && OF_CONTROL && CLK && POWER_DOMAIN + depends on DM && OF_CONTROL && POWER_DOMAIN help Supports the 'simple-pm-bus' driver, which is used for busses that have power domains and/or clocks which need to be enabled before use. +config SPL_SIMPLE_PM_BUS + bool "Support simple-pm-bus driver in SPL" + depends on SPL_DM && SPL_OF_CONTROL && SPL_POWER_DOMAIN + help + Supports the 'simple-pm-bus' driver, which is used for busses that + have power domains and/or clocks which need to be enabled before use, + in SPL. + config OF_TRANSLATE bool "Translate addresses using fdt_translate_address" depends on DM && OF_CONTROL diff --git a/drivers/core/Makefile b/drivers/core/Makefile index a549890c22b..1073c26b2ed 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_$(PHASE_)ACPIGEN) += acpi.o obj-$(CONFIG_$(PHASE_)DEVRES) += devres.o obj-$(CONFIG_$(PHASE_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(PHASE_)SIMPLE_BUS) += simple-bus.o -obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o +obj-$(CONFIG_$(PHASE_)SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_DM) += dump.o obj-$(CONFIG_$(PHASE_)REGMAP) += regmap.o obj-$(CONFIG_$(PHASE_)SYSCON) += syscon-uclass.o diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 4763963914b..284fb70b036 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -87,7 +87,7 @@ int acpi_copy_name(char *out_name, const char *name) int acpi_get_name(const struct udevice *dev, char *out_name) { - struct acpi_ops *aops; + const struct acpi_ops *aops; const char *name; int ret; @@ -154,10 +154,9 @@ static int add_item(struct acpi_ctx *ctx, struct udevice *dev, if (!item->size) return 0; if (type != TYPE_OTHER) { - item->buf = malloc(item->size); + item->buf = memdup(start, item->size); if (!item->buf) return log_msg_ret("mem", -ENOMEM); - memcpy(item->buf, start, item->size); } item_count++; log_debug("* %s: Added type %d, %p, size %x\n", @@ -276,7 +275,7 @@ static int sort_acpi_item_type(struct acpi_ctx *ctx, void *start, acpi_method acpi_get_method(struct udevice *dev, enum method_t method) { - struct acpi_ops *aops; + const struct acpi_ops *aops; aops = device_get_acpi_ops(dev); if (aops) { diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index d605c0f7b7c..1388b481031 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1798,10 +1798,9 @@ int ofnode_write_prop(ofnode node, const char *propname, const void *value, void *newval; if (copy) { - newval = malloc(len); + newval = memdup(value, len); if (!newval) return log_ret(-ENOMEM); - memcpy(newval, value, len); value = newval; } ret = of_write_prop(ofnode_to_np(node), propname, len, value); diff --git a/drivers/core/read.c b/drivers/core/read.c index c0d7a969db2..ba48862f44b 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -132,12 +132,14 @@ fdt_addr_t dev_read_addr_index(const struct udevice *dev, int index) void *dev_read_addr_index_ptr(const struct udevice *dev, int index) { - fdt_addr_t addr = dev_read_addr_index(dev, index); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size_index(dev, index, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, size); } fdt_addr_t dev_read_addr_size_index(const struct udevice *dev, int index, @@ -157,17 +159,19 @@ void *dev_read_addr_size_index_ptr(const struct udevice *dev, int index, if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, *size); } void *dev_remap_addr_index(const struct udevice *dev, int index) { - fdt_addr_t addr = dev_read_addr_index(dev, index); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size_index(dev, index, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_physmem(addr, 0, MAP_NOCACHE); + return map_physmem(addr, size, MAP_NOCACHE); } fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name) @@ -182,12 +186,14 @@ fdt_addr_t dev_read_addr_name(const struct udevice *dev, const char *name) void *dev_read_addr_name_ptr(const struct udevice *dev, const char *name) { - fdt_addr_t addr = dev_read_addr_name(dev, name); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size_name(dev, name, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, size); } fdt_addr_t dev_read_addr_size_name(const struct udevice *dev, const char *name, @@ -209,17 +215,19 @@ void *dev_read_addr_size_name_ptr(const struct udevice *dev, const char *name, if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, *size); } void *dev_remap_addr_name(const struct udevice *dev, const char *name) { - fdt_addr_t addr = dev_read_addr_name(dev, name); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size_name(dev, name, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_physmem(addr, 0, MAP_NOCACHE); + return map_physmem(addr, size, MAP_NOCACHE); } fdt_addr_t dev_read_addr(const struct udevice *dev) @@ -229,12 +237,14 @@ fdt_addr_t dev_read_addr(const struct udevice *dev) void *dev_read_addr_ptr(const struct udevice *dev) { - fdt_addr_t addr = dev_read_addr(dev); + fdt_addr_t addr; + fdt_size_t size = 0; + addr = dev_read_addr_size(dev, &size); if (addr == FDT_ADDR_T_NONE) return NULL; - return map_sysmem(addr, 0); + return map_sysmem(addr, size); } void *dev_remap_addr(const struct udevice *dev) diff --git a/drivers/core/root.c b/drivers/core/root.c index d43645f34dd..2aa16d59b69 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -81,10 +81,9 @@ static int dm_setup_inst(void) /* Now allocate space for the priv/plat data, and copy it in */ size = __priv_data_end - __priv_data_start; - base = calloc(1, size); + base = memdup(__priv_data_start, size); if (!base) return log_msg_ret("priv", -ENOMEM); - memcpy(base, __priv_data_start, size); gd_set_dm_priv_base(base); } @@ -460,7 +459,7 @@ static int root_acpi_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "\\_SB"); } -struct acpi_ops root_acpi_ops = { +static const struct acpi_ops root_acpi_ops = { .get_name = root_acpi_get_name, }; #endif diff --git a/drivers/cpu/armv8_cpu.c b/drivers/cpu/armv8_cpu.c index 4eedfe5e2c5..337661c23a8 100644 --- a/drivers/cpu/armv8_cpu.c +++ b/drivers/cpu/armv8_cpu.c @@ -124,7 +124,7 @@ int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -struct acpi_ops armv8_cpu_acpi_ops = { +static const struct acpi_ops armv8_cpu_acpi_ops = { .fill_ssdt = armv8_cpu_fill_ssdt, .fill_madt = armv8_cpu_fill_madt, }; diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c index ad638cd8fff..43e74d1811b 100644 --- a/drivers/cpu/bcm283x_cpu.c +++ b/drivers/cpu/bcm283x_cpu.c @@ -193,7 +193,7 @@ static int bcm_cpu_probe(struct udevice *dev) return ret; } -struct acpi_ops bcm283x_cpu_acpi_ops = { +static const struct acpi_ops __maybe_unused bcm283x_cpu_acpi_ops = { .fill_ssdt = armv8_cpu_fill_ssdt, .fill_madt = armv8_cpu_fill_madt, }; diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 3473712a423..7bb7b420176 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019, 2024 NXP + * Copyright 2019, 2024-2026 NXP */ #include <cpu.h> @@ -28,8 +28,18 @@ struct cpu_imx_plat { u32 mpidr; }; +__weak const char *get_cpu_variant_type_name(u32 type) +{ + return NULL; +} + static const char *get_imx_type_str(u32 imxtype) { + const char *name = get_cpu_variant_type_name(imxtype); + + if (name) + return name; + switch (imxtype) { case MXC_CPU_IMX8MM: return "8MMQ"; /* Quad-core version of the imx8mm */ @@ -63,12 +73,18 @@ static const char *get_imx_type_str(u32 imxtype) return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */ case MXC_CPU_IMX8MP: return "8MP[8]"; /* Quad-core version of the imx8mp */ + case MXC_CPU_IMX8MPD2: + return "8MP Dual[2]"; /* Dual-core version of the imx8mp, low cost industrial & HMI */ case MXC_CPU_IMX8MPD: return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ case MXC_CPU_IMX8MPL: return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ + case MXC_CPU_IMX8MP5: + return "8MP[5]"; /* Quad-core version of the imx8mp, low cost industrial & HMI */ case MXC_CPU_IMX8MP6: return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ + case MXC_CPU_IMX8MPUL: + return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */ case MXC_CPU_IMX8MQ: return "8MQ"; /* Quad-core version of the imx8mq */ case MXC_CPU_IMX8MQL: @@ -374,6 +390,7 @@ static int imx_cpu_probe(struct udevice *dev) { struct cpu_imx_plat *plat = dev_get_plat(dev); u32 cpurev; + fdt_addr_t addr; set_core_data(dev); cpurev = get_cpu_rev(); @@ -381,12 +398,14 @@ static int imx_cpu_probe(struct udevice *dev) get_imx_rev_str(plat, cpurev & 0xFFF); plat->type = get_imx_type_str((cpurev & 0x1FF000) >> 12); plat->freq_mhz = imx_get_cpu_rate(dev) / 1000000; - plat->mpidr = dev_read_addr(dev); - if (plat->mpidr == FDT_ADDR_T_NONE) { + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) { printf("%s: Failed to get CPU reg property\n", __func__); return -EINVAL; } + plat->mpidr = (u32)addr; + return 0; } diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig index 401225b8528..a4710257f62 100644 --- a/drivers/crypto/aspeed/Kconfig +++ b/drivers/crypto/aspeed/Kconfig @@ -15,11 +15,11 @@ config ASPEED_ACRY bool "ASPEED RSA and ECC Engine" depends on ASPEED_AST2600 help - Select this option to enable a driver for using the RSA/ECC engine in - the ASPEED BMC SoCs. + Select this option to enable a driver for using the RSA/ECC engine in + the ASPEED BMC SoCs. - Enabling this allows the use of RSA/ECC operations in hardware without requiring the - software implementations. It also improves performance and saves code size. + Enabling this allows the use of RSA/ECC operations in hardware without requiring the + software implementations. It also improves performance and saves code size. config ASPEED_CPTRA_SHA bool "Caliptra SHA ACC for Aspeed AST27xx SoCs" diff --git a/drivers/crypto/aspeed/aspeed_acry.c b/drivers/crypto/aspeed/aspeed_acry.c index e3f81ebd5c7..ff01256e150 100644 --- a/drivers/crypto/aspeed/aspeed_acry.c +++ b/drivers/crypto/aspeed/aspeed_acry.c @@ -144,13 +144,13 @@ static int aspeed_acry_probe(struct udevice *dev) return ret; } - acry->base = devfdt_get_addr_index(dev, 0); + acry->base = dev_read_addr_index(dev, 0); if (acry->base == FDT_ADDR_T_NONE) { debug("Failed to get acry base\n"); return acry->base; } - acry->sram_base = devfdt_get_addr_index(dev, 1); + acry->sram_base = dev_read_addr_index(dev, 1); if (acry->sram_base == FDT_ADDR_T_NONE) { debug("Failed to get acry SRAM base\n"); return acry->sram_base; diff --git a/drivers/crypto/aspeed/aspeed_hace.c b/drivers/crypto/aspeed/aspeed_hace.c index 17cc30a7b54..22b5008a296 100644 --- a/drivers/crypto/aspeed/aspeed_hace.c +++ b/drivers/crypto/aspeed/aspeed_hace.c @@ -341,7 +341,7 @@ static int aspeed_hace_probe(struct udevice *dev) return rc; } - hace->base = devfdt_get_addr(dev); + hace->base = dev_read_addr(dev); return rc; } diff --git a/drivers/crypto/aspeed/cptra_ecdsa.c b/drivers/crypto/aspeed/cptra_ecdsa.c index 4b70d89def7..7603ca373ff 100644 --- a/drivers/crypto/aspeed/cptra_ecdsa.c +++ b/drivers/crypto/aspeed/cptra_ecdsa.c @@ -149,7 +149,7 @@ static int cptra_ecdsa_probe(struct udevice *dev) { struct cptra_ecdsa *ce = dev_get_priv(dev); - ce->regs = (void *)devfdt_get_addr(dev); + ce->regs = (void *)dev_read_addr(dev); if (ce->regs == (void *)FDT_ADDR_T_NONE) { debug("cannot map Caliptra mailbox registers\n"); return -EINVAL; diff --git a/drivers/crypto/aspeed/cptra_sha.c b/drivers/crypto/aspeed/cptra_sha.c index 26b97bdd92b..f57778e160d 100644 --- a/drivers/crypto/aspeed/cptra_sha.c +++ b/drivers/crypto/aspeed/cptra_sha.c @@ -219,7 +219,7 @@ static int cptra_sha_probe(struct udevice *dev) { struct cptra_sha *cs = dev_get_priv(dev); - cs->regs = (void *)devfdt_get_addr(dev); + cs->regs = (void *)dev_read_addr(dev); if (cs->regs == (void *)FDT_ADDR_T_NONE) { debug("cannot map Caliptra SHA ACC registers\n"); return -ENODEV; diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index eb01c6cf700..244a9bd905d 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -20,6 +20,7 @@ config SYS_FSL_MAX_NUM_OF_SEC config CAAM_64BIT bool + depends on FSL_CAAM default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 help Select Crypto driver for 64 bits CAAM version @@ -27,27 +28,27 @@ config CAAM_64BIT config SYS_FSL_HAS_SEC bool help - Enable Freescale Secure Boot and Trusted Architecture + Enable Freescale Secure Boot and Trusted Architecture config SYS_FSL_SEC_COMPAT_2 bool help - Secure boot and trust architecture compatible version 2 + Secure boot and trust architecture compatible version 2 config SYS_FSL_SEC_COMPAT_4 bool help - Secure boot and trust architecture compatible version 4 + Secure boot and trust architecture compatible version 4 config SYS_FSL_SEC_COMPAT_5 bool help - Secure boot and trust architecture compatible version 5 + Secure boot and trust architecture compatible version 5 config SYS_FSL_SEC_COMPAT_6 bool help - Secure boot and trust architecture compatible version 6 + Secure boot and trust architecture compatible version 6 config SYS_FSL_SEC_BE bool "Big-endian access to Freescale Secure Boot" diff --git a/drivers/crypto/tegra/tegra_aes.c b/drivers/crypto/tegra/tegra_aes.c index 7b374c757ba..55a4cec525b 100644 --- a/drivers/crypto/tegra/tegra_aes.c +++ b/drivers/crypto/tegra/tegra_aes.c @@ -518,7 +518,7 @@ static int tegra_aes_probe(struct udevice *dev) return -EINVAL; } - priv->iram_addr = devfdt_get_addr_size_name_ptr(dev, "iram-buffer", &iram_size); + priv->iram_addr = dev_read_addr_size_name_ptr(dev, "iram-buffer", &iram_size); if (!priv->iram_addr) { log_debug("%s: Cannot find iram buffer address, binding failed\n", __func__); return -EINVAL; diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index b36a765a5de..2d2b72cf766 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -104,7 +104,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -ENXIO; @@ -158,7 +158,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_set_firewall(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_agilex5.c b/drivers/ddr/altera/sdram_agilex5.c index ee66c72157a..d14e4bc5dcc 100644 --- a/drivers/ddr/altera/sdram_agilex5.c +++ b/drivers/ddr/altera/sdram_agilex5.c @@ -302,7 +302,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, gd->bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); ret = -ENXIO; @@ -345,19 +345,19 @@ int sdram_mmr_init_full(struct udevice *dev) for (i = 0; i < config_dram_banks; i++) { remaining_size = hw_size - size_counter; if (remaining_size <= dram_bank_info[i].max_size) { - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = remaining_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = remaining_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + i, gd->dram[i].start, gd->dram[i].size); break; } - gd->bd->bi_dram[i].start = dram_bank_info[i].start; - gd->bd->bi_dram[i].size = dram_bank_info[i].max_size; + gd->dram[i].start = dram_bank_info[i].start; + gd->dram[i].size = dram_bank_info[i].max_size; debug("Memory bank[%d] Starting address: 0x%llx size: 0x%llx\n", - i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); - size_counter += gd->bd->bi_dram[i].size; + i, gd->dram[i].start, gd->dram[i].size); + size_counter += gd->dram[i].size; } gd->ram_size = hw_size; @@ -408,7 +408,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: firewall init success\n"); - priv->info.base = gd->bd->bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c index 9b3cc5c7b86..e4d522202d8 100644 --- a/drivers/ddr/altera/sdram_agilex7m.c +++ b/drivers/ddr/altera/sdram_agilex7m.c @@ -375,7 +375,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { printf("%s: Failed to decode memory node\n", memory_type_in_use(dev)); @@ -484,7 +484,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("%s: firewall init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; /* Ending DDR driver initialization success tracking */ diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index c281f711fdf..9cc809b8001 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -674,9 +674,9 @@ static void sdram_size_check(void) debug("DDR: Running SDRAM size sanity check\n"); - ram_check = get_ram_size((long *)gd->bd->bi_dram[0].start, - gd->bd->bi_dram[0].size); - if (ram_check != gd->bd->bi_dram[0].size) { + ram_check = get_ram_size((long *)gd->dram[0].start, + gd->dram[0].size); + if (ram_check != gd->dram[0].size) { puts("DDR: SDRAM size check failed!\n"); hang(); } @@ -719,14 +719,14 @@ int ddr_calibration_sequence(void) /* setup the dram info within bd */ dram_init_banksize(); - if (gd->ram_size != gd->bd->bi_dram[0].size) { + if (gd->ram_size != gd->dram[0].size) { printf("DDR: Warning: DRAM size from device tree (%ld MiB)\n", - gd->bd->bi_dram[0].size >> 20); + gd->dram[0].size >> 20); printf(" mismatch with hardware (%ld MiB).\n", gd->ram_size >> 20); } - if (gd->bd->bi_dram[0].size > gd->ram_size) { + if (gd->dram[0].size > gd->ram_size) { printf("DDR: Error: DRAM size from device tree is greater\n"); printf(" than hardware size.\n"); hang(); diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index 17ec6afa82b..900d4f59989 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -2279,7 +2279,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { debug("%s: Failed to decode memory node\n", __func__); return -1; @@ -2287,7 +2287,7 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: %lld MiB\n", gd->ram_size >> 20); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; sdram_size_check(&bd); diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 4ac4c79e0ac..6664090f86a 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -285,7 +285,7 @@ int sdram_mmr_init_full(struct udevice *dev) /* Get bank configuration from devicetree */ ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, - (phys_size_t *)&gd->ram_size, &bd); + (phys_size_t *)&gd->ram_size, gd); if (ret) { puts("DDR: Failed to decode memory node\n"); return -1; @@ -328,7 +328,7 @@ int sdram_mmr_init_full(struct udevice *dev) sdram_size_check(&bd); - priv->info.base = bd.bi_dram[0].start; + priv->info.base = gd->dram[0].start; priv->info.size = gd->ram_size; debug("DDR: HMC init success\n"); diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 8ee7049b164..93df3d1812a 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -150,8 +150,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) icache_enable(); - start_addr = bd->bi_dram[0].start; - size = bd->bi_dram[0].size; + start_addr = gd->dram[0].start; + size = gd->dram[0].size; /* Initialize small block for page table */ memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); @@ -174,8 +174,8 @@ void sdram_init_ecc_bits(struct bd_info *bd) if (bank >= CONFIG_NR_DRAM_BANKS) break; - start_addr = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; + start_addr = gd->dram[bank].start; + size = gd->dram[bank].size; } dcache_disable(); @@ -198,12 +198,12 @@ void sdram_size_check(struct bd_info *bd) phys_addr_t start = 0; phys_size_t remaining_size; - start = bd->bi_dram[bank].start; - remaining_size = bd->bi_dram[bank].size; + start = gd->dram[bank].start; + remaining_size = gd->dram[bank].size; debug("Checking bank %d: start=0x%llx, size=0x%llx\n", bank, start, remaining_size); - while (ram_check < bd->bi_dram[bank].size) { + while (ram_check < gd->dram[bank].size) { phys_size_t size, test_size, detected_size; size = min((phys_addr_t)SZ_1G, (phys_addr_t)remaining_size); @@ -232,7 +232,7 @@ void sdram_size_check(struct bd_info *bd) } ram_check += detected_size; - remaining_size = bd->bi_dram[bank].size - ram_check; + remaining_size = gd->dram[bank].size - ram_check; } total_ram_check += ram_check; @@ -292,10 +292,10 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) u32 lower, upper; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -322,7 +322,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting non-secure MPU limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); @@ -354,10 +354,10 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) phys_size_t value; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (!bd->bi_dram[i].size) + if (!gd->dram[i].size) continue; - value = bd->bi_dram[i].start; + value = gd->dram[i].start; /* Keep first 1MB of SDRAM memory region as secure region when * using ATF flow, where the ATF code is located. @@ -376,7 +376,7 @@ static void sdram_set_firewall_f2sdram(struct bd_info *bd) (i * 4 * sizeof(u32))); /* Setting limit and limit extended */ - value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1; + value = gd->dram[i].start + gd->dram[i].size - 1; lower = lower_32_bits(value); upper = upper_32_bits(value); diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 7f8f3570dd8..b11fa79ca59 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -21,12 +21,12 @@ if SYS_FSL_DDR || SYS_FSL_MMDC config SYS_FSL_DDR_BE bool help - Access DDR registers in big-endian + Access DDR registers in big-endian config SYS_FSL_DDR_LE bool help - Access DDR registers in little-endian + Access DDR registers in little-endian config FSL_DDR_BIST bool diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index d59e94779ff..2b879c63b5f 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -221,7 +221,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, unsigned int i2c_address = 0; if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index a8520754006..e43dc869fc5 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -21,7 +21,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR; if (ctrl_num != 0) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index 00b4b376dd4..3a8ad6cc86b 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -26,7 +26,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index b0a61fa2b41..ee9811481ab 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -71,7 +71,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, break; #endif default: - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); return; } diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig index b953bca4f06..7b3dbf53dff 100644 --- a/drivers/ddr/imx/imx9/Kconfig +++ b/drivers/ddr/imx/imx9/Kconfig @@ -29,4 +29,11 @@ config SAVED_DRAM_TIMING_BASE after DRAM is trained, need to save the dram related timming info into memory for low power use. +config QB_SAVED_STATE_BASE + hex "Define the base address for saved QuickBoot state" + default 0x8fe00000 + help + Once DRAM is trained, the resulted training info is + saved into memory in order to be reachable from U-Boot. + endmenu diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index d904982c800..8c9b377e8a3 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -3,14 +3,14 @@ if ARCH_K3 config TI_K3_NAVSS_UDMA - bool "Texas Instruments UDMA" - depends on ARCH_K3 - select DEVRES - select DMA - select TI_K3_NAVSS_RINGACC - select TI_K3_PSIL - help - Support for UDMA used in K3 devices. + bool "Texas Instruments UDMA" + depends on ARCH_K3 + select DEVRES + select DMA + select TI_K3_NAVSS_RINGACC + select TI_K3_PSIL + help + Support for UDMA used in K3 devices. endif config TI_K3_PSIL diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index fb583580ebe..ea14ed4ef95 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -3,7 +3,7 @@ * Xilinx Zynq MPSoC Firmware driver * * Copyright (C) 2018-2019 Xilinx, Inc. - * Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. */ #include <asm/arch/hardware.h> @@ -197,6 +197,58 @@ int zynqmp_pm_ufs_cal_reg(u32 *value) *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET); return 0; } +#endif /* CONFIG_ARCH_VERSAL2 */ + +#if defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL2) +u32 zynqmp_pm_get_pmc_global_pggs_reg(u32 reg_addr) +{ + int ret; + u32 value = 0; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + if (reg_addr == PMC_GLOBAL_PGGS3_REG) { + value = 0; + } else if (reg_addr == PMC_GLOBAL_PGGS4_REG) { + value = 1; + } else { + printf("%s: not supported pggs register 0x%x\n", + __func__, reg_addr); + return 0; + } + + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_PGGS); + if (ret) { + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG); + if (ret) { + printf("%s: IOCTL_READ_REG is not supported : %d\n" + , __func__, ret); + return 0; + } + + /* find node ID from the pggs3 offset */ + value = PM_REG_PGGS3 + value; + + ret = xilinx_pm_request(PM_IOCTL, value, + IOCTL_READ_REG, 0, 0, 0, 0, + ret_payload); + if (ret) { + printf("%s: node 0x%x get pggs register failed\n", + __func__, value); + return 0; + } + } else { + ret = xilinx_pm_request(PM_IOCTL, PMC_GLOBAL_PGGS3_REG_NODE, + IOCTL_READ_PGGS, value, 0, 0, 0, + ret_payload); + if (ret) { + printf("%s: node 0x%x get pggs register failed\n", + __func__, PMC_GLOBAL_PGGS3_REG_NODE); + return 0; + } + } + + return ret_payload[1]; +} #endif int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value) diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 792e4033428..e3715bf2b24 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -52,7 +52,7 @@ static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize, default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -75,7 +75,7 @@ static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -234,7 +234,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -279,7 +279,7 @@ static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - checksum the data? */ } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -423,7 +423,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -434,7 +434,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ printf ("%s: Slave Serial Dumping is unavailable\n", - __FUNCTION__); + __func__); return FPGA_FAIL; } diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 98405589134..6221041e092 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -57,7 +57,7 @@ static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize, default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -80,7 +80,7 @@ static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) default: printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + __func__, desc->iface); } return ret_val; @@ -241,7 +241,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -286,7 +286,7 @@ static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - checksum the data? */ } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -442,7 +442,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -453,7 +453,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ printf ("%s: Slave Serial Dumping is unavailable\n", - __FUNCTION__); + __func__); return FPGA_FAIL; } diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 44d7ad6bd54..b6966c7d2cb 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -149,8 +149,8 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype, int flags) { - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); return FPGA_FAIL; } @@ -200,8 +200,8 @@ int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize, int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + if (!xilinx_validate(desc, (char *)__func__)) { + printf("%s: Invalid device descriptor\n", __func__); return FPGA_FAIL; } @@ -217,7 +217,7 @@ int xilinx_info(xilinx_desc *desc) { int ret_val = FPGA_FAIL; - if (xilinx_validate (desc, (char *)__FUNCTION__)) { + if (xilinx_validate(desc, (char *)__func__)) { printf ("Family: \t"); switch (desc->family) { case xilinx_spartan2: @@ -293,7 +293,7 @@ int xilinx_info(xilinx_desc *desc) ret_val = FPGA_SUCCESS; } else { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); + printf("%s: Invalid device descriptor\n", __func__); } return ret_val; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 0b5466b39b8..75b35fbc5be 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -294,9 +294,9 @@ config MAX7320_GPIO bool "MAX7320 I2C GPIO Expander driver" depends on DM_GPIO && DM_I2C help - Support for MAX7320 I2C 8/16-bit GPIO expander. - original maxim device has 8 push/pull outputs, - some clones offers 16bit. + Support for MAX7320 I2C 8/16-bit GPIO expander. + original maxim device has 8 push/pull outputs, + some clones offers 16bit. config MAX77663_GPIO bool "MAX77663 GPIO cell of PMIC driver" @@ -309,27 +309,27 @@ config MAX77663_GPIO config MCP230XX_GPIO bool "MCP230XX GPIO driver" - depends on DM + depends on DM && DM_I2C && DM_SPI help - Support for Microchip's MCP230XX I2C connected GPIO devices. + Support for Microchip's MCP230XX I2C and SPI connected GPIO devices. The following chips are supported: - - MCP23008 - - MCP23017 - - MCP23018 - - MCP23S08 - - MCP23S17 - - MCP23S18 + - MCP23008 + - MCP23017 + - MCP23018 + - MCP23S08 + - MCP23S17 + - MCP23S18 config MSCC_SGPIO bool "Microsemi Serial GPIO driver" depends on DM_GPIO && SOC_VCOREIII help Support for the VCoreIII SoC serial GPIO device. By using a - serial interface, the SIO controller significantly extends - the number of available GPIOs with a minimum number of - additional pins on the device. The primary purpose of the - SIO controller is to connect control signals from SFP - modules and to act as an LED controller. + serial interface, the SIO controller significantly extends + the number of available GPIOs with a minimum number of + additional pins on the device. The primary purpose of the + SIO controller is to connect control signals from SFP + modules and to act as an LED controller. config MSM_GPIO bool "Qualcomm GPIO driver" @@ -404,8 +404,8 @@ config PCF8575_GPIO bool "PCF8575 I2C GPIO Expander driver" depends on DM_GPIO && DM_I2C help - Support for PCF8575 I2C 16-bit GPIO expander. Most of these - chips are from NXP and TI. + Support for PCF8575 I2C 16-bit GPIO expander. Most of these + chips are from NXP and TI. config RCAR_GPIO bool "Renesas R-Car GPIO driver" @@ -459,9 +459,9 @@ config SUNXI_GPIO config SUNXI_NEW_PINCTRL bool depends on SUNXI_GPIO - ---help--- - The Allwinner D1 and other new SoCs use a different register map - for the GPIO block, which we need to know about in the SPL. + help + The Allwinner D1 and other new SoCs use a different register map + for the GPIO block, which we need to know about in the SPL. config XILINX_GPIO bool "Xilinx GPIO driver" @@ -728,15 +728,15 @@ config SLG7XL45106_I2C_GPO bool "slg7xl45106 i2c gpo expander" depends on DM_GPIO && ARCH_ZYNQMP help - Support for slg7xl45106 i2c gpo expander. It is an i2c based - 8-bit gpo expander, all gpo lines are controlled by writing - value into data register. + Support for slg7xl45106 i2c gpo expander. It is an i2c based + 8-bit gpo expander, all gpo lines are controlled by writing + value into data register. config GPIO_SCMI bool "SCMI GPIO pinctrl driver" depends on DM_GPIO && PINCTRL_SCMI help - Support pinctrl GPIO over the SCMI interface. + Support pinctrl GPIO over the SCMI interface. config ADP5585_GPIO bool "ADP5585 GPIO driver" @@ -756,10 +756,11 @@ config SPL_ADP5585_GPIO depends on SPL_DM_GPIO && SPL_I2C help Support ADP5585 GPIO expander in SPL. + config MPFS_GPIO bool "Enable Polarfire SoC GPIO driver" depends on DM_GPIO help - Enable to support the GPIO driver on Polarfire SoC + Enable to support the GPIO driver on Polarfire SoC endif diff --git a/drivers/gpio/gpio-aspeed-g7.c b/drivers/gpio/gpio-aspeed-g7.c index 4607468ca05..ae330173f38 100644 --- a/drivers/gpio/gpio-aspeed-g7.c +++ b/drivers/gpio/gpio-aspeed-g7.c @@ -131,7 +131,7 @@ static int aspeed_gpio_probe(struct udevice *dev) uc_priv->bank_name = dev->name; ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count); - priv->regs = devfdt_get_addr_ptr(dev); + priv->regs = dev_read_addr_ptr(dev); return 0; } diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c index 4bbdec756f3..d6144d5706b 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -223,9 +223,9 @@ static int aspeed_sgpio_probe(struct udevice *dev) ulong apb_freq; int ret; - priv->base = devfdt_get_addr_ptr(dev); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; priv->pdata = (const struct aspeed_sgpio_pdata *)dev_get_driver_data(dev); if (!priv->pdata) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index c5608f4a9df..54a786c4dc0 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -275,7 +275,7 @@ static int aspeed_gpio_probe(struct udevice *dev) uc_priv->bank_name = dev->name; ofnode_read_u32(dev_ofnode(dev), "ngpios", &uc_priv->gpio_count); - priv->regs = devfdt_get_addr_ptr(dev); + priv->regs = dev_read_addr_ptr(dev); return 0; } diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c index c8d2dff5f7b..180799139b3 100644 --- a/drivers/gpio/gpio-fxl6408.c +++ b/drivers/gpio/gpio-fxl6408.c @@ -273,7 +273,7 @@ static int fxl6408_probe(struct udevice *dev) u32 val32; addr = dev_read_addr(dev); - if (addr == 0) + if (addr == FDT_ADDR_T_NONE) return -EINVAL; info->addr = addr; diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 7651d5360d6..4d40738e5aa 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -877,8 +877,19 @@ static int get_function(struct udevice *dev, int offset, bool skip_unused, return -ENODEV; if (offset < 0 || offset >= uc_priv->gpio_count) return -EINVAL; - if (namep) + if (namep) { *namep = uc_priv->name[offset]; + /* Fall back to DT "gpio-line-names" for unrequested pins. */ + if (CONFIG_IS_ENABLED(DM_GPIO_LOOKUP_LINE_NAME) && + (!*namep || !**namep)) { + const char *dt_name = NULL; + + if (!dev_read_string_index(dev, "gpio-line-names", + offset, &dt_name) && + dt_name && *dt_name) + *namep = dt_name; + } + } if (skip_unused && !gpio_is_claimed(uc_priv, offset)) return GPIOF_UNUSED; if (ops->get_function) { diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 7cf178f8a48..ba3c5fcf25b 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -194,11 +194,11 @@ static int imx_rgpio2p_bind(struct udevice *dev) dual_base = true; if (dual_base) { - addr = devfdt_get_addr_index(dev, 1); + addr = dev_read_addr_index(dev, 1); if (addr == FDT_ADDR_T_NONE) return -EINVAL; } else { - addr = devfdt_get_addr_index(dev, 0); + addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index 709d04017d1..40646407369 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -171,6 +171,58 @@ static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio) return dir ? GPIOF_OUTPUT : GPIOF_INPUT; } +static int mpc8xxx_gpio_set_flags(struct udevice *dev, uint gpio, + ulong flags) +{ + u32 mask = gpio_mask(gpio); + int ret; + + /* The QorIQ GPIO pad supports open-drain only; open-source has + * no silicon counterpart, so reject it rather than silently + * pretending. + */ + if (flags & GPIOD_OPEN_SOURCE) + return -EOPNOTSUPP; + + /* GPODR is per-pin and meaningful in both directions (it stays + * latched when the pin is re-purposed), so apply it before the + * direction change. + */ + if (flags & GPIOD_OPEN_DRAIN) + mpc8xxx_gpio_open_drain_on(dev, mask); + else + mpc8xxx_gpio_open_drain_off(dev, mask); + + if (flags & GPIOD_IS_OUT) { + ret = mpc8xxx_gpio_direction_output(dev, gpio, + !!(flags & GPIOD_IS_OUT_ACTIVE)); + } else if (flags & GPIOD_IS_IN) { + ret = mpc8xxx_gpio_direction_input(dev, gpio); + } else { + ret = 0; + } + + return ret; +} + +static int mpc8xxx_gpio_get_flags(struct udevice *dev, uint gpio, + ulong *flagsp) +{ + u32 mask = gpio_mask(gpio); + ulong flags = 0; + + if (mpc8xxx_gpio_get_dir(dev, mask)) + flags |= GPIOD_IS_OUT; + else + flags |= GPIOD_IS_IN; + + if (mpc8xxx_gpio_open_drain_val(dev, mask)) + flags |= GPIOD_OPEN_DRAIN; + + *flagsp = flags; + return 0; +} + #if CONFIG_IS_ENABLED(OF_CONTROL) static int mpc8xxx_gpio_of_to_plat(struct udevice *dev) { @@ -255,6 +307,8 @@ static const struct dm_gpio_ops gpio_mpc8xxx_ops = { .get_value = mpc8xxx_gpio_get_value, .set_value = mpc8xxx_gpio_set_value, .get_function = mpc8xxx_gpio_get_function, + .set_flags = mpc8xxx_gpio_set_flags, + .get_flags = mpc8xxx_gpio_get_flags, }; static const struct udevice_id mpc8xxx_gpio_ids[] = { diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c index 5abbb34daea..1c3d27eb1cc 100644 --- a/drivers/gpio/nx_gpio.c +++ b/drivers/gpio/nx_gpio.c @@ -213,9 +213,10 @@ static int nx_gpio_of_to_plat(struct udevice *dev) { struct nx_gpio_plat *plat = dev_get_plat(dev); - plat->regs = map_physmem(devfdt_get_addr(dev), - sizeof(struct nx_gpio_regs), - MAP_NOCACHE); + plat->regs = dev_remap_addr(dev); + if (!plat->regs) + return -EINVAL; + plat->gpio_count = dev_read_s32_default(dev, "nexell,gpio-bank-width", 32); plat->bank_name = dev_read_string(dev, "gpio-bank-name"); diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c index 523ca8473a8..965a5fcf30b 100644 --- a/drivers/gpio/pca953x_gpio.c +++ b/drivers/gpio/pca953x_gpio.c @@ -312,7 +312,7 @@ static int pca953x_probe(struct udevice *dev) u8 val[MAX_BANK]; addr = dev_read_addr(dev); - if (addr == 0) + if (addr == FDT_ADDR_T_NONE) return -ENODEV; info->addr = addr; diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 6215f794e09..ad4a70dd49b 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -409,7 +409,7 @@ static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigne return 0; } -struct pinctrl_ops qcom_pmic_pinctrl_ops = { +static const struct pinctrl_ops qcom_pmic_pinctrl_ops = { .get_pins_count = qcom_pmic_pinctrl_get_pins_count, .get_pin_name = qcom_pmic_pinctrl_get_pin_name, .set_state = pinctrl_generic_set_state, diff --git a/drivers/gpio/qcom_spmi_gpio.c b/drivers/gpio/qcom_spmi_gpio.c index fc1aac8b534..3efee206007 100644 --- a/drivers/gpio/qcom_spmi_gpio.c +++ b/drivers/gpio/qcom_spmi_gpio.c @@ -1021,7 +1021,7 @@ static int qcom_spmi_pmic_pinctrl_pinmux_set_mux(struct udevice *dev, unsigned i return spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_EN_CTL, val); } -struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = { +static const struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = { .get_pins_count = qcom_spmi_pmic_pinctrl_get_pins_count, .get_pin_name = qcom_spmi_pmic_pinctrl_get_pin_name, .set_state = pinctrl_generic_set_state, diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index e8f50d815d7..76aff0ed5aa 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -306,7 +306,7 @@ static int sb_gpio_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "GPIO"); } -struct acpi_ops gpio_sandbox_acpi_ops = { +static const struct acpi_ops gpio_sandbox_acpi_ops = { .get_name = sb_gpio_get_name, }; #endif /* ACPIGEN */ @@ -568,7 +568,7 @@ static struct pinctrl_ops sandbox_pinctrl_gpio_ops = { }; #if CONFIG_IS_ENABLED(ACPIGEN) -struct acpi_ops pinctrl_sandbox_acpi_ops = { +static const struct acpi_ops pinctrl_sandbox_acpi_ops = { .get_name = sb_pinctrl_get_name, }; #endif diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 37288a47eb7..ab5af17858c 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -110,16 +110,16 @@ config I2C_CROS_EC_TUNNEL config I2C_CROS_EC_LDO bool "Provide access to LDOs on the Chrome OS EC" depends on CROS_EC - ---help--- - On many Chromebooks the main PMIC is inaccessible to the AP. This is - often dealt with by using an I2C pass-through interface provided by - the EC. On some unfortunate models (e.g. Spring) the pass-through - is not available, and an LDO message is available instead. This - option enables a driver which provides very basic access to those - regulators, via the EC. We implement this as an I2C bus which - emulates just the TPS65090 messages we know about. This is done to - avoid duplicating the logic in the TPS65090 regulator driver for - enabling/disabling an LDO. + help + On many Chromebooks the main PMIC is inaccessible to the AP. This is + often dealt with by using an I2C pass-through interface provided by + the EC. On some unfortunate models (e.g. Spring) the pass-through + is not available, and an LDO message is available instead. This + option enables a driver which provides very basic access to those + regulators, via the EC. We implement this as an I2C bus which + emulates just the TPS65090 messages we know about. This is done to + avoid duplicating the logic in the TPS65090 regulator driver for + enabling/disabling an LDO. config I2C_SET_DEFAULT_BUS_NUM bool "Set default I2C bus number" @@ -180,9 +180,9 @@ config SYS_I2C_IPROC Say yes here to to enable the Broadco I2C driver. config SYS_I2C_FSL - bool "Freescale I2C bus driver" - depends on M68K || PPC - help + bool "Freescale I2C bus driver" + depends on M68K || PPC + help Add support for Freescale I2C busses as used on MPC8240, MPC8245, and MPC85xx processors. @@ -249,14 +249,14 @@ config SYS_I2C_DW_PCI controller. config SYS_I2C_AST2600 - bool "AST2600 I2C Controller" - depends on DM_I2C && ARCH_ASPEED - help - Say yes here to select AST2600 I2C Host Controller. The driver - support AST2600 I2C new mode register. This I2C controller supports: - _Standard-mode (up to 100 kHz) - _Fast-mode (up to 400 kHz) - _Fast-mode Plus (up to 1 MHz) + bool "AST2600 I2C Controller" + depends on DM_I2C && ARCH_ASPEED + help + Say yes here to select AST2600 I2C Host Controller. The driver + support AST2600 I2C new mode register. This I2C controller supports: + _Standard-mode (up to 100 kHz) + _Fast-mode (up to 400 kHz) + _Fast-mode Plus (up to 1 MHz) config SYS_I2C_ASPEED bool "Aspeed I2C Controller" @@ -333,50 +333,50 @@ if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) config SYS_I2C_MXC_I2C1 bool "NXP MXC I2C1" help - Add support for NXP MXC I2C Controller 1. - Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 1. + Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C2 bool "NXP MXC I2C2" help - Add support for NXP MXC I2C Controller 2. - Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 2. + Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C3 bool "NXP MXC I2C3" help - Add support for NXP MXC I2C Controller 3. - Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 3. + Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C4 bool "NXP MXC I2C4" help - Add support for NXP MXC I2C Controller 4. - Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 4. + Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C5 bool "NXP MXC I2C5" help - Add support for NXP MXC I2C Controller 5. - Required for SoCs which have I2C MXC controller 5 eg LX2160A + Add support for NXP MXC I2C Controller 5. + Required for SoCs which have I2C MXC controller 5 eg LX2160A config SYS_I2C_MXC_I2C6 bool "NXP MXC I2C6" help - Add support for NXP MXC I2C Controller 6. - Required for SoCs which have I2C MXC controller 6 eg LX2160A + Add support for NXP MXC I2C Controller 6. + Required for SoCs which have I2C MXC controller 6 eg LX2160A config SYS_I2C_MXC_I2C7 bool "NXP MXC I2C7" help - Add support for NXP MXC I2C Controller 7. - Required for SoCs which have I2C MXC controller 7 eg LX2160A + Add support for NXP MXC I2C Controller 7. + Required for SoCs which have I2C MXC controller 7 eg LX2160A config SYS_I2C_MXC_I2C8 bool "NXP MXC I2C8" help - Add support for NXP MXC I2C Controller 8. - Required for SoCs which have I2C MXC controller 8 eg LX2160A + Add support for NXP MXC I2C Controller 8. + Required for SoCs which have I2C MXC controller 8 eg LX2160A endif if SYS_I2C_MXC_I2C1 @@ -385,13 +385,13 @@ config SYS_MXC_I2C1_SPEED default 40000000 if TARGET_LS2080A_EMU default 100000 help - MXC I2C Channel 1 speed + MXC I2C Channel 1 speed config SYS_MXC_I2C1_SLAVE hex "I2C1 Slave" default 0x0 help - MXC I2C1 Slave + MXC I2C1 Slave endif if SYS_I2C_MXC_I2C2 @@ -400,13 +400,13 @@ config SYS_MXC_I2C2_SPEED default 40000000 if TARGET_LS2080A_EMU default 100000 help - MXC I2C Channel 2 speed + MXC I2C Channel 2 speed config SYS_MXC_I2C2_SLAVE hex "I2C2 Slave" default 0x0 help - MXC I2C2 Slave + MXC I2C2 Slave endif if SYS_I2C_MXC_I2C3 @@ -414,13 +414,13 @@ config SYS_MXC_I2C3_SPEED int "I2C Channel 3 speed" default 100000 help - MXC I2C Channel 3 speed + MXC I2C Channel 3 speed config SYS_MXC_I2C3_SLAVE hex "I2C3 Slave" default 0x0 help - MXC I2C3 Slave + MXC I2C3 Slave endif if SYS_I2C_MXC_I2C4 @@ -428,13 +428,13 @@ config SYS_MXC_I2C4_SPEED int "I2C Channel 4 speed" default 100000 help - MXC I2C Channel 4 speed + MXC I2C Channel 4 speed config SYS_MXC_I2C4_SLAVE hex "I2C4 Slave" default 0x0 help - MXC I2C4 Slave + MXC I2C4 Slave endif if SYS_I2C_MXC_I2C5 @@ -442,13 +442,13 @@ config SYS_MXC_I2C5_SPEED int "I2C Channel 5 speed" default 100000 help - MXC I2C Channel 5 speed + MXC I2C Channel 5 speed config SYS_MXC_I2C5_SLAVE hex "I2C5 Slave" default 0x0 help - MXC I2C5 Slave + MXC I2C5 Slave endif if SYS_I2C_MXC_I2C6 @@ -456,13 +456,13 @@ config SYS_MXC_I2C6_SPEED int "I2C Channel 6 speed" default 100000 help - MXC I2C Channel 6 speed + MXC I2C Channel 6 speed config SYS_MXC_I2C6_SLAVE hex "I2C6 Slave" default 0x0 help - MXC I2C6 Slave + MXC I2C6 Slave endif if SYS_I2C_MXC_I2C7 @@ -470,13 +470,13 @@ config SYS_MXC_I2C7_SPEED int "I2C Channel 7 speed" default 100000 help - MXC I2C Channel 7 speed + MXC I2C Channel 7 speed config SYS_MXC_I2C7_SLAVE hex "I2C7 Slave" default 0x0 help - MXC I2C7 Slave + MXC I2C7 Slave endif if SYS_I2C_MXC_I2C8 @@ -484,13 +484,13 @@ config SYS_MXC_I2C8_SPEED int "I2C Channel 8 speed" default 100000 help - MXC I2C Channel 8 speed + MXC I2C Channel 8 speed config SYS_MXC_I2C8_SLAVE hex "I2C8 Slave" default 0x0 help - MXC I2C8 Slave + MXC I2C8 Slave endif config SYS_I2C_NEXELL @@ -668,19 +668,19 @@ config SYS_I2C_STM32F7 help Enable this option to add support for STM32 I2C controller introduced with STM32F7/H7 SoCs. This I2C controller supports : - _ Slave and master modes - _ Multimaster capability - _ Standard-mode (up to 100 kHz) - _ Fast-mode (up to 400 kHz) - _ Fast-mode Plus (up to 1 MHz) - _ 7-bit and 10-bit addressing mode - _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) - _ All 7-bit addresses acknowledge mode - _ General call - _ Programmable setup and hold times - _ Easy to use event management - _ Optional clock stretching - _ Software reset + _ Slave and master modes + _ Multimaster capability + _ Standard-mode (up to 100 kHz) + _ Fast-mode (up to 400 kHz) + _ Fast-mode Plus (up to 1 MHz) + _ 7-bit and 10-bit addressing mode + _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) + _ All 7-bit addresses acknowledge mode + _ General call + _ Programmable setup and hold times + _ Easy to use event management + _ Optional clock stretching + _ Software reset config SYS_I2C_SUN6I_P2WI bool "Allwinner sun6i P2WI controller" @@ -780,7 +780,7 @@ config SYS_I2C_BUS_MAX int "Max I2C busses" depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA default 3 if OMAP34XX || AM33XX || AM43XX - default 4 if ARCH_SOCFPGA + default 4 if ARCH_SOCFPGA || OMAP44XX default 5 if OMAP54XX help Define the maximum number of available I2C buses. @@ -792,10 +792,10 @@ config SYS_I2C_XILINX_XIIC Support for Xilinx AXI I2C controller. config SYS_I2C_IHS - bool "gdsys IHS I2C driver" - depends on DM_I2C - help - Support for gdsys IHS I2C driver on FPGA bus. + bool "gdsys IHS I2C driver" + depends on DM_I2C + help + Support for gdsys IHS I2C driver on FPGA bus. source "drivers/i2c/muxes/Kconfig" diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index ad4122c2abd..db2706fdb6e 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -168,7 +168,7 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev, return 0; } -static struct acpi_ops dw_i2c_acpi_ops = { +static const struct acpi_ops dw_i2c_acpi_ops = { .fill_ssdt = dw_i2c_acpi_fill_ssdt, }; diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index a309fd6f07c..e2b4fd334ec 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -239,7 +239,6 @@ static int bus_i2c_stop(struct udevice *bus) start_time = get_timer(0); while (1) { status = readl(®s->msr); - result = imx_lpci2c_check_clear_error(regs); /* stop detect flag */ if (status & LPI2C_MSR_SDF_MASK) { /* clear stop flag */ @@ -250,10 +249,13 @@ static int bus_i2c_stop(struct udevice *bus) if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) { debug("stop timeout\n"); + result = imx_lpci2c_check_clear_error(regs); return -ETIMEDOUT; } } + result = imx_lpci2c_check_clear_error(regs); + return result; } diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 3b1220b2105..9f642e4451f 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -49,7 +49,7 @@ config I2C_MUX_PCA954x MAX7356, MAX7357, MAX7358, MAX7367, MAX7368 and MAX7369 config I2C_MUX_GPIO - tristate "GPIO-based I2C multiplexer" + tristate "GPIO-based I2C multiplexer" depends on I2C_MUX && DM_GPIO select DEVRES help diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index de95a1debdc..04ebc24e8cf 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -133,7 +133,7 @@ config LED_GPIO config SPL_LED_GPIO bool "LED support for GPIO-connected LEDs in SPL" - depends on SPL_LED && SPL_DM_GPIO + depends on SPL_LED && SPL_DM_GPIO help This option is an SPL-variant of the LED_GPIO option. See the help of LED_GPIO for details. diff --git a/drivers/led/led_sw_blink.c b/drivers/led/led_sw_blink.c index ee1546d02d4..4190fde8f0f 100644 --- a/drivers/led/led_sw_blink.c +++ b/drivers/led/led_sw_blink.c @@ -114,9 +114,11 @@ bool led_sw_on_state_change(struct udevice *dev, enum led_state_t state) case LEDST_ON: ops->set_state(dev, LEDST_OFF); sw_blink->state = LED_SW_BLINK_ST_OFF; + break; default: ops->set_state(dev, LEDST_ON); sw_blink->state = LED_SW_BLINK_ST_ON; + break; } return true; diff --git a/drivers/mailbox/apple-mbox.c b/drivers/mailbox/apple-mbox.c index 2ee49734f40..39a7edc0285 100644 --- a/drivers/mailbox/apple-mbox.c +++ b/drivers/mailbox/apple-mbox.c @@ -59,7 +59,7 @@ static int apple_mbox_recv(struct mbox_chan *chan, void *data) return 0; } -struct mbox_ops apple_mbox_ops = { +static const struct mbox_ops apple_mbox_ops = { .of_xlate = apple_mbox_of_xlate, .send = apple_mbox_send, .recv = apple_mbox_recv, diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index c7eaa3de96f..fd0fce21d78 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -387,7 +387,7 @@ int imx_mu_of_xlate(struct mbox_chan *chan, struct ofnode_phandle_args *args) return plat->dcfg->of_xlate(chan, args); } -struct mbox_ops imx_mu_ops = { +static const struct mbox_ops imx_mu_ops = { .of_xlate = imx_mu_of_xlate, .request = imx_mu_chan_request, .rfree = imx_mu_chan_free, diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index 6f5ad37919f..6eebfcd3601 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -293,7 +293,7 @@ static int k3_sec_proxy_recv(struct mbox_chan *chan, void *data) return 0; } -struct mbox_ops k3_sec_proxy_mbox_ops = { +static const struct mbox_ops k3_sec_proxy_mbox_ops = { .of_xlate = k3_sec_proxy_of_xlate, .request = k3_sec_proxy_request, .rfree = k3_sec_proxy_free, diff --git a/drivers/mailbox/renesas-mfis.c b/drivers/mailbox/renesas-mfis.c index 1e9e8285974..19b801e56a6 100644 --- a/drivers/mailbox/renesas-mfis.c +++ b/drivers/mailbox/renesas-mfis.c @@ -29,7 +29,7 @@ static int mfis_send(struct mbox_chan *chan, const void *data) return 0; } -struct mbox_ops mfis_mbox_ops = { +static const struct mbox_ops mfis_mbox_ops = { .send = mfis_send, }; diff --git a/drivers/mailbox/sandbox-mbox.c b/drivers/mailbox/sandbox-mbox.c index 87e06e492fe..d6ac758c4d8 100644 --- a/drivers/mailbox/sandbox-mbox.c +++ b/drivers/mailbox/sandbox-mbox.c @@ -86,7 +86,7 @@ static const struct udevice_id sandbox_mbox_ids[] = { { } }; -struct mbox_ops sandbox_mbox_mbox_ops = { +static const struct mbox_ops sandbox_mbox_mbox_ops = { .request = sandbox_mbox_request, .rfree = sandbox_mbox_free, .send = sandbox_mbox_send, diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c index dda108735fc..49f7795b3cd 100644 --- a/drivers/mailbox/stm32-ipcc.c +++ b/drivers/mailbox/stm32-ipcc.c @@ -147,7 +147,7 @@ static const struct udevice_id stm32_ipcc_ids[] = { { } }; -struct mbox_ops stm32_ipcc_mbox_ops = { +static const struct mbox_ops stm32_ipcc_mbox_ops = { .request = stm32_ipcc_request, .rfree = stm32_ipcc_free, .send = stm32_ipcc_send, diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 591d9d9c656..82d0fa80396 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -44,15 +44,15 @@ config STM32_OMM This driver manages the muxing between the 2 OSPI busses and the 2 output ports. There are 4 possible muxing configurations: - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 - output is on port 2 + output is on port 2 - OSPI1 and OSPI2 are multiplexed over the same output port 1 - swapped mode (no multiplexing), OSPI1 output is on port 2, - OSPI2 output is on port 1 + OSPI2 output is on port 1 - OSPI1 and OSPI2 are multiplexed over the same output port 2 It also manages : - - the split of the memory area shared between the 2 OSPI instances. - - chip select selection override. - - the time between 2 transactions in multiplexed mode. + - the split of the memory area shared between the 2 OSPI instances. + - chip select selection override. + - the time between 2 transactions in multiplexed mode. config TI_AEMIF tristate "Texas Instruments AEMIF driver" @@ -71,9 +71,9 @@ config TI_GPMC depends on MEMORY && CLK && OF_CONTROL help This driver is for the General Purpose Memory Controller (GPMC) - present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows - interfacing to a variety of asynchronous as well as synchronous - memory drives like NOR, NAND, OneNAND, SRAM. + present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows + interfacing to a variety of asynchronous as well as synchronous + memory drives like NOR, NAND, OneNAND, SRAM. if TI_GPMC config TI_GPMC_DEBUG diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ae53b02f27c..79f4db9849c 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1,4 +1,4 @@ config MFD_ATMEL_SMC - bool "Atmel Static Memory Controller driver" - help - Say yes here to support Atmel Static Memory Controller driver. + bool "Atmel Static Memory Controller driver" + help + Say yes here to support Atmel Static Memory Controller driver. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ea785793d18..bde5c640de8 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -71,9 +71,9 @@ config ATSHA204A select BITREVERSE depends on MISC help - Enable support for I2C connected Atmel's ATSHA204A - CryptoAuthentication module found for example on the Turris Omnia - board. + Enable support for I2C connected Atmel's ATSHA204A + CryptoAuthentication module found for example on the Turris Omnia + board. config GATEWORKS_SC bool "Gateworks System Controller Support" @@ -94,7 +94,7 @@ config QCOM_GENI etc. config ROCKCHIP_EFUSE - bool "Rockchip e-fuse support" + bool "Rockchip e-fuse support" depends on MISC help Enable (read-only) access for the e-fuse block found in Rockchip @@ -647,6 +647,7 @@ config IHS_FPGA gdsys devices, which supply the majority of the functionality offered by the devices. This driver supports both CON and CPU variants of the devices, depending on the device tree entry. + config ESM_K3 bool "Enable K3 ESM driver" depends on ARCH_K3 diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index fabe4964a33..e163224b8e3 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -258,7 +258,7 @@ static int send_command_proto3(struct cros_ec_dev *cdev, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int out_bytes, in_bytes; int rv; @@ -287,7 +287,7 @@ static int send_command(struct cros_ec_dev *dev, uint cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int ret = -1; /* Handle protocol version 3 support */ @@ -487,7 +487,7 @@ int cros_ec_read_build_info(struct udevice *dev, char **strp) } int cros_ec_read_current_image(struct udevice *dev, - enum ec_current_image *image) + enum ec_image *image) { struct ec_response_get_version *r; @@ -756,9 +756,8 @@ int cros_ec_flash_protect(struct udevice *dev, uint32_t set_mask, static int cros_ec_check_version(struct udevice *dev) { struct cros_ec_dev *cdev = dev_get_uclass_priv(dev); + const struct dm_cros_ec_ops *ops; struct ec_params_hello req; - - struct dm_cros_ec_ops *ops; int ret; ops = dm_cros_ec_get_ops(dev); @@ -1638,7 +1637,7 @@ int cros_ec_vstore_write(struct udevice *dev, int slot, const uint8_t *data, int cros_ec_get_switches(struct udevice *dev) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int ret; ops = dm_cros_ec_get_ops(dev); diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 432b1fbb0c4..9fedca4e6b6 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -100,7 +100,7 @@ struct ec_state { struct fdt_cros_ec ec_config; uint8_t *flash_data; int flash_data_len; - enum ec_current_image current_image; + enum ec_image current_image; int matrix_count; struct ec_keymatrix_entry *matrix; /* the key matrix info */ uint8_t keyscan[KEYBOARD_COLS]; @@ -726,7 +726,7 @@ int cros_ec_probe(struct udevice *dev) return cros_ec_register(dev); } -struct dm_cros_ec_ops cros_ec_ops = { +static const struct dm_cros_ec_ops cros_ec_ops = { .packet = cros_ec_sandbox_packet, .get_switches = cros_ec_sandbox_get_switches, }; diff --git a/drivers/misc/i2c_eeprom_emul.c b/drivers/misc/i2c_eeprom_emul.c index 3ad2e047ee3..40f34ad03a4 100644 --- a/drivers/misc/i2c_eeprom_emul.c +++ b/drivers/misc/i2c_eeprom_emul.c @@ -144,7 +144,7 @@ static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg, return 0; } -struct dm_i2c_ops sandbox_i2c_emul_ops = { +static const struct dm_i2c_ops sandbox_i2c_emul_ops = { .xfer = sandbox_i2c_eeprom_xfer, }; diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 8ee0a7733ca..355fd86ed8c 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -795,6 +795,38 @@ int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_outp return ret; } +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg = {}; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_V2X_GET_STATE_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + state->v2x_state = msg.data[1] & 0xFF; + state->v2x_power_state = (msg.data[1] & 0xFF00) >> 8; + state->v2x_err_code = msg.data[2]; + + return ret; +} + int ele_volt_change_start_req(void) { struct udevice *dev = gd->arch.ele_dev; diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index cdb85b999db..65a4779c041 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -209,7 +209,7 @@ static int imx8ulp_mu_probe(struct udevice *dev) debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); - addr = devfdt_get_addr(dev); + addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/misc/k3_avs.c b/drivers/misc/k3_avs.c index 0774e0a4c9e..a885c99c547 100644 --- a/drivers/misc/k3_avs.c +++ b/drivers/misc/k3_avs.c @@ -300,7 +300,7 @@ static void k3_avs_program_tshut(struct k3_avs_privdata *priv) void __iomem *cfg2_base; void __iomem *fuse_base; - cfg2_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 1); + cfg2_base = (void __iomem *)dev_read_addr_index(priv->dev, 1); if (IS_ERR(cfg2_base)) { dev_err(priv->dev, "cfg base is not defined\n"); return; @@ -319,7 +319,7 @@ static void k3_avs_program_tshut(struct k3_avs_privdata *priv) */ if (device_is_compatible(priv->dev, "ti,j721e-vtm")) { - fuse_base = (void __iomem *)devfdt_get_addr_index(priv->dev, 2); + fuse_base = (void __iomem *)dev_read_addr_index(priv->dev, 2); if (IS_ERR(fuse_base)) { dev_err(priv->dev, "fuse-base is not defined for J721E Soc\n"); return; diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 0e002ac25f4..8a11637ca7f 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -152,7 +152,7 @@ UCLASS_DRIVER(qfw) = { .per_device_auto = sizeof(struct qfw_dev), }; -struct bootdev_ops qfw_bootdev_ops = { +static const struct bootdev_ops qfw_bootdev_ops = { .get_bootflow = qfw_get_bootflow, }; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 6c513328de2..0a40fca2596 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -332,7 +332,7 @@ config MMC_MESON_GX bool "Meson GX EMMC controller support" depends on ARCH_MESON help - Support for EMMC host controller on Meson GX ARM SoCs platform (S905) + Support for EMMC host controller on Meson GX ARM SoCs platform (S905) config MMC_OWL bool "Actions OWL Multimedia Card Interface support" @@ -415,7 +415,7 @@ config MMC_OMAP36XX_PINS config HSMMC2_8BIT bool "Enable 8-bit interface for eMMC (interface #2)" - depends on MMC_OMAP_HS && (OMAP54XX || DRA7XX || AM33XX || \ + depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \ AM43XX || ARCH_KEYSTONE) config SH_MMCIF @@ -659,8 +659,8 @@ config MMC_SDHCI_MSM depends on MMC_SDHCI && ARCH_SNAPDRAGON help Enables support for SDHCI 2.0 controller present on some Qualcomm - Snapdragon devices. This device is compatible with eMMC v4.5 and - SD 3.0 specifications. Both SD and eMMC devices are supported. + Snapdragon devices. This device is compatible with eMMC v4.5 and + SD 3.0 specifications. Both SD and eMMC devices are supported. Card-detect gpios are not supported. config MMC_SDHCI_MV @@ -852,7 +852,7 @@ config FTSDC010_SDIO bool "Support ftsdc010 sdio" depends on FTSDC010 help - This can enable ftsdc010 sdio function. + This can enable ftsdc010 sdio function. config MMC_MTK bool "MediaTek SD/MMC Card Interface support" diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c index 036e798f374..b756649f90f 100644 --- a/drivers/mmc/cv1800b_sdhci.c +++ b/drivers/mmc/cv1800b_sdhci.c @@ -85,7 +85,7 @@ static int cv1800b_sdhci_probe(struct udevice *dev) int ret; host->name = dev->name; - host->ioaddr = devfdt_get_addr_ptr(dev); + host->ioaddr = dev_read_addr_ptr(dev); upriv->mmc = &plat->mmc; host->mmc = &plat->mmc; @@ -94,6 +94,9 @@ static int cv1800b_sdhci_probe(struct udevice *dev) host->ops = &cv1800b_sdhci_sd_ops; host->max_clk = MMC_MAX_CLOCK; + if (dev_read_bool(dev, "no-1-8-v")) + host->quirks |= SDHCI_QUIRK_NO_1_8_V; + ret = mmc_of_parse(dev, &plat->cfg); if (ret) return ret; diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 87125493c0d..e718a17f94c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -36,7 +36,6 @@ #include <dm/pinctrl.h> #include <dt-structs.h> #include <mapmem.h> -#include <dm/ofnode.h> #include <linux/iopoll.h> #include <linux/dma-mapping.h> @@ -1393,7 +1392,6 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) struct udevice *vqmmc_dev; int ret; - ofnode node = dev_ofnode(dev); fdt_addr_t addr; unsigned int val; @@ -1407,15 +1405,15 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) priv->dev = dev; priv->mode = -1; - val = ofnode_read_u32_default(node, "fsl,tuning-step", 1); + val = dev_read_u32_default(dev, "fsl,tuning-step", 1); priv->tuning_step = val; - val = ofnode_read_u32_default(node, "fsl,tuning-start-tap", - ESDHC_TUNING_START_TAP_DEFAULT); + val = dev_read_u32_default(dev, "fsl,tuning-start-tap", + ESDHC_TUNING_START_TAP_DEFAULT); priv->tuning_start_tap = val; - val = ofnode_read_u32_default(node, "fsl,strobe-dll-delay-target", - ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); + val = dev_read_u32_default(dev, "fsl,strobe-dll-delay-target", + ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); priv->strobe_dll_delay_target = val; - val = ofnode_read_u32_default(node, "fsl,signal-voltage-switch-extra-delay-ms", 0); + val = dev_read_u32_default(dev, "fsl,signal-voltage-switch-extra-delay-ms", 0); priv->signal_voltage_switch_extra_delay_ms = val; if (dev_read_bool(dev, "broken-cd")) diff --git a/drivers/mmc/mmc_bootdev.c b/drivers/mmc/mmc_bootdev.c index 5a1688b75d0..b382521fdeb 100644 --- a/drivers/mmc/mmc_bootdev.c +++ b/drivers/mmc/mmc_bootdev.c @@ -19,7 +19,7 @@ static int mmc_bootdev_bind(struct udevice *dev) return 0; } -struct bootdev_ops mmc_bootdev_ops = { +static const struct bootdev_ops mmc_bootdev_ops = { }; static const struct udevice_id mmc_bootdev_ids[] = { diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index aaa87923604..7bdb02142a2 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -64,14 +64,13 @@ static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); const struct msm_sdhc_variant_info *var_info; - ofnode node = dev_ofnode(dev); ulong clk_rate; int ret, i = 0, n_clks; const char *clk_name; var_info = (void *)dev_get_driver_data(dev); - if (ofnode_read_u32(node, "max-frequency", (uint *)(&clk_rate))) + if (dev_read_u32(dev, "max-frequency", (uint *)(&clk_rate))) clk_rate = 201500000; ret = clk_get_bulk(dev, &prv->clks); @@ -87,7 +86,7 @@ static int msm_sdc_clk_init(struct udevice *dev) } /* If clock-names is unspecified, then the first clock is the core clock */ - if (!ofnode_get_property(node, "clock-names", &n_clks)) { + if (!dev_read_prop(dev, "clock-names", &n_clks)) { if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) { log_warning("Couldn't set core clock rate: %d\n", ret); return -EINVAL; @@ -96,7 +95,7 @@ static int msm_sdc_clk_init(struct udevice *dev) /* Find the index of the "core" clock */ while (i < n_clks) { - ofnode_read_string_index(node, "clock-names", i, &clk_name); + dev_read_string_index(dev, "clock-names", i, &clk_name); if (!strcmp(clk_name, "core")) break; i++; diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index 5af1953cd14..89d511c1a6f 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -375,8 +375,8 @@ static void mvebu_window_setup(const struct mmc *mmc) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if (size && attrib) { mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_CTRL_DATA(size, diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c index bb4fb29424b..b4942f99a52 100644 --- a/drivers/mmc/octeontx_hsmmc.c +++ b/drivers/mmc/octeontx_hsmmc.c @@ -3514,7 +3514,7 @@ static u32 xlate_voltage(u32 voltage) */ static bool octeontx_mmc_get_valid(struct udevice *dev) { - const char *stat = ofnode_read_string(dev_ofnode(dev), "status"); + const char *stat = dev_read_string(dev, "status"); if (!stat || !strncmp(stat, "ok", 2)) return true; @@ -3536,16 +3536,13 @@ static int octeontx_mmc_get_config(struct udevice *dev) uint low, high; char env_name[32]; int err; - ofnode node = dev_ofnode(dev); int bus_width = 1; ulong new_max_freq; debug("%s(%s)", __func__, dev->name); slot->cfg.name = dev->name; - slot->cfg.f_max = ofnode_read_s32_default(dev_ofnode(dev), - "max-frequency", - 26000000); + slot->cfg.f_max = dev_read_s32_default(dev, "max-frequency", 26000000); snprintf(env_name, sizeof(env_name), "mmc_max_frequency%d", slot->bus_id); @@ -3562,26 +3559,21 @@ static int octeontx_mmc_get_config(struct udevice *dev) if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { slot->hs400_tuning_block = - ofnode_read_s32_default(dev_ofnode(dev), - "marvell,hs400-tuning-block", - -1); + dev_read_s32_default(dev, "marvell,hs400-tuning-block", -1); debug("%s(%s): mmc HS400 tuning block: %d\n", __func__, dev->name, slot->hs400_tuning_block); slot->hs200_tap_adj = - ofnode_read_s32_default(dev_ofnode(dev), - "marvell,hs200-tap-adjust", 0); + dev_read_s32_default(dev, "marvell,hs200-tap-adjust", 0); debug("%s(%s): hs200-tap-adjust: %d\n", __func__, dev->name, slot->hs200_tap_adj); slot->hs400_tap_adj = - ofnode_read_s32_default(dev_ofnode(dev), - "marvell,hs400-tap-adjust", 0); + dev_read_s32_default(dev, "marvell,hs400-tap-adjust", 0); debug("%s(%s): hs400-tap-adjust: %d\n", __func__, dev->name, slot->hs400_tap_adj); } - err = ofnode_read_u32_array(dev_ofnode(dev), "voltage-ranges", - voltages, 2); + err = dev_read_u32_array(dev, "voltage-ranges", voltages, 2); if (err) { slot->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; } else { @@ -3601,12 +3593,12 @@ static int octeontx_mmc_get_config(struct udevice *dev) } while (low <= high); } debug("%s: config voltages: 0x%x\n", __func__, slot->cfg.voltages); - slot->slew = ofnode_read_s32_default(node, "cavium,clk-slew", -1); - slot->drive = ofnode_read_s32_default(node, "cavium,drv-strength", -1); + slot->slew = dev_read_s32_default(dev, "cavium,clk-slew", -1); + slot->drive = dev_read_s32_default(dev, "cavium,drv-strength", -1); gpio_request_by_name(dev, "cd-gpios", 0, &slot->cd_gpio, GPIOD_IS_IN); - slot->cd_inverted = ofnode_read_bool(node, "cd-inverted"); + slot->cd_inverted = dev_read_bool(dev, "cd-inverted"); gpio_request_by_name(dev, "wp-gpios", 0, &slot->wp_gpio, GPIOD_IS_IN); - slot->wp_inverted = ofnode_read_bool(node, "wp-inverted"); + slot->wp_inverted = dev_read_bool(dev, "wp-inverted"); if (slot->cfg.voltages & MMC_VDD_165_195) { slot->is_1_8v = true; slot->is_3_3v = false; @@ -3617,7 +3609,7 @@ static int octeontx_mmc_get_config(struct udevice *dev) slot->is_3_3v = true; } - bus_width = ofnode_read_u32_default(node, "bus-width", 1); + bus_width = dev_read_u32_default(dev, "bus-width", 1); /* Note fall-through */ switch (bus_width) { case 8: @@ -3628,63 +3620,63 @@ static int octeontx_mmc_get_config(struct udevice *dev) slot->cfg.host_caps |= MMC_MODE_1BIT; break; } - if (ofnode_read_bool(node, "no-1-8-v")) { + if (dev_read_bool(dev, "no-1-8-v")) { slot->is_3_3v = true; slot->is_1_8v = false; if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34))) pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n", __func__, dev->name); } - if (ofnode_read_bool(node, "mmc-ddr-3-3v")) { + if (dev_read_bool(dev, "mmc-ddr-3-3v")) { slot->is_3_3v = true; slot->is_1_8v = false; if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34))) pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n", __func__, dev->name); } - if (ofnode_read_bool(node, "cap-sd-highspeed") || - ofnode_read_bool(node, "cap-mmc-highspeed") || - ofnode_read_bool(node, "sd-uhs-sdr25")) + if (dev_read_bool(dev, "cap-sd-highspeed") || + dev_read_bool(dev, "cap-mmc-highspeed") || + dev_read_bool(dev, "sd-uhs-sdr25")) slot->cfg.host_caps |= MMC_MODE_HS; if (slot->cfg.f_max >= 50000000 && slot->cfg.host_caps & MMC_MODE_HS) slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; - if (ofnode_read_bool(node, "sd-uhs-sdr50")) + if (dev_read_bool(dev, "sd-uhs-sdr50")) slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; - if (ofnode_read_bool(node, "sd-uhs-ddr50")) + if (dev_read_bool(dev, "sd-uhs-ddr50")) slot->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz; if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) { if (!slot->is_asim && !slot->is_emul) { - if (ofnode_read_bool(node, "mmc-hs200-1_8v")) + if (dev_read_bool(dev, "mmc-hs200-1_8v")) slot->cfg.host_caps |= MMC_MODE_HS200 | MMC_MODE_HS_52MHz; - if (ofnode_read_bool(node, "mmc-hs400-1_8v")) + if (dev_read_bool(dev, "mmc-hs400-1_8v")) slot->cfg.host_caps |= MMC_MODE_HS400 | MMC_MODE_HS_52MHz | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz; slot->cmd_out_hs200_delay = - ofnode_read_u32_default(node, + dev_read_u32_default(dev, "marvell,cmd-out-hs200-dly", MMC_DEFAULT_HS200_CMD_OUT_DLY); debug("%s(%s): HS200 cmd out delay: %d\n", __func__, dev->name, slot->cmd_out_hs200_delay); slot->data_out_hs200_delay = - ofnode_read_u32_default(node, + dev_read_u32_default(dev, "marvell,data-out-hs200-dly", MMC_DEFAULT_HS200_DATA_OUT_DLY); debug("%s(%s): HS200 data out delay: %d\n", __func__, dev->name, slot->data_out_hs200_delay); slot->cmd_out_hs400_delay = - ofnode_read_u32_default(node, + dev_read_u32_default(dev, "marvell,cmd-out-hs400-dly", MMC_DEFAULT_HS400_CMD_OUT_DLY); debug("%s(%s): HS400 cmd out delay: %d\n", __func__, dev->name, slot->cmd_out_hs400_delay); slot->data_out_hs400_delay = - ofnode_read_u32_default(node, + dev_read_u32_default(dev, "marvell,data-out-hs400-dly", MMC_DEFAULT_HS400_DATA_OUT_DLY); debug("%s(%s): HS400 data out delay: %d\n", @@ -3692,12 +3684,10 @@ static int octeontx_mmc_get_config(struct udevice *dev) } } - slot->disable_ddr = ofnode_read_bool(node, "marvell,disable-ddr"); - slot->non_removable = ofnode_read_bool(node, "non-removable"); - slot->cmd_clk_skew = ofnode_read_u32_default(node, - "cavium,cmd-clk-skew", 0); - slot->dat_clk_skew = ofnode_read_u32_default(node, - "cavium,dat-clk-skew", 0); + slot->disable_ddr = dev_read_bool(dev, "marvell,disable-ddr"); + slot->non_removable = dev_read_bool(dev, "non-removable"); + slot->cmd_clk_skew = dev_read_u32_default(dev, "cavium,cmd-clk-skew", 0); + slot->dat_clk_skew = dev_read_u32_default(dev, "cavium,dat-clk-skew", 0); debug("%s(%s): host caps: 0x%x\n", __func__, dev->name, slot->cfg.host_caps); return 0; @@ -3843,7 +3833,6 @@ static int octeontx_mmc_host_probe(struct udevice *dev) pr_err("%s: No device tree information found\n", __func__); return -1; } - host->node = dev_ofnode(dev); host->last_slotid = -1; #if !defined(CONFIG_ARCH_OCTEON) if (otx_is_platform(PLATFORM_ASIM)) @@ -3851,9 +3840,7 @@ static int octeontx_mmc_host_probe(struct udevice *dev) if (otx_is_platform(PLATFORM_EMULATOR)) host->is_emul = true; #endif - host->dma_wait_delay = - ofnode_read_u32_default(dev_ofnode(dev), - "marvell,dma-wait-delay", 1); + host->dma_wait_delay = dev_read_u32_default(dev, "marvell,dma-wait-delay", 1); /* Force reset of eMMC */ writeq(0, host->base_addr + MIO_EMM_CFG()); debug("%s: Clearing MIO_EMM_CFG\n", __func__); @@ -3922,13 +3909,12 @@ static int octeontx_mmc_host_child_pre_probe(struct udevice *dev) struct octeontx_mmc_host *host = dev_get_priv(dev_get_parent(dev)); struct octeontx_mmc_slot *slot; struct mmc_uclass_priv *upriv; - ofnode node = dev_ofnode(dev); u32 bus_id; char name[16]; int err; debug("%s(%s) Pre-Probe\n", __func__, dev->name); - if (ofnode_read_u32(node, "reg", &bus_id)) { + if (dev_read_u32(dev, "reg", &bus_id)) { pr_err("%s(%s): Error: \"reg\" not found in device tree\n", __func__, dev->name); return -1; diff --git a/drivers/mmc/octeontx_hsmmc.h b/drivers/mmc/octeontx_hsmmc.h index 9849121f174..c374ce18838 100644 --- a/drivers/mmc/octeontx_hsmmc.h +++ b/drivers/mmc/octeontx_hsmmc.h @@ -123,7 +123,6 @@ struct octeontx_mmc_host { union mio_emm_cfg emm_cfg; u64 timing_taps; struct mmc *last_mmc; /** Last mmc used */ - ofnode node; int cur_slotid; int last_slotid; int max_width; diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index d446c55f72b..82e393fd9d6 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -137,11 +137,11 @@ static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev, return 0; } -struct acpi_ops pci_mmc_acpi_ops = { #ifdef CONFIG_ACPIGEN +static const struct acpi_ops pci_mmc_acpi_ops = { .fill_ssdt = pci_mmc_acpi_fill_ssdt, -#endif }; +#endif static const struct udevice_id pci_mmc_match[] = { { .compatible = "intel,apl-sd", .data = TYPE_SD }, diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 648dfa4b5ef..08594e10266 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -215,7 +215,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, u32 mask, flags, mode = 0; unsigned int time = 0; int mmc_dev = mmc_get_blk_desc(mmc)->devnum; - ulong start = get_timer(0); + ulong start; host->start_addr = 0; /* Timeout unit - ms */ diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index 0e4902fab77..6aa73792f96 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -537,10 +537,9 @@ static int xenon_sdhci_of_to_plat(struct udevice *dev) host->ioaddr = dev_read_addr_ptr(dev); if (device_is_compatible(dev, "marvell,armada-3700-sdhci")) - priv->pad_ctrl_reg = devfdt_get_addr_index_ptr(dev, 1); + priv->pad_ctrl_reg = dev_read_addr_index_ptr(dev, 1); - name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type", - NULL); + name = ofnode_get_property(dev_ofnode(dev), "marvell,pad-type", NULL); if (name) { if (0 == strncmp(name, "sd", 2)) { priv->pad_type = SOC_PAD_SD; diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 21b8b21f6b2..38d6dd142dd 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -205,16 +205,16 @@ config HBMC_AM654 bool "HyperBus controller driver for AM65x SoC" depends on MULTIPLEXER && (MUX_MMIO || SPL_MUX_MMIO) help - This is the driver for HyperBus controller on TI's AM65x and - other SoCs + This is the driver for HyperBus controller on TI's AM65x and + other SoCs config STM32_FLASH bool "STM32 MCU Flash driver" depends on ARCH_STM32 select USE_SYS_MAX_FLASH_BANKS help - This is the driver of embedded flash for some STMicroelectronics - STM32 MCU. + This is the driver of embedded flash for some STMicroelectronics + STM32 MCU. config SYS_MAX_FLASH_SECT int "Maximum number of sectors on a flash chip" @@ -236,17 +236,17 @@ config SYS_MAX_FLASH_BANKS depends on USE_SYS_MAX_FLASH_BANKS default 1 help - Max number of Flash memory banks using by the MTD framework, in the - flash CFI driver and in some other driver to define the flash_info - struct declaration. + Max number of Flash memory banks using by the MTD framework, in the + flash CFI driver and in some other driver to define the flash_info + struct declaration. config SYS_MAX_FLASH_BANKS_DETECT bool "Detection of flash banks number in CFI driver" depends on CFI_FLASH && FLASH_CFI_DRIVER help - This enables detection of number of flash banks in CFI driver, - to reduce the effective number of flash bank, between 0 and - CONFIG_SYS_MAX_FLASH_BANKS + This enables detection of number of flash banks in CFI driver, + to reduce the effective number of flash bank, between 0 and + CONFIG_SYS_MAX_FLASH_BANKS source "drivers/mtd/nand/Kconfig" diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 2999e6b1710..b5dfad7380f 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -310,47 +310,47 @@ choice prompt "ECC scheme" default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW help - On OMAP platforms, this CONFIG specifies NAND ECC scheme. - It can take following values: - OMAP_ECC_HAM1_CODE_SW + On OMAP platforms, this CONFIG specifies NAND ECC scheme. + It can take following values: + OMAP_ECC_HAM1_CODE_SW 1-bit Hamming code using software lib. (for legacy devices only) - OMAP_ECC_HAM1_CODE_HW + OMAP_ECC_HAM1_CODE_HW 1-bit Hamming code using GPMC hardware. (for legacy devices only) - OMAP_ECC_BCH4_CODE_HW_DETECTION_SW + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW 4-bit BCH code (unsupported) - OMAP_ECC_BCH4_CODE_HW + OMAP_ECC_BCH4_CODE_HW 4-bit BCH code (unsupported) - OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 8-bit BCH code with - ecc calculation using GPMC hardware engine, - error detection using software library. - requires CONFIG_BCH to enable software BCH library (For legacy device which do not have ELM h/w engine) - OMAP_ECC_BCH8_CODE_HW + OMAP_ECC_BCH8_CODE_HW 8-bit BCH code with - ecc calculation using GPMC hardware engine, - error detection using ELM hardware engine. - OMAP_ECC_BCH16_CODE_HW + OMAP_ECC_BCH16_CODE_HW 16-bit BCH code with - ecc calculation using GPMC hardware engine, - error detection using ELM hardware engine. - How to select ECC scheme on OMAP and AMxx platforms ? - ----------------------------------------------------- - Though higher ECC schemes have more capability to detect and correct - bit-flips, but still selection of ECC scheme is dependent on following - - hardware engines present in SoC. + How to select ECC scheme on OMAP and AMxx platforms ? + ----------------------------------------------------- + Though higher ECC schemes have more capability to detect and correct + bit-flips, but still selection of ECC scheme is dependent on following + - hardware engines present in SoC. Some legacy OMAP SoC do not have ELM h/w engine thus such SoC cannot support BCHx_HW ECC schemes. - - size of OOB/Spare region + - size of OOB/Spare region With higher ECC schemes, more OOB/Spare area is required to store ECC. So choice of ECC scheme is limited by NAND oobsize. - In general following expression can help: + In general following expression can help: NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES - where + where NAND_OOBSIZE = number of bytes available in OOB/spare area per NAND page. NAND_PAGESIZE = bytes in main-area of NAND page. diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 7324dc72e0a..ef01d48acc0 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -184,6 +184,7 @@ struct pxa3xx_nand_host { struct pxa3xx_nand_info { struct nand_hw_control controller; struct pxa3xx_nand_platform_data *pdata; + struct udevice *dev; struct clk *clk; void __iomem *mmio_base; @@ -585,8 +586,7 @@ static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) ts = get_timer(0); while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) { if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) { - dev_err(info->controller.active->mtd.dev, - "Timeout on RDDREQ while draining the FIFO\n"); + dev_err(info->dev, "Timeout on RDDREQ while draining the FIFO\n"); return; } } @@ -638,8 +638,7 @@ static void handle_data_pio(struct pxa3xx_nand_info *info) DIV_ROUND_UP(info->step_spare_size, 4)); break; default: - dev_err(info->controller.active->mtd.dev, - "%s: invalid state %d\n", __func__, info->state); + dev_err(info->dev, "%s: invalid state %d\n", __func__, info->state); BUG(); } @@ -1557,8 +1556,7 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info, ecc->size = 512; if (ecc_stepsize != 512 || !(nfc_layouts[i].strength)) { - dev_err(info->controller.active->mtd.dev, - "ECC strength %d at page size %d is not supported\n", + dev_err(info->dev, "ECC strength %d at page size %d is not supported\n", strength, page_size); return -ENODEV; } @@ -1799,6 +1797,7 @@ static int pxa3xx_nand_probe(struct udevice *dev) if (ret) return ret; + info->dev = dev; pdata = info->pdata; ret = alloc_nand_resource(dev, info); diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index de78a6cb707..4ff58380b59 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -94,39 +94,39 @@ config SPI_FLASH_SFDP_SUPPORT bool "SFDP table parsing support for SPI NOR flashes" depends on !SPI_FLASH_BAR help - Enable support for parsing and auto discovery of parameters for - SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) - tables as per JESD216 standard. + Enable support for parsing and auto discovery of parameters for + SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) + tables as per JESD216 standard. config SPI_FLASH_SMART_HWCAPS bool "Smart hardware capability detection based on SPI MEM supports_op() hook" default y help - Enable support for smart hardware capability detection based on SPI - MEM supports_op() hook that lets controllers express whether they - can support a type of operation in a much more refined way compared - to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc. + Enable support for smart hardware capability detection based on SPI + MEM supports_op() hook that lets controllers express whether they + can support a type of operation in a much more refined way compared + to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc. config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT bool "Command extension type is INVERT for Software Reset on boot" help - Because of SFDP information can not be get before boot. - So define command extension type is INVERT when Software Reset on boot only. + Because of SFDP information can not be get before boot. + So define command extension type is INVERT when Software Reset on boot only. config SPI_FLASH_SOFT_RESET bool "Software Reset support for SPI NOR flashes" help - Enable support for xSPI Software Reset. It will be used to switch from - Octal DTR mode to legacy mode on shutdown and boot (if enabled). + Enable support for xSPI Software Reset. It will be used to switch from + Octal DTR mode to legacy mode on shutdown and boot (if enabled). config SPI_FLASH_SOFT_RESET_ON_BOOT bool "Perform a Software Reset on boot on flashes that boot in stateful mode" depends on SPI_FLASH_SOFT_RESET help - Perform a Software Reset on boot to allow detecting flashes that are - handed to us in Octal DTR mode. Do not enable this config on flashes - that are not supposed to be handed to U-Boot in Octal DTR mode, even - if they _do_ support the Soft Reset sequence. + Perform a Software Reset on boot to allow detecting flashes that are + handed to us in Octal DTR mode. Do not enable this config on flashes + that are not supposed to be handed to U-Boot in Octal DTR mode, even + if they _do_ support the Soft Reset sequence. config SPI_FLASH_BAR bool "SPI flash Bank/Extended address register support" @@ -139,18 +139,18 @@ config SPI_FLASH_LOCK bool "Enable the Locking feature" default y help - Enable the SPI flash lock support. By default this is set to y. - If you intend not to use the lock support you should say n here. + Enable the SPI flash lock support. By default this is set to y. + If you intend not to use the lock support you should say n here. config SPI_FLASH_UNLOCK_ALL bool "Unlock the entire SPI flash on u-boot startup" default y help - Some flashes tend to power up with the software write protection - bits set. If this option is set, the whole flash will be unlocked. + Some flashes tend to power up with the software write protection + bits set. If this option is set, the whole flash will be unlocked. - For legacy reasons, this option default to y. But if you intend to - actually use the software protection bits you should say n here. + For legacy reasons, this option default to y. But if you intend to + actually use the software protection bits you should say n here. config SPI_FLASH_ATMEL bool "Atmel SPI flash support" @@ -201,9 +201,9 @@ config SPI_FLASH_S28HX_T bool "Cypress SEMPER Octal (S28) chip support" depends on SPI_FLASH_SPANSION help - Add support for the Cypress S28HL-T and S28HS-T chip. This is a separate - config because the fixup hooks for this flash add extra size overhead. - Boards that don't use the flash can disable this to save space. + Add support for the Cypress S28HL-T and S28HS-T chip. This is a separate + config because the fixup hooks for this flash add extra size overhead. + Boards that don't use the flash can disable this to save space. config SPI_FLASH_STMICRO bool "STMicro SPI flash support" @@ -214,9 +214,9 @@ config SPI_FLASH_MT35XU bool "Micron MT35XU chip support" depends on SPI_FLASH_STMICRO help - Add support for the Micron MT35XU chip. This is a separate config - because the fixup hooks for this flash add extra size overhead. Boards - that don't use the flash can disable this to save space. + Add support for the Micron MT35XU chip. This is a separate config + because the fixup hooks for this flash add extra size overhead. Boards + that don't use the flash can disable this to save space. config SPI_FLASH_SST bool "SST SPI flash support" @@ -282,7 +282,7 @@ config SPI_FLASH_MTD bool "SPI Flash MTD support" depends on SPI_FLASH && MTD help - Enable the MTD support for spi flash layer, this adapter is for + Enable the MTD support for spi flash layer, this adapter is for translating mtd_read/mtd_write commands into spi_flash_read/write commands. It is not intended to use it within sf_cmd or the SPI flash subsystem. Such an adapter is needed for subsystems like @@ -294,7 +294,7 @@ config SPL_SPI_FLASH_MTD bool "SPI flash MTD support for SPL" depends on SPI_FLASH && SPL help - Enable the MTD support for the SPI flash layer in SPL. + Enable the MTD support for the SPI flash layer in SPL. If unsure, say N diff --git a/drivers/mtd/spi/sf_bootdev.c b/drivers/mtd/spi/sf_bootdev.c index 017a74a3016..6ace4ee0aed 100644 --- a/drivers/mtd/spi/sf_bootdev.c +++ b/drivers/mtd/spi/sf_bootdev.c @@ -57,7 +57,7 @@ static int sf_bootdev_bind(struct udevice *dev) return 0; } -struct bootdev_ops sf_bootdev_ops = { +static const struct bootdev_ops sf_bootdev_ops = { .get_bootflow = sf_get_bootflow, }; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index c0fa98424aa..31a2ba49a87 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -231,6 +231,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd55lb02gf", 0xc8601c, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index ba77c034736..e523a4c4707 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -82,8 +82,8 @@ config MTD_UBI_BEB_LIMIT config MTD_UBI_FASTMAP bool "UBI Fastmap (Experimental feature)" help - Important: this feature is experimental so far and the on-flash - format for fastmap may change in the next kernel versions + Important: this feature is experimental so far and the on-flash + format for fastmap may change in the next kernel versions Fastmap is a mechanism which allows attaching an UBI device in nearly constant time. Instead of scanning the whole MTD device it diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig index de74e5d5e4e..383dac532c1 100644 --- a/drivers/mux/Kconfig +++ b/drivers/mux/Kconfig @@ -5,17 +5,17 @@ config MULTIPLEXER depends on DM select DEVRES help - The mux framework is a minimalistic subsystem that handles multiplexer - controllers. It provides the same API as Linux and mux drivers should - be portable with a minimum effort. + The mux framework is a minimalistic subsystem that handles multiplexer + controllers. It provides the same API as Linux and mux drivers should + be portable with a minimum effort. if MULTIPLEXER config SPL_MUX_MMIO bool "MMIO register bitfield-controlled Multiplexer" - depends on MULTIPLEXER && SYSCON - help - MMIO register bitfield-controlled Multiplexer controller. + depends on MULTIPLEXER && SYSCON + help + MMIO register bitfield-controlled Multiplexer controller. The driver builds multiplexer controllers for bitfields in a syscon register. For N bit wide bitfields, there will be 2^N possible diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 666618681df..4399c6c7a99 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -184,10 +184,10 @@ config CALXEDA_XGMAC config DWC_ETH_XGMAC bool select PHYLIB - help - This driver supports the Synopsys Designware Ethernet XGMAC (10G - Ethernet MAC) IP block. The IP supports many options for bus type, - clocking/reset structure, and feature list. + help + This driver supports the Synopsys Designware Ethernet XGMAC (10G + Ethernet MAC) IP block. The IP supports many options for bus type, + clocking/reset structure, and feature list. config DWC_ETH_XGMAC_SOCFPGA bool "Synopsys DWC Ethernet XGMAC device support for SOCFPGA" @@ -229,8 +229,8 @@ config DWC_ETH_QOS_ADI bool "Synopsys DWC Ethernet QOS device support for ADI SC59x-64 parts" depends on DWC_ETH_QOS && ARCH_SC5XX help - The Synopsis Designware Ethernet QoS IP block with the specific - configuration used in the ADI ADSP-SC59X 64 bit SoCs + The Synopsis Designware Ethernet QoS IP block with the specific + configuration used in the ADI ADSP-SC59X 64 bit SoCs config DWC_ETH_QOS_IMX bool "Synopsys DWC Ethernet QOS device support for IMX" @@ -246,6 +246,20 @@ config DWC_ETH_QOS_INTEL The Synopsys Designware Ethernet QOS IP block with the specific configuration used in the Intel Elkhart-Lake soc. +config DWC_ETH_QOS_MTK + bool "Synopsys DWC Ethernet QOS device support for MediaTek SoCs" + depends on DWC_ETH_QOS && ARCH_MEDIATEK + help + The Synopsys Designware Ethernet QOS IP block with the specific + configuration used in MediaTek SoCs. + +config DWC_ETH_QOS_QCOM + bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs" + depends on DWC_ETH_QOS + help + The Synopsys Designware Ethernet QOS IP block with specific + configuration used in Qcom QCS404 SoC. + config DWC_ETH_QOS_ROCKCHIP bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs" depends on DWC_ETH_QOS && ARCH_ROCKCHIP @@ -254,6 +268,13 @@ config DWC_ETH_QOS_ROCKCHIP The Synopsys Designware Ethernet QOS IP block with specific configuration used in Rockchip SoCs. +config DWC_ETH_QOS_STARFIVE + bool "Synopsys DWC Ethernet QOS device support for STARFIVE" + depends on DWC_ETH_QOS + help + The Synopsys Designware Ethernet QOS IP block with specific + configuration used in STARFIVE JH7110 soc. + config DWC_ETH_QOS_STM32 bool "Synopsys DWC Ethernet QOS device support for STM32" depends on DWC_ETH_QOS && ARCH_STM32MP @@ -271,20 +292,6 @@ config DWC_ETH_QOS_TEGRA186 The Synopsys Designware Ethernet QOS IP block with specific configuration used in NVIDIA's Tegra186 chip. -config DWC_ETH_QOS_QCOM - bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs" - depends on DWC_ETH_QOS - help - The Synopsys Designware Ethernet QOS IP block with specific - configuration used in Qcom QCS404 SoC. - -config DWC_ETH_QOS_STARFIVE - bool "Synopsys DWC Ethernet QOS device support for STARFIVE" - depends on DWC_ETH_QOS - help - The Synopsys Designware Ethernet QOS IP block with specific - configuration used in STARFIVE JH7110 soc. - config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" depends on PCI @@ -460,9 +467,9 @@ config FSL_FM_10GEC_REGULAR_NOTATION help On SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 + 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 While on SoCs T1024, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC1, 10GEC2->MAC2 + 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. @@ -529,7 +536,7 @@ config KSZ9477 config LITEETH bool "LiteX LiteEth Ethernet MAC" help - Driver for the LiteEth Ethernet MAC from LiteX. + Driver for the LiteEth Ethernet MAC from LiteX. config MV88E6XXX bool "Marvell MV88E6xxx Ethernet switch DSA driver" @@ -701,12 +708,12 @@ config SJA1105 family. These are 5-port devices and are managed over an SPI interface. Probing is handled based on OF bindings. The driver supports the following revisions: - - SJA1105E (Gen. 1, No TT-Ethernet) - - SJA1105T (Gen. 1, TT-Ethernet) - - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet) - - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet) - - SJA1105R (Gen. 2, SGMII, No TT-Ethernet) - - SJA1105S (Gen. 2, SGMII, TT-Ethernet) + - SJA1105E (Gen. 1, No TT-Ethernet) + - SJA1105T (Gen. 1, TT-Ethernet) + - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet) + - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet) + - SJA1105R (Gen. 2, SGMII, No TT-Ethernet) + - SJA1105S (Gen. 2, SGMII, TT-Ethernet) config SMC911X bool "SMSC LAN911x and LAN921x controller driver" @@ -740,11 +747,11 @@ config SUN4I_EMAC This driver supports the Allwinner based SUN4I Ethernet MAC. config SUN8I_EMAC - bool "Allwinner Sun8i Ethernet MAC support" - select PHYLIB + bool "Allwinner Sun8i Ethernet MAC support" + select PHYLIB select PHY_GIGE - help - This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. + help + This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. It can be found in H3/A64/A83T based SoCs and compatible with both External and Internal PHYs. @@ -905,7 +912,7 @@ config FEC1_PHY help Define to the hardcoded PHY address which corresponds to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 + #define CONFIG_FEC1_PHY 4 means that the PHY with address 4 is connected to FEC1 When set to -1, means to probe for first available. @@ -929,7 +936,7 @@ config FEC2_PHY help Define to the hardcoded PHY address which corresponds to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 + #define CONFIG_FEC1_PHY 4 means that the PHY with address 4 is connected to FEC1 When set to -1, means to probe for first available. @@ -1018,8 +1025,8 @@ config FSL_ENETC config FSL_ENETC_NETC_BLK_CTRL bool "NXP ENETC NETC blocks control driver" depends on FSL_ENETC - depends on IMX95 || IMX94 - default y if IMX95 || IMX94 + depends on IMX95 || IMX94 || IMX952 + default y if IMX95 || IMX94 || IMX952 help This driver configures Integrated Endpoint Register Block (IERB) and Privileged Register Block (PRB) of NETC. For i.MX platforms, it also @@ -1034,7 +1041,7 @@ config MDIO_GPIO_BITBANG bool "GPIO bitbanging MDIO driver" depends on DM_MDIO && DM_GPIO help - Driver for bitbanging MDIO + Driver for bitbanging MDIO config MDIO_MUX_I2CREG bool "MDIO MUX accessed as a register over I2C" @@ -1080,8 +1087,8 @@ config MDIO_MSCC_MIIM depends on DM_MDIO select REGMAP help - This driver supports MDIO interface found in Microsemi and Microchip - network switches. + This driver supports MDIO interface found in Microsemi and Microchip + network switches. config MDIO_MUX_MMIOREG bool "MDIO MUX accessed as a MMIO register access" diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 5e90183d090..761f7f0f451 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o -obj-y += airoha/ obj-$(CONFIG_AIROHA_ETH) += airoha_eth.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o @@ -22,12 +21,13 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_ADI) += dwc_eth_qos_adi.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o obj-$(CONFIG_DWC_ETH_QOS_INTEL) += dwc_eth_qos_intel.o -obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o +obj-$(CONFIG_DWC_ETH_QOS_MTK) += dwc_eth_qos_mtk.o obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o -obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o -obj-$(CONFIG_DWC_ETH_XGMAC_SOCFPGA) += dwc_eth_xgmac_socfpga.o +obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o obj-$(CONFIG_DWC_ETH_QOS_STM32) += dwc_eth_qos_stm32.o +obj-$(CONFIG_DWC_ETH_XGMAC) += dwc_eth_xgmac.o +obj-$(CONFIG_DWC_ETH_XGMAC_SOCFPGA) += dwc_eth_xgmac_socfpga.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o obj-$(CONFIG_EEPRO100) += eepro100.o @@ -62,9 +62,9 @@ obj-$(CONFIG_KSZ9477) += ksz9477.o obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o +obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o -obj-$(CONFIG_MDIO_GPIO_BITBANG) += mdio_gpio.o obj-$(CONFIG_MDIO_MT7531_MMIO) += mdio-mt7531-mmio.o obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o obj-$(CONFIG_MDIO_MUX_MESON_G12A) += mdio_mux_meson_g12a.o @@ -109,6 +109,7 @@ obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o +obj-y += airoha/ obj-y += mscc_eswitch/ obj-y += phy/ obj-y += qe/ diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index 92990fa6d47..df0ed820e06 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -555,7 +555,7 @@ static int xgmac_ofdata_to_platdata(struct udevice *dev) return -ENOMEM; dev_set_priv(dev, priv); - pdata->iobase = devfdt_get_addr(dev); + pdata->iobase = dev_read_addr(dev); if (pdata->iobase == FDT_ADDR_T_NONE) { printf("%s: Cannot find XGMAC base address\n", __func__); return -EINVAL; diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 8fa549280aa..2a21eceac57 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -653,7 +653,7 @@ static int dc2114x_of_to_plat(struct udevice *dev) struct eth_pdata *plat = dev_get_plat(dev); struct dc2114x_priv *priv = dev_get_priv(dev); - plat->iobase = (phys_addr_t)map_physmem((phys_addr_t)devfdt_get_addr(dev), 0, MAP_NOCACHE); + plat->iobase = (phys_addr_t)dev_remap_addr(dev); priv->iobase = (void *)plat->iobase; return 0; diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 0f31d646845..b7e6299c307 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1659,6 +1659,12 @@ static const struct udevice_id eqos_ids[] = { .data = (ulong)&eqos_adi_config }, #endif +#if IS_ENABLED(CONFIG_DWC_ETH_QOS_MTK) + { + .compatible = "mediatek,mt8189-gmac", + .data = (ulong)&eqos_mtk_config + }, +#endif { } }; diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index ba16f1a37cb..978b848b46e 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -97,6 +97,7 @@ struct eqos_mac_regs { #define EQOS_MAC_MDIO_ADDRESS_PA_MASK GENMASK(25, 21) #define EQOS_MAC_MDIO_ADDRESS_RDA_MASK GENMASK(20, 16) #define EQOS_MAC_MDIO_ADDRESS_CR_MASK GENMASK(11, 8) +#define EQOS_MAC_MDIO_ADDRESS_CR_60_100 0 #define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 #define EQOS_MAC_MDIO_ADDRESS_CR_150_250 4 @@ -316,3 +317,4 @@ extern struct eqos_config eqos_stm32mp15_config; extern struct eqos_config eqos_stm32mp25_config; extern struct eqos_config eqos_jh7110_config; extern struct eqos_config eqos_adi_config; +extern struct eqos_config eqos_mtk_config; diff --git a/drivers/net/dwc_eth_qos_mtk.c b/drivers/net/dwc_eth_qos_mtk.c new file mode 100644 index 00000000000..43e1085dfe5 --- /dev/null +++ b/drivers/net/dwc_eth_qos_mtk.c @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan <[email protected]> + */ + +#include <dm.h> +#include <dm/device_compat.h> +#include <linux/bitfield.h> +#include <net.h> +#include <phy.h> +#include <regmap.h> +#include <syscon.h> + +#include "dwc_eth_qos.h" + +/* + * Peri Configuration register is SoC specific, + * so add a SoC specific prefix. + */ +#define MT8189_PERI_ETH_CTRL0 0x270 +#define MT8189_PERI_ETH_CTRL1 0x274 +#define MT8189_PERI_ETH_CTRL2 0x278 + +#define EQOS_MTK_RMII_CLK_SRC_INTERNAL BIT(28) +#define EQOS_MTK_RMII_CLK_SRC_RXC BIT(27) +#define EQOS_MTK_ETH_INTF_SEL GENMASK(26, 24) +#define EQOS_MTK_PHY_INTF_MII 0 +#define EQOS_MTK_PHY_INTF_RGMII 1 +#define EQOS_MTK_PHY_INTF_RMII 4 +#define EQOS_MTK_RGMII_TXC_PHASE_CTRL BIT(22) +#define EQOS_MTK_EXT_PHY_MODE BIT(21) +#define EQOS_MTK_TXC_OUT_OP BIT(20) +#define EQOS_MTK_DLY_GTXC_INV BIT(12) +#define EQOS_MTK_DLY_GTXC_STAGE_FINE GENMASK(11, 6) +#define EQOS_MTK_DLY_GTXC_ENABLE BIT(5) +#define EQOS_MTK_DLY_GTXC_STAGES GENMASK(4, 0) + +#define EQOS_MTK_DLY_RXC_INV BIT(25) +#define EQOS_MTK_DLY_RXC_ENABLE BIT(18) +#define EQOS_MTK_DLY_RXC_STAGES GENMASK(17, 13) +#define EQOS_MTK_DLY_TXC_INV BIT(12) +#define EQOS_MTK_DLY_TXC_ENABLE BIT(5) +#define EQOS_MTK_DLY_TXC_STAGES GENMASK(4, 0) + +#define EQOS_MTK_DLY_RMII_RXC_INV BIT(25) +#define EQOS_MTK_DLY_RMII_RXC_ENABLE BIT(18) +#define EQOS_MTK_DLY_RMII_RXC_STAGES GENMASK(17, 13) +#define EQOS_MTK_DLY_RMII_TXC_INV BIT(12) +#define EQOS_MTK_DLY_RMII_TXC_ENABLE BIT(5) +#define EQOS_MTK_DLY_RMII_TXC_STAGES GENMASK(4, 0) + +#define DELAY_MAX_PS 9800 +#define DELAY_PS_PER_STAGE 290 + +struct eqos_mtk_priv { + struct regmap *peri_regmap; + bool rmii_clk_from_mac; + bool rmii_rxc; + u32 tx_delay_stage; + u32 rx_delay_stage; + bool tx_inv; + bool rx_inv; +}; + +static int mtk_clk_init(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + ret = clk_get_by_name(dev, "mac_main", &eqos->clk_tx); + if (ret) { + dev_err(dev, "clk_get_by_name(mac_main) failed: %d", ret); + return ret; + } + + ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); + if (ret) { + dev_err(dev, "clk_get_by_name(ptp_ref) failed: %d", ret); + return ret; + } + + return 0; +} + +static int mtk_set_delay(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0; + + switch (pdata->phy_interface) { + case PHY_INTERFACE_MODE_MII: + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_ENABLE, + !!mtk_pdata->tx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_STAGES, mtk_pdata->tx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_INV, mtk_pdata->tx_inv); + + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_STAGES, mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_INV, mtk_pdata->rx_inv); + break; + case PHY_INTERFACE_MODE_RMII: + if (mtk_pdata->rmii_clk_from_mac) { + /* case 1: mac provides the rmii reference clock, + * and the clock output to TXC pin. + * The egress timing can be adjusted by RMII_TXC delay macro circuit. + * The ingress timing can be adjusted by RMII_RXC delay macro circuit. + */ + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_TXC_ENABLE, + !!mtk_pdata->tx_delay_stage); + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_TXC_STAGES, + mtk_pdata->tx_delay_stage); + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_TXC_INV, + mtk_pdata->tx_inv); + + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_RXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_RXC_STAGES, + mtk_pdata->rx_delay_stage); + rmii_delay_val |= FIELD_PREP(EQOS_MTK_DLY_RMII_RXC_INV, + mtk_pdata->rx_inv); + } else { + /* case 2: the rmii reference clock is from external phy, + * and the property "rmii_rxc" indicates which pin(TXC/RXC) + * the reference clk is connected to. The reference clock is a + * received signal, so rx_delay_stage/rx_inv are used to indicate + * the reference clock timing adjustment + */ + if (mtk_pdata->rmii_rxc) { + /* the rmii reference clock from outside is connected + * to RXC pin, the reference clock will be adjusted + * by RXC delay macro circuit. + */ + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_STAGES, + mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_INV, + mtk_pdata->rx_inv); + } else { + /* the rmii reference clock from outside is connected + * to TXC pin, the reference clock will be adjusted + * by TXC delay macro circuit. + */ + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_STAGES, + mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_TXC_INV, + mtk_pdata->rx_inv); + } + } + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + gtxc_delay_val |= FIELD_PREP(EQOS_MTK_DLY_GTXC_ENABLE, + !!mtk_pdata->tx_delay_stage); + gtxc_delay_val |= FIELD_PREP(EQOS_MTK_DLY_GTXC_STAGES, + mtk_pdata->tx_delay_stage); + gtxc_delay_val |= FIELD_PREP(EQOS_MTK_DLY_GTXC_INV, mtk_pdata->tx_inv); + gtxc_delay_val |= EQOS_MTK_DLY_GTXC_STAGE_FINE; + + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_ENABLE, + !!mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_STAGES, mtk_pdata->rx_delay_stage); + delay_val |= FIELD_PREP(EQOS_MTK_DLY_RXC_INV, mtk_pdata->rx_inv); + + break; + default: + dev_err(dev, "phy interface not supported\n"); + return -EINVAL; + } + + regmap_update_bits(mtk_pdata->peri_regmap, + MT8189_PERI_ETH_CTRL0, + EQOS_MTK_RGMII_TXC_PHASE_CTRL | + EQOS_MTK_DLY_GTXC_ENABLE | + EQOS_MTK_DLY_GTXC_INV | + EQOS_MTK_DLY_GTXC_STAGE_FINE | + EQOS_MTK_DLY_GTXC_STAGES, + gtxc_delay_val); + regmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL1, delay_val); + regmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL2, rmii_delay_val); + + return 0; +} + +static int mtk_set_interface(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + int rmii_clk_from_mac = mtk_pdata->rmii_clk_from_mac ? EQOS_MTK_RMII_CLK_SRC_INTERNAL : 0; + int rmii_rxc = mtk_pdata->rmii_rxc ? EQOS_MTK_RMII_CLK_SRC_RXC : 0; + u32 intf_val = 0; + + /* select phy interface in top control domain */ + switch (pdata->phy_interface) { + case PHY_INTERFACE_MODE_MII: + intf_val |= FIELD_PREP(EQOS_MTK_ETH_INTF_SEL, EQOS_MTK_PHY_INTF_MII); + break; + case PHY_INTERFACE_MODE_RMII: + intf_val |= (rmii_rxc | rmii_clk_from_mac); + intf_val |= FIELD_PREP(EQOS_MTK_ETH_INTF_SEL, EQOS_MTK_PHY_INTF_RMII); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + intf_val |= FIELD_PREP(EQOS_MTK_ETH_INTF_SEL, EQOS_MTK_PHY_INTF_RGMII); + break; + default: + dev_err(dev, "phy interface not supported\n"); + return -EINVAL; + } + + /* only support external PHY */ + intf_val |= EQOS_MTK_EXT_PHY_MODE; + + intf_val |= EQOS_MTK_TXC_OUT_OP; + + regmap_write(mtk_pdata->peri_regmap, MT8189_PERI_ETH_CTRL0, intf_val); + + return 0; +} + +static int mtk_config_dt(struct udevice *dev) +{ struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + struct ofnode_phandle_args args; + u32 tx_delay_ps = 0, rx_delay_ps = 0; + int ret; + + if (!dev_read_u32(dev, "mediatek,tx-delay-ps", &tx_delay_ps)) { + if (tx_delay_ps > DELAY_MAX_PS) { + dev_err(dev, "Invalid TX clock delay: %dps\n", tx_delay_ps); + return -EINVAL; + } + } + + if (!dev_read_u32(dev, "mediatek,rx-delay-ps", &rx_delay_ps)) { + if (rx_delay_ps > DELAY_MAX_PS) { + dev_err(dev, "Invalid RX clock delay: %dps\n", rx_delay_ps); + return -EINVAL; + } + } + + mtk_pdata->tx_delay_stage = tx_delay_ps / DELAY_PS_PER_STAGE; + mtk_pdata->rx_delay_stage = rx_delay_ps / DELAY_PS_PER_STAGE; + + mtk_pdata->tx_inv = dev_read_bool(dev, "mediatek,txc-inverse"); + mtk_pdata->rx_inv = dev_read_bool(dev, "mediatek,rxc-inverse"); + mtk_pdata->rmii_clk_from_mac = dev_read_bool(dev, "mediatek,rmii-clk-from-mac"); + mtk_pdata->rmii_rxc = dev_read_bool(dev, "mediatek,rmii-rxc"); + + ret = dev_read_phandle_with_args(dev, "mediatek,pericfg", NULL, 0, 0, &args); + if (ret) { + dev_err(dev, "Failed to get mediatek,pericfg property: %d\n", ret); + return ret; + } + + mtk_pdata->peri_regmap = syscon_node_to_regmap(args.node); + if (IS_ERR(mtk_pdata->peri_regmap)) { + dev_err(dev, "fail to get regmap: %d\n", (int)PTR_ERR(mtk_pdata->peri_regmap)); + return PTR_ERR(mtk_pdata->peri_regmap); + } + + return 0; +} + +static int eqos_probe_resources_mtk(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata; + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = eqos_get_base_addr_dt(dev); + if (ret) { + dev_err(dev, "eqos_get_base_addr_dt failed: %d\n", ret); + return ret; + } + + mtk_pdata = calloc(1, sizeof(struct eqos_mtk_priv)); + if (!mtk_pdata) + return -ENOMEM; + + pdata->priv_pdata = mtk_pdata; + + ret = mtk_config_dt(dev); + if (ret) { + dev_err(dev, "mtk config dt failed: %d\n", ret); + goto err; + } + + ret = mtk_clk_init(dev); + if (ret) + goto err; + + pdata->phy_interface = eqos->config->interface(dev); + if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) { + dev_err(dev, "Invalid PHY interface\n"); + ret = -EINVAL; + goto err; + } + + ret = mtk_set_interface(dev); + if (ret) + goto err; + + ret = mtk_set_delay(dev); + if (ret) + goto err; + + debug("%s: OK\n", __func__); + return 0; +err: + free(mtk_pdata); + return ret; +} + +static int eqos_remove_resources_mtk(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + + debug("%s(dev=%p):\n", __func__, dev); + + free(mtk_pdata); + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_stop_clks_mtk(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clk_disable(&eqos->clk_ptp_ref); + clk_disable(&eqos->clk_tx); + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_start_clks_mtk(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = clk_enable(&eqos->clk_tx); + if (ret < 0) { + dev_err(dev, "clk_enable(mac_main) failed: %d", ret); + goto err; + } + + ret = clk_enable(&eqos->clk_ptp_ref); + if (ret < 0) { + dev_err(dev, "clk_enable(ptp_ref) failed: %d", ret); + goto err_disable_clk_mac_main; + } + + debug("%s: OK\n", __func__); + return 0; + +err_disable_clk_mac_main: + clk_disable(&eqos->clk_tx); +err: + debug("%s: FAILED: %d\n", __func__, ret); + return ret; +} + +static int eqos_fix_mac_speed_mtk(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct eqos_mtk_priv *mtk_pdata = pdata->priv_pdata; + + debug("%s(dev=%p):\n", __func__, dev); + + switch (pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: + if (eqos->phy->speed == SPEED_1000) + regmap_update_bits(mtk_pdata->peri_regmap, + MT8189_PERI_ETH_CTRL0, + EQOS_MTK_RGMII_TXC_PHASE_CTRL | + EQOS_MTK_DLY_GTXC_ENABLE | + EQOS_MTK_DLY_GTXC_INV | + EQOS_MTK_DLY_GTXC_STAGE_FINE | + EQOS_MTK_DLY_GTXC_STAGES, + EQOS_MTK_RGMII_TXC_PHASE_CTRL); + else + mtk_set_delay(dev); + break; + default: + debug("%s: dev=%p no need to adjust mac delay\n", __func__, dev); + break; + } + + debug("%s: OK\n", __func__); + return 0; +} + +static struct eqos_ops eqos_mtk_ops = { + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, + .eqos_inval_buffer = eqos_inval_buffer_generic, + .eqos_flush_buffer = eqos_flush_buffer_generic, + .eqos_probe_resources = eqos_probe_resources_mtk, + .eqos_remove_resources = eqos_remove_resources_mtk, + .eqos_stop_resets = eqos_null_ops, + .eqos_start_resets = eqos_null_ops, + .eqos_stop_clks = eqos_stop_clks_mtk, + .eqos_start_clks = eqos_start_clks_mtk, + .eqos_calibrate_pads = eqos_null_ops, + .eqos_disable_calibration = eqos_null_ops, + .eqos_set_tx_clk_speed = eqos_fix_mac_speed_mtk, + .eqos_get_enetaddr = eqos_null_ops, +}; + +struct eqos_config eqos_mtk_config = { + .reg_access_always_ok = false, + .mdio_wait = 10000, + .swr_wait = 10, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_60_100, + .axi_bus_width = EQOS_AXI_WIDTH_64, + .interface = dev_read_phy_mode, + .ops = &eqos_mtk_ops +}; diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index dc7e6f1929f..87b2b3426c8 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -686,7 +686,7 @@ static int ethoc_of_to_plat(struct udevice *dev) fdt_addr_t addr; pdata->eth_pdata.iobase = dev_read_addr(dev); - addr = devfdt_get_addr_index(dev, 1); + addr = dev_read_addr_index(dev, 1); if (addr != FDT_ADDR_T_NONE) pdata->packet_base = addr; return 0; diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 206f1a381bb..f393af40e27 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -18,6 +18,7 @@ #include <asm/io.h> #include <pci.h> #include <miiphy.h> +#include <linux/bitfield.h> #include <linux/bug.h> #include <linux/delay.h> #include <linux/build_bug.h> @@ -74,10 +75,36 @@ static int enetc_is_ls1028a(struct udevice *dev) pplat->vendor == PCI_VENDOR_ID_FREESCALE; } +static int enetc_dev_id_imx(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_IMX952)) { + int bus_devfn; + u32 reg[5]; + int error; + + error = dev_read_u32_array(dev, "reg", reg, ARRAY_SIZE(reg)); + if (error) + return error; + + bus_devfn = (reg[0] >> 8) & 0xffff; + + switch (bus_devfn) { + case 0: + return 0; + case 0x100: + return 1; + default: + return -EINVAL; + } + } + + return PCI_DEV(pci_get_devfn(dev)) >> 3; +} + static int enetc_dev_id(struct udevice *dev) { if (enetc_is_imx95(dev)) - return PCI_DEV(pci_get_devfn(dev)) >> 3; + return enetc_dev_id_imx(dev); if (enetc_is_ls1028a(dev)) return PCI_FUNC(pci_get_devfn(dev)); @@ -396,7 +423,7 @@ static int enetc_init_sgmii(struct udevice *dev) /* set up MAC for RGMII */ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) { - u32 old_val, val, dpx = 0; + u32 old_val, val = 0; old_val = val = enetc_read_mac_port(dev, ENETC_PM_IF_MODE); @@ -416,15 +443,14 @@ static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) val |= ENETC_PM_IFM_SSP_10; } - if (enetc_is_imx95(dev)) - dpx = ENETC_PM_IFM_FULL_DPX_IMX; + if (enetc_is_imx95(dev)) + val = u32_replace_bits(val, + phydev->duplex == DUPLEX_FULL ? 0 : 1, + ENETC_PM_IFM_FULL_DPX_IMX); else if (enetc_is_ls1028a(dev)) - dpx = ENETC_PM_IFM_FULL_DPX_LS; - - if (phydev->duplex == DUPLEX_FULL) - val |= dpx; - else - val &= ~dpx; + val = u32_replace_bits(val, + phydev->duplex == DUPLEX_FULL ? 1 : 0, + ENETC_PM_IFM_FULL_DPX_LS); if (val == old_val) return; diff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c index 8577bb75632..0c87d80ea5c 100644 --- a/drivers/net/fsl_enetc_netc_blk_ctrl.c +++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c @@ -35,6 +35,7 @@ #define MII_PROT_RGMII 0x2 #define MII_PROT_SERIAL 0x3 #define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2)) +#define MII_PROT_GET(reg, port) (((reg) >> ((port) << 2)) & 0xf) #define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4) #define PCS_PROT_1G_SGMII BIT(0) @@ -97,6 +98,9 @@ #define IMX94_TIMER1_ID 1 #define IMX94_TIMER2_ID 2 +#define IMX952_ENETC0_BUS_DEVFN 0x0 +#define IMX952_ENETC1_BUS_DEVFN 0x100 + /* Flags for different platforms */ #define NETC_HAS_NETCMIX BIT(0) @@ -567,6 +571,69 @@ static int netc_prb_check_error(struct netc_blk_ctrl *priv) return 0; } +static int imx952_netcmix_init(struct udevice *dev) +{ + struct netc_blk_ctrl *priv = dev_get_priv(dev); + ofnode child, gchild; + phy_interface_t interface; + int bus_devfn, mii_proto; + u32 val; + + /* Default setting */ + val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII); + + /* Update the link MII protocol through parsing phy-mode */ + dev_for_each_subnode(child, dev) { + if (!ofnode_is_enabled(child)) + continue; + + ofnode_for_each_subnode(gchild, child) { + if (!ofnode_is_enabled(gchild)) + continue; + + if (!ofnode_device_is_compatible(gchild, "pci1131,e101")) + continue; + + bus_devfn = netc_of_pci_get_bus_devfn(gchild); + if (bus_devfn < 0) + return -EINVAL; + + interface = ofnode_read_phy_mode(gchild); + if (interface == -1) + continue; + + mii_proto = netc_get_link_mii_protocol(interface); + if (mii_proto < 0) + return -EINVAL; + + switch (bus_devfn) { + case IMX952_ENETC0_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_0; + val |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto); + break; + case IMX952_ENETC1_BUS_DEVFN: + val &= ~CFG_LINK_MII_PORT_1; + val |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto); + break; + default: + return -EINVAL; + } + } + } + + if (MII_PROT_GET(val, 1) == MII_PROT_SERIAL) { + /* Configure Link I/O variant */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR, + IO_VAR(1, IO_VAR_16FF_16G_SERDES)); + /* Configure Link 2 PCS protocol */ + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(1), + PCS_PROT_2500M_SGMII); + } + netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val); + + return 0; +} + static const struct netc_devinfo imx95_devinfo = { .netcmix_init = imx95_netcmix_init, .ierb_init = imx95_ierb_init, @@ -578,9 +645,14 @@ static const struct netc_devinfo imx94_devinfo = { .xpcs_port_init = imx94_netc_xpcs_port_init, }; +static const struct netc_devinfo imx952_devinfo = { + .netcmix_init = imx952_netcmix_init, +}; + static const struct udevice_id netc_blk_ctrl_match[] = { { .compatible = "nxp,imx95-netc-blk-ctrl", .data = (ulong)&imx95_devinfo }, { .compatible = "nxp,imx94-netc-blk-ctrl", .data = (ulong)&imx94_devinfo }, + { .compatible = "nxp,imx952-netc-blk-ctrl", .data = (ulong)&imx952_devinfo }, {}, }; diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 9bf887035d7..79ad6348de8 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -112,7 +112,7 @@ uint mii_send(uint mii_cmd) ep->eir = FEC_EIR_MII; /* clear MII complete */ #ifdef ET_DEBUG printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); + __FILE__, __LINE__, __func__, mii_cmd, mii_reply); #endif return (mii_reply & 0xffff); /* data read from phy */ diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 107a33aa9f5..4dc738980cb 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -256,8 +256,8 @@ static void set_dram_access(struct mvgbe_registers *regs) win_param.access_ctrl = EWIN_ACCESS_FULL; win_param.high_addr = 0; /* Get bank base and size */ - win_param.base_addr = gd->bd->bi_dram[i].start; - win_param.size = gd->bd->bi_dram[i].size; + win_param.base_addr = gd->dram[i].start; + win_param.size = gd->dram[i].size; if (win_param.size == 0) win_param.enable = 0; else diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index f9e979c4d58..ae5920a0201 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4528,7 +4528,7 @@ static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) */ if (phy_dev && phy_dev->drv->uid == 0xffffffff) {/* Generic phy */ - dev_warn(port->phy_dev->dev, + dev_warn(dev, "Marking phy as invalid, link will not be checked\n"); /* set phy_addr to invalid value */ port->phyaddr = PHY_MAX_ADDR; @@ -4540,7 +4540,7 @@ static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) port->phy_dev = phy_dev; if (!phy_dev) { - dev_err(port->phy_dev->dev, "cannot connect to phy\n"); + dev_err(dev, "cannot connect to phy\n"); return; } phy_dev->supported &= PHY_GBIT_FEATURES; @@ -4731,33 +4731,32 @@ static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) { - int port_node = dev_of_offset(dev); - int phy_node; + ofnode port_node = dev_ofnode(dev); + ofnode phy_node; u32 id; int phyaddr = 0; - int fixed_link = 0; + ofnode fixed_link; int ret; - phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy"); - fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node, "fixed-link"); + phy_node = ofnode_parse_phandle(port_node, "phy", 0); + fixed_link = ofnode_find_subnode(port_node, "fixed-link"); - if (phy_node > 0) { - int parent; + if (ofnode_valid(phy_node)) { + ofnode parent; - if (fixed_link != -FDT_ERR_NOTFOUND) { + if (ofnode_valid(fixed_link)) { /* phy_addr is set to invalid value for fixed links */ phyaddr = PHY_MAX_ADDR; } else { - phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, - "reg", 0); + phyaddr = ofnode_read_s32_default(phy_node, "reg", 0); if (phyaddr < 0) { dev_err(dev, "could not find phy address\n"); return -1; } } - parent = fdt_parent_offset(gd->fdt_blob, phy_node); - ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent, - &port->mdio_dev); + parent = ofnode_get_parent(phy_node); + ret = uclass_get_device_by_ofnode(UCLASS_MDIO, parent, + &port->mdio_dev); if (ret) return ret; } else { @@ -4771,7 +4770,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) return -EINVAL; } - id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1); + id = dev_read_s32_default(dev, "port-id", -1); if (id == -1) { dev_err(dev, "missing port-id value\n"); return -EINVAL; @@ -4812,7 +4811,7 @@ static void mvpp2_gpio_init(struct mvpp2_port *port) /* Ports initialization */ static int mvpp2_port_probe(struct udevice *dev, struct mvpp2_port *port, - int port_node, + ofnode port_node, struct mvpp2 *priv) { int err; @@ -5296,16 +5295,16 @@ static int mvpp2_base_probe(struct udevice *dev) } /* Save base addresses for later use */ - priv->base = devfdt_get_addr_index_ptr(dev, 0); + priv->base = dev_read_addr_index_ptr(dev, 0); if (!priv->base) return -EINVAL; if (priv->hw_version == MVPP21) { - priv->lms_base = devfdt_get_addr_index_ptr(dev, 1); + priv->lms_base = dev_read_addr_index_ptr(dev, 1); if (!priv->lms_base) return -EINVAL; } else { - priv->iface_base = devfdt_get_addr_index_ptr(dev, 1); + priv->iface_base = dev_read_addr_index_ptr(dev, 1); if (!priv->iface_base) return -EINVAL; @@ -5346,13 +5345,11 @@ static int mvpp2_probe(struct udevice *dev) if (priv->hw_version == MVPP21) { int priv_common_regs_num = 2; - port->base = devfdt_get_addr_index_ptr( - dev->parent, priv_common_regs_num + port->id); + port->base = dev_read_addr_index_ptr(dev->parent, priv_common_regs_num + port->id); if (!port->base) return -EINVAL; } else { - port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "gop-port-id", -1); + port->gop_id = ofnode_read_s32_default(dev_ofnode(dev), "gop-port-id", -1); if (port->gop_id == -1) { dev_err(dev, "missing gop-port-id value\n"); return -EINVAL; @@ -5376,7 +5373,7 @@ static int mvpp2_probe(struct udevice *dev) priv->probe_done = 1; } - err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv); + err = mvpp2_port_probe(dev, port, dev_ofnode(dev), priv); if (err) return err; @@ -5437,13 +5434,11 @@ static struct driver mvpp2_driver = { */ static int mvpp2_base_bind(struct udevice *parent) { - const void *blob = gd->fdt_blob; - int node = dev_of_offset(parent); struct uclass_driver *drv; struct udevice *dev; struct eth_pdata *plat; char *name; - int subnode; + ofnode subnode; u32 id; int base_id_add; @@ -5456,19 +5451,19 @@ static int mvpp2_base_bind(struct udevice *parent) base_id_add = base_id; - fdt_for_each_subnode(subnode, blob, node) { + dev_for_each_subnode(subnode, parent) { /* Increment base_id for all subnodes, also the disabled ones */ base_id++; /* Skip disabled ports */ - if (!fdtdec_get_is_enabled(blob, subnode)) + if (!ofnode_is_enabled(subnode)) continue; plat = calloc(1, sizeof(*plat)); if (!plat) return -ENOMEM; - id = fdtdec_get_int(blob, subnode, "port-id", -1); + id = ofnode_read_s32_default(subnode, "port-id", -1); id += base_id_add; name = calloc(1, 16); @@ -5479,8 +5474,7 @@ static int mvpp2_base_bind(struct udevice *parent) sprintf(name, "mvpp2-%d", id); /* Create child device UCLASS_ETH and bind it */ - device_bind(parent, &mvpp2_driver, name, plat, - offset_to_ofnode(subnode), &dev); + device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev); } return 0; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 0025c895f12..3f7953d693c 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -81,7 +81,7 @@ config PHYLIB_10G config PHY_ADIN bool "Analog Devices Industrial Ethernet PHYs" help - Add support for configuring RGMII on Analog Devices ADIN PHYs. + Add support for configuring RGMII on Analog Devices ADIN PHYs. menuconfig PHY_AQUANTIA bool "Aquantia Ethernet PHYs support" @@ -126,9 +126,9 @@ config SYS_CORTINA_NO_FW_UPLOAD bool "Cortina firmware loading support" depends on PHY_CORTINA help - Cortina phy has provision to store phy firmware in attached dedicated - EEPROM. And boards designed with such EEPROM does not require firmware - upload. + Cortina phy has provision to store phy firmware in attached dedicated + EEPROM. And boards designed with such EEPROM does not require firmware + upload. choice prompt "Location of the Cortina firmware" @@ -167,7 +167,7 @@ config PHY_CORTINA_ACCESS default y depends on CORTINA_NI_ENET help - Cortina Access Ethernet PHYs init process + Cortina Access Ethernet PHYs init process config PHY_DAVICOM bool "Davicom Ethernet PHYs support" @@ -317,13 +317,13 @@ config PHY_TERANETICS config PHY_TI bool "Texas Instruments Ethernet PHYs support" - ---help--- + help Adds PHY registration support for TI PHYs. config PHY_TI_DP83867 select PHY_TI bool "Texas Instruments Ethernet DP83867 PHY support" - ---help--- + help Adds support for the TI DP83867 1Gbit PHY. config SPL_PHY_TI_DP83867 @@ -333,13 +333,13 @@ config SPL_PHY_TI_DP83867 config PHY_TI_DP83869 select PHY_TI bool "Texas Instruments Ethernet DP83869 PHY support" - ---help--- + help Adds support for the TI DP83869 1Gbit PHY. config PHY_TI_GENERIC select PHY_TI bool "Texas Instruments Generic Ethernet PHYs support" - ---help--- + help Adds support for Generic TI PHYs that don't need special handling but the PHY name is associated with a PHY ID. diff --git a/drivers/net/phy/airoha/Kconfig b/drivers/net/phy/airoha/Kconfig index 4139df343ad..2d58d674200 100644 --- a/drivers/net/phy/airoha/Kconfig +++ b/drivers/net/phy/airoha/Kconfig @@ -2,12 +2,25 @@ menuconfig PHY_AIROHA bool "Airoha Ethernet PHYs support" +config PHY_AIROHA_AN8801 + bool "Airoha Ethernet AN8801 support" + depends on PHY_AIROHA + select PHY_AIROHA_PHYLIB + help + Currently support AIROHA AN8801 1G PHY. + config PHY_AIROHA_EN8811 bool "Airoha Ethernet EN8811H support" depends on PHY_AIROHA depends on SUPPORTS_FW_LOADER select FW_LOADER + select PHY_AIROHA_PHYLIB select PHY_COMMON_PROPS help AIROHA EN8811H supported. AIROHA AN8811HB supported. + +config PHY_AIROHA_PHYLIB + bool + help + Airoha Ethernet PHY common library diff --git a/drivers/net/phy/airoha/Makefile b/drivers/net/phy/airoha/Makefile index 84d23b19ab0..25e44004cfd 100644 --- a/drivers/net/phy/airoha/Makefile +++ b/drivers/net/phy/airoha/Makefile @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_AIROHA_AN8801) += air_an8801.o obj-$(CONFIG_PHY_AIROHA_EN8811) += air_en8811.o +obj-$(CONFIG_PHY_AIROHA_PHYLIB) += air_phy_lib.o diff --git a/drivers/net/phy/airoha/air_an8801.c b/drivers/net/phy/airoha/air_an8801.c new file mode 100644 index 00000000000..9d9958fc665 --- /dev/null +++ b/drivers/net/phy/airoha/air_an8801.c @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * air_an8801.c - PHY driver for Airoha AN8801. + * Copyright (c) 2026 Airoha Technology Corp. + * Copyright (C) 2026 BayLibre, SAS. + * Author: Kevin-KW Huang <[email protected]> + * Sita Huang <[email protected]> + * Julien Stephan <[email protected]> + */ + +#include <malloc.h> +#include <phy.h> +#include <dm/device_compat.h> + +#include "air_phy_lib.h" + +#define AN8801R_PHY_ID1 0xc0ff +#define AN8801R_PHY_ID2 0x0421 +#define AN8801R_PHY_ID ((u32)((AN8801R_PHY_ID1 << 16) | AN8801R_PHY_ID2)) + +#define AN8801R_MAX_LED_SIZE 3 + +/* MII Registers - Airoha Page 4 */ +#define AN8801_PBUS_ACCESS BIT(28) + +/* BPBUS Registers */ +#define AN8801_BPBUS_REG_LED_GPIO 0x54 +#define AN8801_BPBUS_REG_LED_ID_SEL 0x58 +#define LED_ID_GPIO_SEL(led, gpio) ((led) << ((gpio) * 3)) + +#define AN8801_BPBUS_REG_GPIO_MODE 0x70 + +#define AN8801_BPBUS_REG_LINK_MODE 0x5054 +#define AN8801_BPBUS_LINK_MODE_1000 BIT(0) + +#define AN8801_BPBUS_REG_BYPASS_PTP 0x21c004 +#define AN8801_BYP_PTP_RGMII_TO_GPHY BIT(0) + +#define AN8801_BPBUS_REG_TXDLY_STEP 0x21c024 +#define RGMII_DELAY_STEP_MASK GENMASK(2, 0) +#define AIR_RGMII_DELAY_NOSTEP 0 +#define AIR_RGMII_DELAY_STEP_1 1 +#define AIR_RGMII_DELAY_STEP_2 2 +#define AIR_RGMII_DELAY_STEP_3 3 +#define AIR_RGMII_DELAY_STEP_4 4 +#define AIR_RGMII_DELAY_STEP_5 5 +#define AIR_RGMII_DELAY_STEP_6 6 +#define AIR_RGMII_DELAY_STEP_7 7 +#define RGMII_TXDELAY_FORCE_MODE BIT(24) + +#define AN8801_BPBUS_REG_RXDLY_STEP 0x21c02c +#define RGMII_RXDELAY_ALIGN BIT(4) +#define RGMII_RXDELAY_FORCE_MODE BIT(24) + +#define AN8801_BPBUS_REG_EFIFO_CTL(x) (0x270004 + (0x100 * (x))) /* 0..2 */ +#define AN8801_EFIFO_ALL_EN GENMASK(7, 0) +#define AN8801_EFIFO_RX_EN BIT(0) +#define AN8801_EFIFO_TX_EN BIT(1) +#define AN8801_EFIFO_RX_CLK_EN BIT(2) +#define AN8801_EFIFO_TX_CLK_EN BIT(3) +#define AN8801_EFIFO_RX_EEE_EN BIT(4) +#define AN8801_EFIFO_TX_EEE_EN BIT(5) +#define AN8801_EFIFO_RX_ODD_NIBBLE_EN BIT(6) +#define AN8801_EFIFO_TX_ODD_NIBBLE_EN BIT(7) + +#define AN8801_BPBUS_REG_HWRST_DE_GLITCH 0xc8 +#define AN8801_DE_GLITCH_EN BIT(2) +#define AN8801_11_CYCLE_XTAL_PERIOD_DE_GLITCH GENMASK(1, 0) + +#define LED_BCR 0x21 +#define LED_BCR_MODE_MASK GENMASK(1, 0) +#define LED_BCR_TIME_TEST BIT(2) +#define LED_BCR_CLK_EN BIT(3) +#define LED_BCR_EVT_ALL BIT(4) +#define LED_BCR_EXT_CTRL BIT(15) +#define LED_BCR_MODE_DISABLE 0 +#define LED_BCR_MODE_2LED 1 +#define LED_BCR_MODE_3LED_1 2 +#define LED_BCR_MODE_3LED_2 3 + +#define LED_ON_DUR 0x22 +#define LED_ON_DUR_MASK GENMASK(15, 0) + +#define LED_BLINK_DUR 0x23 +#define LED_BLINK_DUR_MASK GENMASK(15, 0) + +#define LED_ON_CTRL(i) (0x024 + ((i) * 2)) +#define LED_ON_EVT_MASK GENMASK(6, 0) +#define LED_ON_EVT_LINK_1000M BIT(0) +#define LED_ON_EVT_LINK_100M BIT(1) +#define LED_ON_EVT_LINK_10M BIT(2) +#define LED_ON_EVT_LINK_DN BIT(3) +#define LED_ON_EVT_FDX BIT(4) +#define LED_ON_EVT_HDX BIT(5) +#define LED_ON_EVT_FORCE BIT(6) +#define LED_ON_POL BIT(14) +#define LED_ON_EN BIT(15) + +#define LED_BLINK_CTRL(i) (0x025 + ((i) * 2)) +#define LED_BLINK_EVT_MASK GENMASK(9, 0) +#define LED_BLINK_EVT_1000M_TX BIT(0) +#define LED_BLINK_EVT_1000M_RX BIT(1) +#define LED_BLINK_EVT_100M_TX BIT(2) +#define LED_BLINK_EVT_100M_RX BIT(3) +#define LED_BLINK_EVT_10M_TX BIT(4) +#define LED_BLINK_EVT_10M_RX BIT(5) +#define LED_BLINK_EVT_FORCE BIT(9) + +#define UNIT_LED_BLINK_DURATION 780 +#define LED_BLINK_DURATION(f) (UNIT_LED_BLINK_DURATION << (f)) + +/* Link on(1G/100M/10M), no activity */ +#define AIR_LED0_ON \ + (LED_ON_EVT_LINK_1000M | LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M) +#define AIR_LED0_BLINK 0x0 +/* No link on, activity(1G/100M/10M TX/RX) */ +#define AIR_LED1_ON 0x0 +#define AIR_LED1_BLINK \ + (LED_BLINK_EVT_1000M_TX | LED_BLINK_EVT_1000M_RX | \ + LED_BLINK_EVT_100M_TX | LED_BLINK_EVT_100M_RX | \ + LED_BLINK_EVT_10M_TX | LED_BLINK_EVT_10M_RX) +/* Link on(100M/10M), activity(100M/10M TX/RX) */ +#define AIR_LED2_ON \ + (LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M) +#define AIR_LED2_BLINK \ + (LED_BLINK_EVT_100M_TX | LED_BLINK_EVT_100M_RX | \ + LED_BLINK_EVT_10M_TX | LED_BLINK_EVT_10M_RX) + +#define INVALID_DATA GENMASK(31, 0) + +#define AN8801_REG_PHY_INTERNAL0 0x600 +#define AN8801_REG_PHY_INTERNAL1 0x601 + +#define AN8801_LED_ENABLE 1 + +enum air_led_gpio_pin { + AIR_LED_GPIO1 = 1, + AIR_LED_GPIO2, + AIR_LED_GPIO3 +}; + +enum air_led { + AIR_LED0 = 0, + AIR_LED1, + AIR_LED2, + AIR_LED3 +}; + +enum air_led_blink_dut { + AIR_LED_BLINK_DUR_32M = 0, + AIR_LED_BLINK_DUR_64M, + AIR_LED_BLINK_DUR_128M, + AIR_LED_BLINK_DUR_256M, + AIR_LED_BLINK_DUR_512M, + AIR_LED_BLINK_DUR_1024M, + AIR_LED_BLINK_DUR_LAST +}; + +enum air_led_polarity { + AIR_ACTIVE_LOW = 0, + AIR_ACTIVE_HIGH, +}; + +enum air_led_mode { + AIR_LED_MODE_DISABLE = 0, + AIR_LED_MODE_USER_DEFINE, + AIR_LED_MODE_LAST +}; + +struct air_led_cfg { + u16 led_en; + u16 gpio; + u16 led_polarity; + u16 led_on_cfg; + u16 led_blk_cfg; +}; + +struct an8801r_priv { + struct air_led_cfg led_cfg[AN8801R_MAX_LED_SIZE]; + u32 led_blink_cfg; + u8 rxdelay_force; + u8 txdelay_force; + u16 rxdelay_step; + u8 rxdelay_align; + u16 txdelay_step; +}; + +#define phydev_cfg(phy) ((struct an8801r_priv *)(phy)->priv) + +/* + * GPIO1 <-> LED0, + * GPIO2 <-> LED1, + * GPIO3 <-> LED2, + */ +static const struct an8801r_priv an8801r_priv_defaults = { + .led_cfg = { + /* LED Enable, GPIO, LED Polarity, LED ON, LED Blink */ + {AN8801_LED_ENABLE, AIR_LED_GPIO1, AIR_ACTIVE_LOW, AIR_LED0_ON, AIR_LED0_BLINK}, + {AN8801_LED_ENABLE, AIR_LED_GPIO2, AIR_ACTIVE_HIGH, AIR_LED1_ON, AIR_LED1_BLINK}, + {AN8801_LED_ENABLE, AIR_LED_GPIO3, AIR_ACTIVE_HIGH, AIR_LED2_ON, AIR_LED2_BLINK}, + }, + .led_blink_cfg = AIR_LED_BLINK_DUR_64M, + .rxdelay_force = false, + .txdelay_force = false, + .rxdelay_step = AIR_RGMII_DELAY_NOSTEP, + .rxdelay_align = false, + .txdelay_step = AIR_RGMII_DELAY_NOSTEP, +}; + +static int an8801_buckpbus_reg_rmw(struct phy_device *phydev, + u32 addr, u32 mask, u32 set) +{ + return air_phy_buckpbus_reg_modify(phydev, + addr | AN8801_PBUS_ACCESS, + mask, set); +} + +static int an8801_buckpbus_reg_set_bits(struct phy_device *phydev, + u32 addr, u32 mask) +{ + return air_phy_buckpbus_reg_modify(phydev, + addr | AN8801_PBUS_ACCESS, + mask, mask); +} + +static int an8801_buckpbus_reg_clear_bits(struct phy_device *phydev, + u32 addr, u32 mask) +{ + return air_phy_buckpbus_reg_modify(phydev, + addr | AN8801_PBUS_ACCESS, + mask, 0); +} + +static int an8801_buckpbus_reg_write(struct phy_device *phydev, u32 addr, u32 data) +{ + return air_phy_buckpbus_reg_write(phydev, addr | AN8801_PBUS_ACCESS, data); +} + +static int an8801r_led_set_usr_def(struct phy_device *phydev, u8 entity, + u16 polar, u16 on_evt, u16 blk_evt) +{ + int ret; + + if (polar == AIR_ACTIVE_HIGH) + on_evt |= LED_ON_POL; + else + on_evt &= ~LED_ON_POL; + + on_evt |= LED_ON_EN; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(entity), on_evt); + if (ret) + return ret; + + return phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(entity), blk_evt); +} + +static int an8801r_led_set_blink(struct phy_device *phydev, u16 blink) +{ + int ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_DUR, + LED_BLINK_DURATION(blink)); + if (ret) + return ret; + + return phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_DUR, + LED_BLINK_DURATION(blink) / 2); +} + +static int an8801r_led_set_mode(struct phy_device *phydev, u8 mode) +{ + int ret; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_BCR); + if (ret < 0) + return ret; + + switch (mode) { + case AIR_LED_MODE_DISABLE: + ret &= ~LED_BCR_EXT_CTRL; + ret &= ~LED_BCR_MODE_MASK; + ret |= LED_BCR_MODE_DISABLE; + break; + case AIR_LED_MODE_USER_DEFINE: + ret |= LED_BCR_EXT_CTRL | LED_BCR_CLK_EN; + break; + } + return phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BCR, ret); +} + +static int an8801r_led_set_state(struct phy_device *phydev, u8 entity, u8 state) +{ + int ret; + + ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(entity)); + if (ret < 0) + return ret; + + if (state) + ret |= LED_ON_EN; + else + ret &= ~LED_ON_EN; + + return phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(entity), ret); +} + +static int an8801r_led_init(struct phy_device *phydev) +{ + struct an8801r_priv *priv = phydev_cfg(phydev); + struct air_led_cfg *led_cfg = priv->led_cfg; + u16 led_blink_cfg = priv->led_blink_cfg; + int ret, led_id; + + ret = an8801r_led_set_blink(phydev, led_blink_cfg); + if (ret) + return ret; + + ret = an8801r_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE); + if (ret) { + dev_err(phydev->dev, "AN8801R: Fail to set LED mode, ret %d!\n", ret); + return ret; + } + + for (led_id = AIR_LED0; led_id < AN8801R_MAX_LED_SIZE; led_id++) { + ret = an8801r_led_set_state(phydev, led_id, led_cfg[led_id].led_en); + if (ret) { + dev_err(phydev->dev, "AN8801R: Fail to set LED%d state, ret %d!\n", + led_id, ret); + return ret; + } + + if (!led_cfg[led_id].led_en) + continue; + + ret = an8801_buckpbus_reg_set_bits(phydev, AN8801_BPBUS_REG_LED_GPIO, + BIT(led_cfg[led_id].gpio)); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_set_bits(phydev, AN8801_BPBUS_REG_LED_ID_SEL, + LED_ID_GPIO_SEL(led_id, + led_cfg[led_id].gpio)); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_clear_bits(phydev, AN8801_BPBUS_REG_GPIO_MODE, + BIT(led_cfg[led_id].gpio)); + if (ret) + return ret; + + ret = an8801r_led_set_usr_def(phydev, led_id, + led_cfg[led_id].led_polarity, + led_cfg[led_id].led_on_cfg, + led_cfg[led_id].led_blk_cfg); + if (ret) { + dev_err(phydev->dev, "AN8801R: Fail to set LED%d, ret %d!\n", + led_id, ret); + return ret; + } + } + return 0; +} + +static int an8801r_of_init(struct phy_device *phydev) +{ + struct an8801r_priv *priv = phydev_cfg(phydev); + ofnode node = phy_get_ofnode(phydev); + u32 val = 0; + int ret; + + if (!ofnode_valid(node)) + return -EINVAL; + + if (ofnode_has_property(node, "airoha,rxclk-delay")) { + ret = ofnode_read_u32(node, "airoha,rxclk-delay", &val); + if (ret) { + dev_err(phydev->dev, "airoha,rxclk-delay value is invalid.\n"); + return ret; + } + if (val > AIR_RGMII_DELAY_STEP_7) { + dev_err(phydev->dev, "airoha,rxclk-delay value %u out of range.\n", val); + return -EINVAL; + } + priv->rxdelay_force = true; + priv->rxdelay_step = val; + priv->rxdelay_align = ofnode_read_bool(node, + "airoha,rxclk-delay-align"); + } + + if (ofnode_has_property(node, "airoha,txclk-delay")) { + ret = ofnode_read_u32(node, "airoha,txclk-delay", &val); + if (ret) { + dev_err(phydev->dev, "airoha,txclk-delay value is invalid.\n"); + return ret; + } + if (val > AIR_RGMII_DELAY_STEP_7) { + dev_err(phydev->dev, "airoha,txclk-delay value %u out of range.\n", val); + return -EINVAL; + } + priv->txdelay_force = true; + priv->txdelay_step = val; + } + return 0; +} + +static int an8801r_rgmii_rxdelay(struct phy_device *phydev, u16 delay, u8 align) +{ + u32 reg_val = delay & RGMII_DELAY_STEP_MASK; + int ret; + + if (align) { + reg_val |= RGMII_RXDELAY_ALIGN; + debug("AN8801R: Rxdelay align\n"); + } + reg_val |= RGMII_RXDELAY_FORCE_MODE; + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_RXDLY_STEP, reg_val); + if (ret) + return ret; + + debug("AN8801R: Force rxdelay = %d(0x%x)\n", delay, reg_val); + return 0; +} + +static int an8801r_rgmii_txdelay(struct phy_device *phydev, u16 delay) +{ + u32 reg_val = delay & RGMII_DELAY_STEP_MASK; + int ret; + + reg_val |= RGMII_TXDELAY_FORCE_MODE; + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_TXDLY_STEP, reg_val); + if (ret) + return ret; + + debug("AN8801R: Force txdelay = %d(0x%x)\n", delay, reg_val); + return 0; +} + +static int an8801r_rgmii_delay_config(struct phy_device *phydev) +{ + struct an8801r_priv *priv = phydev_cfg(phydev); + int ret; + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII_TXID: + return an8801r_rgmii_txdelay(phydev, AIR_RGMII_DELAY_STEP_4); + case PHY_INTERFACE_MODE_RGMII_RXID: + return an8801r_rgmii_rxdelay(phydev, AIR_RGMII_DELAY_NOSTEP, true); + case PHY_INTERFACE_MODE_RGMII_ID: + ret = an8801r_rgmii_txdelay(phydev, AIR_RGMII_DELAY_STEP_4); + if (ret) + return ret; + return an8801r_rgmii_rxdelay(phydev, AIR_RGMII_DELAY_NOSTEP, true); + case PHY_INTERFACE_MODE_RGMII: + default: + if (priv->rxdelay_force) { + ret = an8801r_rgmii_rxdelay(phydev, priv->rxdelay_step, + priv->rxdelay_align); + if (ret) + return ret; + } + if (priv->txdelay_force) + return an8801r_rgmii_txdelay(phydev, priv->txdelay_step); + return 0; + } +} + +static int an8801r_config_init(struct phy_device *phydev) +{ + int ret; + + ret = an8801r_of_init(phydev); + if (ret < 0) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_HWRST_DE_GLITCH, + AN8801_DE_GLITCH_EN | + AN8801_11_CYCLE_XTAL_PERIOD_DE_GLITCH); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0, 0x1e); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1, 0x02); + if (ret) + return ret; + + ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_BYPASS_PTP, + AN8801_BYP_PTP_RGMII_TO_GPHY); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(0), + AN8801_EFIFO_RX_EN | + AN8801_EFIFO_TX_EN | + AN8801_EFIFO_RX_CLK_EN | + AN8801_EFIFO_TX_CLK_EN | + AN8801_EFIFO_RX_EEE_EN | + AN8801_EFIFO_TX_EEE_EN); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(1), + AN8801_EFIFO_ALL_EN); + if (ret) + return ret; + + ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(2), + AN8801_EFIFO_ALL_EN); + if (ret) + return ret; + + ret = an8801r_rgmii_delay_config(phydev); + if (ret) + return ret; + + ret = an8801r_led_init(phydev); + if (ret) { + dev_err(phydev->dev, "AN8801R: LED initialize fail, ret %d!\n", ret); + return ret; + } + return 0; +} + +static int an8801r_phy_probe(struct phy_device *phydev) +{ + struct an8801r_priv *priv; + u32 phy_id; + int ret; + + ret = get_phy_id(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, &phy_id); + if (ret) + return ret; + + if (phy_id != AN8801R_PHY_ID) { + dev_err(phydev->dev, + "AN8801R can't be detected (id=0x%08x).\n", phy_id); + return -ENODEV; + } + + priv = malloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + + *priv = an8801r_priv_defaults; + + phydev->priv = priv; + + return 0; +} + +static int an8801r_read_status(struct phy_device *phydev) +{ + u32 data; + + if (!phydev->link) + return 0; + + debug("AN8801R: SPEED %d\n", phydev->speed); + data = phydev->speed == SPEED_1000 ? AN8801_BPBUS_LINK_MODE_1000 : 0; + + return an8801_buckpbus_reg_rmw(phydev, AN8801_BPBUS_REG_LINK_MODE, + AN8801_BPBUS_LINK_MODE_1000, data); +} + +static int an8801r_startup(struct phy_device *phydev) +{ + int ret; + + ret = genphy_startup(phydev); + if (ret) + return ret; + + return an8801r_read_status(phydev); +} + +U_BOOT_PHY_DRIVER(an8801r) = { + .name = "Airoha AN8801R", + .uid = AN8801R_PHY_ID, + .mask = 0x0ffffff0, + .features = PHY_GBIT_FEATURES, + .probe = &an8801r_phy_probe, + .config = &an8801r_config_init, + .read_page = &air_phy_read_page, + .write_page = &air_phy_write_page, + .startup = &an8801r_startup, + .shutdown = &genphy_shutdown, +}; diff --git a/drivers/net/phy/airoha/air_en8811.c b/drivers/net/phy/airoha/air_en8811.c index 32f06dd6dfa..7a07be2e956 100644 --- a/drivers/net/phy/airoha/air_en8811.c +++ b/drivers/net/phy/airoha/air_en8811.c @@ -25,6 +25,8 @@ #include <u-boot/crc.h> #include <linux/phy/phy-common-props.h> +#include "air_phy_lib.h" + /* MII Registers */ #define AIR_AUX_CTRL_STATUS 0x1d #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) @@ -33,10 +35,6 @@ #define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc -#define AIR_EXT_PAGE_ACCESS 0x1f -#define AIR_PHY_PAGE_STANDARD 0x0000 -#define AIR_PHY_PAGE_EXTENDED_4 0x0004 - #define AIR_PBUS_MODE_ADDR_HIGH 0x1c /* MII Registers Page 4 */ #define AIR_BPBUS_MODE 0x10 @@ -310,166 +308,6 @@ static int air_pbus_reg_write(struct phy_device *phydev, return ret; } -static int air_buckpbus_reg_write(struct phy_device *phydev, - u32 pbus_address, u32 pbus_data) -{ - int ret, saved_page; - - saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); - if (saved_page < 0) - return saved_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, - AIR_BPBUS_MODE_ADDR_FIXED); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_HIGH, - upper_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_LOW, - lower_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_HIGH, - upper_16_bits(pbus_data)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_LOW, - lower_16_bits(pbus_data)); - if (ret < 0) - goto restore_page; - -restore_page: - if (ret < 0) - dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, - pbus_address, ret); - - return phy_restore_page(phydev, saved_page, ret); -} - -static int air_buckpbus_reg_read(struct phy_device *phydev, - u32 pbus_address, u32 *pbus_data) -{ - int pbus_data_low, pbus_data_high; - int ret = 0, saved_page; - - saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); - if (saved_page < 0) - return saved_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, - AIR_BPBUS_MODE_ADDR_FIXED); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_HIGH, - upper_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_LOW, - lower_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_DATA_HIGH); - if (pbus_data_high < 0) { - ret = pbus_data_high; - goto restore_page; - } - - pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_DATA_LOW); - if (pbus_data_low < 0) { - ret = pbus_data_low; - goto restore_page; - } - - *pbus_data = pbus_data_low | (pbus_data_high << 16); - -restore_page: - if (ret < 0) - dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, - pbus_address, ret); - - return phy_restore_page(phydev, saved_page, ret); -} - -static int air_buckpbus_reg_modify(struct phy_device *phydev, - u32 pbus_address, u32 mask, u32 set) -{ - int pbus_data_low, pbus_data_high; - u32 pbus_data_old, pbus_data_new; - int ret = 0, saved_page; - - saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); - if (saved_page < 0) - return saved_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, - AIR_BPBUS_MODE_ADDR_FIXED); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_HIGH, - upper_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_LOW, - lower_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_DATA_HIGH); - if (pbus_data_high < 0) { - ret = pbus_data_high; - goto restore_page; - } - - pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_DATA_LOW); - if (pbus_data_low < 0) { - ret = pbus_data_low; - goto restore_page; - } - - pbus_data_old = pbus_data_low | (pbus_data_high << 16); - pbus_data_new = (pbus_data_old & ~mask) | set; - if (pbus_data_new == pbus_data_old) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_HIGH, - upper_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_LOW, - lower_16_bits(pbus_address)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_HIGH, - upper_16_bits(pbus_data_new)); - if (ret < 0) - goto restore_page; - - ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_LOW, - lower_16_bits(pbus_data_new)); - if (ret < 0) - goto restore_page; - -restore_page: - if (ret < 0) - dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, - pbus_address, ret); - - return phy_restore_page(phydev, saved_page, ret); -} - static int air_write_buf(struct phy_device *phydev, unsigned long address, unsigned long array_size, const unsigned char *buffer) { @@ -540,12 +378,12 @@ static int an8811hb_check_crc(struct phy_device *phydev, u32 pbus_value; /* Configure CRC */ - ret = air_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, - AN8811HB_CRC_RD_EN); + ret = air_phy_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, + AN8811HB_CRC_RD_EN); if (ret < 0) return ret; - ret = air_buckpbus_reg_read(phydev, set1, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, set1, &pbus_value); if (ret < 0) return ret; @@ -554,14 +392,14 @@ static int an8811hb_check_crc(struct phy_device *phydev, do { mdelay(300); - ret = air_buckpbus_reg_read(phydev, mon2, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value); if (ret < 0) return ret; debug("%d: reg 0x%x val 0x%x!\n", __LINE__, mon2, pbus_value); if (pbus_value & AN8811HB_CRC_ST) { - ret = air_buckpbus_reg_read(phydev, mon3, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value); if (ret < 0) return ret; @@ -585,11 +423,11 @@ static int an8811hb_check_crc(struct phy_device *phydev, } } while (--retry); - ret = air_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, 0); + ret = air_phy_buckpbus_reg_modify(phydev, set1, AN8811HB_CRC_RD_EN, 0); if (ret < 0) return ret; - ret = air_buckpbus_reg_read(phydev, set1, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, set1, &pbus_value); if (ret < 0) return ret; @@ -647,9 +485,9 @@ static int an8811hb_surge_protect_cfg(struct phy_device *phydev) return ret; } - ret = air_buckpbus_reg_modify(phydev, AIR_PHY_CONTROL, - AIR_PHY_CONTROL_SURGE_5R, - AIR_PHY_CONTROL_SURGE_5R); + ret = air_phy_buckpbus_reg_modify(phydev, AIR_PHY_CONTROL, + AIR_PHY_CONTROL_SURGE_5R, + AIR_PHY_CONTROL_SURGE_5R); if (ret < 0) return ret; @@ -707,14 +545,14 @@ static int en8811h_load_firmware(struct phy_device *phydev) goto en8811h_load_firmware_out; } - ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_START); + ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_START); if (ret < 0) goto en8811h_load_firmware_out; - ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, - EN8811H_FW_CTRL_2_LOADING, - EN8811H_FW_CTRL_2_LOADING); + ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, + EN8811H_FW_CTRL_2_LOADING, + EN8811H_FW_CTRL_2_LOADING); if (ret < 0) goto en8811h_load_firmware_out; @@ -728,13 +566,13 @@ static int en8811h_load_firmware(struct phy_device *phydev) if (ret < 0) goto en8811h_load_firmware_out; - ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, - EN8811H_FW_CTRL_2_LOADING, 0); + ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, + EN8811H_FW_CTRL_2_LOADING, 0); if (ret < 0) goto en8811h_load_firmware_out; - ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_FINISH); + ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_FINISH); if (ret < 0) goto en8811h_load_firmware_out; @@ -742,8 +580,8 @@ static int en8811h_load_firmware(struct phy_device *phydev) if (ret < 0) goto en8811h_load_firmware_out; - air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, - &priv->firmware_version); + air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, + &priv->firmware_version); dev_info(phydev->dev, "MD32 firmware version: %08x\n", priv->firmware_version); @@ -779,8 +617,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev) if (ret < 0) goto an8811hb_load_firmware_out; - ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, - AIR_PHY_FW_CTRL_1_START); + ret = air_phy_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_START); if (ret < 0) goto an8811hb_load_firmware_out; @@ -804,8 +642,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev) if (ret < 0) goto an8811hb_load_firmware_out; - ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, - AIR_PHY_FW_CTRL_1_FINISH); + ret = air_phy_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_FINISH); if (ret < 0) goto an8811hb_load_firmware_out; @@ -818,7 +656,7 @@ static int an8811hb_load_firmware(struct phy_device *phydev) do { mdelay(300); - ret = air_buckpbus_reg_read(phydev, AIR_PHY_FW_CTRL_1, ®_val); + ret = air_phy_buckpbus_reg_read(phydev, AIR_PHY_FW_CTRL_1, ®_val); if (ret < 0) goto an8811hb_load_firmware_out; @@ -828,8 +666,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev) debug("%d: reg 0x%x val 0x%x!\n", __LINE__, AIR_PHY_FW_CTRL_1, reg_val); - ret = air_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, - AIR_PHY_FW_CTRL_1_FINISH); + ret = air_phy_buckpbus_reg_write(phydev, AIR_PHY_FW_CTRL_1, + AIR_PHY_FW_CTRL_1_FINISH); if (ret < 0) goto an8811hb_load_firmware_out; @@ -839,8 +677,8 @@ static int an8811hb_load_firmware(struct phy_device *phydev) if (ret < 0) goto an8811hb_load_firmware_out; - air_buckpbus_reg_read(phydev, AIR_PHY_MD32FW_VERSION, - &priv->firmware_version); + air_phy_buckpbus_reg_read(phydev, AIR_PHY_MD32FW_VERSION, + &priv->firmware_version); debug("MD32 firmware version: %08x\n", priv->firmware_version); @@ -859,17 +697,17 @@ int an8811hb_cko_cfg(struct phy_device *phydev) int ret = 0; if (!ofnode_read_bool(node, "airoha,phy-output-clock")) { - ret = air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, - AN8811HB_CLK_DRV_CKO_MASK, - AN8811HB_CLK_DRV_CKOPWD | - AN8811HB_CLK_DRV_CKO_LDPWD | - AN8811HB_CLK_DRV_CKO_LPPWD); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, + AN8811HB_CLK_DRV_CKO_MASK, + AN8811HB_CLK_DRV_CKOPWD | + AN8811HB_CLK_DRV_CKO_LDPWD | + AN8811HB_CLK_DRV_CKO_LPPWD); if (ret < 0) return ret; debug("CKO Output mode - Disabled\n"); } else { - ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); if (ret < 0) return ret; @@ -888,13 +726,13 @@ static int en8811h_restart_mcu(struct phy_device *phydev) if (ret < 0) return ret; - ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_START); + ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_START); if (ret < 0) return ret; - return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_FINISH); + return air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_FINISH); } static int air_led_hw_control_set(struct phy_device *phydev, u8 index, @@ -1083,9 +921,10 @@ static int en8811h_config_serdes_polarity(struct phy_device *phydev) if (pol == PHY_POL_NORMAL) pbus_value |= EN8811H_POLARITY_TX_NORMAL; - return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY, - EN8811H_POLARITY_RX_REVERSE | - EN8811H_POLARITY_TX_NORMAL, pbus_value); + return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY, + EN8811H_POLARITY_RX_REVERSE | + EN8811H_POLARITY_TX_NORMAL, + pbus_value); } static int en8811h_config(struct phy_device *phydev) @@ -1170,12 +1009,12 @@ static int an8811hb_config(struct phy_device *phydev) priv->mcu_needs_restart = true; } - ret = air_buckpbus_reg_read(phydev, AN8811HB_PRO_ID, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_PRO_ID, &pbus_value); if (ret < 0) return ret; priv->pro_id = (pbus_value & AN8811HB_PRO_ID_VERSION) + 1; - ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); + ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); if (ret < 0) return ret; priv->pkg_sel = (pbus_value & AN8811HB_HWTRAP2_PKG) >> 12; @@ -1191,8 +1030,8 @@ static int an8811hb_config(struct phy_device *phydev) pbus_value |= AN8811HB_RX_POLARITY_NORMAL; debug("1 pbus_value 0x%x\n", pbus_value); - ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY, - AN8811HB_RX_POLARITY_NORMAL, pbus_value); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY, + AN8811HB_RX_POLARITY_NORMAL, pbus_value); if (ret < 0) return ret; @@ -1203,35 +1042,35 @@ static int an8811hb_config(struct phy_device *phydev) pbus_value |= AN8811HB_TX_POLARITY_NORMAL; debug("2 pbus_value 0x%x\n", pbus_value); - ret = air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY, - AN8811HB_TX_POLARITY_NORMAL, pbus_value); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY, + AN8811HB_TX_POLARITY_NORMAL, pbus_value); if (ret < 0) return ret; /* Configure led gpio pins as output */ if (priv->pkg_sel) { - ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, - AN8811HB_GPIO_OUTPUT_MASK, - AN8811HB_GPIO_OUTPUT_0115); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, + AN8811HB_GPIO_OUTPUT_MASK, + AN8811HB_GPIO_OUTPUT_0115); if (ret < 0) return ret; - ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_1, - AN8811HB_GPIO_SEL_1_0_MASK | - AN8811HB_GPIO_SEL_1_1_MASK, - AN8811HB_GPIO_SEL_1_0 | - AN8811HB_GPIO_SEL_1_1); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_1, + AN8811HB_GPIO_SEL_1_0_MASK | + AN8811HB_GPIO_SEL_1_1_MASK, + AN8811HB_GPIO_SEL_1_0 | + AN8811HB_GPIO_SEL_1_1); if (ret < 0) return ret; - ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_2, - AN8811HB_GPIO_SEL_2_15_MASK, - AN8811HB_GPIO_SEL_2_15); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_SEL_2, + AN8811HB_GPIO_SEL_2_15_MASK, + AN8811HB_GPIO_SEL_2_15); if (ret < 0) return ret; } else { - ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, - AN8811HB_GPIO_OUTPUT_345, - AN8811HB_GPIO_OUTPUT_345); + ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, + AN8811HB_GPIO_OUTPUT_345, + AN8811HB_GPIO_OUTPUT_345); if (ret < 0) return ret; } @@ -1401,16 +1240,6 @@ static int en8811h_probe(struct phy_device *phydev) return 0; } -static int air_phy_read_page(struct phy_device *phydev) -{ - return phy_read(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS); -} - -static int air_phy_write_page(struct phy_device *phydev, int page) -{ - return phy_write(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS, page); -} - U_BOOT_PHY_DRIVER(en8811h) = { .name = "Airoha EN8811H", .uid = EN8811H_PHY_ID, diff --git a/drivers/net/phy/airoha/air_phy_lib.c b/drivers/net/phy/airoha/air_phy_lib.c new file mode 100644 index 00000000000..61c3bf82822 --- /dev/null +++ b/drivers/net/phy/airoha/air_phy_lib.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Airoha Ethernet PHY common library + * + * Copyright (C) 2026 Airoha Technology Corp. + * Copyright (C) 2026 Collabora Ltd. + * Louis-Alexis Eyraud <[email protected]> + * + * Adapated from https://lore.kernel.org/all/20260326-add-airoha-an8801-support-v2-2-1a42d6b6050f@collabora.com/ + */ + +#include <dm/device_compat.h> +#include <linux/compat.h> +#include <phy.h> + +#include "air_phy_lib.h" + +#define AIR_EXT_PAGE_ACCESS 0x1f + +static int __air_buckpbus_reg_read(struct phy_device *phydev, + u32 pbus_address, u32 *pbus_data) +{ + int pbus_data_low, pbus_data_high; + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, + AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_HIGH, + upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_LOW, + lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + + pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, + AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) + return pbus_data_high; + + pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, + AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) + return pbus_data_low; + + *pbus_data = pbus_data_low | (pbus_data_high << 16); + return 0; +} + +static int __air_buckpbus_reg_write(struct phy_device *phydev, + u32 pbus_address, u32 pbus_data) +{ + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, + AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_HIGH, + upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_LOW, + lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_HIGH, + upper_16_bits(pbus_data)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_LOW, + lower_16_bits(pbus_data)); + if (ret < 0) + return ret; + + return 0; +} + +static int __air_buckpbus_reg_modify(struct phy_device *phydev, + u32 pbus_address, u32 mask, u32 set) +{ + int pbus_data_low, pbus_data_high; + u32 pbus_data_old, pbus_data_new; + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_MODE, + AIR_BPBUS_MODE_ADDR_FIXED); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_HIGH, + upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_RD_ADDR_LOW, + lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + + pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, + AIR_BPBUS_RD_DATA_HIGH); + if (pbus_data_high < 0) + return pbus_data_high; + + pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, + AIR_BPBUS_RD_DATA_LOW); + if (pbus_data_low < 0) + return pbus_data_low; + + pbus_data_old = pbus_data_low | (pbus_data_high << 16); + pbus_data_new = (pbus_data_old & ~mask) | set; + if (pbus_data_new == pbus_data_old) + return 0; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_HIGH, + upper_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_ADDR_LOW, + lower_16_bits(pbus_address)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_HIGH, + upper_16_bits(pbus_data_new)); + if (ret < 0) + return ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AIR_BPBUS_WR_DATA_LOW, + lower_16_bits(pbus_data_new)); + if (ret < 0) + return ret; + + return 0; +} + +int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address, + u32 *pbus_data) +{ + int saved_page; + int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + + if (saved_page >= 0) { + ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data); + if (ret < 0) + dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, + pbus_address, ret); + } + + return phy_restore_page(phydev, saved_page, ret); +} + +int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address, + u32 pbus_data) +{ + int saved_page; + int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + + if (saved_page >= 0) { + ret = __air_buckpbus_reg_write(phydev, pbus_address, + pbus_data); + if (ret < 0) + dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, + pbus_address, ret); + } + + return phy_restore_page(phydev, saved_page, ret); +} + +int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address, + u32 mask, u32 set) +{ + int saved_page; + int ret = 0; + + saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); + + if (saved_page >= 0) { + ret = __air_buckpbus_reg_modify(phydev, pbus_address, mask, + set); + if (ret < 0) + dev_err(phydev->dev, "%s 0x%08x failed: %d\n", __func__, + pbus_address, ret); + } + + return phy_restore_page(phydev, saved_page, ret); +} + +int air_phy_read_page(struct phy_device *phydev) +{ + return phy_read(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS); +} + +int air_phy_write_page(struct phy_device *phydev, int page) +{ + return phy_write(phydev, MDIO_DEVAD_NONE, AIR_EXT_PAGE_ACCESS, page); +} + +MODULE_DESCRIPTION("Airoha PHY Library"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Louis-Alexis Eyraud"); diff --git a/drivers/net/phy/airoha/air_phy_lib.h b/drivers/net/phy/airoha/air_phy_lib.h new file mode 100644 index 00000000000..845d2f7cfb4 --- /dev/null +++ b/drivers/net/phy/airoha/air_phy_lib.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2026 Airoha Technology Corp. + * Copyright (C) 2026 Collabora Ltd. + * Louis-Alexis Eyraud <[email protected]> + */ + +#ifndef __AIR_PHY_LIB_H +#define __AIR_PHY_LIB_H + +#define AIR_EXT_PAGE_ACCESS 0x1f + +#define AIR_PHY_PAGE_STANDARD 0x0000 +#define AIR_PHY_PAGE_EXTENDED_1 0x0001 +#define AIR_PHY_PAGE_EXTENDED_4 0x0004 + +/* MII Registers Page 4*/ +#define AIR_BPBUS_MODE 0x10 +#define AIR_BPBUS_MODE_ADDR_FIXED 0x0000 +#define AIR_BPBUS_MODE_ADDR_INCR BIT(15) +#define AIR_BPBUS_WR_ADDR_HIGH 0x11 +#define AIR_BPBUS_WR_ADDR_LOW 0x12 +#define AIR_BPBUS_WR_DATA_HIGH 0x13 +#define AIR_BPBUS_WR_DATA_LOW 0x14 +#define AIR_BPBUS_RD_ADDR_HIGH 0x15 +#define AIR_BPBUS_RD_ADDR_LOW 0x16 +#define AIR_BPBUS_RD_DATA_HIGH 0x17 +#define AIR_BPBUS_RD_DATA_LOW 0x18 + +int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address, + u32 mask, u32 set); +int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address, + u32 *pbus_data); +int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address, + u32 pbus_data); +int air_phy_read_page(struct phy_device *phydev); +int air_phy_write_page(struct phy_device *phydev, int page); + +#endif /* __AIR_PHY_LIB_H */ diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c index a1e4c3d053b..9814ac498ed 100644 --- a/drivers/net/phy/nxp-c45-tja11xx.c +++ b/drivers/net/phy/nxp-c45-tja11xx.c @@ -343,7 +343,7 @@ static int nxp_c45_probe(struct phy_device *phydev) { struct nxp_c45_phy *priv; - priv = devm_kzalloc(phydev->priv, sizeof(*priv), GFP_KERNEL); + priv = kzalloc(sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; diff --git a/drivers/net/qe/dm_qe_uec.c b/drivers/net/qe/dm_qe_uec.c index ac3aedd8b49..f9bc5d49c8f 100644 --- a/drivers/net/qe/dm_qe_uec.c +++ b/drivers/net/qe/dm_qe_uec.c @@ -1133,7 +1133,7 @@ static int qe_uec_of_to_plat(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); - pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); + pdata->iobase = (phys_addr_t)dev_read_addr(dev); pdata->phy_interface = dev_read_phy_mode(dev); if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 5b093623619..e203faed26b 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -404,7 +404,7 @@ static int rtl8169_init_board(unsigned long dev_iobase, const char *name) u32 tmp; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_iobase; @@ -534,7 +534,7 @@ static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, int length = 0; #ifdef DEBUG_RTL8169_RX - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_iobase; @@ -608,7 +608,7 @@ static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, #ifdef DEBUG_RTL8169_TX int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); printf("sending %d bytes\n", len); #endif @@ -679,7 +679,7 @@ static void rtl8169_set_rx_mode(void) u32 tmp = 0; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif /* IFF_ALLMULTI */ @@ -701,7 +701,7 @@ static void rtl8169_hw_start(struct udevice *dev) #ifdef DEBUG_RTL8169 int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif #if 0 @@ -771,7 +771,7 @@ static void rtl8169_init_ring(struct udevice *dev) #ifdef DEBUG_RTL8169 int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif tpc->cur_rx = 0; @@ -810,7 +810,7 @@ static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr, #ifdef DEBUG_RTL8169 int stime = currticks(); - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_iobase; @@ -851,7 +851,7 @@ static void rtl_halt_common(struct udevice *dev) int i; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = priv->iobase; @@ -906,7 +906,7 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name, int option = -1, Cap10_100 = 0, Cap1000 = 0; #ifdef DEBUG_RTL8169 - printf ("%s\n", __FUNCTION__); + printf("%s\n", __func__); #endif ioaddr = dev_ioaddr; diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 93c3a0c35f2..2d72af8aade 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -14,7 +14,7 @@ config DRIVER_TI_EMAC bool "TI Davinci EMAC" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS help - Support for davinci emac + Support for davinci emac config DRIVER_TI_EMAC_USE_RMII depends on DRIVER_TI_EMAC @@ -26,7 +26,7 @@ config DRIVER_TI_KEYSTONE_NET bool "TI Keystone 2 Ethernet" depends on ARCH_KEYSTONE help - This driver supports the TI Keystone 2 Ethernet subsystem + This driver supports the TI Keystone 2 Ethernet subsystem choice prompt "TI Keystone 2 Ethernet NETCP IP revision" diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index bd4ebdd745a..d03368b9408 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -37,6 +37,23 @@ ) #endif /* CFG_TSEC_TBICR_SETTINGS */ +struct tsec_private { + struct txbd8 __iomem txbd[TX_BUF_CNT]; + struct rxbd8 __iomem rxbd[PKTBUFSRX]; + struct tsec __iomem *regs; + struct tsec_mii_mng __iomem *phyregs_sgmii; + struct phy_device *phydev; + phy_interface_t interface; + struct mii_dev *bus; + uint phyaddr; + uint tbiaddr; + char mii_devname[16]; + u32 flags; + uint rx_idx; /* index of the current RX buffer */ + uint tx_idx; /* index of the current TX buffer */ + struct udevice *dev; +}; + /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) { diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 39df0e776df..9ffccc3a80b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -101,11 +101,11 @@ config PCI_ENHANCED_ALLOCATION devices in place of traditional BARS for allocation of resources. config PCI_ARID - bool "Enable Alternate Routing-ID support for PCI" - help - Say Y here if you want to enable Alternate Routing-ID capability - support on PCI devices. This helps to skip some devices in BDF - scan that are not present. + bool "Enable Alternate Routing-ID support for PCI" + help + Say Y here if you want to enable Alternate Routing-ID capability + support on PCI devices. This helps to skip some devices in BDF + scan that are not present. config PCI_SCAN_SHOW bool "Show PCI devices during startup" @@ -287,7 +287,7 @@ config PCI_IOMMU_EXTRA_MAPPINGS the node describing the PCI controller. The intent is to cover SR-IOV scenarios which need mappings for VFs and PCI hot-plug scenarios. More documentation can be found under: - arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra + arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint mode support" @@ -440,8 +440,8 @@ config PCIE_XILINX_NWL bool "Xilinx NWL PCIe controller" depends on ARCH_ZYNQMP help - Say 'Y' here if you want support for Xilinx / AMD NWL PCIe - controller as Root Port. + Say 'Y' here if you want support for Xilinx / AMD NWL PCIe + controller as Root Port. config PCIE_PLDA_COMMON bool diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index 08d5c4fbb8b..53cb0916741 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -10,6 +10,7 @@ #include <clk.h> #include <dm.h> #include <errno.h> +#include <fdtdec.h> #include <pci.h> #include <linux/bitops.h> @@ -235,9 +236,9 @@ static int rcar_gen2_pci_of_to_plat(struct udevice *dev) { struct rcar_gen2_pci_priv *priv = dev_get_priv(dev); - priv->cfg_base = devfdt_get_addr_index(dev, 0); - priv->mem_base = devfdt_get_addr_index(dev, 1); - if (!priv->cfg_base || !priv->mem_base) + priv->cfg_base = dev_read_addr_index(dev, 0); + priv->mem_base = dev_read_addr_index(dev, 1); + if (priv->cfg_base == FDT_ADDR_T_NONE || priv->mem_base == FDT_ADDR_T_NONE) return -EINVAL; return 0; diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index d4b4037ce19..1925d968c16 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -19,6 +19,7 @@ #include <clk.h> #include <dm.h> #include <errno.h> +#include <fdtdec.h> #include <pci.h> #include <wait_bit.h> #include <linux/bitops.h> @@ -391,8 +392,8 @@ static int rcar_gen3_pcie_of_to_plat(struct udevice *dev) { struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev); - priv->regs = devfdt_get_addr_index(dev, 0); - if (!priv->regs) + priv->regs = dev_read_addr_index(dev, 0); + if (priv->regs == FDT_ADDR_T_NONE) return -EINVAL; return 0; diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index f58d542ef75..4bdd1f7477f 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1126,14 +1126,14 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node, return 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (bd->bi_dram[i].size) { - phys_addr_t start = bd->bi_dram[i].start; + if (gd->dram[i].size) { + phys_addr_t start = gd->dram[i].start; if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY)) - start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start); + start = virt_to_phys((void *)(uintptr_t)gd->dram[i].start); pci_set_region(hose->regions + hose->region_count++, - start, start, bd->bi_dram[i].size, + start, start, gd->dram[i].size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); } } diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index c07feba7976..96550a9ff8f 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -170,13 +170,14 @@ static int mpc85xx_pci_dm_remove(struct udevice *dev) static int mpc85xx_pci_of_to_plat(struct udevice *dev) { struct mpc85xx_pci_priv *priv = dev_get_priv(dev); - fdt_addr_t addr; + void __iomem *addr; - addr = devfdt_get_addr_index(dev, 0); - if (addr == FDT_ADDR_T_NONE) + addr = dev_remap_addr_index(dev, 0); + if (!addr) return -EINVAL; - priv->cfg_addr = (void __iomem *)map_physmem(addr, 0, MAP_NOCACHE); - priv->cfg_data = (void __iomem *)((ulong)priv->cfg_addr + 4); + + priv->cfg_addr = addr; + priv->cfg_data = priv->cfg_addr + 4; return 0; } diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 43b919175c9..5a177478afc 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -565,13 +565,12 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev) struct pcie_dw_mvebu *pcie = dev_get_priv(dev); /* Get the controller base address */ - pcie->ctrl_base = devfdt_get_addr_index_ptr(dev, 0); + pcie->ctrl_base = dev_read_addr_index_ptr(dev, 0); if (!pcie->ctrl_base) return -EINVAL; /* Get the config space base address and size */ - pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1, - &pcie->cfg_size); + pcie->cfg_base = dev_read_addr_size_index_ptr(dev, 1, &pcie->cfg_size); if (!pcie->cfg_base) return -EINVAL; diff --git a/drivers/pci/pcie_dw_qcom.c b/drivers/pci/pcie_dw_qcom.c index 10c45aaba20..ce6b4d97d1d 100644 --- a/drivers/pci/pcie_dw_qcom.c +++ b/drivers/pci/pcie_dw_qcom.c @@ -22,7 +22,7 @@ struct qcom_pcie; -struct qcom_pcie_ops { +static const struct qcom_pcie_ops { int (*config_sid)(struct qcom_pcie *priv); }; diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 8d853ecf2c2..c8b8e171e39 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -774,8 +774,8 @@ static int imx_pcie_of_to_plat(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); - priv->dbi_base = devfdt_get_addr_index_ptr(dev, 0); - priv->cfg_base = devfdt_get_addr_index_ptr(dev, 1); + priv->dbi_base = dev_read_addr_index_ptr(dev, 0); + priv->cfg_base = dev_read_addr_index_ptr(dev, 1); if (!priv->dbi_base || !priv->cfg_base) return -EINVAL; diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index d5f4930e181..e6d47241e71 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -10,6 +10,7 @@ #include <fdtdec.h> #include <pci.h> +#include <linux/ioport.h> #include <linux/sizes.h> #include <linux/types.h> #include <asm/arch-fsl-layerscape/svr.h> @@ -164,7 +165,7 @@ struct ls_pcie_rc { }; struct ls_pcie_ep { - struct fdt_resource addr_res; + struct resource addr_res; struct ls_pcie *pcie; struct udevice *bus; void __iomem *addr; diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index 3520488b345..b7809857565 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -7,7 +7,6 @@ #include <config.h> #include <asm/arch/fsl_serdes.h> #include <dm.h> -#include <asm/global_data.h> #include <dm/devres.h> #include <errno.h> #include <pci_ep.h> @@ -16,8 +15,6 @@ #include <linux/log2.h> #include "pcie_layerscape.h" -DECLARE_GLOBAL_DATA_PTR; - static void ls_pcie_ep_enable_cfg(struct ls_pcie_ep *pcie_ep) { struct ls_pcie *pcie = pcie_ep->pcie; @@ -250,17 +247,15 @@ static int ls_pcie_ep_probe(struct udevice *dev) pcie_ep->pcie = pcie; - pcie->dbi = devfdt_get_addr_index_ptr(dev, 0); + pcie->dbi = dev_read_addr_index_ptr(dev, 0); if (!pcie->dbi) return -EINVAL; - pcie->ctrl = devfdt_get_addr_index_ptr(dev, 1); + pcie->ctrl = dev_read_addr_index_ptr(dev, 1); if (!pcie->ctrl) return -EINVAL; - ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev), - "reg", "reg-names", - "addr_space", &pcie_ep->addr_res); + ret = dev_read_resource_byname(dev, "addr_space", &pcie_ep->addr_res); if (ret) { printf("%s: resource \"addr_space\" not found\n", dev->name); return ret; @@ -273,8 +268,7 @@ static int ls_pcie_ep_probe(struct udevice *dev) if (!is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx))) return 0; - pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), - "big-endian"); + pcie->big_endian = dev_read_bool(dev, "big-endian"); svr = SVR_SOC_VER(get_svr()); @@ -294,13 +288,9 @@ static int ls_pcie_ep_probe(struct udevice *dev) if (pcie->mode != PCI_HEADER_TYPE_NORMAL) return 0; - pcie_ep->max_functions = fdtdec_get_int(gd->fdt_blob, - dev_of_offset(dev), - "max-functions", 1); - pcie_ep->num_ib_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "num-ib-windows", 8); - pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "num-ob-windows", 8); + pcie_ep->max_functions = dev_read_s32_default(dev, "max-functions", 1); + pcie_ep->num_ib_wins = dev_read_s32_default(dev, "num-ib-windows", 8); + pcie_ep->num_ob_wins = dev_read_s32_default(dev, "num-ob-windows", 8); printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, "Endpoint"); diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig index 9900481daa6..d1db4951a0c 100644 --- a/drivers/pci_endpoint/Kconfig +++ b/drivers/pci_endpoint/Kconfig @@ -9,10 +9,10 @@ config PCI_ENDPOINT bool "PCI Endpoint Support" depends on DM help - Enable this configuration option to support configurable PCI - endpoints. This should be enabled if the platform has a PCI - controllers that can operate in endpoint mode (as a device - connected to PCI host or bridge). + Enable this configuration option to support configurable PCI + endpoints. This should be enabled if the platform has a PCI + controllers that can operate in endpoint mode (as a device + connected to PCI host or bridge). config PCIE_CADENCE_EP bool "Cadence PCIe endpoint controller" diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 5c8ec2b146f..89d84df96ae 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -72,14 +72,14 @@ config AB8500_USB_PHY Support for the USB OTG PHY in ST-Ericsson AB8500. config APPLE_ATCPHY - bool "Apple Type-C PHY Driver" - depends on PHY && ARCH_APPLE - default y - help - Support for the Apple Type-C PHY. + bool "Apple Type-C PHY Driver" + depends on PHY && ARCH_APPLE + default y + help + Support for the Apple Type-C PHY. - This is a dummy driver since the PHY is initialized - sufficiently by previous stage firmware. + This is a dummy driver since the PHY is initialized + sufficiently by previous stage firmware. config BCM6318_USBH_PHY bool "BCM6318 USBH PHY support" @@ -114,7 +114,7 @@ config BCM_SR_PCIE_PHY If unsure, say N. config PHY_DA8XX_USB - tristate "TI DA8xx USB PHY Driver" + bool "TI DA8xx USB PHY Driver" depends on PHY && ARCH_DAVINCI help Enable this to support the USB PHY on DA8xx SoCs. @@ -138,7 +138,7 @@ config SPL_PIPE3_PHY and omap5 config AM654_PHY - tristate "TI AM654 SERDES support" + bool "TI AM654 SERDES support" depends on PHY && ARCH_K3 select REGMAP select SYSCON @@ -155,7 +155,7 @@ config STI_USB_PHY STiH407 SoC families. config PHY_RCAR_GEN2 - tristate "Renesas R-Car Gen2 USB PHY" + bool "Renesas R-Car Gen2 USB PHY" depends on PHY && RCAR_GEN2 help Support for the Renesas R-Car Gen2 USB PHY. This driver operates the @@ -163,7 +163,7 @@ config PHY_RCAR_GEN2 allows configuring the module multiplexing. config PHY_RCAR_GEN3 - tristate "Renesas R-Car Gen3 USB PHY" + bool "Renesas R-Car Gen3 USB PHY" depends on PHY && CLK && DM_REGULATOR && (RCAR_GEN3 || RZG2L) default y if (RCAR_GEN3 || RZG2L) help @@ -171,7 +171,7 @@ config PHY_RCAR_GEN3 PHY connected to EHCI USB module and controls USB OTG operation. config PHY_STM32_USBPHYC - tristate "STMicroelectronics STM32 SoC USB HS PHY driver" + bool "STMicroelectronics STM32 SoC USB HS PHY driver" depends on PHY && ARCH_STM32MP help Enable this to support the High-Speed USB transceiver that is part of @@ -249,14 +249,14 @@ config MT7620_USB_PHY depends on PHY depends on SOC_MT7620 help - Support the intergated USB PHY in MediaTek MT7620 SoC + Support the intergated USB PHY in MediaTek MT7620 SoC config MT76X8_USB_PHY bool "MediaTek MT76x8 (7628/88) USB PHY support" depends on PHY depends on SOC_MT7628 help - Support the USB PHY in MT76x8 SoCs + Support the USB PHY in MT76x8 SoCs This PHY is found on MT76x8 devices supporting USB. @@ -283,7 +283,7 @@ config PHY_MTK_TPHY so you can easily distinguish them by banks layout. config PHY_MTK_UFS - tristate "MediaTek UFS M-PHY driver" + bool "MediaTek UFS M-PHY driver" depends on ARCH_MEDIATEK depends on PHY help @@ -337,7 +337,7 @@ config PHY_IMX8M_PCIE This PHY is found on i.MX8M devices supporting PCIe. config PHY_XILINX_ZYNQMP - tristate "Xilinx ZynqMP PHY driver" + bool "Xilinx ZynqMP PHY driver" depends on PHY && ARCH_ZYNQMP help Enable this to support ZynqMP High Speed Gigabit Transceiver diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig index 8c0ab80fbbc..f5f096889fe 100644 --- a/drivers/phy/cadence/Kconfig +++ b/drivers/phy/cadence/Kconfig @@ -1,11 +1,11 @@ config PHY_CADENCE_SIERRA - tristate "Cadence Sierra PHY Driver" + bool "Cadence Sierra PHY Driver" depends on DM_RESET help Enable this to support the Cadence Sierra PHY driver config PHY_CADENCE_TORRENT - tristate "Cadence Torrent PHY Driver" + bool "Cadence Torrent PHY Driver" depends on DM_RESET help Enable this to support the Cadence Torrent PHY driver diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index bd7ab9d1b77..9f8a6d8d43d 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -1068,12 +1068,12 @@ static int cdns_sierra_phy_probe(struct udevice *dev) sp->dev = dev; - sp->base = devfdt_remap_addr_index(dev, 0); + sp->base = dev_remap_addr_index(dev, 0); if (!sp->base) { dev_err(dev, "unable to map regs\n"); return -ENOMEM; } - devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&sp->size); + dev_read_addr_size_index(dev, 0, (fdt_size_t *)&sp->size); /* Get init data for this PHY */ data = (struct cdns_sierra_data *)dev_get_driver_data(dev); diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 933533b2b0b..814aff15070 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -791,10 +791,10 @@ static int cdns_torrent_phy_probe(struct udevice *dev) return ret; } - cdns_phy->sd_base = devfdt_remap_addr_index(dev, 0); - if (IS_ERR(cdns_phy->sd_base)) - return PTR_ERR(cdns_phy->sd_base); - devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&cdns_phy->size); + cdns_phy->sd_base = dev_remap_addr_index(dev, 0); + if (!cdns_phy->sd_base) + return -EINVAL; + dev_read_addr_size_index(dev, 0, (fdt_size_t *)&cdns_phy->size); dev_for_each_subnode(child, dev) subnodes++; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index b074d58f9f6..0ab5f9a3f0a 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -84,11 +84,11 @@ static int comphy_probe(struct udevice *dev) int res; /* Save base addresses for later use */ - chip_cfg->comphy_base_addr = devfdt_get_addr_index_ptr(dev, 0); + chip_cfg->comphy_base_addr = dev_read_addr_index_ptr(dev, 0); if (!chip_cfg->comphy_base_addr) return -EINVAL; - chip_cfg->hpipe3_base_addr = devfdt_get_addr_index_ptr(dev, 1); + chip_cfg->hpipe3_base_addr = dev_read_addr_index_ptr(dev, 1); if (!chip_cfg->hpipe3_base_addr) return -EINVAL; diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index 49f830abf01..1fdadaccb12 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -2,12 +2,12 @@ config MSM8916_USB_PHY bool select PHY help - Support the Qualcomm MSM8916 USB PHY + Support the Qualcomm MSM8916 USB PHY This PHY is found on qualcomm dragonboard410c development board. config PHY_QCOM_IPQ4019_USB - tristate "Qualcomm IPQ4019 USB PHY driver" + bool "Qualcomm IPQ4019 USB PHY driver" depends on PHY && ARCH_IPQ40XX help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. @@ -21,26 +21,26 @@ config PHY_QCOM_QMP_COMBO PHY (USB3 + DisplayPort). Currently only USB3 mode is supported. config PHY_QCOM_QMP_PCIE - tristate "Qualcomm QMP PCIe PHY driver" + bool "Qualcomm QMP PCIe PHY driver" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the PCIe QMP PHY on various Qualcomm chipsets. config PHY_QCOM_QMP_UFS - tristate "Qualcomm QMP UFS PHY driver" + bool "Qualcomm QMP UFS PHY driver" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the UFS QMP PHY on various Qualcomm chipsets. config PHY_QCOM_QUSB2 - tristate "Qualcomm USB QUSB2 PHY driver" + bool "Qualcomm USB QUSB2 PHY driver" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Super-Speed USB transceiver on various Qualcomm chipsets. config PHY_QCOM_USB_SNPS_FEMTO_V2 - tristate "Qualcomm SNPS FEMTO USB HS PHY v2" + bool "Qualcomm SNPS FEMTO USB HS PHY v2" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Qualcomm Synopsys DesignWare Core 7nm @@ -48,7 +48,7 @@ config PHY_QCOM_USB_SNPS_FEMTO_V2 is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. config PHY_QCOM_SNPS_EUSB2 - tristate "Qualcomm Synopsys eUSB2 High-Speed PHY" + bool "Qualcomm Synopsys eUSB2 High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Qualcomm Synopsys DesignWare eUSB2 @@ -56,7 +56,7 @@ config PHY_QCOM_SNPS_EUSB2 is usually paired with Synopsys DWC3 USB IPs on MSM SOCs. config PHY_QCOM_USB_HS_28NM - tristate "Qualcomm 28nm High-Speed PHY" + bool "Qualcomm 28nm High-Speed PHY" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Qualcomm Synopsys DesignWare Core 28nm @@ -65,7 +65,7 @@ config PHY_QCOM_USB_HS_28NM IPs on MSM SOCs. config PHY_QCOM_USB_SS - tristate "Qualcomm USB Super-Speed PHY driver" + bool "Qualcomm USB Super-Speed PHY driver" depends on PHY && ARCH_SNAPDRAGON help Enable this to support the Super-Speed USB transceiver on various diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c index 80eba734a63..3df88189a90 100644 --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c @@ -1741,6 +1741,8 @@ static const struct udevice_id qmp_ufs_ids[] = { { .compatible = "qcom,milos-qmp-ufs-phy", .data = (ulong)&milos_ufsphy_cfg, }, { .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, }, { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, + { .compatible = "qcom,sm6115-qmp-ufs-phy", .data = (ulong)&sm6115_ufsphy_cfg, }, + { .compatible = "qcom,sm6125-qmp-ufs-phy", .data = (ulong)&sm6115_ufsphy_cfg, }, { .compatible = "qcom,sm6350-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, { .compatible = "qcom,sm7150-qmp-ufs-phy", .data = (ulong)&sm7150_ufsphy_cfg }, { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg }, diff --git a/drivers/phy/renesas/Kconfig b/drivers/phy/renesas/Kconfig index affbee0500c..3358d454e59 100644 --- a/drivers/phy/renesas/Kconfig +++ b/drivers/phy/renesas/Kconfig @@ -3,19 +3,19 @@ # Phy drivers for Renesas platforms config PHY_R8A779F0_ETHERNET_SERDES - tristate "Renesas R-Car S4-8 Ethernet SERDES driver" + bool "Renesas R-Car S4-8 Ethernet SERDES driver" depends on RCAR_64 && PHY help Support for Ethernet SERDES found on Renesas R-Car S4-8 SoCs. config PHY_R8A78000_ETHERNET_PCS - tristate "Renesas R-Car X5H Ethernet PCS driver" + bool "Renesas R-Car X5H Ethernet PCS driver" depends on RCAR_64 && PHY help Support for Ethernet PCS found on Renesas R-Car X5H SoCs. config PHY_R8A78000_MP_PHY - tristate "Renesas R-Car X5H Multi-Protocol PHY driver" + bool "Renesas R-Car X5H Multi-Protocol PHY driver" depends on RCAR_64 && PHY help Support for Multi-Protocol PHY on Renesas R-Car X5H SoCs. diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 80128335d52..6f3d7ebe29e 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -49,7 +49,7 @@ config PHY_ROCKCHIP_SNPS_PCIE3 also be able splited into multiple combinations of lanes. config PHY_ROCKCHIP_USBDP - tristate "Rockchip USBDP COMBO PHY Driver" + bool "Rockchip USBDP COMBO PHY Driver" depends on ARCH_ROCKCHIP select PHY help diff --git a/drivers/phy/ti-pipe3-phy.c b/drivers/phy/ti-pipe3-phy.c index 62f6cc2bfbf..080016ba417 100644 --- a/drivers/phy/ti-pipe3-phy.c +++ b/drivers/phy/ti-pipe3-phy.c @@ -6,6 +6,7 @@ #include <dm.h> #include <dm/device.h> +#include <dm/device_compat.h> #include <generic-phy.h> #include <asm/global_data.h> #include <asm/io.h> @@ -428,10 +429,10 @@ static int pipe3_exit(struct phy *phy) static void *get_reg(struct udevice *dev, const char *name) { + struct ofnode_phandle_args phandle; struct udevice *syscon; struct regmap *regmap; - const fdt32_t *cell; - int len, err; + int err; void *base; err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, @@ -449,10 +450,14 @@ static void *get_reg(struct udevice *dev, const char *name) return NULL; } - cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name, - &len); - if (len < 2*sizeof(fdt32_t)) { - pr_err("offset not available for %s\n", name); + err = dev_read_phandle_with_args(dev, name, NULL, 0, 0, &phandle); + if (err) { + dev_err(dev, "parse %s failed: %d\n", name, err); + return NULL; + } + + if (phandle.args_count < 1) { + dev_err(dev, "%s: missing args\n", name); return NULL; } @@ -460,7 +465,7 @@ static void *get_reg(struct udevice *dev, const char *name) if (!base) return NULL; - return fdtdec_get_number(cell + 1, 1) + base; + return base + phandle.args[0]; } static int pipe3_phy_probe(struct udevice *dev) @@ -471,7 +476,7 @@ static int pipe3_phy_probe(struct udevice *dev) struct pipe3_data *data; /* PHY_RX */ - addr = devfdt_get_addr_size_index(dev, 0, &sz); + addr = dev_read_addr_size_index(dev, 0, &sz); if (addr == FDT_ADDR_T_NONE) { pr_err("missing phy_rx address\n"); return -EINVAL; @@ -484,7 +489,7 @@ static int pipe3_phy_probe(struct udevice *dev) } /* PLLCTRL */ - addr = devfdt_get_addr_size_index(dev, 2, &sz); + addr = dev_read_addr_size_index(dev, 2, &sz); if (addr == FDT_ADDR_T_NONE) { pr_err("missing pll ctrl address\n"); return -EINVAL; diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index df750b26d66..fe96eb6806f 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -1,5 +1,5 @@ config PHY_J721E_WIZ - tristate "TI J721E WIZ (SERDES Wrapper) support" + bool "TI J721E WIZ (SERDES Wrapper) support" depends on ARCH_K3 help This option enables support for WIZ module present in TI's J721E diff --git a/drivers/pinctrl/broadcom/Kconfig b/drivers/pinctrl/broadcom/Kconfig index b01b725583a..d7cf3855928 100644 --- a/drivers/pinctrl/broadcom/Kconfig +++ b/drivers/pinctrl/broadcom/Kconfig @@ -3,13 +3,13 @@ config PINCTRL_BCM283X default y bool "Broadcom 283x family pin control driver" help - Support pin multiplexing and pin configuration control on - Broadcom's 283x family of SoCs. + Support pin multiplexing and pin configuration control on + Broadcom's 283x family of SoCs. config PINCTRL_BCM6838 depends on ARCH_BMIPS && PINCTRL_FULL && OF_CONTROL default y bool "Broadcom 6838 family pin control driver" help - Support pin multiplexing and pin configuration control on - Broadcom's 6838 family of SoCs. + Support pin multiplexing and pin configuration control on + Broadcom's 6838 family of SoCs. diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index cf72a7df62c..5a90d74a9e1 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -59,7 +59,7 @@ config PINCTRL_MT8516 select PINCTRL_MTK config PINCTRL_MT8518 - bool "MT8518 SoC pinctrl driver" + bool "MT8518 SoC pinctrl driver" select PINCTRL_MTK endif diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index cfffbaeef84..01f67f09407 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -251,7 +251,7 @@ static int mtk_pinconf_get(struct udevice *dev, u32 pin, char *buf, size_t size) if (mtk_get_pin_io_type(dev, pin, &io_type)) return 0; - pos = snprintf(buf, size, " (%s)", io_type.name); + pos = scnprintf(buf, size, " (%s)", io_type.name); if (pos >= size) return pos; @@ -306,7 +306,7 @@ static int mtk_get_pin_muxing(struct udevice *dev, unsigned int selector, if (err) return err; - pos = snprintf(buf, size, "Aux Func.%d", val); + pos = scnprintf(buf, size, "Aux Func.%d", val); if (pos >= size) return 0; @@ -721,7 +721,7 @@ int mtk_pinconf_get_pu_pd(struct udevice *dev, u32 pin, char *buf, size_t size) if (err) return err; - return snprintf(buf, size, " PU:%d PD:%d", pu, pd); + return scnprintf(buf, size, " PU:%d PD:%d", pu, pd); } int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t size) @@ -740,7 +740,7 @@ int mtk_pinconf_get_pupd_r1_r0(struct udevice *dev, u32 pin, char *buf, size_t s if (err) return err; - return snprintf(buf, size, " PUPD:%d R1:%d R0:%d", pupd, r1, r0); + return scnprintf(buf, size, " PUPD:%d R1:%d R0:%d", pupd, r1, r0); } int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t size) @@ -755,7 +755,7 @@ int mtk_pinconf_get_pu_pd_rsel(struct udevice *dev, u32 pin, char *buf, size_t s if (err) return err; - return pos + snprintf(buf + pos, size - pos, " RSEL:%d", rsel); + return pos + scnprintf(buf + pos, size - pos, " RSEL:%d", rsel); } #endif diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig index 567c93f404c..285787c4467 100644 --- a/drivers/pinctrl/mscc/Kconfig +++ b/drivers/pinctrl/mscc/Kconfig @@ -10,8 +10,8 @@ config PINCTRL_MSCC_OCELOT default y bool "Microsemi ocelot family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi ocelot SoCs. + Support pin multiplexing and pin configuration control on + Microsemi ocelot SoCs. config PINCTRL_MSCC_LUTON depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL @@ -19,8 +19,8 @@ config PINCTRL_MSCC_LUTON default y bool "Microsemi luton family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi luton SoCs. + Support pin multiplexing and pin configuration control on + Microsemi luton SoCs. config PINCTRL_MSCC_JR2 depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL @@ -28,8 +28,8 @@ config PINCTRL_MSCC_JR2 default y bool "Microsemi jr2 family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi jr2 SoCs. + Support pin multiplexing and pin configuration control on + Microsemi jr2 SoCs. config PINCTRL_MSCC_SERVALT depends on SOC_SERVALT && PINCTRL_FULL && OF_CONTROL @@ -37,8 +37,8 @@ config PINCTRL_MSCC_SERVALT default y bool "Microsemi servalt family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi servalt SoCs. + Support pin multiplexing and pin configuration control on + Microsemi servalt SoCs. config PINCTRL_MSCC_SERVAL depends on SOC_SERVAL && PINCTRL_FULL && OF_CONTROL @@ -46,6 +46,6 @@ config PINCTRL_MSCC_SERVAL default y bool "Microsemi serval family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi serval SoCs. + Support pin multiplexing and pin configuration control on + Microsemi serval SoCs. diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig index 10ba440f246..72b97a7935d 100644 --- a/drivers/pinctrl/mvebu/Kconfig +++ b/drivers/pinctrl/mvebu/Kconfig @@ -4,22 +4,22 @@ config PINCTRL_ARMADA_38X depends on ARMADA_38X && PINCTRL_FULL bool "Armada 38x pin control driver" help - Support pin multiplexing and pin configuration control on - Marvell's Armada-38x SoC. + Support pin multiplexing and pin configuration control on + Marvell's Armada-38x SoC. config PINCTRL_ARMADA_37XX depends on ARMADA_3700 && PINCTRL_FULL select DEVRES bool "Armada 37xx pin control driver" help - Support pin multiplexing and pin configuration control on - Marvell's Armada-37xx SoC. + Support pin multiplexing and pin configuration control on + Marvell's Armada-37xx SoC. config PINCTRL_ARMADA_8K depends on (ARMADA_8K || ALLEYCAT_5) && PINCTRL_FULL bool "Armada 7k/8k pin control driver" help - Support pin multiplexing and pin configuration control on - Marvell's Armada-8K SoC. + Support pin multiplexing and pin configuration control on + Marvell's Armada-8K SoC. endif diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c index 78184d2860a..c18afe958dc 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c @@ -550,7 +550,7 @@ static int armada_38x_pinctrl_probe(struct udevice *dev) return 0; } -struct pinctrl_ops armada_37xx_pinctrl_ops = { +static const struct pinctrl_ops armada_37xx_pinctrl_ops = { .get_pins_count = armada_38x_pinctrl_get_pins_count, .get_pin_name = armada_38x_pinctrl_get_pin_name, .get_functions_count = armada_38x_pinctrl_get_functions_count, diff --git a/drivers/pinctrl/nexell/pinctrl-nexell.c b/drivers/pinctrl/nexell/pinctrl-nexell.c index af1acd91649..bd89e779864 100644 --- a/drivers/pinctrl/nexell/pinctrl-nexell.c +++ b/drivers/pinctrl/nexell/pinctrl-nexell.c @@ -49,7 +49,7 @@ int nexell_pinctrl_probe(struct udevice *dev) if (!priv) return -EINVAL; - base = devfdt_get_addr(dev); + base = dev_read_addr(dev); if (base == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 2938635ed95..50a130d700f 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -527,7 +527,7 @@ static int at91_pinctrl_probe(struct udevice *dev) if (list_empty(&dev->child_head)) { for (index = 0; index < MAX_GPIO_BANKS; index++) { - addr_base = devfdt_get_addr_index(dev, index); + addr_base = dev_read_addr_index(dev, index); if (addr_base == FDT_ADDR_T_NONE) break; diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 11e6763b5f3..0bea461fcc3 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -79,12 +79,12 @@ config PINCTRL_QCOM_QCS404 as well as the associated GPIO driver. config PINCTRL_QCOM_QCS615 - bool "Qualcomm QCS615 Pinctrl" + bool "Qualcomm QCS615 Pinctrl" default y if PINCTRL_QCOM_GENERIC - select PINCTRL_QCOM - help - Say Y here to enable support for pinctrl on the Snapdragon QCS615 SoC, - as well as the associated GPIO driver. + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon QCS615 SoC, + as well as the associated GPIO driver. config PINCTRL_QCOM_SA8775P bool "Qualcomm SA8775P Pinctrl" @@ -133,6 +133,14 @@ config PINCTRL_QCOM_SM6115 Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_SM6125 + bool "Qualcomm SM6125 Pinctrl" + default y if PINCTRL_QCOM_GENERIC + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM6125 SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_SM6350 bool "Qualcomm SM6350 Pinctrl" default y if PINCTRL_QCOM_GENERIC diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4096c1aa491..87cb128c4d4 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_QCOM_SDM670) += pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_QCOM_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_QCOM_SM6350) += pinctrl-sm6350.o obj-$(CONFIG_PINCTRL_QCOM_SM7150) += pinctrl-sm7150.o obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c new file mode 100644 index 00000000000..82f8972ff5b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Pinctrl driver for Qualcomm SM6125 + * + * (C) Copyright 2026 Biswapriyo Nath <[email protected]> + * + * Based on Linux Kernel driver + */ + +#include <dm.h> + +#include "pinctrl-qcom.h" + +#define TLMM_BASE 0x00500000 +#define WEST (0x00500000 - TLMM_BASE) /* 0x0 */ +#define SOUTH (0x00900000 - TLMM_BASE) /* 0x400000 */ +#define EAST (0x00d00000 - TLMM_BASE) /* 0x800000 */ + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + { "qup04", 1 }, + { "gpio", 0 }, +}; + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = pg_name, \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = pg_name, \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + } + +static const struct msm_special_pin_data msm_special_pins_data[] = { + [0] = UFS_RESET("ufs_reset", 0x190000), + [1] = SDC_QDSD_PINGROUP("sdc1_rclk", WEST + 0x18d000, 15, 0), + [2] = SDC_QDSD_PINGROUP("sdc1_clk", WEST + 0x18d000, 13, 6), + [3] = SDC_QDSD_PINGROUP("sdc1_cmd", WEST + 0x18d000, 11, 3), + [4] = SDC_QDSD_PINGROUP("sdc1_data", WEST + 0x18d000, 9, 0), + [5] = SDC_QDSD_PINGROUP("sdc2_clk", SOUTH + 0x58b000, 14, 6), + [6] = SDC_QDSD_PINGROUP("sdc2_cmd", SOUTH + 0x58b000, 11, 3), + [7] = SDC_QDSD_PINGROUP("sdc2_data", SOUTH + 0x58b000, 9, 0), +}; + +static const unsigned int sm6125_pin_offsets[] = { + [0] = WEST, [1] = WEST, [2] = WEST, [3] = WEST, + [4] = WEST, [5] = WEST, [6] = WEST, [7] = WEST, + [8] = WEST, [9] = WEST, [10] = EAST, [11] = EAST, + [12] = EAST, [13] = EAST, [14] = WEST, [15] = WEST, + [16] = WEST, [17] = WEST, [18] = EAST, [19] = EAST, + [20] = EAST, [21] = EAST, [22] = WEST, [23] = WEST, + [24] = WEST, [25] = WEST, [26] = WEST, [27] = WEST, + [28] = WEST, [29] = WEST, [30] = WEST, [31] = WEST, + [32] = WEST, [33] = WEST, [34] = SOUTH, [35] = SOUTH, + [36] = SOUTH, [37] = SOUTH, [38] = EAST, [39] = EAST, + [40] = EAST, [41] = EAST, [42] = EAST, [43] = EAST, + [44] = SOUTH, [45] = SOUTH, [46] = SOUTH, [47] = SOUTH, + [48] = SOUTH, [49] = SOUTH, [50] = SOUTH, [51] = SOUTH, + [52] = SOUTH, [53] = SOUTH, [54] = SOUTH, [55] = SOUTH, + [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH, + [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH, + [64] = SOUTH, [65] = SOUTH, [66] = SOUTH, [67] = SOUTH, + [68] = SOUTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH, + [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH, + [76] = SOUTH, [77] = SOUTH, [78] = SOUTH, [79] = SOUTH, + [80] = SOUTH, [81] = SOUTH, [82] = SOUTH, [83] = SOUTH, + [84] = SOUTH, [85] = SOUTH, [86] = SOUTH, [87] = WEST, + [88] = WEST, [89] = WEST, [90] = WEST, [91] = WEST, + [92] = WEST, [93] = WEST, [94] = SOUTH, [95] = SOUTH, + [96] = SOUTH, [97] = SOUTH, [98] = SOUTH, [99] = SOUTH, + [100] = SOUTH, [101] = SOUTH, [102] = SOUTH, [103] = SOUTH, + [104] = EAST, [105] = EAST, [106] = EAST, [107] = EAST, + [108] = EAST, [109] = EAST, [110] = EAST, [111] = EAST, + [112] = EAST, [113] = EAST, [114] = EAST, [115] = EAST, + [116] = EAST, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH, + [120] = SOUTH, [121] = EAST, [122] = EAST, [123] = EAST, + [124] = EAST, [125] = EAST, [126] = EAST, [127] = EAST, + [128] = EAST, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH, + [132] = SOUTH, +}; + +static const char *sm6125_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm6125_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector >= 133 && selector <= 140) + snprintf(pin_name, MAX_PIN_NAME_LEN, + msm_special_pins_data[selector - 133].name); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static int sm6125_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm6125_data = { + .pin_data = { + .pin_offsets = sm6125_pin_offsets, + .pin_count = 141, + .special_pins_start = 133, + .special_pins_data = msm_special_pins_data, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm6125_get_function_name, + .get_function_mux = sm6125_get_function_mux, + .get_pin_name = sm6125_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm6125-tlmm", .data = (ulong)&sm6125_data }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_sm6125) = { + .name = "pinctrl_sm6125", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 1b06d8a66c7..66c389d073b 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,7 +1,7 @@ menuconfig POWER - bool "Power" - default y - help + bool "Power" + default y + help Enable support for power control in U-Boot. This includes support for PMICs (Power-management Integrated Circuits) and some of the features provided by PMICs. In particular, voltage regulators can @@ -63,98 +63,98 @@ choice config SUNXI_NO_PMIC bool "board without a pmic" - ---help--- - Select this for boards which do not use a PMIC. + help + Select this for boards which do not use a PMIC. config AXP152_POWER bool "axp152 pmic support" depends on MACH_SUN5I select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp152 pmic found on most - A10s boards. + help + Select this to enable support for the axp152 pmic found on most + A10s boards. config AXP209_POWER bool "axp209 pmic support" depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp209 pmic found on most - A10, A13 and A20 boards. + help + Select this to enable support for the axp209 pmic found on most + A10, A13 and A20 boards. config AXP221_POWER bool "axp221 / axp223 pmic support" depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp221/axp223 pmic found on most - A23 and A31 boards. + help + Select this to enable support for the axp221/axp223 pmic found on most + A23 and A31 boards. config AXP305_POWER bool "axp305 pmic support" depends on MACH_SUN50I_H616 select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp305 pmic found on most - H616 boards. + help + Select this to enable support for the axp305 pmic found on most + H616 boards. config AXP313_POWER bool "axp313 pmic support" depends on MACH_SUN50I_H616 select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the AXP313 PMIC found on some - H616 boards. + help + Select this to enable support for the AXP313 PMIC found on some + H616 boards. config AXP717_POWER bool "axp717 pmic support" select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the AXP717 PMIC found on some boards. + help + Select this to enable support for the AXP717 PMIC found on some boards. config AXP803_POWER bool "AXP803 PMIC support" select AXP_PMIC_BUS - ---help--- - Select this to enable support for the AXP803 PMIC found on some boards. + help + Select this to enable support for the AXP803 PMIC found on some boards. config AXP809_POWER bool "axp809 pmic support" depends on MACH_SUN9I select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Say y here to enable support for the axp809 pmic found on A80 boards. + help + Say y here to enable support for the axp809 pmic found on A80 boards. config AXP818_POWER bool "axp818 pmic support" depends on MACH_SUN8I_A83T select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Say y here to enable support for the axp818 pmic found on - A83T dev board. + help + Say y here to enable support for the axp818 pmic found on + A83T dev board. config AXP318W_POWER bool "axp318w pmic support" select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the AXP318W PMIC found on some - A733 boards. + help + Select this to enable support for the AXP318W PMIC found on some + A733 boards. config SY8106A_POWER bool "SY8106A pmic support" depends on MACH_SUNXI_H3_H5 - ---help--- - Select this to enable support for the SY8106A pmic found on some - H3 boards. + help + Select this to enable support for the SY8106A pmic found on some + H3 boards. endchoice @@ -166,22 +166,22 @@ config AXP_I2C_ADDRESS default 0x36 if AXP318W_POWER default 0x30 if AXP152_POWER default 0x34 - ---help--- - I2C address of the AXP PMIC, used for the SPL only. + help + I2C address of the AXP PMIC, used for the SPL only. config AXP_DCDC1_VOLT int "axp pmic dcdc1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER default 3300 if AXP818_POWER || MACH_SUN8I_R40 || AXP803_POWER default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to - disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for - generic 3.3V IO voltage for external devices like the lcd-panal and - sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to - save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T - dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally - powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. + help + Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to + disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for + generic 3.3V IO voltage for external devices like the lcd-panal and + sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to + save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T + dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally + powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. config AXP_DCDC2_VOLT int "axp pmic dcdc2 voltage" @@ -194,16 +194,16 @@ config AXP_DCDC2_VOLT default 1200 if MACH_SUN6I default 1100 if MACH_SUN8I default 0 if MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to - disable dcdc2. - On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V. - On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V. - On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. - On A80 boards dcdc2 powers the GPU and can be left off. - On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. - On R40 boards dcdc2 is VDD-CPU and should be 1.1V - On boards using the AXP313 or AXP717 it's often VDD-CPU. + help + Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to + disable dcdc2. + On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V. + On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V. + On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. + On A80 boards dcdc2 powers the GPU and can be left off. + On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On R40 boards dcdc2 is VDD-CPU and should be 1.1V + On boards using the AXP313 or AXP717 it's often VDD-CPU. config AXP_DCDC3_VOLT int "axp pmic dcdc3 voltage" @@ -214,18 +214,18 @@ config AXP_DCDC3_VOLT default 1100 if AXP313_POWER default 1100 if MACH_SUN8I_R40 default 1200 if MACH_SUN6I || MACH_SUN8I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to - disable dcdc3. - On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and - should be 1.25V. - On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. - On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. - On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. - On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. - On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V. - On boards using the AXP313 or AXP717 it's often VDD-DRAM and should - be 1.1V for LPDDR4. + help + Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to + disable dcdc3. + On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and + should be 1.25V. + On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. + On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. + On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. + On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V. + On boards using the AXP313 or AXP717 it's often VDD-DRAM and should + be 1.1V for LPDDR4. config AXP_DCDC4_VOLT int "axp pmic dcdc4 voltage" @@ -235,25 +235,25 @@ config AXP_DCDC4_VOLT default 0 if MACH_SUN8I default 900 if MACH_SUN9I default 1500 if AXP305_POWER - ---help--- - Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to - disable dcdc4. - On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. - On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. - On A23 / A33 boards dcdc4 is unused and should be disabled. - On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V. - On A83T boards dcdc4 is used for VDD-GPU. - On H616 boards dcdcd is used for VCC-DRAM. + help + Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to + disable dcdc4. + On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. + On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. + On A23 / A33 boards dcdc4 is unused and should be disabled. + On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V. + On A83T boards dcdc4 is used for VDD-GPU. + On H616 boards dcdcd is used for VCC-DRAM. config AXP_DCDC5_VOLT int "axp pmic dcdc5 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to - disable dcdc5. - On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and - should be 1.5V, 1.35V if DDR3L is used. + help + Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to + disable dcdc5. + On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and + should be 1.5V, 1.35V if DDR3L is used. config AXP_ALDO1_VOLT int "axp pmic (a)ldo1 voltage" @@ -261,14 +261,14 @@ config AXP_ALDO1_VOLT default 0 if MACH_SUN6I || MACH_SUN8I_R40 default 1800 if MACH_SUN8I_A83T default 3000 if MACH_SUN8I || MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to - disable aldo1. - On A31 boards aldo1 is often used to power the wifi module. - On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V. - On A80 boards aldo1 powers the USB hosts and should be 3.0V. - On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and - should be 1.8V. + help + Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to + disable aldo1. + On A31 boards aldo1 is often used to power the wifi module. + On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V. + On A80 boards aldo1 powers the USB hosts and should be 3.0V. + On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and + should be 1.8V. config AXP_ALDO2_VOLT int "axp pmic (a)ldo2 voltage" @@ -277,188 +277,188 @@ config AXP_ALDO2_VOLT default 0 if MACH_SUN6I || MACH_SUN9I default 1800 if MACH_SUN8I_A83T default 2500 if MACH_SUN8I - ---help--- - Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to - disable aldo2. - On A10(s) / A13 / A20 boards aldo2 is AVCC and should be 3.0V. - On A31 boards aldo2 is typically unused and should be disabled. - On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V. - On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V. - On A80 boards aldo2 powers PB pingroup and camera IO and can be left off. - On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC, - LPDDR2, and the codec. It should be 1.8V. + help + Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to + disable aldo2. + On A10(s) / A13 / A20 boards aldo2 is AVCC and should be 3.0V. + On A31 boards aldo2 is typically unused and should be disabled. + On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V. + On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V. + On A80 boards aldo2 powers PB pingroup and camera IO and can be left off. + On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC, + LPDDR2, and the codec. It should be 1.8V. config AXP_ALDO3_VOLT int "axp pmic (a)ldo3 voltage" depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 if AXP209_POWER || MACH_SUN9I default 3000 if MACH_SUN6I || MACH_SUN8I - ---help--- - Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to - disable aldo3. - On A10(s) / A13 / A20 boards aldo3 should be 2.8V. - On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should - be 3.0V. - On A80 boards aldo3 is normally not used. - On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be - 3.0V. + help + Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to + disable aldo3. + On A10(s) / A13 / A20 boards aldo3 should be 2.8V. + On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should + be 3.0V. + On A80 boards aldo3 is normally not used. + On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be + 3.0V. choice prompt "axp pmic (a)ldo3 voltage rate control" depends on AXP209_POWER default AXP_ALDO3_VOLT_SLOPE_NONE - ---help--- - The AXP can slowly ramp up voltage to reduce the inrush current when - changing voltages. - Note, this does not apply when enabling/disabling LDO3. See - "axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit - inrush current on broken board designs. + help + The AXP can slowly ramp up voltage to reduce the inrush current when + changing voltages. + Note, this does not apply when enabling/disabling LDO3. See + "axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit + inrush current on broken board designs. config AXP_ALDO3_VOLT_SLOPE_NONE bool "No voltage slope" - ---help--- - Tries to reach the next voltage setting near instantaneously. Measurements - indicate that this is about 0.0167 V/uS. + help + Tries to reach the next voltage setting near instantaneously. Measurements + indicate that this is about 0.0167 V/uS. config AXP_ALDO3_VOLT_SLOPE_16 bool "1.6 mV per uS" - ---help--- - Increases the voltage by 1.6 mV per uS until the final voltage has - been reached. Note that the scaling is in 25 mV steps and thus - the slew rate in reality is about 25 mV/31.250 uS. + help + Increases the voltage by 1.6 mV per uS until the final voltage has + been reached. Note that the scaling is in 25 mV steps and thus + the slew rate in reality is about 25 mV/31.250 uS. config AXP_ALDO3_VOLT_SLOPE_08 bool "0.8 mV per uS" - ---help--- - Increases the voltage by 0.8 mV per uS until the final voltage has - been reached. Note that the scaling is in 25 mV steps however and thus - the slew rate in reality is about 25 mV/15.625 uS. - This is the slowest supported rate. + help + Increases the voltage by 0.8 mV per uS until the final voltage has + been reached. Note that the scaling is in 25 mV steps however and thus + the slew rate in reality is about 25 mV/15.625 uS. + This is the slowest supported rate. endchoice config AXP_ALDO3_INRUSH_QUIRK bool "axp pmic (a)ldo3 inrush quirk" depends on AXP209_POWER - ---help--- - The reference design denotes a value of 4.7 uF for the output capacitor - of LDO3. Some boards have too high capacitance causing an inrush current - and resulting an AXP209 shutdown. + help + The reference design denotes a value of 4.7 uF for the output capacitor + of LDO3. Some boards have too high capacitance causing an inrush current + and resulting an AXP209 shutdown. config AXP_ALDO4_VOLT int "axp pmic (a)ldo4 voltage" depends on AXP209_POWER default 0 if AXP209_POWER - ---help--- - Set the voltage (mV) to program the axp pmic aldo4 at, set to 0 to - disable aldo4. - On A10(s) / A13 / A20 boards aldo4 should be 2.8V. + help + Set the voltage (mV) to program the axp pmic aldo4 at, set to 0 to + disable aldo4. + On A10(s) / A13 / A20 boards aldo4 should be 2.8V. config AXP_DLDO1_VOLT int "axp pmic dldo1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to - disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used - to power the ethernet phy. On A23, A33 and A80 boards this is often - used to power the wifi. + help + Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to + disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used + to power the ethernet phy. On A23, A33 and A80 boards this is often + used to power the wifi. config AXP_DLDO2_VOLT int "axp pmic dldo2 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 3000 if MACH_SUN9I default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to - disable dldo2. - On A80 boards dldo2 normally powers the PL pins and should be 3.0V. + help + Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to + disable dldo2. + On A80 boards dldo2 normally powers the PL pins and should be 3.0V. config AXP_DLDO3_VOLT int "axp pmic dldo3 voltage" depends on AXP221_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to - disable dldo3. + help + Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to + disable dldo3. config AXP_DLDO4_VOLT int "axp pmic dldo4 voltage" depends on AXP221_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to - disable dldo4. + help + Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to + disable dldo4. config AXP_ELDO1_VOLT int "axp pmic eldo1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to - disable eldo1. + help + Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to + disable eldo1. config AXP_ELDO2_VOLT int "axp pmic eldo2 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to - disable eldo2. + help + Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to + disable eldo2. config AXP_ELDO3_VOLT int "axp pmic eldo3 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 3000 if MACH_SUN9I default 0 - ---help--- - Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to - disable eldo3. On some A31(s) tablets it might be used to supply - 1.2V for the SSD2828 chip (converter of parallel LCD interface - into MIPI DSI). - On A80 boards it powers the PM pingroup and should be 3.0V. + help + Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to + disable eldo3. On some A31(s) tablets it might be used to supply + 1.2V for the SSD2828 chip (converter of parallel LCD interface + into MIPI DSI). + On A80 boards it powers the PM pingroup and should be 3.0V. config AXP_FLDO1_VOLT int "axp pmic fldo1 voltage" depends on AXP818_POWER default 0 if MACH_SUN8I_A83T - ---help--- - Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to - disable fldo1. - On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is - used. + help + Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to + disable fldo1. + On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is + used. config AXP_FLDO2_VOLT int "axp pmic fldo2 voltage" depends on AXP818_POWER default 900 if MACH_SUN8I_A83T - ---help--- - Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to - disable fldo2. - On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. + help + Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to + disable fldo2. + On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. config AXP_FLDO3_VOLT int "axp pmic fldo3 voltage" depends on AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to - disable fldo3. + help + Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to + disable fldo3. config AXP_SW_ON bool "axp pmic sw on" depends on AXP809_POWER || AXP818_POWER - ---help--- - Enable to turn on axp pmic sw. + help + Enable to turn on axp pmic sw. config SY8106A_VOUT1_VOLT int "SY8106A pmic VOUT1 voltage" depends on SY8106A_POWER default 1200 - ---help--- - Set the voltage (mV) to program the SY8106A pmic VOUT1. This - is typically used to power the VDD-CPU and should be 1200mV. - Values can range from 680mV till 1950mV. + help + Set the voltage (mV) to program the SY8106A pmic VOUT1. This + is typically used to power the VDD-CPU and should be 1200mV. + Values can range from 680mV till 1950mV. config TPS6586X_POWER bool "Enable legacy driver for TI TPS6586x power management chip" @@ -467,9 +467,9 @@ config TWL4030_POWER depends on OMAP34XX bool "Enable driver for TI TWL4030 power management chip" imply CMD_POWEROFF - ---help--- - The TWL4030 in a combination audio CODEC/power management with - GPIO and it is commonly used with the OMAP3 family of processors + help + The TWL4030 in a combination audio CODEC/power management with + GPIO and it is commonly used with the OMAP3 family of processors config POWER_MT6323 bool "Poweroff driver for mediatek mt6323" diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 4112b777371..bb9c52155d2 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -35,10 +35,10 @@ config BCM6328_POWER_DOMAIN config IMX8_POWER_DOMAIN bool "Enable i.MX8 power domain driver" - depends on ARCH_IMX8 - help - Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC - requests to the SCU. + depends on ARCH_IMX8 + help + Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC + requests to the SCU. config IMX8M_POWER_DOMAIN bool "Enable i.MX8M power domain driver" diff --git a/drivers/power/domain/apple-pmgr.c b/drivers/power/domain/apple-pmgr.c index 71fedb405da..9873d3cd8db 100644 --- a/drivers/power/domain/apple-pmgr.c +++ b/drivers/power/domain/apple-pmgr.c @@ -67,7 +67,7 @@ static int apple_reset_deassert(struct reset_ctl *reset_ctl) return 0; } -struct reset_ops apple_reset_ops = { +static const struct reset_ops apple_reset_ops = { .of_xlate = apple_reset_of_xlate, .rst_assert = apple_reset_assert, .rst_deassert = apple_reset_deassert, @@ -139,7 +139,7 @@ static int apple_pmgr_probe(struct udevice *dev) return 0; } -struct power_domain_ops apple_pmgr_ops = { +static const struct power_domain_ops apple_pmgr_ops = { .on = apple_pmgr_on, .of_xlate = apple_pmgr_of_xlate, }; diff --git a/drivers/power/domain/bcm6328-power-domain.c b/drivers/power/domain/bcm6328-power-domain.c index 36b5a933748..5b449f4c29d 100644 --- a/drivers/power/domain/bcm6328-power-domain.c +++ b/drivers/power/domain/bcm6328-power-domain.c @@ -57,7 +57,7 @@ static const struct udevice_id bcm6328_power_domain_ids[] = { { /* sentinel */ } }; -struct power_domain_ops bcm6328_power_domain_ops = { +static const struct power_domain_ops bcm6328_power_domain_ops = { .off = bcm6328_power_domain_off, .on = bcm6328_power_domain_on, .request = bcm6328_power_domain_request, diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index 713a51d7807..a646f667039 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -347,7 +347,7 @@ static const struct udevice_id imx8_power_domain_ids[] = { { } }; -struct power_domain_ops imx8_power_domain_ops = { +static const struct power_domain_ops imx8_power_domain_ops = { .on = imx8_power_domain_on, .off = imx8_power_domain_off, .of_xlate = imx8_power_domain_of_xlate, diff --git a/drivers/power/domain/imx8-power-domain.c b/drivers/power/domain/imx8-power-domain.c index e8dcc057fee..5740cd686db 100644 --- a/drivers/power/domain/imx8-power-domain.c +++ b/drivers/power/domain/imx8-power-domain.c @@ -51,7 +51,7 @@ static const struct udevice_id imx8_power_domain_ids[] = { { } }; -struct power_domain_ops imx8_power_domain_ops_v2 = { +static const struct power_domain_ops imx8_power_domain_ops_v2 = { .on = imx8_power_domain_on, .off = imx8_power_domain_off, }; diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index 1c731b897cc..a3ef49aa67c 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -476,7 +476,7 @@ static int imx8m_power_domain_bind(struct udevice *dev) const char *name; int ret = 0; - ofnode_for_each_subnode(subnode, dev_ofnode(dev)) { + dev_for_each_subnode(subnode, dev) { /* Bind the subnode to this driver */ name = ofnode_get_name(subnode); @@ -531,7 +531,7 @@ static int imx8m_power_domain_of_to_plat(struct udevice *dev) struct imx_pgc_domain_data *domain_data = (struct imx_pgc_domain_data *)dev_get_driver_data(dev); - pdata->resource_id = ofnode_read_u32_default(dev_ofnode(dev), "reg", -1); + pdata->resource_id = dev_read_u32_default(dev, "reg", -1); pdata->domain = &domain_data->domains[pdata->resource_id]; pdata->regs = domain_data->pgc_regs; pdata->base = dev_read_addr_ptr(dev->parent); @@ -558,7 +558,7 @@ static const struct udevice_id imx8m_power_domain_ids[] = { { } }; -struct power_domain_ops imx8m_power_domain_ops = { +static const struct power_domain_ops imx8m_power_domain_ops = { .on = imx8m_power_domain_on, .off = imx8m_power_domain_off, .of_xlate = imx8m_power_domain_of_xlate, diff --git a/drivers/power/domain/imx8mp-mediamix.c b/drivers/power/domain/imx8mp-mediamix.c index 504c22f7d36..66ea5d8e60c 100644 --- a/drivers/power/domain/imx8mp-mediamix.c +++ b/drivers/power/domain/imx8mp-mediamix.c @@ -194,7 +194,7 @@ static const struct udevice_id imx8mp_mediamix_ids[] = { { } }; -struct power_domain_ops imx8mp_mediamix_ops = { +static const struct power_domain_ops imx8mp_mediamix_ops = { .on = imx8mp_mediamix_on, .off = imx8mp_mediamix_off, .of_xlate = imx8mp_mediamix_of_xlate, diff --git a/drivers/power/domain/meson-ee-pwrc.c b/drivers/power/domain/meson-ee-pwrc.c index 4d9f3bba644..882238f2937 100644 --- a/drivers/power/domain/meson-ee-pwrc.c +++ b/drivers/power/domain/meson-ee-pwrc.c @@ -386,7 +386,7 @@ static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain, return 0; } -struct power_domain_ops meson_ee_pwrc_ops = { +static const struct power_domain_ops meson_ee_pwrc_ops = { .off = meson_ee_pwrc_off, .on = meson_ee_pwrc_on, .of_xlate = meson_ee_pwrc_of_xlate, @@ -435,8 +435,7 @@ static const struct udevice_id meson_ee_pwrc_ids[] = { static int meson_ee_pwrc_probe(struct udevice *dev) { struct meson_ee_pwrc_priv *priv = dev_get_priv(dev); - u32 ao_phandle; - ofnode ao_node; + struct ofnode_phandle_args args; int ret; priv->data = (void *)dev_get_driver_data(dev); @@ -447,16 +446,12 @@ static int meson_ee_pwrc_probe(struct udevice *dev) if (IS_ERR(priv->regmap_hhi)) return PTR_ERR(priv->regmap_hhi); - ret = ofnode_read_u32(dev_ofnode(dev), "amlogic,ao-sysctrl", - &ao_phandle); + ret = dev_read_phandle_with_args(dev, "amlogic,ao-sysctrl", NULL, 0, 0, + &args); if (ret) return ret; - ao_node = ofnode_get_by_phandle(ao_phandle); - if (!ofnode_valid(ao_node)) - return -EINVAL; - - priv->regmap_ao = syscon_node_to_regmap(ao_node); + priv->regmap_ao = syscon_node_to_regmap(args.node); if (IS_ERR(priv->regmap_ao)) return PTR_ERR(priv->regmap_ao); diff --git a/drivers/power/domain/meson-gx-pwrc-vpu.c b/drivers/power/domain/meson-gx-pwrc-vpu.c index 1c56e8508c3..e08c0fac49a 100644 --- a/drivers/power/domain/meson-gx-pwrc-vpu.c +++ b/drivers/power/domain/meson-gx-pwrc-vpu.c @@ -262,7 +262,7 @@ static int meson_pwrc_vpu_of_xlate(struct power_domain *power_domain, return 0; } -struct power_domain_ops meson_gx_pwrc_vpu_ops = { +static const struct power_domain_ops meson_gx_pwrc_vpu_ops = { .off = meson_pwrc_vpu_off, .on = meson_pwrc_vpu_on, .of_xlate = meson_pwrc_vpu_of_xlate, @@ -283,24 +283,19 @@ static const struct udevice_id meson_gx_pwrc_vpu_ids[] = { static int meson_gx_pwrc_vpu_probe(struct udevice *dev) { struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(dev); - u32 hhi_phandle; - ofnode hhi_node; + struct ofnode_phandle_args args; int ret; priv->regmap_ao = syscon_node_to_regmap(dev_ofnode(dev_get_parent(dev))); if (IS_ERR(priv->regmap_ao)) return PTR_ERR(priv->regmap_ao); - ret = ofnode_read_u32(dev_ofnode(dev), "amlogic,hhi-sysctrl", - &hhi_phandle); + ret = dev_read_phandle_with_args(dev, "amlogic,hhi-sysctrl", NULL, 0, 0, + &args); if (ret) return ret; - hhi_node = ofnode_get_by_phandle(hhi_phandle); - if (!ofnode_valid(hhi_node)) - return -EINVAL; - - priv->regmap_hhi = syscon_node_to_regmap(hhi_node); + priv->regmap_hhi = syscon_node_to_regmap(args.node); if (IS_ERR(priv->regmap_hhi)) return PTR_ERR(priv->regmap_hhi); diff --git a/drivers/power/domain/meson-secure-pwrc.c b/drivers/power/domain/meson-secure-pwrc.c index f70f8e02423..1b82b58f3e5 100644 --- a/drivers/power/domain/meson-secure-pwrc.c +++ b/drivers/power/domain/meson-secure-pwrc.c @@ -120,7 +120,7 @@ static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { SEC_PD(RSA), }; -struct power_domain_ops meson_secure_pwrc_ops = { +static const struct power_domain_ops meson_secure_pwrc_ops = { .on = meson_secure_pwrc_on, .off = meson_secure_pwrc_off, .of_xlate = meson_secure_pwrc_of_xlate, diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c index 2d1ba1855a5..24dd540897d 100644 --- a/drivers/power/domain/mtk-power-domain.c +++ b/drivers/power/domain/mtk-power-domain.c @@ -392,7 +392,7 @@ static const struct udevice_id mtk_power_domain_ids[] = { { /* sentinel */ } }; -struct power_domain_ops mtk_power_domain_ops = { +static const struct power_domain_ops mtk_power_domain_ops = { .off = scpsys_power_off, .on = scpsys_power_on, .request = scpsys_power_request, diff --git a/drivers/power/domain/sandbox-power-domain.c b/drivers/power/domain/sandbox-power-domain.c index a8031657638..a30826a3b4d 100644 --- a/drivers/power/domain/sandbox-power-domain.c +++ b/drivers/power/domain/sandbox-power-domain.c @@ -78,7 +78,7 @@ static const struct udevice_id sandbox_power_domain_ids[] = { { } }; -struct power_domain_ops sandbox_power_domain_ops = { +static const struct power_domain_ops sandbox_power_domain_ops = { .request = sandbox_power_domain_request, .rfree = sandbox_power_domain_free, .on = sandbox_power_domain_on, diff --git a/drivers/power/domain/scmi-power-domain.c b/drivers/power/domain/scmi-power-domain.c index e8c0ba8878e..a369fe52f2f 100644 --- a/drivers/power/domain/scmi-power-domain.c +++ b/drivers/power/domain/scmi-power-domain.c @@ -165,21 +165,15 @@ static int scmi_power_domain_probe(struct udevice *dev) for (i = 0; i < priv->num_pwdoms; i++) { ret = scmi_pwd_attrs(dev, i, &priv->prop[i].attributes, &priv->prop[i].name); - if (ret) { + if (ret) dev_err(dev, "failed to get attributes pwd:%d (%d)\n", i, ret); - for (i--; i >= 0; i--) - free(priv->prop[i].name); - free(priv->prop); - - return ret; - } } return 0; } -struct power_domain_ops scmi_power_domain_ops = { +static const struct power_domain_ops scmi_power_domain_ops = { .on = scmi_power_domain_on, .off = scmi_power_domain_off, }; diff --git a/drivers/power/domain/tegra186-power-domain.c b/drivers/power/domain/tegra186-power-domain.c index 334c460c805..3865cd4cf47 100644 --- a/drivers/power/domain/tegra186-power-domain.c +++ b/drivers/power/domain/tegra186-power-domain.c @@ -55,7 +55,7 @@ static int tegra186_power_domain_off(struct power_domain *power_domain) return tegra186_power_domain_common(power_domain, false); } -struct power_domain_ops tegra186_power_domain_ops = { +static const struct power_domain_ops tegra186_power_domain_ops = { .on = tegra186_power_domain_on, .off = tegra186_power_domain_off, }; diff --git a/drivers/power/domain/zynqmp-power-domain.c b/drivers/power/domain/zynqmp-power-domain.c index a54de5c1439..0acfc54e787 100644 --- a/drivers/power/domain/zynqmp-power-domain.c +++ b/drivers/power/domain/zynqmp-power-domain.c @@ -57,7 +57,7 @@ static int zynqmp_power_domain_off(struct power_domain *power_domain) return 0; } -struct power_domain_ops zynqmp_power_domain_ops = { +static const struct power_domain_ops zynqmp_power_domain_ops = { .request = zynqmp_power_domain_request, .rfree = zynqmp_power_domain_free, .on = zynqmp_power_domain_on, diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 5bc14842e66..4bd9b4e1940 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -1,14 +1,14 @@ config DM_PMIC bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC)" depends on DM - ---help--- - This config enables the driver-model PMIC support. - UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. - For the multi-function PMIC devices, this can be used as parent I/O - device for each IC's interface. Then, each children uses its parent - for read/write. For detailed description, please refer to the files: - - 'drivers/power/pmic/pmic-uclass.c' - - 'include/power/pmic.h' + help + This config enables the driver-model PMIC support. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' if DM_PMIC @@ -16,34 +16,34 @@ config SPL_DM_PMIC bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL" depends on SPL_DM default y - ---help--- - This config enables the driver-model PMIC support in SPL. - UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. - For the multi-function PMIC devices, this can be used as parent I/O - device for each IC's interface. Then, each children uses its parent - for read/write. For detailed description, please refer to the files: - - 'drivers/power/pmic/pmic-uclass.c' - - 'include/power/pmic.h' + help + This config enables the driver-model PMIC support in SPL. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' config PMIC_CHILDREN bool "Allow child devices for PMICs" default y - ---help--- - This allows PMICs to support child devices (such as regulators) in - SPL. This adds quite a bit of code so if you are not using this - feature you can turn it off. Most likely you should turn it on for - U-Boot proper. + help + This allows PMICs to support child devices (such as regulators) in + SPL. This adds quite a bit of code so if you are not using this + feature you can turn it off. Most likely you should turn it on for + U-Boot proper. config SPL_PMIC_CHILDREN bool "Allow child devices for PMICs in SPL" depends on SPL_DM_PMIC default y - ---help--- - This allows PMICs to support child devices (such as regulators) in - SPL. This adds quite a bit of code so if you are not using this - feature you can turn it off. In this case you may need a 'back door' - to call your regulator code (e.g. see rk8xx.c for direct functions - for use in SPL). + help + This allows PMICs to support child devices (such as regulators) in + SPL. This adds quite a bit of code so if you are not using this + feature you can turn it off. In this case you may need a 'back door' + to call your regulator code (e.g. see rk8xx.c for direct functions + for use in SPL). config PMIC_AB8500 bool "Enable driver for ST-Ericsson AB8500 PMIC via PRCMU" @@ -57,11 +57,11 @@ config PMIC_AB8500 config PMIC_ACT8846 bool "Enable support for the active-semi 8846 PMIC" depends on DM_I2C - ---help--- - This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout - regulators (LDOs). It also provides some GPIO, reset and battery - functions. It uses an I2C interface and is designed for use with - tablets and smartphones. + help + This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout + regulators (LDOs). It also provides some GPIO, reset and battery + functions. It uses an I2C interface and is designed for use with + tablets and smartphones. config PMIC_AXP bool "Enable Driver Model for X-Powers AXP PMICs" @@ -101,8 +101,8 @@ config PMIC_AS3722 required for a tablets or laptop. config DM_PMIC_BD71837 - bool "Enable Driver Model for PMIC BD71837" - help + bool "Enable Driver Model for PMIC BD71837" + help This config enables implementation of driver-model pmic uclass features for PMIC BD71837. The driver implements read/write operations. @@ -173,257 +173,257 @@ config SPL_DM_PMIC_PCA9450 config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC PFUZE100. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC PFUZE100. The driver implements read/write operations. config SPL_DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100 in SPL" depends on SPL_DM_PMIC - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC PFUZE100 in SPL. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC PFUZE100 in SPL. The driver implements read/write operations. config DM_PMIC_MAX8907 bool "Enable Driver Model for PMIC MAX8907" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX8907. The driver implements read/write operations. - This is a Power Management IC with a decent set of peripherals from which - 3 DC-to-DC Step-Down (SD) Regulators, 20 Low-Dropout Linear (LDO) Regulators, - Real-Time Clock (RTC) and more with I2C Compatible Interface. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8907. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 3 DC-to-DC Step-Down (SD) Regulators, 20 Low-Dropout Linear (LDO) Regulators, + Real-Time Clock (RTC) and more with I2C Compatible Interface. config DM_PMIC_MAX77663 bool "Enable Driver Model for PMIC MAX77663" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX77663. The driver implements read/write operations. - This is a Power Management IC with a decent set of peripherals from which - 4 DC-to-DC Step-Down (SD) Regulators, 9 Low-Dropout Linear (LDO) Regulators, - 8 GPIOs, Real-Time Clock (RTC) and more with I2C Compatible Interface. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX77663. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 4 DC-to-DC Step-Down (SD) Regulators, 9 Low-Dropout Linear (LDO) Regulators, + 8 GPIOs, Real-Time Clock (RTC) and more with I2C Compatible Interface. config DM_PMIC_MAX77686 bool "Enable Driver Model for PMIC MAX77686" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX77686. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX77686. The driver implements read/write operations. config DM_PMIC_MAX8998 bool "Enable Driver Model for PMIC MAX8998" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX8998. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8998. The driver implements read/write operations. config DM_PMIC_MC34708 bool "Enable Driver Model for PMIC MC34708" help - This config enables implementation of driver-model pmic uclass features - for PMIC MC34708. The driver implements read/write operations. + This config enables implementation of driver-model pmic uclass features + for PMIC MC34708. The driver implements read/write operations. config PMIC_MAX8997 bool "Enable Driver Model for PMIC MAX8997" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX8997. The driver implements read/write operations. - This is a Power Management IC with RTC, Fuel Gauge, MUIC control on Chip. - - 21x LDOs - - 12x GPIOs - - Haptic motor driver - - RTC with two alarms - - Fuel Gauge and one backup battery charger - - MUIC - - Others + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8997. The driver implements read/write operations. + This is a Power Management IC with RTC, Fuel Gauge, MUIC control on Chip. + - 21x LDOs + - 12x GPIOs + - Haptic motor driver + - RTC with two alarms + - Fuel Gauge and one backup battery charger + - MUIC + - Others config PMIC_QCOM bool "Enable Driver Model for Qualcomm generic PMIC" - ---help--- - The Qcom PMIC is connected to one (or several) processors - with SPMI bus. It has 2 slaves with several peripherals: - - 18x LDO - - 4x GPIO - - Power and Reset buttons - - Watchdog - - RTC - - Vibrator drivers - - Others + help + The Qcom PMIC is connected to one (or several) processors + with SPMI bus. It has 2 slaves with several peripherals: + - 18x LDO + - 4x GPIO + - Power and Reset buttons + - Watchdog + - RTC + - Vibrator drivers + - Others - Driver binding info: doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt + Driver binding info: doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt config PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX" select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF - ---help--- - The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, - an RTC and two low Rds (resistance (drain to source)) switches. It is - accessed via an I2C interface. The device is used with Rockchip SoCs. - This driver implements register read/write operations. + help + The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, + an RTC and two low Rds (resistance (drain to source)) switches. It is + accessed via an I2C interface. The device is used with Rockchip SoCs. + This driver implements register read/write operations. config SPL_PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX in SPL" depends on SPL_DM_PMIC - ---help--- - The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, - an RTC and two low Rds (resistance (drain to source)) switches. It is - accessed via an I2C interface. The device is used with Rockchip SoCs. - This driver implements register read/write operations. + help + The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, + an RTC and two low Rds (resistance (drain to source)) switches. It is + accessed via an I2C interface. The device is used with Rockchip SoCs. + This driver implements register read/write operations. config PMIC_S2MPS11 bool "Enable Driver Model for PMIC Samsung S2MPS11" - ---help--- - The Samsung S2MPS11 PMIC provides: - - 38 adjustable LDO regulators - - 9 High-Efficiency Buck Converters - - 1 BuckBoost Converter - - RTC with two alarms - - Backup battery charger - - I2C Configuration Interface - This driver provides access to I/O interface only. - Binding info: doc/device-tree-bindings/pmic/s2mps11.txt + help + The Samsung S2MPS11 PMIC provides: + - 38 adjustable LDO regulators + - 9 High-Efficiency Buck Converters + - 1 BuckBoost Converter + - RTC with two alarms + - Backup battery charger + - I2C Configuration Interface + This driver provides access to I/O interface only. + Binding info: doc/device-tree-bindings/pmic/s2mps11.txt config DM_PMIC_SANDBOX bool "Enable Driver Model for emulated Sandbox PMIC" - ---help--- - Enable the driver for Sandbox PMIC emulation. The emulated PMIC device - depends on two drivers: - - sandbox PMIC I/O driver - implements dm pmic operations - - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission + help + Enable the driver for Sandbox PMIC emulation. The emulated PMIC device + depends on two drivers: + - sandbox PMIC I/O driver - implements dm pmic operations + - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission - A detailed information can be found in header: '<power/sandbox_pmic.h>' + A detailed information can be found in header: '<power/sandbox_pmic.h>' - The Sandbox PMIC info: - * I/O interface: - - I2C chip address: 0x40 - - first register address: 0x0 - - register count: 0x10 - * Adjustable outputs: - - 2x LDO - - 2x BUCK - - Each, with a different operating conditions (header). - * Reset values: - - set by i2c emul driver's probe() (defaults in header) + The Sandbox PMIC info: + * I/O interface: + - I2C chip address: 0x40 + - first register address: 0x0 + - register count: 0x10 + * Adjustable outputs: + - 2x LDO + - 2x BUCK + - Each, with a different operating conditions (header). + * Reset values: + - set by i2c emul driver's probe() (defaults in header) - Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt + Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt config DM_PMIC_CPCAP bool "Enable Driver Model for Motorola CPCAP" help - The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC - whose main purpose is power control. It was used in a wide variety of - Motorola products, both Tegra and OMAP based. The most notable devices - using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2. - Unlike most PMICs, this one is not I2C based; it uses the SPI bus. The - core driver provides both read and write access to the device registers. + The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC + whose main purpose is power control. It was used in a wide variety of + Motorola products, both Tegra and OMAP based. The most notable devices + using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2. + Unlike most PMICs, this one is not I2C based; it uses the SPI bus. The + core driver provides both read and write access to the device registers. config PMIC_S5M8767 bool "Enable Driver Model for the Samsung S5M8767 PMIC" - ---help--- - The S5M8767 PMIC provides a large array of LDOs and BUCKs for use - as a SoC power controller. It also provides 32KHz clock outputs. This - driver provides basic register access and sets up the attached - regulators if regulator support is enabled. + help + The S5M8767 PMIC provides a large array of LDOs and BUCKs for use + as a SoC power controller. It also provides 32KHz clock outputs. This + driver provides basic register access and sets up the attached + regulators if regulator support is enabled. config PMIC_RN5T567 bool "Enable driver for Ricoh RN5T567 PMIC" - ---help--- - The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO - regulators Real-Time Clock and 4 GPIOs. This driver provides - register access only. + help + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. config SPL_PMIC_RN5T567 bool "Enable driver for Ricoh RN5T567 PMIC in SPL" depends on SPL_DM_PMIC - ---help--- - The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO - regulators Real-Time Clock and 4 GPIOs. This driver provides - register access only. + help + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" - ---help--- - The TPS65090 is a PMIC containing several LDOs, DC to DC convertors, - FETs and a battery charger. This driver provides register access - only, and you can enable the regulator/charger drivers separately if - required. + help + The TPS65090 is a PMIC containing several LDOs, DC to DC convertors, + FETs and a battery charger. This driver provides register access + only, and you can enable the regulator/charger drivers separately if + required. config PMIC_PALMAS bool "Enable driver for Texas Instruments PALMAS PMIC" - ---help--- - The PALMAS is a PMIC containing several LDOs, SMPS. - This driver binds the pmic children. + help + The PALMAS is a PMIC containing several LDOs, SMPS. + This driver binds the pmic children. config PMIC_LP873X bool "Enable driver for Texas Instruments LP873X PMIC" - ---help--- - The LP873X is a PMIC containing couple of LDOs and couple of SMPS. - This driver binds the pmic children. + help + The LP873X is a PMIC containing couple of LDOs and couple of SMPS. + This driver binds the pmic children. config PMIC_LP87565 bool "Enable driver for Texas Instruments LP87565 PMIC" - ---help--- - The LP87565 is a PMIC containing a bunch of SMPS. - This driver binds the pmic children. + help + The LP87565 is a PMIC containing a bunch of SMPS. + This driver binds the pmic children. config DM_PMIC_TPS65910 bool "Enable driver for Texas Instruments TPS65910 PMIC" - ---help--- - The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost - DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO - pmic children. + help + The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost + DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO + pmic children. config DM_PMIC_TPS80031 bool "Enable driver for Texas Instruments TPS80031/TPS80032 PMIC" - ---help--- - This config enables implementation of driver-model pmic uclass features - for TPS80031/TPS80032 PMICs. The driver implements read/write operations. - This is a Power Management IC with a decent set of peripherals from which - 5 Buck Converters refered as Switched-mode power supply (SMPS), 11 General- - Purpose Low-Dropout Voltage Regulators (LDO), USB OTG Module, Real-Time - Clock (RTC) with Timer and Alarm Wake-Up, Two Digital PWM Outputs and more - with I2C Compatible Interface. PMIC occupies 4 I2C addresses. + help + This config enables implementation of driver-model pmic uclass features + for TPS80031/TPS80032 PMICs. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 5 Buck Converters referred as Switched-mode power supply (SMPS), 11 General- + Purpose Low-Dropout Voltage Regulators (LDO), USB OTG Module, Real-Time + Clock (RTC) with Timer and Alarm Wake-Up, Two Digital PWM Outputs and more + with I2C Compatible Interface. PMIC occupies 4 I2C addresses. config PMIC_STPMIC1 bool "Enable support for STMicroelectronics STPMIC1 PMIC" depends on DM_I2C select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF && !ARM_PSCI_FW - ---help--- - The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. - It is accessed via an I2C interface. The device is used with STM32MP1 - SoCs. This driver implements register read/write operations. + help + The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. + It is accessed via an I2C interface. The device is used with STM32MP1 + SoCs. This driver implements register read/write operations. config SPL_PMIC_PALMAS bool "Enable driver for Texas Instruments PALMAS PMIC" depends on SPL_DM_PMIC help - The PALMAS is a PMIC containing several LDOs, SMPS. - This driver binds the pmic children in SPL. + The PALMAS is a PMIC containing several LDOs, SMPS. + This driver binds the pmic children in SPL. config SPL_PMIC_LP873X bool "Enable driver for Texas Instruments LP873X PMIC" depends on SPL_DM_PMIC help - The LP873X is a PMIC containing couple of LDOs and couple of SMPS. - This driver binds the pmic children in SPL. + The LP873X is a PMIC containing couple of LDOs and couple of SMPS. + This driver binds the pmic children in SPL. config SPL_PMIC_LP87565 bool "Enable driver for Texas Instruments LP87565 PMIC" depends on SPL_DM_PMIC help - The LP87565 is a PMIC containing a bunch of SMPS. - This driver binds the pmic children in SPL. + The LP87565 is a PMIC containing a bunch of SMPS. + This driver binds the pmic children in SPL. config PMIC_TPS65941 bool "Enable driver for Texas Instruments TPS65941 PMIC" depends on DM_PMIC help - The TPS65941 is a PMIC containing a bunch of SMPS & LDOs. - This driver binds the pmic children. + The TPS65941 is a PMIC containing a bunch of SMPS & LDOs. + This driver binds the pmic children. config PMIC_TPS65219 bool "Enable driver for Texas Instruments TPS65219 PMIC" depends on DM_PMIC help - The TPS65219 is a PMIC containing a bunch of SMPS & LDOs. - This driver binds the pmic children. + The TPS65219 is a PMIC containing a bunch of SMPS & LDOs. + This driver binds the pmic children. config PMIC_RAA215300 bool "Renesas RAA215300 PMIC driver" @@ -445,11 +445,11 @@ endif config PMIC_TPS65217 bool "Enable driver for Texas Instruments TPS65217 PMIC" - ---help--- - The TPS65217 is a PMIC containing several LDOs, DC to DC convertors, - FETs and a battery charger. This driver provides register access - only, and you can enable the regulator/charger drivers separately if - required. + help + The TPS65217 is a PMIC containing several LDOs, DC to DC convertors, + FETs and a battery charger. This driver provides register access + only, and you can enable the regulator/charger drivers separately if + required. config POWER_TPS65218 bool "Enable legacy driver for TPS65218 PMIC" @@ -485,9 +485,9 @@ config POWER_PFUZE3000 config POWER_MC34VR500 bool "Enable driver for Freescale MC34VR500 PMIC" - ---help--- - The MC34VR500 is used in conjunction with the FSL T1 and LS1 series - SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed - via an I2C interface. + help + The MC34VR500 is used in conjunction with the FSL T1 and LS1 series + SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed + via an I2C interface. endif diff --git a/drivers/power/pmic/i2c_pmic_emul.c b/drivers/power/pmic/i2c_pmic_emul.c index 6e81b9c3427..b5c8efd427a 100644 --- a/drivers/power/pmic/i2c_pmic_emul.c +++ b/drivers/power/pmic/i2c_pmic_emul.c @@ -146,7 +146,7 @@ static int sandbox_i2c_pmic_probe(struct udevice *emul) return 0; } -struct dm_i2c_ops sandbox_i2c_pmic_emul_ops = { +static const struct dm_i2c_ops sandbox_i2c_pmic_emul_ops = { .xfer = sandbox_i2c_pmic_xfer, }; diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index c95e6357ee8..cbe8cd05be7 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -90,7 +90,7 @@ static int pca9450_probe(struct udevice *dev) return ret; } - if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset")) + if (dev_read_bool(dev, "nxp,wdog_b-warm-reset")) reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_WARM; else reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12; diff --git a/drivers/power/pmic/pmic_qcom.c b/drivers/power/pmic/pmic_qcom.c index 92d0a95859b..4b8dcc6104c 100644 --- a/drivers/power/pmic/pmic_qcom.c +++ b/drivers/power/pmic/pmic_qcom.c @@ -72,7 +72,7 @@ static int pmic_qcom_probe(struct udevice *dev) * contains two discrete values, not a single 64-bit address. * The address is the first value. */ - ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, &priv->usid); + ret = dev_read_u32_index(dev, "reg", 0, &priv->usid); if (ret < 0) return -EINVAL; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index ca5de5b8726..3b3ed97eb9f 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -1,38 +1,38 @@ config DM_REGULATOR bool "Enable Driver Model for REGULATOR drivers (UCLASS_REGULATOR)" depends on DM - ---help--- - This config enables the driver model regulator support. - UCLASS_REGULATOR - designed to provide a common API for basic regulator's - functions, like get/set Voltage or Current value, enable state, etc... - Note: - When enabling this, please read the description, found in the files: - - 'include/power/pmic.h' - - 'include/power/regulator.h' - - 'drivers/power/pmic/pmic-uclass.c' - - 'drivers/power/pmic/regulator-uclass.c' - It's important to call the device_bind() with the proper node offset, - when binding the regulator devices. The pmic_bind_childs() can be used - for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_dev() - otherwise. Detailed information can be found in the header file. + help + This config enables the driver model regulator support. + UCLASS_REGULATOR - designed to provide a common API for basic regulator's + functions, like get/set Voltage or Current value, enable state, etc... + Note: + When enabling this, please read the description, found in the files: + - 'include/power/pmic.h' + - 'include/power/regulator.h' + - 'drivers/power/pmic/pmic-uclass.c' + - 'drivers/power/pmic/regulator-uclass.c' + It's important to call the device_bind() with the proper node offset, + when binding the regulator devices. The pmic_bind_childs() can be used + for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_dev() + otherwise. Detailed information can be found in the header file. config SPL_DM_REGULATOR bool "Enable regulators for SPL" depends on DM_REGULATOR && SPL_POWER - ---help--- - Regulators are seldom needed in SPL. Even if they are accessed, some - code space can be saved by accessing the PMIC registers directly. - Enable this option if you need regulators in SPL and can cope with - the extra code size. + help + Regulators are seldom needed in SPL. Even if they are accessed, some + code space can be saved by accessing the PMIC registers directly. + Enable this option if you need regulators in SPL and can cope with + the extra code size. config REGULATOR_ACT8846 bool "Enable driver for ACT8846 regulator" depends on DM_REGULATOR && PMIC_ACT8846 - ---help--- - Enable support for the regulator functions of the ACT8846 PMIC. The - driver implements get/set api for the various BUCKS and LDOS supported - by the PMIC device. This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the regulator functions of the ACT8846 PMIC. The + driver implements get/set api for the various BUCKS and LDOS supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. config REGULATOR_AS3722 bool "Enable driver for AS7322 regulator" @@ -75,33 +75,33 @@ config DM_REGULATOR_BD71837 bool "Enable Driver Model for ROHM BD71837/BD71847 regulators" depends on DM_REGULATOR && DM_PMIC_BD71837 help - This config enables implementation of driver-model regulator uclass - features for regulators on ROHM BD71837 and BD71847 PMICs. - BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version - containing 6 bucks and 6 LDOs. The driver implements get/set api for - value and enable. + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM BD71837 and BD71847 PMICs. + BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version + containing 6 bucks and 6 LDOs. The driver implements get/set api for + value and enable. config SPL_DM_REGULATOR_BD71837 bool "Enable Driver Model for ROHM BD71837/BD71847 regulators in SPL" depends on DM_REGULATOR_BD71837 && SPL help - This config enables implementation of driver-model regulator uclass - features for regulators on ROHM BD71837 and BD71847 in SPL. + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM BD71837 and BD71847 in SPL. config DM_REGULATOR_PCA9450 bool "Enable Driver Model for NXP PCA9450 regulators" depends on DM_REGULATOR && DM_PMIC_PCA9450 help - This config enables implementation of driver-model regulator uclass - features for regulators on NXP PCA9450 PMICs. PCA9450 contains 6 bucks - and 5 LDOS. The driver implements get/set api for value and enable. + This config enables implementation of driver-model regulator uclass + features for regulators on NXP PCA9450 PMICs. PCA9450 contains 6 bucks + and 5 LDOS. The driver implements get/set api for value and enable. config SPL_DM_REGULATOR_PCA9450 bool "Enable Driver Model for NXP PCA9450 regulators in SPL" depends on DM_REGULATOR_PCA9450 && SPL help - This config enables implementation of driver-model regulator uclass - features for regulators on ROHM PCA9450 in SPL. + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM PCA9450 in SPL. config DM_REGULATOR_DA9063 bool "Enable Driver Model for REGULATOR DA9063" @@ -127,55 +127,55 @@ config DM_REGULATOR_PFUZE100 bool "Enable Driver Model for REGULATOR PFUZE100" depends on DM_REGULATOR && DM_PMIC_PFUZE100 default DM_PMIC_PFUZE100 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR PFUZE100. The driver implements get/set api for: - value, enable and mode. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR PFUZE100. The driver implements get/set api for: + value, enable and mode. config SPL_DM_REGULATOR_PFUZE100 bool "Enable Driver Model for REGULATOR PFUZE100 in SPL" depends on SPL_DM_REGULATOR && SPL_DM_PMIC_PFUZE100 default SPL_DM_PMIC_PFUZE100 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR PFUZE100. The driver implements get/set api for: - value, enable and mode. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR PFUZE100. The driver implements get/set api for: + value, enable and mode. config REGULATOR_PWM bool "Enable driver for PWM regulators" depends on DM_REGULATOR && DM_PWM - ---help--- - Enable support for the PWM regulator functions which voltage are - controlled by PWM duty ratio. Some of Rockchip board using this kind - of regulator. The driver implements get/set api for the various BUCKS. - This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the PWM regulator functions which voltage are + controlled by PWM duty ratio. Some of Rockchip board using this kind + of regulator. The driver implements get/set api for the various BUCKS. + This driver is controlled by a device tree node + which includes voltage limits. config DM_REGULATOR_MAX8907 bool "Enable Driver Model for REGULATOR MAX8907" depends on DM_REGULATOR && DM_PMIC_MAX8907 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR MAX8907. The driver supports both DC-to-DC - Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators - found in MAX8907 PMIC and implements get/set api for value and enable. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX8907. The driver supports both DC-to-DC + Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators + found in MAX8907 PMIC and implements get/set api for value and enable. config DM_REGULATOR_MAX77663 bool "Enable Driver Model for REGULATOR MAX77663" depends on DM_REGULATOR && DM_PMIC_MAX77663 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR MAX77663. The driver supports both DC-to-DC - Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators - found in MAX77663 PMIC and implements get/set api for value and enable. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX77663. The driver supports both DC-to-DC + Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators + found in MAX77663 PMIC and implements get/set api for value and enable. config DM_REGULATOR_MAX77686 bool "Enable Driver Model for REGULATOR MAX77686" depends on DM_REGULATOR && DM_PMIC_MAX77686 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR MAX77686. The driver implements get/set api for: - value, enable and mode. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX77686. The driver implements get/set api for: + value, enable and mode. config DM_REGULATOR_NPCM8XX bool "Enable Driver Model for NPCM8xx voltage supply" @@ -221,33 +221,33 @@ config DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value" depends on DM_REGULATOR select DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for fixed value regulators. The driver implements get/set api - for enable and get only for voltage value. + help + This config enables implementation of driver-model regulator uclass + features for fixed value regulators. The driver implements get/set api + for enable and get only for voltage value. config SPL_DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value in SPL" depends on DM_REGULATOR_FIXED && SPL select SPL_DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for fixed value regulators in SPL. + help + This config enables implementation of driver-model regulator uclass + features for fixed value regulators in SPL. config DM_REGULATOR_GPIO bool "Enable Driver Model for GPIO REGULATOR" depends on DM_REGULATOR && DM_GPIO select DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for gpio regulators. The driver implements get/set for - voltage value. + help + This config enables implementation of driver-model regulator uclass + features for gpio regulators. The driver implements get/set for + voltage value. config DM_REGULATOR_QCOM_RPMH bool "Enable driver model for Qualcomm RPMh regulator" depends on DM_REGULATOR && QCOM_RPMH select DEVRES - ---help--- + help Enable support for the Qualcomm RPMh regulator. The driver implements get/set api for a limited set of regulators used by u-boot. @@ -255,7 +255,7 @@ config DM_REGULATOR_QCOM_RPMH config DM_REGULATOR_QCOM_USB_VBUS bool "Enable driver model for Qualcomm USB vbus regulator" depends on DM_REGULATOR && DM_PMIC - ---help--- + help Enable support for the Qualcomm USB Vbus regulator. The driver implements get/set api for the regulator to be used by u-boot. @@ -263,18 +263,18 @@ config SPL_DM_REGULATOR_GPIO bool "Enable Driver Model for GPIO REGULATOR in SPL" depends on DM_REGULATOR_GPIO && SPL_DM_GPIO select SPL_DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for gpio regulators in SPL. + help + This config enables implementation of driver-model regulator uclass + features for gpio regulators in SPL. config REGULATOR_RK8XX bool "Enable driver for RK8XX regulators" depends on DM_REGULATOR && PMIC_RK8XX - ---help--- - Enable support for the regulator functions of the RK8XX PMIC. The - driver implements get/set api for the various BUCKS and LDOs supported - by the PMIC device. This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the regulator functions of the RK8XX PMIC. The + driver implements get/set api for the various BUCKS and LDOs supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. config SPL_REGULATOR_RK8XX bool "Enable driver for RK8XX regulators in SPL" @@ -288,162 +288,162 @@ config SPL_REGULATOR_RK8XX config DM_REGULATOR_S2MPS11 bool "Enable driver for S2MPS11 regulator" depends on DM_REGULATOR && PMIC_S2MPS11 - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR S2MPS11. - The driver implements get/set api for: value and enable. + help + This enables implementation of driver-model regulator uclass + features for REGULATOR S2MPS11. + The driver implements get/set api for: value and enable. config REGULATOR_S5M8767 bool "Enable support for S5M8767 regulator" depends on DM_REGULATOR && PMIC_S5M8767 - ---help--- - This enables the regulator features of the S5M8767, allowing voltages - to be set, etc. The driver is not fully complete but supports most - common requirements, including all LDOs and BUCKs. This allows many - supplies to be set automatically using the device tree values. + help + This enables the regulator features of the S5M8767, allowing voltages + to be set, etc. The driver is not fully complete but supports most + common requirements, including all LDOs and BUCKs. This allows many + supplies to be set automatically using the device tree values. config DM_REGULATOR_SANDBOX bool "Enable Driver Model for Sandbox PMIC regulator" depends on DM_REGULATOR && DM_PMIC_SANDBOX - ---help--- - Enable the regulator driver for emulated Sandbox PMIC. - The emulated PMIC device depends on two drivers: - - sandbox PMIC I/O driver - implements dm pmic operations - - sandbox PMIC regulator driver - implements dm regulator operations - - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission + help + Enable the regulator driver for emulated Sandbox PMIC. + The emulated PMIC device depends on two drivers: + - sandbox PMIC I/O driver - implements dm pmic operations + - sandbox PMIC regulator driver - implements dm regulator operations + - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission - The regulator driver provides uclass operations for sandbox PMIC's - regulators. The driver implements get/set api for: voltage, current, - operation mode and enable state. - The driver supports LDO and BUCK regulators. + The regulator driver provides uclass operations for sandbox PMIC's + regulators. The driver implements get/set api for: voltage, current, + operation mode and enable state. + The driver supports LDO and BUCK regulators. - The Sandbox PMIC info: - * I/O interface: - - I2C chip address: 0x40 - - first register address: 0x0 - - register count: 0x10 - * Adjustable outputs: - - 2x LDO - - 2x BUCK - - Each, with a different operating conditions (header). - * Reset values: - - set by i2c emul driver's probe() (defaults in header) + The Sandbox PMIC info: + * I/O interface: + - I2C chip address: 0x40 + - first register address: 0x0 + - register count: 0x10 + * Adjustable outputs: + - 2x LDO + - 2x BUCK + - Each, with a different operating conditions (header). + * Reset values: + - set by i2c emul driver's probe() (defaults in header) - A detailed information can be found in header: '<power/sandbox_pmic.h>' - Binding info: 'doc/device-tree-bindings/pmic/max77686.txt' + A detailed information can be found in header: '<power/sandbox_pmic.h>' + Binding info: 'doc/device-tree-bindings/pmic/max77686.txt' config REGULATOR_TPS65090 bool "Enable driver for TPS65090 PMIC regulators" depends on PMIC_TPS65090 - ---help--- - The TPS65090 provides several FETs (Field-effect Transistors, - effectively switches) which are supported by this driver as - regulators, one for each FET. The standard regulator interface is - supported, but it is only possible to turn the regulators on or off. - There is no voltage/current control. + help + The TPS65090 provides several FETs (Field-effect Transistors, + effectively switches) which are supported by this driver as + regulators, one for each FET. The standard regulator interface is + supported, but it is only possible to turn the regulators on or off. + There is no voltage/current control. config DM_REGULATOR_PALMAS bool "Enable driver for PALMAS PMIC regulators" - depends on PMIC_PALMAS - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR PALMAS and the family of PALMAS PMICs. - The driver implements get/set api for: value and enable. + depends on PMIC_PALMAS + help + This enables implementation of driver-model regulator uclass + features for REGULATOR PALMAS and the family of PALMAS PMICs. + The driver implements get/set api for: value and enable. config DM_REGULATOR_PBIAS bool "Enable driver for PBIAS regulator" depends on DM_REGULATOR select REGMAP select SYSCON - ---help--- - This enables implementation of driver-model regulator uclass - features for pseudo-regulator PBIAS found in the OMAP SOCs. - This pseudo-regulator is used to provide a BIAS voltage to MMC1 - signal pads and must be configured properly during a voltage switch. - Voltage switching is required by some operating modes of SDcards and - eMMC. + help + This enables implementation of driver-model regulator uclass + features for pseudo-regulator PBIAS found in the OMAP SOCs. + This pseudo-regulator is used to provide a BIAS voltage to MMC1 + signal pads and must be configured properly during a voltage switch. + Voltage switching is required by some operating modes of SDcards and + eMMC. config DM_REGULATOR_LP873X bool "Enable driver for LP873X PMIC regulators" - depends on PMIC_LP873X - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR LP873X and the family of LP873X PMICs. - The driver implements get/set api for: value and enable. + depends on PMIC_LP873X + help + This enables implementation of driver-model regulator uclass + features for REGULATOR LP873X and the family of LP873X PMICs. + The driver implements get/set api for: value and enable. config DM_REGULATOR_LP87565 bool "Enable driver for LP87565 PMIC regulators" - depends on PMIC_LP87565 - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR LP87565 and the family of LP87565 PMICs. - LP87565 series of PMICs have 4 single phase BUCKs that can also - be configured in multi phase modes. The driver implements - get/set api for value and enable. + depends on PMIC_LP87565 + help + This enables implementation of driver-model regulator uclass + features for REGULATOR LP87565 and the family of LP87565 PMICs. + LP87565 series of PMICs have 4 single phase BUCKs that can also + be configured in multi phase modes. The driver implements + get/set api for value and enable. config DM_REGULATOR_STM32_VREFBUF bool "Enable driver for STMicroelectronics STM32 VREFBUF" depends on DM_REGULATOR && (STM32H7 || ARCH_STM32MP) help - This driver supports STMicroelectronics STM32 VREFBUF (voltage - reference buffer) which can be used as voltage reference for - internal ADCs, DACs and also for external components through - dedicated Vref+ pin. + This driver supports STMicroelectronics STM32 VREFBUF (voltage + reference buffer) which can be used as voltage reference for + internal ADCs, DACs and also for external components through + dedicated Vref+ pin. config DM_REGULATOR_TPS65910 bool "Enable driver for TPS65910 PMIC regulators" depends on DM_PMIC_TPS65910 - ---help--- - The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all - regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements - the get/set api for value and enable. + help + The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all + regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements + the get/set api for value and enable. config DM_REGULATOR_TPS65911 bool "Enable driver for TPS65911 PMIC regulators" depends on DM_PMIC_TPS65910 - ---help--- - This config enables implementation of driver-model regulator - uclass features for the TPS65911 PMIC. The driver supports Step-Down - DC-DC Converters for Processor Cores (VDD1 and VDD2), Step-Down DC-DC - Converter for I/O Power (VIO), Controller for External FETs (VDDCtrl) - and LDO Voltage Regulators found in TPS65911 PMIC and implements - get/set api for value and enable. + help + This config enables implementation of driver-model regulator + uclass features for the TPS65911 PMIC. The driver supports Step-Down + DC-DC Converters for Processor Cores (VDD1 and VDD2), Step-Down DC-DC + Converter for I/O Power (VIO), Controller for External FETs (VDDCtrl) + and LDO Voltage Regulators found in TPS65911 PMIC and implements + get/set api for value and enable. config DM_REGULATOR_TPS62360 bool "Enable driver for TPS6236x Power Regulator" depends on DM_REGULATOR help - The TPS6236X DC/DC step down converter provides a single output - power line peaking at 3A current. This driver supports all four - variants of the chip (TPS62360, TPS62361, TPS62362, TPS62363). It - implements the get/set api for value only, as the power line is - always on. + The TPS6236X DC/DC step down converter provides a single output + power line peaking at 3A current. This driver supports all four + variants of the chip (TPS62360, TPS62361, TPS62362, TPS62363). It + implements the get/set api for value only, as the power line is + always on. config DM_REGULATOR_TPS80031 bool "Enable driver for TPS80031/TPS80032 PMIC regulators" depends on DM_PMIC_TPS80031 - ---help--- - This enables implementation of driver-model regulator uclass - features for TPS80031/TPS80032 PMICs. The driver implements - get/set api for: value and enable. + help + This enables implementation of driver-model regulator uclass + features for TPS80031/TPS80032 PMICs. The driver implements + get/set api for: value and enable. config DM_REGULATOR_TPS6287X bool "Enable driver for TPS6287x Power Regulator" depends on DM_REGULATOR help - The TPS6287X is a step down converter with a fast transient - response. This driver supports all four variants of the chip - (TPS62870, TPS62871, TPS62872, TPS62873). It implements the - get/set api for value only, as the power line is always on. + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. config DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators" depends on DM_REGULATOR && PMIC_STPMIC1 - ---help--- - Enable support for the regulator functions of the STPMIC1 PMIC. The - driver implements get/set api for the various BUCKS and LDOs supported - by the PMIC device. This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the regulator functions of the STPMIC1 PMIC. The + driver implements get/set api for the various BUCKS and LDOs supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. config DM_REGULATOR_ANATOP bool "Enable driver for ANATOP regulators" @@ -451,18 +451,18 @@ config DM_REGULATOR_ANATOP select REGMAP select SYSCON help - Enable support for the Freescale i.MX on-chip ANATOP LDO - regulators. It is recommended that this option be enabled on - i.MX6 platform. + Enable support for the Freescale i.MX on-chip ANATOP LDO + regulators. It is recommended that this option be enabled on + i.MX6 platform. config SPL_DM_REGULATOR_TPS6287X bool "Enable driver for TPS6287x Power Regulator" depends on SPL_DM_REGULATOR help - The TPS6287X is a step down converter with a fast transient - response. This driver supports all four variants of the chip - (TPS62870, TPS62871, TPS62872, TPS62873). It implements the - get/set api for value only, as the power line is always on. + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. config SPL_DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators in SPL" @@ -474,54 +474,54 @@ config SPL_DM_REGULATOR_PALMAS bool "Enable driver for PALMAS PMIC regulators" depends on SPL_PMIC_PALMAS help - This enables implementation of driver-model regulator uclass - features for REGULATOR PALMAS and the family of PALMAS PMICs. - The driver implements get/set api for: value and enable in SPL. + This enables implementation of driver-model regulator uclass + features for REGULATOR PALMAS and the family of PALMAS PMICs. + The driver implements get/set api for: value and enable in SPL. config SPL_DM_REGULATOR_LP87565 bool "Enable driver for LP87565 PMIC regulators" depends on SPL_PMIC_LP87565 help - This enables implementation of driver-model regulator uclass - features for REGULATOR LP87565 and the family of LP87565 PMICs. - LP87565 series of PMICs have 4 single phase BUCKs that can also - be configured in multi phase modes. The driver implements - get/set api for value and enable in SPL. + This enables implementation of driver-model regulator uclass + features for REGULATOR LP87565 and the family of LP87565 PMICs. + LP87565 series of PMICs have 4 single phase BUCKs that can also + be configured in multi phase modes. The driver implements + get/set api for value and enable in SPL. config SPL_DM_REGULATOR_LP873X bool "Enable driver for LP873X PMIC regulators" depends on SPL_PMIC_LP873X help - This enables implementation of driver-model regulator uclass - features for REGULATOR LP873X and the family of LP873X PMICs. - The driver implements get/set api for: value and enable in SPL. + This enables implementation of driver-model regulator uclass + features for REGULATOR LP873X and the family of LP873X PMICs. + The driver implements get/set api for: value and enable in SPL. config DM_REGULATOR_TPS65941 bool "Enable driver for TPS65941 PMIC regulators" - depends on PMIC_TPS65941 + depends on PMIC_TPS65941 help - This enables implementation of driver-model regulator uclass - features for REGULATOR TPS65941 and the family of TPS65941 PMICs. - TPS65941 series of PMICs have 5 single phase BUCKs that can also - be configured in multi phase modes & 4 LDOs. The driver implements - get/set api for value and enable. + This enables implementation of driver-model regulator uclass + features for REGULATOR TPS65941 and the family of TPS65941 PMICs. + TPS65941 series of PMICs have 5 single phase BUCKs that can also + be configured in multi phase modes & 4 LDOs. The driver implements + get/set api for value and enable. config DM_REGULATOR_SCMI bool "Enable driver for SCMI voltage domain regulators" depends on DM_REGULATOR select SCMI_AGENT - help - Enable this option if you want to support regulators exposed through + help + Enable this option if you want to support regulators exposed through the SCMI voltage domain protocol by a SCMI server. config DM_REGULATOR_TPS65219 bool "Enable driver for TPS65219 PMIC regulators" - depends on PMIC_TPS65219 + depends on PMIC_TPS65219 help - This enables implementation of driver-model regulator uclass - features for REGULATOR TPS65219 and the family of TPS65219 PMICs. - TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs. - The driver implements get/set api for value and enable. + This enables implementation of driver-model regulator uclass + features for REGULATOR TPS65219 and the family of TPS65219 PMICs. + TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs. + The driver implements get/set api for value and enable. config REGULATOR_RZG2L_USBPHY bool "Enable driver for RZ/G2L USB PHY VBUS supply" @@ -534,11 +534,11 @@ config REGULATOR_RZG2L_USBPHY config DM_REGULATOR_CPCAP bool "Enable driver for CPCAP PMIC regulators" depends on DM_REGULATOR && DM_PMIC_CPCAP - ---help--- - Enable implementation of driver-model regulator uclass features for - REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching - (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP - PMIC and implements get/set api for voltage and state. + help + Enable implementation of driver-model regulator uclass features for + REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching + (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP + PMIC and implements get/set api for voltage and state. config DM_REGULATOR_MT6357 bool "Enable driver for MediaTek MT6357 PMIC regulators" diff --git a/drivers/power/regulator/anatop_regulator.c b/drivers/power/regulator/anatop_regulator.c index 824a753db16..88570a1f624 100644 --- a/drivers/power/regulator/anatop_regulator.c +++ b/drivers/power/regulator/anatop_regulator.c @@ -170,8 +170,7 @@ static int anatop_regulator_probe(struct udevice *dev) anatop_reg = dev_get_plat(dev); uc_pdata = dev_get_uclass_plat(dev); - anatop_reg->name = ofnode_read_string(dev_ofnode(dev), - "regulator-name"); + anatop_reg->name = dev_read_string(dev, "regulator-name"); if (!anatop_reg->name) return log_msg_ret("regulator-name", -EINVAL); diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index 77c82a00b65..57af16cfbb9 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -550,6 +550,8 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV) return -EINVAL; } val = pmic_reg_read(dev->parent, desc->vsel_reg); + if (val < 0) + return val; if (desc->high_volt_mask && (val & desc->high_volt_mask)) { min_uV = desc->high_volt_desc->min_uV; uV_step = desc->high_volt_desc->uV_step; diff --git a/drivers/power/regulator/qcom-rpmh-regulator.c b/drivers/power/regulator/qcom-rpmh-regulator.c index f789b5b6f86..c458f227bed 100644 --- a/drivers/power/regulator/qcom-rpmh-regulator.c +++ b/drivers/power/regulator/qcom-rpmh-regulator.c @@ -5,6 +5,7 @@ #define pr_fmt(fmt) "%s: " fmt, __func__ #include <linux/err.h> +#include <dm.h> #include <dm/device_compat.h> #include <dm/device.h> #include <dm/devres.h> @@ -888,7 +889,7 @@ static int rpmh_regulator_probe(struct udevice *dev) priv->hw_data = init_data->hw_data; priv->enabled = -EINVAL; priv->uv = -ENOTRECOVERABLE; - if (ofnode_read_u32(dev_ofnode(dev), "regulator-initial-mode", &priv->mode)) + if (dev_read_u32(dev, "regulator-initial-mode", &priv->mode)) priv->mode = -EINVAL; plat_data->mode = priv->hw_data->pmic_mode_map; @@ -939,7 +940,7 @@ static int rpmh_regulators_bind(struct udevice *dev) return -ENODEV; } - pmic_id = ofnode_read_string(dev_ofnode(dev), "qcom,pmic-id"); + pmic_id = dev_read_string(dev, "qcom,pmic-id"); if (!pmic_id) { dev_err(dev, "No PMIC ID\n"); return -ENODEV; @@ -947,7 +948,7 @@ static int rpmh_regulators_bind(struct udevice *dev) drv = lists_driver_lookup_name("rpmh_regulator_drm"); - ofnode_for_each_subnode(node, dev_ofnode(dev)) { + dev_for_each_subnode(node, dev) { data = vreg_get_init_data(init_data, node); if (!data) continue; diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index 85af8d599ad..c0387eff4fc 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -87,6 +87,9 @@ int regulator_common_set_enable(const struct udevice *dev, } } + if (enable && plat->off_on_delay_us) + udelay(plat->off_on_delay_us); + ret = dm_gpio_set_value(&plat->gpio, enable); if (ret) { pr_err("Can't set regulator : %s gpio to: %d\n", dev->name, @@ -97,9 +100,6 @@ int regulator_common_set_enable(const struct udevice *dev, if (enable && plat->startup_delay_us) udelay(plat->startup_delay_us); - if (!enable && plat->off_on_delay_us) - udelay(plat->off_on_delay_us); - if (enable) plat->enable_count++; else diff --git a/drivers/power/regulator/scmi_regulator.c b/drivers/power/regulator/scmi_regulator.c index 7d2db1e2bee..aa7b4278260 100644 --- a/drivers/power/regulator/scmi_regulator.c +++ b/drivers/power/regulator/scmi_regulator.c @@ -180,7 +180,7 @@ static int scmi_regulator_bind(struct udevice *dev) ofnode node; int ret; - regul_node = ofnode_find_subnode(dev_ofnode(dev), "regulators"); + regul_node = dev_read_subnode(dev, "regulators"); if (!ofnode_valid(regul_node)) { dev_err(dev, "no regulators node\n"); return -ENXIO; diff --git a/drivers/power/regulator/tps6287x_regulator.c b/drivers/power/regulator/tps6287x_regulator.c index 6d185719199..2e6d85f677a 100644 --- a/drivers/power/regulator/tps6287x_regulator.c +++ b/drivers/power/regulator/tps6287x_regulator.c @@ -141,7 +141,7 @@ static int tps6287x_regulator_probe(struct udevice *dev) pdata->config = (void *)dev_get_driver_data(dev); - slave_id = devfdt_get_addr_index(dev, 0); + slave_id = dev_read_addr_index(dev, 0); ret = i2c_get_chip(dev->parent, slave_id, 1, &pdata->i2c); if (ret) { diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index e4918460de6..fa5c890bb7a 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -4,19 +4,19 @@ menuconfig ASPEED_RAM depends on ARCH_ASPEED || TARGET_ASPEED_AST2700_IBEX default ARCH_ASPEED help - Configuration options for DDR SDRAM on ASPEED systems. + Configuration options for DDR SDRAM on ASPEED systems. - RAM initialisation is always built in for the platform. This menu - allows customisation of the configuration used. + RAM initialisation is always built in for the platform. This menu + allows customisation of the configuration used. config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" depends on ASPEED_RAM help - Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM - SRAM controller needs to know if the memory chip mounted on the - board is dual x8 die or not, otherwise it may get the wrong - size of the memory space. + Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM + SRAM controller needs to know if the memory chip mounted on the + board is dual x8 die or not, otherwise it may get the wrong + size of the memory space. config ASPEED_BYPASS_SELFTEST depends on ASPEED_RAM @@ -77,7 +77,7 @@ choice prompt "AST2700 DDR target date rate" default ASPEED_DDR_3200 depends on ASPEED_RAM - depends on TARGET_ASPEED_AST2700_IBEX + depends on ASPEED_AST2700 || TARGET_ASPEED_AST2700_IBEX config ASPEED_DDR_1600 bool "1600 Mbps" diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile index 1f0b22c8e9f..d29e2154ce9 100644 --- a/drivers/ram/aspeed/Makefile +++ b/drivers/ram/aspeed/Makefile @@ -2,4 +2,5 @@ # obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o +obj-$(CONFIG_ASPEED_AST2700) += sdram_ast2700.o obj-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += sdram_ast2700.o diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index 55e80fba3dc..2cf9296468d 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -1076,10 +1076,10 @@ static int ast2600_sdrammc_probe(struct udevice *dev) return ret; } - priv->scu = devfdt_get_addr_ptr(clk_dev); - if (IS_ERR(priv->scu)) { + priv->scu = dev_read_addr_ptr(clk_dev); + if (!priv->scu) { debug("%s(): can't get SCU\n", __func__); - return PTR_ERR(priv->scu); + return -ENODEV; } if (readl(&priv->scu->dram_hdshk) & SCU_DRAM_HDSHK_RDY) { @@ -1136,12 +1136,11 @@ static int ast2600_sdrammc_of_to_plat(struct udevice *dev) { struct dram_info *priv = dev_get_priv(dev); - priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); - priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); - priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); + priv->regs = (void *)(uintptr_t)dev_read_addr_index(dev, 0); + priv->phy_setting = (void *)(uintptr_t)dev_read_addr_index(dev, 1); + priv->phy_status = (void *)(uintptr_t)dev_read_addr_index(dev, 2); - priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "clock-frequency", 0); + priv->clock_rate = ofnode_read_s32_default(dev_ofnode(dev), "clock-frequency", 0); if (!priv->clock_rate) { debug("DDR Clock Rate not defined\n"); return -EINVAL; diff --git a/drivers/ram/aspeed/sdram_ast2700.c b/drivers/ram/aspeed/sdram_ast2700.c index 4a019c4edb1..8605a92abb2 100644 --- a/drivers/ram/aspeed/sdram_ast2700.c +++ b/drivers/ram/aspeed/sdram_ast2700.c @@ -14,6 +14,11 @@ #include <linux/sizes.h> #include <ram.h> +__weak int fmc_hdr_get_prebuilt(u32 type, u32 *ofst, u32 *size) +{ + return -ENOSYS; +} + enum ddr_type { DDR4_1600 = 0x0, DDR4_2400, @@ -128,13 +133,13 @@ static size_t ast2700_sdrammc_get_vga_mem_size(struct sdrammc *sdrammc) reg = readl(scu0 + SCU0_PCI_MISC70); if (reg & SCU0_PCI_MISC70_EN_PCIEVGA0) { - debug("VGA0:%dMB\n", vga_memsz[sel] / SZ_1M); + debug("VGA0:%zuMB\n", vga_memsz[sel] / SZ_1M); dual++; } reg = readl(scu0 + SCU0_PCI_MISC80); if (reg & SCU0_PCI_MISC80_EN_PCIEVGA1) { - debug("VGA1:%dMB\n", vga_memsz[sel] / SZ_1M); + debug("VGA1:%zuMB\n", vga_memsz[sel] / SZ_1M); dual++; } @@ -560,7 +565,7 @@ void dwc_get_mailbox(struct sdrammc *sdrammc, const int mode, u32 *mbox) dwc_ddrphy_apb_wr(0xd0031, 1); } -uint32_t dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half) +u32 dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half) { u32 data_word; @@ -727,7 +732,7 @@ int dwc_ddrphy_phyinit_userCustom_D_loadIMEM(struct sdrammc *sdrammc, const int fmc_hdr_get_prebuilt(pb_type, &imem_ofst, &imem_size); memcpy(sdrammc->phy + (DWC_PHY_IMEM_OFST << 1), - (void *)(0x20000000 + imem_ofst), imem_size); + (void *)(uintptr_t)(0x20000000 + imem_ofst), imem_size); return 0; } @@ -746,7 +751,7 @@ int dwc_ddrphy_phyinit_userCustom_F_loadDMEM(struct sdrammc *sdrammc, fmc_hdr_get_prebuilt(pb_type, &dmem_ofst, &dmem_size); memcpy(sdrammc->phy + (DWC_PHY_DMEM_OFST << 1), - (void *)(0x20000000 + dmem_ofst), dmem_size); + (void *)(uintptr_t)(0x20000000 + dmem_ofst), dmem_size); return 0; } @@ -956,13 +961,13 @@ static int ast2700_sdrammc_of_to_plat(struct udevice *dev) ofnode node; int rc; - sdrammc->regs = (struct sdrammc_regs *)devfdt_get_addr_index(dev, 0); + sdrammc->regs = (struct sdrammc_regs *)dev_read_addr_index(dev, 0); if (sdrammc->regs == (void *)FDT_ADDR_T_NONE) { debug("cannot map DRAM register\n"); return -ENODEV; } - sdrammc->phy = (void *)devfdt_get_addr_index(dev, 1); + sdrammc->phy = (void *)dev_read_addr_index(dev, 1); if (sdrammc->phy == (void *)FDT_ADDR_T_NONE) { debug("cannot map PHY memory\n"); return -ENODEV; diff --git a/drivers/ram/octeon/Kconfig b/drivers/ram/octeon/Kconfig index f19957293f9..37bf4851400 100644 --- a/drivers/ram/octeon/Kconfig +++ b/drivers/ram/octeon/Kconfig @@ -2,14 +2,14 @@ config RAM_OCTEON bool "Ram drivers for Octeon SoCs" depends on RAM && ARCH_OCTEON help - This enables support for RAM drivers for Octeon SoCs. + This enables support for RAM drivers for Octeon SoCs. if RAM_OCTEON config RAM_OCTEON_DDR4 bool "Octeon III DDR4 RAM support" help - This enables support for DDR4 RAM suppoort for Octeon III. This does - not include support for Octeon CN70XX. + This enables support for DDR4 RAM suppoort for Octeon III. This does + not include support for Octeon CN70XX. endif # RAM_OCTEON diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig index 1aaf064c30c..76bd17a8874 100644 --- a/drivers/ram/stm32mp1/Kconfig +++ b/drivers/ram/stm32mp1/Kconfig @@ -6,43 +6,43 @@ config STM32MP1_DDR select SPL_RAM if SPL default y help - activate STM32MP1 DDR controller driver for STM32MP1 soc - family: support for LPDDR2, LPDDR3 and DDR3 - the SDRAM parameters for controleur and phy need to be provided - in device tree (computed by DDR tuning tools) + activate STM32MP1 DDR controller driver for STM32MP1 soc + family: support for LPDDR2, LPDDR3 and DDR3 + the SDRAM parameters for controleur and phy need to be provided + in device tree (computed by DDR tuning tools) config STM32MP1_DDR_INTERACTIVE bool "STM32MP1 DDR driver : interactive support" depends on STM32MP1_DDR help - activate interactive support in STM32MP1 DDR controller driver - used for DDR tuning tools - to enter in intercative mode type 'd' during SPL DDR driver - initialisation + activate interactive support in STM32MP1 DDR controller driver + used for DDR tuning tools + to enter in intercative mode type 'd' during SPL DDR driver + initialisation config STM32MP1_DDR_INTERACTIVE_FORCE bool "STM32MP1 DDR driver : force interactive mode" depends on STM32MP1_DDR_INTERACTIVE help - force interactive mode in STM32MP1 DDR controller driver - skip the polling of character 'd' in console - useful when SPL is loaded in sysram - directly by programmer + force interactive mode in STM32MP1 DDR controller driver + skip the polling of character 'd' in console + useful when SPL is loaded in sysram + directly by programmer config STM32MP1_DDR_TESTS bool "STM32MP1 DDR driver : tests support" depends on STM32MP1_DDR_INTERACTIVE default y help - activate test support for interactive support in - STM32MP1 DDR controller driver: command test + activate test support for interactive support in + STM32MP1 DDR controller driver: command test config STM32MP1_DDR_TUNING bool "STM32MP1 DDR driver : support of tuning" depends on STM32MP1_DDR_INTERACTIVE default y help - activate tuning command in STM32MP1 DDR interactive mode - used for DDR tuning tools - - DQ Deskew algorithm - - DQS Trimming + activate tuning command in STM32MP1 DDR interactive mode + used for DDR tuning tools + - DQ Deskew algorithm + - DQS Trimming diff --git a/drivers/reboot-mode/Kconfig b/drivers/reboot-mode/Kconfig index 72b33d71223..3fdb4218a8b 100644 --- a/drivers/reboot-mode/Kconfig +++ b/drivers/reboot-mode/Kconfig @@ -11,26 +11,26 @@ config DM_REBOOT_MODE depends on DM select DEVRES help - Enable support for reboot mode control. This will allow users to - adjust the boot process based on reboot mode parameter - passed to U-Boot. + Enable support for reboot mode control. This will allow users to + adjust the boot process based on reboot mode parameter + passed to U-Boot. config DM_REBOOT_MODE_GPIO bool "Use GPIOs as reboot mode backend" depends on DM_REBOOT_MODE help - Use GPIOs to control the reboot mode. This will allow users to boot - a device in a specific mode by using a GPIO that can be controlled - outside U-Boot. + Use GPIOs to control the reboot mode. This will allow users to boot + a device in a specific mode by using a GPIO that can be controlled + outside U-Boot. config DM_REBOOT_MODE_RTC bool "Use RTC as reboot mode backend" depends on DM_RTC depends on DM_REBOOT_MODE help - Use RTC non volatile memory to control the reboot mode. This will allow users to boot - a device in a specific mode by using a register(s) that can be controlled - outside U-Boot (e.g. Kernel). + Use RTC non volatile memory to control the reboot mode. This will allow users to boot + a device in a specific mode by using a register(s) that can be controlled + outside U-Boot (e.g. Kernel). config REBOOT_MODE_NVMEM bool "Use NVMEM reboot mode" diff --git a/drivers/remoteproc/ipu_rproc.c b/drivers/remoteproc/ipu_rproc.c index 2ca78b550a7..8f0b619daf7 100644 --- a/drivers/remoteproc/ipu_rproc.c +++ b/drivers/remoteproc/ipu_rproc.c @@ -695,9 +695,8 @@ static int ipu_probe(struct udevice *dev) priv = dev_get_priv(dev); priv->mem.bus_addr = - devfdt_get_addr_size_name(dev, - ipu_mem_names[0], - (fdt_addr_t *)&priv->mem.size); + dev_read_addr_size_name(dev, ipu_mem_names[0], + (fdt_addr_t *)&priv->mem.size); ret = reset_get_by_index(dev, 2, &reset); if (ret < 0) { @@ -718,7 +717,7 @@ static int ipu_probe(struct udevice *dev) priv->mem.cpu_addr = map_physmem(priv->mem.bus_addr, priv->mem.size, MAP_NOCACHE); - if (devfdt_get_addr(dev) == 0x58820000) + if (dev_read_addr(dev) == 0x58820000) priv->id = 0; else priv->id = 1; diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 9aec138637b..b0823bfd22d 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -421,19 +421,16 @@ static void pru_set_id(struct pru_privdata *priv, struct udevice *dev) static int pru_probe(struct udevice *dev) { struct pru_privdata *priv; - ofnode node; - - node = dev_ofnode(dev); priv = dev_get_priv(dev); priv->prusspriv = dev_get_priv(dev->parent); - priv->pru_iram = devfdt_get_addr_size_index(dev, PRU_MEM_IRAM, - &priv->pru_iramsz); - priv->pru_ctrl = devfdt_get_addr_size_index(dev, PRU_MEM_CTRL, - &priv->pru_ctrlsz); - priv->pru_debug = devfdt_get_addr_size_index(dev, PRU_MEM_DEBUG, - &priv->pru_debugsz); + priv->pru_iram = dev_read_addr_size_index(dev, PRU_MEM_IRAM, + &priv->pru_iramsz); + priv->pru_ctrl = dev_read_addr_size_index(dev, PRU_MEM_CTRL, + &priv->pru_ctrlsz); + priv->pru_debug = dev_read_addr_size_index(dev, PRU_MEM_DEBUG, + &priv->pru_debugsz); priv->iram_da = 0; priv->pdram_da = 0; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index e7c0870c918..c851354c7a5 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -107,6 +107,15 @@ config RESET_AST2600 Say Y if you want to control reset signals of different peripherals through System Control Unit (SCU). +config RESET_AST2700 + bool "Reset controller driver for AST2700 SoCs" + depends on DM_RESET && ASPEED_AST2700 + default y if ASPEED_AST2700 + help + Support for reset controller on AST2700 SoC. + Say Y if you want to control reset signals of different peripherals + through System Control Unit (SCU). + config RESET_ROCKCHIP bool "Reset controller driver for Rockchip SoCs" depends on DM_RESET && ARCH_ROCKCHIP && CLK diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 2c83f858895..3fce96509cd 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o +obj-$(CONFIG_RESET_AST2700) += reset-ast2700.o obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git a/drivers/reset/reset-ast2500.c b/drivers/reset/reset-ast2500.c index f3543fa8cc1..c85906bbeb5 100644 --- a/drivers/reset/reset-ast2500.c +++ b/drivers/reset/reset-ast2500.c @@ -77,10 +77,10 @@ static int ast2500_reset_probe(struct udevice *dev) return rc; } - priv->scu = devfdt_get_addr_ptr(scu_dev); + priv->scu = dev_read_addr_ptr(scu_dev); if (IS_ERR_OR_NULL(priv->scu)) { debug("%s: invalid SCU base pointer\n", __func__); - return PTR_ERR(priv->scu); + return -EINVAL; } return 0; @@ -91,7 +91,7 @@ static const struct udevice_id ast2500_reset_ids[] = { { } }; -struct reset_ops ast2500_reset_ops = { +static const struct reset_ops ast2500_reset_ops = { .rst_assert = ast2500_reset_assert, .rst_deassert = ast2500_reset_deassert, .rst_status = ast2500_reset_status, diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c index ec7b9b6625d..71b6220225a 100644 --- a/drivers/reset/reset-ast2600.c +++ b/drivers/reset/reset-ast2600.c @@ -76,10 +76,10 @@ static int ast2600_reset_probe(struct udevice *dev) return rc; } - priv->scu = devfdt_get_addr_ptr(scu_dev); + priv->scu = dev_read_addr_ptr(scu_dev); if (IS_ERR_OR_NULL(priv->scu)) { debug("%s: invalid SCU base pointer\n", __func__); - return PTR_ERR(priv->scu); + return -EINVAL; } return 0; @@ -90,7 +90,7 @@ static const struct udevice_id ast2600_reset_ids[] = { { } }; -struct reset_ops ast2600_reset_ops = { +static const struct reset_ops ast2600_reset_ops = { .rst_assert = ast2600_reset_assert, .rst_deassert = ast2600_reset_deassert, .rst_status = ast2600_reset_status, diff --git a/drivers/reset/reset-ast2700.c b/drivers/reset/reset-ast2700.c new file mode 100644 index 00000000000..2dd9e36cc0a --- /dev/null +++ b/drivers/reset/reset-ast2700.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <asm/io.h> +#include <dm.h> +#include <linux/err.h> +#include <reset.h> +#include <reset-uclass.h> + +/* Offset of the modrst register block within the SCU. */ +#define AST2700_RESET_OFFSET 0x200 + +struct ast2700_reset_priv { + void __iomem *base; +}; + +static int ast2700_reset_assert(struct reset_ctl *reset_ctl) +{ + struct ast2700_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), priv->base); + else + writel(BIT(reset_ctl->id - 32), priv->base + 0x20); + + return 0; +} + +static int ast2700_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct ast2700_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), priv->base + 0x04); + else + writel(BIT(reset_ctl->id - 32), priv->base + 0x24); + + return 0; +} + +static int ast2700_reset_status(struct reset_ctl *reset_ctl) +{ + struct ast2700_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int status; + + if (reset_ctl->id < 32) + status = BIT(reset_ctl->id) & readl(priv->base); + else + status = BIT(reset_ctl->id - 32) & readl(priv->base + 0x20); + + return !!status; +} + +static int ast2700_reset_probe(struct udevice *dev) +{ + struct ast2700_reset_priv *priv = dev_get_priv(dev); + void __iomem *scu_base; + + scu_base = dev_read_addr_ptr(dev); + if (!scu_base) + return -EINVAL; + + priv->base = scu_base + AST2700_RESET_OFFSET; + + return 0; +} + +static const struct reset_ops ast2700_reset_ops = { + .rst_assert = ast2700_reset_assert, + .rst_deassert = ast2700_reset_deassert, + .rst_status = ast2700_reset_status, +}; + +U_BOOT_DRIVER(ast2700_reset) = { + .name = "ast2700_reset", + .id = UCLASS_RESET, + .probe = ast2700_reset_probe, + .ops = &ast2700_reset_ops, + .priv_auto = sizeof(struct ast2700_reset_priv), +}; diff --git a/drivers/reset/reset-at91.c b/drivers/reset/reset-at91.c index 165c87acdc4..ebbfae1469b 100644 --- a/drivers/reset/reset-at91.c +++ b/drivers/reset/reset-at91.c @@ -79,7 +79,7 @@ static int at91_rst_deassert(struct reset_ctl *reset_ctl) return at91_rst_update(reset, reset_ctl->id, false); } -struct reset_ops at91_reset_ops = { +static const struct reset_ops at91_reset_ops = { .of_xlate = at91_reset_of_xlate, .rst_assert = at91_rst_assert, .rst_deassert = at91_rst_deassert, diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c index 6f140574216..161d00d1b0c 100644 --- a/drivers/reset/reset-bcm6345.c +++ b/drivers/reset/reset-bcm6345.c @@ -49,7 +49,7 @@ static int bcm6345_reset_request(struct reset_ctl *rst) return bcm6345_reset_assert(rst); } -struct reset_ops bcm6345_reset_reset_ops = { +static const struct reset_ops bcm6345_reset_reset_ops = { .request = bcm6345_reset_request, .rst_assert = bcm6345_reset_assert, .rst_deassert = bcm6345_reset_deassert, diff --git a/drivers/reset/reset-dra7.c b/drivers/reset/reset-dra7.c index 2f0ec4c042f..6b570d87d23 100644 --- a/drivers/reset/reset-dra7.c +++ b/drivers/reset/reset-dra7.c @@ -51,7 +51,7 @@ static int dra7_reset_assert(struct reset_ctl *reset_ctl) return 0; } -struct reset_ops dra7_reset_ops = { +static const struct reset_ops dra7_reset_ops = { .rst_assert = dra7_reset_assert, .rst_deassert = dra7_reset_deassert, }; diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c index 4b3afab92ea..66bcf7c29b6 100644 --- a/drivers/reset/reset-mediatek.c +++ b/drivers/reset/reset-mediatek.c @@ -47,7 +47,7 @@ static int mediatek_reset_deassert(struct reset_ctl *reset_ctl) priv->regofs + ((id / 32) << 2), BIT(id % 32), 0); } -struct reset_ops mediatek_reset_ops = { +static const struct reset_ops mediatek_reset_ops = { .rst_assert = mediatek_reset_assert, .rst_deassert = mediatek_reset_deassert, }; diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 6337cdaaffa..8c27563ce23 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -66,7 +66,7 @@ static int meson_reset_deassert(struct reset_ctl *reset_ctl) return meson_reset_level(reset_ctl, false); } -struct reset_ops meson_reset_ops = { +static const struct reset_ops meson_reset_ops = { .request = meson_reset_request, .rst_assert = meson_reset_assert, .rst_deassert = meson_reset_deassert, diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c index a3b85a42250..66b541f09e6 100644 --- a/drivers/reset/reset-npcm.c +++ b/drivers/reset/reset-npcm.c @@ -126,7 +126,7 @@ static const struct udevice_id npcm_reset_ids[] = { { } }; -struct reset_ops npcm_reset_ops = { +static const struct reset_ops npcm_reset_ops = { .request = npcm_reset_request, .rfree = npcm_reset_free, .rst_assert = npcm_reset_assert, diff --git a/drivers/reset/reset-raspberrypi.c b/drivers/reset/reset-raspberrypi.c index 1792f0813f7..73acd301e3d 100644 --- a/drivers/reset/reset-raspberrypi.c +++ b/drivers/reset/reset-raspberrypi.c @@ -28,7 +28,7 @@ static int raspberrypi_reset_assert(struct reset_ctl *reset_ctl) } } -struct reset_ops raspberrypi_reset_ops = { +static const struct reset_ops raspberrypi_reset_ops = { .request = raspberrypi_reset_request, .rst_assert = raspberrypi_reset_assert, }; diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c index fd47e1f9e37..6195edd5b2f 100644 --- a/drivers/reset/reset-sunxi.c +++ b/drivers/reset/reset-sunxi.c @@ -67,7 +67,7 @@ static int sunxi_reset_deassert(struct reset_ctl *reset_ctl) return sunxi_set_reset(reset_ctl, true); } -struct reset_ops sunxi_reset_ops = { +static const struct reset_ops sunxi_reset_ops = { .request = sunxi_reset_request, .rst_assert = sunxi_reset_assert, .rst_deassert = sunxi_reset_deassert, diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index fe4cebf54f1..c199e3e5da7 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -13,6 +13,7 @@ #include <reset-uclass.h> #include <dm/devres.h> #include <dm/lists.h> +#include <linux/delay.h> static inline struct reset_ops *reset_dev_ops(struct udevice *dev) { @@ -225,6 +226,39 @@ int reset_deassert_bulk(struct reset_ctl_bulk *bulk) return 0; } +int reset_reset(struct reset_ctl *reset_ctl, ulong delay_us) +{ + struct reset_ops *ops = reset_dev_ops(reset_ctl->dev); + int ret; + + debug("%s(reset_ctl=%p, delay_us=%lu)\n", __func__, reset_ctl, + delay_us); + + if (ops->rst_reset) + return ops->rst_reset(reset_ctl, delay_us); + + ret = reset_assert(reset_ctl); + if (ret < 0) + return ret; + + udelay(delay_us); + + return reset_deassert(reset_ctl); +} + +int reset_reset_bulk(struct reset_ctl_bulk *bulk, ulong delay_us) +{ + int i, ret; + + for (i = 0; i < bulk->count; i++) { + ret = reset_reset(&bulk->resets[i], delay_us); + if (ret < 0) + return ret; + } + + return 0; +} + int reset_status(struct reset_ctl *reset_ctl) { struct reset_ops *ops = reset_dev_ops(reset_ctl->dev); diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index d04e8eef3bb..2b58f3a75b4 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -45,6 +45,16 @@ static int zynqmp_reset_deassert(struct reset_ctl *rst) PM_RESET_ACTION_RELEASE); } +static int zynqmp_reset_reset(struct reset_ctl *rst, ulong delay_us) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id); + + return zynqmp_pm_reset_assert(priv->reset_id + rst->id, + PM_RESET_ACTION_PULSE); +} + static int zynqmp_reset_request(struct reset_ctl *rst) { struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); @@ -74,6 +84,7 @@ const struct reset_ops zynqmp_reset_ops = { .request = zynqmp_reset_request, .rst_assert = zynqmp_reset_assert, .rst_deassert = zynqmp_reset_deassert, + .rst_reset = zynqmp_reset_reset, }; static const struct udevice_id zynqmp_reset_ids[] = { diff --git a/drivers/reset/sandbox-reset-test.c b/drivers/reset/sandbox-reset-test.c index dfacb764bc7..64c205596c5 100644 --- a/drivers/reset/sandbox-reset-test.c +++ b/drivers/reset/sandbox-reset-test.c @@ -96,6 +96,20 @@ int sandbox_reset_test_deassert_bulk(struct udevice *dev) return reset_deassert_bulk(sbrt->bulkp); } +int sandbox_reset_test_reset(struct udevice *dev) +{ + struct sandbox_reset_test *sbrt = dev_get_priv(dev); + + return reset_reset(sbrt->ctlp, 0); +} + +int sandbox_reset_test_reset_bulk(struct udevice *dev) +{ + struct sandbox_reset_test *sbrt = dev_get_priv(dev); + + return reset_reset_bulk(sbrt->bulkp, 0); +} + int sandbox_reset_test_free(struct udevice *dev) { struct sandbox_reset_test *sbrt = dev_get_priv(dev); diff --git a/drivers/reset/sandbox-reset.c b/drivers/reset/sandbox-reset.c index adf9eedcba6..12812f0f340 100644 --- a/drivers/reset/sandbox-reset.c +++ b/drivers/reset/sandbox-reset.c @@ -9,12 +9,14 @@ #include <reset-uclass.h> #include <asm/io.h> #include <asm/reset.h> +#include <linux/delay.h> #define SANDBOX_RESET_SIGNALS 101 struct sandbox_reset_signal { bool asserted; bool requested; + int reset_count; }; struct sandbox_reset { @@ -31,6 +33,7 @@ static int sandbox_reset_request(struct reset_ctl *reset_ctl) return -EINVAL; sbr->signals[reset_ctl->id].requested = true; + sbr->signals[reset_ctl->id].reset_count = 0; return 0; } @@ -66,6 +69,21 @@ static int sandbox_reset_deassert(struct reset_ctl *reset_ctl) return 0; } +static int sandbox_reset_reset(struct reset_ctl *reset_ctl, ulong delay_us) +{ + struct sandbox_reset *sbr = dev_get_priv(reset_ctl->dev); + + debug("%s(reset_ctl=%p, delay_us=%lu)\n", __func__, reset_ctl, + delay_us); + + sbr->signals[reset_ctl->id].asserted = true; + udelay(delay_us); + sbr->signals[reset_ctl->id].asserted = false; + sbr->signals[reset_ctl->id].reset_count++; + + return 0; +} + static int sandbox_reset_bind(struct udevice *dev) { debug("%s(dev=%p)\n", __func__, dev); @@ -85,11 +103,12 @@ static const struct udevice_id sandbox_reset_ids[] = { { } }; -struct reset_ops sandbox_reset_reset_ops = { +static const struct reset_ops sandbox_reset_reset_ops = { .request = sandbox_reset_request, .rfree = sandbox_reset_free, .rst_assert = sandbox_reset_assert, .rst_deassert = sandbox_reset_deassert, + .rst_reset = sandbox_reset_reset, }; U_BOOT_DRIVER(sandbox_reset) = { @@ -102,6 +121,33 @@ U_BOOT_DRIVER(sandbox_reset) = { .ops = &sandbox_reset_reset_ops, }; +/* + * Second sandbox reset controller for tests: same assert/deassert + * behaviour as sandbox_reset, but no rst_reset so reset_reset() uses + * the core assert / udelay / deassert fallback (reset_count never bumps). + */ +static const struct udevice_id sandbox_reset_fallback_ids[] = { + { .compatible = "sandbox,reset-ctl-fallback-only" }, + { } +}; + +static const struct reset_ops sandbox_reset_fallback_reset_ops = { + .request = sandbox_reset_request, + .rfree = sandbox_reset_free, + .rst_assert = sandbox_reset_assert, + .rst_deassert = sandbox_reset_deassert, +}; + +U_BOOT_DRIVER(sandbox_reset_fallback) = { + .name = "sandbox_reset_fallback", + .id = UCLASS_RESET, + .of_match = sandbox_reset_fallback_ids, + .bind = sandbox_reset_bind, + .probe = sandbox_reset_probe, + .priv_auto = sizeof(struct sandbox_reset), + .ops = &sandbox_reset_fallback_reset_ops, +}; + int sandbox_reset_query(struct udevice *dev, unsigned long id) { struct sandbox_reset *sbr = dev_get_priv(dev); @@ -125,3 +171,15 @@ int sandbox_reset_is_requested(struct udevice *dev, unsigned long id) return sbr->signals[id].requested; } + +int sandbox_reset_get_count(struct udevice *dev, unsigned long id) +{ + struct sandbox_reset *sbr = dev_get_priv(dev); + + debug("%s(dev=%p, id=%ld)\n", __func__, dev, id); + + if (id >= SANDBOX_RESET_SIGNALS) + return -EINVAL; + + return sbr->signals[id].reset_count; +} diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c index 412a0c5b452..37a37a72fd3 100644 --- a/drivers/reset/sti-reset.c +++ b/drivers/reset/sti-reset.c @@ -290,7 +290,7 @@ static int sti_reset_deassert(struct reset_ctl *reset_ctl) return sti_reset_program_hw(reset_ctl, false); } -struct reset_ops sti_reset_ops = { +static const struct reset_ops sti_reset_ops = { .rst_assert = sti_reset_assert, .rst_deassert = sti_reset_deassert, }; diff --git a/drivers/reset/tegra-car-reset.c b/drivers/reset/tegra-car-reset.c index e3ecc8d3735..63f148cf3d9 100644 --- a/drivers/reset/tegra-car-reset.c +++ b/drivers/reset/tegra-car-reset.c @@ -42,7 +42,7 @@ static int tegra_car_reset_deassert(struct reset_ctl *reset_ctl) return 0; } -struct reset_ops tegra_car_reset_ops = { +static const struct reset_ops tegra_car_reset_ops = { .request = tegra_car_reset_request, .rst_assert = tegra_car_reset_assert, .rst_deassert = tegra_car_reset_deassert, diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c index 89624227c29..1d8f40acaef 100644 --- a/drivers/reset/tegra186-reset.c +++ b/drivers/reset/tegra186-reset.c @@ -43,7 +43,7 @@ static int tegra186_reset_deassert(struct reset_ctl *reset_ctl) return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT); } -struct reset_ops tegra186_reset_ops = { +static const struct reset_ops tegra186_reset_ops = { .rst_assert = tegra186_reset_assert, .rst_deassert = tegra186_reset_deassert, }; diff --git a/drivers/rng/iproc_rng200.c b/drivers/rng/iproc_rng200.c index 4c49aa9e444..aa211df28cd 100644 --- a/drivers/rng/iproc_rng200.c +++ b/drivers/rng/iproc_rng200.c @@ -155,7 +155,7 @@ static int iproc_rng200_of_to_plat(struct udevice *dev) { struct iproc_rng200_plat *pdata = dev_get_plat(dev); - pdata->base = devfdt_map_physmem(dev, sizeof(void *)); + pdata->base = dev_remap_addr(dev); if (!pdata->base) return -ENODEV; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 65d9bf533cb..6fb3019a644 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -44,8 +44,8 @@ config VPL_DM_RTC config RTC_ENABLE_32KHZ_OUTPUT bool "Enable RTC 32Khz output" help - Some real-time clocks support the output of 32kHz square waves (such as ds3231), - the config symbol choose Real Time Clock device 32Khz output feature. + Some real-time clocks support the output of 32kHz square waves (such as ds3231), + the config symbol choose Real Time Clock device 32Khz output feature. config RTC_ARMADA38X bool "Enable Armada 38x Marvell SoC RTC" @@ -163,6 +163,9 @@ config RTC_PCF85063 help If you say yes here you get support for the NXP PCF85063 RTC and compatible chips. + Support for the following chip features is currently not implemented: + - NVMEM device for RAM register + - CLKOUT generation config RTC_PCF8563 bool "Philips PCF8563" diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 34d8f8c5276..4176ab3701e 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -116,9 +116,9 @@ static int ds1307_rtc_get(struct udevice *dev, struct rtc_time *tm) if (ret < 0) return ret; - if (type == ds_1337 || type == ds_1340) { - uint reg = (type == ds_1337) ? DS1337_STAT_REG_ADDR : - DS1340_STAT_REG_ADDR; + if (type == ds_1337 || type == ds_1339 || type == ds_1340) { + uint reg = (type == ds_1340) ? DS1340_STAT_REG_ADDR : + DS1337_STAT_REG_ADDR; int status = dm_i2c_reg_read(dev, reg); if (status >= 0 && (status & RTC_STAT_BIT_OSF)) { diff --git a/drivers/rtc/goldfish_rtc.c b/drivers/rtc/goldfish_rtc.c index d2991ca6719..652eec7dd0c 100644 --- a/drivers/rtc/goldfish_rtc.c +++ b/drivers/rtc/goldfish_rtc.c @@ -40,8 +40,8 @@ static int goldfish_rtc_get(struct udevice *dev, struct rtc_time *time) u64 time_low; u64 now; - time_low = ioread32(base + GOLDFISH_TIME_LOW); - time_high = ioread32(base + GOLDFISH_TIME_HIGH); + time_low = __raw_readl(base + GOLDFISH_TIME_LOW); + time_high = __raw_readl(base + GOLDFISH_TIME_HIGH); now = (time_high << 32) | time_low; do_div(now, 1000000000U); @@ -62,8 +62,8 @@ static int goldfish_rtc_set(struct udevice *dev, const struct rtc_time *time) return -EINVAL; now = rtc_mktime(time) * 1000000000ULL; - iowrite32(now >> 32, base + GOLDFISH_TIME_HIGH); - iowrite32(now, base + GOLDFISH_TIME_LOW); + __raw_writel(now >> 32, base + GOLDFISH_TIME_HIGH); + __raw_writel(now, base + GOLDFISH_TIME_LOW); if (time->tm_isdst > 0) priv->isdst = 1; @@ -80,9 +80,13 @@ static int goldfish_rtc_of_to_plat(struct udevice *dev) struct goldfish_rtc_plat *plat = dev_get_plat(dev); fdt_addr_t addr; + plat->reg = 0; + addr = dev_read_addr(dev); - if (addr != FDT_ADDR_T_NONE) - plat->reg = addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = addr; return 0; } diff --git a/drivers/rtc/i2c_rtc_emul.c b/drivers/rtc/i2c_rtc_emul.c index ea11c72c964..41bdf275f1e 100644 --- a/drivers/rtc/i2c_rtc_emul.c +++ b/drivers/rtc/i2c_rtc_emul.c @@ -191,7 +191,7 @@ static int sandbox_i2c_rtc_xfer(struct udevice *emul, struct i2c_msg *msg, return 0; } -struct dm_i2c_ops sandbox_i2c_rtc_emul_ops = { +static const struct dm_i2c_ops sandbox_i2c_rtc_emul_ops = { .xfer = sandbox_i2c_rtc_xfer, }; diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 7bfea9e0b31..b3734baf63e 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -66,7 +66,7 @@ static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf) { debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", - __FUNCTION__, + __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); @@ -83,7 +83,7 @@ static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf) debug("%s: tm is secs=%d, mins=%d, hours=%d, " "mday=%d, mon=%d, year=%d, wday=%d\n", - __FUNCTION__, + __func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); } diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c index 9708971c5c4..23ffb2b31a1 100644 --- a/drivers/rtc/mcfrtc.c +++ b/drivers/rtc/mcfrtc.c @@ -73,7 +73,7 @@ int rtc_set(struct rtc_time *tmp) days += month_days[i]; if (i == 1) - days += isleap(i); + days += isleap(tmp->tm_year); } days += tmp->tm_mday - 1; diff --git a/drivers/rtc/pcf85063.c b/drivers/rtc/pcf85063.c index 737d4547aca..421c42c0b81 100644 --- a/drivers/rtc/pcf85063.c +++ b/drivers/rtc/pcf85063.c @@ -11,11 +11,33 @@ #include <dm/device_compat.h> #define PCF85063_REG_CTRL1 0x00 /* status */ -#define PCF85063_REG_CTRL1_SR 0x58 +#define PCF85063_REG_CTRL1_CAP_SEL BIT(0) +#define PCF85063_REG_CTRL1_STOP BIT(5) +#define PCF85063_REG_CTRL1_EXT_TEST BIT(7) +#define PCF85063_REG_CTRL1_SWR 0x58 /* Software reset command */ + +#define PCF85063_REG_CTRL2 0x01 +#define PCF85063_CTRL2_AF BIT(6) +#define PCF85063_CTRL2_AIE BIT(7) + +#define PCF85063_REG_OFFSET 0x02 +#define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */ +#define PCF85063_OFFSET_MODE BIT(7) +#define PCF85063_OFFSET_STEP0 4340 +#define PCF85063_OFFSET_STEP1 4069 + +#define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */ +#define PCF85063_REG_CLKO_F_32768HZ 0x00 +#define PCF85063_REG_CLKO_F_OFF 0x07 + +#define PCF85063_REG_RAM 0x03 #define PCF85063_REG_SC 0x04 /* datetime */ #define PCF85063_REG_SC_OS 0x80 +#define PCF85063_REG_ALM_S 0x0b +#define PCF85063_AEN BIT(7) + static int pcf85063_get_time(struct udevice *dev, struct rtc_time *tm) { u8 regs[7]; @@ -35,7 +57,9 @@ static int pcf85063_get_time(struct udevice *dev, struct rtc_time *tm) tm->tm_hour = bcd2bin(regs[2] & 0x3f); tm->tm_mday = bcd2bin(regs[3] & 0x3f); tm->tm_wday = regs[4] & 0x07; - tm->tm_mon = bcd2bin(regs[5] & 0x1f) - 1; + /* rtc register and rtc_time spec uses 1 - 12 */ + tm->tm_mon = bcd2bin(regs[5] & 0x1f); + /* adjust rtc_time (years since 0) to match register spec */ tm->tm_year = bcd2bin(regs[6]) + 2000; return 0; @@ -44,40 +68,102 @@ static int pcf85063_get_time(struct udevice *dev, struct rtc_time *tm) static int pcf85063_set_time(struct udevice *dev, const struct rtc_time *tm) { u8 regs[7]; + int rc; if (tm->tm_year < 2000 || tm->tm_year > 2099) { dev_err(dev, "Year must be between 2000 and 2099.\n"); return -EINVAL; } - regs[0] = bin2bcd(tm->tm_sec); + /* + * to accurately set the time, reset the divider chain and keep it in + * reset state until all time/date registers are written + */ + rc = dm_i2c_reg_clrset(dev, PCF85063_REG_CTRL1, + PCF85063_REG_CTRL1_EXT_TEST | + PCF85063_REG_CTRL1_STOP, + PCF85063_REG_CTRL1_STOP); + + if (rc) + return rc; + + /* hours, minutes and seconds */ + regs[0] = bin2bcd(tm->tm_sec) & (~PCF85063_REG_SC_OS); + regs[1] = bin2bcd(tm->tm_min); regs[2] = bin2bcd(tm->tm_hour); + + /* Day of month, 1 - 31 */ regs[3] = bin2bcd(tm->tm_mday); - regs[4] = tm->tm_wday; - regs[5] = bin2bcd(tm->tm_mon + 1); + + /* Day of week 0 - 6 */ + regs[4] = tm->tm_wday & 0x07; + + /* rtc register and rtc_time spec uses 1 - 12 */ + regs[5] = bin2bcd(tm->tm_mon); + /* adjust register to match rtc_time spec */ regs[6] = bin2bcd(tm->tm_year % 100); - return dm_i2c_write(dev, PCF85063_REG_SC, regs, sizeof(regs)); + rc = dm_i2c_write(dev, PCF85063_REG_SC, regs, sizeof(regs)); + if (rc) + return rc; + + /* + * Write the control register as a separate action since the size of + * the register space is different between the PCF85063TP and + * PCF85063A devices. The rollover point can not be used. + */ + return dm_i2c_reg_clrset(dev, PCF85063_REG_CTRL1, + PCF85063_REG_CTRL1_STOP, 0); } static int pcf85063_reset(struct udevice *dev) { - return dm_i2c_reg_write(dev, PCF85063_REG_CTRL1, PCF85063_REG_CTRL1_SR); + return dm_i2c_reg_write(dev, PCF85063_REG_CTRL1, PCF85063_REG_CTRL1_SWR); } static int pcf85063_read(struct udevice *dev, unsigned int offset, u8 *buf, unsigned int len) { + if (offset + len > dev->driver_data) + return -EINVAL; + return dm_i2c_read(dev, offset, buf, len); } static int pcf85063_write(struct udevice *dev, unsigned int offset, const u8 *buf, unsigned int len) { + if (offset + len > dev->driver_data) + return -EINVAL; + return dm_i2c_write(dev, offset, buf, len); } +static int pcf85063_load_capacitance(struct udevice *dev) +{ + u32 load = 7000; + u8 reg = 0; + + if (ofnode_read_u32(dev_ofnode(dev), "quartz-load-femtofarads", &load)) + return 0; + + switch (load) { + default: + dev_warn(dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000", + load); + fallthrough; + case 7000: + break; + case 12500: + reg = PCF85063_REG_CTRL1_CAP_SEL; + break; + } + + return dm_i2c_reg_clrset(dev, PCF85063_REG_CTRL1, + PCF85063_REG_CTRL1_CAP_SEL, reg); +} + static const struct rtc_ops pcf85063_rtc_ops = { .get = pcf85063_get_time, .set = pcf85063_set_time, @@ -88,13 +174,45 @@ static const struct rtc_ops pcf85063_rtc_ops = { static int pcf85063_probe(struct udevice *dev) { + u8 tmp; + int err; + i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS | DM_I2C_CHIP_WR_ADDRESS); + err = dm_i2c_read(dev, PCF85063_REG_SC, &tmp, sizeof(tmp)); + if (err) { + dev_err(dev, "RTC chip is not present\n"); + return err; + } + + /* + * If a Power loss is detected, SW reset the device. + * From PCF85063A datasheet: + * There is a low probability that some devices will have corruption + * of the registers after the automatic power-on reset... + */ + if (tmp & PCF85063_REG_SC_OS) { + dev_warn(dev, "POR issue detected, sending a SW reset\n"); + err = dm_i2c_reg_clrset(dev, PCF85063_REG_CTRL1, + 0xff, PCF85063_REG_CTRL1_SWR); + if (err < 0) + dev_warn(dev, "SW reset failed, trying to continue\n"); + } + + err = pcf85063_load_capacitance(dev); + if (err < 0) + dev_warn(dev, "failed to set xtal load capacitance: %d", + err); + return 0; } static const struct udevice_id pcf85063_of_id[] = { - { .compatible = "microcrystal,rv8263" }, + { .compatible = "microcrystal,rv8263", .data = 0x12 }, + { .compatible = "nxp,pcf85063", .data = 0xb }, + { .compatible = "nxp,pcf85063a", .data = 0x12 }, + { .compatible = "nxp,pcf85063tp", .data = 0xb }, + { .compatible = "nxp,pcf85073a", .data = 0x12 }, { } }; diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c index 4404501c2f6..1ade5d50b23 100644 --- a/drivers/rtc/sandbox_rtc.c +++ b/drivers/rtc/sandbox_rtc.c @@ -73,7 +73,7 @@ static int sandbox_rtc_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "RTCC"); } -struct acpi_ops sandbox_rtc_acpi_ops = { +static const struct acpi_ops sandbox_rtc_acpi_ops = { .get_name = sandbox_rtc_get_name, }; #endif diff --git a/drivers/scsi/sandbox_scsi.c b/drivers/scsi/sandbox_scsi.c index 544a0247083..5f0b01d86d5 100644 --- a/drivers/scsi/sandbox_scsi.c +++ b/drivers/scsi/sandbox_scsi.c @@ -128,7 +128,7 @@ static int sandbox_scsi_remove(struct udevice *dev) return 0; } -struct scsi_ops sandbox_scsi_ops = { +static const struct scsi_ops sandbox_scsi_ops = { .exec = sandbox_scsi_exec, .bus_reset = sandbox_scsi_bus_reset, }; diff --git a/drivers/scsi/scsi_bootdev.c b/drivers/scsi/scsi_bootdev.c index 28e4612f337..541b021b732 100644 --- a/drivers/scsi/scsi_bootdev.c +++ b/drivers/scsi/scsi_bootdev.c @@ -37,9 +37,6 @@ static int scsi_bootdev_hunt(struct bootdev_hunter *info, bool show) return 0; } -struct bootdev_ops scsi_bootdev_ops = { -}; - static const struct udevice_id scsi_bootdev_ids[] = { { .compatible = "u-boot,bootdev-scsi" }, { } @@ -48,7 +45,6 @@ static const struct udevice_id scsi_bootdev_ids[] = { U_BOOT_DRIVER(scsi_bootdev) = { .name = "scsi_bootdev", .id = UCLASS_BOOTDEV, - .ops = &scsi_bootdev_ops, .bind = scsi_bootdev_bind, .of_match = scsi_bootdev_ids, }; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5f8b98f0704..e221800d5d0 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -759,11 +759,11 @@ config MVEBU_A3700_UART config MCFUART bool "Freescale ColdFire UART support" depends on M68K - help - Choose this option to add support for UART driver on the ColdFire - SoC's family. The serial communication channel provides a full-duplex - asynchronous/synchronous receiver and transmitter deriving an - operating frequency from the internal bus clock or an external clock. + help + Choose this option to add support for UART driver on the ColdFire + SoC's family. The serial communication channel provides a full-duplex + asynchronous/synchronous receiver and transmitter deriving an + operating frequency from the internal bus clock or an external clock. config MXC_UART bool "IMX serial port support" @@ -1024,12 +1024,12 @@ config OCTEON_SERIAL_BOOTCMD bool "MIPS Octeon PCI remote bootcmd input" depends on ARCH_OCTEON depends on DM_SERIAL - select SYS_IS_IN_ENV + select SYS_CONSOLE_IS_IN_ENV select CONSOLE_MUX help - This driver supports remote input over the PCIe bus from a host - to U-Boot for entering commands. It is utilized by the host - commands 'oct-remote-load' and 'oct-remote-bootcmd'. + This driver supports remote input over the PCIe bus from a host + to U-Boot for entering commands. It is utilized by the host + commands 'oct-remote-load' and 'oct-remote-bootcmd'. config OCTEON_SERIAL_PCIE_CONSOLE bool "MIPS Octeon PCIe remote console" diff --git a/drivers/serial/serial_cortina.c b/drivers/serial/serial_cortina.c index 3ae8fb46584..de8af5b0574 100644 --- a/drivers/serial/serial_cortina.c +++ b/drivers/serial/serial_cortina.c @@ -83,11 +83,13 @@ int ca_serial_setbrg(struct udevice *dev, int baudrate) static int ca_serial_getc(struct udevice *dev) { struct ca_uart_priv *priv = dev_get_priv(dev); - int ch; + unsigned int status; - ch = readl(priv->base + URX_DATA) & 0xFF; + status = readl(priv->base + UINFO); + if (status & UINFO_RX_FIFO_EMPTY) + return -EAGAIN; - return (int)ch; + return readl(priv->base + URX_DATA) & 0xFF; } static int ca_serial_putc(struct udevice *dev, const char ch) diff --git a/drivers/serial/serial_goldfish.c b/drivers/serial/serial_goldfish.c index 91dc040fcf2..732f167caae 100644 --- a/drivers/serial/serial_goldfish.c +++ b/drivers/serial/serial_goldfish.c @@ -74,8 +74,10 @@ static int goldfish_serial_of_to_plat(struct udevice *dev) fdt_addr_t addr; addr = dev_read_addr(dev); - if (addr != FDT_ADDR_T_NONE) - plat->reg = addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = addr; return 0; } diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 9fdb6503085..955f1c96407 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -53,11 +53,7 @@ #define FIFO_RXSIZE_MASK 0x7 #define FIFO_RXSIZE_OFF 0 #define FIFO_TXFE 0x80 -#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT) #define FIFO_RXFE 0x08 -#else -#define FIFO_RXFE 0x40 -#endif #define WATER_TXWATER_OFF 0 #define WATER_RXWATER_OFF 16 @@ -523,8 +519,7 @@ static int lpuart_serial_probe(struct udevice *dev) static int lpuart_serial_of_to_plat(struct udevice *dev) { struct lpuart_serial_plat *plat = dev_get_plat(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); + ofnode node = dev_ofnode(dev); fdt_addr_t addr; addr = dev_read_addr(dev); @@ -534,18 +529,18 @@ static int lpuart_serial_of_to_plat(struct udevice *dev) plat->reg = (void *)addr; plat->flags = dev_get_driver_data(dev); - if (fdtdec_get_bool(blob, node, "little-endian")) + if (ofnode_read_bool(node, "little-endian")) plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG; - if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart")) + if (ofnode_device_is_compatible(node, "fsl,ls1021a-lpuart")) plat->devtype = DEV_LS1021A; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx7ulp-lpuart")) plat->devtype = DEV_MX7ULP; - else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,vf610-lpuart")) plat->devtype = DEV_VF610; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx8qm-lpuart")) plat->devtype = DEV_IMX8; - else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imxrt-lpuart")) plat->devtype = DEV_IMXRT; return 0; diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 3dca581f68f..ae4015e0fdc 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -55,6 +55,7 @@ #define SE_UART_RX_PARITY_CFG 0x2a8 #define DEF_TX_WM 2 +#define DEF_RX_WM 2 /* GENI_FORCE_DEFAULT_REG fields */ #define UART_START_READ 0x1 @@ -345,6 +346,7 @@ static void qcom_geni_serial_start_rx(struct udevice *dev) geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); + writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG); setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); } @@ -373,6 +375,7 @@ static void msm_geni_serial_setup_rx(struct udevice *dev) geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); + writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG); setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); } @@ -616,6 +619,7 @@ static inline void _debug_uart_init(void) phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); geni_serial_init(&init_dev); + writel(DEF_RX_WM, base + SE_GENI_RX_WATERMARK_REG); geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE); qcom_geni_serial_start_tx(base); } diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig index e5d7dcc81b1..5b68ad5f10f 100644 --- a/drivers/smem/Kconfig +++ b/drivers/smem/Kconfig @@ -4,22 +4,22 @@ menuconfig SMEM if SMEM config SANDBOX_SMEM - bool "Sandbox Shared Memory Manager (SMEM)" - depends on SANDBOX && DM - help - enable SMEM support for sandbox. This is an emulation of a real SMEM - manager. - The sandbox driver allocates a shared memory from the heap and - initialzies it on start. + bool "Sandbox Shared Memory Manager (SMEM)" + depends on SANDBOX && DM + help + enable SMEM support for sandbox. This is an emulation of a real SMEM + manager. + The sandbox driver allocates a shared memory from the heap and + initialzies it on start. config MSM_SMEM - bool "Qualcomm Shared Memory Manager (SMEM)" - depends on DM - depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX - select DEVRES - help - Enable support for the Qualcomm Shared Memory Manager. - The driver provides an interface to items in a heap shared among all - processors in a Qualcomm platform. + bool "Qualcomm Shared Memory Manager (SMEM)" + depends on DM + depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX + select DEVRES + help + Enable support for the Qualcomm Shared Memory Manager. + The driver provides an interface to items in a heap shared among all + processors in a Qualcomm platform. endif # menu "SMEM Support" diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 36129cb72f6..9734bf32cb0 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -21,8 +21,8 @@ config TI_KEYSTONE_SERDES bool "Keystone SerDes driver for ethernet" depends on ARCH_KEYSTONE help - SerDes driver for Keystone SoC used for ethernet support on TI - K2 platforms. + SerDes driver for Keystone SoC used for ethernet support on TI + K2 platforms. config TI_PRUSS bool "Support for TI's K3 based Pruss driver" diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c index 5b9b3f65263..d1d03ae91d4 100644 --- a/drivers/sound/da7219.c +++ b/drivers/sound/da7219.c @@ -170,7 +170,7 @@ static int da7219_acpi_setup_nhlt(const struct udevice *dev, } #endif -struct acpi_ops da7219_acpi_ops = { +static const struct acpi_ops da7219_acpi_ops = { #ifdef CONFIG_ACPIGEN .fill_ssdt = da7219_acpi_fill_ssdt, #ifdef CONFIG_X86 diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index da56ffdd6bb..47978d4fe27 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -136,7 +136,7 @@ static int max98357a_acpi_setup_nhlt(const struct udevice *dev, } #endif -struct acpi_ops max98357a_acpi_ops = { +static const struct acpi_ops max98357a_acpi_ops = { #ifdef CONFIG_ACPIGEN .fill_ssdt = max98357a_acpi_fill_ssdt, #ifdef CONFIG_X86 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index cfbedd64c4c..009dd997efb 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -2,10 +2,10 @@ menuconfig SPI bool "SPI Support" help The "Serial Peripheral Interface" is a low level synchronous - protocol. Chips that support SPI can have data transfer rates - up to several tens of Mbit/sec. Chips are addressed with a - controller and a chipselect. Most SPI slaves don't support - dynamic device discovery; some are even write-only or read-only. + protocol. Chips that support SPI can have data transfer rates + up to several tens of Mbit/sec. Chips are addressed with a + controller and a chipselect. Most SPI slaves don't support + dynamic device discovery; some are even write-only or read-only. SPI is widely used by microcontrollers to talk with sensors, eeprom and flash memory, codecs and various other controller @@ -200,11 +200,11 @@ config CADENCE_XSPI by using the Auto Command work mode. config CF_SPI - bool "ColdFire SPI driver" - depends on M68K - help - Enable the ColdFire SPI driver. This driver can be used on - some m68k SoCs. + bool "ColdFire SPI driver" + depends on M68K + help + Enable the ColdFire SPI driver. This driver can be used on + some m68k SoCs. config CV1800B_SPIF bool "Sophgo cv1800b SPI Flash Controller driver" @@ -352,7 +352,7 @@ config MTK_SNOR select DEVRES help Enable the Mediatek SPINOR controller driver. This driver has - better read/write performance with NOR. + better read/write performance with NOR. config MTK_SNFI_SPI bool "Mediatek SPI memory controller driver" @@ -544,8 +544,8 @@ config SPI_SIFIVE config SOFT_SPI bool "Soft SPI driver" help - Enable Soft SPI driver. This driver is to use GPIO simulate - the SPI protocol. + Enable Soft SPI driver. This driver is to use GPIO simulate + the SPI protocol. config SPI_SN_F_OSPI tristate "Socionext F_OSPI SPI flash controller" @@ -673,8 +673,8 @@ config ZYNQMP_GQSPI config SPI_STACKED_PARALLEL bool "Enable support for stacked or parallel memories" help - Enable support for stacked/or parallel memories. This functionality - may appear on Xilinx hardware. By default this is disabled. + Enable support for stacked/or parallel memories. This functionality + may appear on Xilinx hardware. By default this is disabled. endif # if DM_SPI diff --git a/drivers/spi/apple_spi.c b/drivers/spi/apple_spi.c index 088d02e3b90..acc87ea7bdc 100644 --- a/drivers/spi/apple_spi.c +++ b/drivers/spi/apple_spi.c @@ -228,7 +228,7 @@ static int apple_spi_set_mode(struct udevice *bus, uint mode) return 0; } -struct dm_spi_ops apple_spi_ops = { +static const struct dm_spi_ops apple_spi_ops = { .xfer = apple_spi_xfer, .set_speed = apple_spi_set_speed, .set_mode = apple_spi_set_mode, diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 2a4a49c5f1c..984d4a39ded 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -31,6 +31,8 @@ #define CQSPI_DISABLE_STIG_MODE BIT(0) #define CQSPI_DMA_MODE BIT(1) +#define CQSPI_RESET_DELAY_US 10 + __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op) { @@ -256,19 +258,9 @@ static int cadence_spi_probe(struct udevice *bus) priv->resets = devm_reset_bulk_get_optional(bus); if (priv->resets) { - /* Assert all OSPI reset lines */ - ret = reset_assert_bulk(priv->resets); - if (ret) { - dev_err(bus, "Failed to assert OSPI reset: %d\n", ret); - return ret; - } - - udelay(10); - - /* Deassert all OSPI reset lines */ - ret = reset_deassert_bulk(priv->resets); + ret = reset_reset_bulk(priv->resets, CQSPI_RESET_DELAY_US); if (ret) { - dev_err(bus, "Failed to deassert OSPI reset: %d\n", ret); + dev_err(bus, "Failed to reset OSPI: %d\n", ret); return ret; } } diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index ca29cfd7c88..0186b01ad9a 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -53,18 +53,20 @@ struct aspeed_spi_regs { u32 dma_len; /* 0x8c DMA Length Register */ u32 dma_checksum; /* 0x90 Checksum Calculation Result */ u32 timings[ASPEED_SPI_MAX_CS]; /* 0x94 Read Timing Compensation */ + u32 _reserved3[83]; /* 0xA8 - 0x1F0 */ + u32 val_kept_wdt; /* 0x1F4 Value Kept WDT */ }; struct aspeed_spi_plat { u8 max_cs; - void __iomem *ahb_base; /* AHB address base for all flash devices. */ + uintptr_t ahb_base; /* AHB address base for all flash devices. */ fdt_size_t ahb_sz; /* Overall AHB window size for all flash device. */ u32 hclk_rate; /* AHB clock rate */ }; struct aspeed_spi_flash { - void __iomem *ahb_base; - u32 ahb_decoded_sz; + uintptr_t ahb_base; + size_t ahb_decoded_sz; u32 ce_ctrl_user; u32 ce_ctrl_read; u32 max_freq; @@ -84,9 +86,9 @@ struct aspeed_spi_info { u32 min_decoded_sz; u32 clk_ctrl_mask; void (*set_4byte)(struct udevice *bus, u32 cs); - u32 (*segment_start)(struct udevice *bus, u32 reg); - u32 (*segment_end)(struct udevice *bus, u32 reg); - u32 (*segment_reg)(u32 start, u32 end); + uintptr_t (*segment_start)(struct udevice *bus, u32 reg); + uintptr_t (*segment_end)(struct udevice *bus, u32 reg); + u32 (*segment_reg)(uintptr_t start, uintptr_t end); int (*adjust_decoded_sz)(struct udevice *bus); u32 (*get_clk_setting)(struct udevice *dev, uint hz); }; @@ -118,30 +120,30 @@ static u32 aspeed_spi_get_io_mode(u32 bus_width) } } -static u32 ast2400_spi_segment_start(struct udevice *bus, u32 reg) +static uintptr_t ast2400_spi_segment_start(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 start_offset = ((reg >> 16) & 0xff) << 23; + uintptr_t start_offset = ((reg >> 16) & 0xff) << 23; if (start_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + start_offset; + return plat->ahb_base + start_offset; } -static u32 ast2400_spi_segment_end(struct udevice *bus, u32 reg) +static uintptr_t ast2400_spi_segment_end(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 end_offset = ((reg >> 24) & 0xff) << 23; + uintptr_t end_offset = ((reg >> 24) & 0xff) << 23; /* Meaningless end_offset, set to physical ahb base. */ if (end_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + end_offset; + return plat->ahb_base + end_offset; } -static u32 ast2400_spi_segment_reg(u32 start, u32 end) +static u32 ast2400_spi_segment_reg(uintptr_t start, uintptr_t end) { if (start == end) return 0; @@ -206,30 +208,30 @@ static u32 ast2400_get_clk_setting(struct udevice *dev, uint max_hz) return hclk_div; } -static u32 ast2500_spi_segment_start(struct udevice *bus, u32 reg) +static uintptr_t ast2500_spi_segment_start(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 start_offset = ((reg >> 16) & 0xff) << 23; + uintptr_t start_offset = ((reg >> 16) & 0xff) << 23; if (start_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + start_offset; + return plat->ahb_base + start_offset; } -static u32 ast2500_spi_segment_end(struct udevice *bus, u32 reg) +static uintptr_t ast2500_spi_segment_end(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 end_offset = ((reg >> 24) & 0xff) << 23; + uintptr_t end_offset = ((reg >> 24) & 0xff) << 23; /* Meaningless end_offset, set to physical ahb base. */ if (end_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + end_offset; + return plat->ahb_base + end_offset; } -static u32 ast2500_spi_segment_reg(u32 start, u32 end) +static u32 ast2500_spi_segment_reg(uintptr_t start, uintptr_t end) { if (start == end) return 0; @@ -346,30 +348,30 @@ end: return hclk_div; } -static u32 ast2600_spi_segment_start(struct udevice *bus, u32 reg) +static uintptr_t ast2600_spi_segment_start(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 start_offset = (reg << 16) & 0x0ff00000; + uintptr_t start_offset = (reg << 16) & 0x0ff00000; if (start_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + start_offset; + return plat->ahb_base + start_offset; } -static u32 ast2600_spi_segment_end(struct udevice *bus, u32 reg) +static uintptr_t ast2600_spi_segment_end(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 end_offset = reg & 0x0ff00000; + uintptr_t end_offset = reg & 0x0ff00000; /* Meaningless end_offset, set to physical ahb base. */ if (end_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + end_offset + 0x100000; + return plat->ahb_base + end_offset + 0x100000; } -static u32 ast2600_spi_segment_reg(u32 start, u32 end) +static u32 ast2600_spi_segment_reg(uintptr_t start, uintptr_t end) { if (start == end) return 0; @@ -473,6 +475,70 @@ static u32 ast2600_get_clk_setting(struct udevice *dev, uint max_hz) return hclk_div; } +static uintptr_t ast2700_spi_segment_start(struct udevice *bus, u32 reg) +{ + struct aspeed_spi_plat *plat = dev_get_plat(bus); + uintptr_t start_offset = (reg & 0x0000ffff) << 16; + + if (start_offset == 0) + return plat->ahb_base; + + return plat->ahb_base + start_offset; +} + +static uintptr_t ast2700_spi_segment_end(struct udevice *bus, u32 reg) +{ + struct aspeed_spi_plat *plat = dev_get_plat(bus); + uintptr_t end_offset = reg & 0xffff0000; + + /* Meaningless end_offset, set to physical ahb base. */ + if (end_offset == 0) + return plat->ahb_base; + + return plat->ahb_base + end_offset; +} + +static u32 ast2700_spi_segment_reg(uintptr_t start, uintptr_t end) +{ + if (start == end) + return 0; + + return (((start >> 16) & 0x7fff) | ((end + 1) & 0x7fff0000)); +} + +static void ast2700_spi_chip_set_4byte(struct udevice *bus, u32 cs) +{ + struct aspeed_spi_priv *priv = dev_get_priv(bus); + u32 reg_val; + + reg_val = readl(&priv->regs->ctrl); + reg_val |= 0x11 << cs; + writel(reg_val, &priv->regs->ctrl); + + reg_val = readl(&priv->regs->val_kept_wdt); + reg_val |= (0x11 << 4) << cs; + writel(reg_val, &priv->regs->val_kept_wdt); +} + +static int ast2700_adjust_decoded_size(struct udevice *bus) +{ + struct aspeed_spi_plat *plat = dev_get_plat(bus); + struct aspeed_spi_priv *priv = dev_get_priv(bus); + struct aspeed_spi_flash *flashes = &priv->flashes[0]; + int ret; + int cs; + + /* Close unused CS. */ + for (cs = priv->num_cs; cs < plat->max_cs; cs++) + flashes[cs].ahb_decoded_sz = 0; + + ret = aspeed_spi_trim_decoded_size(bus); + if (ret != 0) + return ret; + + return 0; +} + /* * As the flash size grows up, we need to trim some decoded * size if needed for the sake of conforming the maximum @@ -512,12 +578,12 @@ static int aspeed_spi_trim_decoded_size(struct udevice *bus) return 0; } -static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, +static int aspeed_spi_read_from_ahb(uintptr_t ahb_base, void *buf, size_t len) { size_t offset = 0; - if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && + if (IS_ALIGNED(ahb_base, sizeof(uintptr_t)) && IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { readsl(ahb_base, buf, len >> 2); offset = len & ~0x3; @@ -529,12 +595,12 @@ static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, return 0; } -static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, +static int aspeed_spi_write_to_ahb(uintptr_t ahb_base, const void *buf, size_t len) { size_t offset = 0; - if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && + if (IS_ALIGNED(ahb_base, sizeof(uintptr_t)) && IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { writesl(ahb_base, buf, len >> 2); offset = len & ~0x3; @@ -589,7 +655,7 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, struct aspeed_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev); u32 cs = slave_plat->cs[0]; - u32 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; + uintptr_t ce_ctrl_reg = (uintptr_t)&priv->regs->ce_ctrl[cs]; u32 ce_ctrl_val; struct aspeed_spi_flash *flash = &priv->flashes[cs]; u8 dummy_data[16] = {0}; @@ -602,7 +668,7 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, op->data.nbytes, op->data.buswidth); if (priv->info == &ast2400_spi_info) - ce_ctrl_reg = (u32)&priv->regs->ctrl; + ce_ctrl_reg = (uintptr_t)&priv->regs->ctrl; /* * Set controller to 4-byte address mode @@ -670,7 +736,7 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) u32 i; u32 cs = slave_plat->cs[0]; u32 cmd_io_conf; - u32 ce_ctrl_reg; + uintptr_t ce_ctrl_reg; if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { /* @@ -681,9 +747,9 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) return -EOPNOTSUPP; } - ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; + ce_ctrl_reg = (uintptr_t)&priv->regs->ce_ctrl[cs]; if (info == &ast2400_spi_info) - ce_ctrl_reg = (u32)&priv->regs->ctrl; + ce_ctrl_reg = (uintptr_t)&priv->regs->ctrl; if (desc->info.length > 0x1000000) priv->info->set_4byte(bus, cs); @@ -693,7 +759,7 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) priv->flashes[cs].ahb_decoded_sz = desc->info.length; for (i = 0; i < priv->num_cs; i++) { - dev_dbg(dev, "cs: %d, sz: 0x%x\n", i, + dev_dbg(dev, "cs: %d, sz: 0x%zx\n", i, priv->flashes[cs].ahb_decoded_sz); } @@ -728,7 +794,7 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u32 cs = slave_plat->cs[0]; int ret; - dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n", + dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%zx\n", desc->info.op_tmpl.cmd.opcode, offs, len); if (priv->flashes[cs].ahb_decoded_sz < offs + len || @@ -738,7 +804,10 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, if (ret != 0) return 0; } else { - memcpy_fromio(buf, priv->flashes[cs].ahb_base + offs, len); + memcpy_fromio(buf, + (void __iomem *)(priv->flashes[cs].ahb_base + + (uintptr_t)offs), + len); } return len; @@ -783,19 +852,19 @@ static void aspeed_spi_decoded_range_set(struct udevice *bus) struct aspeed_spi_plat *plat = dev_get_plat(bus); struct aspeed_spi_priv *priv = dev_get_priv(bus); u32 decoded_reg_val; - u32 start_addr, end_addr; + uintptr_t start_addr, end_addr; u32 cs; for (cs = 0; cs < plat->max_cs; cs++) { - start_addr = (u32)priv->flashes[cs].ahb_base; - end_addr = (u32)priv->flashes[cs].ahb_base + + start_addr = priv->flashes[cs].ahb_base; + end_addr = priv->flashes[cs].ahb_base + priv->flashes[cs].ahb_decoded_sz; decoded_reg_val = priv->info->segment_reg(start_addr, end_addr); writel(decoded_reg_val, &priv->regs->segment_addr[cs]); - dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%x, end: 0x%x\n", + dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%lx, end: 0x%lx\n", cs, decoded_reg_val, start_addr, end_addr); } } @@ -851,13 +920,13 @@ static int aspeed_spi_decoded_ranges_sanity(struct udevice *bus) * address base are monotonic increasing with CE#. */ for (cs = plat->max_cs - 1; cs > 0; cs--) { - if ((u32)priv->flashes[cs].ahb_base != 0 && - (u32)priv->flashes[cs].ahb_base < - (u32)priv->flashes[cs - 1].ahb_base + + if (priv->flashes[cs].ahb_base != 0 && + priv->flashes[cs].ahb_base < + priv->flashes[cs - 1].ahb_base + priv->flashes[cs - 1].ahb_decoded_sz) { - dev_err(bus, "decoded range overlay 0x%08x 0x%08x\n", - (u32)priv->flashes[cs].ahb_base, - (u32)priv->flashes[cs - 1].ahb_base); + dev_err(bus, "decoded range overlay 0x%08lx 0x%08lx\n", + priv->flashes[cs].ahb_base, + priv->flashes[cs - 1].ahb_base); return -EINVAL; } } @@ -895,14 +964,13 @@ static int aspeed_spi_read_fixed_decoded_ranges(struct udevice *bus) return ret; for (i = 0; i < count; i++) { - priv->flashes[ranges[i].cs].ahb_base = - (void __iomem *)ranges[i].ahb_base; + priv->flashes[ranges[i].cs].ahb_base = ranges[i].ahb_base; priv->flashes[ranges[i].cs].ahb_decoded_sz = ranges[i].sz; } for (i = 0; i < plat->max_cs; i++) { - dev_dbg(bus, "ahb_base: 0x%p, size: 0x%08x\n", + dev_dbg(bus, "ahb_base: 0x%lx, size: 0x%08zx\n", priv->flashes[i].ahb_base, priv->flashes[i].ahb_decoded_sz); } @@ -1063,6 +1131,32 @@ static const struct aspeed_spi_info ast2600_spi_info = { .get_clk_setting = ast2600_get_clk_setting, }; +static const struct aspeed_spi_info ast2700_fmc_info = { + .io_mode_mask = 0xf0000000, + .max_bus_width = 4, + .min_decoded_sz = 0x10000, + .clk_ctrl_mask = 0x0f000f00, + .set_4byte = ast2700_spi_chip_set_4byte, + .segment_start = ast2700_spi_segment_start, + .segment_end = ast2700_spi_segment_end, + .segment_reg = ast2700_spi_segment_reg, + .adjust_decoded_sz = ast2700_adjust_decoded_size, + .get_clk_setting = ast2600_get_clk_setting, +}; + +static const struct aspeed_spi_info ast2700_spi_info = { + .io_mode_mask = 0xf0000000, + .max_bus_width = 4, + .min_decoded_sz = 0x10000, + .clk_ctrl_mask = 0x0f000f00, + .set_4byte = ast2700_spi_chip_set_4byte, + .segment_start = ast2700_spi_segment_start, + .segment_end = ast2700_spi_segment_end, + .segment_reg = ast2700_spi_segment_reg, + .adjust_decoded_sz = ast2700_adjust_decoded_size, + .get_clk_setting = ast2600_get_clk_setting, +}; + static int aspeed_spi_claim_bus(struct udevice *dev) { struct udevice *bus = dev->parent; @@ -1129,7 +1223,8 @@ static int apseed_spi_of_to_plat(struct udevice *bus) return -EINVAL; } - plat->ahb_base = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahb_sz); + plat->ahb_base = + (uintptr_t)devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahb_sz); if (!plat->ahb_base) { dev_err(bus, "wrong AHB base\n"); return -EINVAL; @@ -1147,8 +1242,8 @@ static int apseed_spi_of_to_plat(struct udevice *bus) plat->hclk_rate = clk_get_rate(&hclk); - dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n", - (u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz); + dev_dbg(bus, "ctrl_base = 0x%p, ahb_base = 0x%lx, size = 0x%llx\n", + priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz); dev_dbg(bus, "hclk = %dMHz, max_cs = %d\n", plat->hclk_rate / 1000000, plat->max_cs); @@ -1199,6 +1294,8 @@ static const struct udevice_id aspeed_spi_ids[] = { { .compatible = "aspeed,ast2500-spi", .data = (ulong)&ast2500_spi_info, }, { .compatible = "aspeed,ast2600-fmc", .data = (ulong)&ast2600_fmc_info, }, { .compatible = "aspeed,ast2600-spi", .data = (ulong)&ast2600_spi_info, }, + { .compatible = "aspeed,ast2700-fmc", .data = (ulong)&ast2700_fmc_info, }, + { .compatible = "aspeed,ast2700-spi", .data = (ulong)&ast2700_spi_info, }, { } }; diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index ab4878ebae4..e28fd9af1d0 100644 --- a/drivers/spmi/Kconfig +++ b/drivers/spmi/Kconfig @@ -3,7 +3,7 @@ menu "SPMI support" config SPMI bool "Enable SPMI bus support" depends on DM - ---help--- + help Select this to enable to support SPMI bus. SPMI (System Power Management Interface) bus is used to connect PMIC devices on various SoCs. @@ -11,13 +11,13 @@ config SPMI config SPMI_MSM bool "Support Qualcomm SPMI bus" depends on SPMI - ---help--- + help Support SPMI bus implementation found on Qualcomm Snapdragon SoCs. config SPMI_SANDBOX bool "Support for Sandbox SPMI bus" depends on SPMI - ---help--- + help Demo SPMI bus implementation. Emulates part of PM8916 as single - slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3. + slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3. endmenu diff --git a/drivers/sysinfo/Kconfig b/drivers/sysinfo/Kconfig index df83df69ffb..6922dac9170 100644 --- a/drivers/sysinfo/Kconfig +++ b/drivers/sysinfo/Kconfig @@ -59,4 +59,12 @@ config SYSINFO_GPIO This ternary number is then mapped to a board revision name using device tree properties. +config SYSINFO_TQ_EEPROM + bool "Enable TQ-Systems EEPROM sysinfo driver" + depends on I2C_EEPROM + depends on SPL_I2C_EEPROM || !SPL_SYSINFO + help + Support querying EEPROM of TQ-Systems SOMs to determine board + information. + endif diff --git a/drivers/sysinfo/Makefile b/drivers/sysinfo/Makefile index 26ca3150999..d21fb3c2270 100644 --- a/drivers/sysinfo/Makefile +++ b/drivers/sysinfo/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_SYSINFO_IOT2050) += iot2050.o obj-$(CONFIG_SYSINFO_RCAR3) += rcar3.o obj-$(CONFIG_SYSINFO_SANDBOX) += sandbox.o obj-$(CONFIG_SYSINFO_SMBIOS) += smbios.o +obj-$(CONFIG_SYSINFO_TQ_EEPROM) += tq_eeprom.o diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c index f04998ef8bb..d18a168614e 100644 --- a/drivers/sysinfo/sysinfo-uclass.c +++ b/drivers/sysinfo/sysinfo-uclass.c @@ -42,6 +42,16 @@ int sysinfo_detect(struct udevice *dev) return ret; } +int sysinfo_get_and_detect(struct udevice **devp) +{ + int ret = sysinfo_get(devp); + + if (!ret) + ret = sysinfo_detect(*devp); + + return ret; +} + int sysinfo_get_fit_loadable(struct udevice *dev, int index, const char *type, const char **strp) { @@ -152,5 +162,5 @@ UCLASS_DRIVER(sysinfo) = { .id = UCLASS_SYSINFO, .name = "sysinfo", .post_bind = dm_scan_fdt_dev, - .per_device_auto = sizeof(bool), + .per_device_auto = sizeof(struct sysinfo_priv), }; diff --git a/drivers/sysinfo/tq_eeprom.c b/drivers/sysinfo/tq_eeprom.c new file mode 100644 index 00000000000..63be07b664e --- /dev/null +++ b/drivers/sysinfo/tq_eeprom.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Nora Schiffer + */ + +#include <dm.h> +#include <log.h> +#include <net.h> +#include <dm/device_compat.h> +#include <linux/build_bug.h> +#include <linux/ctype.h> +#include <nvmem.h> +#include <sysinfo/tq_eeprom.h> + +#define TQ_EE_RSV1_BYTES 10 +#define TQ_EE_SERIAL_BYTES 8 +#define TQ_EE_RSV2_BYTES 8 +#define TQ_EE_BDID_BYTES 0x40 + +struct tq_eeprom_data { + u8 mac[ETH_ALEN]; /* 0x20 ... 0x25 */ + u8 rsv1[TQ_EE_RSV1_BYTES]; + u8 serial[TQ_EE_SERIAL_BYTES]; /* 0x30 ... 0x37 */ + u8 rsv2[TQ_EE_RSV2_BYTES]; + u8 id[TQ_EE_BDID_BYTES]; /* 0x40 ... 0x7f */ +}; + +static_assert(sizeof(struct tq_eeprom_data) == 0x60, + "struct tq_eeprom_data has incorrect size"); + +/** + * struct sysinfo_tq_eeprom_priv - sysinfo private data + */ +struct sysinfo_tq_eeprom_priv { + struct nvmem_cell device_info_cell; + + /* Reserve extra space for \0 in id and serial */ + char id[TQ_EE_BDID_BYTES + 1]; + char serial[TQ_EE_SERIAL_BYTES + 1]; + u8 mac[ETH_ALEN]; +}; + +static void tq_eeprom_parse_id(struct udevice *dev, const struct tq_eeprom_data *data) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < sizeof(data->id); i++) { + if (!(isprint(data->id[i]) && isascii(data->id[i]))) + break; + } + + if (i == 0) + dev_warn(dev, "no valid model name in EEPROM\n"); + + snprintf(priv->id, sizeof(priv->id), "%.*s", i, data->id); +} + +static int tq_eeprom_serial_len(const struct tq_eeprom_data *data, bool allow_upper) +{ + int i; + + for (i = 0; i < sizeof(data->serial); i++) { + if (!(isdigit(data->serial[i]) || (allow_upper && isupper(data->serial[i])))) + break; + } + + return i; +} + +static void tq_eeprom_parse_serial(struct udevice *dev, const struct tq_eeprom_data *data) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + bool use_new_format; + int len; + + use_new_format = data->serial[0] == 'T' && data->serial[1] == 'Q'; + + len = tq_eeprom_serial_len(data, use_new_format); + + /* For now, only serial numbers with the exact size of the field are accepted */ + if (len != sizeof(data->serial)) { + dev_warn(dev, "no valid serial number in EEPROM\n"); + len = 0; + } + + snprintf(priv->serial, sizeof(priv->serial), "%.*s", len, data->serial); +} + +static int tq_eeprom_dump(const struct sysinfo_tq_eeprom_priv *priv) +{ + printf("TQ EEPROM:\n"); + printf(" ID: %s\n", priv->id[0] ? priv->id : "<invalid>"); + printf(" SN: %s\n", priv->serial[0] ? priv->serial : "<invalid>"); + printf(" MAC: "); + if (is_valid_ethaddr(priv->mac)) + printf("%pM\n", priv->mac); + else + printf("<invalid>\n"); + + return 0; +} + +static int sysinfo_tq_eeprom_detect(struct udevice *dev) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + struct tq_eeprom_data data; + int ret; + + ret = nvmem_cell_read(&priv->device_info_cell, (u8 *)&data, sizeof(data)); + if (ret < 0) { + dev_err(dev, "EEPROM read failed: %d\n", ret); + return ret; + } + + tq_eeprom_parse_id(dev, &data); + tq_eeprom_parse_serial(dev, &data); + memcpy(priv->mac, data.mac, ETH_ALEN); + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + tq_eeprom_dump(priv); + + return 0; +} + +static int sysinfo_tq_eeprom_get_str(struct udevice *dev, int id, size_t size, char *val) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_TQ_MODEL: + if (!priv->id[0]) + return -ENODATA; + + strlcpy(val, priv->id, size); + return 0; + + case SYSID_TQ_SERIAL: + if (!priv->serial[0]) + return -ENODATA; + + strlcpy(val, priv->serial, size); + return 0; + + default: + return -EINVAL; + } +} + +static int sysinfo_tq_eeprom_get_data(struct udevice *dev, int id, void **data, size_t *size) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + + switch (id) { + case SYSID_TQ_MAC_ADDR: + if (!is_valid_ethaddr(priv->mac)) + return -ENODATA; + + *data = priv->mac; + *size = sizeof(priv->mac); + + return 0; + + default: + return -EINVAL; + } +} + +static const struct sysinfo_ops sysinfo_tq_eeprom_ops = { + .detect = sysinfo_tq_eeprom_detect, + .get_str = sysinfo_tq_eeprom_get_str, + .get_data = sysinfo_tq_eeprom_get_data, +}; + +static int sysinfo_tq_eeprom_probe(struct udevice *dev) +{ + struct sysinfo_tq_eeprom_priv *priv = dev_get_priv(dev); + int ret; + + ret = nvmem_cell_get_by_name(dev, "device_info", &priv->device_info_cell); + if (ret) { + dev_err(dev, "device_info not found: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct udevice_id sysinfo_tq_eeprom_ids[] = { + { .compatible = "tq,eeprom-sysinfo" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sysinfo_tq_eeprom) = { + .name = "sysinfo_tq_eeprom", + .id = UCLASS_SYSINFO, + .of_match = sysinfo_tq_eeprom_ids, + .ops = &sysinfo_tq_eeprom_ops, + .priv_auto = sizeof(struct sysinfo_tq_eeprom_priv), + .probe = sysinfo_tq_eeprom_probe, +}; diff --git a/drivers/sysreset/sysreset_qemu_virt_ctrl.c b/drivers/sysreset/sysreset_qemu_virt_ctrl.c index e7cacc9b6e9..ce15e776f8f 100644 --- a/drivers/sysreset/sysreset_qemu_virt_ctrl.c +++ b/drivers/sysreset/sysreset_qemu_virt_ctrl.c @@ -8,6 +8,7 @@ #include <dm.h> #include <qemu_virt_ctrl.h> #include <sysreset.h> +#include <mapmem.h> #include <asm/io.h> #include <linux/err.h> @@ -24,6 +25,7 @@ static int qemu_virt_ctrl_request(struct udevice *dev, enum sysreset_t type) { struct qemu_virt_ctrl_plat *plat = dev_get_plat(dev); + void __iomem *reg = map_sysmem(plat->reg + VIRT_CTRL_REG_CMD, 0x4); u32 val; switch (type) { @@ -38,7 +40,7 @@ static int qemu_virt_ctrl_request(struct udevice *dev, enum sysreset_t type) return -EPROTONOSUPPORT; } - writel(val, plat->reg + VIRT_CTRL_REG_CMD); + __raw_writel(val, reg); return -EINPROGRESS; } diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 91c39aa4dee..9ad0d699850 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -13,9 +13,9 @@ config IMX_THERMAL depends on MX6 || MX7 help Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs. - It supports one critical trip point and one passive trip point. The - cpufreq is used as the cooling device to throttle CPUs when the - passive trip is crossed. + It supports one critical trip point and one passive trip point. The + cpufreq is used as the cooling device to throttle CPUs when the + passive trip is crossed. config IMX_SCU_THERMAL bool "Temperature sensor driver for NXP i.MX8" @@ -27,11 +27,12 @@ config IMX_SCU_THERMAL trip is crossed config IMX_TMU - bool "Thermal Management Unit driver for NXP i.MX8M and iMX93" - depends on ARCH_IMX8M || IMX93 - help - Support for Temperature sensors on NXP i.MX8M and iMX93. - It supports one critical trip point and one passive trip point. + bool "Thermal Management Unit driver for NXP i.MX8M / i.MX93 and QorIQ" + depends on ARCH_IMX8M || IMX93 || FSL_LAYERSCAPE + help + Support for the NXP Thermal Management Unit (TMU) sensors on + i.MX8M, i.MX93 and on QorIQ/Layerscape SoCs (LX2160A, + LS1028A, LS1088A, ...). The boot is hold to the cool device to throttle CPUs when the passive trip is crossed @@ -44,15 +45,22 @@ config RCAR_GEN3_THERMAL driver into the U-Boot thermal framework. config TI_DRA7_THERMAL - bool "Temperature sensor driver for TI dra7xx SOCs" - help - Enable thermal support for for the Texas Instruments DRA752 SoC family. - The driver supports reading CPU temperature. + bool "Temperature sensor driver for TI dra7xx SOCs" + help + Enable thermal support for the Texas Instruments DRA752 SoC family. + The driver supports reading CPU temperature. config TI_LM74_THERMAL - bool "Temperature sensor driver for TI LM74 chip" - help - Enable thermal support for the Texas Instruments LM74 chip. - The driver supports reading CPU temperature. + bool "Temperature sensor driver for TI LM74 chip" + help + Enable thermal support for the Texas Instruments LM74 chip. + The driver supports reading CPU temperature. + +config DM_THERMAL_JC42 + bool "JEDEC JC-42.4/TSE2004av SPD temperature sensor" + depends on DM_I2C + help + Enable support for the JEDEC JC-42.4 temperature sensor found + on the SPD bus of DDR3 and DDR4 DIMMs (TSE2004av and compatible). endif # if DM_THERMAL diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index b6f06c00ed9..c9fa7561b45 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_RCAR_GEN3_THERMAL) += rcar_gen3_thermal.o obj-$(CONFIG_SANDBOX) += thermal_sandbox.o obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o obj-$(CONFIG_TI_LM74_THERMAL) += ti-lm74.o +obj-$(CONFIG_DM_THERMAL_JC42) += jc42.o diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index 1bde4d07f52..da0825ecd34 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -6,14 +6,17 @@ #include <config.h> #include <asm/io.h> -#include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> +#if IS_ENABLED(CONFIG_ARCH_IMX8M) || IS_ENABLED(CONFIG_IMX93) +#include <asm/arch/clock.h> +#endif #include <dm.h> #include <dm/device_compat.h> #include <dm/device-internal.h> #include <dm/device.h> #include <errno.h> #include <fuse.h> +#include <linux/bitops.h> #include <linux/delay.h> #include <malloc.h> #include <thermal.h> @@ -22,10 +25,12 @@ #define FLAGS_VER2 0x1 #define FLAGS_VER3 0x2 #define FLAGS_VER4 0x4 +#define FLAGS_QORIQ 0x8 #define TMR_DISABLE 0x0 #define TMR_ME 0x80000000 #define TMR_ALPF 0x0c000000 +#define QORIQ_TMR_ALPF (0x3 << 24) /* QorIQ ALPF lives at bits[25:24] */ #define TMTMIR_DEFAULT 0x00000002 #define TIER_DISABLE 0x0 @@ -33,7 +38,19 @@ #define TER_ADC_PD 0x40000000 #define TER_ALPF 0x3 +/* default CPU delay time to cool down if over temperature */ #define IMX_TMU_POLLING_DELAY_MS 5000 + +/* TRITSR - QorIQ Immediate Temperature Site Register. + * + * Per LX2160A Reference Manual, Rev. 1 (10/2021) section 28.3.1.24 + * the calibrated reading lives in TEMP[8:0] and is reported in + * degrees Kelvin (integer). The QorIQ regs_v1 variant has no + * fractional 0.5 degC bit, unlike the i.MX regs_v2 / VER4 layouts. + */ +#define TRITSR_V BIT(31) /* reading valid */ +#define TRITSR_TEMP_MASK GENMASK(8, 0) /* degrees Kelvin */ +#define TRITSR_KELVIN_OFFSET 273 /* TEMP[8:0] - 273 = degC */ /* * i.MX TMU Registers */ @@ -148,11 +165,37 @@ struct imx_tmu_regs_v3 { u32 trim; }; +/* + * fsl,qoriq-tmu (LX2160A, LS1028A, LS1088A, ...). Same TMU IP family as + * the i.MX "regs_v1" layout but: site-enable is a discrete TMSR at 0x08 + * (TMTMIR moves to 0x0C), and the temperature range registers are + * variable-length at 0xF10 (a SoC may use fewer than 16). Calibration is + * taken from the DT (fsl,tmu-range / fsl,tmu-calibration) exactly like + * the i.MX regs_v1 path, so qoriq reuses imx_tmu_calibration()'s scheme. + */ +struct qoriq_tmu_regs { + u32 tmr; /* 0x000 mode */ + u32 tsr; /* 0x004 status */ + u32 tmsr; /* 0x008 monitor-site enable (bit N = site N) */ + u32 tmtmir; /* 0x00C measurement interval */ + u8 res0[0x10]; + u32 tier; /* 0x020 interrupt enable */ + u32 tidr; /* 0x024 interrupt detect */ + u8 res1[0x58]; + u32 ttcfgr; /* 0x080 temperature config (cal walk) */ + u32 tscfgr; /* 0x084 sensor config (cal walk) */ + u8 res2[0x78]; + struct imx_tmu_site_regs site[SITES_MAX]; /* 0x100 */ + u8 res3[0xd10]; + u32 ttrcr[16]; /* 0xF10 temperature range control */ +}; + union tmu_regs { struct imx_tmu_regs regs_v1; struct imx_tmu_regs_v2 regs_v2; struct imx_tmu_regs_v3 regs_v3; struct imx_tmu_regs_v4 regs_v4; + struct qoriq_tmu_regs regs_qoriq; }; struct imx_tmu_plat { @@ -189,6 +232,9 @@ static int read_temperature(struct udevice *dev, int *temp) } else if (drv_data & FLAGS_VER4) { val = readl(&pdata->regs->regs_v4.tritsr0); valid = val & 0x80000000; + } else if (drv_data & FLAGS_QORIQ) { + val = readl(&pdata->regs->regs_qoriq.site[pdata->id].tritsr); + valid = val & TRITSR_V; } else { val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr); valid = val & 0x80000000; @@ -213,6 +259,19 @@ static int read_temperature(struct udevice *dev, int *temp) /* Convert Kelvin to Celsius */ *temp -= 273000; + } else if (drv_data & FLAGS_QORIQ) { + /* + * LX2160A Reference Manual, Rev. 1 (10/2021) + * section 28.3.1.24: TEMP[8:0] is the calibrated + * reading in degrees Kelvin (integer, no 0.5 degC + * bit on the regs_v1 variant). The calibration + * point examples in the same RM section 28.1.3 + * use the same Kelvin/Celsius offset: + * TTR0CR=0x800000E6 -> 230K (-43 degC) + * TTR1CR=0x8001017D -> 381K (108 degC) + */ + *temp = ((val & TRITSR_TEMP_MASK) - + TRITSR_KELVIN_OFFSET) * 1000; } else { *temp = (val & 0xff) * 1000; } @@ -265,6 +324,35 @@ static int imx_tmu_calibration(struct udevice *dev) if (drv_data & (FLAGS_VER2 | FLAGS_VER3)) return 0; + if (drv_data & FLAGS_QORIQ) { + const fdt32_t *ranges; + int n; + + ranges = dev_read_prop(dev, "fsl,tmu-range", &len); + if (!ranges || len % 4 || + len / 4 > (int)ARRAY_SIZE(pdata->regs->regs_qoriq.ttrcr)) { + dev_err(dev, "TMU: missing/invalid fsl,tmu-range\n"); + return -ENODEV; + } + n = len / 4; + for (i = 0; i < n; i++) + writel(fdt32_to_cpu(ranges[i]), + &pdata->regs->regs_qoriq.ttrcr[i]); + + calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len); + if (!calibration || len % 8) { + dev_err(dev, "TMU: invalid calibration data.\n"); + return -ENODEV; + } + for (i = 0; i < len; i += 8, calibration += 2) { + writel(fdt32_to_cpu(*calibration), + &pdata->regs->regs_qoriq.ttcfgr); + writel(fdt32_to_cpu(*(calibration + 1)), + &pdata->regs->regs_qoriq.tscfgr); + } + return 0; + } + if (drv_data & FLAGS_VER4) { calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len); if (!calibration || len % 8 || len > 128) { @@ -402,6 +490,18 @@ static inline void imx_tmu_mx8mq_init(struct udevice *dev) { } static void imx_tmu_arch_init(struct udevice *dev) { + /* + * QorIQ takes its calibration from the DT (fsl,tmu-calibration), + * not from OCOTP fuses, so it has no per-SoC arch init. The #if + * below is still required: the i.MX SoC-ID helpers and fuse API + * (<asm/arch/sys_proto.h>) do not exist in a Layerscape build, so + * the references must be removed at compile time, not merely + * skipped at runtime. + */ + if (dev_get_driver_data(dev) & FLAGS_QORIQ) + return; + +#if IS_ENABLED(CONFIG_ARCH_IMX8M) || IS_ENABLED(CONFIG_IMX93) if (is_imx8mm() || is_imx8mn()) imx_tmu_mx8mm_mx8mn_init(dev); else if (is_imx8mp()) @@ -412,6 +512,7 @@ static void imx_tmu_arch_init(struct udevice *dev) imx_tmu_mx8mq_init(dev); else dev_err(dev, "Unsupported SoC, TMU calibration not loaded!\n"); +#endif } static void imx_tmu_init(struct udevice *dev) @@ -443,6 +544,15 @@ static void imx_tmu_init(struct udevice *dev) /* Set update_interval */ writel(TMTMIR_DEFAULT, &pdata->regs->regs_v4.tmtmir); + } else if (drv_data & FLAGS_QORIQ) { + /* Disable monitoring */ + writel(TMR_DISABLE, &pdata->regs->regs_qoriq.tmr); + + /* Disable interrupt, using polling instead */ + writel(TIER_DISABLE, &pdata->regs->regs_qoriq.tier); + + /* Set update_interval */ + writel(TMTMIR_DEFAULT, &pdata->regs->regs_qoriq.tmtmir); } else { /* Disable monitoring */ writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr); @@ -511,6 +621,18 @@ static int imx_tmu_enable_msite(struct udevice *dev) /* Enable ME */ reg |= TMR_ME; writel(reg, &pdata->regs->regs_v4.tmr); + } else if (drv_data & FLAGS_QORIQ) { + /* Clear ME, enable every site at once via the discrete TMSR */ + reg = readl(&pdata->regs->regs_qoriq.tmr); + reg &= ~TMR_ME; + writel(reg, &pdata->regs->regs_qoriq.tmr); + + writel(GENMASK(SITES_MAX - 1, 0), + &pdata->regs->regs_qoriq.tmsr); + + reg |= QORIQ_TMR_ALPF; + reg |= TMR_ME; + writel(reg, &pdata->regs->regs_qoriq.tmr); } else { /* Clear the ME before setting MSITE and ALPF*/ reg = readl(&pdata->regs->regs_v1.tmr); @@ -650,6 +772,7 @@ static const struct udevice_id imx_tmu_ids[] = { { .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, }, { .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, }, { .compatible = "fsl,imx93-tmu", .data = FLAGS_VER4, }, + { .compatible = "fsl,qoriq-tmu", .data = FLAGS_QORIQ, }, { } }; diff --git a/drivers/thermal/jc42.c b/drivers/thermal/jc42.c new file mode 100644 index 00000000000..6945260e8b0 --- /dev/null +++ b/drivers/thermal/jc42.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Free Mobile - Vincent Jardin + * + * JEDEC JC-42.4 / TSE2004av Temperature Sensor driver. + * + * Generic I2C temperature sensor of the Serial Presence Detect (SPD) + * bus of DDR3 and DDR4 SO-DIMMs / UDIMMs / RDIMMs per the JEDEC + * JC-42.4 standard. The TSE2004av variant adds an integrated SPD + * EEPROM, but the thermal register interface is the same and is + * what this driver exposes. + * + * Register layout (subset): + * 0x05 Ambient temperature, 16-bit big-endian: + * bit 15 : T_CRIT alarm flag (read-only) + * bit 14 : T_HIGH alarm flag (read-only) + * bit 13 : T_LOW alarm flag (read-only) + * bit 12 : sign (two's-complement within bits[12:0]) + * bits[11:0]: magnitude * 16 (LSB = 0.0625 degC = 62.5 mC) + * 0x06 Manufacturer ID (16-bit BE, JEP-106 vendor code) + * 0x07 Device ID + Revision (upper byte = ID, lower = revision) + * ... + */ + +#include <dm.h> +#include <i2c.h> +#include <thermal.h> +#include <linux/bitops.h> + +#define JC42_REG_TEMP 0x05 + +#define JC42_TEMP_SIGN BIT(12) +#define JC42_TEMP_MAGNITUDE GENMASK(11, 0) + +static int jc42_get_temp(struct udevice *dev, int *temp) +{ + u8 buf[2]; + int ret; + int mag; + + ret = dm_i2c_read(dev, JC42_REG_TEMP, buf, sizeof(buf)); + if (ret) + return ret; + + mag = ((buf[0] << 8) | buf[1]) & (JC42_TEMP_SIGN | JC42_TEMP_MAGNITUDE); + if (mag & JC42_TEMP_SIGN) + mag -= (JC42_TEMP_SIGN << 1); + + /* + * mag is in units of 1/16 degC. Multiply first to keep one + * extra bit of precision before the divide. Worst-case range + * for a 13-bit signed value is +/-4096, so the product fits + * comfortably in an int (~4.1M mC). + */ + *temp = mag * 1000 / 16; + + return 0; +} + +static const struct dm_thermal_ops jc42_ops = { + .get_temp = jc42_get_temp, +}; + +/* + * Optional DT label property override: it replace the default DM + * device name (the ofnode name, eg "temp@18") so + * temperature list or temperature get commands + * show a human-meaningful identifier such as "ddr-top" or + * "ddr-bottom". + * It mirrors the Linux hwmon binding which uses label for the + * per-sensor display name. + */ +static int jc42_bind(struct udevice *dev) +{ + const char *label = dev_read_string(dev, "label"); + + if (label && *label) + return device_set_name(dev, label); + return 0; +} + +static const struct udevice_id jc42_match[] = { + { .compatible = "jedec,jc-42.4-temp" }, + { } +}; + +U_BOOT_DRIVER(jc42_thermal) = { + .name = "jc42_thermal", + .id = UCLASS_THERMAL, + .of_match = jc42_match, + .bind = jc42_bind, + .ops = &jc42_ops, +}; diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c index dc869f108e4..643971e12cd 100644 --- a/drivers/thermal/ti-bandgap.c +++ b/drivers/thermal/ti-bandgap.c @@ -176,7 +176,7 @@ static int ti_bandgap_probe(struct udevice *dev) { struct ti_bandgap *bgp = dev_get_priv(dev); - bgp->base = devfdt_get_addr_index(dev, 1); + bgp->base = dev_read_addr_index(dev, 1); return 0; } diff --git a/drivers/timer/goldfish_timer.c b/drivers/timer/goldfish_timer.c index 70673bbd93c..59ce43fcb46 100644 --- a/drivers/timer/goldfish_timer.c +++ b/drivers/timer/goldfish_timer.c @@ -31,8 +31,8 @@ static u64 goldfish_timer_get_count(struct udevice *dev) * We must read LOW before HIGH to latch the high 32-bit value * and ensure a consistent 64-bit timestamp. */ - low = readl(priv->base + TIMER_TIME_LOW); - high = readl(priv->base + TIMER_TIME_HIGH); + low = __raw_readl(priv->base + TIMER_TIME_LOW); + high = __raw_readl(priv->base + TIMER_TIME_HIGH); time = ((u64)high << 32) | low; @@ -45,8 +45,10 @@ static int goldfish_timer_of_to_plat(struct udevice *dev) fdt_addr_t addr; addr = dev_read_addr(dev); - if (addr != FDT_ADDR_T_NONE) - plat->reg = addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = addr; return 0; } diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c index 821b681a232..4d1c6b5cef2 100644 --- a/drivers/timer/orion-timer.c +++ b/drivers/timer/orion-timer.c @@ -2,6 +2,7 @@ #include <asm/io.h> #include <config.h> #include <div64.h> +#include <dm.h> #include <dm/device.h> #include <dm/fdtaddr.h> #include <timer.h> @@ -113,7 +114,7 @@ static int orion_timer_probe(struct udevice *dev) enum input_clock_type type = dev_get_driver_data(dev); struct orion_timer_priv *priv = dev_get_priv(dev); - priv->base = devfdt_remap_addr_index(dev, 0); + priv->base = dev_remap_addr_index(dev, 0); if (!priv->base) { debug("unable to map registers\n"); return -ENOMEM; diff --git a/drivers/timer/sp804_timer.c b/drivers/timer/sp804_timer.c index 05532e3330c..d1a5fc8c5bf 100644 --- a/drivers/timer/sp804_timer.c +++ b/drivers/timer/sp804_timer.c @@ -44,7 +44,7 @@ static int sp804_clk_of_to_plat(struct udevice *dev) struct sp804_timer_plat *plat = dev_get_plat(dev); plat->base = dev_read_addr(dev); - if (!plat->base) + if (plat->base == FDT_ADDR_T_NONE) return -ENOENT; return 0; diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index 14a94f8d4a8..46805eaa013 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -889,7 +889,7 @@ static int cr50_i2c_probe(struct udevice *dev) return 0; } -struct acpi_ops cr50_acpi_ops = { +static const struct acpi_ops cr50_acpi_ops = { .fill_ssdt = cr50_acpi_fill_ssdt, }; diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig index 49472933de3..0b5df54e8fb 100644 --- a/drivers/ufs/Kconfig +++ b/drivers/ufs/Kconfig @@ -19,7 +19,7 @@ config UFS_AMD_VERSAL2 config UFS_CADENCE bool "Cadence platform driver for UFS" depends on UFS - help + help This selects the platform driver for the Cadence UFS host controller present on present TI's J721e devices. @@ -51,7 +51,7 @@ config UFS_PCI config UFS_QCOM bool "Qualcomm Host Controller driver for UFS" depends on UFS && ARCH_SNAPDRAGON - help + help This selects the platform driver for the UFS host controller present on Qualcomm Snapdragon SoCs. diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c index dc40ee62daf..f5f5a6eb110 100644 --- a/drivers/ufs/ufs-qcom.c +++ b/drivers/ufs/ufs-qcom.c @@ -30,6 +30,7 @@ #define UFS_CPU_MAX_BANDWIDTH 819200 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable); +static u32 ufs_qcom_get_core_clk_unipro_max_freq(struct ufs_hba *hba); static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv) { @@ -47,17 +48,6 @@ static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv) return 0; } -static int ufs_qcom_init_clks(struct ufs_qcom_priv *priv) -{ - int err; - struct udevice *dev = priv->hba->dev; - - err = clk_get_bulk(dev, &priv->clks); - if (err) - return err; - - return 0; -} static int ufs_qcom_check_hibern8(struct ufs_hba *hba) { @@ -557,10 +547,45 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable) static int ufs_qcom_init(struct ufs_hba *hba) { struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + struct udevice *dev = hba->dev; + struct clk clk; + u32 max_freq; + long rate; int err; priv->hba = hba; + /* Get maximum frequency for core_clk_unipro from device tree */ + max_freq = ufs_qcom_get_core_clk_unipro_max_freq(hba); + + /* Get and configure core_clk_unipro */ + err = clk_get_by_name(dev, "core_clk_unipro", &clk); + if (err) { + dev_err(dev, "Failed to get core_clk_unipro: %d\n", err); + return err; + } + + rate = clk_set_rate(&clk, max_freq); + if (rate < 0) { + dev_err(dev, "Failed to set core_clk_unipro rate to %u Hz: %ld\n", + max_freq, rate); + } + + /* Get all clocks */ + err = clk_get_bulk(dev, &priv->clks); + if (err) { + dev_err(dev, "clk_get_bulk failed: %d\n", err); + return err; + } + + /* Enable clocks */ + err = ufs_qcom_enable_clks(priv); + if (err) { + dev_err(dev, "failed to enable clocks: %d\n", err); + clk_release_bulk(&priv->clks); + return err; + } + /* setup clocks */ ufs_qcom_setup_clocks(hba, true, PRE_CHANGE); @@ -579,14 +604,7 @@ static int ufs_qcom_init(struct ufs_hba *hba) priv->hw_ver.minor, priv->hw_ver.step); - err = ufs_qcom_init_clks(priv); - if (err) { - dev_err(hba->dev, "failed to initialize clocks, err:%d\n", err); - return err; - } - ufs_qcom_advertise_quirks(hba); - ufs_qcom_setup_clocks(hba, true, POST_CHANGE); return 0; } diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 93c5ee69b25..05ac388ecf2 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -1,7 +1,7 @@ menuconfig USB bool "USB support" select BLK - ---help--- + help Universal Serial Bus (USB) is a specification for a serial bus subsystem which offers higher speeds and more features than the traditional PC serial port. The bus supplies power to peripherals @@ -94,7 +94,7 @@ comment "USB peripherals" config USB_STORAGE bool "USB Mass Storage support" - ---help--- + help Say Y here if you want to connect USB mass storage devices to your board's USB port. @@ -103,7 +103,7 @@ config USB_KEYBOARD depends on DM_USB select DM_KEYBOARD select SYS_STDIO_DEREGISTER - ---help--- + help Say Y here if you want to use a USB keyboard for U-Boot command line input. @@ -111,7 +111,7 @@ config USB_ONBOARD_HUB bool "Onboard USB hub support" depends on DM_USB select DEVRES - ---help--- + help Say Y here if you want to support discrete onboard USB hubs that don't require an additional control bus for initialization, but need some non-trivial form of initialization, such as enabling a @@ -163,17 +163,17 @@ choice prompt "USB keyboard polling" default SYS_USB_EVENT_POLL_VIA_INT_QUEUE if ARCH_SUNXI default SYS_USB_EVENT_POLL - ---help--- + help Enable a polling mechanism for USB keyboard. config SYS_USB_EVENT_POLL - bool "Interrupt polling" + bool "Interrupt polling" config SYS_USB_EVENT_POLL_VIA_INT_QUEUE - bool "Poll via interrupt queue" + bool "Poll via interrupt queue" config SYS_USB_EVENT_POLL_VIA_CONTROL_EP - bool "Poll via control EP" + bool "Poll via control EP" endchoice diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c index 99519602eb2..8cb5796b6ad 100644 --- a/drivers/usb/dwc3/dwc3-am62.c +++ b/drivers/usb/dwc3/dwc3-am62.c @@ -105,7 +105,7 @@ static void dwc3_ti_am62_glue_configure(struct udevice *dev, int index, writel(reg, usbss + USBSS_MODE_CONTROL); } -struct dwc3_glue_ops ti_am62_ops = { +static const struct dwc3_glue_ops ti_am62_ops = { .glue_configure = dwc3_ti_am62_glue_configure, }; diff --git a/drivers/usb/dwc3/dwc3-generic-sti.c b/drivers/usb/dwc3/dwc3-generic-sti.c index b34f5ceceac..ce195b2553b 100644 --- a/drivers/usb/dwc3/dwc3-generic-sti.c +++ b/drivers/usb/dwc3/dwc3-generic-sti.c @@ -114,7 +114,7 @@ static void dwc3_stih407_glue_configure(struct udevice *dev, int index, setbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); }; -struct dwc3_glue_ops stih407_ops = { +static const struct dwc3_glue_ops stih407_ops = { .glue_configure = dwc3_stih407_glue_configure, }; diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 22b9ef0b24e..2356b3bc0aa 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -330,7 +330,7 @@ void dwc3_imx8mp_glue_configure(struct udevice *dev, int index, unmap_physmem(base, MAP_NOCACHE); } -struct dwc3_glue_ops imx8mp_ops = { +static const struct dwc3_glue_ops imx8mp_ops = { .glue_configure = dwc3_imx8mp_glue_configure, }; @@ -414,7 +414,7 @@ enum dwc3_omap_utmi_mode { unmap_physmem(base, MAP_NOCACHE); } -struct dwc3_glue_ops ti_ops = { +static const struct dwc3_glue_ops ti_ops = { .glue_configure = dwc3_ti_glue_configure, }; @@ -506,16 +506,16 @@ static int dwc3_flat_dt_get_ctrl_dev(struct udevice *dev, ofnode *node) return 0; } -struct dwc3_glue_ops qcom_ops = { +static const struct dwc3_glue_ops qcom_ops = { .glue_configure = dwc3_qcom_glue_configure, }; -struct dwc3_glue_ops qcom_flat_dt_ops = { +static const struct dwc3_glue_ops qcom_flat_dt_ops = { .glue_configure = dwc3_qcom_glue_configure, .glue_get_ctrl_dev = dwc3_flat_dt_get_ctrl_dev, }; -struct dwc3_glue_ops rk_ops = { +static const struct dwc3_glue_ops rk_ops = { .glue_get_ctrl_dev = dwc3_flat_dt_get_ctrl_dev, }; diff --git a/drivers/usb/eth/Kconfig b/drivers/usb/eth/Kconfig index 2f6bfa8e71b..b9b77f46743 100644 --- a/drivers/usb/eth/Kconfig +++ b/drivers/usb/eth/Kconfig @@ -1,6 +1,6 @@ menuconfig USB_HOST_ETHER bool "USB to Ethernet Controller Drivers" - ---help--- + help Say Y here if you would like to enable support for USB Ethernet adapters. @@ -9,14 +9,14 @@ if USB_HOST_ETHER config USB_ETHER_ASIX bool "ASIX AX8817X (USB 2.0) support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support ASIX AX8817X based USB 2.0 Ethernet Devices. config USB_ETHER_ASIX88179 bool "ASIX AX88179 (USB 3.0) support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support ASIX AX88179 based USB 3.0 Ethernet Devices. @@ -24,7 +24,7 @@ config USB_ETHER_LAN75XX bool "Microchip LAN75XX support" depends on USB_HOST_ETHER depends on PHYLIB - ---help--- + help Say Y here if you would like to support Microchip LAN75XX Hi-Speed USB 2.0 to 10/100/1000 Gigabit Ethernet controller. Supports 10Base-T/ 100Base-TX/1000Base-T. @@ -34,7 +34,7 @@ config USB_ETHER_LAN78XX bool "Microchip LAN78XX support" depends on USB_HOST_ETHER depends on PHYLIB - ---help--- + help Say Y here if you would like to support Microchip LAN78XX USB 3.1 Gen 1 to 10/100/1000 Gigabit Ethernet controller. Supports 10Base-T/ 100Base-TX/1000Base-T. @@ -43,14 +43,14 @@ config USB_ETHER_LAN78XX config USB_ETHER_MCS7830 bool "MOSCHIP MCS7830 (7730/7830/7832) suppport" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices. config USB_ETHER_RTL8152 bool "Realtek RTL8152B/RTL8153 support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support Realtek RTL8152B/RTL8153 base USB Ethernet Devices. This driver also supports compatible devices from Samsung, Lenovo, TP-LINK and Nvidia. @@ -58,7 +58,7 @@ config USB_ETHER_RTL8152 config USB_ETHER_SMSC95XX bool "SMSC LAN95x support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support SMSC LAN95xx based USB 2.0 Ethernet Devices. diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 5390878254a..e42d5a43696 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -19,10 +19,10 @@ menuconfig USB_GADGET select DM_USB imply CMD_BIND help - USB is a master/slave protocol, organized with one master - host (such as a PC) controlling up to 127 peripheral devices. - The USB hardware is asymmetric, which makes it easier to set up: - you can't connect a "to-the-host" connector to a peripheral. + USB is a master/slave protocol, organized with one master + host (such as a PC) controlling up to 127 peripheral devices. + The USB hardware is asymmetric, which makes it easier to set up: + you can't connect a "to-the-host" connector to a peripheral. U-Boot can run in the host, or in the peripheral. In both cases you need a low level bus controller driver, and some software @@ -164,10 +164,10 @@ config USB_GADGET_VBUS_DRAW range 2 500 default 2 help - Some devices need to draw power from USB when they are - configured, perhaps to operate circuitry or to recharge - batteries. This is in addition to any local power supply, - such as an AC adapter or batteries. + Some devices need to draw power from USB when they are + configured, perhaps to operate circuitry or to recharge + batteries. This is in addition to any local power supply, + such as an AC adapter or batteries. Enter the maximum power your device draws through USB, in milliAmperes. The permitted range of values is 2 - 500 mA; @@ -350,9 +350,9 @@ config SPL_DFU_RAM bool "RAM device" depends on SPL_DFU && SPL_RAM_SUPPORT help - select RAM/DDR memory device for loading binary images - (u-boot/kernel) to the selected device partition using - DFU and execute the u-boot/kernel from RAM. + select RAM/DDR memory device for loading binary images + (u-boot/kernel) to the selected device partition using + DFU and execute the u-boot/kernel from RAM. endchoice diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 71dc58da3f0..87ed25e8bb3 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -2275,6 +2275,17 @@ static int fsg_set_alt(struct usb_function *f, unsigned intf, unsigned alt) static void fsg_disable(struct usb_function *f) { struct fsg_dev *fsg = fsg_from_func(f); + + /* Disable the endpoints */ + if (fsg->bulk_in_enabled) { + usb_ep_disable(fsg->bulk_in); + fsg->bulk_in_enabled = 0; + } + if (fsg->bulk_out_enabled) { + usb_ep_disable(fsg->bulk_out); + fsg->bulk_out_enabled = 0; + } + fsg->common->new_fsg = NULL; raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE); } diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index f72e27028b7..cd2c282247a 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -75,6 +75,7 @@ struct hid_report { #define SDP_HID_PACKET_SIZE_EP1 1024 #define SDP_EXIT 1 +#define SDP_FAIL 2 struct sdp_command { u16 cmd; @@ -840,11 +841,14 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_LOAD_FIT if (image_get_magic(header) == FDT_MAGIC) { struct spl_load_info load; + int ret; debug("Found FIT\n"); spl_load_init(&load, sdp_load_read, header, 1); - spl_load_simple_fit(spl_image, &load, 0, - header); + ret = spl_load_simple_fit(spl_image, &load, 0, + header); + if (ret) + return SDP_FAIL; return SDP_EXIT; } @@ -852,9 +856,13 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { struct spl_load_info load; + int ret; spl_load_init(&load, sdp_load_read, header, 1); - spl_load_imx_container(spl_image, &load, 0); + ret = spl_load_imx_container(spl_image, &load, 0); + if (ret) + return SDP_FAIL; + return SDP_EXIT; } @@ -924,6 +932,8 @@ int spl_sdp_handle(struct udevice *udc, struct spl_image_info *spl_image, if (flag == SDP_EXIT) return 0; + else if (flag == SDP_FAIL) + return -EIO; schedule(); dm_usb_gadget_handle_interrupts(udc); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d75883e2865..6bbed9cb513 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -24,7 +24,7 @@ config USB_XHCI_HCD bool "xHCI HCD (USB 3.0) support" depends on DM && OF_CONTROL select USB_HOST - ---help--- + help The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 "SuperSpeed" host controller hardware. @@ -149,7 +149,7 @@ config USB_EHCI_HCD select USB_HOST select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN - ---help--- + help The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. If your USB host controller supports USB 2.0, you will likely want to @@ -174,14 +174,14 @@ config USB_EHCI_ATMEL bool "Support for Atmel on-chip EHCI USB controller" depends on ARCH_AT91 default y - ---help--- + help Enables support for the on-chip EHCI controller on Atmel chips. config USB_EHCI_EXYNOS bool "Support for Samsung Exynos EHCI USB controller" depends on ARCH_EXYNOS default y - ---help--- + help Enables support for the on-chip EHCI controller on Samsung Exynos SoCs. @@ -191,7 +191,7 @@ config USB_EHCI_MARVELL default y select USB_EHCI_IS_TDI if !ARM64 select USB_EHCI_IS_TDI if ALLEYCAT_5 - ---help--- + help Enables support for the on-chip EHCI controller on MVEBU SoCs. config USB_EHCI_MX5 @@ -205,7 +205,7 @@ config USB_EHCI_MX6 depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT select EHCI_HCD_INIT_AFTER_RESET default y - ---help--- + help Enables support for the on-chip EHCI controller on i.MX6 SoCs. config USB_EHCI_MX7 @@ -215,7 +215,7 @@ config USB_EHCI_MX7 select PHY if IMX8M || IMX9 select NOP_PHY if IMX8M || IMX9 default y - ---help--- + help Enables support for the on-chip EHCI controller on i.MX7/i.MX8M/i.MX9 SoCs. config USB_EHCI_MXS @@ -230,7 +230,7 @@ config USB_EHCI_MXS config USB_EHCI_NPCM bool "Support for Nuvoton NPCM on-chip EHCI USB controller" depends on ARCH_NPCM - ---help--- + help Enables support for the on-chip EHCI controller on Nuvoton NPCM chips. @@ -240,7 +240,7 @@ config USB_EHCI_OMAP select PHY imply NOP_PHY default y - ---help--- + help Enables support for the on-chip EHCI controller on OMAP3 and later SoCs. @@ -255,7 +255,7 @@ if USB_EHCI_MX6 || USB_EHCI_MX7 config MXC_USB_OTG_HACTIVE bool "USB Power pin high active" - ---help--- + help Set the USB Power pin polarity to be high active (PWR_POL) endif @@ -265,7 +265,7 @@ config USB_EHCI_MSM depends on DM_USB select USB_ULPI select MSM8916_USB_PHY - ---help--- + help Enables support for the on-chip EHCI controller on Qualcomm Snapdragon SoCs. @@ -280,7 +280,7 @@ config USB_EHCI_TEGRA bool "Support for NVIDIA Tegra on-chip EHCI USB controller" depends on ARCH_TEGRA select USB_EHCI_IS_TDI - ---help--- + help Enable support for Tegra on-chip EHCI USB controller. If you enable ULPI and your PHY needs a different reference clock than the standard 24 MHz then you have to define CFG_ULPI_REF_CLK to the appropriate @@ -291,14 +291,14 @@ config USB_EHCI_ZYNQ depends on ARCH_ZYNQ default y select USB_EHCI_IS_TDI - ---help--- + help Enable support for Zynq on-chip EHCI USB controller config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on DM_USB default ARCH_SUNXI - ---help--- + help Enables support for generic EHCI controller. config EHCI_HCD_INIT_AFTER_RESET @@ -310,7 +310,7 @@ config USB_EHCI_FSL select EHCI_HCD_INIT_AFTER_RESET select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \ !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020) - ---help--- + help Enables support for the on-chip EHCI controller on FSL chips. config SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -340,7 +340,7 @@ config USB_OHCI_HCD depends on DM && OF_CONTROL select USB_HOST select USB_OHCI_NEW - ---help--- + help The Open Host Controller Interface (OHCI) is a standard for accessing USB 1.1 host controller hardware. It does more in hardware than Intel's UHCI specification. If your USB host controller follows the OHCI spec, @@ -361,7 +361,7 @@ config USB_OHCI_PCI config USB_OHCI_GENERIC bool "Support for generic OHCI USB controller" default ARCH_SUNXI - ---help--- + help Enables support for generic OHCI controller. config USB_OHCI_DA8XX @@ -374,7 +374,7 @@ config USB_OHCI_DA8XX config USB_OHCI_NPCM bool "Support for Nuvoton NPCM on-chip OHCI USB controller" depends on ARCH_NPCM - ---help--- + help Enables support for the on-chip OHCI controller on Nuvoton NPCM chips. @@ -391,7 +391,7 @@ config SYS_OHCI_SWAP_REG_ACCESS config USB_UHCI_HCD bool "UHCI HCD (most Intel and VIA) support" select USB_HOST - ---help--- + help The Universal Host Controller Interface is a standard by Intel for accessing the USB hardware in the PC (which is also called the USB host controller). If your USB host controller conforms to this @@ -410,7 +410,7 @@ config USB_DWC2 bool "DesignWare USB2 Core support" depends on DM && OF_CONTROL select USB_HOST - ---help--- + help The DesignWare USB 2.0 controller is compliant with the USB-Implementers Forum (USB-IF) USB 2.0 specifications. Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) @@ -421,7 +421,7 @@ if USB_DWC2 config USB_DWC2_BUFFER_SIZE int "Data buffer size in kB" default 64 - ---help--- + help By default 64 kB buffer is used but if amount of RAM avaialble on the target is not enough to accommodate allocation of buffer of that size it is possible to shrink it. Smaller sizes should be fine @@ -433,7 +433,7 @@ config USB_R8A66597_HCD bool "Renesas R8A66597 USB Core support" depends on DM && OF_CONTROL select USB_HOST - ---help--- + help This enables support for the on-chip Renesas R8A66597 USB 2.0 controller, present in various RZ and SH SoCs. diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c index 794a4168913..38ee17f063d 100644 --- a/drivers/usb/host/ehci-marvell.c +++ b/drivers/usb/host/ehci-marvell.c @@ -222,8 +222,8 @@ static void usb_brg_adrdec_setup(int index) break; } - size = gd->bd->bi_dram[i].size; - base = gd->bd->bi_dram[i].start; + size = gd->dram[i].size; + base = gd->dram[i].start; if ((size) && (attrib)) writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, attrib, MVCPU_WIN_ENABLE), diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 1d6711ccec4..3fcf9d53d59 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1750,7 +1750,7 @@ static int hc_reset(ohci_t *ohci) int timeout = 30; int smm_timeout = 50; /* 0,5 sec */ - dbg("%s\n", __FUNCTION__); + dbg("%s\n", __func__); #ifdef CONFIG_PCI_EHCI_DEVNO /* diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index f8daaddc657..6fb37c787de 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -23,11 +23,11 @@ config USB_MUSB_GADGET if USB_MUSB_HOST || USB_MUSB_GADGET config USB_MUSB_SC5XX - bool "Analog Devices MUSB support" - depends on (SC57X || SC58X) + bool "Analog Devices MUSB support" + depends on (SC57X || SC58X) help - Say y here to enable support for the USB controller on - ADI SC57X/SC58X processors. + Say y here to enable support for the USB controller on + ADI SC57X/SC58X processors. config USB_MUSB_DA8XX bool "Enable DA8xx MUSB Controller" @@ -81,9 +81,9 @@ config USB_MUSB_SUNXI depends on PHY_SUN4I_USB select USB_MUSB_PIO_ONLY default y - ---help--- - Say y here to enable support for the sunxi OTG / DRC USB controller - used on almost all sunxi boards. + help + Say y here to enable support for the sunxi OTG / DRC USB controller + used on almost all sunxi boards. config USB_MUSB_UX500 bool "Enable ST-Ericsson Ux500 USB controller" diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 7fd6639013a..c8c6bf0c84f 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -100,7 +100,7 @@ static int omap2430_musb_enable(struct musb *musb) #ifdef CONFIG_TWL4030_USB if (twl4030_usb_ulpi_init()) { serial_printf("ERROR: %s Could not initialize PHY\n", - __PRETTY_FUNCTION__); + __func__); } #endif return 0; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index c2acc13139c..15000e21840 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -29,6 +29,13 @@ config VIDEO_FONT_4X6 Provides character bitmap data in header file. When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. +config VIDEO_FONT_6X8 + bool "6 x 8 font size" + help + Font for video console driver, 6 x 8 pixels. + Provides character bitmap data in header file. + When selecting multiple fonts, you may want to enable CMD_SELECT_FONT too. + config VIDEO_FONT_8X16 bool "8 x 16 font size" default y @@ -247,10 +254,10 @@ config SYS_WHITE_ON_BLACK bool "Display console as white on a black background" default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || ARCH_TEGRA || X86 || ARCH_SUNXI help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background. This can be - better in low-light situations or to reduce eye strain in some - cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background. This can be + better in low-light situations or to reduce eye strain in some + cases. config NO_FB_CLEAR bool "Skip framebuffer clear" @@ -508,10 +515,10 @@ config FRAMEBUFFER_VESA_MODE config VIDEO_LCD_ANX9804 bool "ANX9804 bridge chip" - ---help--- - Support for the ANX9804 bridge chip, which can take pixel data coming - from a parallel LCD interface and translate it on the fy into a DP - interface for driving eDP TFT displays. It uses I2C for configuration. + help + Support for the ANX9804 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fy into a DP + interface for driving eDP TFT displays. It uses I2C for configuration. config ATMEL_LCD bool "Atmel LCD panel support" @@ -534,7 +541,7 @@ config VIDEO_BCM2835 that U-Boot can access it with full colour depth. config VIDEO_LCD_ENDEAVORU - tristate "Endeavoru 720x1280 DSI video mode panel" + bool "Endeavoru 720x1280 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -549,8 +556,8 @@ config VIDEO_LCD_HIMAX_HX8394 depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Himax HX8394 - dsi 4dl panel. + Say Y here if you want to enable support for Himax HX8394 + dsi 4dl panel. config VIDEO_LCD_ILITEK_ILI9806E bool "Ilitek ILI9806E-based panels" @@ -561,7 +568,7 @@ config VIDEO_LCD_ILITEK_ILI9806E is implemented. config VIDEO_LCD_MOT - tristate "Atrix 4G and Droid X2 540x960 DSI video mode panel" + bool "Atrix 4G and Droid X2 540x960 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -574,15 +581,15 @@ config VIDEO_LCD_NOVATEK_NT35510 bool "Novatek NT35510 DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Novatek nt35510 - dsi panel. + Say Y here if you want to enable support for Novatek nt35510 + dsi panel. config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Orise Technology - otm8009a 480x800 dsi 2dl panel. + Say Y here if you want to enable support for Orise Technology + otm8009a 480x800 dsi 2dl panel. config VIDEO_LCD_LG_LD070WX3 bool "LD070WX3 DSI LCD panel support" @@ -602,13 +609,14 @@ config VIDEO_LCD_LG_LH400WV3 config VIDEO_LCD_RAYDIUM_RM68200 bool "RM68200 DSI LCD panel support" + depends on BACKLIGHT select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Raydium RM68200 - 720x1280 DSI video mode panel. + Say Y here if you want to enable support for Raydium RM68200 + 720x1280 DSI video mode panel. config VIDEO_LCD_RENESAS_R61307 - tristate "Renesas R61307 DSI video mode panel" + bool "Renesas R61307 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -617,7 +625,7 @@ config VIDEO_LCD_RENESAS_R61307 resolution and uses 24 bit RGB per pixel. config VIDEO_LCD_RENESAS_R69328 - tristate "Renesas R69328 720x1280 DSI video mode panel" + bool "Renesas R69328 720x1280 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -626,7 +634,7 @@ config VIDEO_LCD_RENESAS_R69328 resolution and uses 24 bit RGB per pixel. config VIDEO_LCD_SAMSUNG_LTL106HL02 - tristate "Samsung LTL106HL02 1920x1080 DSI video mode panel" + bool "Samsung LTL106HL02 1920x1080 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -635,7 +643,7 @@ config VIDEO_LCD_SAMSUNG_LTL106HL02 resolution (1920x1080). config VIDEO_LCD_SHARP_LQ079L1SX01 - tristate "Sharp LQ079L1SX01 1536x2048 DSI video mode panel" + bool "Sharp LQ079L1SX01 1536x2048 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -644,7 +652,7 @@ config VIDEO_LCD_SHARP_LQ079L1SX01 resolution (1536x2048). config VIDEO_LCD_SHARP_LQ101R1SX01 - tristate "Sharp LQ101R1SX01 2560x1600 DSI video mode panel" + bool "Sharp LQ101R1SX01 2560x1600 DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -654,41 +662,41 @@ config VIDEO_LCD_SHARP_LQ101R1SX01 config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" - ---help--- - Support for the SSD2828 bridge chip, which can take pixel data coming - from a parallel LCD interface and translate it on the fly into MIPI DSI - interface for driving a MIPI compatible LCD panel. It uses SPI for - configuration. + help + Support for the SSD2828 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fly into MIPI DSI + interface for driving a MIPI compatible LCD panel. It uses SPI for + configuration. config VIDEO_LCD_SSD2828_TX_CLK int "SSD2828 TX_CLK frequency (in MHz)" depends on VIDEO_LCD_SSD2828 default 0 - ---help--- - The frequency of the crystal, which is clocking SSD2828. It may be - anything in the 8MHz-30MHz range and the exact value should be - retrieved from the board schematics. Or in the case of Allwinner - hardware, it can be usually found as 'lcd_xtal_freq' variable in - FEX files. It can be also set to 0 for selecting PCLK from the - parallel LCD interface instead of TX_CLK as the PLL clock source. + help + The frequency of the crystal, which is clocking SSD2828. It may be + anything in the 8MHz-30MHz range and the exact value should be + retrieved from the board schematics. Or in the case of Allwinner + hardware, it can be usually found as 'lcd_xtal_freq' variable in + FEX files. It can be also set to 0 for selecting PCLK from the + parallel LCD interface instead of TX_CLK as the PLL clock source. config VIDEO_LCD_SSD2828_RESET string "RESET pin of SSD2828" depends on VIDEO_LCD_SSD2828 default "" - ---help--- - The reset pin of SSD2828 chip. This takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + The reset pin of SSD2828 chip. This takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_TDO_TL070WSH30 bool "TDO TL070WSH30 DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for TDO TL070WSH30 - 1024x600 DSI video mode panel. + Say Y here if you want to enable support for TDO TL070WSH30 + 1024x600 DSI video mode panel. config VIDEO_LCD_HITACHI_TX10D07VM0BAA - tristate "Hitachi TX10D07VM0BAA 480x800 MIPI DSI video mode panel" + bool "Hitachi TX10D07VM0BAA 480x800 MIPI DSI video mode panel" depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help @@ -697,13 +705,13 @@ config VIDEO_LCD_HITACHI_TX10D07VM0BAA config VIDEO_LCD_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LVDS LCD panel support" - ---help--- - Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a - lcd controller which needs to be initialized over SPI, once that is - done they work like a regular LVDS panel. + help + Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a + lcd controller which needs to be initialized over SPI, once that is + done they work like a regular LVDS panel. config VIDEO_LCD_SONY_L4F00430T01 - tristate "Sony L4F00430T01 480x800 LCD panel support" + bool "Sony L4F00430T01 480x800 LCD panel support" depends on PANEL help Say Y here if you want to enable support for Sony L4F00430T01 @@ -712,7 +720,7 @@ config VIDEO_LCD_SONY_L4F00430T01 data comes from RGB. config VIDEO_LCD_SAMSUNG_S6E63M0 - tristate "Samsung S6E63M0 controller based panel support" + bool "Samsung S6E63M0 controller based panel support" depends on PANEL && BACKLIGHT help Say Y here if you want to enable support for Samsung S6E63M0 @@ -723,44 +731,44 @@ config VIDEO_LCD_SPI_CS string "SPI CS pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_SCLK string "SPI SCLK pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MOSI string "SPI MOSI pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MISO string "SPI MISO pin for LCD related config job (optional)" depends on VIDEO_LCD_SSD2828 default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. If wired up, this pin may provide additional - useful functionality. Such as bi-directional communication with the - hardware and LCD panel id retrieval (if the panel can report it). The - option takes a string in the format understood by 'sunxi_name_to_gpio' - function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. If wired up, this pin may provide additional + useful functionality. Such as bi-directional communication with the + hardware and LCD panel id retrieval (if the panel can report it). The + option takes a string in the format understood by 'sunxi_name_to_gpio' + function, e.g. PH1 for pin 1 of port H. source "drivers/video/meson/Kconfig" @@ -768,9 +776,9 @@ config VIDEO_MVEBU bool "Armada XP LCD controller" depends on ARCH_MVEBU imply VIDEO_DAMAGE - ---help--- - Support for the LCD controller integrated in the Marvell - Armada XP SoC. + help + Support for the LCD controller integrated in the Marvell + Armada XP SoC. config VIDEO_OMAP3 bool "Enable OMAP3+ DSS Support" @@ -781,23 +789,23 @@ config VIDEO_OMAP3 config I2C_EDID bool "Enable EDID library" help - This enables library for accessing EDID data from an LCD panel. + This enables library for accessing EDID data from an LCD panel. config I2C_EDID_STANDARD bool "Enable standard timings EDID library expansion" depends on I2C_EDID help - This enables standard timings expansion for EDID data from an LCD panel. + This enables standard timings expansion for EDID data from an LCD panel. config DISPLAY bool "Enable Display support" depends on DM select I2C_EDID help - This supports drivers that provide a display, such as eDP (Embedded - DisplayPort) and HDMI (High Definition Multimedia Interface). - The devices provide a simple interface to start up the display, - read display information and enable it. + This supports drivers that provide a display, such as eDP (Embedded + DisplayPort) and HDMI (High Definition Multimedia Interface). + The devices provide a simple interface to start up the display, + read display information and enable it. config NXP_TDA19988 bool "Enable NXP TDA19988 support" @@ -811,7 +819,7 @@ config ATMEL_HLCD depends on ARCH_AT91 imply VIDEO_DAMAGE help - HLCDC supports video output to an attached LCD panel. + HLCDC supports video output to an attached LCD panel. config BACKLIGHT_AAT2870 bool "Backlight Driver for AAT2870" @@ -865,7 +873,7 @@ source "drivers/video/exynos/Kconfig" config LOGICORE_DP_TX bool "Enable Logicore DP TX driver" - depends on DISPLAY + depends on DISPLAY && AXI help Enable the driver for the transmitter part of the Xilinx LogiCORE DisplayPort, a IP core for Xilinx FPGAs that implements a DisplayPort @@ -930,9 +938,9 @@ config VIDEO_NX bool "Enable video support on Nexell SoC" depends on ARCH_S5P6818 || ARCH_S5P4418 help - Nexell SoC supports many video output options including eDP and - HDMI. This option enables this support which can be used on devices - which have an eDP display connected. + Nexell SoC supports many video output options including eDP and + HDMI. This option enables this support which can be used on devices + which have an eDP display connected. config VIDEO_SEPS525 bool "Enable video support for Seps525" @@ -1018,9 +1026,9 @@ config OSD bool "Enable OSD support" depends on DM help - This supports drivers that provide a OSD (on-screen display), which - is a (usually text-oriented) graphics buffer to show information on - a display. + This supports drivers that provide a OSD (on-screen display), which + is a (usually text-oriented) graphics buffer to show information on + a display. config SANDBOX_OSD bool "Enable sandbox OSD" @@ -1213,10 +1221,10 @@ config SPL_SPLASH_SCREEN config SPL_SYS_WHITE_ON_BLACK bool "Display console as white on a black background at SPL" help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background at spl stage. - This can be better in low-light situations or to reduce eye strain in - some cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. config SPL_VIDEO_PCI_DEFAULT_FB_SIZE hex "Default framebuffer size to use if no drivers request it at SPL" @@ -1279,10 +1287,10 @@ config SPL_SIMPLE_PANEL config SPL_SYS_WHITE_ON_BLACK bool "Display console as white on a black background at SPL" help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background at spl stage. - This can be better in low-light situations or to reduce eye strain in - some cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. config SPL_VIDEO_REMOVE bool "Remove video driver after SPL stage" @@ -1408,13 +1416,13 @@ config SPL_VIDEO_BPP32 will be empty. config SPL_HIDE_LOGO_VERSION - bool "Hide the version information on the splash screen at SPL" - help - Normally the U-Boot version string is shown on the display when the - splash screen is enabled. This information is not otherwise visible - since video starts up after U-Boot has displayed the initial banner. + bool "Hide the version information on the splash screen at SPL" + help + Normally the U-Boot version string is shown on the display when the + splash screen is enabled. This information is not otherwise visible + since video starts up after U-Boot has displayed the initial banner. - Enable this option to hide this information. + Enable this option to hide this information. endif endmenu diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig index 5322a002928..81261c61005 100644 --- a/drivers/video/bridge/Kconfig +++ b/drivers/video/bridge/Kconfig @@ -41,8 +41,8 @@ config VIDEO_BRIDGE_ANALOGIX_ANX6345 depends on VIDEO_BRIDGE select DM_I2C help - The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD - panel to be connected to an parallel LCD interface. + The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD + panel to be connected to an parallel LCD interface. config VIDEO_BRIDGE_SOLOMON_SSD2825 bool "Solomon SSD2825 bridge driver" diff --git a/drivers/video/bridge/anx6345.c b/drivers/video/bridge/anx6345.c index 8cee4c958bd..a5d2781aa48 100644 --- a/drivers/video/bridge/anx6345.c +++ b/drivers/video/bridge/anx6345.c @@ -403,7 +403,7 @@ static int anx6345_probe(struct udevice *dev) return anx6345_enable(dev); } -struct video_bridge_ops anx6345_ops = { +static const struct video_bridge_ops anx6345_ops = { .attach = anx6345_attach, .set_backlight = anx6345_set_backlight, .read_edid = anx6345_read_edid, diff --git a/drivers/video/bridge/ps862x.c b/drivers/video/bridge/ps862x.c index efd03752281..a08227f8355 100644 --- a/drivers/video/bridge/ps862x.c +++ b/drivers/video/bridge/ps862x.c @@ -116,7 +116,7 @@ static int ps8622_probe(struct udevice *dev) return 0; } -struct video_bridge_ops ps8622_ops = { +static const struct video_bridge_ops ps8622_ops = { .attach = ps8622_attach, .set_backlight = ps8622_set_backlight, }; diff --git a/drivers/video/bridge/ptn3460.c b/drivers/video/bridge/ptn3460.c index 5851e1ef15e..ce576c0b282 100644 --- a/drivers/video/bridge/ptn3460.c +++ b/drivers/video/bridge/ptn3460.c @@ -15,7 +15,7 @@ static int ptn3460_attach(struct udevice *dev) return video_bridge_set_active(dev, true); } -struct video_bridge_ops ptn3460_ops = { +static const struct video_bridge_ops ptn3460_ops = { .attach = ptn3460_attach, }; diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c index 07db613ac53..6dc0a6eaf9d 100644 --- a/drivers/video/console_normal.c +++ b/drivers/video/console_normal.c @@ -133,7 +133,7 @@ static int console_set_cursor_visible(struct udevice *dev, bool visible, return 0; } -struct vidconsole_ops console_ops = { +static const struct vidconsole_ops console_ops = { .putc_xy = console_putc_xy, .move_rows = console_move_rows, .set_row = console_set_row, diff --git a/drivers/video/console_rotate.c b/drivers/video/console_rotate.c index 886b25dcfaf..e478e0ef3bc 100644 --- a/drivers/video/console_rotate.c +++ b/drivers/video/console_rotate.c @@ -284,7 +284,7 @@ static int console_putc_xy_3(struct udevice *dev, uint x_frac, uint y, int cp) return VID_TO_POS(fontdata->width); } -struct vidconsole_ops console_ops_1 = { +static const struct vidconsole_ops console_ops_1 = { .putc_xy = console_putc_xy_1, .move_rows = console_move_rows_1, .set_row = console_set_row_1, @@ -293,7 +293,7 @@ struct vidconsole_ops console_ops_1 = { .select_font = console_simple_select_font, }; -struct vidconsole_ops console_ops_2 = { +static const struct vidconsole_ops console_ops_2 = { .putc_xy = console_putc_xy_2, .move_rows = console_move_rows_2, .set_row = console_set_row_2, @@ -302,7 +302,7 @@ struct vidconsole_ops console_ops_2 = { .select_font = console_simple_select_font, }; -struct vidconsole_ops console_ops_3 = { +static const struct vidconsole_ops console_ops_3 = { .putc_xy = console_putc_xy_3, .move_rows = console_move_rows_3, .set_row = console_set_row_3, diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index eaf169e8386..b9b6f394fbc 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -1069,7 +1069,7 @@ static int console_truetype_probe(struct udevice *dev) return 0; } -struct vidconsole_ops console_truetype_ops = { +static const struct vidconsole_ops console_truetype_ops = { .putc_xy = console_truetype_putc_xy, .move_rows = console_truetype_move_rows, .set_row = console_truetype_set_row, diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c index c74fe678d12..ec5d4c81812 100644 --- a/drivers/video/dw_mipi_dsi.c +++ b/drivers/video/dw_mipi_dsi.c @@ -837,7 +837,7 @@ static int dw_mipi_dsi_enable(struct udevice *dev) return 0; } -struct dsi_host_ops dw_mipi_dsi_ops = { +static const struct dsi_host_ops dw_mipi_dsi_ops = { .init = dw_mipi_dsi_init, .enable = dw_mipi_dsi_enable, }; diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig index c25f209629e..0c386595559 100644 --- a/drivers/video/imx/Kconfig +++ b/drivers/video/imx/Kconfig @@ -20,7 +20,7 @@ config IPU_CLK_LEGACY depends on VIDEO_IPUV3 && !CLK default y help - Use legacy clock management instead of Common Clock Framework. + Use legacy clock management instead of Common Clock Framework. config IMX_LDB bool "Freescale i.MX8MP LDB bridge" diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h index ae40e20bc28..aecb6adffce 100644 --- a/drivers/video/imx/ipu.h +++ b/drivers/video/imx/ipu.h @@ -136,7 +136,6 @@ struct ipu_ctx { struct clk *ipu_clk; struct clk *ldb_clk; - unsigned char ipu_clk_enabled; struct clk *di_clk[2]; struct clk *pixel_clk[2]; diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index 8630374a055..d3b52605731 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -299,9 +299,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk); clk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk); +#endif clk_enable(ctx->ipu_clk); -#endif for (int i = 0; i <= 1; i++) { ret = ipu_di_clk_init(ctx, i); @@ -384,10 +384,8 @@ int32_t ipu_init_channel(struct ipu_ctx *ctx, ipu_channel_t channel, debug("init channel = %d\n", IPU_CHAN_ID(channel)); - if (ctx->ipu_clk_enabled == 0) { - ctx->ipu_clk_enabled = 1; + if (!ipu_clk_enabled(ctx)) clk_enable(ipu_clk); - } if (*channel_init_mask & (1L << IPU_CHAN_ID(channel))) { printf("Warning: channel already initialized %d\n", @@ -543,7 +541,6 @@ void ipu_uninit_channel(struct ipu_ctx *ctx, ipu_channel_t channel) if (ipu_conf == 0) { clk_disable(ctx->ipu_clk); - ctx->ipu_clk_enabled = 0; } } @@ -1045,5 +1042,9 @@ ipu_color_space_t format_to_colorspace(u32 fmt) bool ipu_clk_enabled(struct ipu_ctx *ctx) { - return ctx->ipu_clk_enabled; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return clk_get_usecount(ctx->ipu_clk); +#else + return ctx->ipu_clk->enable_count; +#endif } diff --git a/drivers/video/imx/ldb.c b/drivers/video/imx/ldb.c index e918341c0a3..32a327647f8 100644 --- a/drivers/video/imx/ldb.c +++ b/drivers/video/imx/ldb.c @@ -230,7 +230,7 @@ dis_clk: return ret; } -struct video_bridge_ops imx_ldb_ops = { +static const struct video_bridge_ops imx_ldb_ops = { .attach = imx_ldb_attach, .set_backlight = imx_ldb_set_backlight, }; diff --git a/drivers/video/meson/meson_vpu.c b/drivers/video/meson/meson_vpu.c index ca627728743..a686faf9f58 100644 --- a/drivers/video/meson/meson_vpu.c +++ b/drivers/video/meson/meson_vpu.c @@ -81,8 +81,8 @@ cvbs: meson_fb.fb_size = ALIGN(meson_fb.xsize * meson_fb.ysize * ((1 << VPU_MAX_LOG2_BPP) / 8) + MESON_VPU_OVERSCAN, EFI_PAGE_SIZE); - meson_fb.base = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - meson_fb.fb_size; + meson_fb.base = gd->dram[0].start + + gd->dram[0].size - meson_fb.fb_size; /* Override the framebuffer address */ uc_plat->base = meson_fb.base; @@ -175,8 +175,8 @@ static void meson_vpu_setup_simplefb(void *fdt) * at the end of the RAM and we strip this portion from the kernel * allowed region */ - mem_start = gd->bd->bi_dram[0].start; - mem_size = gd->bd->bi_dram[0].size - meson_fb.fb_size; + mem_start = gd->dram[0].start; + mem_size = gd->dram[0].size - meson_fb.fb_size; ret = fdt_fixup_memory_banks(fdt, &mem_start, &mem_size, 1); if (ret) { eprintf("Cannot setup simplefb: Error reserving memory\n"); diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 96af6d28ef0..41d249cb90c 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -21,7 +21,7 @@ menuconfig VIDEO_ROCKCHIP Rockchip RK3288 and RK3399. config VIDEO_ROCKCHIP_MAX_XRES - int "Maximum horizontal resolution (for memory allocation purposes)" + int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP default 3840 if DISPLAY_ROCKCHIP_HDMI default 1920 @@ -31,7 +31,7 @@ config VIDEO_ROCKCHIP_MAX_XRES framebuffer during device-model binding/probing. config VIDEO_ROCKCHIP_MAX_YRES - int "Maximum vertical resolution (for memory allocation purposes)" + int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP default 2160 if DISPLAY_ROCKCHIP_HDMI default 1080 diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 8d0772d4e51..631ae00b1e1 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -9,6 +9,8 @@ #include <log.h> #include <video.h> #include <asm/global_data.h> +#include <asm/system.h> +#include <linux/sizes.h> static int simple_video_probe(struct udevice *dev) { @@ -20,8 +22,14 @@ static int simple_video_probe(struct udevice *dev) fdt_addr_t base; fdt_size_t size; u32 width, height, stride, rot; + struct ofnode_phandle_args args; + + ret = dev_read_phandle_with_args(dev, "memory-region", NULL, 0, 0, &args); + if (ret) + base = dev_read_addr_size(dev, &size); + else + base = ofnode_get_addr_size(args.node, "reg", &size); - base = dev_read_addr_size(dev, &size); if (base == FDT_ADDR_T_NONE) { debug("%s: Failed to decode memory region\n", __func__); return -EINVAL; @@ -37,6 +45,13 @@ static int simple_video_probe(struct udevice *dev) plat->base = base; plat->size = size; +#ifdef CONFIG_ARM64 + /* The framebuffer buffer might not be mapped on some devices */ + if (plat->base % SZ_4K) + log_warning("Framebuffer base %lx is not 4k aligned!\n", plat->base); + mmu_map_region((phys_addr_t)plat->base, (phys_addr_t)ALIGN(plat->size, SZ_4K), false); +#endif + video_set_flush_dcache(dev, true); debug("%s: Query resolution...\n", __func__); diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c index 5c4d8d2aab5..29c57a4ff89 100644 --- a/drivers/video/stm32/stm32_dsi.c +++ b/drivers/video/stm32/stm32_dsi.c @@ -511,7 +511,7 @@ err_reg: return ret; } -struct video_bridge_ops stm32_dsi_ops = { +static const struct video_bridge_ops stm32_dsi_ops = { .attach = stm32_dsi_attach, .set_backlight = stm32_dsi_set_backlight, }; diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 154641b9a69..ab36ee1595b 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -368,7 +368,7 @@ int sunxi_simplefb_setup(void *blob) return 0; /* Keep older kernels working */ } - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = de2_plat->base - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 4a6a89ef9d2..fa492c661db 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -1336,7 +1336,7 @@ int sunxi_simplefb_setup(void *blob) * and e.g. Linux refuses to iomap RAM on ARM, see: * linux/arch/arm/mm/ioremap.c around line 301. */ - start = gd->bd->bi_dram[0].start; + start = gd->dram[0].start; size = sunxi_display->fb_addr - start; ret = fdt_fixup_memory_banks(blob, &start, &size, 1); if (ret) { diff --git a/drivers/video/tda19988.c b/drivers/video/tda19988.c index ebc8521c6ed..a4cc3a49232 100644 --- a/drivers/video/tda19988.c +++ b/drivers/video/tda19988.c @@ -522,7 +522,7 @@ static int tda19988_enable(struct udevice *dev, int panel_bpp, return 0; } -struct dm_display_ops tda19988_ops = { +static const struct dm_display_ops tda19988_ops = { .read_edid = tda19988_read_edid, .enable = tda19988_enable, }; diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig index 8bc29f2838b..125504024fc 100644 --- a/drivers/video/tegra/Kconfig +++ b/drivers/video/tegra/Kconfig @@ -9,13 +9,13 @@ config VIDEO_TEGRA depends on OF_CONTROL && ARCH_TEGRA select HOST1X_TEGRA help - Enable support for Display Controller found in Tegra SoC. The - Display Controller Complex integrates two independent display - controllers. Each display controller is capable of interfacing - to an external display device, which can be a parallel interface - or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD. - Direct interface is supported directly to most LCD displays with - TFT or TFT-like interface. + Enable support for Display Controller found in Tegra SoC. The + Display Controller Complex integrates two independent display + controllers. Each display controller is capable of interfacing + to an external display device, which can be a parallel interface + or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD. + Direct interface is supported directly to most LCD displays with + TFT or TFT-like interface. config VIDEO_DSI_TEGRA bool "Enable DSI controller support on Tegra devices" @@ -23,9 +23,9 @@ config VIDEO_DSI_TEGRA select VIDEO_TEGRA select VIDEO_MIPI_DSI help - Enable support for the Display Serial Interface (DSI) found in - Tegra SoC. It is a MIPI standard serial bitstream, intended to - provide a low pin count interface to a display panel. + Enable support for the Display Serial Interface (DSI) found in + Tegra SoC. It is a MIPI standard serial bitstream, intended to + provide a low pin count interface to a display panel. config VIDEO_HDMI_TEGRA bool "Enable HDMI support on Tegra devices" @@ -33,31 +33,31 @@ config VIDEO_HDMI_TEGRA select I2C_EDID select VIDEO_TEGRA help - Enable support for the High-Definition Multimedia Interface (HDMI) - found in Tegra SoC. + Enable support for the High-Definition Multimedia Interface (HDMI) + found in Tegra SoC. config TEGRA_BACKLIGHT_PWM bool "Enable Tegra DC PWM backlight support" depends on BACKLIGHT && VIDEO_TEGRA help - Enable support for the Display Controller dependent PWM backlight - found in the Tegra SoC and usually used with DSI panels. + Enable support for the Display Controller dependent PWM backlight + found in the Tegra SoC and usually used with DSI panels. config TEGRA_8BIT_CPU_BRIDGE bool "Enable 8 bit panel communication protocol for Tegra 20/30" depends on VIDEO_BRIDGE && DM_GPIO && VIDEO_TEGRA select VIDEO_MIPI_DSI help - Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control - protocol. This option allows use it as a MIPI DSI bridge to - set up and control compatible panel. + Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control + protocol. This option allows use it as a MIPI DSI bridge to + set up and control compatible panel. config VIDEO_TEGRA124 bool "Enable video support on Tegra124" depends on ARCH_TEGRA imply VIDEO_DAMAGE help - Tegra124 supports many video output options including eDP and - HDMI. At present only eDP is supported by U-Boot. This option - enables this support which can be used on devices which - have an eDP display connected. + Tegra124 supports many video output options including eDP and + HDMI. At present only eDP is supported by U-Boot. This option + enables this support which can be used on devices which + have an eDP display connected. diff --git a/drivers/video/tegra/dsi.c b/drivers/video/tegra/dsi.c index bc308869f4e..f53fabf6fd6 100644 --- a/drivers/video/tegra/dsi.c +++ b/drivers/video/tegra/dsi.c @@ -337,7 +337,7 @@ static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, return count; } -struct mipi_dsi_host_ops tegra_dsi_bridge_host_ops = { +static const struct mipi_dsi_host_ops tegra_dsi_bridge_host_ops = { .transfer = tegra_dsi_host_transfer, }; diff --git a/drivers/video/ti/Kconfig b/drivers/video/ti/Kconfig index 0483f760ea1..a3cbefef0de 100644 --- a/drivers/video/ti/Kconfig +++ b/drivers/video/ti/Kconfig @@ -6,4 +6,4 @@ config AM335X_LCD bool "Enable AM335x video support" depends on ARCH_OMAP2PLUS help - Supports video output to an attached LCD panel. + Supports video output to an attached LCD panel. diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig index 3291b3ceb8d..c9849110059 100644 --- a/drivers/video/tidss/Kconfig +++ b/drivers/video/tidss/Kconfig @@ -10,7 +10,7 @@ menuconfig VIDEO_TIDSS bool "Enable TIDSS video support" - depends on VIDEO + depends on VIDEO && PANEL imply VIDEO_DAMAGE help TIDSS supports video output options LVDS and @@ -19,7 +19,7 @@ menuconfig VIDEO_TIDSS config SPL_VIDEO_TIDSS bool "Enable TIDSS video support in SPL Stage" - depends on SPL_VIDEO + depends on SPL_VIDEO && SPL_PANEL help This options enables tidss driver in SPL stage. If you need to use tidss at SPL stage use this config. diff --git a/drivers/video/zynqmp/Kconfig b/drivers/video/zynqmp/Kconfig index b35cd1fb342..2c737710639 100644 --- a/drivers/video/zynqmp/Kconfig +++ b/drivers/video/zynqmp/Kconfig @@ -3,6 +3,6 @@ config VIDEO_ZYNQMP_DPSUB bool "Enable video support for ZynqMP Display Port" depends on ZYNQMP_POWER_DOMAIN help - Enable support for Xilinx ZynqMP Display Port. Currently this file - is used as placeholder for driver. The main reason is to record - compatible string and calling power domain driver. + Enable support for Xilinx ZynqMP Display Port. Currently this file + is used as placeholder for driver. The main reason is to record + compatible string and calling power domain driver. diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c index c36e9e9b3a7..a871a1439d4 100644 --- a/drivers/virtio/virtio-uclass.c +++ b/drivers/virtio/virtio-uclass.c @@ -400,9 +400,6 @@ UCLASS_DRIVER(virtio) = { .per_device_auto = sizeof(struct virtio_dev_priv), }; -struct bootdev_ops virtio_bootdev_ops = { -}; - static const struct udevice_id virtio_bootdev_ids[] = { { .compatible = "u-boot,bootdev-virtio" }, { } @@ -411,7 +408,6 @@ static const struct udevice_id virtio_bootdev_ids[] = { U_BOOT_DRIVER(virtio_bootdev) = { .name = "virtio_bootdev", .id = UCLASS_BOOTDEV, - .ops = &virtio_bootdev_ops, .bind = virtio_bootdev_bind, .of_match = virtio_bootdev_ids, }; diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 7b1d891cdcb..404d9140cb2 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -232,14 +232,11 @@ static int virtio_blk_bind(struct udevice *dev) return devnum; desc->devnum = devnum; desc->part_type = PART_TYPE_UNKNOWN; - /* - * virtio mmio transport supplies string identification for us, - * while pci trnasport uses a 2-byte subvendor value. - */ - if (uc_priv->vendor >> 16) - sprintf(desc->vendor, "%s", (char *)&uc_priv->vendor); + + if (uc_priv->vendor == VIRTIO_VENDOR_QEMU) + strcpy(desc->vendor, "QEMU"); else - sprintf(desc->vendor, "%04x", uc_priv->vendor); + sprintf(desc->vendor, "%08x", uc_priv->vendor); desc->bdev = dev; /* Indicate what driver features we support */ diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index d90d8309f99..975f98cd9e5 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -12,6 +12,7 @@ #include <virtio_types.h> #include <virtio.h> #include <virtio_ring.h> +#include <virtio_mmio.h> #include <linux/bug.h> #include <linux/compat.h> #include <linux/err.h> @@ -335,21 +336,28 @@ static int virtio_mmio_notify(struct udevice *udev, struct virtqueue *vq) static int virtio_mmio_of_to_plat(struct udevice *udev) { - struct virtio_mmio_priv *priv = dev_get_priv(udev); + struct virtio_mmio_plat *plat = dev_get_plat(udev); + fdt_addr_t addr; + + addr = dev_read_addr(udev); - priv->base = (void __iomem *)(ulong)dev_read_addr(udev); - if (priv->base == (void __iomem *)FDT_ADDR_T_NONE) + if (addr == FDT_ADDR_T_NONE) return -EINVAL; + plat->base = addr; + return 0; } static int virtio_mmio_probe(struct udevice *udev) { + struct virtio_mmio_plat *plat = dev_get_plat(udev); struct virtio_mmio_priv *priv = dev_get_priv(udev); struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev); u32 magic; + priv->base = (void __iomem *)(uintptr_t)plat->base; + /* Check magic value */ magic = readl(priv->base + VIRTIO_MMIO_MAGIC_VALUE); if (magic != ('v' | 'i' << 8 | 'r' << 16 | 't' << 24)) { @@ -405,11 +413,12 @@ static const struct udevice_id virtio_mmio_ids[] = { }; U_BOOT_DRIVER(virtio_mmio) = { - .name = "virtio-mmio", - .id = UCLASS_VIRTIO, - .of_match = virtio_mmio_ids, - .ops = &virtio_mmio_ops, - .probe = virtio_mmio_probe, + .name = "virtio-mmio", + .id = UCLASS_VIRTIO, + .of_match = virtio_mmio_ids, + .ops = &virtio_mmio_ops, + .probe = virtio_mmio_probe, .of_to_plat = virtio_mmio_of_to_plat, - .priv_auto = sizeof(struct virtio_mmio_priv), + .priv_auto = sizeof(struct virtio_mmio_priv), + .plat_auto = sizeof(struct virtio_mmio_plat), }; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 9ea617f1e43..b91727e1265 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -217,6 +217,7 @@ config SPL_WDT_GPIO config WDT_MAX6370 bool "MAX6370 watchdog timer support" depends on WDT + select GPIO select DM_GPIO help Select this to enable max6370 watchdog timer. @@ -383,10 +384,10 @@ config WDT_SBSA bool "SBSA watchdog timer support" depends on WDT help - Select this to enable SBSA watchdog timer. - This driver can operate ARM SBSA Generic Watchdog as a single stage. - In the single stage mode, when the timeout is reached, your system - will be reset by WS1. The first signal (WS0) is ignored. + Select this to enable SBSA watchdog timer. + This driver can operate ARM SBSA Generic Watchdog as a single stage. + In the single stage mode, when the timeout is reached, your system + will be reset by WS1. The first signal (WS0) is ignored. config WDT_SIEMENS_PMIC bool "Enable PMIC Watchdog Timer support for Siemens platforms" diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index bd9d7105366..91228de5e8e 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -122,7 +122,7 @@ static int designware_wdt_probe(struct udevice *dev) return ret; ret = clk_enable(&clk); - if (ret) + if (ret && ret != -ENOSYS) return ret; priv->clk_khz = clk_get_rate(&clk) / 1000; diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index 7fcb866f574..068f99c5fc6 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -81,7 +81,7 @@ static int mpc8xxx_wdt_of_to_plat(struct udevice *dev) { struct mpc8xxx_wdt_priv *priv = dev_get_priv(dev); - priv->base = (void __iomem *)devfdt_remap_addr(dev); + priv->base = (void __iomem *)dev_remap_addr(dev); if (!priv->base) return -EINVAL; diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c index c79d9539c13..7299a9f9739 100644 --- a/drivers/watchdog/octeontx_wdt.c +++ b/drivers/watchdog/octeontx_wdt.c @@ -159,7 +159,8 @@ static const struct octeontx_wdt_data octeon_data = { }; static const struct udevice_id octeontx_wdt_ids[] = { - { .compatible = "arm,sbsa-gwdt", .data = (ulong)&octeontx_data }, + { .compatible = "marvell,cn10624-wdt", .data = (ulong)&octeontx_data }, + { .compatible = "marvell,cn9670-wdt", .data = (ulong)&octeontx_data }, { .compatible = "cavium,octeon-7890-ciu3", .data = (ulong)&octeon_data }, {} }; diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index a2000b968c9..5a6cad135aa 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -40,8 +40,14 @@ struct orion_wdt_priv { #define TIMER_A370_STATUS 0x04 #define WDT_AXP_FIXED_ENABLE_BIT BIT(10) +#define TIMER1_FIXED_ENABLE_BIT BIT(12) #define WDT_A370_EXPIRED BIT(31) +struct orion_watchdog_data { + int (*plat_start)(struct udevice *dev, u64 timeout, ulong flags); + int (*plat_stop)(struct udevice *dev); +}; + static int orion_wdt_reset(struct udevice *dev) { struct orion_wdt_priv *priv = dev_get_priv(dev); @@ -53,7 +59,59 @@ static int orion_wdt_reset(struct udevice *dev) return 0; } -static int orion_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +static int armadaxp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct orion_wdt_priv *priv = dev_get_priv(dev); + u32 reg; + + priv->timeout = DIV_ROUND_UP(timeout_ms, 1000); + + /* Fix the wdt and timer1 clock freqency to 25MHz */ + reg = readl(priv->reg + TIMER_CTRL); + reg |= (WDT_AXP_FIXED_ENABLE_BIT | TIMER1_FIXED_ENABLE_BIT); + writel(reg, priv->reg + TIMER_CTRL); + + /* Set watchdog duration */ + writel(priv->clk_rate * priv->timeout, + priv->reg + priv->wdt_counter_offset); + + /* Clear the watchdog expiration bit */ + reg = readl(priv->reg + TIMER_A370_STATUS); + reg &= ~WDT_A370_EXPIRED; + writel(reg, priv->reg + TIMER_A370_STATUS); + + /* Enable watchdog timer */ + reg = readl(priv->reg + TIMER_CTRL); + reg |= WDT_ENABLE_BIT; + writel(reg, priv->reg + TIMER_CTRL); + + /* Enable reset on watchdog */ + reg = readl(priv->rstout); + reg |= RSTOUT_ENABLE_BIT; + writel(reg, priv->rstout); + + return 0; +} + +static int armadaxp_wdt_stop(struct udevice *dev) +{ + struct orion_wdt_priv *priv = dev_get_priv(dev); + u32 reg; + + /* Disable reset on watchdog */ + reg = readl(priv->rstout); + reg &= ~RSTOUT_ENABLE_BIT; + writel(reg, priv->rstout); + + /* Disable watchdog timer */ + reg = readl(priv->reg + TIMER_CTRL); + reg &= ~WDT_ENABLE_BIT; + writel(reg, priv->reg + TIMER_CTRL); + + return 0; +} + +static int armada380_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) { struct orion_wdt_priv *priv = dev_get_priv(dev); u32 reg; @@ -91,7 +149,7 @@ static int orion_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) return 0; } -static int orion_wdt_stop(struct udevice *dev) +static int armada380_wdt_stop(struct udevice *dev) { struct orion_wdt_priv *priv = dev_get_priv(dev); u32 reg; @@ -113,13 +171,29 @@ static int orion_wdt_stop(struct udevice *dev) return 0; } +static int orion_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct orion_watchdog_data *data = + (struct orion_watchdog_data *)dev_get_driver_data(dev); + + return data->plat_start(dev, timeout_ms, flags); +} + +static int orion_wdt_stop(struct udevice *dev) +{ + struct orion_watchdog_data *data = + (struct orion_watchdog_data *)dev_get_driver_data(dev); + + return data->plat_stop(dev); +} + static inline bool save_reg_from_ofdata(struct udevice *dev, int index, void __iomem **reg, int *offset) { fdt_addr_t addr; fdt_size_t off; - addr = devfdt_get_addr_size_index(dev, index, &off); + addr = dev_read_addr_size_index(dev, index, &off); if (addr == FDT_ADDR_T_NONE) return false; @@ -141,8 +215,10 @@ static int orion_wdt_of_to_plat(struct udevice *dev) if (!save_reg_from_ofdata(dev, 1, &priv->rstout, NULL)) goto err; - if (!save_reg_from_ofdata(dev, 2, &priv->rstout_mask, NULL)) - goto err; + if (device_is_compatible(dev, "marvell,armada-380-wdt")) { + if (!save_reg_from_ofdata(dev, 2, &priv->rstout_mask, NULL)) + goto err; + } return 0; err: @@ -173,9 +249,20 @@ static const struct wdt_ops orion_wdt_ops = { .stop = orion_wdt_stop, }; +static struct orion_watchdog_data armada380_data = { + .plat_start = armada380_wdt_start, + .plat_stop = armada380_wdt_stop, +}; + +static struct orion_watchdog_data armadaxp_data = { + .plat_start = armadaxp_wdt_start, + .plat_stop = armadaxp_wdt_stop, +}; + static const struct udevice_id orion_wdt_ids[] = { - { .compatible = "marvell,armada-380-wdt" }, - {} + { .compatible = "marvell,armada-380-wdt", .data = (ulong)&armada380_data}, + { .compatible = "marvell,armada-xp-wdt", .data = (ulong)&armadaxp_data}, + { } }; U_BOOT_DRIVER(orion_wdt) = { diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c index 7b387266b99..866f555789c 100644 --- a/drivers/watchdog/rti_wdt.c +++ b/drivers/watchdog/rti_wdt.c @@ -39,7 +39,7 @@ #define WDT_PRELOAD_MAX 0xfff struct rti_wdt_priv { - phys_addr_t regs; + void __iomem *regs; unsigned int clk_hz; }; @@ -177,7 +177,7 @@ static int rti_wdt_probe(struct udevice *dev) struct clk clk; int ret; - priv->regs = devfdt_get_addr(dev); + priv->regs = dev_read_addr_ptr(dev); if (!priv->regs) return -EINVAL; diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index 807884c5bc7..3a924cb2b9a 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -50,6 +50,7 @@ static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags) { struct sbsa_gwdt_priv *priv = dev_get_priv(dev); u32 clk; + u64 tout_wdog; /* * it work in the single stage mode in u-boot, @@ -58,8 +59,13 @@ static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags) * to half value of timeout. */ clk = get_tbclk(); - writel(clk / (2 * 1000) * timeout, - priv->reg_control + SBSA_GWDT_WOR); + + /* if requested timeout overflows, clamp it to u32_max */ + tout_wdog = ((u64)clk * timeout) / (2 * 1000); + if (tout_wdog > U32_MAX) + tout_wdog = U32_MAX; + + writel(tout_wdog, priv->reg_control + SBSA_GWDT_WOR); /* writing WCS will cause an explicit watchdog refresh */ writel(SBSA_GWDT_WCS_EN, priv->reg_control + SBSA_GWDT_WCS); diff --git a/drivers/watchdog/starfive_wdt.c b/drivers/watchdog/starfive_wdt.c index ee9ec4cdc3a..d2c16150f4c 100644 --- a/drivers/watchdog/starfive_wdt.c +++ b/drivers/watchdog/starfive_wdt.c @@ -290,9 +290,9 @@ static int starfive_wdt_of_to_plat(struct udevice *dev) { struct starfive_wdt_priv *wdt = dev_get_priv(dev); - wdt->base = (void *)dev_read_addr(dev); + wdt->base = dev_read_addr_ptr(dev); if (!wdt->base) - return -ENODEV; + return -EINVAL; wdt->apb_clk = devm_clk_get(dev, "apb"); if (IS_ERR(wdt->apb_clk)) diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 83f19dc0e86..e3a89031c44 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -7,6 +7,7 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <dm.h> +#include <linux/delay.h> #include <wdt.h> /* @@ -51,11 +52,9 @@ struct ulp_wdt_priv { #define CLK_RATE_1KHZ 1000 #define CLK_RATE_32KHZ 125 -void hw_watchdog_set_timeout(u16 val) +void hw_watchdog_set_timeout(struct wdog_regs *wdog, u16 val) { /* setting timeout value */ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(val, &wdog->toval); } @@ -89,7 +88,7 @@ void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout) while (!(readl(&wdog->cs) & WDGCS_ULK)) ; - hw_watchdog_set_timeout(timeout); + hw_watchdog_set_timeout(wdog, timeout); writel(0, &wdog->win); /* setting 1-kHz clock source, enable counter running, and clear interrupt */ @@ -107,57 +106,20 @@ void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout) ulp_watchdog_reset(wdog); } -void hw_watchdog_reset(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - - ulp_watchdog_reset(wdog); -} - -void hw_watchdog_init(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - - ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS); -} - -#if !CONFIG_IS_ENABLED(SYSRESET) +#if !CONFIG_IS_ENABLED(SYSRESET) && CONFIG_IS_ENABLED(WDT) void reset_cpu(void) { - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - u32 cmd32 = 0; - - if (readl(&wdog->cs) & WDGCS_CMD32EN) { - writel(UNLOCK_WORD, &wdog->cnt); - cmd32 = WDGCS_CMD32EN; - } else { - dmb(); - __raw_writel(UNLOCK_WORD0, &wdog->cnt); - __raw_writel(UNLOCK_WORD1, &wdog->cnt); - dmb(); - } + struct udevice *wdt; - /* Wait WDOG Unlock */ - while (!(readl(&wdog->cs) & WDGCS_ULK)) - ; + for (uclass_first_device(UCLASS_WDT, &wdt); + wdt; + uclass_next_device(&wdt)) { + if (!dev_read_enabled(wdt)) + continue; - hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout for imx93 */ - writel(0, &wdog->win); - - /* enable counter running */ - if (IS_ENABLED(CONFIG_ARCH_IMX9)) - writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES | - WDGCS_INT), &wdog->cs); - else - writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); - - /* Wait WDOG reconfiguration */ - while (!(readl(&wdog->cs) & WDGCS_RCS)) - ; - - hw_watchdog_reset(); - - while (1); + wdt_expire_now(wdt, 0); + break; + } } #endif @@ -184,6 +146,20 @@ static int ulp_wdt_reset(struct udevice *dev) return 0; } +static int ulp_wdt_expire_now(struct udevice *dev, ulong flags) +{ + int ret; + + /* 5ms timeout for all others; 40ms timeout for "fsl,imx93-wdt" */ + ret = ulp_wdt_start(dev, 5, flags); + if (ret) + return ret; + + mdelay(50); + + return 0; +} + static int ulp_wdt_probe(struct udevice *dev) { struct ulp_wdt_priv *priv = dev_get_priv(dev); @@ -202,6 +178,7 @@ static int ulp_wdt_probe(struct udevice *dev) static const struct wdt_ops ulp_wdt_ops = { .start = ulp_wdt_start, .reset = ulp_wdt_reset, + .expire_now = ulp_wdt_expire_now, }; static const struct udevice_id ulp_wdt_ids[] = { |