diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk_scmi.c | 4 | ||||
| -rw-r--r-- | drivers/clk/stm32/clk-stm32h7.c | 4 | ||||
| -rw-r--r-- | drivers/pwm/pwm-stm32.c | 11 | ||||
| -rw-r--r-- | drivers/reset/stm32/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/reset/stm32/stm32-reset-core.c | 2 | ||||
| -rw-r--r-- | drivers/reset/stm32/stm32-reset-mp1.c | 2 | ||||
| -rw-r--r-- | drivers/reset/stm32/stm32-reset-mp25.c | 2 | ||||
| -rw-r--r-- | drivers/reset/stm32/stm32-reset.c | 4 |
8 files changed, 20 insertions, 11 deletions
diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index cfb372e6190..0c9a81cabcc 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -336,8 +336,8 @@ static int scmi_clk_probe(struct udevice *dev) static int __scmi_clk_set_parent(struct clk *clk, struct clk *parent) { struct scmi_clk_parent_set_in in = { - .clock_id = clk->id, - .parent_clk = parent->id, + .clock_id = clk_get_id(clk), + .parent_clk = clk_get_id(parent), }; struct scmi_clk_parent_set_out out; struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index aa3be414a29..df82db69738 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -549,8 +549,8 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; - fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK; - fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT; + fracn1 = readl(®s->pll1fracr) & RCC_PLL1FRACR_FRACN1_MASK; + fracn1 = (fracn1 >> RCC_PLL1FRACR_FRACN1_SHIFT) + 1; vco = (pllsrc / divm1) * divn1; rate = (pllsrc * fracn1) / (divm1 * 8192); diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c index 5fa649b5903..a691f75e4a7 100644 --- a/drivers/pwm/pwm-stm32.c +++ b/drivers/pwm/pwm-stm32.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <asm/arch/timers.h> #include <dm/device_compat.h> +#include <linux/bitfield.h> #include <linux/time.h> #define CCMR_CHANNEL_SHIFT 8 @@ -157,7 +158,14 @@ static void stm32_pwm_detect_complementary(struct udevice *dev) { struct stm32_timers_plat *plat = dev_get_plat(dev_get_parent(dev)); struct stm32_pwm_priv *priv = dev_get_priv(dev); - u32 ccer; + u32 ccer, val; + + if (plat->ipidr) { + /* Simply read from HWCFGR the number of complementary outputs (MP25). */ + val = readl(plat->base + TIM_HWCFGR1); + priv->have_complementary_output = !!FIELD_GET(TIM_HWCFGR1_NB_OF_DT, val); + return; + } /* * If complementary bit doesn't exist writing 1 will have no @@ -192,6 +200,7 @@ static const struct pwm_ops stm32_pwm_ops = { static const struct udevice_id stm32_pwm_ids[] = { { .compatible = "st,stm32-pwm" }, + { .compatible = "st,stm32mp25-pwm" }, { } }; diff --git a/drivers/reset/stm32/Kconfig b/drivers/reset/stm32/Kconfig index 39dcfa0a9ca..fdd88a6bfae 100644 --- a/drivers/reset/stm32/Kconfig +++ b/drivers/reset/stm32/Kconfig @@ -16,7 +16,7 @@ config RESET_STM32MP1 config RESET_STM32MP25 bool "Enable the STM32MP25 reset" - depends on STM32MP25X + depends on STM32MP23X || STM32MP25X default y help Support for reset controllers on STMicroelectronics STM32MP2 family SoCs. diff --git a/drivers/reset/stm32/stm32-reset-core.c b/drivers/reset/stm32/stm32-reset-core.c index 7dd92e07e1a..9eeed6536e0 100644 --- a/drivers/reset/stm32/stm32-reset-core.c +++ b/drivers/reset/stm32/stm32-reset-core.c @@ -6,7 +6,7 @@ #include <dm.h> #include <reset-uclass.h> -#include <stm32-reset-core.h> +#include "stm32-reset-core.h" #include <stm32_rcc.h> #include <dm/device_compat.h> #include <linux/iopoll.h> diff --git a/drivers/reset/stm32/stm32-reset-mp1.c b/drivers/reset/stm32/stm32-reset-mp1.c index 6863f6e64b7..ce4532561e5 100644 --- a/drivers/reset/stm32/stm32-reset-mp1.c +++ b/drivers/reset/stm32/stm32-reset-mp1.c @@ -5,7 +5,7 @@ */ #include <dm.h> -#include <stm32-reset-core.h> +#include "stm32-reset-core.h" /* Reset clear offset for STM32MP RCC */ #define RCC_CLR_OFFSET 0x4 diff --git a/drivers/reset/stm32/stm32-reset-mp25.c b/drivers/reset/stm32/stm32-reset-mp25.c index 91c0336bc58..1cbe5c7f3d5 100644 --- a/drivers/reset/stm32/stm32-reset-mp25.c +++ b/drivers/reset/stm32/stm32-reset-mp25.c @@ -5,7 +5,7 @@ */ #include <dm.h> -#include <stm32-reset-core.h> +#include "stm32-reset-core.h" #include <stm32mp25_rcc.h> #include <dt-bindings/reset/st,stm32mp25-rcc.h> diff --git a/drivers/reset/stm32/stm32-reset.c b/drivers/reset/stm32/stm32-reset.c index 975f67f712a..024f15cb25e 100644 --- a/drivers/reset/stm32/stm32-reset.c +++ b/drivers/reset/stm32/stm32-reset.c @@ -5,7 +5,7 @@ */ #include <dm.h> -#include <stm32-reset-core.h> +#include "stm32-reset-core.h" /* Timeout for deassert */ #define STM32_DEASSERT_TIMEOUT_US 10000 @@ -19,7 +19,7 @@ static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *rese ptr_line->offset = bank; ptr_line->bit_idx = offset; - ptr_line->set_clr = true; + ptr_line->set_clr = false; return ptr_line; } |