diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/amcore.h | 2 | ||||
| -rw-r--r-- | include/configs/amd_versal2.h | 9 | ||||
| -rw-r--r-- | include/configs/anbernic-rg-ds-rk3568.h | 12 | ||||
| -rw-r--r-- | include/configs/aquila-imx95.h | 15 | ||||
| -rw-r--r-- | include/configs/bananapi-f3.h | 13 | ||||
| -rw-r--r-- | include/configs/imx95_frdm.h | 23 | ||||
| -rw-r--r-- | include/configs/k1.h | 20 | ||||
| -rw-r--r-- | include/configs/librem5-devkit.h | 36 | ||||
| -rw-r--r-- | include/configs/milkv_duo_256m.h | 12 | ||||
| -rw-r--r-- | include/configs/phycore_imx8mm.h | 5 | ||||
| -rw-r--r-- | include/configs/rcar-gen5-common.h | 4 | ||||
| -rw-r--r-- | include/configs/roc-pc-rk3588s.h | 8 | ||||
| -rw-r--r-- | include/configs/sparrowhawk.h | 121 | ||||
| -rw-r--r-- | include/configs/stmark2.h | 2 | ||||
| -rw-r--r-- | include/configs/toradex-smarc-imx95.h | 15 | ||||
| -rw-r--r-- | include/configs/x960.h | 28 |
16 files changed, 296 insertions, 29 deletions
diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 4c695fb9df9..c6260969064 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -2,7 +2,7 @@ /* * Sysam AMCORE board configuration * - * (C) Copyright 2016 Angelo Dureghello <[email protected]> + * (C) Copyright 2016 Angelo Dureghello <[email protected]> */ #ifndef __AMCORE_CONFIG_H diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index a07e12bd146..00627dcd943 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -19,6 +19,15 @@ #define GICD_BASE 0xe2000000 #define GICR_BASE 0xe2060000 +/* + * The 2VM3654 part has 4 APU cores and 3 GIC ITS blocks (vs 8 cores and a + * single ITS on the base part), which moves the redistributor region up by + * the two extra ITS blocks. The right base is selected at runtime in + * lowlevel_init() based on the PMC TAP IDCODE. + */ +#define GICR_BASE_2VM3654 0xe20a0000 +#define GICR_IDCODE_2VM3654 0x04d98093 + /* Serial setup */ #define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/anbernic-rg-ds-rk3568.h b/include/configs/anbernic-rg-ds-rk3568.h new file mode 100644 index 00000000000..3c5bed952ef --- /dev/null +++ b/include/configs/anbernic-rg-ds-rk3568.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ANBERNIC_RG_DS_RK3568_H +#define __ANBERNIC_RG_DS_RK3568_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3568_common.h> + +#endif diff --git a/include/configs/aquila-imx95.h b/include/configs/aquila-imx95.h index 07d09d138cb..96c11ff2d5b 100644 --- a/include/configs/aquila-imx95.h +++ b/include/configs/aquila-imx95.h @@ -10,16 +10,19 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */ +/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above. + * Actual size is determined at runtime. + */ #define SZ_6G _AC(0x180000000, ULL) -/* first 256MB reserved for firmware */ -#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +/* The first 256MB of SDRAM is reserved for firmware (Cortex M7) */ +#define PHYS_SDRAM_FW_RSVD SZ_256M +#define CFG_SYS_INIT_RAM_ADDR PHYS_SDRAM #define CFG_SYS_INIT_RAM_SIZE SZ_2M -#define CFG_SYS_SDRAM_BASE 0x90000000 -#define PHYS_SDRAM 0x90000000 -#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define PHYS_SDRAM (0x80000000 + PHYS_SDRAM_FW_RSVD) +#define PHYS_SDRAM_SIZE (SZ_2G - PHYS_SDRAM_FW_RSVD) #define PHYS_SDRAM_2_SIZE SZ_6G #define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */ diff --git a/include/configs/bananapi-f3.h b/include/configs/bananapi-f3.h deleted file mode 100644 index 97cf4d72df0..00000000000 --- a/include/configs/bananapi-f3.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2024, Kongyang Liu <[email protected]> - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CFG_SYS_SDRAM_BASE 0x0 -#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/imx95_frdm.h b/include/configs/imx95_frdm.h new file mode 100644 index 00000000000..132eea28643 --- /dev/null +++ b/include/configs/imx95_frdm.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2026 NXP + */ + +#ifndef __IMX95_EVK_H +#define __IMX95_EVK_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 + +#define PHYS_SDRAM_SIZE 0x70000000 /* 2GB - 256MB DDR */ + +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6GB (Totally 8GB) */ + +#endif diff --git a/include/configs/k1.h b/include/configs/k1.h new file mode 100644 index 00000000000..e09c3594905 --- /dev/null +++ b/include/configs/k1.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2024, Kongyang Liu <[email protected]> + * Copyright (C) 2025-2026, RISCstar Ltd. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_NS16550_CLK 14700000 +#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ +#define CFG_SYS_SDRAM_BASE 0x0 + +#define RISCV_MMODE_TIMERBASE 0xe4000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 +#define RISCV_MMODE_TIMER_FREQ 24000000 +#define RISCV_SMODE_TIMER_FREQ 24000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/librem5-devkit.h b/include/configs/librem5-devkit.h new file mode 100644 index 00000000000..9ba6a70d58e --- /dev/null +++ b/include/configs/librem5-devkit.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + * 2018 Emcraft Systems + * 2022 Purism + * 2026 Phosh.mobi e.V. + */ + +#ifndef __LIBREM5_DEVKIT_H +#define __LIBREM5_DEVKIT_H + +/* #define DEBUG */ + +#include <version.h> +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_FSL_USDHC_NUM 2 + +/* UART */ +#define CFG_MXC_UART_BASE UART1_BASE_ADDR + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 + +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */ + +/* Monitor Command Prompt */ + +#define CFG_SYS_FSL_ESDHC_ADDR 0 + +#endif diff --git a/include/configs/milkv_duo_256m.h b/include/configs/milkv_duo_256m.h new file mode 100644 index 00000000000..4d6678b9c84 --- /dev/null +++ b/include/configs/milkv_duo_256m.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2026, Hiago De Franco <[email protected]> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 20e2ab832ee..d4571cc6f39 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -28,6 +28,7 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ - +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE SZ_1G /* 4GB DDR */ #endif /* __PHYCORE_IMX8MM_H */ diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index a0c05521c85..8ccd823cf53 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -27,6 +27,10 @@ #define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (133333333 / 4) +/* HyperFlash */ +#define CFG_SYS_FLASH_BANKS_LIST { 0x34000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA + /* Environment setting */ #define CFG_EXTRA_ENV_SETTINGS \ "rsip_ipl_params_base=0x8c100000\0" \ diff --git a/include/configs/roc-pc-rk3588s.h b/include/configs/roc-pc-rk3588s.h new file mode 100644 index 00000000000..c9316687c38 --- /dev/null +++ b/include/configs/roc-pc-rk3588s.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ROC_PC_RK3588S_H +#define __ROC_PC_RK3588S_H + +#include <configs/rk3588_common.h> + +#endif /* __ROC_PC_RK3588S_H */ diff --git a/include/configs/sparrowhawk.h b/include/configs/sparrowhawk.h index 0524e39229c..a4309953433 100644 --- a/include/configs/sparrowhawk.h +++ b/include/configs/sparrowhawk.h @@ -11,4 +11,125 @@ #include "rcar-gen4-common.h" +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(NVME, nvme, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +/* + * Support for USB-ethernet and PCIe-ethernet is disabled, do not + * initialize either and directly boot via native ethernet only. + */ +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START +#undef BOOTENV_SHARED_USB +#define BOOTENV_SHARED_USB \ + "usb_boot=" \ + "run boot_pci_enum ; usb start ; " \ + BOOTENV_SHARED_BLKDEV_BODY(usb) +#undef BOOTENV_DEV_DHCP +#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \ + "bootcmd_dhcp=" \ + "devtype=" #devtypel "; " \ + "if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \ + "source ${scriptaddr}; " \ + "fi;" \ + BOOTENV_EFI_RUN_DHCP \ + "\0" + +/* Environment setting */ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + \ + "renesas_rcar_gen4_pcie_firmware_sf_offset=0x300000\0" \ + "renesas_rcar_gen4_pcie_firmware_sd_path=lib/firmware/rcar_gen4_pcie.bin\0" \ + "renesas_rcar_gen4_load_firmware=" \ + "env set renesas_rcar_gen4_load_firmware_addr 0x54000000 && " \ + "env set renesas_rcar_gen4_load_firmware_size 0x8000 && " \ + "sf probe && " \ + "sf read ${renesas_rcar_gen4_load_firmware_addr} " \ + "${renesas_rcar_gen4_pcie_firmware_sf_offset} " \ + "${renesas_rcar_gen4_load_firmware_size}\0" \ + "flash_pcie_fw_to_qspi_from_mmc=" \ + "load mmc 0:1 ${loadaddr} " \ + "${renesas_rcar_gen4_pcie_firmware_sd_path} && " \ + "sf probe && " \ + "sf update ${loadaddr} " \ + "${renesas_rcar_gen4_pcie_firmware_sf_offset} " \ + "${filesize}\0" \ + \ + "renesas_update_loader_iface=mmc\0" \ + "renesas_update_loader_dev=0\0" \ + "renesas_update_loader_part=1\0" \ + "renesas_update_loader_sf_offset=0x0\0" \ + "renesas_update_loader_filename=flash.bin\0" \ + "update_loader_from_blk=" \ + "load ${renesas_update_loader_iface} " \ + "${renesas_update_loader_dev}:${renesas_update_loader_part} " \ + "${loadaddr} " \ + "${renesas_update_loader_filename} && " \ + "sf probe && " \ + "sf update ${loadaddr} " \ + "${renesas_update_loader_sf_offset} " \ + "${filesize} && " \ + "reset\0" \ + "update_loader_from_blk01=" \ + "env set renesas_update_loader_dev 0 && " \ + "env set renesas_update_loader_part 1 && " \ + "run update_loader_from_blk\0" \ + "update_loader_from_mmc=" \ + "env set renesas_update_loader_iface mmc && " \ + "run update_loader_from_blk01\0" \ + "update_loader_from_nvme=" \ + "pci enum && nvme scan && " \ + "env set renesas_update_loader_iface nvme && " \ + "run update_loader_from_blk01\0" \ + "update_loader_from_usb=" \ + "pci enum && usb start && " \ + "env set renesas_update_loader_iface usb && " \ + "run update_loader_from_blk01\0" \ + \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scan_dev_for_scripts=" \ + "if test -e ${devtype} ${devnum}:${distro_bootpart} " \ + "${prefix}fitImage; then " \ + "echo Found fitImage ${prefix}fitImage ; " \ + "if test ${devtype} = \"mmc\" ; then " \ + "env set bootargs \"${bootargs} " \ + "root=/dev/mmcblk0p1\" ; " \ + "elif test ${devtype} = \"nvme\" ; then " \ + "env set bootargs \"${bootargs} " \ + "root=/dev/nvme0n1p1\" ; " \ + "elif test ${devtype} = \"usb\" ; then " \ + "env set bootargs \"${bootargs} " \ + "root=/dev/sda1\" ; " \ + "else " \ + "part uuid ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "uuid ; " \ + "env set bootargs \"${bootargs} " \ + "root=PARTUUID=${uuid}\" ; " \ + "fi ; " \ + "env set bootargs \"${bootargs} rw rootwait\" ; " \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}fitImage && " \ + "source ${scriptaddr}:script ; " \ + "echo fitImage script FAILED: continuing...; " \ + "fi; " \ + "for script in ${boot_scripts}; do " \ + "if test -e ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${prefix}${script}; then " \ + "echo Found U-Boot script " \ + "${prefix}${script}; " \ + "run boot_a_script; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi; " \ + "done\0" + #endif /* __SPARROWHAWK_H */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index c1096398359..a42779621fc 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -2,7 +2,7 @@ /* * Sysam stmark2 board configuration * - * (C) Copyright 2017 Angelo Dureghello <[email protected]> + * (C) Copyright 2017 Angelo Dureghello <[email protected]> */ #ifndef __STMARK2_CONFIG_H diff --git a/include/configs/toradex-smarc-imx95.h b/include/configs/toradex-smarc-imx95.h index 8a880b96503..97e3322ac28 100644 --- a/include/configs/toradex-smarc-imx95.h +++ b/include/configs/toradex-smarc-imx95.h @@ -7,16 +7,19 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */ +/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above. + * Actual size is determined at runtime. + */ #define SZ_6G _AC(0x180000000, ULL) -/* first 256MB reserved for firmware */ -#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +/* The first 256MB of SDRAM is reserved for firmware (Cortex M7) */ +#define PHYS_SDRAM_FW_RSVD SZ_256M +#define CFG_SYS_INIT_RAM_ADDR PHYS_SDRAM #define CFG_SYS_INIT_RAM_SIZE SZ_2M -#define CFG_SYS_SDRAM_BASE 0x90000000 -#define PHYS_SDRAM 0x90000000 -#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define PHYS_SDRAM (0x80000000 + PHYS_SDRAM_FW_RSVD) +#define PHYS_SDRAM_SIZE (SZ_2G - PHYS_SDRAM_FW_RSVD) #define PHYS_SDRAM_2_SIZE SZ_6G #endif diff --git a/include/configs/x960.h b/include/configs/x960.h new file mode 100644 index 00000000000..b9699518751 --- /dev/null +++ b/include/configs/x960.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2026 Allied Telesis + */ + +#ifndef __X960_H_ +#define __X960_H_ + +/* + * High Level Configuration Options (easy to change) + */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ + +/* additions for new ARM relocation support */ +#define CFG_SYS_SDRAM_BASE 0x00000000 + +#define BOOT_TARGETS "usb scsi pxe dhcp" + +#define CFG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x6d00000\0" \ + "pxefile_addr_r=0x6e00000\0" \ + "fdt_addr_r=0x6f00000\0" \ + "kernel_addr_r=0x7000000\0" \ + "ramdisk_addr_r=0xa000000\0" \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __X960_H_ */ |