diff options
Diffstat (limited to 'include')
46 files changed, 891 insertions, 242 deletions
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index 4895366a618..ac50ea10312 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -674,6 +674,7 @@ struct __packed acpi_dmar { #define ACPI_DBG2_ARM_SBSA_GENERIC 0x000E #define ACPI_DBG2_ARM_DCC 0x000F #define ACPI_DBG2_BCM2835 0x0010 +#define ACPI_DBG2_16550_WITH_GAS 0x0012 /* 16550-compatible UART with GAS */ #define ACPI_DBG2_1394_STANDARD 0x0000 diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 4c695fb9df9..c6260969064 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -2,7 +2,7 @@ /* * Sysam AMCORE board configuration * - * (C) Copyright 2016 Angelo Dureghello <[email protected]> + * (C) Copyright 2016 Angelo Dureghello <[email protected]> */ #ifndef __AMCORE_CONFIG_H diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index a07e12bd146..00627dcd943 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -19,6 +19,15 @@ #define GICD_BASE 0xe2000000 #define GICR_BASE 0xe2060000 +/* + * The 2VM3654 part has 4 APU cores and 3 GIC ITS blocks (vs 8 cores and a + * single ITS on the base part), which moves the redistributor region up by + * the two extra ITS blocks. The right base is selected at runtime in + * lowlevel_init() based on the PMC TAP IDCODE. + */ +#define GICR_BASE_2VM3654 0xe20a0000 +#define GICR_IDCODE_2VM3654 0x04d98093 + /* Serial setup */ #define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/anbernic-rg-ds-rk3568.h b/include/configs/anbernic-rg-ds-rk3568.h new file mode 100644 index 00000000000..3c5bed952ef --- /dev/null +++ b/include/configs/anbernic-rg-ds-rk3568.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ANBERNIC_RG_DS_RK3568_H +#define __ANBERNIC_RG_DS_RK3568_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3568_common.h> + +#endif diff --git a/include/configs/aquila-imx95.h b/include/configs/aquila-imx95.h index 07d09d138cb..96c11ff2d5b 100644 --- a/include/configs/aquila-imx95.h +++ b/include/configs/aquila-imx95.h @@ -10,16 +10,19 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */ +/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above. + * Actual size is determined at runtime. + */ #define SZ_6G _AC(0x180000000, ULL) -/* first 256MB reserved for firmware */ -#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +/* The first 256MB of SDRAM is reserved for firmware (Cortex M7) */ +#define PHYS_SDRAM_FW_RSVD SZ_256M +#define CFG_SYS_INIT_RAM_ADDR PHYS_SDRAM #define CFG_SYS_INIT_RAM_SIZE SZ_2M -#define CFG_SYS_SDRAM_BASE 0x90000000 -#define PHYS_SDRAM 0x90000000 -#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define PHYS_SDRAM (0x80000000 + PHYS_SDRAM_FW_RSVD) +#define PHYS_SDRAM_SIZE (SZ_2G - PHYS_SDRAM_FW_RSVD) #define PHYS_SDRAM_2_SIZE SZ_6G #define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */ diff --git a/include/configs/bananapi-f3.h b/include/configs/bananapi-f3.h deleted file mode 100644 index 97cf4d72df0..00000000000 --- a/include/configs/bananapi-f3.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2024, Kongyang Liu <[email protected]> - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CFG_SYS_SDRAM_BASE 0x0 -#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/imx95_frdm.h b/include/configs/imx95_frdm.h new file mode 100644 index 00000000000..132eea28643 --- /dev/null +++ b/include/configs/imx95_frdm.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2026 NXP + */ + +#ifndef __IMX95_EVK_H +#define __IMX95_EVK_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 + +#define PHYS_SDRAM_SIZE 0x70000000 /* 2GB - 256MB DDR */ + +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6GB (Totally 8GB) */ + +#endif diff --git a/include/configs/k1.h b/include/configs/k1.h new file mode 100644 index 00000000000..e09c3594905 --- /dev/null +++ b/include/configs/k1.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2024, Kongyang Liu <[email protected]> + * Copyright (C) 2025-2026, RISCstar Ltd. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_NS16550_CLK 14700000 +#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ +#define CFG_SYS_SDRAM_BASE 0x0 + +#define RISCV_MMODE_TIMERBASE 0xe4000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 +#define RISCV_MMODE_TIMER_FREQ 24000000 +#define RISCV_SMODE_TIMER_FREQ 24000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/librem5-devkit.h b/include/configs/librem5-devkit.h new file mode 100644 index 00000000000..9ba6a70d58e --- /dev/null +++ b/include/configs/librem5-devkit.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 NXP + * 2018 Emcraft Systems + * 2022 Purism + * 2026 Phosh.mobi e.V. + */ + +#ifndef __LIBREM5_DEVKIT_H +#define __LIBREM5_DEVKIT_H + +/* #define DEBUG */ + +#include <version.h> +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_FSL_USDHC_NUM 2 + +/* UART */ +#define CFG_MXC_UART_BASE UART1_BASE_ADDR + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 + +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */ + +/* Monitor Command Prompt */ + +#define CFG_SYS_FSL_ESDHC_ADDR 0 + +#endif diff --git a/include/configs/milkv_duo_256m.h b/include/configs/milkv_duo_256m.h new file mode 100644 index 00000000000..4d6678b9c84 --- /dev/null +++ b/include/configs/milkv_duo_256m.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2026, Hiago De Franco <[email protected]> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 20e2ab832ee..d4571cc6f39 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -28,6 +28,7 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ - +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE SZ_1G /* 4GB DDR */ #endif /* __PHYCORE_IMX8MM_H */ diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index a0c05521c85..8ccd823cf53 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -27,6 +27,10 @@ #define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (133333333 / 4) +/* HyperFlash */ +#define CFG_SYS_FLASH_BANKS_LIST { 0x34000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA + /* Environment setting */ #define CFG_EXTRA_ENV_SETTINGS \ "rsip_ipl_params_base=0x8c100000\0" \ diff --git a/include/configs/roc-pc-rk3588s.h b/include/configs/roc-pc-rk3588s.h new file mode 100644 index 00000000000..c9316687c38 --- /dev/null +++ b/include/configs/roc-pc-rk3588s.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ROC_PC_RK3588S_H +#define __ROC_PC_RK3588S_H + +#include <configs/rk3588_common.h> + +#endif /* __ROC_PC_RK3588S_H */ diff --git a/include/configs/sparrowhawk.h b/include/configs/sparrowhawk.h index 0524e39229c..a4309953433 100644 --- a/include/configs/sparrowhawk.h +++ b/include/configs/sparrowhawk.h @@ -11,4 +11,125 @@ #include "rcar-gen4-common.h" +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(NVME, nvme, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +/* + * Support for USB-ethernet and PCIe-ethernet is disabled, do not + * initialize either and directly boot via native ethernet only. + */ +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START +#undef BOOTENV_SHARED_USB +#define BOOTENV_SHARED_USB \ + "usb_boot=" \ + "run boot_pci_enum ; usb start ; " \ + BOOTENV_SHARED_BLKDEV_BODY(usb) +#undef BOOTENV_DEV_DHCP +#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \ + "bootcmd_dhcp=" \ + "devtype=" #devtypel "; " \ + "if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \ + "source ${scriptaddr}; " \ + "fi;" \ + BOOTENV_EFI_RUN_DHCP \ + "\0" + +/* Environment setting */ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + \ + "renesas_rcar_gen4_pcie_firmware_sf_offset=0x300000\0" \ + "renesas_rcar_gen4_pcie_firmware_sd_path=lib/firmware/rcar_gen4_pcie.bin\0" \ + "renesas_rcar_gen4_load_firmware=" \ + "env set renesas_rcar_gen4_load_firmware_addr 0x54000000 && " \ + "env set renesas_rcar_gen4_load_firmware_size 0x8000 && " \ + "sf probe && " \ + "sf read ${renesas_rcar_gen4_load_firmware_addr} " \ + "${renesas_rcar_gen4_pcie_firmware_sf_offset} " \ + "${renesas_rcar_gen4_load_firmware_size}\0" \ + "flash_pcie_fw_to_qspi_from_mmc=" \ + "load mmc 0:1 ${loadaddr} " \ + "${renesas_rcar_gen4_pcie_firmware_sd_path} && " \ + "sf probe && " \ + "sf update ${loadaddr} " \ + "${renesas_rcar_gen4_pcie_firmware_sf_offset} " \ + "${filesize}\0" \ + \ + "renesas_update_loader_iface=mmc\0" \ + "renesas_update_loader_dev=0\0" \ + "renesas_update_loader_part=1\0" \ + "renesas_update_loader_sf_offset=0x0\0" \ + "renesas_update_loader_filename=flash.bin\0" \ + "update_loader_from_blk=" \ + "load ${renesas_update_loader_iface} " \ + "${renesas_update_loader_dev}:${renesas_update_loader_part} " \ + "${loadaddr} " \ + "${renesas_update_loader_filename} && " \ + "sf probe && " \ + "sf update ${loadaddr} " \ + "${renesas_update_loader_sf_offset} " \ + "${filesize} && " \ + "reset\0" \ + "update_loader_from_blk01=" \ + "env set renesas_update_loader_dev 0 && " \ + "env set renesas_update_loader_part 1 && " \ + "run update_loader_from_blk\0" \ + "update_loader_from_mmc=" \ + "env set renesas_update_loader_iface mmc && " \ + "run update_loader_from_blk01\0" \ + "update_loader_from_nvme=" \ + "pci enum && nvme scan && " \ + "env set renesas_update_loader_iface nvme && " \ + "run update_loader_from_blk01\0" \ + "update_loader_from_usb=" \ + "pci enum && usb start && " \ + "env set renesas_update_loader_iface usb && " \ + "run update_loader_from_blk01\0" \ + \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "scan_dev_for_scripts=" \ + "if test -e ${devtype} ${devnum}:${distro_bootpart} " \ + "${prefix}fitImage; then " \ + "echo Found fitImage ${prefix}fitImage ; " \ + "if test ${devtype} = \"mmc\" ; then " \ + "env set bootargs \"${bootargs} " \ + "root=/dev/mmcblk0p1\" ; " \ + "elif test ${devtype} = \"nvme\" ; then " \ + "env set bootargs \"${bootargs} " \ + "root=/dev/nvme0n1p1\" ; " \ + "elif test ${devtype} = \"usb\" ; then " \ + "env set bootargs \"${bootargs} " \ + "root=/dev/sda1\" ; " \ + "else " \ + "part uuid ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "uuid ; " \ + "env set bootargs \"${bootargs} " \ + "root=PARTUUID=${uuid}\" ; " \ + "fi ; " \ + "env set bootargs \"${bootargs} rw rootwait\" ; " \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}fitImage && " \ + "source ${scriptaddr}:script ; " \ + "echo fitImage script FAILED: continuing...; " \ + "fi; " \ + "for script in ${boot_scripts}; do " \ + "if test -e ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${prefix}${script}; then " \ + "echo Found U-Boot script " \ + "${prefix}${script}; " \ + "run boot_a_script; " \ + "echo SCRIPT FAILED: continuing...; " \ + "fi; " \ + "done\0" + #endif /* __SPARROWHAWK_H */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index c1096398359..a42779621fc 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -2,7 +2,7 @@ /* * Sysam stmark2 board configuration * - * (C) Copyright 2017 Angelo Dureghello <[email protected]> + * (C) Copyright 2017 Angelo Dureghello <[email protected]> */ #ifndef __STMARK2_CONFIG_H diff --git a/include/configs/toradex-smarc-imx95.h b/include/configs/toradex-smarc-imx95.h index 8a880b96503..97e3322ac28 100644 --- a/include/configs/toradex-smarc-imx95.h +++ b/include/configs/toradex-smarc-imx95.h @@ -7,16 +7,19 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h> -/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */ +/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above. + * Actual size is determined at runtime. + */ #define SZ_6G _AC(0x180000000, ULL) -/* first 256MB reserved for firmware */ -#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +/* The first 256MB of SDRAM is reserved for firmware (Cortex M7) */ +#define PHYS_SDRAM_FW_RSVD SZ_256M +#define CFG_SYS_INIT_RAM_ADDR PHYS_SDRAM #define CFG_SYS_INIT_RAM_SIZE SZ_2M -#define CFG_SYS_SDRAM_BASE 0x90000000 -#define PHYS_SDRAM 0x90000000 -#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define PHYS_SDRAM (0x80000000 + PHYS_SDRAM_FW_RSVD) +#define PHYS_SDRAM_SIZE (SZ_2G - PHYS_SDRAM_FW_RSVD) #define PHYS_SDRAM_2_SIZE SZ_6G #endif diff --git a/include/configs/x960.h b/include/configs/x960.h new file mode 100644 index 00000000000..b9699518751 --- /dev/null +++ b/include/configs/x960.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2026 Allied Telesis + */ + +#ifndef __X960_H_ +#define __X960_H_ + +/* + * High Level Configuration Options (easy to change) + */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ + +/* additions for new ARM relocation support */ +#define CFG_SYS_SDRAM_BASE 0x00000000 + +#define BOOT_TARGETS "usb scsi pxe dhcp" + +#define CFG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x6d00000\0" \ + "pxefile_addr_r=0x6e00000\0" \ + "fdt_addr_r=0x6f00000\0" \ + "kernel_addr_r=0x7000000\0" \ + "ramdisk_addr_r=0xa000000\0" \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __X960_H_ */ diff --git a/include/cyclic.h b/include/cyclic.h index df8b725e3d0..ec2c53b6ecf 100644 --- a/include/cyclic.h +++ b/include/cyclic.h @@ -78,15 +78,6 @@ void cyclic_unregister(struct cyclic_info *cyclic); */ int cyclic_unregister_all(void); -/** - * cyclic_get_list() - Get cyclic list pointer - * - * Return the cyclic list pointer - * - * @return: pointer to cyclic_list - */ -struct hlist_head *cyclic_get_list(void); - #else static inline void cyclic_register(struct cyclic_info *cyclic, cyclic_func_t func, diff --git a/include/dm/platform_data/serial_coldfire.h b/include/dm/platform_data/serial_coldfire.h index 5e265e9087d..86dc57e140e 100644 --- a/include/dm/platform_data/serial_coldfire.h +++ b/include/dm/platform_data/serial_coldfire.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (c) 2015 Angelo Dureghello <[email protected]> + * Copyright (c) 2015 Angelo Dureghello <[email protected]> */ #ifndef __serial_coldfire_h diff --git a/include/dm/platform_data/spi_coldfire.h b/include/dm/platform_data/spi_coldfire.h index 0d534b1d665..b88c51e910f 100644 --- a/include/dm/platform_data/spi_coldfire.h +++ b/include/dm/platform_data/spi_coldfire.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (c) 2018 Angelo Dureghello <[email protected]> + * Copyright (c) 2018 Angelo Dureghello <[email protected]> */ #ifndef __spi_coldfire_h diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h deleted file mode 100644 index 1c28d6cb1fa..00000000000 --- a/include/dt-bindings/pinctrl/rockchip.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Header providing constants for Rockchip pinctrl bindings. - * - * Copyright (c) 2013 MundoReader S.L. - * Author: Heiko Stuebner <[email protected]> - */ - -#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ -#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ - -#define RK_GPIO0 0 -#define RK_GPIO1 1 -#define RK_GPIO2 2 -#define RK_GPIO3 3 -#define RK_GPIO4 4 -#define RK_GPIO6 6 - -#define RK_PA0 0 -#define RK_PA1 1 -#define RK_PA2 2 -#define RK_PA3 3 -#define RK_PA4 4 -#define RK_PA5 5 -#define RK_PA6 6 -#define RK_PA7 7 -#define RK_PB0 8 -#define RK_PB1 9 -#define RK_PB2 10 -#define RK_PB3 11 -#define RK_PB4 12 -#define RK_PB5 13 -#define RK_PB6 14 -#define RK_PB7 15 -#define RK_PC0 16 -#define RK_PC1 17 -#define RK_PC2 18 -#define RK_PC3 19 -#define RK_PC4 20 -#define RK_PC5 21 -#define RK_PC6 22 -#define RK_PC7 23 -#define RK_PD0 24 -#define RK_PD1 25 -#define RK_PD2 26 -#define RK_PD3 27 -#define RK_PD4 28 -#define RK_PD5 29 -#define RK_PD6 30 -#define RK_PD7 31 - -#define RK_FUNC_GPIO 0 -#define RK_FUNC_1 1 -#define RK_FUNC_2 2 -#define RK_FUNC_3 3 -#define RK_FUNC_4 4 -#define RK_FUNC_5 5 -#define RK_FUNC_6 6 - -#endif diff --git a/include/dt-bindings/reset/r8a78000-reset-scmi.h b/include/dt-bindings/reset/r8a78000-reset-scmi.h index 3d84bfb073a..bf8c1b710f0 100644 --- a/include/dt-bindings/reset/r8a78000-reset-scmi.h +++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h @@ -24,4 +24,6 @@ #define SCP_RESET_DOMAIN_ID_MPPHY31 0x67 #define SCP_RESET_DOMAIN_ID_MPPHY02 0x68 +#define SCP_RESET_DOMAIN_ID_SCP 0x20 + #endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */ diff --git a/include/dt-bindings/reset/spacemit-k1-reset.h b/include/dt-bindings/reset/spacemit-k1-reset.h deleted file mode 100644 index 74db58b27ef..00000000000 --- a/include/dt-bindings/reset/spacemit-k1-reset.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 Spacemit Inc. - * Copyright (C) 2025 Huan Zhou <[email protected]> - */ - -#ifndef __DT_BINDINGS_RESET_SAPCEMIT_K1_H__ -#define __DT_BINDINGS_RESET_SAPCEMIT_K1_H__ -/* APBC */ -#define RESET_UART1 1 -#define RESET_UART2 2 -#define RESET_GPIO 3 -#define RESET_PWM0 4 -#define RESET_PWM1 5 -#define RESET_PWM2 6 -#define RESET_PWM3 7 -#define RESET_PWM4 8 -#define RESET_PWM5 9 -#define RESET_PWM6 10 -#define RESET_PWM7 11 -#define RESET_PWM8 12 -#define RESET_PWM9 13 -#define RESET_PWM10 14 -#define RESET_PWM11 15 -#define RESET_PWM12 16 -#define RESET_PWM13 17 -#define RESET_PWM14 18 -#define RESET_PWM15 19 -#define RESET_PWM16 20 -#define RESET_PWM17 21 -#define RESET_PWM18 22 -#define RESET_PWM19 23 -#define RESET_SSP3 24 -#define RESET_UART3 25 -#define RESET_RTC 26 -#define RESET_TWSI0 27 -#define RESET_TIMERS1 28 -#define RESET_AIB 29 -#define RESET_TIMERS2 30 -#define RESET_ONEWIRE 31 -#define RESET_SSPA0 32 -#define RESET_SSPA1 33 -#define RESET_DRO 34 -#define RESET_IR 35 -#define RESET_TWSI1 36 -#define RESET_TSEN 37 -#define RESET_TWSI2 38 -#define RESET_TWSI4 39 -#define RESET_TWSI5 40 -#define RESET_TWSI6 41 -#define RESET_TWSI7 42 -#define RESET_TWSI8 43 -#define RESET_IPC_AP2AUD 44 -#define RESET_UART4 45 -#define RESET_UART5 46 -#define RESET_UART6 47 -#define RESET_UART7 48 -#define RESET_UART8 49 -#define RESET_UART9 50 -#define RESET_CAN0 51 - -/* MPMU */ -#define RESET_WDT 52 - -/* APMU */ -#define RESET_JPG 53 -#define RESET_CSI 54 -#define RESET_CCIC2_PHY 55 -#define RESET_CCIC3_PHY 56 -#define RESET_ISP 57 -#define RESET_ISP_AHB 58 -#define RESET_ISP_CI 59 -#define RESET_ISP_CPP 60 -#define RESET_LCD 61 -#define RESET_DSI_ESC 62 -#define RESET_V2D 63 -#define RESET_MIPI 64 -#define RESET_LCD_SPI 65 -#define RESET_LCD_SPI_BUS 66 -#define RESET_LCD_SPI_HBUS 67 -#define RESET_LCD_MCLK 68 -#define RESET_CCIC_4X 69 -#define RESET_CCIC1_PHY 70 -#define RESET_SDH_AXI 71 -#define RESET_SDH0 72 -#define RESET_SDH1 73 -#define RESET_USB_AXI 74 -#define RESET_USBP1_AXI 75 -#define RESET_USB3_0 76 -#define RESET_QSPI 77 -#define RESET_QSPI_BUS 78 -#define RESET_DMA 79 -#define RESET_AES 80 -#define RESET_VPU 81 -#define RESET_GPU 82 -#define RESET_SDH2 83 -#define RESET_MC 84 -#define RESET_EM_AXI 85 -#define RESET_EM 86 -#define RESET_AUDIO_SYS 87 -#define RESET_HDMI 88 -#define RESET_PCIE0 89 -#define RESET_PCIE1 90 -#define RESET_PCIE2 91 -#define RESET_EMAC0 92 -#define RESET_EMAC1 93 - -/* APBC2 */ -#define RESET_SEC_UART1 94 -#define RESET_SEC_SSP2 95 -#define RESET_SEC_TWSI3 96 -#define RESET_SEC_RTC 97 -#define RESET_SEC_TIMERS0 98 -#define RESET_SEC_KPC 99 -#define RESET_SEC_GPIO 100 -#define RESET_NUMBER 101 - -#endif diff --git a/include/efi.h b/include/efi.h index b98871fedad..a4c21d7681d 100644 --- a/include/efi.h +++ b/include/efi.h @@ -268,6 +268,9 @@ enum efi_memory_type { #define EFI_MEMORY_CPU_CRYPTO ((u64)0x0000000000080000ULL) /* cryptographically protectable */ #define EFI_MEMORY_HOT_PLUGGABLE \ ((u64)0x0000000000100000ULL) /* hot pluggable */ +#define EFI_MEMORY_ISA_MASK ((u64)0x0FFFF00000000000ULL) /* ISA-specific attributes */ +#define EFI_MEMORY_ISA_SHIFT 44 +#define EFI_MEMORY_ISA_VALID ((u64)0x4000000000000000ULL) /* ISA_MASK field is valid */ #define EFI_MEMORY_RUNTIME ((u64)0x8000000000000000ULL) /* range requires runtime mapping */ #define EFI_MEM_DESC_VERSION 1 @@ -682,6 +685,26 @@ int efi_get_mmap(struct efi_mem_desc **descp, int *sizep, uint *keyp, void efi_show_tables(struct efi_system_table *systab); /** + * efi_show_memmap() - print an EFI memory map + * + * Prints one line per descriptor with the memory type name, the physical + * start and end address and the attributes as a '|'-separated list of + * mnemonics. The ISA-specific attribute field is printed as ISA=<value> + * when EFI_MEMORY_ISA_VALID is set, and any remaining bits without a + * mnemonic are printed as a hexadecimal value. + * + * The virtual addresses of the descriptors are not shown: the map is + * identity mapped before SetVirtualAddressMap() is called, so the field + * carries no information at this point. + * + * @map: memory map to print + * @map_size: size of the memory map in bytes + * @desc_size: size of a single descriptor in bytes + */ +void efi_show_memmap(struct efi_mem_desc *map, efi_uintn_t map_size, + efi_uintn_t desc_size); + +/** * efi_get_basename() - Get the default filename to use when loading * * E.g. this function returns BOOTAA64.EFI for an aarch target diff --git a/include/env_callback.h b/include/env_callback.h index 1181ab4a157..572cacde03e 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -70,6 +70,12 @@ #define DFU_CALLBACK #endif +#ifdef CONFIG_BOOT_RETRY +#define BOOTRETRY_CALLBACK "bootretry:bootretry," +#else +#define BOOTRETRY_CALLBACK +#endif + /* * This list of callback bindings is static, but may be overridden by defining * a new association in the ".callbacks" environment variable. @@ -81,6 +87,7 @@ NET6_CALLBACKS \ BOOTSTD_CALLBACK \ DFU_CALLBACK \ + BOOTRETRY_CALLBACK \ "loadaddr:loadaddr," \ SILENT_CALLBACK \ "stdin:console,stdout:console,stderr:console," \ diff --git a/include/image.h b/include/image.h index 4b3c9c87bf5..6edcb1995bf 100644 --- a/include/image.h +++ b/include/image.h @@ -1535,6 +1535,10 @@ int fit_check_format(const void *fit, ulong size); * compatible list, "foo,bar", matches a compatible string in the root of fdt1. * "bim,bam" in fdt2 matches the second string which isn't as good as fdt1. * + * If several configurations match at the same position, the one named by the + * 'default' property of the configurations node is preferred, then the first + * one listed. + * * As an optimization, the compatible property from the FDT's root node can be * copied into the configuration node in the FIT image. This is required to * match configurations with compressed FDTs. @@ -1893,6 +1897,29 @@ struct image_region *fit_region_make_list(const void *fit, struct fdt_region *fdt_regions, int count, struct image_region *region); +/** + * fit_config_get_signed_nodes() - Build the list of nodes covered by a config + * signature + * + * Collects the paths of the nodes that the configuration signature is + * computed over: the root node, the configuration node, and for each image + * referenced by the configuration its node, its hash subnodes and its cipher + * and dm-verity subnodes. The result is the same node list used when creating + * and verifying the signature, and is suitable for passing to + * fdt_find_regions(). + * + * @fit: FIT blob + * @conf_noffset: Configuration node offset + * @node_inc: Array to fill with pointers to packed path strings + * @max_nodes: Number of entries in @node_inc + * @buf: Buffer for the packed null-terminated path strings + * @buf_len: Size of @buf + * Return: number of entries written to @node_inc, or -ve on error + */ +int fit_config_get_signed_nodes(const void *fit, int conf_noffset, + char **node_inc, int max_nodes, + char *buf, int buf_len); + static inline int fit_image_check_target_arch(const void *fdt, int node) { #ifndef USE_HOSTCC diff --git a/include/imx_sip.h b/include/imx_sip.h index 8a5ca34f393..478cbd3fdaf 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -16,5 +16,7 @@ #define IMX_SIP_SRC_MCU_START 0x00 #define IMX_SIP_SRC_MCU_STARTED 0x01 #define IMX_SIP_SRC_MCU_STOP 0x02 +#define IMX_SIP_SRC_MCU_PREP 0x04 +#define IMX_SIP_SRC_MCU_PREPED 0x05 #endif diff --git a/include/linux/hw_bitfield.h b/include/linux/hw_bitfield.h new file mode 100644 index 00000000000..6e74d902ed3 --- /dev/null +++ b/include/linux/hw_bitfield.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2025, Collabora Ltd. + */ + +#ifndef _LINUX_HW_BITFIELD_H +#define _LINUX_HW_BITFIELD_H + +#include <linux/bitfield.h> +#include <linux/build_bug.h> + +/** + * FIELD_PREP_WM16() - prepare a bitfield element with a mask in the upper half + * @_mask: shifted mask defining the field's length and position + * @_val: value to put in the field + * + * FIELD_PREP_WM16() masks and shifts up the value, as well as bitwise ORs the + * result with the mask shifted up by 16. + * + * This is useful for a common design of hardware registers where the upper + * 16-bit half of a 32-bit register is used as a write-enable mask. In such a + * register, a bit in the lower half is only updated if the corresponding bit + * in the upper half is high. + */ +#define FIELD_PREP_WM16(_mask, _val) \ + ({ \ + typeof(_val) __val = _val; \ + typeof(_mask) __mask = _mask; \ + __BF_FIELD_CHECK(__mask, ((u16)0U), __val, \ + "HWORD_UPDATE: "); \ + (((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \ + ((__mask) << 16); \ + }) + +/** + * FIELD_PREP_WM16_CONST() - prepare a constant bitfield element with a mask in + * the upper half + * @_mask: shifted mask defining the field's length and position + * @_val: value to put in the field + * + * FIELD_PREP_WM16_CONST() masks and shifts up the value, as well as bitwise ORs + * the result with the mask shifted up by 16. + * + * This is useful for a common design of hardware registers where the upper + * 16-bit half of a 32-bit register is used as a write-enable mask. In such a + * register, a bit in the lower half is only updated if the corresponding bit + * in the upper half is high. + * + * Unlike FIELD_PREP_WM16(), this is a constant expression and can therefore + * be used in initializers. Error checking is less comfortable for this + * version. + */ +#define FIELD_PREP_WM16_CONST(_mask, _val) \ + ( \ + FIELD_PREP_CONST(_mask, _val) | \ + (BUILD_BUG_ON_ZERO((u64)(_mask) > U16_MAX) + \ + ((_mask) << 16)) \ + ) + + +#endif /* _LINUX_HW_BITFIELD_H */ diff --git a/include/linux/string.h b/include/linux/string.h index 850356d7c3f..986499dfc70 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -43,12 +43,8 @@ extern int strcmp(const char *,const char *); #ifndef __HAVE_ARCH_STRNCMP extern int strncmp(const char *,const char *,__kernel_size_t); #endif -#ifndef __HAVE_ARCH_STRCASECMP int strcasecmp(const char *s1, const char *s2); -#endif -#ifndef __HAVE_ARCH_STRNCASECMP -extern int strncasecmp(const char *s1, const char *s2, __kernel_size_t len); -#endif +int strncasecmp(const char *s1, const char *s2, __kernel_size_t len); #ifndef __HAVE_ARCH_STRCHR extern char * strchr(const char *,int); #endif @@ -63,7 +59,7 @@ extern char * strchr(const char *,int); * @c: character to search for * Return: position of @c in @s, or end of @s if not found */ -const char *strchrnul(const char *s, int c); +char *strchrnul(const char *s, int c); #ifndef __HAVE_ARCH_STRRCHR extern char * strrchr(const char *,int); @@ -75,6 +71,7 @@ extern char * strstr(const char *,const char *); #ifndef __HAVE_ARCH_STRNSTR extern char *strnstr(const char *, const char *, size_t); #endif +char *strcasestr(const char *, const char *); #ifndef __HAVE_ARCH_STRLEN extern __kernel_size_t strlen(const char *); #endif @@ -107,10 +104,6 @@ extern char * strndup(const char *, size_t); extern const char *strdup_const(const char *s); extern void kfree_const(const void *x); -#ifndef __HAVE_ARCH_STRSWAB -extern char * strswab(const char *); -#endif - #ifndef __HAVE_ARCH_MEMSET extern void * memset(void *,int,__kernel_size_t); #endif diff --git a/include/lmb.h b/include/lmb.h index ed472e9ef2e..157a24baf97 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -124,7 +124,7 @@ struct lmb { * Return: 0 on success, -ve value on failure * * When the allocation is of type @LMB_MEM_ALLOC_ADDR, the return value can - * be -EINVAL if the requested memory region is not part of the LMB memory + * be -EFAULT if the requested memory region is not part of the LMB memory * map, and -EEXIST if the requested region is already allocated. */ int lmb_alloc_mem(enum lmb_mem_type type, u64 align, phys_addr_t *addr, @@ -168,6 +168,8 @@ int lmb_is_reserved_flags(phys_addr_t addr, int flags); * @flags: Memory region attributes * * Return: 0 on success, negative error code on failure. + * + * The return value can be -EFAULT when the region has not been allocated. */ long lmb_free(phys_addr_t base, phys_size_t size, u32 flags); diff --git a/include/mmc.h b/include/mmc.h index 9509c9e9543..4bda44ea220 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -67,6 +67,7 @@ struct bd_info; #define MMC_CAP_NONREMOVABLE BIT(14) #define MMC_CAP_NEEDS_POLL BIT(15) #define MMC_CAP_CD_ACTIVE_HIGH BIT(16) +#define MMC_CAP_CMD23 BIT(17) #define MMC_MODE_8BIT BIT(30) #define MMC_MODE_4BIT BIT(29) @@ -141,6 +142,8 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define SD_HIGHSPEED_BUSY 0x00020000 #define SD_HIGHSPEED_SUPPORTED 0x00020000 +#define SD_SCR_CMD23_SUPPORT BIT(1) + #define UHS_SDR12_BUS_SPEED 0 #define HIGH_SPEED_BUS_SPEED 1 #define UHS_SDR25_BUS_SPEED 1 diff --git a/include/mpfs-mailbox.h b/include/mpfs-mailbox.h index c0ff327a4ce..39c998e4c8d 100644 --- a/include/mpfs-mailbox.h +++ b/include/mpfs-mailbox.h @@ -58,6 +58,8 @@ struct mpfs_sys_serv { }; int mpfs_syscontroller_run_service(struct mpfs_syscontroller_priv *sys_controller, struct mpfs_mss_msg *msg); +int mpfs_syscontroller_recv_response(struct mpfs_syscontroller_priv + *sys_controller, struct mpfs_mss_msg *msg, unsigned long timeout_ms); int mpfs_syscontroller_read_sernum(struct mpfs_sys_serv *sys_serv_priv, u8 *device_serial_number); void mpfs_syscontroller_process_dtbo(struct mpfs_sys_serv *sys_serv_priv); struct mpfs_syscontroller_priv *mpfs_syscontroller_get(struct udevice *dev); diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h index 0f6f5c23dee..258623d5c67 100644 --- a/include/mvebu_mmc.h +++ b/include/mvebu_mmc.h @@ -253,8 +253,6 @@ #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type D */ #define MMC_CAP_DRIVER_TYPE_D (1 << 25) -/* CMD23 supported. */ -#define MMC_CAP_CMD23 (1 << 30) /* Hardware reset */ #define MMC_CAP_HW_RESET (1 << 31) diff --git a/include/net-lwip.h b/include/net-lwip.h index 5d0627eb271..8e59a2299e0 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -53,6 +53,7 @@ bool wget_validate_uri(char *uri); int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_nfs(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_tftpsrv(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_wget(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); #endif /* __NET_LWIP_H__ */ diff --git a/include/power/pf9453.h b/include/power/pf9453.h new file mode 100644 index 00000000000..f33b839cde0 --- /dev/null +++ b/include/power/pf9453.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2024 NXP + */ + +#ifndef PF9453_H_ +#define PF9453_H_ + +#define PF9453_REGULATOR_DRIVER "pf9453_regulator" + +enum { + PF9453_REG_DEV_ID = 0x00, + PF9453_OTP_VER = 0x01, + PF9453_INT1 = 0x02, + PF9453_INT1_MSK = 0x03, + PF9453_INT1_STATUS = 0x04, + PF9453_VRFLT1_INT = 0x05, + PF9453_VRFLT1_MASK = 0x06, + PF9453_PWRON_STAT = 0x07, + PF9453_RESET_CTRL = 0x08, + PF9453_SW_RST = 0x09, + PF9453_PWR_CTRL = 0x0a, + PF9453_CONFIG1 = 0x0b, + PF9453_CONFIG2 = 0x0c, + PF9453_32K_CONFIG = 0x0d, + PF9453_BUCK1CTRL = 0x10, + PF9453_BUCK1OUT = 0x11, + PF9453_BUCK2CTRL = 0x14, + PF9453_BUCK2OUT = 0x15, + PF9453_BUCK2OUT_STBY = 0x1D, + PF9453_BUCK2OUT_MAX_LIMIT = 0x1F, + PF9453_BUCK2OUT_MIN_LIMIT = 0x20, + PF9453_BUCK3CTRL = 0x21, + PF9453_BUCK3OUT = 0x22, + PF9453_BUCK4CTRL = 0x2e, + PF9453_BUCK4OUT = 0x2f, + PF9453_LDO1OUT_L = 0x36, + PF9453_LDO1CFG = 0x37, + PF9453_LDO1OUT_H = 0x38, + PF9453_LDOSNVS_CFG1 = 0x39, + PF9453_LDOSNVS_CFG2 = 0x3a, + PF9453_LDO2CFG = 0x3b, + PF9453_LDO2OUT = 0x3c, + PF9453_BUCK_POK = 0x3d, + PF9453_LSW_CTRL1 = 0x40, + PF9453_LSW_CTRL2 = 0x41, + PF9453_REG_LOCK = 0x4e, + PF9453_REG_NUM, +}; + +int power_pf9453_init(unsigned char bus, unsigned char addr); + +enum { + NXP_CHIP_TYPE_PF9453 = 0, + NXP_CHIP_TYPE_AMOUNT +}; + +#define PF9453_UNLOCK_KEY 0x5c +#define PF9453_LOCK_KEY 0x0 + +#define PF9453_EN_MODE_MASK 0x3 +#define PF9453_BUCK_RUN_MASK 0x7f +#define PF9453_LDO1_MASK 0x7f +#define PF9453_LDO2_MASK 0x3f +#define PF9453_LDOSNVS_MASK 0x7f + +#define PF9453_PMIC_RESET_WDOG_B_CFG_MASK 0xc0 +#define PF9453_PMIC_RESET_WDOG_B_CFG_WARM 0x40 +#define PF9453_PMIC_RESET_WDOG_B_CFG_COLD 0x80 + +#endif diff --git a/include/power/spacemit_p1.h b/include/power/spacemit_p1.h new file mode 100644 index 00000000000..ef5a45e8cec --- /dev/null +++ b/include/power/spacemit_p1.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +#ifndef __SPACEMIT_P1_H_ +#define __SPACEMIT_P1_H_ + +#define P1_MAX_REGS 0xA8 + +#define P1_REG_ID 0x0 + +#define P1_ID 0x2 + +#define P1_REG_BUCK1_CTRL 0x47 +#define P1_REG_BUCK2_CTRL 0x4a +#define P1_REG_BUCK3_CTRL 0x4d +#define P1_REG_BUCK4_CTRL 0x50 +#define P1_REG_BUCK5_CTRL 0x53 +#define P1_REG_BUCK6_CTRL 0x56 + +#define P1_REG_BUCK1_VSEL 0x48 +#define P1_REG_BUCK2_VSEL 0x4b +#define P1_REG_BUCK3_VSEL 0x4e +#define P1_REG_BUCK4_VSEL 0x51 +#define P1_REG_BUCK5_VSEL 0x54 +#define P1_REG_BUCK6_VSEL 0x57 + +#define P1_REG_BUCK1_SVSEL 0x49 +#define P1_REG_BUCK2_SVSEL 0x4c +#define P1_REG_BUCK3_SVSEL 0x4f +#define P1_REG_BUCK4_SVSEL 0x52 +#define P1_REG_BUCK5_SVSEL 0x55 +#define P1_REG_BUCK6_SVSEL 0x58 + +#define P1_BUCK_CTRL(x) (0x47 + ((x) - 1) * 3) +#define P1_BUCK_VSEL(x) (0x48 + ((x) - 1) * 3) +#define P1_BUCK_SVSEL(x) (0x49 + ((x) - 1) * 3) + +#define BUCK_VSEL_MASK 0xff +#define BUCK_EN_MASK 0x1 +#define BUCK_SVSEL_MASK 0xff + +#define P1_REG_ALDO1_CTRL 0x5b +#define P1_REG_ALDO2_CTRL 0x5e +#define P1_REG_ALDO3_CTRL 0x61 +#define P1_REG_ALDO4_CTRL 0x64 + +#define P1_REG_ALDO1_VOLT 0x5c +#define P1_REG_ALDO2_VOLT 0x5f +#define P1_REG_ALDO3_VOLT 0x62 +#define P1_REG_ALDO4_VOLT 0x65 + +#define P1_REG_ALDO1_SVOLT 0x5d +#define P1_REG_ALDO2_SVOLT 0x60 +#define P1_REG_ALDO3_SVOLT 0x63 +#define P1_REG_ALDO4_SVOLT 0x66 + +#define P1_ALDO_CTRL(x) (0x5b + ((x) - 1) * 3) +#define P1_ALDO_VOLT(x) (0x5c + ((x) - 1) * 3) +#define P1_ALDO_SVOLT(x) (0x5d + ((x) - 1) * 3) + +#define ALDO_SVSEL_MASK 0x7f +#define ALDO_EN_MASK 0x1 +#define ALDO_VSEL_MASK 0x7f + +#define P1_REG_DLDO1_CTRL 0x67 +#define P1_REG_DLDO2_CTRL 0x6a +#define P1_REG_DLDO3_CTRL 0x6d +#define P1_REG_DLDO4_CTRL 0x70 +#define P1_REG_DLDO5_CTRL 0x73 +#define P1_REG_DLDO6_CTRL 0x76 +#define P1_REG_DLDO7_CTRL 0x79 + +#define P1_REG_DLDO1_VOLT 0x68 +#define P1_REG_DLDO2_VOLT 0x6b +#define P1_REG_DLDO3_VOLT 0x6e +#define P1_REG_DLDO4_VOLT 0x71 +#define P1_REG_DLDO5_VOLT 0x74 +#define P1_REG_DLDO6_VOLT 0x77 +#define P1_REG_DLDO7_VOLT 0x7a + +#define P1_REG_DLDO1_SVOLT 0x69 +#define P1_REG_DLDO2_SVOLT 0x6c +#define P1_REG_DLDO3_SVOLT 0x6f +#define P1_REG_DLDO4_SVOLT 0x72 +#define P1_REG_DLDO5_SVOLT 0x75 +#define P1_REG_DLDO6_SVOLT 0x78 +#define P1_REG_DLDO7_SVOLT 0x7b + +#define P1_DLDO_CTRL(x) (0x67 + ((x) - 1) * 3) +#define P1_DLDO_VOLT(x) (0x68 + ((x) - 1) * 3) +#define P1_DLDO_SVOLT(x) (0x69 + ((x) - 1) * 3) + +#define DLDO_SVSEL_MASK 0x7f +#define DLDO_EN_MASK 0x1 +#define DLDO_VSEL_MASK 0x7f + +#define P1_REG_SWITCH_CTRL 0x59 +#define P1_SWTICH_EN_MASK 0x1 + +#define P1_REG_SWITCH_PWRKEY_EVENT_CTRL 0x97 +#define P1_SWITCH_PWRKEY_EVENT_EN_MSK 0xf + +#define P1_REG_SWITCH_PWRKEY_INIT_CTRL 0x9e +#define P1_SWITCH_PWRKEY_INT_EN_MSK 0xf + +/* Watchdog Timer Registers */ +#define P1_WDT_CTRL 0x44 +#define P1_PWR_CTRL0 0x7C +#define P1_PWR_CTRL2 0x7E +#define P1_PWR_CTRL2_MSK 0xff + +/* Watchdog Timer Control Bits */ +#define P1_WDT_CLEAR_STATUS 0x1 +#define P1_SW_RST 0x2 +#define P1_WDT_RESET_ENABLE 0x80 +#define P1_WDT_ENABLE 0x8 +#define P1_WDT_TIMEOUT_1S 0x0 +#define P1_WDT_TIMEOUT_4S 0x1 +#define P1_WDT_TIMEOUT_8S 0x2 +#define P1_WDT_TIMEOUT_16S 0x3 + +#define P1_RTC_TICK_CTRL 0x1d +#define P1_RTC_TICK_CTRL_MSK 0x7f + +#define P1_RTC_TICK_EVENT 0x92 +#define P1_RTC_TICK_EVENT_MSK 0x3f + +#define P1_RTC_TICK_IRQ 0x99 +#define P1_RTC_TICK_IRQ_MSK 0x3f + +#define P1_REG_ALIVE 0xab +#define P1_ALIVE_MSK 0x7 +#define SYS_REBOOT_FLAG_BIT 0x2 + +/* SWITCH ID */ +enum { + P1_ID_SWITCH1, + P1_ID_SWITCH1_PWRKEY_EVENT, + P1_ID_SWITCH1_PWRKEY_INT, + P1_ID_SWITCH_RTC_TICK_CTRL, + P1_ID_SWITCH_RTC_TICK_EVENT, + P1_ID_SWITCH_RTC_TCK_IRQ, + P1_ID_SWITCH_POWER_DOWN, + P1_ID_SWITCH_CHARGING_FLAG, +}; + +/* POWERKEY events */ +enum { + PWRKEY_RISING_EVENT = 1, + PWRKEY_FAILING_EVENT = 2, + PWRKEY_SHORT_PRESS_EVENT = 4, + PWRKEY_LONG_PRESS_EVENT = 8, +}; + +#define P1_BUCK_DRIVER "p1_buck" +#define P1_ALDO_DRIVER "p1_aldo" +#define P1_DLDO_DRIVER "p1_dldo" +#define P1_SWITCH_DRIVER "p1_switch" +#define P1_WDT_DRIVER "p1_wdt" + +#endif /* __SPACEMIT_P1_H_ */ diff --git a/include/power/tps65219.h b/include/power/tps65219.h index e8780af2d81..c3114f26e1d 100644 --- a/include/power/tps65219.h +++ b/include/power/tps65219.h @@ -47,10 +47,10 @@ #define TPS65219_LDO12_VOLT_MIN 600000 #define TPS65219_LDO12_VOLT_MAX 3400000 #define TPS65219_LDO12_VOLT_REG_MIN 0 -#define TPS65219_LDO12_VOLT_REG_MAX 0x56 +#define TPS65219_LDO12_VOLT_REG_MAX 0x38 #define TPS65219_LDO34_VOLT_MIN 1200000 #define TPS65219_LDO34_VOLT_MAX 3300000 -#define TPS65219_LDO34_VOLT_REG_MIN 0x12 -#define TPS65219_LDO34_VOLT_REG_MAX 0x54 +#define TPS65219_LDO34_VOLT_REG_MIN 0x0c +#define TPS65219_LDO34_VOLT_REG_MAX 0x36 #endif /* TPS65219_H */ diff --git a/include/sandbox_host.h b/include/sandbox_host.h index 1330358ef7a..815b32487e7 100644 --- a/include/sandbox_host.h +++ b/include/sandbox_host.h @@ -9,10 +9,12 @@ #define __SANDBOX_HOST__ /** - * Device flags. + * enum host_platform_flags - device flags + * */ enum host_platform_flags { - HOST_FLAG_BROKEN = BIT(0), /** Simulate broken device */ + /** @HOST_FLAG_BROKEN: simulate broken device */ + HOST_FLAG_BROKEN = BIT(0), }; /** diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index c40b448bcba..c9d77ad8ec7 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -58,6 +58,9 @@ struct scmi_agent_priv { #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_80) struct udevice *vendor_dev_80; #endif +#if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_81) + struct udevice *vendor_dev_81; +#endif #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_82) struct udevice *vendor_dev_82; #endif diff --git a/include/scmi_nxp_protocols.h b/include/scmi_nxp_protocols.h index c17f3663eba..184dcc1e04b 100644 --- a/include/scmi_nxp_protocols.h +++ b/include/scmi_nxp_protocols.h @@ -18,6 +18,7 @@ #define SCMI_ARRAY(X, Y) ((SCMI_PAYLOAD_LEN - (X)) / sizeof(Y)) #define SCMI_IMX_MISC_RESET_REASON 0xA +#define SCMI_IMX_MISC_CFG_INFO 0xC struct scmi_imx_misc_reset_reason_in { #define MISC_REASON_FLAG_SYSTEM BIT(0) @@ -119,4 +120,14 @@ static inline int scmi_imx_cpu_start(struct udevice *dev, u32 cpuid, bool start) return -EOPNOTSUPP; } #endif + +struct scmi_imx_misc_cfg_info_out { + s32 status; + /* Mode selector value */ + u32 msel; +#define MISC_MAX_CFGNAME 16 + /* Config (cfg) file basename */ + char cfgname[MISC_MAX_CFGNAME]; +}; + #endif diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index a8fd0a5a729..86165f8ba5e 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -26,6 +26,7 @@ enum scmi_std_protocol { SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17, SCMI_PROTOCOL_ID_PINCTRL = 0x19, SCMI_PROTOCOL_ID_VENDOR_80 = 0x80, + SCMI_PROTOCOL_ID_VENDOR_81 = 0x81, SCMI_PROTOCOL_ID_VENDOR_82 = 0x82, }; @@ -1340,7 +1341,7 @@ struct scmi_pinctrl_release_out { /* SCMI Pinctrl Config Types */ enum scmi_config_type { - SCMI_PIN_DEFUALT = 0, + SCMI_PIN_DEFAULT = 0, SCMI_PIN_BIAS_BUS_HOLD = 1, SCMI_PIN_BIAS_DISABLE = 2, SCMI_PIN_BIAS_HIGH_IMPEDANCE = 3, diff --git a/include/soc/spacemit/k1-reset.h b/include/soc/spacemit/k1-reset.h new file mode 100644 index 00000000000..1dbfd6b1cb0 --- /dev/null +++ b/include/soc/spacemit/k1-reset.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * SpacemiT K1 reset driver — header interface. + * + * Copyright (C) 2026 RISCstar Ltd. + */ + +#ifndef _SOC_SPACEMIT_K1_RESET_H +#define _SOC_SPACEMIT_K1_RESET_H + +struct udevice; + +enum spacemit_k1_reset_syscon { + SPACEMIT_K1_RESET_MPMU, + SPACEMIT_K1_RESET_APMU, + SPACEMIT_K1_RESET_APBC, + SPACEMIT_K1_RESET_APBC2, +}; + +int spacemit_k1_reset_bind(struct udevice *parent, + enum spacemit_k1_reset_syscon syscon); + +#endif /* _SOC_SPACEMIT_K1_RESET_H */ diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h new file mode 100644 index 00000000000..331cc1d35bb --- /dev/null +++ b/include/soc/spacemit/k1-syscon.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* SpacemiT clock and reset driver definitions for the K1 SoC */ + +#ifndef __SOC_K1_SYSCON_H__ +#define __SOC_K1_SYSCON_H__ + +/* APBS register offset */ +#define APBS_PLL1_SWCR1 0x100 +#define APBS_PLL1_SWCR2 0x104 +#define APBS_PLL1_SWCR3 0x108 +#define APBS_PLL2_SWCR1 0x118 +#define APBS_PLL2_SWCR2 0x11c +#define APBS_PLL2_SWCR3 0x120 +#define APBS_PLL3_SWCR1 0x124 +#define APBS_PLL3_SWCR2 0x128 +#define APBS_PLL3_SWCR3 0x12c + +/* MPMU register offset */ +#define MPMU_POSR 0x0010 +#define MPMU_FCCR 0x0008 +#define POSR_PLL1_LOCK BIT(27) +#define POSR_PLL2_LOCK BIT(28) +#define POSR_PLL3_LOCK BIT(29) +#define MPMU_SUCCR 0x0014 +#define MPMU_ISCCR 0x0044 +#define MPMU_WDTPCR 0x0200 +#define MPMU_RIPCCR 0x0210 +#define MPMU_ACGR 0x1024 +#define MPMU_APBCSCR 0x1050 +#define MPMU_SUCCR_1 0x10b0 + +/* APBC register offset */ +#define APBC_UART1_CLK_RST 0x00 +#define APBC_UART2_CLK_RST 0x04 +#define APBC_GPIO_CLK_RST 0x08 +#define APBC_PWM0_CLK_RST 0x0c +#define APBC_PWM1_CLK_RST 0x10 +#define APBC_PWM2_CLK_RST 0x14 +#define APBC_PWM3_CLK_RST 0x18 +#define APBC_TWSI8_CLK_RST 0x20 +#define APBC_UART3_CLK_RST 0x24 +#define APBC_RTC_CLK_RST 0x28 +#define APBC_TWSI0_CLK_RST 0x2c +#define APBC_TWSI1_CLK_RST 0x30 +#define APBC_TIMERS1_CLK_RST 0x34 +#define APBC_TWSI2_CLK_RST 0x38 +#define APBC_AIB_CLK_RST 0x3c +#define APBC_TWSI4_CLK_RST 0x40 +#define APBC_TIMERS2_CLK_RST 0x44 +#define APBC_ONEWIRE_CLK_RST 0x48 +#define APBC_TWSI5_CLK_RST 0x4c +#define APBC_DRO_CLK_RST 0x58 +#define APBC_IR_CLK_RST 0x5c +#define APBC_TWSI6_CLK_RST 0x60 +#define APBC_COUNTER_CLK_SEL 0x64 +#define APBC_TWSI7_CLK_RST 0x68 +#define APBC_TSEN_CLK_RST 0x6c +#define APBC_UART4_CLK_RST 0x70 +#define APBC_UART5_CLK_RST 0x74 +#define APBC_UART6_CLK_RST 0x78 +#define APBC_SSP3_CLK_RST 0x7c +#define APBC_SSPA0_CLK_RST 0x80 +#define APBC_SSPA1_CLK_RST 0x84 +#define APBC_IPC_AP2AUD_CLK_RST 0x90 +#define APBC_UART7_CLK_RST 0x94 +#define APBC_UART8_CLK_RST 0x98 +#define APBC_UART9_CLK_RST 0x9c +#define APBC_CAN0_CLK_RST 0xa0 +#define APBC_PWM4_CLK_RST 0xa8 +#define APBC_PWM5_CLK_RST 0xac +#define APBC_PWM6_CLK_RST 0xb0 +#define APBC_PWM7_CLK_RST 0xb4 +#define APBC_PWM8_CLK_RST 0xb8 +#define APBC_PWM9_CLK_RST 0xbc +#define APBC_PWM10_CLK_RST 0xc0 +#define APBC_PWM11_CLK_RST 0xc4 +#define APBC_PWM12_CLK_RST 0xc8 +#define APBC_PWM13_CLK_RST 0xcc +#define APBC_PWM14_CLK_RST 0xd0 +#define APBC_PWM15_CLK_RST 0xd4 +#define APBC_PWM16_CLK_RST 0xd8 +#define APBC_PWM17_CLK_RST 0xdc +#define APBC_PWM18_CLK_RST 0xe0 +#define APBC_PWM19_CLK_RST 0xe4 + +/* APMU register offset */ +#define APMU_JPG_CLK_RES_CTRL 0x020 +#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 +#define APMU_ISP_CLK_RES_CTRL 0x038 +#define APMU_LCD_CLK_RES_CTRL1 0x044 +#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 +#define APMU_LCD_CLK_RES_CTRL2 0x04c +#define APMU_CCIC_CLK_RES_CTRL 0x050 +#define APMU_SDH0_CLK_RES_CTRL 0x054 +#define APMU_SDH1_CLK_RES_CTRL 0x058 +#define APMU_USB_CLK_RES_CTRL 0x05c +#define APMU_QSPI_CLK_RES_CTRL 0x060 +#define APMU_DMA_CLK_RES_CTRL 0x064 +#define APMU_AES_CLK_RES_CTRL 0x068 +#define APMU_VPU_CLK_RES_CTRL 0x0a4 +#define APMU_GPU_CLK_RES_CTRL 0x0cc +#define APMU_SDH2_CLK_RES_CTRL 0x0e0 +#define APMU_PMUA_MC_CTRL 0x0e8 +#define APMU_PMU_CC2_AP 0x100 +#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 +#define APMU_AUDIO_CLK_RES_CTRL 0x14c +#define APMU_HDMI_CLK_RES_CTRL 0x1b8 +#define APMU_CCI550_CLK_CTRL 0x300 +#define APMU_ACLK_CLK_CTRL 0x388 +#define APMU_CPU_C0_CLK_CTRL 0x38C +#define APMU_CPU_C1_CLK_CTRL 0x390 +#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc +#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 +#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc +#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 +#define APMU_EMAC1_CLK_RES_CTRL 0x3ec + +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c + +#endif /* __SOC_K1_SYSCON_H__ */ diff --git a/include/spi.h b/include/spi.h index 7eaf0aa69b8..97096a77526 100644 --- a/include/spi.h +++ b/include/spi.h @@ -161,6 +161,7 @@ struct spi_slave { unsigned int max_write_size; void *memory_map; + u8 bits_per_word; u8 flags; #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ diff --git a/include/u-boot/hash.h b/include/u-boot/hash.h index f9d47a99a77..7dba66047f5 100644 --- a/include/u-boot/hash.h +++ b/include/u-boot/hash.h @@ -19,6 +19,8 @@ enum HASH_ALGO { HASH_ALGO_INVALID = 0xffffffff, }; +struct udevice; + /* general APIs for hash algo information */ enum HASH_ALGO hash_algo_lookup_by_name(const char *name); ssize_t hash_algo_digest_size(enum HASH_ALGO algo); @@ -31,6 +33,24 @@ int hash_digest(struct udevice *dev, enum HASH_ALGO algo, int hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, const void *ibuf, const uint32_t ilen, void *obuf, uint32_t chunk_sz); +/** + * hash_digest_wd_lookup() - Hash with the first provider supporting an algorithm + * + * Probe each hash device in order and use the first one which supports the + * requested algorithm. Probe failures are remembered while later providers are + * tried. Once a provider accepts an operation, hard failures are returned + * without trying another provider. + * + * @algo: Hash algorithm + * @ibuf: Input buffer + * @ilen: Input buffer length + * @obuf: Output buffer + * @chunk_sz: Watchdog scheduling interval + * Return: 0 on success, -ENODEV if there are no providers, -EOPNOTSUPP if no + * provider supports @algo, or another negative error from a provider + */ +int hash_digest_wd_lookup(enum HASH_ALGO algo, const void *ibuf, + const u32 ilen, void *obuf, u32 chunk_sz); int hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp); int hash_update(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen); int hash_finish(struct udevice *dev, void *ctx, void *obuf); diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 0e545e3db1b..f753a67ac27 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -465,10 +465,6 @@ int zynqmp_mmio_read(const u32 address, u32 *value); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_pm_feature(const u32 api_id); u32 zynqmp_pm_get_bootmode_reg(void); -int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value); -int zynqmp_pm_ufs_sram_csr_read(u32 *value); -int zynqmp_pm_ufs_sram_csr_write(u32 *value); -int zynqmp_pm_ufs_cal_reg(u32 *value); u32 zynqmp_pm_get_pmc_multi_boot_reg(void); u32 zynqmp_pm_get_pmc_global_pggs_reg(u32 reg_addr); @@ -535,7 +531,14 @@ extern smc_call_handler_t __data smc_call_handler; #define PM_DEV_OSPI (0x1822402aU) -#define PM_REG_PGGS3 0x30004003 +#define PM_REGNODE_PMC_IOU_SLCR 0x30000002 +#define PM_REGNODE_EFUSE_CACHE 0x30000003 +#define PM_REG_PGGS3 0x30004003 + +#define SRAM_CSR_OFFSET 0x104C +#define TXRX_CFGRDY_OFFSET 0x1054 +#define UFS_CAL_1_OFFSET 0xBE8 + #define PMC_GLOBAL_PGGS3_REG_NODE 0x1824C005 #endif /* _ZYNQMP_FIRMWARE_H_ */ |