diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/rcar-gen5-common.h | 7 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a78000-clock-scmi.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/reset/r8a78000-reset-scmi.h | 38 |
3 files changed, 24 insertions, 23 deletions
diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 81b5e2aa5bb..5ff2a76fc05 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -10,10 +10,15 @@ /* Console */ #define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 } +#define CFG_HSCIF /* Memory */ -#define DRAM_RSV_SIZE 0x08000000 +#define DRAM_RSV_SIZE 0x20600000 +#ifdef CONFIG_RCAR_64_RSIP +#define CFG_SYS_SDRAM_BASE 0xb8400000 +#else #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#endif #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) diff --git a/include/dt-bindings/clock/r8a78000-clock-scmi.h b/include/dt-bindings/clock/r8a78000-clock-scmi.h index 455402ee8cc..663effddeb4 100644 --- a/include/dt-bindings/clock/r8a78000-clock-scmi.h +++ b/include/dt-bindings/clock/r8a78000-clock-scmi.h @@ -43,4 +43,6 @@ #define SCP_CLOCK_ID_MDLC_MPPHY31 347 #define SCP_CLOCK_ID_MDLC_MPPHY02 348 +#define SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN 1691 + #endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */ diff --git a/include/dt-bindings/reset/r8a78000-reset-scmi.h b/include/dt-bindings/reset/r8a78000-reset-scmi.h index e0d10caa589..3d84bfb073a 100644 --- a/include/dt-bindings/reset/r8a78000-reset-scmi.h +++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h @@ -1,33 +1,27 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (C) 2025 Renesas Electronics Corp. - * - * IDs match SCP 4.27 + * Copyright (C) 2025-2026 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__ #define __DT_BINDINGS_R8A78000_SCMI_RESET_H__ -/* - * These definition indices match the Reset ID defined by SCP FW 4.27. - */ - -#define SCP_RESET_DOMAIN_ID_UFS0 202 -#define SCP_RESET_DOMAIN_ID_UFS1 203 +#define SCP_RESET_DOMAIN_ID_UFS0 0x60 +#define SCP_RESET_DOMAIN_ID_UFS1 0x61 -#define SCP_RESET_DOMAIN_ID_XPCS0 316 -#define SCP_RESET_DOMAIN_ID_XPCS1 317 -#define SCP_RESET_DOMAIN_ID_XPCS2 318 -#define SCP_RESET_DOMAIN_ID_XPCS3 319 -#define SCP_RESET_DOMAIN_ID_XPCS4 320 -#define SCP_RESET_DOMAIN_ID_XPCS5 321 -#define SCP_RESET_DOMAIN_ID_XPCS6 322 -#define SCP_RESET_DOMAIN_ID_XPCS7 323 +#define SCP_RESET_DOMAIN_ID_XPCS0 0x30 +#define SCP_RESET_DOMAIN_ID_XPCS1 0x31 +#define SCP_RESET_DOMAIN_ID_XPCS2 0x32 +#define SCP_RESET_DOMAIN_ID_XPCS3 0x33 +#define SCP_RESET_DOMAIN_ID_XPCS4 0x34 +#define SCP_RESET_DOMAIN_ID_XPCS5 0x35 +#define SCP_RESET_DOMAIN_ID_XPCS6 0x36 +#define SCP_RESET_DOMAIN_ID_XPCS7 0x37 -#define SCP_RESET_DOMAIN_ID_MPPHY01 344 -#define SCP_RESET_DOMAIN_ID_MPPHY11 345 -#define SCP_RESET_DOMAIN_ID_MPPHY21 346 -#define SCP_RESET_DOMAIN_ID_MPPHY31 347 -#define SCP_RESET_DOMAIN_ID_MPPHY02 348 +#define SCP_RESET_DOMAIN_ID_MPPHY01 0x64 +#define SCP_RESET_DOMAIN_ID_MPPHY11 0x65 +#define SCP_RESET_DOMAIN_ID_MPPHY21 0x66 +#define SCP_RESET_DOMAIN_ID_MPPHY31 0x67 +#define SCP_RESET_DOMAIN_ID_MPPHY02 0x68 #endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */ |