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-rw-r--r--include/smbios.h45
-rw-r--r--include/smbios_def.h127
2 files changed, 172 insertions, 0 deletions
diff --git a/include/smbios.h b/include/smbios.h
index 293d6795cf3..2deafea9aa1 100644
--- a/include/smbios.h
+++ b/include/smbios.h
@@ -327,6 +327,51 @@ struct __packed smbios_type16 {
u64 ext_max_cap;
char eos[SMBIOS_STRUCT_EOS_BYTES];
};
+
+struct __packed smbios_type17 {
+ struct smbios_header hdr;
+ u16 phy_mem_array_hdl;
+ u16 mem_err_info_hdl;
+ u16 total_width;
+ u16 data_width;
+ u16 size;
+ u8 form_factor;
+ u8 dev_set;
+ u8 dev_locator;
+ u8 bank_locator;
+ u8 mem_type;
+ u16 type_detail;
+ u16 speed;
+ u8 manufacturer;
+ u8 serial_number;
+ u8 asset_tag;
+ u8 part_number;
+ u8 attributes;
+ u32 ext_size;
+ u16 config_mem_speed;
+ u16 min_voltage;
+ u16 max_voltage;
+ u16 config_voltage;
+ u8 mem_tech;
+ u16 mem_op_mode_cap;
+ u8 fw_ver;
+ u16 module_man_id;
+ u16 module_prod_id;
+ u16 mem_subsys_con_man_id;
+ u16 mem_subsys_con_prod_id;
+ u64 nonvolatile_size;
+ u64 volatile_size;
+ u64 cache_size;
+ u64 logical_size;
+ u32 ext_speed;
+ u32 ext_config_mem_speed;
+ u16 pmic0_man_id;
+ u16 pmic0_rev_num;
+ u16 rcd_man_id;
+ u16 rcd_rev_num;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
struct __packed smbios_type32 {
u8 type;
u8 length;
diff --git a/include/smbios_def.h b/include/smbios_def.h
index c6850a5d6f5..ce913f2f32a 100644
--- a/include/smbios_def.h
+++ b/include/smbios_def.h
@@ -309,4 +309,131 @@
#define SMBIOS_MA_ERRINFO_NONE 0xFFFE
#define SMBIOS_MA_ERRINFO_NOERR 0xFFFF
+/* Memory Device */
+
+/* Size */
+
+#define SMBIOS_MD_SIZE_UNKNOWN 0xFFFF
+#define SMBIOS_MD_SIZE_EXT 0x7FFF
+
+/* Form Factor */
+#define SMBIOS_MD_FF_OTHER 1
+#define SMBIOS_MD_FF_UNKNOWN 2
+#define SMBIOS_MD_FF_SIMM 3
+#define SMBIOS_MD_FF_SIP 4
+#define SMBIOS_MD_FF_CHIP 5
+#define SMBIOS_MD_FF_DIP 6
+#define SMBIOS_MD_FF_ZIP 7
+#define SMBIOS_MD_FF_PROPCARD 8
+#define SMBIOS_MD_FF_DIMM 9
+#define SMBIOS_MD_FF_TSOP 10
+#define SMBIOS_MD_FF_ROC 11
+#define SMBIOS_MD_FF_RIMM 12
+#define SMBIOS_MD_FF_SODIMM 13
+#define SMBIOS_MD_FF_SRIMM 14
+#define SMBIOS_MD_FF_FBDIMM 15
+#define SMBIOS_MD_FF_DIE 16
+
+/* Device set */
+#define SMBIOS_MD_DEVSET_NONE 0
+#define SMBIOS_MD_DEVSET_UNKNOWN 0xFF
+
+/* Speed */
+#define SMBIOS_MD_SPEED_UNKNOWN 0
+#define SMBIOS_MD_SPEED_EXT 0xFFFF
+
+/* Attributes */
+#define SMBIOS_MD_ATTR_RANK_UNKNOWN 0
+
+/* Configured Memory Speed */
+#define SMBIOS_MD_CONFSPEED_UNKNOWN 0
+#define SMBIOS_MD_CONFSPEED_EXT 0xFFFF
+
+/* Voltage */
+#define SMBIOS_MD_VOLTAGE_UNKNOWN 0
+
+/* Type */
+#define SMBIOS_MD_TYPE_OTHER 1
+#define SMBIOS_MD_TYPE_UNKNOWN 2
+#define SMBIOS_MD_TYPE_DRAM 3
+#define SMBIOS_MD_TYPE_EDRAM 4
+#define SMBIOS_MD_TYPE_VRAM 5
+#define SMBIOS_MD_TYPE_SRAM 6
+#define SMBIOS_MD_TYPE_RAM 7
+#define SMBIOS_MD_TYPE_ROM 8
+#define SMBIOS_MD_TYPE_FLASH 9
+#define SMBIOS_MD_TYPE_EEPROM 10
+#define SMBIOS_MD_TYPE_FEPROM 11
+#define SMBIOS_MD_TYPE_EPROM 12
+#define SMBIOS_MD_TYPE_CDRAM 13
+#define SMBIOS_MD_TYPE_3DRAM 14
+#define SMBIOS_MD_TYPE_SDRAM 15
+#define SMBIOS_MD_TYPE_SGRAM 16
+#define SMBIOS_MD_TYPE_RDRAM 17
+#define SMBIOS_MD_TYPE_DDR 18
+#define SMBIOS_MD_TYPE_DDR2 19
+#define SMBIOS_MD_TYPE_DDR2FBD 20
+#define SMBIOS_MD_TYPE_RSVD1 21
+#define SMBIOS_MD_TYPE_RSVD2 22
+#define SMBIOS_MD_TYPE_DSVD3 23
+#define SMBIOS_MD_TYPE_DDR3 24
+#define SMBIOS_MD_TYPE_FBD2 25
+#define SMBIOS_MD_TYPE_DDR4 26
+#define SMBIOS_MD_TYPE_LPDDR 27
+#define SMBIOS_MD_TYPE_LPDDR2 28
+#define SMBIOS_MD_TYPE_LPDDR3 29
+#define SMBIOS_MD_TYPE_LPDDR4 30
+#define SMBIOS_MD_TYPE_LNVD 31
+#define SMBIOS_MD_TYPE_HBM 32
+#define SMBIOS_MD_TYPE_HBM2 33
+#define SMBIOS_MD_TYPE_DDR5 34
+#define SMBIOS_MD_TYPE_LPDDR5 35
+#define SMBIOS_MD_TYPE_HBM3 36
+
+/* Type Detail */
+#define SMBIOS_MD_TD_RSVD 1 /* BIT(0), set to 0 */
+#define SMBIOS_MD_TD_OTHER 2 /* BIT(1) */
+#define SMBIOS_MD_TD_UNKNOWN 4 /* BIT(2) */
+#define SMBIOS_MD_TD_FP 8 /* BIT(3) */
+#define SMBIOS_MD_TD_SC 0x10 /* BIT(4) */
+#define SMBIOS_MD_TD_PS 0x20 /* BIT(5) */
+#define SMBIOS_MD_TD_RAMBUS 0x40 /* BIT(6) */
+#define SMBIOS_MD_TD_SYNC 0x80 /* BIT(7) */
+#define SMBIOS_MD_TD_CMOS 0x100 /* BIT(8) */
+#define SMBIOS_MD_TD_EDO 0x200 /* BIT(9) */
+#define SMBIOS_MD_TD_WINDRAM 0x400 /* BIT(10) */
+#define SMBIOS_MD_TD_CACHEDRAM 0x800 /* BIT(11) */
+#define SMBIOS_MD_TD_NV 0x1000 /* BIT(12) */
+#define SMBIOS_MD_TD_RGSTD 0x2000 /* BIT(13) */
+#define SMBIOS_MD_TD_UNRGSTD 0x4000 /* BIT(14) */
+#define SMBIOS_MD_TD_LRDIMM 0x8000 /* BIT(15) */
+
+/* Technology */
+#define SMBIOS_MD_TECH_OTHER 1
+#define SMBIOS_MD_TECH_UNKNOWN 2
+#define SMBIOS_MD_TECH_DRAM 3
+#define SMBIOS_MD_TECH_NVDIMMN 4
+#define SMBIOS_MD_TECH_NVDIMMF 5
+#define SMBIOS_MD_TECH_NVDIMMP 6
+#define SMBIOS_MD_TECH_OPTANE 7
+
+/* Operating Mode Capability */
+#define SMBIOS_MD_OPMC_RSVD 1 /* BIT(0), set to 0 */
+#define SMBIOS_MD_OPMC_OTHER 2 /* BIT(1) */
+#define SMBIOS_MD_OPMC_UNKNOWN 4 /* BIT(2) */
+#define SMBIOS_MD_OPMC_VM 8 /* BIT(3) */
+#define SMBIOS_MD_OPMC_BYTEAPM 0x10 /* BIT(4) */
+#define SMBIOS_MD_OPMC_BLKAPM 0x20 /* BIT(5) */
+/* Bit 6:15 Reserved, set to 0 */
+
+/* Non-volatile / Volatile / Cache / Logical portion Size */
+#define SMBIOS_MD_PORT_SIZE_NONE 0
+#define SMBIOS_MD_PORT_SIZE_UNKNOWN_HI 0xFFFFFFFF
+#define SMBIOS_MD_PORT_SIZE_UNKNOWN_LO 0xFFFFFFFF
+#define SMBIOS_MS_PORT_SIZE_UNKNOWN 0xFFFFFFFFFFFFFFFF
+
+/* Error Information Handle */
+#define SMBIOS_MD_ERRINFO_NONE 0xFFFE
+#define SMBIOS_MD_ERRINFO_NOERR 0xFFFF
+
#endif /* _SMBIOS_DEF_H_ */