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-rw-r--r--include/bootdev.h8
-rw-r--r--include/configs/rcar-gen5-common.h42
-rw-r--r--include/dt-bindings/clock/rk3128-cru.h273
-rw-r--r--include/dt-bindings/clock/rk3228-cru.h287
-rw-r--r--include/r8a779g0-dbsc5.h (renamed from include/dbsc5.h)0
-rw-r--r--include/r8a78000-dbsc5.h63
6 files changed, 108 insertions, 565 deletions
diff --git a/include/bootdev.h b/include/bootdev.h
index 12c90c4ec1b..14f8a98633b 100644
--- a/include/bootdev.h
+++ b/include/bootdev.h
@@ -30,10 +30,10 @@ struct udevice;
* generally very quick to access, e.g. less than 100ms
* @BOOTDEVP_3_INTERNAL_SLOW: Internal devices which don't need scanning but
* take a significant fraction of a second to access
- * @BOOTDEVP_4_SCAN_FAST: Extenal devices which need scanning or bus
+ * @BOOTDEVP_4_SCAN_FAST: External devices which need scanning or bus
* enumeration to find, but this enumeration happens quickly, typically under
* 100ms
- * @BOOTDEVP_5_SCAN_SLOW: Extenal devices which need scanning or bus
+ * @BOOTDEVP_5_SCAN_SLOW: External devices which need scanning or bus
* enumeration to find. The enumeration takes significant fraction of a second
* to complete
* @BOOTDEVP_6_NET_BASE: Basic network devices which are quickly and easily
@@ -327,7 +327,7 @@ int bootdev_hunt_and_find_by_label(const char *label, struct udevice **devp,
* Bootdev scanners are used as needed. For example a label "mmc1" results in
* running the "mmc" bootdrv.
*
- * @iter: Interation info, containing iter->cur_label
+ * @iter: Iteration info, containing iter->cur_label
* @devp: New bootdev found, if any was found
* @method_flagsp: If non-NULL, returns any flags implied by the label
* (enum bootflow_meth_flags_t), 0 if none
@@ -342,7 +342,7 @@ int bootdev_next_label(struct bootflow_iter *iter, struct udevice **devp,
* This moves @devp to the next bootdev with the current priority. If there is
* none, then it moves to the next priority and scans for new bootdevs there.
*
- * @iter: Interation info, containing iter->cur_prio
+ * @iter: Iteration info, containing iter->cur_prio
* @devp: On entry this is the previous bootdev that was considered. On exit
* this is the new bootdev, if any was found
* Returns 0 on success (*devp is updated), -ENODEV if there are no more
diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h
index 5ff2a76fc05..a0c05521c85 100644
--- a/include/configs/rcar-gen5-common.h
+++ b/include/configs/rcar-gen5-common.h
@@ -26,10 +26,50 @@
#if defined(CONFIG_RCAR_64_RSIP)
#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
#define CFG_SYS_TIMER_RATE (133333333 / 4)
-#endif
/* Environment setting */
+#define CFG_EXTRA_ENV_SETTINGS \
+ "rsip_ipl_params_base=0x8c100000\0" \
+ "rsip_ipl_params_optee=0x8c100088\0" \
+ "rsip_ipl_params_uboot=0x8c100030\0" \
+ "rsip_ipl_optee_ep=0x8c400000\0" \
+ "rsip_ipl_tfa_ep=0x8c200000\0" \
+ "rsip_ipl_uboot_ep=0x8e300000\0" \
+ "rsip_ipl_params_write=" \
+ "base ${rsip_ipl_params_base} ; " \
+ "mw 0x00 0 0x9e ; " /* Clear the area */ \
+ "mw 0x00 0x00300103 ; " /* type, version, size */ \
+ "mw 0x20 0x${rsip_ipl_params_uboot} ; " /* U-Boot descriptor */ \
+ "" \
+ "base ${rsip_ipl_params_uboot} ; " \
+ "mw 0x00 0x00580101 ; " /* type, version, size */ \
+ "mw 0x04 0x00000001 ; " /* attr */ \
+ "mw 0x08 ${rsip_ipl_uboot_ep} ; " /* U-Boot entry point */ \
+ "mw 0x10 0x000003c5 ; " /* SPSR */ \
+ "" \
+ "base ${rsip_ipl_params_optee} ; " \
+ "mw 0x00 0x00580201 ; " /* type, version, size */ \
+ "mw 0x04 0x00000008 ; " /* attr */ \
+ "mw 0x08 ${rsip_ipl_optee_ep} ; " /* OPTEE-OS entry point */ \
+ "mw 0x10 0x000003c5 ; " /* SPSR */ \
+ "" \
+ "base 0\0" \
+ "rsip_ipl_boot_ca0=" /* Start TFA BL31, OPTEE-OS, U-Boot on Cortex-A720AE core 0 */ \
+ "scsi scan && " /* Scan for UFS devices */ \
+ "rproc init && " /* Start remoteproc */ \
+ "rproc load 0 0x344c0000 0x60000 && " /* Load SCP from HF */ \
+ "rproc start 0 && " /* Start SCP */ \
+ "scsi read ${rsip_ipl_uboot_ep} 0x7200 0x100 && " /* Load U-Boot from UFS */ \
+ "scsi read ${rsip_ipl_optee_ep} 0x5200 0x200 && " /* Load OPTEE-OS from UFS */ \
+ "scsi read ${rsip_ipl_tfa_ep} 0x5000 0x40 && " /* Load TFA BL31 from UFS */ \
+ "run rsip_ipl_params_write && " /* Write entry point descriptors */ \
+ "rproc load 13 ${rsip_ipl_tfa_ep} 4 && " /* Set up Cortex-A720AE Core 0 */ \
+ "rproc start 13\0" /* Start Cortex-A720AE Core 0 */
+
+#else
+/* Environment setting */
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
+#endif
#endif /* __RCAR_GEN5_COMMON_H */
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
deleted file mode 100644
index 6a47825dac5..00000000000
--- a/include/dt-bindings/clock/rk3128-cru.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
- * Author: Elaine <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_GPLL 4
-#define ARMCLK 5
-#define PLL_GPLL_DIV2 6
-#define PLL_GPLL_DIV3 7
-
-/* sclk gates (special clocks) */
-#define SCLK_SPI0 65
-#define SCLK_NANDC 67
-#define SCLK_SDMMC 68
-#define SCLK_SDIO 69
-#define SCLK_EMMC 71
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_I2S0 80
-#define SCLK_I2S1 81
-#define SCLK_SPDIF 83
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_TIMER4 89
-#define SCLK_TIMER5 90
-#define SCLK_SARADC 91
-#define SCLK_I2S_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO_DRV 115
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO_SAMPLE 119
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_VOP 122
-#define SCLK_MAC_SRC 124
-#define SCLK_MAC 126
-#define SCLK_MAC_REFOUT 127
-#define SCLK_MAC_REF 128
-#define SCLK_MAC_RX 129
-#define SCLK_MAC_TX 130
-#define SCLK_HEVC_CORE 134
-#define SCLK_RGA 135
-#define SCLK_CRYPTO 138
-#define SCLK_TSP 139
-#define SCLK_OTGPHY0 142
-#define SCLK_OTGPHY1 143
-#define SCLK_DDRC 144
-#define SCLK_PVTM_FUNC 145
-#define SCLK_PVTM_CORE 146
-#define SCLK_PVTM_GPU 147
-#define SCLK_MIPI_24M 148
-#define SCLK_PVTM 149
-#define SCLK_CIF_SRC 150
-#define SCLK_CIF_OUT_SRC 151
-#define SCLK_CIF_OUT 152
-#define SCLK_SFC 153
-#define SCLK_USB480M 154
-
-/* dclk gates */
-#define DCLK_VOP 190
-#define DCLK_EBC 191
-
-/* aclk gates */
-#define ACLK_VIO0 192
-#define ACLK_VIO1 193
-#define ACLK_DMAC 194
-#define ACLK_CPU 195
-#define ACLK_VEPU 196
-#define ACLK_VDPU 197
-#define ACLK_CIF 198
-#define ACLK_IEP 199
-#define ACLK_LCDC0 204
-#define ACLK_RGA 205
-#define ACLK_PERI 210
-#define ACLK_VOP 211
-#define ACLK_GMAC 212
-#define ACLK_GPU 213
-
-/* pclk gates */
-#define PCLK_SARADC 318
-#define PCLK_WDT 319
-#define PCLK_GPIO0 320
-#define PCLK_GPIO1 321
-#define PCLK_GPIO2 322
-#define PCLK_GPIO3 323
-#define PCLK_VIO_H2P 324
-#define PCLK_MIPI 325
-#define PCLK_EFUSE 326
-#define PCLK_HDMI 327
-#define PCLK_ACODEC 328
-#define PCLK_GRF 329
-#define PCLK_I2C0 332
-#define PCLK_I2C1 333
-#define PCLK_I2C2 334
-#define PCLK_I2C3 335
-#define PCLK_SPI0 338
-#define PCLK_UART0 341
-#define PCLK_UART1 342
-#define PCLK_UART2 343
-#define PCLK_TSADC 344
-#define PCLK_PWM 350
-#define PCLK_TIMER 353
-#define PCLK_CPU 354
-#define PCLK_PERI 363
-#define PCLK_GMAC 367
-#define PCLK_PMU_PRE 368
-#define PCLK_SIM_CARD 369
-
-/* hclk gates */
-#define HCLK_SPDIF 440
-#define HCLK_GPS 441
-#define HCLK_USBHOST 442
-#define HCLK_I2S_8CH 443
-#define HCLK_I2S_2CH 444
-#define HCLK_VOP 452
-#define HCLK_NANDC 453
-#define HCLK_SDMMC 456
-#define HCLK_SDIO 457
-#define HCLK_EMMC 459
-#define HCLK_CPU 460
-#define HCLK_VEPU 461
-#define HCLK_VDPU 462
-#define HCLK_LCDC0 463
-#define HCLK_EBC 465
-#define HCLK_VIO 466
-#define HCLK_RGA 467
-#define HCLK_IEP 468
-#define HCLK_VIO_H2P 469
-#define HCLK_CIF 470
-#define HCLK_HOST2 473
-#define HCLK_OTG 474
-#define HCLK_TSP 475
-#define HCLK_CRYPTO 476
-#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0_PO 0
-#define SRST_CORE1_PO 1
-#define SRST_CORE2_PO 2
-#define SRST_CORE3_PO 3
-#define SRST_CORE0 4
-#define SRST_CORE1 5
-#define SRST_CORE2 6
-#define SRST_CORE3 7
-#define SRST_CORE0_DBG 8
-#define SRST_CORE1_DBG 9
-#define SRST_CORE2_DBG 10
-#define SRST_CORE3_DBG 11
-#define SRST_TOPDBG 12
-#define SRST_ACLK_CORE 13
-#define SRST_STRC_SYS_A 14
-#define SRST_L2C 15
-
-#define SRST_CPUSYS_H 18
-#define SRST_AHB2APBSYS_H 19
-#define SRST_SPDIF 20
-#define SRST_INTMEM 21
-#define SRST_ROM 22
-#define SRST_PERI_NIU 23
-#define SRST_I2S_2CH 24
-#define SRST_I2S_8CH 25
-#define SRST_GPU_PVTM 26
-#define SRST_FUNC_PVTM 27
-#define SRST_CORE_PVTM 29
-#define SRST_EFUSE_P 30
-#define SRST_ACODEC_P 31
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_GPIO3 35
-#define SRST_MIPIPHY_P 36
-#define SRST_UART0 39
-#define SRST_UART1 40
-#define SRST_UART2 41
-#define SRST_I2C0 43
-#define SRST_I2C1 44
-#define SRST_I2C2 45
-#define SRST_I2C3 46
-#define SRST_SFC 47
-
-#define SRST_PWM 48
-#define SRST_DAP_PO 50
-#define SRST_DAP 51
-#define SRST_DAP_SYS 52
-#define SRST_CRYPTO 53
-#define SRST_GRF 55
-#define SRST_GMAC 56
-#define SRST_PERIPH_SYS_A 57
-#define SRST_PERIPH_SYS_H 58
-#define SRST_PERIPH_SYS_P 59
-#define SRST_SMART_CARD 60
-#define SRST_CPU_PERI 61
-#define SRST_EMEM_PERI 62
-#define SRST_USB_PERI 63
-
-#define SRST_DMA 64
-#define SRST_GPS 67
-#define SRST_NANDC 68
-#define SRST_USBOTG0 69
-#define SRST_OTGC0 71
-#define SRST_USBOTG1 72
-#define SRST_OTGC1 74
-#define SRST_DDRMSCH 79
-
-#define SRST_SDMMC 81
-#define SRST_SDIO 82
-#define SRST_EMMC 83
-#define SRST_SPI 84
-#define SRST_WDT 86
-#define SRST_SARADC 87
-#define SRST_DDRPHY 88
-#define SRST_DDRPHY_P 89
-#define SRST_DDRCTRL 90
-#define SRST_DDRCTRL_P 91
-#define SRST_TSP 92
-#define SRST_TSP_CLKIN 93
-#define SRST_HOST0_ECHI 94
-
-#define SRST_HDMI_P 96
-#define SRST_VIO_ARBI_H 97
-#define SRST_VIO0_A 98
-#define SRST_VIO_BUS_H 99
-#define SRST_VOP_A 100
-#define SRST_VOP_H 101
-#define SRST_VOP_D 102
-#define SRST_UTMI0 103
-#define SRST_UTMI1 104
-#define SRST_USBPOR 105
-#define SRST_IEP_A 106
-#define SRST_IEP_H 107
-#define SRST_RGA_A 108
-#define SRST_RGA_H 109
-#define SRST_CIF0 110
-#define SRST_PMU 111
-
-#define SRST_VCODEC_A 112
-#define SRST_VCODEC_H 113
-#define SRST_VIO1_A 114
-#define SRST_HEVC_CORE 115
-#define SRST_VCODEC_NIU_A 116
-#define SRST_PMU_NIU_P 117
-#define SRST_LCDC0_S 119
-#define SRST_GPU 120
-#define SRST_GPU_NIU_A 122
-#define SRST_EBC_A 123
-#define SRST_EBC_H 124
-
-#define SRST_CORE_DBG 128
-#define SRST_DBG_P 129
-#define SRST_TIMER0 130
-#define SRST_TIMER1 131
-#define SRST_TIMER2 132
-#define SRST_TIMER3 133
-#define SRST_TIMER4 134
-#define SRST_TIMER5 135
-#define SRST_VIO_H2P 136
-#define SRST_VIO_MIPI_DSI 137
-
-#endif
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
deleted file mode 100644
index de550ea56ee..00000000000
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ /dev/null
@@ -1,287 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
- * Author: Jeffy Chen <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
-#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
-
-/* core clocks */
-#define PLL_APLL 1
-#define PLL_DPLL 2
-#define PLL_CPLL 3
-#define PLL_GPLL 4
-#define ARMCLK 5
-
-/* sclk gates (special clocks) */
-#define SCLK_SPI0 65
-#define SCLK_NANDC 67
-#define SCLK_SDMMC 68
-#define SCLK_SDIO 69
-#define SCLK_EMMC 71
-#define SCLK_TSADC 72
-#define SCLK_UART0 77
-#define SCLK_UART1 78
-#define SCLK_UART2 79
-#define SCLK_I2S0 80
-#define SCLK_I2S1 81
-#define SCLK_I2S2 82
-#define SCLK_SPDIF 83
-#define SCLK_TIMER0 85
-#define SCLK_TIMER1 86
-#define SCLK_TIMER2 87
-#define SCLK_TIMER3 88
-#define SCLK_TIMER4 89
-#define SCLK_TIMER5 90
-#define SCLK_I2S_OUT 113
-#define SCLK_SDMMC_DRV 114
-#define SCLK_SDIO_DRV 115
-#define SCLK_EMMC_DRV 117
-#define SCLK_SDMMC_SAMPLE 118
-#define SCLK_SDIO_SAMPLE 119
-#define SCLK_SDIO_SRC 120
-#define SCLK_EMMC_SAMPLE 121
-#define SCLK_VOP 122
-#define SCLK_HDMI_HDCP 123
-#define SCLK_MAC_SRC 124
-#define SCLK_MAC_EXTCLK 125
-#define SCLK_MAC 126
-#define SCLK_MAC_REFOUT 127
-#define SCLK_MAC_REF 128
-#define SCLK_MAC_RX 129
-#define SCLK_MAC_TX 130
-#define SCLK_MAC_PHY 131
-#define SCLK_MAC_OUT 132
-#define SCLK_VDEC_CABAC 133
-#define SCLK_VDEC_CORE 134
-#define SCLK_RGA 135
-#define SCLK_HDCP 136
-#define SCLK_HDMI_CEC 137
-#define SCLK_CRYPTO 138
-#define SCLK_TSP 139
-#define SCLK_HSADC 140
-#define SCLK_WIFI 141
-#define SCLK_OTGPHY0 142
-#define SCLK_OTGPHY1 143
-#define SCLK_HDMI_PHY 144
-
-/* dclk gates */
-#define DCLK_VOP 190
-#define DCLK_HDMI_PHY 191
-
-/* aclk gates */
-#define ACLK_DMAC 194
-#define ACLK_CPU 195
-#define ACLK_VPU_PRE 196
-#define ACLK_RKVDEC_PRE 197
-#define ACLK_RGA_PRE 198
-#define ACLK_IEP_PRE 199
-#define ACLK_HDCP_PRE 200
-#define ACLK_VOP_PRE 201
-#define ACLK_VPU 202
-#define ACLK_RKVDEC 203
-#define ACLK_IEP 204
-#define ACLK_RGA 205
-#define ACLK_HDCP 206
-#define ACLK_PERI 210
-#define ACLK_VOP 211
-#define ACLK_GMAC 212
-#define ACLK_GPU 213
-
-/* pclk gates */
-#define PCLK_GPIO0 320
-#define PCLK_GPIO1 321
-#define PCLK_GPIO2 322
-#define PCLK_GPIO3 323
-#define PCLK_VIO_H2P 324
-#define PCLK_HDCP 325
-#define PCLK_EFUSE_1024 326
-#define PCLK_EFUSE_256 327
-#define PCLK_GRF 329
-#define PCLK_I2C0 332
-#define PCLK_I2C1 333
-#define PCLK_I2C2 334
-#define PCLK_I2C3 335
-#define PCLK_SPI0 338
-#define PCLK_UART0 341
-#define PCLK_UART1 342
-#define PCLK_UART2 343
-#define PCLK_TSADC 344
-#define PCLK_PWM 350
-#define PCLK_TIMER 353
-#define PCLK_CPU 354
-#define PCLK_PERI 363
-#define PCLK_HDMI_CTRL 364
-#define PCLK_HDMI_PHY 365
-#define PCLK_GMAC 367
-
-/* hclk gates */
-#define HCLK_I2S0_8CH 442
-#define HCLK_I2S1_8CH 443
-#define HCLK_I2S2_2CH 444
-#define HCLK_SPDIF_8CH 445
-#define HCLK_VOP 452
-#define HCLK_NANDC 453
-#define HCLK_SDMMC 456
-#define HCLK_SDIO 457
-#define HCLK_EMMC 459
-#define HCLK_CPU 460
-#define HCLK_VPU_PRE 461
-#define HCLK_RKVDEC_PRE 462
-#define HCLK_VIO_PRE 463
-#define HCLK_VPU 464
-#define HCLK_RKVDEC 465
-#define HCLK_VIO 466
-#define HCLK_RGA 467
-#define HCLK_IEP 468
-#define HCLK_VIO_H2P 469
-#define HCLK_HDCP_MMU 470
-#define HCLK_HOST0 471
-#define HCLK_HOST1 472
-#define HCLK_HOST2 473
-#define HCLK_OTG 474
-#define HCLK_TSP 475
-#define HCLK_M_CRYPTO 476
-#define HCLK_S_CRYPTO 477
-#define HCLK_PERI 478
-
-#define CLK_NR_CLKS (HCLK_PERI + 1)
-
-/* soft-reset indices */
-#define SRST_CORE0_PO 0
-#define SRST_CORE1_PO 1
-#define SRST_CORE2_PO 2
-#define SRST_CORE3_PO 3
-#define SRST_CORE0 4
-#define SRST_CORE1 5
-#define SRST_CORE2 6
-#define SRST_CORE3 7
-#define SRST_CORE0_DBG 8
-#define SRST_CORE1_DBG 9
-#define SRST_CORE2_DBG 10
-#define SRST_CORE3_DBG 11
-#define SRST_TOPDBG 12
-#define SRST_ACLK_CORE 13
-#define SRST_NOC 14
-#define SRST_L2C 15
-
-#define SRST_CPUSYS_H 18
-#define SRST_BUSSYS_H 19
-#define SRST_SPDIF 20
-#define SRST_INTMEM 21
-#define SRST_ROM 22
-#define SRST_OTG_ADP 23
-#define SRST_I2S0 24
-#define SRST_I2S1 25
-#define SRST_I2S2 26
-#define SRST_ACODEC_P 27
-#define SRST_DFIMON 28
-#define SRST_MSCH 29
-#define SRST_EFUSE1024 30
-#define SRST_EFUSE256 31
-
-#define SRST_GPIO0 32
-#define SRST_GPIO1 33
-#define SRST_GPIO2 34
-#define SRST_GPIO3 35
-#define SRST_PERIPH_NOC_A 36
-#define SRST_PERIPH_NOC_BUS_H 37
-#define SRST_PERIPH_NOC_P 38
-#define SRST_UART0 39
-#define SRST_UART1 40
-#define SRST_UART2 41
-#define SRST_PHYNOC 42
-#define SRST_I2C0 43
-#define SRST_I2C1 44
-#define SRST_I2C2 45
-#define SRST_I2C3 46
-
-#define SRST_PWM 48
-#define SRST_A53_GIC 49
-#define SRST_DAP 51
-#define SRST_DAP_NOC 52
-#define SRST_CRYPTO 53
-#define SRST_SGRF 54
-#define SRST_GRF 55
-#define SRST_GMAC 56
-#define SRST_PERIPH_NOC_H 58
-#define SRST_MACPHY 63
-
-#define SRST_DMA 64
-#define SRST_NANDC 68
-#define SRST_USBOTG 69
-#define SRST_OTGC 70
-#define SRST_USBHOST0 71
-#define SRST_HOST_CTRL0 72
-#define SRST_USBHOST1 73
-#define SRST_HOST_CTRL1 74
-#define SRST_USBHOST2 75
-#define SRST_HOST_CTRL2 76
-#define SRST_USBPOR0 77
-#define SRST_USBPOR1 78
-#define SRST_DDRMSCH 79
-
-#define SRST_SMART_CARD 80
-#define SRST_SDMMC 81
-#define SRST_SDIO 82
-#define SRST_EMMC 83
-#define SRST_SPI 84
-#define SRST_TSP_H 85
-#define SRST_TSP 86
-#define SRST_TSADC 87
-#define SRST_DDRPHY 88
-#define SRST_DDRPHY_P 89
-#define SRST_DDRCTRL 90
-#define SRST_DDRCTRL_P 91
-#define SRST_HOST0_ECHI 92
-#define SRST_HOST1_ECHI 93
-#define SRST_HOST2_ECHI 94
-#define SRST_VOP_NOC_A 95
-
-#define SRST_HDMI_P 96
-#define SRST_VIO_ARBI_H 97
-#define SRST_IEP_NOC_A 98
-#define SRST_VIO_NOC_H 99
-#define SRST_VOP_A 100
-#define SRST_VOP_H 101
-#define SRST_VOP_D 102
-#define SRST_UTMI0 103
-#define SRST_UTMI1 104
-#define SRST_UTMI2 105
-#define SRST_UTMI3 106
-#define SRST_RGA 107
-#define SRST_RGA_NOC_A 108
-#define SRST_RGA_A 109
-#define SRST_RGA_H 110
-#define SRST_HDCP_A 111
-
-#define SRST_VPU_A 112
-#define SRST_VPU_H 113
-#define SRST_VPU_NOC_A 116
-#define SRST_VPU_NOC_H 117
-#define SRST_RKVDEC_A 118
-#define SRST_RKVDEC_NOC_A 119
-#define SRST_RKVDEC_H 120
-#define SRST_RKVDEC_NOC_H 121
-#define SRST_RKVDEC_CORE 122
-#define SRST_RKVDEC_CABAC 123
-#define SRST_IEP_A 124
-#define SRST_IEP_H 125
-#define SRST_GPU_A 126
-#define SRST_GPU_NOC_A 127
-
-#define SRST_CORE_DBG 128
-#define SRST_DBG_P 129
-#define SRST_TIMER0 130
-#define SRST_TIMER1 131
-#define SRST_TIMER2 132
-#define SRST_TIMER3 133
-#define SRST_TIMER4 134
-#define SRST_TIMER5 135
-#define SRST_VIO_H2P 136
-#define SRST_HDMIPHY 139
-#define SRST_VDAC 140
-#define SRST_TIMER_6CH_P 141
-
-#endif
diff --git a/include/dbsc5.h b/include/r8a779g0-dbsc5.h
index b9b8703141a..b9b8703141a 100644
--- a/include/dbsc5.h
+++ b/include/r8a779g0-dbsc5.h
diff --git a/include/r8a78000-dbsc5.h b/include/r8a78000-dbsc5.h
new file mode 100644
index 00000000000..7954f5b0761
--- /dev/null
+++ b/include/r8a78000-dbsc5.h
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ *
+ * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
+ */
+
+#ifndef __INCLUDE_DBSC5_H__
+#define __INCLUDE_DBSC5_H__
+
+/* The number of channels X5H has */
+#define DRAM_CH_CNT 16
+/* The number of slices X5H has */
+#define SLICE_CNT 2
+/* The number of chip select X5H has */
+#define CS_CNT 2
+
+struct renesas_dbsc5_board_config {
+ u32 bdcfg_phyvalid;
+ u32 bdcfg_tx_drv;
+ u32 bdcfg_tx_ffc;
+ u32 bdcfg_rx_odt;
+ u8 bdcfg_rx_dfe;
+ u8 bdcfg_tx_odt;
+ u8 bdcfg_tx_ntodt;
+ u8 bdcfg_tx_dfe;
+ u8 bdcfg_rx_dca;
+ u8 bdcfg_rx_drv;
+ u32 bdcfg_rx_emphasis;
+ u8 bdcfg_tx_dca;
+ u8 bdcfg_ca_vref;
+ u32 bdcfg_rx_vref;
+ u32 bdcfg_rx_vref_step;
+ u32 bdcfg_tx_vref;
+ u8 bdcfg_rfm_chk;
+
+ /* Board parameter about channels */
+ struct {
+ /*
+ * 0x00: 4Gb dual channel die / 2Gb single channel die
+ * 0x01: 6Gb dual channel die / 3Gb single channel die
+ * 0x02: 8Gb dual channel die / 4Gb single channel die
+ * 0x03: 12Gb dual channel die / 6Gb single channel die
+ * 0x04: 16Gb dual channel die / 8Gb single channel die
+ * 0x05: 24Gb dual channel die / 12Gb single channel die
+ * 0x06: 32Gb dual channel die / 16Gb single channel die
+ * 0x07: 24Gb single channel die
+ * 0x08: 32Gb single channel die
+ * 0xFF: NO_MEMORY
+ */
+ u8 bdcfg_ddr_density[CS_CNT];
+ /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
+ u32 bdcfg_ca_swap;
+ /* SoC dqsX([1][0]) -> MEM dqsY: */
+ u8 bdcfg_dqs_swap;
+ /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
+ u32 bdcfg_dq_swap[SLICE_CNT];
+ /* SoC dm -> MEM dqY/dm: (8 means DM) */
+ u8 bdcfg_dm_swap[SLICE_CNT];
+ } ch[DRAM_CH_CNT];
+};
+
+#endif /* __INCLUDE_DBSC5_H__ */
generated by cgit v1.3.1 (git 2.54.0) at 2026-07-11 19:35:20 +0000