diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/rcar-gen5-common.h | 42 | ||||
| -rw-r--r-- | include/r8a779g0-dbsc5.h (renamed from include/dbsc5.h) | 0 | ||||
| -rw-r--r-- | include/r8a78000-dbsc5.h | 63 |
3 files changed, 104 insertions, 1 deletions
diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 5ff2a76fc05..a0c05521c85 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -26,10 +26,50 @@ #if defined(CONFIG_RCAR_64_RSIP) #define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (133333333 / 4) -#endif /* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ + "rsip_ipl_params_base=0x8c100000\0" \ + "rsip_ipl_params_optee=0x8c100088\0" \ + "rsip_ipl_params_uboot=0x8c100030\0" \ + "rsip_ipl_optee_ep=0x8c400000\0" \ + "rsip_ipl_tfa_ep=0x8c200000\0" \ + "rsip_ipl_uboot_ep=0x8e300000\0" \ + "rsip_ipl_params_write=" \ + "base ${rsip_ipl_params_base} ; " \ + "mw 0x00 0 0x9e ; " /* Clear the area */ \ + "mw 0x00 0x00300103 ; " /* type, version, size */ \ + "mw 0x20 0x${rsip_ipl_params_uboot} ; " /* U-Boot descriptor */ \ + "" \ + "base ${rsip_ipl_params_uboot} ; " \ + "mw 0x00 0x00580101 ; " /* type, version, size */ \ + "mw 0x04 0x00000001 ; " /* attr */ \ + "mw 0x08 ${rsip_ipl_uboot_ep} ; " /* U-Boot entry point */ \ + "mw 0x10 0x000003c5 ; " /* SPSR */ \ + "" \ + "base ${rsip_ipl_params_optee} ; " \ + "mw 0x00 0x00580201 ; " /* type, version, size */ \ + "mw 0x04 0x00000008 ; " /* attr */ \ + "mw 0x08 ${rsip_ipl_optee_ep} ; " /* OPTEE-OS entry point */ \ + "mw 0x10 0x000003c5 ; " /* SPSR */ \ + "" \ + "base 0\0" \ + "rsip_ipl_boot_ca0=" /* Start TFA BL31, OPTEE-OS, U-Boot on Cortex-A720AE core 0 */ \ + "scsi scan && " /* Scan for UFS devices */ \ + "rproc init && " /* Start remoteproc */ \ + "rproc load 0 0x344c0000 0x60000 && " /* Load SCP from HF */ \ + "rproc start 0 && " /* Start SCP */ \ + "scsi read ${rsip_ipl_uboot_ep} 0x7200 0x100 && " /* Load U-Boot from UFS */ \ + "scsi read ${rsip_ipl_optee_ep} 0x5200 0x200 && " /* Load OPTEE-OS from UFS */ \ + "scsi read ${rsip_ipl_tfa_ep} 0x5000 0x40 && " /* Load TFA BL31 from UFS */ \ + "run rsip_ipl_params_write && " /* Write entry point descriptors */ \ + "rproc load 13 ${rsip_ipl_tfa_ep} 4 && " /* Set up Cortex-A720AE Core 0 */ \ + "rproc start 13\0" /* Start Cortex-A720AE Core 0 */ + +#else +/* Environment setting */ #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" +#endif #endif /* __RCAR_GEN5_COMMON_H */ diff --git a/include/dbsc5.h b/include/r8a779g0-dbsc5.h index b9b8703141a..b9b8703141a 100644 --- a/include/dbsc5.h +++ b/include/r8a779g0-dbsc5.h diff --git a/include/r8a78000-dbsc5.h b/include/r8a78000-dbsc5.h new file mode 100644 index 00000000000..7954f5b0761 --- /dev/null +++ b/include/r8a78000-dbsc5.h @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#ifndef __INCLUDE_DBSC5_H__ +#define __INCLUDE_DBSC5_H__ + +/* The number of channels X5H has */ +#define DRAM_CH_CNT 16 +/* The number of slices X5H has */ +#define SLICE_CNT 2 +/* The number of chip select X5H has */ +#define CS_CNT 2 + +struct renesas_dbsc5_board_config { + u32 bdcfg_phyvalid; + u32 bdcfg_tx_drv; + u32 bdcfg_tx_ffc; + u32 bdcfg_rx_odt; + u8 bdcfg_rx_dfe; + u8 bdcfg_tx_odt; + u8 bdcfg_tx_ntodt; + u8 bdcfg_tx_dfe; + u8 bdcfg_rx_dca; + u8 bdcfg_rx_drv; + u32 bdcfg_rx_emphasis; + u8 bdcfg_tx_dca; + u8 bdcfg_ca_vref; + u32 bdcfg_rx_vref; + u32 bdcfg_rx_vref_step; + u32 bdcfg_tx_vref; + u8 bdcfg_rfm_chk; + + /* Board parameter about channels */ + struct { + /* + * 0x00: 4Gb dual channel die / 2Gb single channel die + * 0x01: 6Gb dual channel die / 3Gb single channel die + * 0x02: 8Gb dual channel die / 4Gb single channel die + * 0x03: 12Gb dual channel die / 6Gb single channel die + * 0x04: 16Gb dual channel die / 8Gb single channel die + * 0x05: 24Gb dual channel die / 12Gb single channel die + * 0x06: 32Gb dual channel die / 16Gb single channel die + * 0x07: 24Gb single channel die + * 0x08: 32Gb single channel die + * 0xFF: NO_MEMORY + */ + u8 bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + u32 bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + u8 bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + u32 bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + u8 bdcfg_dm_swap[SLICE_CNT]; + } ch[DRAM_CH_CNT]; +}; + +#endif /* __INCLUDE_DBSC5_H__ */ |