diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/sunxi-common.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/sun20i-d1-ccu.h | 158 | ||||
| -rw-r--r-- | include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 | ||||
| -rw-r--r-- | include/dt-bindings/clock/sun50i-h6-ccu.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/sun50i-h616-ccu.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/sun6i-rtc.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/reset/sun20i-d1-ccu.h | 79 | ||||
| -rw-r--r-- | include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 | ||||
| -rw-r--r-- | include/dt-bindings/reset/sun50i-h6-ccu.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/reset/sun50i-h6-r-ccu.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/reset/sun50i-h616-ccu.h | 2 | ||||
| -rw-r--r-- | include/sunxi_gpio.h | 215 |
12 files changed, 494 insertions, 7 deletions
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d2d70f0fc23..b8ca77d031d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -12,7 +12,6 @@ #ifndef _SUNXI_COMMON_CONFIG_H #define _SUNXI_COMMON_CONFIG_H -#include <asm/arch/cpu.h> #include <linux/stringify.h> /* Serial & console */ @@ -24,6 +23,7 @@ #define CFG_SYS_NS16550_CLK 24000000 #endif #if !CONFIG_IS_ENABLED(DM_SERIAL) +#include <asm/arch/serial.h> # define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h new file mode 100644 index 00000000000..fdbfb404f92 --- /dev/null +++ b/include/dt-bindings/clock/sun20i-d1-ccu.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2020 [email protected] + * Copyright (C) 2021 Samuel Holland <[email protected]> + */ + +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ +#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ + +#define CLK_PLL_CPUX 0 +#define CLK_PLL_DDR0 1 +#define CLK_PLL_PERIPH0_4X 2 +#define CLK_PLL_PERIPH0_2X 3 +#define CLK_PLL_PERIPH0_800M 4 +#define CLK_PLL_PERIPH0 5 +#define CLK_PLL_PERIPH0_DIV3 6 +#define CLK_PLL_VIDEO0_4X 7 +#define CLK_PLL_VIDEO0_2X 8 +#define CLK_PLL_VIDEO0 9 +#define CLK_PLL_VIDEO1_4X 10 +#define CLK_PLL_VIDEO1_2X 11 +#define CLK_PLL_VIDEO1 12 +#define CLK_PLL_VE 13 +#define CLK_PLL_AUDIO0_4X 14 +#define CLK_PLL_AUDIO0_2X 15 +#define CLK_PLL_AUDIO0 16 +#define CLK_PLL_AUDIO1 17 +#define CLK_PLL_AUDIO1_DIV2 18 +#define CLK_PLL_AUDIO1_DIV5 19 +#define CLK_CPUX 20 +#define CLK_CPUX_AXI 21 +#define CLK_CPUX_APB 22 +#define CLK_PSI_AHB 23 +#define CLK_APB0 24 +#define CLK_APB1 25 +#define CLK_MBUS 26 +#define CLK_DE 27 +#define CLK_BUS_DE 28 +#define CLK_DI 29 +#define CLK_BUS_DI 30 +#define CLK_G2D 31 +#define CLK_BUS_G2D 32 +#define CLK_CE 33 +#define CLK_BUS_CE 34 +#define CLK_VE 35 +#define CLK_BUS_VE 36 +#define CLK_BUS_DMA 37 +#define CLK_BUS_MSGBOX0 38 +#define CLK_BUS_MSGBOX1 39 +#define CLK_BUS_MSGBOX2 40 +#define CLK_BUS_SPINLOCK 41 +#define CLK_BUS_HSTIMER 42 +#define CLK_AVS 43 +#define CLK_BUS_DBG 44 +#define CLK_BUS_PWM 45 +#define CLK_BUS_IOMMU 46 +#define CLK_DRAM 47 +#define CLK_MBUS_DMA 48 +#define CLK_MBUS_VE 49 +#define CLK_MBUS_CE 50 +#define CLK_MBUS_TVIN 51 +#define CLK_MBUS_CSI 52 +#define CLK_MBUS_G2D 53 +#define CLK_MBUS_RISCV 54 +#define CLK_BUS_DRAM 55 +#define CLK_MMC0 56 +#define CLK_MMC1 57 +#define CLK_MMC2 58 +#define CLK_BUS_MMC0 59 +#define CLK_BUS_MMC1 60 +#define CLK_BUS_MMC2 61 +#define CLK_BUS_UART0 62 +#define CLK_BUS_UART1 63 +#define CLK_BUS_UART2 64 +#define CLK_BUS_UART3 65 +#define CLK_BUS_UART4 66 +#define CLK_BUS_UART5 67 +#define CLK_BUS_I2C0 68 +#define CLK_BUS_I2C1 69 +#define CLK_BUS_I2C2 70 +#define CLK_BUS_I2C3 71 +#define CLK_SPI0 72 +#define CLK_SPI1 73 +#define CLK_BUS_SPI0 74 +#define CLK_BUS_SPI1 75 +#define CLK_EMAC_25M 76 +#define CLK_BUS_EMAC 77 +#define CLK_IR_TX 78 +#define CLK_BUS_IR_TX 79 +#define CLK_BUS_GPADC 80 +#define CLK_BUS_THS 81 +#define CLK_I2S0 82 +#define CLK_I2S1 83 +#define CLK_I2S2 84 +#define CLK_I2S2_ASRC 85 +#define CLK_BUS_I2S0 86 +#define CLK_BUS_I2S1 87 +#define CLK_BUS_I2S2 88 +#define CLK_SPDIF_TX 89 +#define CLK_SPDIF_RX 90 +#define CLK_BUS_SPDIF 91 +#define CLK_DMIC 92 +#define CLK_BUS_DMIC 93 +#define CLK_AUDIO_DAC 94 +#define CLK_AUDIO_ADC 95 +#define CLK_BUS_AUDIO 96 +#define CLK_USB_OHCI0 97 +#define CLK_USB_OHCI1 98 +#define CLK_BUS_OHCI0 99 +#define CLK_BUS_OHCI1 100 +#define CLK_BUS_EHCI0 101 +#define CLK_BUS_EHCI1 102 +#define CLK_BUS_OTG 103 +#define CLK_BUS_LRADC 104 +#define CLK_BUS_DPSS_TOP 105 +#define CLK_HDMI_24M 106 +#define CLK_HDMI_CEC_32K 107 +#define CLK_HDMI_CEC 108 +#define CLK_BUS_HDMI 109 +#define CLK_MIPI_DSI 110 +#define CLK_BUS_MIPI_DSI 111 +#define CLK_TCON_LCD0 112 +#define CLK_BUS_TCON_LCD0 113 +#define CLK_TCON_TV 114 +#define CLK_BUS_TCON_TV 115 +#define CLK_TVE 116 +#define CLK_BUS_TVE_TOP 117 +#define CLK_BUS_TVE 118 +#define CLK_TVD 119 +#define CLK_BUS_TVD_TOP 120 +#define CLK_BUS_TVD 121 +#define CLK_LEDC 122 +#define CLK_BUS_LEDC 123 +#define CLK_CSI_TOP 124 +#define CLK_CSI_MCLK 125 +#define CLK_BUS_CSI 126 +#define CLK_TPADC 127 +#define CLK_BUS_TPADC 128 +#define CLK_BUS_TZMA 129 +#define CLK_DSP 130 +#define CLK_BUS_DSP_CFG 131 +#define CLK_RISCV 132 +#define CLK_RISCV_AXI 133 +#define CLK_BUS_RISCV_CFG 134 +#define CLK_FANOUT_24M 135 +#define CLK_FANOUT_12M 136 +#define CLK_FANOUT_16M 137 +#define CLK_FANOUT_25M 138 +#define CLK_FANOUT_32K 139 +#define CLK_FANOUT_27M 140 +#define CLK_FANOUT_PCLK 141 +#define CLK_FANOUT0 142 +#define CLK_FANOUT1 143 +#define CLK_FANOUT2 144 +#define CLK_BUS_CAN0 145 +#define CLK_BUS_CAN1 146 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h new file mode 100644 index 00000000000..f95c170711e --- /dev/null +++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2021 Samuel Holland <[email protected]> + */ + +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ + +#define CLK_R_AHB 0 + +#define CLK_BUS_R_TIMER 2 +#define CLK_BUS_R_TWD 3 +#define CLK_BUS_R_PPU 4 +#define CLK_R_IR_RX 5 +#define CLK_BUS_R_IR_RX 6 +#define CLK_BUS_R_RTC 7 +#define CLK_BUS_R_CPUCFG 8 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h index a1545cd60e7..ef9123d8193 100644 --- a/include/dt-bindings/clock/sun50i-h6-ccu.h +++ b/include/dt-bindings/clock/sun50i-h6-ccu.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2017 Icenowy Zheng <[email protected]> */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 1191aca53ac..6f8f01e6762 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2020 Arm Ltd. */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h index c845493e4d3..3bd3aa3d57c 100644 --- a/include/dt-bindings/clock/sun6i-rtc.h +++ b/include/dt-bindings/clock/sun6i-rtc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ #ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ #define _DT_BINDINGS_CLK_SUN6I_RTC_H_ diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h new file mode 100644 index 00000000000..79e52aca591 --- /dev/null +++ b/include/dt-bindings/reset/sun20i-d1-ccu.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2020 [email protected] + * Copyright (C) 2021 Samuel Holland <[email protected]> + */ + +#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ +#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DI 2 +#define RST_BUS_G2D 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MSGBOX0 7 +#define RST_BUS_MSGBOX1 8 +#define RST_BUS_MSGBOX2 9 +#define RST_BUS_SPINLOCK 10 +#define RST_BUS_HSTIMER 11 +#define RST_BUS_DBG 12 +#define RST_BUS_PWM 13 +#define RST_BUS_DRAM 14 +#define RST_BUS_MMC0 15 +#define RST_BUS_MMC1 16 +#define RST_BUS_MMC2 17 +#define RST_BUS_UART0 18 +#define RST_BUS_UART1 19 +#define RST_BUS_UART2 20 +#define RST_BUS_UART3 21 +#define RST_BUS_UART4 22 +#define RST_BUS_UART5 23 +#define RST_BUS_I2C0 24 +#define RST_BUS_I2C1 25 +#define RST_BUS_I2C2 26 +#define RST_BUS_I2C3 27 +#define RST_BUS_SPI0 28 +#define RST_BUS_SPI1 29 +#define RST_BUS_EMAC 30 +#define RST_BUS_IR_TX 31 +#define RST_BUS_GPADC 32 +#define RST_BUS_THS 33 +#define RST_BUS_I2S0 34 +#define RST_BUS_I2S1 35 +#define RST_BUS_I2S2 36 +#define RST_BUS_SPDIF 37 +#define RST_BUS_DMIC 38 +#define RST_BUS_AUDIO 39 +#define RST_USB_PHY0 40 +#define RST_USB_PHY1 41 +#define RST_BUS_OHCI0 42 +#define RST_BUS_OHCI1 43 +#define RST_BUS_EHCI0 44 +#define RST_BUS_EHCI1 45 +#define RST_BUS_OTG 46 +#define RST_BUS_LRADC 47 +#define RST_BUS_DPSS_TOP 48 +#define RST_BUS_HDMI_SUB 49 +#define RST_BUS_HDMI_MAIN 50 +#define RST_BUS_MIPI_DSI 51 +#define RST_BUS_TCON_LCD0 52 +#define RST_BUS_TCON_TV 53 +#define RST_BUS_LVDS0 54 +#define RST_BUS_TVE 55 +#define RST_BUS_TVE_TOP 56 +#define RST_BUS_TVD 57 +#define RST_BUS_TVD_TOP 58 +#define RST_BUS_LEDC 59 +#define RST_BUS_CSI 60 +#define RST_BUS_TPADC 61 +#define RST_DSP 62 +#define RST_BUS_DSP_CFG 63 +#define RST_BUS_DSP_DBG 64 +#define RST_BUS_RISCV_CFG 65 +#define RST_BUS_CAN0 66 +#define RST_BUS_CAN1 67 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h new file mode 100644 index 00000000000..e20babc990a --- /dev/null +++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2021 Samuel Holland <[email protected]> + */ + +#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_TWD 1 +#define RST_BUS_R_PPU 2 +#define RST_BUS_R_IR_RX 3 +#define RST_BUS_R_RTC 4 +#define RST_BUS_R_CPUCFG 5 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h index 81106f45509..d038ddfa481 100644 --- a/include/dt-bindings/reset/sun50i-h6-ccu.h +++ b/include/dt-bindings/reset/sun50i-h6-ccu.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2017 Icenowy Zheng <[email protected]> */ diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h index 7950e799c76..d541ade884f 100644 --- a/include/dt-bindings/reset/sun50i-h6-r-ccu.h +++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2016 Icenowy Zheng <[email protected]> */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index cb6285a8d12..1bd8bb0a11b 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2020 Arm Ltd. */ diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h new file mode 100644 index 00000000000..db3742c0397 --- /dev/null +++ b/include/sunxi_gpio.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <[email protected]> + * + * Definitions that are shared between the Allwinner pinctrl and GPIO drivers, + * also used by some non-DM SPL code directly. + */ + +#ifndef _SUNXI_GPIO_H +#define _SUNXI_GPIO_H + +#include <linux/types.h> + +#if defined(CONFIG_MACH_SUN9I) +#define SUNXI_PIO_BASE 0x06000800 +#define SUNXI_R_PIO_BASE 0x08002c00 +#elif defined(CONFIG_SUN50I_GEN_H6) +#define SUNXI_PIO_BASE 0x0300b000 +#define SUNXI_R_PIO_BASE 0x07022000 +#elif defined(CONFIG_SUNXI_GEN_NCAT2) +#define SUNXI_PIO_BASE 0x02000000 +#define SUNXI_R_PIO_BASE 0x07022000 +#else +#define SUNXI_PIO_BASE 0x01c20800 +#define SUNXI_R_PIO_BASE 0x01f02c00 +#endif + +/* + * sunxi has 9 banks of gpio, they are: + * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 + * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 + * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 + */ + +#define SUNXI_GPIO_A 0 +#define SUNXI_GPIO_B 1 +#define SUNXI_GPIO_C 2 +#define SUNXI_GPIO_D 3 +#define SUNXI_GPIO_E 4 +#define SUNXI_GPIO_F 5 +#define SUNXI_GPIO_G 6 +#define SUNXI_GPIO_H 7 +#define SUNXI_GPIO_I 8 + +/* + * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) + * at a different register offset. + * + * sun6i has 2 banks: + * PL0 - PL8 | PM0 - PM7 + * + * sun8i has 1 bank: + * PL0 - PL11 + * + * sun9i has 3 banks: + * PL0 - PL9 | PM0 - PM15 | PN0 - PN1 + */ +#define SUNXI_GPIO_L 11 +#define SUNXI_GPIO_M 12 +#define SUNXI_GPIO_N 13 + +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 + +#define SUNXI_GPIOS_PER_BANK 32 + +#define SUNXI_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) + +enum sunxi_gpio_number { + SUNXI_GPIO_A_START = 0, + SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), + SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), + SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), + SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), + SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), + SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), + SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), + SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), + SUNXI_GPIO_L_START = 352, + SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), + SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), + SUNXI_GPIO_AXP0_START = 1024, +}; + +/* SUNXI GPIO number definitions */ +#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) +#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) +#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) +#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) +#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) +#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) +#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) +#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) +#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) +#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) + +#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) + +/* GPIO pin function config */ +#define SUNXI_GPIO_INPUT 0 +#define SUNXI_GPIO_OUTPUT 1 + +#define SUN8I_H3_GPA_UART0 2 +#define SUN8I_H3_GPA_UART2 2 + +#define SUN4I_GPB_PWM 2 +#define SUN4I_GPB_TWI0 2 +#define SUN4I_GPB_TWI1 2 +#define SUN5I_GPB_TWI1 2 +#define SUN8I_V3S_GPB_TWI0 2 +#define SUN4I_GPB_UART0 2 +#define SUN5I_GPB_UART0 2 +#define SUN8I_GPB_UART2 2 +#define SUN8I_A33_GPB_UART0 3 +#define SUN8I_A83T_GPB_UART0 2 +#define SUN8I_V3S_GPB_UART0 3 +#define SUN50I_GPB_UART0 4 + +#define SUNXI_GPC_NAND 2 +#define SUNXI_GPC_SPI0 3 +#define SUNXI_GPC_SDC2 3 +#define SUN6I_GPC_SDC3 4 +#define SUN50I_GPC_SPI0 4 +#define SUNIV_GPC_SPI0 2 + +#define SUNXI_GPD_LCD0 2 +#define SUNXI_GPD_LVDS0 3 + +#define SUNIV_GPE_UART0 5 + +#define SUNXI_GPF_SDC0 2 +#define SUNXI_GPF_UART0 4 +#define SUN8I_GPF_UART0 3 + +#define SUN4I_GPG_SDC1 4 +#define SUN5I_GPG_SDC1 2 +#define SUN6I_GPG_SDC1 2 +#define SUN8I_GPG_SDC1 2 +#define SUN8I_GPG_UART1 2 +#define SUN5I_GPG_UART1 4 + +#define SUN6I_GPH_PWM 2 +#define SUN8I_GPH_PWM 2 +#define SUN4I_GPH_SDC1 5 +#define SUN6I_GPH_TWI0 2 +#define SUN8I_GPH_TWI0 2 +#define SUN50I_GPH_TWI0 2 +#define SUN6I_GPH_TWI1 2 +#define SUN8I_GPH_TWI1 2 +#define SUN50I_GPH_TWI1 2 +#define SUN6I_GPH_UART0 2 +#define SUN9I_GPH_UART0 2 +#define SUN50I_H6_GPH_UART0 2 +#define SUN50I_H616_GPH_UART0 2 + +#define SUNXI_GPI_SDC3 2 + +#define SUN6I_GPL0_R_P2WI_SCK 3 +#define SUN6I_GPL1_R_P2WI_SDA 3 + +#define SUN8I_GPL_R_RSB 2 +#define SUN8I_H3_GPL_R_TWI 2 +#define SUN8I_A23_GPL_R_TWI 3 +#define SUN8I_GPL_R_UART 2 +#define SUN50I_GPL_R_TWI 2 +#define SUN50I_H616_GPL_R_TWI 3 + +#define SUN9I_GPN_R_RSB 3 + +#ifdef CONFIG_SUNXI_NEW_PINCTRL + #define SUNXI_PINCTRL_BANK_SIZE 0x30 + #define SUNXI_GPIO_DISABLE 0xf +#else + #define SUNXI_PINCTRL_BANK_SIZE 0x24 + #define SUNXI_GPIO_DISABLE 0x7 +#endif + +/* GPIO pin pull-up/down config */ +#define SUNXI_GPIO_PULL_DISABLE 0 +#define SUNXI_GPIO_PULL_UP 1 +#define SUNXI_GPIO_PULL_DOWN 2 + +/* Virtual AXP0 GPIOs */ +#define SUNXI_GPIO_AXP0_PREFIX "AXP0-" +#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 +#define SUNXI_GPIO_AXP0_GPIO_COUNT 6 + +struct sunxi_gpio_plat { + void *regs; + char bank_name[3]; +}; + +/* prototypes for the non-DM GPIO/pinctrl functions, used in the SPL */ +void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val); +void sunxi_gpio_set_cfgpin(u32 pin, u32 val); +int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset); +int sunxi_gpio_get_cfgpin(u32 pin); +void sunxi_gpio_set_drv(u32 pin, u32 val); +void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val); +void sunxi_gpio_set_pull(u32 pin, u32 val); +void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val); +int sunxi_name_to_gpio(const char *name); + +#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO +int axp_gpio_init(void); +#else +static inline int axp_gpio_init(void) { return 0; } +#endif + +#endif /* _SUNXI_GPIO_H */ |