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-rw-r--r--include/dt-bindings/clock/qcom,gcc-ipq4019.h169
-rw-r--r--include/linux/bitmap.h8
-rw-r--r--include/soc/qcom/cmd-db.h30
-rw-r--r--include/soc/qcom/rpmh.h28
-rw-r--r--include/soc/qcom/tcs.h81
5 files changed, 147 insertions, 169 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
deleted file mode 100644
index 7e8a7be6dcd..00000000000
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-#ifndef __QCOM_CLK_IPQ4019_H__
-#define __QCOM_CLK_IPQ4019_H__
-
-#define GCC_DUMMY_CLK 0
-#define AUDIO_CLK_SRC 1
-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2
-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3
-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4
-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5
-#define BLSP1_UART1_APPS_CLK_SRC 6
-#define BLSP1_UART2_APPS_CLK_SRC 7
-#define GCC_USB3_MOCK_UTMI_CLK_SRC 8
-#define GCC_APPS_CLK_SRC 9
-#define GCC_APPS_AHB_CLK_SRC 10
-#define GP1_CLK_SRC 11
-#define GP2_CLK_SRC 12
-#define GP3_CLK_SRC 13
-#define SDCC1_APPS_CLK_SRC 14
-#define FEPHY_125M_DLY_CLK_SRC 15
-#define WCSS2G_CLK_SRC 16
-#define WCSS5G_CLK_SRC 17
-#define GCC_APSS_AHB_CLK 18
-#define GCC_AUDIO_AHB_CLK 19
-#define GCC_AUDIO_PWM_CLK 20
-#define GCC_BLSP1_AHB_CLK 21
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25
-#define GCC_BLSP1_UART1_APPS_CLK 26
-#define GCC_BLSP1_UART2_APPS_CLK 27
-#define GCC_DCD_XO_CLK 28
-#define GCC_GP1_CLK 29
-#define GCC_GP2_CLK 30
-#define GCC_GP3_CLK 31
-#define GCC_BOOT_ROM_AHB_CLK 32
-#define GCC_CRYPTO_AHB_CLK 33
-#define GCC_CRYPTO_AXI_CLK 34
-#define GCC_CRYPTO_CLK 35
-#define GCC_ESS_CLK 36
-#define GCC_IMEM_AXI_CLK 37
-#define GCC_IMEM_CFG_AHB_CLK 38
-#define GCC_PCIE_AHB_CLK 39
-#define GCC_PCIE_AXI_M_CLK 40
-#define GCC_PCIE_AXI_S_CLK 41
-#define GCC_PCNOC_AHB_CLK 42
-#define GCC_PRNG_AHB_CLK 43
-#define GCC_QPIC_AHB_CLK 44
-#define GCC_QPIC_CLK 45
-#define GCC_SDCC1_AHB_CLK 46
-#define GCC_SDCC1_APPS_CLK 47
-#define GCC_SNOC_PCNOC_AHB_CLK 48
-#define GCC_SYS_NOC_125M_CLK 49
-#define GCC_SYS_NOC_AXI_CLK 50
-#define GCC_TCSR_AHB_CLK 51
-#define GCC_TLMM_AHB_CLK 52
-#define GCC_USB2_MASTER_CLK 53
-#define GCC_USB2_SLEEP_CLK 54
-#define GCC_USB2_MOCK_UTMI_CLK 55
-#define GCC_USB3_MASTER_CLK 56
-#define GCC_USB3_SLEEP_CLK 57
-#define GCC_USB3_MOCK_UTMI_CLK 58
-#define GCC_WCSS2G_CLK 59
-#define GCC_WCSS2G_REF_CLK 60
-#define GCC_WCSS2G_RTC_CLK 61
-#define GCC_WCSS5G_CLK 62
-#define GCC_WCSS5G_REF_CLK 63
-#define GCC_WCSS5G_RTC_CLK 64
-#define GCC_APSS_DDRPLL_VCO 65
-#define GCC_SDCC_PLLDIV_CLK 66
-#define GCC_FEPLL_VCO 67
-#define GCC_FEPLL125_CLK 68
-#define GCC_FEPLL125DLY_CLK 69
-#define GCC_FEPLL200_CLK 70
-#define GCC_FEPLL500_CLK 71
-#define GCC_FEPLL_WCSS2G_CLK 72
-#define GCC_FEPLL_WCSS5G_CLK 73
-#define GCC_APSS_CPU_PLLDIV_CLK 74
-#define GCC_PCNOC_AHB_CLK_SRC 75
-
-#define WIFI0_CPU_INIT_RESET 0
-#define WIFI0_RADIO_SRIF_RESET 1
-#define WIFI0_RADIO_WARM_RESET 2
-#define WIFI0_RADIO_COLD_RESET 3
-#define WIFI0_CORE_WARM_RESET 4
-#define WIFI0_CORE_COLD_RESET 5
-#define WIFI1_CPU_INIT_RESET 6
-#define WIFI1_RADIO_SRIF_RESET 7
-#define WIFI1_RADIO_WARM_RESET 8
-#define WIFI1_RADIO_COLD_RESET 9
-#define WIFI1_CORE_WARM_RESET 10
-#define WIFI1_CORE_COLD_RESET 11
-#define USB3_UNIPHY_PHY_ARES 12
-#define USB3_HSPHY_POR_ARES 13
-#define USB3_HSPHY_S_ARES 14
-#define USB2_HSPHY_POR_ARES 15
-#define USB2_HSPHY_S_ARES 16
-#define PCIE_PHY_AHB_ARES 17
-#define PCIE_AHB_ARES 18
-#define PCIE_PWR_ARES 19
-#define PCIE_PIPE_STICKY_ARES 20
-#define PCIE_AXI_M_STICKY_ARES 21
-#define PCIE_PHY_ARES 22
-#define PCIE_PARF_XPU_ARES 23
-#define PCIE_AXI_S_XPU_ARES 24
-#define PCIE_AXI_M_VMIDMT_ARES 25
-#define PCIE_PIPE_ARES 26
-#define PCIE_AXI_S_ARES 27
-#define PCIE_AXI_M_ARES 28
-#define ESS_RESET 29
-#define GCC_BLSP1_BCR 30
-#define GCC_BLSP1_QUP1_BCR 31
-#define GCC_BLSP1_UART1_BCR 32
-#define GCC_BLSP1_QUP2_BCR 33
-#define GCC_BLSP1_UART2_BCR 34
-#define GCC_BIMC_BCR 35
-#define GCC_TLMM_BCR 36
-#define GCC_IMEM_BCR 37
-#define GCC_ESS_BCR 38
-#define GCC_PRNG_BCR 39
-#define GCC_BOOT_ROM_BCR 40
-#define GCC_CRYPTO_BCR 41
-#define GCC_SDCC1_BCR 42
-#define GCC_SEC_CTRL_BCR 43
-#define GCC_AUDIO_BCR 44
-#define GCC_QPIC_BCR 45
-#define GCC_PCIE_BCR 46
-#define GCC_USB2_BCR 47
-#define GCC_USB2_PHY_BCR 48
-#define GCC_USB3_BCR 49
-#define GCC_USB3_PHY_BCR 50
-#define GCC_SYSTEM_NOC_BCR 51
-#define GCC_PCNOC_BCR 52
-#define GCC_DCD_BCR 53
-#define GCC_SNOC_BUS_TIMEOUT0_BCR 54
-#define GCC_SNOC_BUS_TIMEOUT1_BCR 55
-#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
-#define GCC_SNOC_BUS_TIMEOUT3_BCR 57
-#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
-#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
-#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
-#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
-#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
-#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
-#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
-#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
-#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
-#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
-#define GCC_TCSR_BCR 68
-#define GCC_QDSS_BCR 69
-#define GCC_MPM_BCR 70
-#define GCC_SPDM_BCR 71
-
-#endif
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index 0a8503af9f1..40ca2212cb4 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -196,6 +196,14 @@ static inline void bitmap_fill(unsigned long *dst, unsigned int nbits)
}
}
+static inline bool bitmap_empty(const unsigned long *src, unsigned int nbits)
+{
+ if (small_const_nbits(nbits))
+ return !(*src & BITMAP_LAST_WORD_MASK(nbits));
+
+ return find_first_bit(src, nbits) == nbits;
+}
+
static inline void bitmap_or(unsigned long *dst, const unsigned long *src1,
const unsigned long *src2, unsigned int nbits)
{
diff --git a/include/soc/qcom/cmd-db.h b/include/soc/qcom/cmd-db.h
new file mode 100644
index 00000000000..1190f2c22ca
--- /dev/null
+++ b/include/soc/qcom/cmd-db.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __QCOM_COMMAND_DB_H__
+#define __QCOM_COMMAND_DB_H__
+
+#include <linux/err.h>
+
+enum cmd_db_hw_type {
+ CMD_DB_HW_INVALID = 0,
+ CMD_DB_HW_MIN = 3,
+ CMD_DB_HW_ARC = CMD_DB_HW_MIN,
+ CMD_DB_HW_VRM = 4,
+ CMD_DB_HW_BCM = 5,
+ CMD_DB_HW_MAX = CMD_DB_HW_BCM,
+ CMD_DB_HW_ALL = 0xff,
+};
+
+#if IS_ENABLED(CONFIG_QCOM_COMMAND_DB)
+u32 cmd_db_read_addr(const char *resource_id);
+
+#else
+static inline u32 cmd_db_read_addr(const char *resource_id)
+{ return 0; }
+
+#endif /* CONFIG_QCOM_COMMAND_DB */
+#endif /* __QCOM_COMMAND_DB_H__ */
diff --git a/include/soc/qcom/rpmh.h b/include/soc/qcom/rpmh.h
new file mode 100644
index 00000000000..3421fbf1ee3
--- /dev/null
+++ b/include/soc/qcom/rpmh.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __SOC_QCOM_RPMH_H__
+#define __SOC_QCOM_RPMH_H__
+
+#include <dm/device-internal.h>
+#include <soc/qcom/tcs.h>
+
+
+#if IS_ENABLED(CONFIG_QCOM_RPMH)
+int rpmh_write(const struct udevice *dev, enum rpmh_state state,
+ const struct tcs_cmd *cmd, u32 n);
+
+#else
+
+static inline int rpmh_write(const struct device *dev, enum rpmh_state state,
+ const struct tcs_cmd *cmd, u32 n)
+{ return -ENODEV; }
+
+#endif /* CONFIG_QCOM_RPMH */
+
+/* u-boot: no multithreading */
+#define rpmh_write_async(dev, state, cmd, n) rpmh_write(dev, state, cmd, n)
+
+#endif /* __SOC_QCOM_RPMH_H__ */
diff --git a/include/soc/qcom/tcs.h b/include/soc/qcom/tcs.h
new file mode 100644
index 00000000000..3acca067c72
--- /dev/null
+++ b/include/soc/qcom/tcs.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __SOC_QCOM_TCS_H__
+#define __SOC_QCOM_TCS_H__
+
+#define MAX_RPMH_PAYLOAD 16
+
+/**
+ * rpmh_state: state for the request
+ *
+ * RPMH_SLEEP_STATE: State of the resource when the processor subsystem
+ * is powered down. There is no client using the
+ * resource actively.
+ * RPMH_WAKE_ONLY_STATE: Resume resource state to the value previously
+ * requested before the processor was powered down.
+ * RPMH_ACTIVE_ONLY_STATE: Active or AMC mode requests. Resource state
+ * is aggregated immediately.
+ */
+enum rpmh_state {
+ RPMH_SLEEP_STATE,
+ RPMH_WAKE_ONLY_STATE,
+ RPMH_ACTIVE_ONLY_STATE,
+};
+
+/**
+ * struct tcs_cmd: an individual request to RPMH.
+ *
+ * @addr: the address of the resource slv_id:18:16 | offset:0:15
+ * @data: the resource state request
+ * @wait: ensure that this command is complete before returning.
+ * Setting "wait" here only makes sense during rpmh_write_batch() for
+ * active-only transfers, this is because:
+ * rpmh_write() - Always waits.
+ * (DEFINE_RPMH_MSG_ONSTACK will set .wait_for_compl)
+ * rpmh_write_async() - Never waits.
+ * (There's no request completion callback)
+ */
+struct tcs_cmd {
+ u32 addr;
+ u32 data;
+ u32 wait;
+};
+
+/**
+ * struct tcs_request: A set of tcs_cmds sent together in a TCS
+ *
+ * @state: state for the request.
+ * @wait_for_compl: wait until we get a response from the h/w accelerator
+ * (same as setting cmd->wait for all commands in the request)
+ * @num_cmds: the number of @cmds in this request
+ * @cmds: an array of tcs_cmds
+ */
+struct tcs_request {
+ enum rpmh_state state;
+ u32 wait_for_compl;
+ u32 num_cmds;
+ struct tcs_cmd *cmds;
+};
+
+#define BCM_TCS_CMD_COMMIT_SHFT 30
+#define BCM_TCS_CMD_COMMIT_MASK 0x40000000
+#define BCM_TCS_CMD_VALID_SHFT 29
+#define BCM_TCS_CMD_VALID_MASK 0x20000000
+#define BCM_TCS_CMD_VOTE_X_SHFT 14
+#define BCM_TCS_CMD_VOTE_MASK 0x3fff
+#define BCM_TCS_CMD_VOTE_Y_SHFT 0
+#define BCM_TCS_CMD_VOTE_Y_MASK 0xfffc000
+
+/* Construct a Bus Clock Manager (BCM) specific TCS command */
+#define BCM_TCS_CMD(commit, valid, vote_x, vote_y) \
+ (((commit) << BCM_TCS_CMD_COMMIT_SHFT) | \
+ ((valid) << BCM_TCS_CMD_VALID_SHFT) | \
+ ((cpu_to_le32(vote_x) & \
+ BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_X_SHFT) | \
+ ((cpu_to_le32(vote_y) & \
+ BCM_TCS_CMD_VOTE_MASK) << BCM_TCS_CMD_VOTE_Y_SHFT))
+
+#endif /* __SOC_QCOM_TCS_H__ */
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-14 18:12:05 +0000