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2025-02-26Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh ↵Tom Rini
into next bbmiiphy clean up and DM alignment, finally gets rid of the static bbmiiphy variables and plugs bbmiiphy into MDIO framework.
2025-02-26net: miiphybb: Drop bb_miiphy_buses and bb_miiphy_buses_numMarek Vasut
Neither bb_miiphy_buses nor bb_miiphy_buses_num are used anymore. Drop both of them. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26net: sh_eth: Drop use of miiphy_get_dev_by_name()Marek Vasut
Instead of doing another lookup, trivially access the struct mii_dev embedded in struct bb_miiphy_bus . No functional change. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: ravb: Drop use of miiphy_get_dev_by_name()Marek Vasut
Instead of doing another lookup, trivially access the struct mii_dev embedded in struct bb_miiphy_bus . No functional change. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26arm: mvebu: a38x: Drop use of miiphy_get_dev_by_name()Marek Vasut
Instead of doing another lookup, trivially access the struct mii_dev embedded in struct bb_miiphy_bus . No functional change. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: miiphybb: Drop name field from struct bb_miiphy_busMarek Vasut
The struct bb_miiphy_bus embeds struct struct mii_dev, which already contains one copy of name field. Drop the duplicate top level copy of name field. The a38x code does static assignment of disparate names, use snprintf(...) to fill in matching name in probe to avoid any breakage. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26net: miiphybb: Use container_of() in bb_miiphy_getbus()Marek Vasut
Replace the name based look up in bb_miiphy_getbus() with trivial container_of() call. This works because the struct bb_miiphy_bus always embeds the matching struct mii_dev . This also makes the code much simpler and more efficient. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26net: designware: Allocate bb_miiphy using bb_miiphy_alloc() and fill in ↵Marek Vasut
callbacks Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks currently listed in bb_miiphy_buses[] array. This is a temporary duplication of assignment to avoid breakage, which will be removed in follow up patches. At this point, the bb_miiphy callbacks can reach these accessors by doing container_of() on struct mii_dev. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: sh_eth: Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacksMarek Vasut
Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks currently listed in bb_miiphy_buses[] array. This is a temporary duplication of assignment to avoid breakage, which will be removed in follow up patches. At this point, the bb_miiphy callbacks can reach these accessors by doing container_of() on struct mii_dev. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: ravb: Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacksMarek Vasut
Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks currently listed in bb_miiphy_buses[] array. This is a temporary duplication of assignment to avoid breakage, which will be removed in follow up patches. At this point, the bb_miiphy callbacks can reach these accessors by doing container_of() on struct mii_dev. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26arm: mvebu: a38x: Allocate bb_miiphy using bb_miiphy_alloc() and fill in ↵Marek Vasut
callbacks Allocate bb_miiphy using bb_miiphy_alloc() and fill in callbacks currently listed in bb_miiphy_buses[] array. This is a temporary duplication of assignment to avoid breakage, which will be removed in follow up patches. At this point, the bb_miiphy callbacks can reach these accessors by doing container_of() on struct mii_dev. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: miiphybb: Introduce bb_miiphy_alloc()/bb_miiphy_free() wrappersMarek Vasut
Introduce bb_miiphy_alloc()/bb_miiphy_free() wrappers to allocate and free struct bb_miiphy_bus. Make struct bb_miiphy_bus wrap struct mii_dev, which will become useful later in bb_miiphy_bus accessors, which would be able to access struct bb_miiphy_bus using container_of, even if the PHY stack only passes in the inner struct mii_dev . Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26net: miiphy: Introduce mdio_init()Marek Vasut
Introduce mdio_init() split off from mdio_alloc(), which is used to initialize already allocated struct mii_dev. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26net: designware: Extract bbmiiphy initialization into dedicated functionMarek Vasut
Pull the bbmiiphy initialization code from designware_eth_probe() into dedicated function, dw_bb_mdio_init(), just like all the other MDIO initialization functions. Keep check for "snps,bitbang-mii" in the designware_eth_probe(), so the driver can initialize this MDIO only in case the property is present, and initialize regular DW MDIO in case it is not present. The dw_bb_mdio_init() allocates its own MDIO instance, because thus far code gated behind "snps,bitbang-mii" did depend on allocation of MDIO bus by the other two MDIO bus options and then rewrote the newly allocated MDIO bus callbacks, which is wrong, instead allocate proper MDIO bus with the correct callbacks outright. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: designware: Drop bus indexMarek Vasut
There is literally one single bbmiiphy bus in this driver, remove the bus index handling. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: miiphybb: Drop bb_miiphy_init() and .init callbackMarek Vasut
The .init callback is not called by any function, drop it. There are no more users of the init callback, drop the entire mechanism. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26arm: mvebu: a38x: Call bb_miiphy init directly in driver probeMarek Vasut
All the resources needed by this .init callback should already be available by the time probe function runs, simply call the init callback directly and set the bb_miiphy init callback to NULL. This shouldn't break anything on this hardware, but would be nice if someone could double-check and test that. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: designware: Reorder bb_miiphy functionsMarek Vasut
Move the bb_miiphy functions before MDIO registration. This is a preparatory patch, the functions will be referenced around the MDIO registration in the follow up patches. No functional change. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26arm: mvebu: a38x: Reorder bb_miiphy functionsMarek Vasut
Move the bb_miiphy functions before MDIO registration. This is a preparatory patch, the functions will be referenced around the MDIO registration in the follow up patches. No functional change. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: sh_eth: Reorder bb_miiphy functionsMarek Vasut
Move the bb_miiphy functions before MDIO registration. This is a preparatory patch, the functions will be referenced around the MDIO registration in the follow up patches. No functional change. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Paul Barker <[email protected]>
2025-02-26net: ravb: Reorder bb_miiphy functionsMarek Vasut
Move the bb_miiphy functions before MDIO registration. This is a preparatory patch, the functions will be referenced around the MDIO registration in the follow up patches. No functional change. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26net: designware: Drop NULL priv assignmentMarek Vasut
This is unnecessary, the unset structure member is initialized to NULL by default, drop the assignment. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26net: sh_eth: Drop empty init callbackMarek Vasut
The init function does nothing, the bb_miiphy_init() already checks whether the .init callback is assigned, and if not, skips calling it. Remove the empty init function. The entire init callback will be removed in follow up patches. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-26net: ravb: Drop empty init callbackMarek Vasut
The init function does nothing, the bb_miiphy_init() already checks whether the .init callback is assigned, and if not, skips calling it. Remove the empty init function. The entire init callback will be removed in follow up patches. Reviewed-by: Paul Barker <[email protected]> Signed-off-by: Marek Vasut <[email protected]>
2025-02-25Merge patch series "Remove "saveenv" functionality from am57xx evms"Tom Rini
Anurag Dutta <[email protected]> says: Previously saved environment introduce discrepancies and may lead to incompatibilities without default settings. This series removes the saved environment functionality on am57xx evms so that the default configuration is always loaded Test result: https://gist.github.com/anuragdutta731/b253ddb0a5538ab6588a3535d7bbecf7 Link: https://lore.kernel.org/r/[email protected]
2025-02-25configs: am57xx: Remove saved environmentsAnurag Dutta
Saved environments lead to inconsistencies leading to conflicts with the default environment that U-boot should update during development. Remove the previously saved environment so that the default environment is always loaded. Signed-off-by: Anurag Dutta <[email protected]>
2025-02-25configs: am57xx_hs: Remove saved environmentsAnurag Dutta
Saved environments cause inconsistencies leading to conflicts with the default environment that U-boot should update during development. Remove the previously saved environment so that the default environment is always loaded. Signed-off-by: Anurag Dutta <[email protected]>
2025-02-25Merge tag 'u-boot-socfpga-next-20250225' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-socfpga into next CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/24816 Please pull the SoCFPGA changes for next from u-boot-socfpga, containing boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The changes include: 1. Board-specific configurations and setup required to enable Agilex 5 operation in U-Boot. 2. Integration of cache coherency unit (CCU) initialization routine, including CCU conguration in DT. 3. Clock, firewall (configured in DT), SMMU, low level initialization specific to Agilex 5. 4. Integration of memory initialization routine, including DDR setup. This patch set has been tested on Agilex 5 devkit with QSPI boot (UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
2025-02-25configs: agilex5: Enable watchdog autostartAlif Zakuan Yuslaimi
Automatically start watchdog timer for Agilex5. This configuration is enabled by default in the Kconfig, hence removing this configuration from Agilex5 defconfig. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFSAlif Zakuan Yuslaimi
Add the required configuration in the U-Boot env to enable Linux QSPI boot with UBI / UBIFS. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25arm: socfpga: soc64: Add support for board_boot_order()Tien Fong Chee
Add board_boot_order() to retrieve the list of boot devices from spl-boot-order property in device tree. This board_boot_order() would be used for all Intel SOC64 devices. Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25configs: socfpga: soc64: agilex5: Enable XGMACTien Fong Chee
Enable XGMAC for SoCFPGA Agilex5 devkit. Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25configs: socfpga: soc64: agilex5: Use common ARMv8 linker scriptAlif Zakuan Yuslaimi
Use default common ARMv8 linker script instead of a separate SoC64 linker script Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
2025-02-25arm: armv8: Improve SPL data save and restore implementationAlif Zakuan Yuslaimi
Introduce a new symbol in the beginning of .data section in the common ARMv8 linker script and use that as a reference for data save and restore. Previously, the code would rely on calculating the start of the .data section address via data size, however, we observed that the data size does not really reflect the SPL mapped addresses. In our case, the binman_sym section size was not included in the data size, which will result in a wrong address for the .data start section, which prevents us from properly saving and restoring SPL data. This approach skips the calculation for the starting address of the .data section, and instead just defines the beginning address of the .data section and calling the symbol as needed, in which we think as a simpler and much more robust method. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGATien Fong Chee
Add SPL support for Agilex5 SoCFPGA. Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25ddr: altera: Add DDR driver for Agilex5 seriesTingting Meng
Adding DDR driver support for Agilex5 series. Signed-off-by: Tingting Meng <[email protected]>
2025-02-25arm: socfpga: smc: Add memory coherency support to mailbox commandAlif Zakuan Yuslaimi
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to perform cache flush of buffers that are shared between U-Boot and ATF using secure monitor calls. Signed-off-by: Mahesh Rao <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25configs: agilex5: Add configuration for malloc poolTien Fong Chee
Adding configuration for SPL malloc pool. Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25arm: socfpga: Export board ID as U-Boot environmentAlif Zakuan Yuslaimi
Board ID is exported as environment variable for use to boot Linux with FIT configuration. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25arm: socfpga: agilex5: Update CPU infoAlif Zakuan Yuslaimi
Update the print info per Agilex5 Signed-off-by: Tien Fong Chee <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25arm: socfpga: agilex5: Add SMMU initializationTien Fong Chee
Allow non-secure accesses only with SMMU peripherals. This would protect the content in DDR secure region from accidentally modified by SMMU peripherals. Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25arm: socfpga: agilex5: Enable cache flush for system memory cache in CCUTien Fong Chee
set/way instructions "dc cisw" which is used by the "dcache flush" command only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in cache coherency unit, hence this patch enables data flush from system memory cache of CCU into DDR memory. Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25arch: arm: Enable PSCI reset driver for Agilex5Alif Zakuan Yuslaimi
Enable PSCI reset driver for Agilex5 cold and warm reset Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25arm: dts: agilex5: Enable XGMACTien Fong Chee
Enable XGMAC for SoCFPGA Agilex5 devkit. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25arm: dts: agilex5: Add firewall configure settingsTien Fong Chee
These firewall configure settings are needed to disable firewall on respective hardware component so both secure and non-secure transactions are allowed. Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25arm: dts: agilex5: Add HPS cache coherency unit configuration settingsTien Fong Chee
These configuration settings are required to enable cache maintenance and access between initiators and targets. Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25arm: socfpga: Add handoff data support for SoCFPGA Agilex5 deviceTien Fong Chee
Agilex5 supports both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and Agilex5 device. Signed-off-by: Tien Fong Chee <[email protected]>
2025-02-25arm: socfpga: Disable GIC for Agilex5Alif Zakuan Yuslaimi
Status polling is used instead of using interrupt controller for Agilex5. Disabling GICV3 in Agilex5 target, as well as disabling GICV2 enabled by default for all SoCFPGA devices. All the other SoCFPGA devices uses GICV2, thus enabling GICV2 in each of the devices. Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Signed-off-by: Tien Fong Chee <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25arm: socfpga: agilex5: Add warm reset mask for Agilex5Alif Zakuan Yuslaimi
There are 5 L4 watchdogs and one SDM triggered warm reset bit in Agilex5 reset manager "stat" register where bit 16:20 for L4 watchdogs. Assigning value 1 to these bits in the register address will initiate SDM to trigger warm reset. Introducing new warm reset mask for Agilex5 to trigger warm reset to all five L4 watchdogs. Signed-off-by: Tien Fong Chee <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>
2025-02-25drivers: clk: agilex5: Set PLL to asynchronous modeAlif Zakuan Yuslaimi
PLL frequency would overshoot from the original target in synchronous mode during low VCC voltage condition. To resolve this issue, PLL is set to run on asynchronous mode instead of enabling synchronous mode in the clock driver. Signed-off-by: Muhammad Hazim Izzat Zamri <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> Reviewed-by: Tien Fong Chee <[email protected]>