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2023-07-21am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.imgNeha Malcom Francis
Support added for HS-SE, HS-FS and GP boot binaries for AM62ax. HS-SE: * tiboot3-am62ax-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am62ax-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am62ax-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by AM62ax requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21am62a: yaml: Add board configs for AM62axNeha Malcom Francis
Added YAML configs for AM62ax Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.imgNeha Malcom Francis
Support added for HS-SE, HS-FS and GP boot binaries for AM62. HS-SE: * tiboot3-am62x-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am62x-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am62x-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by AM62 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21am62: yaml: Add board configs for AM62Neha Malcom Francis
Added YAML configs for AM62 Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.imgNeha Malcom Francis
Support has been added for both HS-SE, HS-FS and GP images. HS-SE: * tiboot3-j721s2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j721s2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j721s2-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J721S2 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21j721s2: yaml: Add board configs for J721S2Neha Malcom Francis
Added YAML configs for J721S2 Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.imgNeha Malcom Francis
Support added for HS and GP boot binaries for AM64x. HS-SE: * tiboot3-am64x_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am64x_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am64x-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned Note that the bootflow followed by AM64x requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * sysfw * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * ATF * OP-TEE * A53 SPL * A53 SPL dtbs u-boot.img: * A53 U-Boot * A53 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21am64x: yaml: Add board configs for AM64xNeha Malcom Francis
Added YAML configs for AM64xx Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.imgNeha Malcom Francis
Support has been added for both HS-SE(SR 2.0) and GP(SR 2.0) images. HS-SE: * tiboot3-am65x_sr2-hs-evm.bin * sysfw-am65x_sr2-hs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am65x_sr2-gp-evm.bin * sysfw.itb --> sysfw-am65x_sr2-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned Note that the bootflow followed by AM65x requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * sysfw * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * ATF * OP-TEE * A53 SPL * A53 SPL dtbs u-boot.img: * A53 U-Boot * A53 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21am65x: yaml: Add AM65x board config filesNeha Malcom Francis
Added YAML configs for AM65x Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.imgNeha Malcom Francis
Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP images. HS-SE: * tiboot3-j7200_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j7200_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j7200-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J7200 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21j7200: yaml: Add J7200 board config filesNeha Malcom Francis
Added YAML configs for J7200 Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.imgNeha Malcom Francis
By providing entries in the binman node of the device tree, binman will be able to find and package board config artifacts generated by TIBoardConfig with sysfw.bin and generate the final image sysfw.itb. It will also pick out the R5 SPL and sign it with the help of TI signing entry and generate the final tiboot3.bin. Entries for A72 build have been added to k3-j721e-binman.dtsi to generate tispl.bin and u-boot.img. Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images In HS-SE, the encrypted system firmware binary must be signed along with the signed certificate binary. HS-SE: * tiboot3-j721e_sr1_1-hs-evm.bin * sysfw-j721e_sr1_1-hs-evm.itb * tispl.bin * u-boot.img HS-FS: * tiboot3-j721e_sr2-hs-fs-evm.bin * sysfw-j721e_sr2-hs-fs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin -->tiboot3-j721e-gp-evm.bin * sysfw.itb --> sysfw-j721e-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J721E requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <[email protected]> [[email protected]: changed output binary names appropriately] Signed-off-by: Andrew Davis <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21j721e: schema: yaml: Add general schema and J721E board config filesNeha Malcom Francis
Schema file in YAML must be provided in board/ti/common for validating input config files and packaging system firmware. The schema includes entries for rm-cfg, board-cfg, pm-cfg and sec-cfg. Board config files must be provided in board/ti/<devicename> in YAML. These can then be consumed for generation of binaries to package system firmware. Added YAML configs for J721E in particular. Signed-off-by: Tarun Sahu <[email protected]> [[email protected]: prepared patch for upstreaming] Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21arm: dts: k3: Add support for packaging sysfw.itb and tiboot3.binNeha Malcom Francis
Board config binary artifacts must be generated to be used by binman to package sysfw.itb and tiboot3.bin for all K3 devices. For devices that follow combined flow, these board configuration binaries must again be packaged into a combined board configuration blobs to be used by binman to package tiboot3.bin. Add common k3-binman.dtsi to generate all the board configuration binaries needed. Also add custMpk.pem and ti-degenerate-key.pem needed for signing GP and HS bootloader images common to all K3 devices. Reviewed-by: Simon Glass <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21binman: ti-secure: Add support for TI signingNeha Malcom Francis
The ti-secure entry contains certificate for binaries that will be loaded or booted by system firmware whereas the ti-secure-rom entry contains certificate for binaries that will be booted by ROM. Support for both these types of certificates is necessary for booting of K3 devices. Reviewed-by: Simon Glass <[email protected]> [[email protected]: fixed inconsist cert generation by multiple packing] Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21binman: ti-board-config: Add support for TI board config binariesNeha Malcom Francis
The ti-board-config entry loads and validates a given YAML config file against a given schema, and generates the board config binary. K3 devices require these binaries to be packed into the final system firmware images. Reviewed-by: Simon Glass <[email protected]> Signed-off-by: Neha Malcom Francis <[email protected]>
2023-07-21Merge branch '2023-07-21-assorted-TI-platform-updates'Tom Rini
- The first half of a number of TI platform bugfixes and improvements, primarily around K3 platforms and splash screen support.
2023-07-21common: Kconfig: Fix CMD_BMP/BMP dependencySamuel Dionne-Riel
Using `default y` will not select BMP when CMD_BMP has been enabled, if it was already configured. By using `select`, if `CMD_BMP` is turned on, it will force the presence of `BMP`. Fixes: 072b0e16c4 ("common: Kconfig: Add BMP configs") Signed-off-by: Samuel Dionne-Riel <[email protected]> Signed-off-by: Nikhil M Jain <[email protected]>
2023-07-21doc: board: ti: am62x_sk: Add A53 SPL DDR layoutNikhil M Jain
To understand usage of DDR in A53 SPL stage, add a table showing region and space used by major components of SPL. Signed-off-by: Nikhil M Jain <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2023-07-21configs: am62x_evm_a53: Add bloblist addressNikhil M Jain
Set bloblist address to 0x80D00000. Signed-off-by: Nikhil M Jain <[email protected]> Reviewed-by: Devarsh Thakkar <[email protected]>
2023-07-21common: spl: spl: Remove video driverNikhil M Jain
Use config SPL_VIDEO_REMOVE to remove video driver at SPL stage before jumping to next stage, in place of CONFIG_SPL_VIDEO, to allow user to remove video if required. Signed-off-by: Nikhil M Jain <[email protected]> Reviewed-by: Devarsh Thakkar <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2023-07-21drivers: video: Kconfig: Add config remove videoNikhil M Jain
This is required since user may want to either call the remove method of video driver and reset the display or not call the remove method to continue displaying until next stage. Signed-off-by: Nikhil M Jain <[email protected]> Reviewed-by: Devarsh Thakkar <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2023-07-21common: board_f: Pass frame buffer info from SPL to u-bootNikhil M Jain
U-boot proper can use frame buffer address passed from SPL to reserve the memory area used by framebuffer set in SPL so that splash image set in SPL continues to get displayed while u-boot proper is running. Put the framebuffer address and size in a bloblist to make them available at u-boot proper, if in u-boot proper CONFIG_VIDEO is defined. Signed-off-by: Nikhil M Jain <[email protected]> Reviewed-by: Devarsh Thakkar <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2023-07-21include: video: Reserve video using blobNikhil M Jain
Add method to reserve video framebuffer information using blob, received from previous stage. Signed-off-by: Nikhil M Jain <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2023-07-21board: ti: am62x: evm: Update function calls for splash screenNikhil M Jain
Use spl_dcache_enable, in place of setup_dram, arch_reserve_mmu to set up pagetable, initialise DRAM and enable Dcache to avoid multiple function calls. Check for CONFIG_SPL_VIDEO in place of CONFIG_SPL_VIDEO_TIDSS to prevent any build failure in case video config is not defined and video related functions are called. Check for CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_BMP before calling splash_display to avoid compilation failure. Signed-off-by: Nikhil M Jain <[email protected]>
2023-07-21arch: arm: mach-k3: common: Return a pointer after setting page tableNikhil M Jain
In spl_dcache_enable after setting up page table, set gd->relocaddr pointer to tlb_addr, to get next location to reserve memory. Align tlb_addr with 64KB address. Signed-off-by: Nikhil M Jain <[email protected]> Reviewed-by: Devarsh Thakkar <[email protected]>
2023-07-21common: spl: spl: Update stack pointer addressNikhil M Jain
At SPL stage when stack is relocated, the stack pointer needs to be updated, the stack pointer may point to stack in on chip memory even though stack is relocated. Signed-off-by: Nikhil M Jain <[email protected]> Reviewed-by: Tom Rini <[email protected]>
2023-07-21arm: mach-k3: am62a7: change some prints to debug printsBryan Brattlof
There is little need to print the devstat information or when we exit a function during a typical boot. Remove them to reduce the noise during typical operation Signed-off-by: Bryan Brattlof <[email protected]>
2023-07-21ram: k3-ddrss: do not touch ctrl regs during trainingBryan Brattlof
During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <[email protected]>
2023-07-21arm: omap2: Fix warning in force_emif_self_refreshTom Rini
The function declaration for force_emif_self_refresh takes no parameters but does not specify this, only the prototype in the headers do. As clang will warn about this, correct it. Signed-off-by: Tom Rini <[email protected]>
2023-07-21configs: k2x_evm: Always include FIT loading supportAndrew Davis
Non-HS boards can use FIT images so include the env var commands for these unconditionally. Signed-off-by: Andrew Davis <[email protected]> Reviewed-by: Nishanth Menon <[email protected]>
2023-07-21arm: mach-k3: am62: Fixup CPU core, gpu and pru nodes in fdtEmanuele Ghidoli
AM62x SoC is available in multiple variant: - CPU cores (Cortex-A) AM62x1 (1 core), AM62x2 (2 cores), AM62x4 (4 cores) - GPU AM625x with GPU, AM623x without GPU - PRU (Programmable RT unit) can be present or not on AM62x2/AM62x4 Remove the relevant FDT nodes by reading the actual configuration from the SoC registers, with that change is possible to have a single dts/dtb file handling the different variant at runtime. While removing GPU node and CPU nodes also the watchdog node in the same Module Domain is removed. A similar approach is implemented for example on i.MX8 and STM32MP1 SoC. Signed-off-by: Emanuele Ghidoli <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]>
2023-07-21arm: mach-k3: am62: Add CTRLMMR_WKUP_JTAG_DEVICE_ID register definitionEmanuele Ghidoli
Add register address and relevant bitmasks and shifts. Allow reading these information: - device identification - number of cores (part of device identification) - features (currently: PRU / no PRU) - security - functional safety - speed grade - temperature grade - package Signed-off-by: Emanuele Ghidoli <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]> Reviewed-by: Andrew Davis <[email protected]>
2023-07-21arm: k3: Fix ft_system_setup so it can be enabled on any SoCEmanuele Ghidoli
ft_system_setup cannot be enabled on SoC without msmc sram otherwise fdt_fixup_msmc_ram function fails causing system reset. Fix by moving fdt_fixup_msmc_ram to common_fdt.c file and creating SoC (AM654, J721E and J721S2) specific files for fdt fixups. This change was verified to not change anything on any existing board (all the J721S2, AM654 and J721E boards requires it, none of the remaining k3 boards require it). Fixes: 30e96a240156 ("arm: mach-k3: Move MSMC fixup to SoC level") Signed-off-by: Emanuele Ghidoli <[email protected]> Signed-off-by: Francesco Dolcini <[email protected]>
2023-07-21arm: dts: Fix build of am62a7 dtbsNishanth Menon
am62a7 should be built with CONFIG_SOC_K3_AM62A7 not CONFIG_SOC_K3_AM625 Fixes: 6bdfa69155d8 ("arm: dts: introduce am62a7 u-boot dtbs") Cc: Bryan Brattlof <[email protected]> Cc: Vignesh Raghavendra <[email protected]> Cc: Francesco Dolcini <[email protected]> Cc: Sjoerd Simons <[email protected]> Cc: Wadim Egorov <[email protected]> Reviewed-by: Bryan Brattlof <[email protected]> Reviewed-by: Mattijs Korpershoek <[email protected]> Signed-off-by: Nishanth Menon <[email protected]>
2023-07-21arm: mach-k3: *: dev-data: Update to use ARRAY_SIZENishanth Menon
Instead of hard-coding the count of entries manually, use ARRAY_SIZE to keep the count updates appropriately. Cc: Bryan Brattlof <[email protected]> Suggested-by: Ravi Gunasekaran <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Bryan Brattlof <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]>
2023-07-21arm: mach-k3: am62a7_init: Open up FSS_DAT_REG3 firewallVignesh Raghavendra
On security enforced (HS-SE) devices ROM firewalls OSPI data region3 that is present in above 64bit region. Open this up in bootloader to allow Linux to access OSPI flashes in mmap mode. Without this kernel will crash when accessing this region due to firewall violations on HS-SE devices. Signed-off-by: Vignesh Raghavendra <[email protected]>
2023-07-21common: splash_source: Fix type casting errorsNikhil M Jain
During compilation splash_source puts out below warning for type conversion in splash_load_fit for bmp_load_addr and fit_header. Change their type to uintptr_t to fix the warnings. common/splash_source.c: In function ‘splash_load_fit’: common/splash_source.c:366:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 366 | img_header = (struct legacy_img_hdr *)bmp_load_addr; | ^ common/splash_source.c:376:49: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 376 | res = splash_storage_read_raw(location, (u32)fit_header, fit_size); | ^ common/splash_source.c:401:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 401 | memmove((void *)bmp_load_addr, internal_splash_data, internal_splash_size); The above warnings are generated if CONFIG_FIT is enabled. Signed-off-by: Nikhil M Jain <[email protected]>
2023-07-21board: ti: am62x: evm: Include necessary header filesNikhil M Jain
At the time of compilation evm.c gives below warning for implicit declaration of enable_caches, to mitigate this include cpu_func.h. board/ti/am62x/evm.c: In function ‘spl_board_init’: board/ti/am62x/evm.c:90:9: warning: implicit declaration of function ‘enable_caches’ [-Wimplicit-function-declaration] 90 | enable_caches(); Signed-off-by: Nikhil M Jain <[email protected]>
2023-07-21Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini
For once this adds USB support for two SoCs: the H616 and the F1C100s series. The rest is support for LPDDR3 DRAM chips on H616 boards. Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s board. I don't have an H616 board with LPDDR3 DRAM, but reportedly that works for Mikhail, and doesn't regress on my DDR3 boards.
2023-07-21Merge tag 'xilinx-for-v2023.10-rc1-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.10-rc1 v2 axi_emac: - Change return value if RX packet is not ready cadence_qspi: - Enable flash reset for Versal NET dt: - Various DT syncups with Linux kernel - SOM - reserved pmufw memory location fpga: - Add load event mtd: - Add missing dependency for FLASH_CFI_MTD spi/nand: - Minor cleanup in Xilinx drivers versal-net: - Prioritize boot device in boot_targets - Wire mini ospi/qspi/emmc configurations watchdog: - Use new versal-wwdt property xilinx: - fix sparse warnings in various places ps7_init* - add missing headers - consolidate code around zynqmp_mmio_read/write - switch to amd.com email zynqmp_clk: - Add handling for gem rx/tsu clocks zynq_gem: - Configure mdio clock at run time zynq: - Enable fdt overlay support zynq_sdhci: - Call dll reset only for ZynqMP SOCs
2023-07-21event: Add fpga load eventChristian Taedcke
This enables implementing custom logic after a bitstream was loaded into the fpga. Signed-off-by: Christian Taedcke <[email protected]> Reviewed-by: Simon Glass <[email protected]> Reviewed-by: Tom Rini <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21clk: zynqmp: Add gem rx and tsu clocks to return registerAshok Reddy Soma
Add gem_tsu and gem0_rx till gem3_rx to return proper register from zynqmp_clk_get_register. Otherwise firmware won't be able to set clock for these due to incorrect register address. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21clk: zynqmp: Add set_rate support for gem rx and tsu clksAshok Reddy Soma
gem0_rx till gem3_rx and gem_tsu are missing from set rate function. Add them, so that they can be set from pmu firmware via clock framework. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21net: axi_emac: Change return value to -EAGAIN if RX is not readyMaksim Kiselev
If there is no incoming package than axiemac_recv will return -1 which in turn leads to printing `eth_rx: recv() returned error -1` error message in eth_rx function. But missing a package is not an fatal error, so return -EAGAIN in that case would be more suitable. Signed-off-by: Maksim Kiselev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21arm64: zynqmp: Remove clock-names from pcap nodeMichal Simek
Clock is not used in driver and also not described in binding. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/0a0fa0ba197fa4051a2c8a24e1451cefadce7517.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Rename ams_ps/pl node namesMichal Simek
Fix child node names to be aligned with dt-binding available in the Linux kernel which requires names as ams-ps@ and ams-pl@. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/8f1451d614f654cb0d0da1e799e876c078fbf2c9.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Remove interrupt/reg-names for AMSMichal Simek
These two properties are not described in DT binding and also not used by driver that's why remove them. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/b123c7e537dcf70802e828bbcd484a761a264186.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usbPiyush Mehta
To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk' quirk for usb. This quirk is no more available in linux after the xilinx release 2022.2. This functionality is taken care of by the 'snps,resume-hs-terminations' quirk. Signed-off-by: Piyush Mehta <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/4b7a132116bf0248cdb558e04de3b06b412c4a0f.1688992653.git.michal.simek@amd.com
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