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Add npcm8xx A2 cpu version check
and add 4G RAM support
Signed-off-by: Jim Liu <[email protected]>
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configuration should be done before release host wait
Signed-off-by: Jim Liu <[email protected]>
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In non tip mode, BMC first power on with PORST+CORST.
the gpio status will error.
Signed-off-by: Jim Liu <[email protected]>
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use new memory layout and change uboot load address.
open tpm, tee and more config feature
No need to reserve top memory because the reserved space
is moved to the bottom area of memory.
Signed-off-by: Jim Liu <[email protected]>
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Signed-off-by: Jim Liu <[email protected]>
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The SHA and OTP should under the ahb node
Signed-off-by: Jim Liu <[email protected]>
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add console and mem env to boot to linux kernel
Signed-off-by: Jim Liu <[email protected]>
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Enable FIT and SHA config to decompress the kernel image
Signed-off-by: Jim Liu <[email protected]>
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Use proper register base and access method to access GRF registers.
GRF registers start at a completely different base, and need special
access method, that sets the change mask in the 16 MSBs.
Signed-off-by: Ondrej Jirman <[email protected]>
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If phy is not defined in DT (eg. on rk3399), generic_phy_get_by_name
will return -ENODATA. Handle that case correctly.
Signed-off-by: Ondrej Jirman <[email protected]>
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pllref_clk is unused after being retrieved. fin needs to be set
to dsi->ref clock's rate for the following calculation to work.
Otherwise fin is undefined, and calculation return bogus number
based on undefined variable.
Signed-off-by: Ondrej Jirman <[email protected]>
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ret is undefined if external phy is not used resulting in bogus
error being returned in that scenario.
Signed-off-by: Ondrej Jirman <[email protected]>
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Wrong return codes were checked in several places. Check the proper ones.
Signed-off-by: Ondrej Jirman <[email protected]>
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&priv->phy is always true. Compiler warns about this loudly.
Use a propper check for phy device allocation. Without this fix
using this driver with SoC that doesn't use external phy (eg. RK3399)
doesn't work.
Signed-off-by: Ondrej Jirman <[email protected]>
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These must be read from timings->flags, like other DSI HOST drivers do.
And they must not be inverted either. Low means low.
Without this fix, panel drivers that set *SYNC_LOW produce corrupted
output on screen (shifted horizontally and vertically by back porch
distance).
Signed-off-by: Ondrej Jirman <[email protected]>
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Fix confusing use of indentation.
Signed-off-by: Ondrej Jirman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The intermediate value could overflow for large periods and levels.
Signed-off-by: Matthias Schiffer <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The driver is for panels based on the Himax HX8394 controller, such as the
HannStar HSD060BHW4 720x1440 TFT LCD panel that uses a MIPI-DSI interface.
This panel is used in Pinephone Pro.
Signed-off-by: Ondrej Jirman <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
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Some callers expect to call this with NULL font name to select the
default font (eg. boot/scene.c). Without handling the NULL condition
U-Boot crashes instead of displaying a bootflow GUI menu.
Signed-off-by: Ondrej Jirman <[email protected]>
Cc: Anatolij Gustschin <[email protected]>
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- Add xtxtech spi-nor chip parts (Bruce Suen)
- Add bcm63xx-hsspi driver fixes (William Zhang)
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- mvebu: Thecus: Misc enhancement and cleanup (Tony)
- mvebu: Add AC5X Allied Telesis x240 board support incl NAND
controller enhancements for this SoC (Chris)
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20230713
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Merge for 2023.10.
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888
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The sar-reg0 alias was left over from an earlier iteration of the
patches adding support for this board. Remove the unused alias.
Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board")
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The x240 and SE240 are a series of L2+ switches from Allied Telesis.
There are a number of them in the range but as far as U-Boot is
concerned all the CPU block components are the same so there's only one
board defined.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Currently, a random MAC address is assigned to eth1 in Linux.
Fix this behavor by retrieving the second MAC address from the fuses.
Signed-off-by: Fabio Estevam <[email protected]>
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With LTO enabled, SPL shrinks about 10K and U-Boot shrinks
about 30K.
Signed-off-by: Adam Ford <[email protected]>
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On the XEA (imx287) system the FAT file system is not used neither in
SPL nor u-boot proper.
Hence, to save ~6KiB of u-boot.img size - it has been disabled.
Signed-off-by: Lukasz Majewski <[email protected]>
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The XEA system (imx287 based) is not using support for EXTLINUX and VBE.
As those configuration options have been enabled by default with modern
Kconfig it is safe to explicitly disable them.
After that change the u-boot.img size has been reduced by ~16 KiB.
Signed-off-by: Lukasz Majewski <[email protected]>
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The conversion to CONFIG_DM_SERIAL is mandatory, so select this option.
Signed-off-by: Fabio Estevam <[email protected]>
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The conversion to CONFIG_DM_SERIAL is mandatory, so select this option.
Signed-off-by: Fabio Estevam <[email protected]>
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The conversion to CONFIG_DM_SERIAL is mandatory, so select this option.
Signed-off-by: Fabio Estevam <[email protected]>
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Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal
may be used to control some power-rails on the carrier board, therefore
it should be set to high when the module is booting.
To do this as early as possible is generally a good idea and the issue
was noticed on the Yavia carrier board where it is needed to power the
I2C EEPROM on the carrier board.
Signed-off-by: Andrejs Cainikovs <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
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Enable CONFIG_SPL_GPIO_HOG option to be able to control GPIO hogs from
SPL.
Signed-off-by: Andrejs Cainikovs <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
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Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal
may be used to control some power-rails on the carrier board, therefore
it should be set to high when the module is booting.
To do this as early as possible is generally a good idea and the issue
was noticed on the Yavia carrier board where it is needed to power the
I2C EEPROM on the carrier board.
Signed-off-by: Andrejs Cainikovs <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
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Enable CONFIG_SPL_GPIO_HOG option to be able to control GPIO hogs from
SPL.
Signed-off-by: Andrejs Cainikovs <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
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Synchronise device trees with linux v6.5-rc1.
Signed-off-by: Marcel Ziswiler <[email protected]>
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The USB Power domains should not have been removed as it causes
the board to hang if the USB is started.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Several changes have been made to the device tree
in the kernel, so update that as well as the
corresponding imx8mp-u-boot.dtsi files to prevent
breaking the booting.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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There are some newer clocks added to the kernel recently,
so to fix prepare for resycing the device trees, update
the clock list. Since there are some minor changes to
the USB clocks, update which USB clocks are enabled
to match with the upstream kernel as well.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Tested-by: Tim Harvey <[email protected]> #imx8mp-venice-gw74xx
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Initialize Secure Non-Volatile Storage, aka SNVS.
Signed-off-by: Andrejs Cainikovs <[email protected]>
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For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.
For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.
The hardware configuration (EC) is determined at runtime by
reading from the SOM EEPROM.
To support both hardware configurations (EC and non-EC), adjust/fix
the PHY reset gpios according to the hardware configuration
read at runtime from the SOM EEPROM. This adjustement is done in
U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.
Signed-off-by: Hugo Villeneuve <[email protected]>
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In case the i.MX8M Plus starts from eMMC BOOT1/BOOT2 HW partitions, the
flash.bin container is stored at offset 0 from the start, that means the
fitImage itb is at offset 0x2c0 instead of 0x300 sectors from the start.
Handle this difference in custom spl_mmc_get_uboot_raw_sector() .
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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iMX93 ADC features:
- 4 channels
- 12 bit resolution
Signed-off-by: Luca Ellero <[email protected]>
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This commit adds driver for iMX93 ADC.
The driver is implemented using driver model and provides
ADC uclass's methods for ADC single channel operations:
- adc_start_channel()
- adc_channel_data()
- adc_stop()
ADC features:
- channels: 4
- resolution: 12-bit
Signed-off-by: Luca Ellero <[email protected]>
Reviewed-by: Haibo Chen <[email protected]>
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Bitwise operations on signed integers are not defined,
replace them with per-call checks.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Heiko Schocher <[email protected]>
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In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and
SPL_CRYPTO should be enabled in Kconfig like other i.MX8M
boards.
This also needs to occur in the SPL so enable CONFIG_SPL_BOARD_INIT and
add a void spl_board_init function which calls arch_misc_init to probe
the CAAM driver.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Switch to a 2-bank dram config to properly support 4GiB.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Update RAM Timings for 2GB RAM based on DDR Controller Configuration
Spreadsheet revision 22. Including the update of the refresh
rate to workaround errata ERR050805.
Signed-off-by: Cem Tenruh <[email protected]>
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The csf_spl.txt and csf_fit.txt templates contain file paths which must
be edited for the location of your NXP CST generated key files.
Streamline the process of signing an image by assigning unique var names
to these which can be expended from env variables in the csf.sh script.
The following vars are used:
SRK_TABLE - full path to SRK_1_2_3_4_table.bin
CSF_KEY - full path to the CSF Key CSF1_1_sha256_4096_65537_v3_usr_crt.pem
IMG_KEY - full path to the IMG Key IMG1_1_sha256_4096_65537_v3_usr_crt.pem
Additionally provide an example of running the csf.sh script.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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The sec_in32 preprocessor is defined as follows in include/fsl_sec.h file:
When address "a" is calculated using math for ex: addition of base address and
an offset, then casting is applied only to the first address which in this
example is base address.
caam_ccbvid_reg = sec_in32(CONFIG_SYS_FSL_SEC_ADDR + CAAM_CCBVID_OFFSET)
resolves to:
caam_ccbvid_reg = in_le32((ulong *)(ulong)CONFIG_SYS_FSL_SEC_ADDR +
CAAM_CCBVID_OFFSET)
instead it should resolve to:
caam_ccbvid_reg = in_le32((ulong *)(ulong)(CONFIG_SYS_FSL_SEC_ADDR +
CAAM_CCBVID_OFFSET))
Thus add parenthesis around the address "a" so that however the address is
calculated, the casting is applied to the final calculated address.
Reviewed-by: Horia Geanta <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Utkarsh Gupta <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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