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Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.
Signed-off-by: Peng Fan <[email protected]>
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Upgrade SCFW API to 1.16
Add more APIs:
sc_misc_get_button_status
sc_pm_reboot
sc_seco_v2x_build_info
Signed-off-by: Peng Fan <[email protected]>
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The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan <[email protected]>
Tested-by: Oliver Graute <[email protected]>
Reviewed-by: Oliver Graute <[email protected]>
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The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan <[email protected]>
Tested-by: Oliver Graute <[email protected]>
Reviewed-by: Oliver Graute <[email protected]>
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The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan <[email protected]>
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The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan <[email protected]>
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The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan <[email protected]>
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The return value is int type, not sc_err_t(u8), correct the usage.
Signed-off-by: Peng Fan <[email protected]>
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Enable LTO for binary size reduction.
Signed-off-by: Teresa Remmet <[email protected]>
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Enable LTO for binary size reduction.
Signed-off-by: Teresa Remmet <[email protected]>
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Running a memtest in U-Boot and Linux shows that some Colibri iMX6
produce bitflips at temperatures above 60°C. This happens because the
RALAT and WALAT values on the Colibri iMX6 are too low. The problems
were introduced by commit 09dbac8174c4 ("mx6: ddr: Restore ralat/walat
in write level calibration") before the calibration process overwrote
the values and set them to the maximum value. With this commit, we make
sure that the RALAT and WALAT values are set to the maximum values
again. This has been proven to work for years.
Fixes: 09dbac8174c4 ("mx6: ddr: Restore ralat/walat in write level calibration")
Signed-off-by: Stefan Eichenberger <[email protected]>
Signed-off-by: Francesco Dolcini <[email protected]>
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Add documentation on how to build a bootable U-Boot image for the PHYTEC
phyCORE-i.MX 8M Plus.
Signed-off-by: Yannic Moog <[email protected]>
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Add documentation on how to build a bootable U-Boot image for the PHYTEC
phyCORE-i.MX 8M Mini.
Signed-off-by: Yannic Moog <[email protected]>
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As the serial devices are configured in the device tree, enable
DM_SERIAL in the non-SPL T1024RDB defconfigs.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all". Add these u-boot specific properties
to an *-u-boot.dtsi file.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the serial node descriptions similar to Linux v6.4 for the
t1024rdb board and its dependencies.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The serial clock is provided by the get_serial_clock() callback on PPC
under DM_SERIAL. Use the same method to compute the clock as for
non-DM_SERIAL use cases.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Call pci_init() to force PCI enumeration at probe time.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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As the serial devices are configured in the device tree, enable
DM_SERIAL in the non-SPL T1042D4RDB defconfigs.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all". Add these u-boot specific properties
to an *-u-boot.dtsi file.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the serial node descriptions similar to Linux v6.4 for the
t1042d4rdb board and its dependencies.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The serial clock is provided by the get_serial_clock() callback on PPC
under DM_SERIAL. Use the same method to compute the clock as for
non-DM_SERIAL use cases.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Call pci_init() to force PCI enumeration at probe time.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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As the serial devices are configured in the device tree, enable
DM_SERIAL in the non-SPL T4240RDB defconfig.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all". Add these u-boot specific properties
to an *-u-boot.dtsi file.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the serial node descriptions similar to Linux v6.4 for the t4240rdb
board and its dependencies.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The serial clock is provided by the get_serial_clock() callback on PPC
under DM_SERIAL. Use the same method to compute the clock as for
non-DM_SERIAL use cases.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Call pci_init() to force PCI enumeration at probe time.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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As the serial devices are configured in the device tree, enable
DM_SERIAL in the non-SPL T2080RDB defconfigs.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all". Add these u-boot specific properties
to an *-u-boot.dtsi file.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add the serial node descriptions similar to Linux v6.4 for the t2080rdb
board and its dependencies.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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The serial clock is provided by the get_serial_clock() callback on PPC
under DM_SERIAL. Use the same method to compute the clock as for
non-DM_SERIAL use cases.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Call pci_init() to force PCI enumeration at probe time.
Signed-off-by: Camelia Groza <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
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Add support for Winbond 256M-bit flash w25q256jwm.
Performed basic erase/write/readback operations on
ZynqMP zc1751+dc1 board.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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If cs gpio is requested with ACTIVE_HIGH flag, it will
be pulled low(i.e. active). This is not what we expected.
Signed-off-by: Jim Liu <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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add following XTX part numbers to the list:
xt25f08: 3V QSPI, 8Mbit
xt25f16: 3V QSPI, 16Mbit
xt25f32: 3V QSPI, 32Mbit
xt25f64: 3V QSPI, 64Mbit
xt25f128: 3V QSPI, 128Mbit
xt25f256: 3V QSPI, 256Mbit
xt25q08: 1.8V QSPI, 8Mbit
xt25q16: 1.8V QSPI, 16Mbit
xt25q32: 1.8V QSPI, 32Mbit
xt25q64: 1.8V QSPI, 64Mbit
xt25q128: 1.8V QSPI, 128Mbit
xt25q256: 1.8V QSPI, 256Mbit
xt25q512: 1.8V QSPI, 512Mbit
xt25q01g: 1.8V QSPI, 1Gbit
xt25w512: wide voltage, QSPI, 512Mbit
xt25w01g: wide voltage, QSPI, 1Gbit
remove xt25f128b and add xt25f128,because xt25f128b andxt25f128f
share same jdec id,we use xt25f128 instead.
Signed-off-by: Bruce Suen <[email protected]>
[jagan: re-edited the entire patch]
Signed-off-by: Jagan Teki <[email protected]>
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XTX changed full company name from "XTX Technology (Shenzhen) Limited
to "XTX Technology Limited" since 2020,So remove "(Shenzhen)".
Signed-off-by: Bruce Suen <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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According to Documentation/devicetree/bindings/spi/spi-gpio.yaml
from Linux, the recommended spio-gpio properties are:
sck-gpios, miso-gpios and mosi-gpios.
gpio-sck, gpio-mosi and gpio-miso are considered deprecated.
Update the bindings to suggest the recommeded properties.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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According to Documentation/devicetree/bindings/spi/spi-gpio.yaml
from Linux, the recommended spio-gpio properties are:
sck-gpios, miso-gpios and mosi-gpios.
gpio-sck, gpio-mosi and gpio-miso are considered deprecated.
Currently, U-Boot only supports the deprecated properties.
Allow the soft_spi driver to support both the new and old properties.
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Bring the device tree binding document from Linux to u-boot
Port from linux patches:
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Current code expects that SPI_TX_BYTE is single bit mode
but it is wrong. It indicates byte program mode,
not single bit mode.
If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set,
the default transfer bus width is single bit.
Signed-off-by: Masahisa Kojima <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an
updated SPI controller that add the capability to allow the driver to
control chip select explicitly. Driver can control and keep cs low
between the transfers natively. Hence the dummy cs workaround or prepend
mode found in the bcm63xx-hsspi driver are no longer needed and this new
driver is much cleaner.
Port from linux patch:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Due to the controller limitation to keep the chip select low during the
bus idle time between the transfer, a dummy cs workaround was used when
this driver was first upstreamed to the u-boot based on linux kernel
driver. It basically picks the dummy cs as !actual_cs so typically dummy
cs is 1 when most of the case only cs 0 is used in the board design.
Then invert the polarity of both cs and tell the controller to start the
transfers using dummy cs. Assuming both cs are active low before the
inversion, effectively this keeps dummy cs high and actual cs low during
the transfer and workaround the issue.
This workaround requires that dummy cs 1 pin to is set to SPI chip
selection function in the pinmux when the transfer clock is above 25MHz.
The old chips likely have default pinmux set to chip select on the dummy
cs pin so it works but this is not case for the new Broadband BCA chips
and this workaround stop working. This is specifically an issue to
support SPI NAND and SPI NOR flash because these flash devices can
typically run at or above 100MHz.
This patch utilizes the prepend feature of the controller to combine the
multiple transfers in the same message to a single transfer when
possible. This way there is no need to keep clock low between transfers
and solve the issue without any pinmux requirement.
Multiple transfers within a SPI message may be combined into one
transfer if the following are all true:
* One or more half duplex write transfer in single bit mode
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
Most of the SPI device meets this requirements such as SPI NOR, SPI NAND
flash, Broadcom SPI voice card and etc. So this change switches to the
prepend mode as the default mode. For any SPI message that does not meet
the above requirement, we switch to original dummy cs mode but limit the
clock rate to the safe 25MHz.
Port from linux patch:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Acked-by: Jagan Teki <[email protected]>
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New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on
dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support
this new binding.
Port from linux patch:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch:
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC
for common features and IP blocks. Use this config instead of each chip
config as the Kconfig dependency for Broadcom HSSPI driver.
Signed-off-by: William Zhang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add support for an optional external chip-select gpio.
Signed-off-by: Lukas Funke <[email protected]>
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Remove the platform data header because its content is only used by the
driver.
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Rename the flush function into pl022_spi_flush to avoid conflicting
types with previous declaration of the function in stdio.h header.
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Align the compatible property with the kernel device tree binding [1]
by removing the '-spi' suffix.
[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/spi/spi-pl022.yaml
Signed-off-by: Lukas Funke <[email protected]>
Signed-off-by: Stefan Herbrechtsmeier <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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