| Age | Commit message (Collapse) | Author |
|---|
|
In order to better compare the Linux rk3288.dtsi version
with the U-Boot version move the io-domains nodes.
Signed-off-by: Johan Jonker <[email protected]>
Reviewed-by: John Keeping <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]> # chromebook-jerry
Reviewed-by: Kever Yang <[email protected]>
|
|
Add support for Rockchip rk3588 variant of pinctrl.
The driver is adapted from the Linux driver.
Signed-off-by: Jianqun Xu <[email protected]>
[[email protected]:
port to latest U-boot, bring more changes from Linux
use translated pull values table]
Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Tested-by: Jonas Karlman <[email protected]>
Reviewed-by: Jonas Karlman <[email protected]>
|
|
ft_board_setup() should be availble for use in board files but using it
in the rk3288 machine file blocks this functionality.
ft_system_setup() is the more appropriate function to use in a machine
definition.
Signed-off-by: John Keeping <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
There is no support to initialize DRAM on RK3588 SoCs using U-Boot TPL
and instead an external TPL binary must be used to generate a bootable
u-boot-rockchip.bin image.
Enable ROCKCHIP_EXTERNAL_TPL by default for RK3588, add build steps for
RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for
rockchip and also a reference board for board vendors.
Hardware:
SoC: RK3588
DRAM: LPDDR4X 8GB
Debug: UART2 via USB
PCIe: 3x4 *1
SATA *2
HDMI out *2
HDMI IN *1
USB2.0 Host *2
USB3.0 Host *1
Type C *1
MIPI DSI panel
dts Sync from Linux v6.2.
Signed-off-by: Kever Yang <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
|
|
Instead of letting the compiler error out if CONFIG_ENV_IS_NOWHERE is
not selected by the user, let's just enforce it when the user builds for
Ringneck PX30 so that no check needs to be performed by the compiler and
the configuration is always valid.
Suggested-by: Tom Rini <[email protected]>
Cc: Quentin Schulz <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
Instead of letting the compiler error out if CONFIG_ENV_IS_NOWHERE is
not selected by the user, let's just enforce it when the user builds for
Puma RK3399 so that no check needs to be performed by the compiler and
the configuration is always valid.
Suggested-by: Tom Rini <[email protected]>
Cc: Quentin Schulz <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.
Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.
Fix it by using MAX(mmc->tran_speed, mmc->clock)
Signed-off-by: Vasily Khoruzhick <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
|
|
When a structure contains a flexible array member, it is not supposed to be
included in arrays or other structs.
Quoting the C spec [0]
"Such a structure (and any union containing, possibly recursively, a
member that is such a structure) shall not be a member of a structure
or an element of an array."
IOW efi_hii_keyboard_layout should not include
struct efi_key_descriptor descriptors[]; since we use it at the
declaration of struct efi_hii_keyboard_package.
[0] https://www.dii.uchile.cl/~daespino/files/Iso_C_1999_definition.pdf
chapter 6.7.2.1
Signed-off-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
|
|
We cannot use old_dtb in the finally block if it has not been assigned
before the try block.
test/py/tests/test_efi_fit.py:458:30:
E0601: Using variable 'old_dtb' before assignment (used-before-assignment)
Fixes: 8391f955494e ("test/py: Create a test for launching UEFI binaries from FIT images")
Signed-off-by: Heinrich Schuchardt <[email protected]>
|
|
Without CONFIG_EFI_CAPSULE_AUTHENTICATE=y the following tests are skipped:
* test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py
* test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py
Signed-off-by: Heinrich Schuchardt <[email protected]>
Acked-by: Ilias Apalodimas <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Fix pylint warnings like:
* Class inherits from object
* Missing module description
* Missing class description
* First line of comment blank
* Superfluous imports
Signed-off-by: Heinrich Schuchardt <[email protected]>
|
|
Remove an unused implementation of efi_capsule_authenticate().
Signed-off-by: Heinrich Schuchardt <[email protected]>
|
|
Indicate that we follow PEP8 and PEP257.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
|
|
Add flags to tell objcopy what kind of ELF to create.
Signed-off-by: Samuel Holland <[email protected]>
|
|
Some sections in the linker scripts are aligned to 4 bytes, which
may cause misaligned exception on some platforms, e.g.: clearing
the bss section on 64-bit hardware if __bss_start does not start
from a naturally 8 bytes aligned address.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
U-Boot SPL is not relocable. Drop these relocation sections.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
board_init_r does not return for U-Boot SPL hence there is no need
to update the link register when jumping to board_init_r.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
The codes currently skip the very first relocation entry, and have
an inaccurate comment "skip first reserved entry" indicating that
the first entry is reserved, but later it references the elements
in the first relocation entry using a minus offset.
Change to use a positive offset so that there is no need to skip
the first relocation entry.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
The argv[2] is never used in prelink-riscv. Drop it.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
The codes forget to call munmap() to unmap the ELF image that was
mapped by previous mmap().
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
Some coding convention fixes.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
't5' already contains relocation type so don't bother reloading it.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
The __bss_start is the source end address hence load its address
directly into register 't2' for optimization.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
Since commit 409e4b547872 ("Makefile: Enforce DWARF4 output") the
whole U-Boot build switched to enforce DWARF4 output, but RISC-V
is still on its own setting. Let's switch to use U-Boot's setting.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
|
|
Replace NDS32 with RISC-V in the comments.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
|
|
This is the initial basic config for StarFive VisionFive v2 board. It
includes consol, Norflash, sdio, ddr etc.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add initial device tree for StarFive VisionFive v2 board.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add initial u-boot device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add initial device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add Kconfig to select the basic functions for StarFive VisionFive v2 Board.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add Kconfig to select the basic functions for StarFive JH7110 SoC.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add board support for StarFive VisionFive v2.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add driver for StarFive JH7110 to support ddr initialization in SPL.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add pinctrl driver for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add pinctrl definitions for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add a DM clock driver for StarFive JH7110 SoC.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add all clock outputs for the StarFive JH7110 clock generator.
Signed-off-by: Yanhong Wang <[email protected]>
Acked-by: Sean Anderson <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add a DM reset driver for StarFive JH7110 SoC.
Note that the register base address of reset controller is the
same with the clock controller. Therefore, there is no device
tree node alone for reset driver.It binds device node in
the clock driver
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add resets for the StarFive JH7110 system(SYS),system-top-group(STG) and
always-on(AON) reset controller.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
This adds support for the StarFive JH7110 SoC which also
feature this SiFive cache controller.
Signed-off-by: Yanhong Wang <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
Add StarFive JH7110 SoC to support RISC-V arch.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Tested-by: Conor Dooley <[email protected]>
|
|
With some USB devices connected on USB HUB for the STMicroelectronics
boards, set the usb_pgood_delay=2 is not enough to ensure a correct
detection for all cases; but it is solved with USB_HUB_DEBOUNCE_TIMEOUT=2s.
For example, issue encountered with the USB flash disk:
ID 058f:6387 Alcor Micro Corp. Flash Drive
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
|
|
In all these cases, the index on the LHS is immediately afterwards
used to access the array appearing in the ARRAY_SIZE() on the RHS - so
if that index is equal to the array size, we'll access
one-past-the-end of the array.
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
|
|
Remove the EDO mode support from as the FMC2 controller does not
support the feature.
Signed-off-by: Christophe Kerello <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
|
|
Add FMC support on STM32MP13x SoC family.
Signed-off-by: Christophe Kerello <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
|
|
The early malloc usage increased so the associated defined
CONFIG_SYS_MALLOC_F_LEN need to be increased.
For example, for stm32mp15_defconfig and
stm32mp157c-dk2-scmi.dtsi, we have:
Early malloc usage: 280b8 / 80000
Signed-off-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
|
|
Currently, in stm32_qspi_claim_bus(), QSPI_CR and QSPI_DCR registers
are saved in stm32_ospi_flash struct on first flash memory initialization
and restored on each flash accesses.
As the logic of spi-uclass.c changed since 'commit 741280e9accd
("spi: spi-uclass: Fix spi_claim_bus() speed/mode setup logic")'
set_speed() and set_mode() callbacks are called systematically when bus
speed or bus mode need to be updated, QSPI_CR and QSPI_DCR registers are
set accordingly.
So stm32_qspi_claim_bus() can be updated by removing QSPI_CR and QSPI_DCR
save/restore code and struct stm32_ospi_flash can be removed as well.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
|
|
Add QSPI support on STM32MP13x SoC family
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
|
