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If strdup call fails, one needs to free priv variable.
Signed-off-by: Francois Berder <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Link: https://lore.kernel.org/r/BESP194MB28052734FD0361EA602F6360DA8FA@BESP194MB2805.EURP194.PROD.OUTLOOK.COM
Signed-off-by: Mattijs Korpershoek <[email protected]>
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A lot of things can go wrong while parsing dfu_alt_info. Make sure to
pass the real error codes all the way up instead of replacing them with
an unhelpful -1.
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.
Signed-off-by: Balaji Selvanathan <[email protected]>
Link: https://patch.msgid.link/[email protected]
[casey: indentation fix]
Signed-off-by: Casey Connolly <[email protected]>
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Add clock gate definitions and entries for QUP (Qualcomm Universal
Peripheral) serial engine clocks across all four wrappers on SA8775P.
This enables proper clock management for I2C, SPI, and UART
peripherals connected to the QUP blocks.
This resolves the "unknown clock ID 133" error for UART10 and
provides complete QUP clock infrastructure for the platform.
Signed-off-by: Swathi Tamilselvan <[email protected]>
Signed-off-by: Balaji Selvanathan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Introduce a fragment config for the Pixel 3, Pixel 3 XL, Pixel 5.
On these devices, U-Boot is chainloaded via fastboot. However, due to
additional requirements added by Google, the image header must have
a specific value for the text offset.
This is solved by setting CONFIG_TEXT_BASE to 0x80080000 in U-Boot.
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: David Heidelberg <[email protected]>
Reviewed-by: Petr Vorel <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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U-Boot does work on Qualcomm 845-based Pixel 3 and 3 XL.
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Signed-off-by: David Heidelberg <[email protected]>
Reviewed-by: Petr Vorel <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Currently we don't properly map between the regulator mode ID enum and
the appropriate register values in the mode map, as a result we always
unintentionally vote for retention mode if we actually attempt to set
it. In the set_mode path we did find the appropriate entry in the mode
map but we wrote the id instead of the register values. Clean this up
and properly map id -> mode and vice versa.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Make use of the new RPMh read support to fetch regulator values that may
have been voted on by a previous bootloader stage. This allows commands
like "regulator status" to report the actual votes programmed into
hardware (though not necessarily the actual states of the regulators
once the votes have been aggregated).
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Implement support for RPMh reads, these allow reading out the
current votes for RPMh controlled resources such as regulators and
interconnects.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Several bugs were discovered in the rpmh-rsc driver which collectively
meant we were never actually waiting for the TCS to flush, these were
likely missed because U-Boot runs single threaded and the RPMh had
typically processed the single command we sent by the time we went
to send the next one. However a future patch will implement rpmh read
support which requires us to properly wait for the RPMh command response
so we can return the value.
Fix these issues so we correctly ensure the TCS is done before
returning.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add some comments explaining a few of the RSC registers
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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If we don't reclaim and clear the IRQ bits, we might get a spurious
interrupt from this TCS in Linux:
WARNING: CPU: 0 PID: 0 at drivers/soc/qcom/rpmh-rsc.c:451 tcs_tx_done+0x98/0x270
...
Call trace:
tcs_tx_done+0x98/0x270 (P)
__handle_irq_event_percpu+0x60/0x220
handle_irq_event+0x54/0xc0
handle_fasteoi_irq+0xa8/0x1c0
handle_irq_desc+0x3c/0x68
generic_handle_domain_irq+0x24/0x40
gic_handle_irq+0x5c/0xd0
...
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Failing to enable clocks will lead to bus hangs and the board crashing
in some cases, let's actually deal with this error and fail probe rather than hoping the clocks are already enabled.
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add more clocks for UART2, i2c9 and a few others. This is enough to get
the rubikpi 3 working.
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The default value of CONFIG_FASTBOOT_BUF_ADDR is 0, which causes
NULL pointer dereference during fastboot commands when users dont
provide "-l" option in fastboot usb command.
Set it to safe and sufficiently large region in RAM
of the QCS615 and QCM6490 boards, to prevent crashes.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Varadarajan Narayanan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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PMIC Arbiter may expose multiple owned and non-owned APIDs per SID/PID.
- Keep current mapping if it is OWNED and a NON-OWNED appears.
- Always update when a NEW OWNED APID appears (make writable).
- If current is NON-OWNED and a new NON-OWNED appears, update to it
(remain read-only).
This avoids write-access violations when not using the newly discovered
owned channels.
Signed-off-by: Aswin Murugan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Qualcomm DTs are being updated to use a new format where the dwc3 glue
node and controller are combined into a single DT node. Update the fixup
code to handle this case.
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Introduce an SDHCI ops hook (config_dll) for MSM SDHCI and implement a
minimal DLL control routine that ensures the core DLL is disabled when
the bus clock is at or below 100 MHz. This approach mirrors the Linux
MSM SDHCI driver.
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Loic Poulain <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add support for configuring the SDCC1 apps clock on QCM2290 by introducing
a frequency table and enabling dynamic rate setting. Previously, the clock
was assumed to be fixed at 384 MHz by firmware, which limited flexibility
and correctness when selecting optimal rates for SD/MMC operations.
Suggested-by: Sumit Garg <[email protected]>
Signed-off-by: Loic Poulain <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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When 'max-clk' is not specified, the SDHCI core retrieves the base clock
from the SDHCI_CAPABILITIES register (bits [15:8]). However, this field
is unreliable on MSM SDHCI controllers, as noted by the Linux driver
using the SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN flag. In addition, the field
is only 8 bits wide and cannot represent base clocks above 255 MHz.
On platforms like Agatti/QCM2290, the firmware sets the SDHCI clock to
384 MHz, but the capabilities register reports 200 MHz. As a result,
the core calculates a divider of 4, producing a 96 MHz SDCLK instead of
the intended ~52 MHz. This overclocking can cause sporadic CRC errors
with certain eMMC.
To fix this, use the actual clock rate reported by the SDHCI core clock
instead of relying on the capabilities register for divider calculation.
Signed-off-by: Loic Poulain <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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This change is imported from Linux driver and tested with SM6125 SoC.
Note, the msm8996_phy_cfg struct is same as sdm660_phy_cfg but
qusb2_phy_cfg::se_clk_scheme_default differs only.
Signed-off-by: Biswapriyo Nath <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Adjust the debug UART clock frequency from 14745600 Hz to 7372800 Hz
for the QCS615 platform. This correction ensures proper UART
communication timing and resolves baud rate miscalculations
that affects early boot console output.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The power on function for the phy only deasserts the reset, so the phy
might be in a weird state that we don't clean up properly.
Assert the reset in probe() so that when we power on we will have the
phy in a clean state.
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Remove setting of fdt_high to ~0, which disables device tree relocation,
from the default environment. Doing so prevents U-Boot from correcting
problems such as having an unaligned device tree and leads to various
failure modes in the OS.
Signed-off-by: Tom Rini <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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host count
The SMEM driver was failing to resolve memory regions on some boards
because `dev_of_offset()` + `fdtdec_lookup_phandle()` did not yield a
valid DT node. Modernize the code to use driver-model/ofnode accessors
and make the probe robust for both DT styles (direct `reg` vs
`memory-region` phandle).
- qcom_smem_map_memory():
* Drop fdtdec path; use dev_read_phandle_with_args() +
ofnode_read_resource().
* Use dev_read_phandle_with_args() +
fnode_read_resource().
- qcom_smem_probe():
* Try dev_read_addr_size() first (map via <reg>), else fall back to
qcom_smem_map_memory() with "memory-region".
* Check "qcom,rpm-msg-ram" presence to add second region.
- Additionally, SMEM_HOST_COUNT is increased to support newer SMEM
versions that include more remote processors. This avoids failures
during processor ID checks.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Varadarajan Narayanan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Enable PINCTRL_QCOM_GENERIC config
The pinctrl drivers are now automatically enabled via Kconfig
defaults based on PINCTRL_QCOM_GENERIC, so explicit selection in the
defconfig is no longer needed.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Introduce a new Kconfig option PINCTRL_QCOM_GENERIC that, when selected,
enables all Qualcomm pinctrl drivers by default. This simplifies defconfigs
for platforms supporting multiple SoCs and avoids manual driver selection.
Individual drivers can still be disabled if required.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add pinctrl driver for QCS615. Driver code is based on the
similar U-Boot and Linux drivers.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Add the PM8150, PM8350, and PM7325 regulator data found on Qualcomm
platforms. These regulator tables are imported from the Linux driver
to enable support for these PMICs in U-Boot.
Signed-off-by: Aswin Murugan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Currently (since 2026.01-rc) on all SDM630/660 based devices this is
printed, after observing long boot delay (several seconds) before
executing preboot commands:
QCOM-FMP: Failed to find boot partition
find_target_partition() function incorrectly assumes that eMMC is always
at number 0. In general you can't rely on device numbering to determine if
particular block device is eMMC or SD-card, because it depends on how
aliases are defined in device tree "chosen" node. Some SoCs have MMC
numbers starting at 1, not 0; so mmc1 is eMMC, mmc2 is SD-card.
Make eMMC detection reliable by using IS_SD() macro from mmc.h header.
Using this method target boot partition can be found successfully.
With debug prints enabled, this is printed:
QCOM-FMP: skipped SD-Card (devnum 2)
QCOM-FMP: Capsule update target: boot (disk 1:60)
QCOM-FMP: DFU string: 'mmc 0=u-boot.bin part 1 60'
Without debug prints nothing is printed, no error about failure to find
boot partition.
Fixes: fe80a5f80095 ("mach-snapdragon: CapsuleUpdate: support all boot methods")
Signed-off-by: Alexey Minnekhanov <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Let's enable proper MMU page table protection to properly
protect write-protected and non-executable sections.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Link: https://patch.msgid.link/20251106-topic-snapdragron-en-pgprot-v1-1-d2b9e802230b@linaro.org
Signed-off-by: Casey Connolly <[email protected]>
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Correct ARCH_QCOM to ARCH_SNAPDRAGON as ARCH_QCOM is outdated/unused
config. Using ARCH_QCOM was causing USB fastboot mode to fail.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Acked-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The default value of CONFIG_FASTBOOT_BUF_ADDR is 0, which causes
NULL pointer dereference during fastboot commands.
Set it to 0xdb300000, a safe and sufficiently large region in RAM
of the QCS9100 board, to prevent crashes and ensure reliable
fastboot functionality.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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To align with the naming convention used for Qualcomm platforms in
U-Boot, renamed the defconfig file from qcs9100_defconfig to
qcom_qcs9100_defconfig.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Added delays before and after setting the PIPE_UTMI_CLK_SEL and
PIPE3_PHYSTATUS_SW bits in the Qscratch GENERAL_CFG register
during UTMI clock selection for DWC3 on Qualcomm platforms.
These delays help ensure proper timing and stability of the UTMI
clock switching sequence, potentially avoiding race conditions or
unstable PHY behavior during initialization.
Tested on platforms using Qscratch-based DWC3 PHY configuration.
This change is taken from this Linux kernel implementation:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/usb/dwc3/dwc3-qcom.c?id=a4333c3a6ba9ca9cff50a3c1d1bf193dc5489e1c
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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Added a check to ensure the requested timeout does not exceed the
hardware's maximum supported value. This prevents register overflow
and ensures watchdog reliability.
So, added a check in qcom_wdt_start() to ensure the requested timeout
does not exceed the hardware-supported maximum value. If the requested
value exceeds the maximum value, then the timeout is clamped
at maximum value.
The timeout is first converted to watchdog ticks and then compared
against QCOM_WDT_MAX_TIMEOUT. This helps prevent misconfiguration
and potential watchdog misbehavior due to overflow.
QCOM_WDT_MAX_TIMEOUT is set to 0xFFFFF, as Qualcomm SoCs typically
use 20 bits to store bark/bite timeout values.
This work builds upon the previous submission:
https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Gopinath Sekar <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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This patch is not as E Shattow authored it, but contains non-trivial
changes from Heinrich Schuchardt as well. The original author has
requested that this commit be reverted until the changes can be
committed showing which parts were authored by E Shattow and which by
Heinrich Schuchardt.
This reverts commit 4c105d2ae7b0f847668ff1ef6b410f63ab4290b7.
Signed-off-by: Tom Rini <[email protected]>
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Ported from the Mediatek SDK. The upstream Linux kernel also has the
same register map as the SDK.
Signed-off-by: Shiji Yang <[email protected]>
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Make crypt_compare() accessible from board-specific code
by removing its dependency on the autoboot feature.
Signed-off-by: Tomas Paukrt <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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The "fixed-layout" nvmem controller subnode used to be optional wrapper
around nvmem controller cells subnodes. The "fixed-layout" node is now
mandatory in most cases, but in order to support both recent and legacy
DTs, both variants have to be supported.
Implement support for the "fixed-layout" node in the most trivial manner,
check whether the nvmem cell supernode is compatible with "fixed-layout"
and if it is, proceed one level above it to find the nvmem controller.
Signed-off-by: Marek Vasut <[email protected]>
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Peripheral registers on MPC83xx-series chips are declared in
immap_83xx.h as a set of structs that ultimately fill the entire MMIO
space of 1 MiB. This patch introduces a compile-time check of the size
of each peripheral struct. The purpose of these checks is two-fold:
1. To quickly tell readers of the code the total size of each struct
2. To verify that the size does not change when a struct is edited
If the size of a peripheral struct were to change by a few bytes due
to an editing error, the result would be mayhem for all following
peripherals, because all offsets would shift by the amount of the error.
All new checks have been compile-tested.
Signed-off-by: J. Neuschäfer <[email protected]>
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This platform is unfortunately frequently very close to the binary
size limit. Currently it is so close that generic bug fixes can trigger
build failure. Remove the license command from the image as that frees
up nearly 7KiB of space.
Suggested-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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The AM571x SoC has 1 GB DDR space. As part of normal re-location process
U-Boot copies itself to the top of DDR bank. However, on HS devices, the
top 37 MB is used by PPA and is firewalled. This results in an exception
and the boot fails. Set CONFIG_SYS_MEM_TOP_HIDE to reserve the top 38 MB
memory (aligned to 2MB as per page size for ARM32) to fix the boot.
Note: This limitation does not exist for other AM57x devices, but this
config is applied in the common defconfig since adding a separate
defconfig only for AM571x is not justified. Losing 38MB of memory at the
bootloader stage on other devices is acceptable.
Signed-off-by: Beleswar Padhi <[email protected]>
Reviewed-by: Andrew Davis <[email protected]>
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David Lechner <[email protected]> says:
While trying to run the test suite for the first time, I encountered a
few minor issues. Here are a few patches to address them.
Link: https://lore.kernel.org/r/20260105-a-few-test-py-improvements-v3-0-fea38243ca5b@baylibre.com
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Add a requirements.txt file to the pylibfdt script directory to specify
setuptools as a dependency. This follows the pattern of each tool in
U-Boot having its own requirements.txt file. The version is set to
78.1.1 to avoid conflict with the same in tools/patman/requirements.txt.
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Mattijs Korpershoek <[email protected]> # sandbox
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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Add a paragraph explaining that in addition to the requirements.txt
for test/py/test.py itself, users may need to install additional python
packages depending on the U-Boot configuration being built.
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Mattijs Korpershoek <[email protected]> # sandbox
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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Set ubconfig to None and add a check in the show_timings() function of
test/py/test.py to ensure that the global ubconfig variable was actually
initialized before access attributes.
If tests fail early, e.g. because --build failed, ubconfig may not have
been initialized yet and results in an exception in an atexit handler.
Adding this check avoids unnecessary noise in the output.
Exception ignored in atexit callback: <function cleanup at 0x7de475ea6b60>
Traceback (most recent call last):
File "u-boot/test/py/conftest.py", line 669, in cleanup
show_timings()
File "u-boot/test/py/conftest.py", line 616, in show_timings
if ubconfig.timing:
^^^^^^^^
NameError: name 'ubconfig' is not defined
Tested-by: Mattijs Korpershoek <[email protected]> # sandbox
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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David Lechner <[email protected]> says:
MT8365 has different pinctrl register layout compared to other SoCs in
the family, so needs its own driver.
This is also the first SoC in this family supported in U-Boot using an
upstream devicetree that has the mediatek,pctl-regmap property, so we
need to add support for that to the common mediatek pinctrl code first.
Link: https://lore.kernel.org/r/[email protected]
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Enable PINCTRL, PINCONF and the SoC-specific driver for MediaTek MT8365
EVK.
Signed-off-by: David Lechner <[email protected]>
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Add pinctrl support for MT8365 SoC.
Signed-off-by: Julien Masson <[email protected]>
Signed-off-by: Vitor Sato Eschholz <[email protected]>
Signed-off-by: David Lechner <[email protected]>
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