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Andrew Goodbody <[email protected]> says:
Smatch reported issues with two power drivers due to redundant code and
an unitialised variable.
Link: https://lore.kernel.org/r/[email protected]
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The MediaTek mt6323 power driver cannot build without access to some
platform specific header files. Express that requirements in Kconfig as
well.
Signed-off-by: Tom Rini <[email protected]>
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The commends in include/power/pmic.h say that once SPL_DM_PMIC exists we
should update things. This has been true for some time, so let us update
this to have the legacy portions in their own header, which should not
be directly included. This cleans up the logic within the file too
slightly.
Signed-off-by: Tom Rini <[email protected]>
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The POWER_LEGACY option functionally depends on not having DM_PMIC
enabled, so add that here.
Signed-off-by: Tom Rini <[email protected]>
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This should say 'switching', so fix it.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Signed-off-by: Heinrich Schuchardt <[email protected]>
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This consistency reads a bit nicer.
Signed-off-by: Adriano Carvalho <[email protected]>
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It was "... doing the same build ... will not trigger a rebuild".
Signed-off-by: Adriano Carvalho <[email protected]>
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Reads better.
Signed-off-by: Adriano Carvalho <[email protected]>
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It might not be clear what is meant with "to make sure the shell leaves it alone".
Signed-off-by: Adriano Carvalho <[email protected]>
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It reads a bit nicer.
Signed-off-by: Adriano Carvalho <[email protected]>
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riscv was missing from the list.
To some, the architecture's name may not be obvious from the code name.
Signed-off-by: Adriano Carvalho <[email protected]>
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Strictly speaking, "has" doesn't make sense.
"supports" seems like a better word and it probably was what the original author meant.
Signed-off-by: Adriano Carvalho <[email protected]>
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Otherwise, the two dashes are rendered as just one.
Signed-off-by: Adriano Carvalho <[email protected]>
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These are fixes to what looks like obvious typos.
Some minor improvments are also included, such as:
- Write "symbolic link" instead of symlink
- Correct capitalization for LLVM (all caps)
- Remove dead link and surrounding sentence
Signed-off-by: Adriano Carvalho <[email protected]>
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This is needed because distro_efi_read_bootflow_net will then need
dhcp_run which is not already enabled by CMD_NET.
Signed-off-by: Jan Kiszka <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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When doing compile testing build we cannot rely on having a valid file
for EFI_VAR_SEED_FILE to exist, so disable this option when doing
compile tests.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Acked-by: Heinrich Schuchardt <[email protected]>
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int is not sufficient to hold and test the return from an EFI function
call. Use efi_status_t instead so that the test can work as expected.
This issue was found by Smatch.
Fixes: 275854baeeec ("efi: Add a serial driver")
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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After the commit 7a53abb18325 ("rockchip: rk3588: Remove USB3 DRD nodes
in u-boot.dtsi") was merged for v2024.10 there is no reason to keep the
usb nodes for the Generic RK3588 board in the board u-boot.dtsi.
Move usb related nodes from board u-boot.dtsi to main board device tree.
While at it, also drop use of the usb3-phy as we only want to enable the
usb2-phy to be compatible with as many boards as possible.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The RK3576 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).
Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG0 U3 port early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The RK3588 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).
Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 ports early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Rockchip TypeC glue driver improperly present itself as a UCLASS_PHY
driver, without ever implementing the required phy_ops.
This is something that in special circumstances can lead to a NULL
pointer dereference followed by a SError crash.
Change the glue driver to use UCLASS_NOP to fix this.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Rockchip USB2PHY glue driver improperly present itself as a
UCLASS_PHY driver, without ever implementing the required phy_ops.
This is something that in special circumstances can lead to a NULL
pointer dereference followed by a SError crash.
Change the glue driver to use UCLASS_NOP to fix this.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Change to use syscon_regmap_lookup_by_phandle() helper instead of
finding the syscon udevice and making a call to syscon_get_regmap().
No runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The init ops for Rockchip COMBPHY driver is more complex than it needs
to be, e.g. declaring multiple init functions that only differ in the
error message.
Simplify the init ops based on code from the Linux mainline driver.
This change also ensure that errors returned from combphy_cfg() and
reset_deassert_bulk() is propertly propagated to the caller. No other
runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip COMBPHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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With working shared reference counting for Generic PHY ops there is no
need for the Rockchip USBDP PHY driver to keep its own status (reference
counting) handling.
Simplify the init ops now that shared reference counting is working.
This also removes the unused mode_change handling as part of the
simplication.
No runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip USBDP PHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
E.g. on a ROCK 5B following could be observed:
=> usb start
starting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb reset
resetting USB...
[...]
rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout
rockchip_udphy phy@fed90000: failed to init usbdp combophy
rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110.
Can't init PHY1
Bus usb@fc400000: probe failed, error -110
scanning usb for storage devices... 0 Storage Device(s) found
With shared reference counting this is fixed:
=> usb reset
resetting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Orange Pi 5 Ultra is another board in the Orange Pi 5 family.
Orange Pi 5 Ultra uses Rockchip RK3588,
a new generation of octa-core 64-bit ARM processor,
which includes quad-core A76 and quad-core A55.
Features tested on a Orange Pi 5 Ultra 16GB:
- SD-card boot
- eMMC boot
ROCKCHIP_TPL:
https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
BL31:
https://github.com/rockchip-linux/rkbin/tree/master/bin/rk35/rk3588_bl31_v1.48.elf
Signed-off-by: Niu Zhihong <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable the needed modules so that ROCKUSB can be used to update the
NanoPi R5S.
Signed-off-by: Diederik de Haas <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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In rockchip_sdhci_execute_tuning the variable tuning_loop_counter is
tested for being less than 0. Ensure that it is a signed type by
declaring it as s8 instead of char.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The RK806 PMIC has a bitfield for configuring the restart/reset behavior
(which I assume Rockchip calls "function") whenever the PMIC is reset
either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL
or RESETB pins.
For RK806, the following values are possible for RST_FUN:
0b00 means "Restart PMU"
0b01 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode"
0b10 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode, and simultaneously
pull down the RESETB PIN for 5mS before releasing"
0b11 means the same as for 0b10 just above.
This adds the appropriate logic in the driver to parse the new
rockchip,reset-mode DT property to pass this information. It just
happens that the values in the binding match the values to write in the
bitfield so no mapping is necessary.
For backward compatibility reasons, if the property is missing we set it
to 0b10 (i.e. BIT(7)) like before this commit was merged instead of
leaving it untouched like in the kernel driver.
Note that this does nothing useful for U-Boot at the moment as the ways
to reset the device (e.g. via `reset` command) doesn't interact with the
RK8xx PMIC and simply does a CPU reset.
Considering the upstream Linux kernel left this register untouched until
(assumed) v6.17[1], this is useful for cases in which the U-Boot
bootloader has this patch (and running with a DT with
rockchip,reset-mode property set) and running an upstream kernel before
(assumed) v6.17, or alternatively later without the property in the
kernel DT.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git/commit/?id=87b48d86b77686013f5c2a8866ed299312b671db
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The bootloader for RK3588 Tiger currently forces the PMIC reset behavior
(stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X
which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Signed-off-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: e82f642b9821384045915dc30e73df7de8424827 ]
(cherry picked from commit d9c568906be166834f4f977bc7f704176bac5b8a)
Reviewed-by: Kever Yang <[email protected]>
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The bootloader for RK3588 Jaguar currently forces the PMIC reset
behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC)
to 0b1X which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Signed-off-by: Quentin Schulz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: ee907113430aa02a8202c91bb574c385ecc28aa2 ]
(cherry picked from commit 8bd14566b75f9409de703a0d2f9a0704b71a7ebe)
Reviewed-by: Kever Yang <[email protected]>
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To make it easier to read the device tree, let's add constants for the
rockchip,reset-mode property values that are currently only applicable
to RK806 PMIC.
Signed-off-by: Quentin Schulz <[email protected]>
[dt-maintainers did not consider this part of the binding, so we're
keeping the header in the devicetree directory]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 304be20e65ca08fc2e9cb58eb939a0054d8a8b81 ]
(cherry picked from commit 0e417bfcbc385c127c7f5ea01df6289aed8325c2)
Reviewed-by: Kever Yang <[email protected]>
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The RK806 PMIC allows to configure its reset/restart behavior whenever
the PMIC is reset either programmatically or via some external pins
(e.g. PWRCTRL or RESETB).
The following modes exist:
- 0; restart PMU,
- 1; reset all power off reset registers and force state to switch to
ACTIVE mode,
- 2; same as mode 1 and also pull RESETB pin down for 5ms,
For example, some hardware may require a full restart (mode 0) in order
to function properly as regulators are shortly interrupted in this mode.
This is the case for RK3588 Jaguar and RK3588 Tiger which have a
companion microcontroller running on an independent power supply and
monitoring the PMIC power rail to know the state of the main system.
When it detects a restart, it resets its own IPs exposed to the main
system as if to simulate its own reset. Failing to perform this fake
reset of the microcontroller may break things (e.g. watchdog not
automatically disabled, buzzer still running until manually disabled,
leftover configuration from previous main system state, etc...).
Some other systems may be depending on the power rails to not be
interrupted even for a small amount of time[1].
This allows to specify how the PMIC should perform on the hardware level
and may differ between hardware designs, so a DT property seems
warranted. I unfortunately do not see how this could be made generic
enough to make it a non-vendor property.
[1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: "Rob Herring (Arm)" <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Lee Jones <[email protected]>
[ upstream commit: 404005d1083997daec7236620b9ba14bccdce449 ]
(cherry picked from commit 8ee72356e9844265334fd344bc05139d1f615c4d)
Reviewed-by: Kever Yang <[email protected]>
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Radxa E20C has a USB OTG Type-C port for Debug and Data.
Add required Kconfig options to use USB gadget features once pending
USB nodes finally lands in dts/upstream by a future sync.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for the PCIe/USB3 combo PHY used in the RK3528 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Jianwei Zheng <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Like Rockchip RK3328, RK3568 and RK3588, the RK3528 also have a single
node to represent the glue and ctrl for USB 3.0.
Use rk_ops as driver data to select correct ctrl node for RK3528 DWC3.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
the phy-rockchip-naneng-combphy driver on RK3528.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The RK3528 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).
Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 port early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Radxa E20C has two main pwm-regulators, vdd_arm and vdd_logic.
Add init-microvolt props to ensure the regulators are initialized at
the recommended power-on sequence voltage instead of at max voltage.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Drop the sdmmc node from soc u-boot.dtsi and instead use the sdmmc node
from rk3528.dtsi with v6.16-dts now merged to dts/upstream.
This cleanup has no intended functional change.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The rk3528-generic target can no longer boot after v6.16-dts was merged
into dts/upstream, and instead end up in a boot loop:
No serial driver found
resetting ...
After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528
i2c+uart aliases to board files") there is no longer an alias for
serial0 defined for the U-Boot only rk3528-generic device tree.
Add a board specific aliases node that include the missing serial0 alias
to resolve the boot issue and ensure that stdout-path = "serial0:..."
can be resolved by U-Boot.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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rk3288 is missing fdtoverlay_addr_r.
The new addresses match those used by rk3308.
Tested on Asus TinkerBoard S.
Signed-off-by: Marius Dinu <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Philipp Tomsich <[email protected]>
Cc: Kever Yang <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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GPIO0_B7 is routed to TXI of the on-board CAN transceiver. The
line has a pull-down per SoC default.
This means the CAN transceiver transmits a dominant zero
and blocks the CAN bus until Linux boots and reconfigures the pin.
Let's switch to pull-up as soon as we can (i.e. in SPL).
This cuts down the "bus is blocked" time from 10 seconds to < 1 second.
Of course, to this needs CONFIG_SPL_BOARD_INIT, so enable it
the Jaguar defconfig.
Signed-off-by: Jakob Unterwurzacher <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT
platform Rockchip RK3576, with a 6 TOPS computing power NPU and support
for up to 16GB of large memory. It supports 4K video encoding and
decoding, offers rich interfaces including dual gigabit Ethernet ports,
WiFi 6 & BT5, and various video outputs.
Features tested on a ArmSoM Sige5 v1.1:
- SD-card boot
- eMMC boot
- Ethernet
- PCIe NVMe
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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