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Add Voyager board maintainer.
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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Add documentation for Voyager board.
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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Add default configuration file for Voyager board.
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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Introduce Voyager board specific code, including
- dram info
- shared cache enabling
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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Introduce the initial device tree support for Andes Voyager board.
We will convert to OF_UPSTREAM once the patch series for kernel is merged.
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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The Voyager is Andes' first RISC-V development board.
It is built around Qilai SoC,
which includes Andes AX45MP quad-core cluster.
Introduce the Kconfig entry for the Voyager board.
Signed-off-by: Randolph Sheng-Kai Lin <[email protected]>
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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Explicitly specify the type by replacing macro with variable
to fix the possible compilation warning.
Signed-off-by: Leo Yu-Chi Liang <[email protected]>
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A new system controller driver has been created to make code modular and
improve and clean code. Update and remove functions to account for these
additional drivers.
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Enable the MPFS mailbox and system controller drivers for use with the
Icicle kit. These functions are crucial for the board setup functions
that run in the Icicle board file - mpfs_icicle.c.
Signed-off-by: Jamie Gibbons <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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This driver provides an interface to access the functions of the system
controller on the Microchip PolarFire SoC.
This driver includes functions to use the system controller to read
the device serial number.
Signed-off-by: Jamie Gibbons <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.
Signed-off-by: Jamie Gibbons <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Move ethernet mac address setting to ft_board_setup() to remove the need
for fdt set in custom boot script.
Signed-off-by: Jamie Gibbons <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Enable CONFIG_OF_BOARD_SETUP and other dependencies to allow the use of
the ft_board_setup() function to replace fdt set in boot scripts for
Microchip's MPFS Icicle kit.
Signed-off-by: Jamie Gibbons <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The commit d92fdb60677b ("binman: Add option for pointing to separate
description") added support for separating binman description to own file
not the be the part of DT for OS.
The main reason is that binman is not passing dt schema validation that's
why want to keep it separated.
Signed-off-by: Michal Simek <[email protected]>
Acked-by: Leo Yu-Chi Liang <[email protected]>
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Properties didn't match dt binding that's why should be fixed.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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OpenSBI expects mmu-type to be present in DT that's why add it. Without it
OpenSBI disable CPU node which ends up in not working boot.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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There is no reason to use OF_BOARD for MBV because reduced DT is used by
SPL and full DT is passed via u-boot.img or u-boot.itb. There is no reason
to pick up DTB from certain address.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Increase Icicle's SYS_BOOTM_LEN to 0x4000000 which is the new default
value.
Done on Conor Dooley's request.
Signed-off-by: Martin Herren <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Remove CONFIG_SYS_BOOTM_LEN from all riscv defconfigs where the new
default value is used.
Signed-off-by: Martin Herren <[email protected]>
Acked-by: Michal Simek <[email protected]> # xilinx_mbv
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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This changes the default value to the most commonly used one among
existing defconfigs.
Signed-off-by: Martin Herren <[email protected]>
Acked-by: Michal Simek <[email protected]> # xilinx_mbv
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
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For all riscv defconfigs that use the current default value.
This is done in provision of changing the default value to the most
common used value of 0x4000000.
Signed-off-by: Martin Herren <[email protected]>
Acked-by: Michal Simek <[email protected]> # xilinx_mbv
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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ifdef CONFIG_CPU only works in U-Boot proper but macro is not working when
XPL phases are used. In this case CONFIG_SPL_CPU is also defined and can be
disabled which is causing compilation error.
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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U-Boot typically can be loaded from different storage media, such as
eMMC, SD card, SPI flash, but also from non-persistent media such as USB
(via proprietary protocols loading directly into SRAM, or fastboot, DFU,
etc..), JTAG, ...
This information is usually reported by the BootROM via some proprietary
mechanism (some specific address in registers/DRAM for example). For
Rockchip, that information is stored in a register
(BROM_BOOTSOURCE_ID_ADDR).
While we already have the information about which medium was used to
load U-Boot proper from SPL (via /chosen/u-boot,spl-boot-device), this
new property represents the medium used to load U-Boot first phase
(depending on configuration, can be VPL/TPL/SPL) which absolutely may
differ from the one used to load U-Boot proper!
It would be useful to know which medium was used to load the first phase
of U-Boot, for example to check fallback mechanisms (proper loaded from
a different medium than first phase) are actually working.
For now, this only applies to Rockchip's U-Boot proper DT but could be
applied to the kernel's as well and possibly for other architectures or
vendors.
Signed-off-by: Quentin Schulz <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-snapdragon
CI: https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/pipelines/27364
Quite a few Smatch issues reported by Andrew, and the LMB allocation
fix.
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The driver specifies 154 pins so should have a maximum selector of 153
to ensure that the index into the array special_pins_names does not
overflow.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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In sa8775p_get_pin_name the limit check for the index into
msm_special_pins_data allows for more elements than exist. Add code to
ensure the array index remains in bounds.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The pointer 'label' is declared and later dereferenced without ever
having a value assigned to it. Add an assignment to this pointer so it
will be valid later when dereferenced.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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The NULL check for priv in qcom_geni_serial_poll_bit serves no useful
prupose as too much other code surrounding it relies on priv being
valid. Remove the NULL check for priv and other related code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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In msm_serial_setbrg if the call to get_clk_div_rate fails then there
will not have been an assignment to clk_div which will lead to the call
to geni_serial_baud using an uninitialised value.
Check for an error from get_clk_div_rate and return an error code if so.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Casey Connolly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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In commit 6e4675b8e5d8 ("lmb: replace the lmb_alloc() and
lmb_alloc_base() API's") an additional allocation was mistakenly
introduced resulting in ${kernel_comp_size} containing the address of a
second 64mb region rather than the actual value of KERNEL_COMP_SIZE.
Additionally, in commit b40d7b8f72f1 ("Merge patch series "lmb: use
a single API for all allocations"") merge conflict resulted in an
additional 128mb allocation for ${loadaddr} when CONFIG_FASTBOOT
is enabled, where it should actually be set to the same value as
${fastboot_addr_r} to respect size constraints (and since it doesn't
seem to interfer with any bootflows).
Fixup both of these, freeing up 192mb of memory.
Fixes: 6e4675b8e5d8 ("lmb: replace the lmb_alloc() and lmb_alloc_base() API's")
Fixes: b40d7b8f72f1 ("Merge patch series "lmb: use a single API for all allocations"")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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In qcom_snps_eusb2_phy_probe after the call to devm_clk_get if an error
is found then ret is printed but has not been assigned to by the code.
Decode the error from the pointer and assign it to ret.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
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In mci_send_cmd the pointer 'data' is optional so guard its use with a
NULL check to prevent any attempt to dereference it when not provided.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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Remove duplicate checks on status from mci_data_read and mci_data_write
which are guaranteed to be true as exiting the above do..while loop
above requires that to be so.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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If the test in the for loop is never matched then the variable 'match'
will never be assigned to. Provide an initial value so this cannot be a
problem.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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The use of the unsigned variable 'i' as a loop index leads to the test
for i being non-negative always being true. Instead declare 'i' as an
int so that the for loop will terminate as expected.
If the original for loop completes 'i' will be 1 past the end of the
array so decrement it in the subsequent error path to prevent an out of
bounds access occurring.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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The variable 'index' is declared as unsigned but used to receive the
return value of a function returning 'int'. This value is then tested
for being less than zero to detect an error condition but as index is
unsigned this can never be true. Change the variable 'index' to be an
int so that the error condition can be detected.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <[email protected]>
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In atmel_qspi_transfer(), the status register is polled with:
imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
return readl_poll_timeout(aq->regs + QSPI_SR, sr,
(sr & imr) == imr,
ATMEL_QSPI_TIMEOUT);
However, this is racy: QSPI_SR_INSTRE can be set before QSPI_SR_CSR,
and will then be cleared by the read. If that happens, the condition
"(sr & imr) == imr" can never be true, and the function times out.
This race condition is avoided in at91bootstrap by accumulating the
status bits across reads until both bits have been observed:
/* Poll INSTruction End and Chip Select Rise flags. */
imr = (QSPI_SR_INSTRE | QSPI_SR_CSR);
sr = 0;
do {
udelay(1);
sr |= qspi_readl(qspi, QSPI_SR) & imr;
} while ((--timeout) && (sr != imr));
Update U-Boot's atmel_qspi_transfer() to use the same pattern,
ensuring that both flags are observed even if they are not set
simultaneously.
Signed-off-by: Ramin Moussavi <[email protected]>
[[email protected]: remove 'sr' and fix commit msg]
Signed-off-by: Eugen Hristev <[email protected]>
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These changes are mostly smaller fixes, and some additions that were
dependent on recent DT updates: We switch the S3/V3/V3s over to
OF_UPSTREAM, the DTs were already identical anyway. While at it, Paul
sent more fixes for this SoC, I am pulling in two easy fixes that were
ready and low risk. Apart from other assorted fixes, this PR also
enables Ethernet on the new A527/T527 boards, made possible by the DT
update from the DT rebasing repository.
This passed the CI, and was boot tested on boards with Allwinner A10,
A20, A33, V40, A80, A83T, T113s3, F1C100s, H3, A64, H6, H616, A133 and
T527 SoCs.
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The JEDEC LPDDR3 spec defines mode register 0 (MR0) as being read-only,
so there is no point in trying to set its value.
Also the H616 memory controller encodes the mode register index to be
written starting from bit 8 in MRCTRL1 (for LPDDR3 and LPDDR4 chips), so
we need to OR in that number to tell the controller which MR to program.
On top of that, the mode registers between DDR3 and LPDDR3 are
completely different, so writing values crafted for DDR3 into a LPDDR3
chip is just wrong. Due to the above mentioned bugs the writes for
MR0-MR2 did not have any effect (as they were all trying to set the
read-only MR0), so the mode registers just stayed unchanged.
Looking at the LPDDR3 spec and the BSP code, let's write the proper MR
values into LPDDR3 chips, using the proper addressing mode.
Use the opportunity to document the LPDDR3 mode register bits written.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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58e9502e6 "arm: sunxi: Enable SPL/SPI boot for Olinuxino Lime2-eMMC
boards" enabled SPI boot for the eMMC variant. Olimex offers the
"s16MB" variant with SPI flash populated but without eMMC populated.
Tested on board rev L.
Signed-off-by: Eric Anderson <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Recent changes in the H6 clock code added delay() calls into the SPL clock
setup routine, which requires the timers to work. When compiling for
AArch64, we are always using the Arm Generic Timer (aka. arch timer),
which does not require further setup, hence having an empty timer_init()
routine.
However for 32-bit SoCs we use the Allwinner timers, which require some
setup routine, and hence we need timer_init() to be called before
clock_init().
Swap the order of the two calls, to be more robust when compiling the H6
clock code for AArch32 or when using the Allwinner timers for whatever
reason.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The pinecube has an ethernet connector which uses the EMAC and internal
PHY of the chip. Enable it in the config.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Paul Kocialkowski <[email protected]>
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Variables holding addresses are typically using the "long" C type in
U-Boot, to be easily compatible with both 32-bit and 64-bit builds.
The A133 DRAM driver is typically compiled for AArch64, so u64 is the
same type as unsigned long, but that breaks when compiling the DRAM
driver in AArch32 (for some experiments).
Fix the type to make the code more portable.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The first of the two Ethernet controllers in the Allwinner A527/T527 is
compatible to the MAC from the previous SoCs. Consequently the recent DT
update brought use the MAC node, using the A64 compatible string as the
fallback, which works out of the box.
Enable the sun8i-emac Ethernet driver in the defconfig for the Radxa and
the Avaota boards, so that kernels and other data can be loaded via
TFTP. Please note that only one of the Ethernet sockets will work, the
second MAC is not compatible, and needs a new U-Boot driver. The
X96QPro+ TV box unfortunately uses only this second EMAC, so Ethernet
cannot be used there at the moment.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The name of the pin function was changed last minute in the DT, from
emac0 to gmac0.
Adjust the name we use in the pinctrl driver accordingly.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
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The V3s (using co-packaged DRAM) runs at 360 MHz, which is specified in
the common platform Kconfig file. However the value for MACH_SUN8I will
be picked up instead due to ordering.
Re-order the defaults to have MACH_SUN8I_V3S before MACH_SUN8I and let
it select the correct default. Also update the LicheePi Zero Dock
defconfig to remove the value, which is now correctly selected.
Signed-off-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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There is nothing special for u-boot in the V3/V3s device-tree files,
they are just copies of the upstream ones.
Remove the copies and switch to OF_UPSTREAM for supported boards.
Signed-off-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
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The Linux pinctrl-sx150 was originally written as a GPIO driver
and fully rewritten by me as a Pinctrl driver and extended by
other contributors.
Fixup the Copyright header style and correctly report the
Copyright headers from the Linux driver.
Signed-off-by: Neil Armstrong <[email protected]>
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Fixes: 5451504256d3 ("pinctrl: gpio: sx150x: add Semtech SX150x I2C GPIO expander and pinctrl driver")
Signed-off-by: Chali Anis <[email protected]>
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This property is not documented. And the "mediatek,ipm-spi" SPI
driver doesn't check it.
Signed-off-by: Shiji Yang <[email protected]>
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