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Add support for National Semiconductor/TI LP8550/1/2/3/5/6/7
LED Backlight. Driver is based on Linux version but is
reworked and optimised for U-Boot DM framework. Currently
only register driven backlight control is supported, PWM
driver backlight control may be added later if needed.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Re-design MIPI calibration driver to fit T124.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Tegra K1 is fully compatible with existing DC and DSI implementation
using Tegra 4 data.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Tegra 124 is fully compatible with existing Tegra pincontrol
driver, but it needs a specific MIPI PAD control pinconfig.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Bind panel in Linux-style, as DSI child.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Parametrize DSI configuration by passing DC source pipe. This
should resolve possible failure if second DC is used with DSI
for some reason.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Use Linux DSI driver approach to calculate lanes for ganged mode.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Calculate packet parameters for video mode same way it is done or
command mode, by halving timings plugged into equations.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Move SOL delay calculation outside of video mode conditions.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Align U-Boot DSI ganged mode implementation with the Linux kernel's
implementation.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Switch to struct clk instead of working with plain clock id.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Switch to Linux-like approach of DSI panel binding as a DSI
controllers child node.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Mainly unification and improving of readability.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Since pinmux driver now is available for Tegra 2, these parts may
be removed from here and defined either in device tree or in
the device board files.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Switch to struct clk instead of working with plain clock id.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
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Anurag Dutta <[email protected]> says:
Previously saved environment introduce discrepancies and may lead to
incompatibilities without default settings. This series removes the saved
environment functionality on am57xx evms so that the default configuration
is always loaded
Test result: https://gist.github.com/anuragdutta731/b253ddb0a5538ab6588a3535d7bbecf7
Link: https://lore.kernel.org/r/[email protected]
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Saved environments lead to inconsistencies leading to conflicts
with the default environment that U-boot should update during
development. Remove the previously saved environment so that
the default environment is always loaded.
Signed-off-by: Anurag Dutta <[email protected]>
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Saved environments cause inconsistencies leading to conflicts
with the default environment that U-boot should update during
development. Remove the previously saved environment so that
the default environment is always loaded.
Signed-off-by: Anurag Dutta <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/24816
Please pull the SoCFPGA changes for next from u-boot-socfpga, containing
boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The
changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.
This patch set has been tested on Agilex 5 devkit with QSPI boot
(UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
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Automatically start watchdog timer for Agilex5. This
configuration is enabled by default in the Kconfig,
hence removing this configuration from Agilex5 defconfig.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add the required configuration in the U-Boot env to enable Linux QSPI
boot with UBI / UBIFS.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add board_boot_order() to retrieve the list of boot devices from
spl-boot-order property in device tree. This board_boot_order()
would be used for all Intel SOC64 devices.
Signed-off-by: Tien Fong Chee <[email protected]>
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Enable XGMAC for SoCFPGA Agilex5 devkit.
Signed-off-by: Tien Fong Chee <[email protected]>
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Use default common ARMv8 linker script instead of a separate
SoC64 linker script
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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Introduce a new symbol in the beginning of .data section in
the common ARMv8 linker script and use that as a reference
for data save and restore.
Previously, the code would rely on calculating the start of
the .data section address via data size, however, we observed
that the data size does not really reflect the SPL mapped
addresses.
In our case, the binman_sym section size was not included in
the data size, which will result in a wrong address for the
.data start section, which prevents us from properly saving
and restoring SPL data.
This approach skips the calculation for the starting address
of the .data section, and instead just defines the beginning
address of the .data section and calling the symbol as needed,
in which we think as a simpler and much more robust method.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Add SPL support for Agilex5 SoCFPGA.
Signed-off-by: Tien Fong Chee <[email protected]>
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Adding DDR driver support for Agilex5 series.
Signed-off-by: Tingting Meng <[email protected]>
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As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.
Signed-off-by: Mahesh Rao <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Adding configuration for SPL malloc pool.
Signed-off-by: Tien Fong Chee <[email protected]>
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Board ID is exported as environment variable for use to boot Linux with FIT
configuration.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Update the print info per Agilex5
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.
Signed-off-by: Tien Fong Chee <[email protected]>
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set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.
Signed-off-by: Tien Fong Chee <[email protected]>
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Enable PSCI reset driver for Agilex5 cold and warm reset
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Enable XGMAC for SoCFPGA Agilex5 devkit.
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Tien Fong Chee <[email protected]>
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These firewall configure settings are needed to disable firewall on
respective hardware component so both secure and non-secure transactions
are allowed.
Signed-off-by: Tien Fong Chee <[email protected]>
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These configuration settings are required to enable cache maintenance and
access between initiators and targets.
Signed-off-by: Tien Fong Chee <[email protected]>
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Agilex5 supports both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and Agilex5 device.
Signed-off-by: Tien Fong Chee <[email protected]>
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Status polling is used instead of using interrupt controller for Agilex5.
Disabling GICV3 in Agilex5 target, as well as disabling GICV2 enabled by
default for all SoCFPGA devices.
All the other SoCFPGA devices uses GICV2, thus enabling GICV2 in each of
the devices.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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There are 5 L4 watchdogs and one SDM triggered warm reset bit
in Agilex5 reset manager "stat" register where bit 16:20 for L4
watchdogs. Assigning value 1 to these bits in the register address
will initiate SDM to trigger warm reset.
Introducing new warm reset mask for Agilex5 to trigger warm reset
to all five L4 watchdogs.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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PLL frequency would overshoot from the original target in
synchronous mode during low VCC voltage condition.
To resolve this issue, PLL is set to run on asynchronous mode
instead of enabling synchronous mode in the clock driver.
Signed-off-by: Muhammad Hazim Izzat Zamri <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Tien Fong Chee <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Some customers prefer to minimize the use of external oscillators,
especially when using the FPGA first configuration mode.
By enabling the configuration of the HPS internal oscillator as
the boot_clk source instead of the default external oscillator,
(HPS_OSC_CLK) in non-secure boot scenarios, this allows them
to eliminate the need for an additional oscillator device and
a dedicated HPS pin, simplifying board layout and routing.
Signed-off-by: Tingting Meng <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Agilex5 retrieves its clock manager address via probing its own clock
driver model during SPL initialization.
Therefore, excluding Agilex5 from calling generic clock driver in misc
driver.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
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Initial creation of new system manager driver.
Add supports for the SOCFPGA System Manager Register block which
aggregates different peripheral function into one area.
On 64 bit ARM parts, the system manager only can be accessed during
EL3 mode, this driver model provide user the high level access
to system register and abstract user from low level access.
The base address of system manager can be retrieved
using DT framework through the System Manager driver.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Boon Khai Ng <[email protected]>
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Enable i2c3 node in Agilex5 device tree
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
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Prepare v2025.04-rc3
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Signed-off-by: Tom Rini <[email protected]>
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For eMMC v4 and newer that is smaller than 2 GiB, the JEDEC JESD84-B51
section 6.2.4 Configure partitions indicates that EXT_CSD SEC_COUNT
should not be used to determine device size, and instead device size
should be calculated from C_SIZE and C_SIZE_MULT.
This is not exactly accurate, the 2 GiB limit is not a hard line,
there are eMMC devices which are smaller than 2 GiB and still
require device size to be determined from EXT_CSD SEC_COUNT. The
hard line is instead OCR HCS bit, which indicates whether the device
is byte or sector addressed, the former applies to most devices
below 2 GiB, and the later applies mostly to devices above 2 GiB.
However, there are a couple of devices which are smaller than 2 GiB
and still set the OCR HCS bit to indicate they are sector addressed,
and therefore the size calculation for those devices should also
use EXT_CSD SEC_COUNT . Use mmc->high_capacity flag to discern the
devices instead of arbitrary 2 GiB limit. The mmc->high_capacity flag
reflects the OCR HCS bit state.
Fixes: 639b7827d1ca ("mmc: fix the condition for MMC version 4")
Signed-off-by: Marek Vasut <[email protected]>
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