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Update the spi_nor_read() function based on the config SPI_FLASH_BAR
and update the length and bank calculation by spliting the memory of
16MB size banks only when the address width is 3byte.
Fix the read issue for 4byte address width by passing the entire
length to the read function.
Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
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Add support for mapping C22 register access to C45-only PHYs.
This is mainly useful for 'mii info' command, which performs
C22 only access to determine PHY ID and link state and does
not work well with this driver so far.
Signed-off-by: Marek Vasut <[email protected]>
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Implement C22 PHY access support in addition to C45 PHY access
support which is already present. This is used for PHYs which
do not support C45 access or which are C22 only.
The C22 access can be recognized when devad is set to -1 or
0xffffffff hex, which also matches MDIO_DEVAD_NONE macro. Test
for this special devad value and if it is set this way, perform
C22 access, otherwise perform C45 access.
Based on work by LUU HOAI <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The Set Station Management Mode : Clause 45 setting of MFF bit in MPSM
register can be done in rswitch_mii_access_c45() once, instead of this
being done before each rswitch_mii_access_c45() call. Deduplicate the
bit setting into rswitch_mii_access_c45(). No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Use clrsetbits_le32() to make this complicated construct simpler.
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Update the macro indent, replace multiple spaces with tabs proper.
No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Replace enum rswitch_reg with plain #define REGISTER OFFSET macros.
The enum rswitch_reg was not referenced anywhere, so there was no
benefit of keeping it around. Include register block labels. Turn
all register offsets into lowercase hex values. No functional change.
Rename EATDQDC to EATDQDCR, GWTRC to GWTRCR, GWDCC to GWDCCR, FWPC0
to FWPC, FWPBFC to FWPBFCR, FWPBFCSDC to FWPBFCSDCR because there
are both register names which used to be part of this enum and also
macros with the same name, each used for slightly different purpose.
Make sure there is no collission.
Signed-off-by: Marek Vasut <[email protected]>
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Enable remoteproc command and APMU remoteproc driver to start Cortex-R52
cores from U-Boot command line. Code on the Cortex-R52 #0 can be started
as follows, code on other cores can be started by passing the correct ID
to 'rproc load' and 'rproc start' to select the core:
"
=> rproc init
=> rproc list
0 - Name:'rcar-apmu-cr52.0-apmu@e6170000' type:'internal memory mapped' supports: load start stop reset is_running
1 - Name:'rcar-apmu-cr52.1-apmu@e6170000' type:'internal memory mapped' supports: load start stop reset is_running
2 - Name:'rcar-apmu-cr52.2-apmu@e6170000' type:'internal memory mapped' supports: load start stop reset is_running
=> rproc load 0 0xeb200000 0x10000
Load Remote Processor 0 with data@addr=0xeb200000 65536 bytes: Success!
=> rproc start 0
"
Signed-off-by: Marek Vasut <[email protected]>
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Describe APMU controller as a remoteproc device capable of starting
the Cortex-R52 cores in Renesas R8A779G0 V4H SoC DT. The APMU IP is
in fact a power management unit capable of additional operations, but
those are not used by U-Boot so far.
Signed-off-by: Marek Vasut <[email protected]>
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Add R-Car Gen4 APMU controller remoteproc driver capable of starting
the Cortex-R52 cores in Renesas R8A779G0 V4H/V4M SoC. The APMU IP is
in fact a power management unit capable of additional operations, but
those are not used by U-Boot so far.
This requires slight adjustment to the SPL entry point code, as that
is being executed on the Cortex-R52 #0 and the Cortex-R52 #0 enters an
endless loop once it starts the rest of the SPL on Cortex-A76 core.
The endless loop now checks for content of APMU CRBARP registers and
tests whether valid VLD_BARP and BAREN_VALID bits are set, if so, the
Cortex-R52 core exits the endless loop and jumps to address started
in CRBARP[31:18] register in ARM mode, which is a trampoline code to
jump to the final entry point.
The trampoline code is in place to avoid limitation of CRBARP[31:18]
address field, which limits the core start address to memory addresses
aligned to 0x40000 or 256 kiB . The trampoline is placed at 0x40000
aligned address and jumps to the final entry point, which can be at
an address with arbitrary alignment at instruction granularity.
Signed-off-by: Marek Vasut <[email protected]>
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This DTC_FLAGS assignment is no longer necessary as all R-Car Gen2/Gen3/Gen4
platforms have been converted to OF_UPSTREAM and matching DTC_FLAGS assignment
is present in dts/upstream/src/arm64/Makefile . Drop the remnant.
Signed-off-by: Marek Vasut <[email protected]>
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Align R-Car Gen2/Gen3/Gen4 configuration header file to look
basically the same way across these three SoC generations.
There are subtle difference between the remaining bits in
those files across SoC generations, but the common bits are
now aligned. There is not much left in those headers either,
most of the configuration is now converted to Kconfig.
Specifically for R-Car Gen3, GIC registers have been moved
to architecture specific header file rcar-gen3-base.h , the
rest of the changes here are comment changes and indentation
changes.
Signed-off-by: Marek Vasut <[email protected]>
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Add support for building U-Boot SPL for Renesas R-Car Gen4 R8A779G0 V4H SoC.
The SPL initializes the DBSC5 DRAM controller, RT-VRAM and loads and starts
U-Boot proper on the Cortex-A76 core.
The SoC BootROM can not boot the CA76 core directly, instead the SPL starts
on the CR52 core which immediately brings up the CA76 core, which in turn
starts executing the actual SPL. This is achieved by placing a tiny bit of
precompiled Aarch32 code at the very beginning of the SPL. The code consists
of some 32 instructions, uses APMU to configure CA76 start address to offset
0x80 Bytes from start of the SPL, and uses APMU to start the CA76 core. The
code parts the CR52 core in an endless loop once the CA76 core got started.
The 32 instructions are completely arbitrary number, so is the offset 0x80
Bytes from start of SPL, because 0x80 = 128 decimal and 128 / 4 bytes per
instruction is 32 instructions. The 32 instructions turned out to be enough
to started the CA76 and 0x80 is nicely aligned.
Once the SPL completes hardware initialization, the SPL loads U-Boot proper.
The u-boot.itb proper fitImage contains 64bit build on u-boot-nodtb.bin and
a DT for R8A779G0 V4H White Hawk board and is generated by binman. The
u-boot.itb is loaded from SPI NOR offset 0x80000.
In order to install this setup on an existing R8A779G0 V4H White Hawk board,
build using r8a779g0_whitehawk_defconfig, generate SPI NOR image flash.bin
and write flash.bin to SPI NOR offset 0x0 . Finally, configure board MD pin
switches according to the R8A779G0 V4H White Hawk board documentation for
40 MHz SPI NOR boot using DMA and restart the board.
Signed-off-by: Marek Vasut <[email protected]>
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In case U-Boot runs in EL3, which is the highest privilege level on ARM64,
there can be no firmware running that would restrict access to the bottom
128 MiB of DRAM. In fact, it is likely that U-Boot would have to load that
firmware into those bottom 128 MiB of DRAM and start that firmware.
Make those bottom 128 MiB of DRAM available in case U-Boot runs in EL3 to
allow loading the firmware to that area.
Signed-off-by: Marek Vasut <[email protected]>
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Split common board code for R-Car Gen3 and Gen4 into separate files.
The R-Car Gen3 board code contains fixups specific to TFA which are
no longer required on R-Car Gen4, keep those fixups in its own file
so they would not interfere with Gen4.
Signed-off-by: Marek Vasut <[email protected]>
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All R-Car Gen4 board files are copies of one another at this point.
Deduplicate them into single board/renesas/rcar-common/gen4-common.c
and remove all the duplicates. The one exception is R-Car V3U Falcon
board, which enables RWDT reset in board_init(), conditionally build
RWDT enablement in board_init() in the new common code for V3U.
Signed-off-by: Marek Vasut <[email protected]>
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Make the R-Car V3U stub PSCI implementation available on 64bit R-Car SoCs.
This implementation is useful during early board bring up, where it can
supplant missing fully-featured PSCI implementation. Note that this PSCI
implementation is very basic and offers only SoC reset functionality. It
is unable to enable or disable secondary CPU cores nor does it offer any
suspend/resume functionality.
Signed-off-by: Marek Vasut <[email protected]>
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Describe DBSC5 DRAM controller and RT-VRAM configuration interface
as two new DT nodes in R-Car Gen4 R8A779G0 U-Boot DT extras file.
This node is used by the U-Boot SPL for R8A779G0 SoC, where the
DBSC5 and RT-VRAM drivers bind to these nodes and bring up the
DRAM controller and RT-VRAM settings respectively, so U-Boot
proper can be loaded into DRAM and started on Cortex A76 core.
Signed-off-by: Marek Vasut <[email protected]>
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Add Renesas R-Car Gen4 DBSC5 DRAM controller driver. This driver is currently
capable of bringing LPDDR5 DRAM on Renesas R-Car V4H Whitehawk board. Further
boards can be supported by supplying board specific DRAM configuration data
via dbsc5_get_board_data(). Support for R-Car V4M is not implemented, however
the driver is already mostly prepared to support this SoC.
Signed-off-by: Marek Vasut <[email protected]>
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Use the IS_ENABLED() macro to reduce amount of #ifdef use in the driver
and improve code coverage. With IS_ENABLED() macro, the code is compiled
and then optimized out, which prevents bitrot.
In case no PFC table matches the SoC in use, do not probe the driver
and instead exit with -ENODEV. This should never happen under normal
conditions, because this would mean the driver DT compatible string
match happened, but the list in probe() cannot match the model listed
in match data associated with the compatible string on which the match
did happen.
Signed-off-by: Marek Vasut <[email protected]>
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Mikhail Kshevetskiy <[email protected]> says:
Legacy TCP stack is bad. Here are some of the known issues:
* tcp packet from other connection can break a current one
* tcp send sequence always starts from zero
* bad tcp options processing
* strange assumptions on packet size for selective acknowledge
* tcp interface assumes one of the two scenarios:
- data downloading from remote host to a board
- request-response exchange with a small packets
so it's not possible to upload large amount of data from the
board to remote host.
* wget test generate bad tcp stream, test should fail but it passes instead
This series of patches fixes all of the above issues.
The benefits:
* A lot of bug was fixed
* Better and more reliable TCP state machine
* Tcp clients becomes smaller/simpler
* Data uploading was fixed (now it's possible to transmit a huge amount of
data from the board to remote host)
Modification was verified with
* firmware downloading via u-boot wget command
* fastboot over tcp
* netcat linux client using test netcat implementation (not included
to this patch series)
* Firefox/Chrome/Edge using test web-server implementation (not included
to this patch series)
[trini: snip]
WARNING: The v16 patch series does NOT fix lib/efi_selftest/efi_selftest_http.c
issue. It looks like the efi_selftest_http test is wrong by itself. The
following issues were detected during efi_selftest_http test study:
* The test should fail with HTTP status code 404 because:
* nowday most web-servers requires the presence of "HOST:" request header
* wget does not support sending "HOST:" request header
* web-server of "http://example.com/" site does NOT provide "default server"
configuration, so it answer 404 on any request without "HOST:" header.
* The test states that:
* test send HTTP HEAD request to a server,
* then test send HTTP GET request to a server,
* reads the actual bytes sent by the server and compare it with
the value from "Contents-Length:" responce header of the HEAD request
But actually it
* does not send HTTP HEAD request, only a single HTTP GET request
is performed
* the test reads the responce twice from the same request. It looks
very suspictiuos
Link: https://lore.kernel.org/r/[email protected]
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fix include ordering to follow
https://docs.u-boot.org/en/latest/develop/codingstyle.html#include-files
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Some driver implements it's own network packet pool, so PKTBUFSRX is zero.
This results in zero-size TCP receive window, so data transfer doesn't
work. Avoid it by setting a reasonable fallback value.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This patch:
* remove useless code,
* use a special function for pretty printing of tcp flags,
* simplify the code
The behavior should not be changed.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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server
According to HTTP/1.0 standard the HTTP reply consist of
* Status Line + CRLF
* Zero or more Response Header Fields (each ended with CRLF)
* CRLF on new line (Response Header Fields end marker)
* Optional Entity Body.
Thus in response headers we state:
Content-Length = 30
but actual transferred file data is:
"\r\n<html><body>Hi</body></html>\r\n".
This is 32 bytes of data.
So we get and check for correctness 32 bytes of data, but
* The response we are used is incorrect, real server will
set Content-Length to 32.
* default_wget_info->hdr_cont_len will be set to wrong
value 30 (used for efi http booting).
Fix an issue by:
* replace bogus response with an actual response from the HTTP server
* format response to show HTTP response structure
* recalculate md5sum as transferred file data has been changed.
The server response was captured with the commands
echo -ne "<html><body>Hi</body></html>\n" > ~/public_html/test.html
echo -ne "GET /~${USER}/test.html HTTP/1.0\r\n\r\n" | netcat localhost 80 >reply.txt
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
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Changes:
* update to new tcp stack
* fix zero values for ISS and IRS issue (see RFC 9293)
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Changes:
* Fix initial send sequence always zero issue
* Use state machine close to RFC 9293. This should make TCP
transfers more reliable (now we can upload a huge array
of data from the board to external server)
* Improve TCP framework a lot. This should make tcp client
code much more simple.
* rewrite wget with new tcp stack
* rewrite fastboot_tcp with new tcp stack
It's quite hard to fix the initial send sequence (ISS) issue
with the separate patch. A naive attempt to fix an issue
inside the tcp_set_tcp_header() function will break tcp packet
retransmit logic in wget and other clients.
Example:
Wget stores tcp_seq_num value before tcp_set_tcp_header() will
be called and (on failure) retransmit the packet with the stored
tcp_seq_num value. Thus:
* the same ISS must allways be used (current case)
* or tcp clients needs to generate a proper ISS when
required.
A proper ISS fix will require a big redesing comparable with
a this one.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Use the names from RFC 9293
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Changes:
* Avoid use net_server_ip in tcp code, use tcp_stream data instead
* Ignore packets from other connections if connection already created.
This prevents us from connection break caused by other tcp stream.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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no functional changes
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Current code assume that all (except last) packets are of the same size.
This is definitely wrong. Replace SACK code with a new one, that does
not rely on this assumption. Also this code uses less memory.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Current TCP code may miss an option if TCP_O_NOP option was used before
it for proper aligning.
Signed-off-by: Mikhail Kshevetskiy <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Simon Glass <[email protected]> says:
This includes various patches towards implementing the VBE abrec
bootmeth in U-Boot. It mostly focuses on SPL tweaks and adjusting what
fatures are available in VPL.
Link: https://lore.kernel.org/r/[email protected]
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Add an entry for crc8, with watchdog handling.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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VBE uses a crc8 checksum to verify that the nvdata is valid, so make
sure it is available if VBE is enabled.
Signed-off-by: Simon Glass <[email protected]>
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Provide options to enable the CRC8 feature in TPL and VPL builds.
Signed-off-by: Simon Glass <[email protected]>
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With VBE we want to use FIT in all phases of the boot. Add Kconfig
options to support this.
Disable the options for sandbox_vpl for now.
Signed-off-by: Simon Glass <[email protected]>
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Add Kconfig symbols and update the Makefile rules so that decompression
can be used in TPL and VPL
Signed-off-by: Simon Glass <[email protected]>
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Add debugging of image-loading progress. Fix a stale comment in the
function comment while we are here.
Signed-off-by: Simon Glass <[email protected]>
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The variable 'ret' is defined twice, which is not intended. This may
have been a local merge error.
Signed-off-by: Simon Glass <[email protected]>
Fixes: 2eefeb6d893 ("spl: Report a loader failure")
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U-Boot uses ulong for addresses. It is confusing to use uintptr_t in a
few places, since it makes people wonder if the types are compatible.
Change the few occurences in SPL to use ulong
Signed-off-by: Simon Glass <[email protected]>
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The current check looks only at SPL, but TPL or VPL might have a
different setting. Update the condition.
Signed-off-by: Simon Glass <[email protected]>
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The current check looks only at SPL, but TPL or VPL might have a
different setting. Update the condition.
Signed-off-by: Simon Glass <[email protected]>
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If a loader returns an error code it is silently ignored. Show a message
to at least provide some feedback to the user.
Signed-off-by: Simon Glass <[email protected]>
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Add a size limit for VPL, to match those for SPL and TPL
Signed-off-by: Simon Glass <[email protected]>
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The VPL phase may want to use the smaller malloc() implementation, so
add an option for this.
Signed-off-by: Simon Glass <[email protected]>
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Show a bit more information when malloc() space is exhausted and
debugging is enabled.
Signed-off-by: Simon Glass <[email protected]>
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Some code has crept in which ignores this parameter. Fix this and add a
little debugging.
Signed-off-by: Simon Glass <[email protected]>
Fixes: b1307f884a9 ("fit: Support compression for non-kernel components (e.g. FDT)")
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The name of the bootdev device is not that important, particular in SPL.
Save a little code space by using a simpler name.
Signed-off-by: Simon Glass <[email protected]>
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When the best-match feature fails to find something, use the provided
config name as a fallback. The allows SPL to select a suitable config
when best-match is enabled.
Signed-off-by: Simon Glass <[email protected]>
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