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Conflicts:
arch/arm/cpu/armv7/config.mk
board/ti/am43xx/mux.c
include/configs/am43xx_evm.h
Signed-off-by: Tom Rini <[email protected]>
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Add bcm281xx architecture support code including a clock framework and
chip reset. Define register block base addresses for the bcm281xx
architecture and create an empty gpio header file required when
CONFIG_CMD_GPIO is set.
Signed-off-by: Darwin Rambo <[email protected]>
Reviewed-by: Steve Rae <[email protected]>
Reviewed-by: Tim Kryger <[email protected]>
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The Kona architecture is present on a number of Broadcom mobile SoCs
including the bcm281xx family of chips.
Signed-off-by: Darwin Rambo <[email protected]>
Reviewed-by: Steve Rae <[email protected]>
Reviewed-by: Tim Kryger <[email protected]>
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Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.
Signed-off-by: Dave Gerlach <[email protected]>
[trini: Rework patch against mainline]
Signed-off-by: Tom Rini <[email protected]>
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Adds support for Bernecker & Rainer Industrieelektronik GmbH KWB
Motherboard, using TI's AM3352 SoC.
Most of code is derived from TI's AM335x_EVM
Signed-off-by: Hannes Petermaier <[email protected]>
Cc: [email protected]
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This patch add support for the Silica Pengwyn board [1]
The board is based on a TI AM3354 CPU [2]
All jumpers removed it will boot from the SDcard, the console is on
UART1 accessible via the FDTI -> USB. The on board NAND flash is
supported and can act as boot medium, depending on jumper settings.
USB Host, USB Device and Ethernet are also provided but untested.
[1]
http://www.silica.com/product/silica-pengwyn-board.html
[2]
http://www.ti.com/product/am3354
Signed-off-by: Lothar Felten <[email protected]>
[trini: Move CONFIG_BOARD_LATE_INIT into am335x_evm.h, drop unused
spi0_pin_mux from Pengwyn support]
Signed-off-by: Tom Rini <[email protected]>
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Conflicts:
Makefile
drivers/net/npe/Makefile
These two conflicts arise from commit 0b2d3f20
("ARM: NET: Remove the IXP NPE ethernet driver") and are
resolved by deleting the drivers/net/npe/Makefile file
and removing the CONFIG_IXP4XX_NPE line from Makefile.
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Having CONFIG_SYS_I2C_BASE requires DW I2C driver to explicitly include
<arch/hardware.h> which other platforms may not have at all.
It's always good to have a driver platform-independent.
Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Heiko Schocher <[email protected]>
Cc: Stefan Roese <[email protected]>
Cc: Vipin Kumar <[email protected]>
Cc: Armando Visconti <[email protected]>
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- When CONFIG_DISPLAY_CPUINFO is not enabled,
print_cpuinfo() should be defined as an empty function
in a header, include/common.h
- Remove #ifdef CONFIG_DISPLAY_CPUINFO .. #endif
from caller, common/board_f.c and arch/arm/lib/board.c
- Remove redundant prototypes in arch/arm/lib/board.c,
arch/arm/include/asm/arch-am33x/sys_proto.h and
board/nokia/rx51/rx51.h, keeping the one in include/common.h
- Add #ifdef CONFIG_DISPLAY_CPUINFO to the func definition
where it is missing
Signed-off-by: Masahiro Yamada <[email protected]>
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Add the SATA boot support for OMAP5 and dra7xx.
Renamed the omap_sata_init to the common init_sata(int dev)
for commonality in with sata stack.
Added the ROM boot device ID for SATA.
Signed-off-by: Dan Murphy <[email protected]>
Reviewed-by: Roger Quadros <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Andy Ng <[email protected]>
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SPL is using ps7_init.c/h files which are generated
from design tools which have to be copied to
boards/xilinx/zynq folder before compilation.
BSS section is moved to SDRAM because fat support
requires more space than SRAM size.
Added:
- MMC and QSPI support
- Boot OS directly from SPL
- Enable SPL command
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Remove hard coded clock divider setting and use the Zynq clock framework
to dynamically calculate appropriate dividers at run time.
Signed-off-by: Soren Brinkmann <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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The GEM driver should not need to know about Zynq specific details of
RCLK related registers and bitfields in the SLCR. Move those details to
the slcr driver.
Signed-off-by: Soren Brinkmann <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Signed-off-by: Soren Brinkmann <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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Define both serial uarts in the driver and return
default uart based on board configuration.
- Move baseaddresses to hardware.h
- Define default baudrate and clock values
Signed-off-by: Michal Simek <[email protected]>
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These numbers will be reused by SPL.
Signed-off-by: Michal Simek <[email protected]>
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Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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The dual lite and solo variant have only 4 SPI controller.
respect this in the MXC_SPI_BASE_ADRESSES macro
Signed-off-by: Markus Niebel <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Provide define for the SCLK_CTL field of the config reg of ECSPI.
While at it, oder the defines to improve readability and make
adding more defines easier.
Signed-off-by: Markus Niebel <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>
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Typo: The correct value is 1 not 2.
Signed-off-by: Stephen Warren <[email protected]>
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Add L2 cache support and enable it by default.
Configure the L2 cache in the same way as done by FSL kernel:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Dirk Behme <[email protected]>
Acked-by: Stefano Babic <[email protected]>
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Currently when we boot a mx6dual U-boot reports that it is a mx6quad.
Report it as MX6D instead:
CPU: Freescale i.MX6D rev1.2 at 792 MHz
Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Stefano babic <[email protected]>
Acked-by: Otavio Salvador <[email protected]>
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Instead of duplicating the CPU definitions at mx5 and mx6 sys_proto.h header
files, introduce a common header to centralize such definitions.
Signed-off-by: Fabio Estevam <[email protected]>
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This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.
This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144sec
Signed-off-by: Rajeshwari S Shinde <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
Signed-off-by: Pantelis Antoniou <[email protected]>
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This patch adds s5p_cpu_rev.
Signed-off-by: Piotr Wilczek <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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This patch enables to read cpu revision on Exynos CPU.
Signed-off-by: Piotr Wilczek <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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The architecture is unmaintained and dead, remove it.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Michael Schwingen <[email protected]>
Cc: Tom Rini <[email protected]>
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The value of PERIPH_ID_COUNT was wrong, and unnecessary.
Signed-off-by: Minkyu Kang <[email protected]>
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Signed-off-by: Minkyu Kang <[email protected]>
Acked-by: Rajehswari Shinde <[email protected]>
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These headers define the Tegra124 hardware. Add them to the usual
place.
Add Tegra124 chip ID/SKU ID definitions to common headers.
There's no real HW change on Tegra124 for 90% of the toys, so it might
make sense for a future patch to unify some of the content of these
files in a common location.
Signed-off-by: Tom Warren <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Pass just the partition ID to power_partition(), rather than also passing
the partition's status register mask too. This makes it simpler to get
call-sites correct, since they don't need to pass two different values
that define the same thing and must match.
Consequently, we can remove the mask definitions from pmc.h.
Suggested-by: Thierry Reding <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Use a named constant for the PLL lock bit in enable_cpu_clocks().
Construct the complete value of pmc_pwrgate_toggle, rather than doing a
read-modify-write; the register is simple enough and doesn't need to
maintain state between operations.
Signed-off-by: Stephen Warren <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Based on the Tegra TRM, the system clock (which is the AVP clock) can
run up to 275MHz. On power on, the default sytem clock source is set to
PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to
408MHz which is beyond system clock's upper limit.
The fix is to set the system clock to CLK_M before initializing PLLP,
and then switch back to PLLP_OUT4, which has an appropriate divider
configured, after PLLP has been configured
Implement this logic in new function tegra30_set_up_pllp(),
which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP
clock switching. Remove the duplicate PLLP setup from pllx_set_rate()
and adjust_pllp_out_freqs().
Signed-off-by: Jimmy Zhang <[email protected]>
[swarren, significantly refactored the change]
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Tegra114 and later's PMC module removes the pwrgate_timer_on register
and replaces it with a clamp_status register. Adjust pmc.h to reflect
this, and update any code affected by the change.
The cpu.c change in this patch was extracted from a much larger patch
by Jimmy Zhang. The pmc.h change was written from scratch, but inspired
by related changes made by Tom Warren.
There could well be other differences in the PMC register set for chips
after Tegra20/30. However, they don't affect the code in U-Boot at
present, so I haven't attempted an exhaustive update of pmc.h.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Some clock sources have 3-bit muxes in bits 31:29. Implement core
support for this mux field.
Signed-off-by: Tom Warren <[email protected]>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Since all code that sets or interprets MASK_BITS_* now uses the enums
to define/compare the values, there is no need for MASK_BITS_* to have
a specific integer value. In fact, having a specific integer value may
encourage people to hard-code those values, or interpret the values in
incorrect ways.
As such, remove the logic that assigns a specific value to the enum
values in order to make it completely clear that it's just an enum, not
something that directly represents some integer value.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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OUT_CLK_SOURCE_ are currently named after the number of bits the mask
they represent includes. However, bit count is not the only possible
variable; bit position may also vary. Rename OUT_CLK_SOURCE_ to
OUT_CLK_SOURCE_31_30_ and OUT_CLK_SOURCE4_ to OUT_CLK_SOURCE_31_28 to
more completely describe exactly what they represent, without having to
go look up the definitions.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The only place where the MASK_BITS_* values are used is in
adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28,
new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK,
i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually
implemented.
Note that no Tegra clock register actually uses all of bits 31:28 as
the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
those cases, nothing is stored in the bits above the mux field, so it's
safe to pretend that the mux field extends all the way to the end of the
register. As such, the U-Boot clock driver is currently a bit lazy, and
doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
them all together and pretends they're all 31:28. This patch doesn't
cause this issue; it was pre-existing. Hopefully, future patches will
clean this up.
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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The enum used to define the set of register bits used to represent a
clock's input mux, MUX_BITS_*, is defined separately for each SoC at
present. Move this definition to a common location to ease fixing up
some issues with the definition, and the code that uses it.
Signed-off-by: Tom Warren <[email protected]>
[swarren, extracted from a larger patch by Tom]
Signed-off-by: Stephen Warren <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Tom Warren <[email protected]>
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Old s5p gpio coding method was not clean and was not working properly
for all parts and banks. New method is clean and easy to extend.
Gpio coding mask:
0x000000ff - pin number
0x00ffff00 - bank offset
0xff000000 - part number
Signed-off-by: Przemyslaw Marczak <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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